From 1bc5c4fe45ccdef68ac4eb213d3f990a87767d92 Mon Sep 17 00:00:00 2001 From: Christophe Priouzeau Date: Mon, 6 Jun 2022 15:12:44 +0200 Subject: [PATCH] CMSIS: add support for stm32mp13 Signed-off-by: Christophe Priouzeau Change-Id: I999ec41342ad6a41e0541b6a1bd1863255afff9d --- ...-STMicro-add-support-of-stm32mp15xxx.patch | 149439 ------------ .../cmsis-svd/cmsis-svd/STM32MP13xx.svd | 184041 +++++++++++++++ .../cmsis-svd/cmsis-svd/STM32MP15xxx.svd | 149424 ++++++++++++ recipes-devtools/cmsis-svd/cmsis-svd_git.bb | 8 +- .../cmsis-svd/cmsis-svd_git.bbappend | 7 +- 5 files changed, 333474 insertions(+), 149445 deletions(-) delete mode 100644 recipes-devtools/cmsis-svd/cmsis-svd/0001-data-STMicro-add-support-of-stm32mp15xxx.patch create mode 100644 recipes-devtools/cmsis-svd/cmsis-svd/STM32MP13xx.svd create mode 100644 recipes-devtools/cmsis-svd/cmsis-svd/STM32MP15xxx.svd diff --git a/recipes-devtools/cmsis-svd/cmsis-svd/0001-data-STMicro-add-support-of-stm32mp15xxx.patch b/recipes-devtools/cmsis-svd/cmsis-svd/0001-data-STMicro-add-support-of-stm32mp15xxx.patch deleted file mode 100644 index e83f65f..0000000 --- a/recipes-devtools/cmsis-svd/cmsis-svd/0001-data-STMicro-add-support-of-stm32mp15xxx.patch +++ /dev/null @@ -1,149439 +0,0 @@ -From 3d6372b1499669919e857e9e6f73915ce6193a7d Mon Sep 17 00:00:00 2001 -From: Jean-Philippe ROMAIN -Date: Wed, 27 Nov 2019 11:52:12 +0100 -Subject: [PATCH] data: STMicro: add support of stm32mp15xxx - - -diff --git a/data/STMicro/STM32MP15xxx.svd b/data/STMicro/STM32MP15xxx.svd -new file mode 100644 -index 0000000..1fe06e9 ---- /dev/null -+++ b/data/STMicro/STM32MP15xxx.svd -@@ -0,0 +1,149424 @@ -+ -+ -+ STM32MP15xxx -+ 1.2 -+ STM32MP15xxx -+ -+ -+ 8 -+ -+ 32 -+ -+ 0x20 -+ 0x0 -+ 0xFFFFFFFF -+ -+ -+ ADC2 -+ ADC2 -+ ADC2 -+ 0x48003100 -+ -+ 0x0 -+ 0x100 -+ registers -+ -+ -+ -+ ADC_ISR -+ ADC_ISR -+ ADC interrupt and status register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADRDY -+ ADRDY -+ 0 -+ 1 -+ -+ -+ EOSMP -+ EOSMP -+ 1 -+ 1 -+ -+ -+ EOC -+ EOC -+ 2 -+ 1 -+ -+ -+ EOS -+ EOS -+ 3 -+ 1 -+ -+ -+ OVR -+ OVR -+ 4 -+ 1 -+ -+ -+ JEOC -+ JEOC -+ 5 -+ 1 -+ -+ -+ JEOS -+ JEOS -+ 6 -+ 1 -+ -+ -+ AWD1 -+ AWD1 -+ 7 -+ 1 -+ -+ -+ AWD2 -+ AWD2 -+ 8 -+ 1 -+ -+ -+ AWD3 -+ AWD3 -+ 9 -+ 1 -+ -+ -+ JQOVF -+ JQOVF -+ 10 -+ 1 -+ -+ -+ -+ -+ ADC_IER -+ ADC_IER -+ ADC interrupt enable register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADRDYIE -+ ADRDYIE -+ 0 -+ 1 -+ -+ -+ EOSMPIE -+ EOSMPIE -+ 1 -+ 1 -+ -+ -+ EOCIE -+ EOCIE -+ 2 -+ 1 -+ -+ -+ EOSIE -+ EOSIE -+ 3 -+ 1 -+ -+ -+ OVRIE -+ OVRIE -+ 4 -+ 1 -+ -+ -+ JEOCIE -+ JEOCIE -+ 5 -+ 1 -+ -+ -+ JEOSIE -+ JEOSIE -+ 6 -+ 1 -+ -+ -+ AWD1IE -+ AWD1IE -+ 7 -+ 1 -+ -+ -+ AWD2IE -+ AWD2IE -+ 8 -+ 1 -+ -+ -+ AWD3IE -+ AWD3IE -+ 9 -+ 1 -+ -+ -+ JQOVFIE -+ JQOVFIE -+ 10 -+ 1 -+ -+ -+ -+ -+ ADC_CR -+ ADC_CR -+ ADC control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x20000000 -+ -+ -+ ADEN -+ ADEN -+ 0 -+ 1 -+ -+ -+ ADDIS -+ ADDIS -+ 1 -+ 1 -+ -+ -+ ADSTART -+ ADSTART -+ 2 -+ 1 -+ -+ -+ JADSTART -+ JADSTART -+ 3 -+ 1 -+ -+ -+ ADSTP -+ ADSTP -+ 4 -+ 1 -+ -+ -+ JADSTP -+ JADSTP -+ 5 -+ 1 -+ -+ -+ BOOST -+ BOOST -+ 8 -+ 1 -+ -+ -+ ADCALLIN -+ ADCALLIN -+ 16 -+ 1 -+ -+ -+ LINCALRDYW1 -+ LINCALRDYW1 -+ 22 -+ 1 -+ -+ -+ LINCALRDYW2 -+ LINCALRDYW2 -+ 23 -+ 1 -+ -+ -+ LINCALRDYW3 -+ LINCALRDYW3 -+ 24 -+ 1 -+ -+ -+ LINCALRDYW4 -+ LINCALRDYW4 -+ 25 -+ 1 -+ -+ -+ LINCALRDYW5 -+ LINCALRDYW5 -+ 26 -+ 1 -+ -+ -+ LINCALRDYW6 -+ LINCALRDYW6 -+ 27 -+ 1 -+ -+ -+ ADVREGEN -+ ADVREGEN -+ 28 -+ 1 -+ -+ -+ DEEPPWD -+ DEEPPWD -+ 29 -+ 1 -+ -+ -+ ADCALDIF -+ ADCALDIF -+ 30 -+ 1 -+ -+ -+ ADCAL -+ ADCAL -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_CFGR -+ ADC_CFGR -+ ADC configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x80000000 -+ -+ -+ DMNGT -+ DMNGT -+ 0 -+ 2 -+ -+ -+ RES -+ RES -+ 2 -+ 3 -+ -+ -+ EXTSEL -+ EXTSEL -+ 5 -+ 5 -+ -+ -+ EXTEN -+ EXTEN -+ 10 -+ 2 -+ -+ -+ OVRMOD -+ OVRMOD -+ 12 -+ 1 -+ -+ -+ CONT -+ CONT -+ 13 -+ 1 -+ -+ -+ AUTDLY -+ AUTDLY -+ 14 -+ 1 -+ -+ -+ DISCEN -+ DISCEN -+ 16 -+ 1 -+ -+ -+ DISCNUM -+ DISCNUM -+ 17 -+ 3 -+ -+ -+ JDISCEN -+ JDISCEN -+ 20 -+ 1 -+ -+ -+ JQM -+ JQM -+ 21 -+ 1 -+ -+ -+ AWD1SGL -+ AWD1SGL -+ 22 -+ 1 -+ -+ -+ AWD1EN -+ AWD1EN -+ 23 -+ 1 -+ -+ -+ JAWD1EN -+ JAWD1EN -+ 24 -+ 1 -+ -+ -+ JAUTO -+ JAUTO -+ 25 -+ 1 -+ -+ -+ AWD1CH -+ AWD1CH -+ 26 -+ 5 -+ -+ -+ JQDIS -+ JQDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_CFGR2 -+ ADC_CFGR2 -+ ADC configuration register 2 -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ROVSE -+ ROVSE -+ 0 -+ 1 -+ -+ -+ JOVSE -+ JOVSE -+ 1 -+ 1 -+ -+ -+ OVSS -+ OVSS -+ 5 -+ 4 -+ -+ -+ TROVS -+ TROVS -+ 9 -+ 1 -+ -+ -+ ROVSM -+ ROVSM -+ 10 -+ 1 -+ -+ -+ RSHIFT1 -+ RSHIFT1 -+ 11 -+ 1 -+ -+ -+ RSHIFT2 -+ RSHIFT2 -+ 12 -+ 1 -+ -+ -+ RSHIFT3 -+ RSHIFT3 -+ 13 -+ 1 -+ -+ -+ RSHIFT4 -+ RSHIFT4 -+ 14 -+ 1 -+ -+ -+ OSVR -+ OSVR -+ 16 -+ 10 -+ -+ -+ LSHIFT -+ LSHIFT -+ 28 -+ 4 -+ -+ -+ -+ -+ ADC_SMPR1 -+ ADC_SMPR1 -+ ADC sample time register 1 -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMP0 -+ SMP0 -+ 0 -+ 3 -+ -+ -+ SMP1 -+ SMP1 -+ 3 -+ 3 -+ -+ -+ SMP2 -+ SMP2 -+ 6 -+ 3 -+ -+ -+ SMP3 -+ SMP3 -+ 9 -+ 3 -+ -+ -+ SMP4 -+ SMP4 -+ 12 -+ 3 -+ -+ -+ SMP5 -+ SMP5 -+ 15 -+ 3 -+ -+ -+ SMP6 -+ SMP6 -+ 18 -+ 3 -+ -+ -+ SMP7 -+ SMP7 -+ 21 -+ 3 -+ -+ -+ SMP8 -+ SMP8 -+ 24 -+ 3 -+ -+ -+ SMP9 -+ SMP9 -+ 27 -+ 3 -+ -+ -+ -+ -+ ADC_SMPR2 -+ ADC_SMPR2 -+ ADC sample time register 2 -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMP10 -+ SMP10 -+ 0 -+ 3 -+ -+ -+ SMP11 -+ SMP11 -+ 3 -+ 3 -+ -+ -+ SMP12 -+ SMP12 -+ 6 -+ 3 -+ -+ -+ SMP13 -+ SMP13 -+ 9 -+ 3 -+ -+ -+ SMP14 -+ SMP14 -+ 12 -+ 3 -+ -+ -+ SMP15 -+ SMP15 -+ 15 -+ 3 -+ -+ -+ SMP16 -+ SMP16 -+ 18 -+ 3 -+ -+ -+ SMP17 -+ SMP17 -+ 21 -+ 3 -+ -+ -+ SMP18 -+ SMP18 -+ 24 -+ 3 -+ -+ -+ SMP19 -+ SMP19 -+ 27 -+ 3 -+ -+ -+ -+ -+ ADC_PCSEL -+ ADC_PCSEL -+ ADC channel preselection register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PCSEL0 -+ PCSEL0 -+ 0 -+ 1 -+ -+ -+ PCSEL1 -+ PCSEL1 -+ 1 -+ 1 -+ -+ -+ PCSEL2 -+ PCSEL2 -+ 2 -+ 1 -+ -+ -+ PCSEL3 -+ PCSEL3 -+ 3 -+ 1 -+ -+ -+ PCSEL4 -+ PCSEL4 -+ 4 -+ 1 -+ -+ -+ PCSEL5 -+ PCSEL5 -+ 5 -+ 1 -+ -+ -+ PCSEL6 -+ PCSEL6 -+ 6 -+ 1 -+ -+ -+ PCSEL7 -+ PCSEL7 -+ 7 -+ 1 -+ -+ -+ PCSEL8 -+ PCSEL8 -+ 8 -+ 1 -+ -+ -+ PCSEL9 -+ PCSEL9 -+ 9 -+ 1 -+ -+ -+ PCSEL10 -+ PCSEL10 -+ 10 -+ 1 -+ -+ -+ PCSEL11 -+ PCSEL11 -+ 11 -+ 1 -+ -+ -+ PCSEL12 -+ PCSEL12 -+ 12 -+ 1 -+ -+ -+ PCSEL13 -+ PCSEL13 -+ 13 -+ 1 -+ -+ -+ PCSEL14 -+ PCSEL14 -+ 14 -+ 1 -+ -+ -+ PCSEL15 -+ PCSEL15 -+ 15 -+ 1 -+ -+ -+ PCSEL16 -+ PCSEL16 -+ 16 -+ 1 -+ -+ -+ PCSEL17 -+ PCSEL17 -+ 17 -+ 1 -+ -+ -+ PCSEL18 -+ PCSEL18 -+ 18 -+ 1 -+ -+ -+ PCSEL19 -+ PCSEL19 -+ 19 -+ 1 -+ -+ -+ -+ -+ ADC_LTR1 -+ ADC_LTR1 -+ ADC watchdog threshold register 1 -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR1 -+ LTR1 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR1 -+ ADC_HTR1 -+ ADC watchdog threshold register 1 -+ 0x24 -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR1 -+ HTR1 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_SQR1 -+ ADC_SQR1 -+ ADC regular sequence register 1 -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L -+ L -+ 0 -+ 4 -+ -+ -+ SQ1 -+ SQ1 -+ 6 -+ 5 -+ -+ -+ SQ2 -+ SQ2 -+ 12 -+ 5 -+ -+ -+ SQ3 -+ SQ3 -+ 18 -+ 5 -+ -+ -+ SQ4 -+ SQ4 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR2 -+ ADC_SQR2 -+ ADC regular sequence register 2 -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ5 -+ SQ5 -+ 0 -+ 5 -+ -+ -+ SQ6 -+ SQ6 -+ 6 -+ 5 -+ -+ -+ SQ7 -+ SQ7 -+ 12 -+ 5 -+ -+ -+ SQ8 -+ SQ8 -+ 18 -+ 5 -+ -+ -+ SQ9 -+ SQ9 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR3 -+ ADC_SQR3 -+ ADC regular sequence register 3 -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ10 -+ SQ10 -+ 0 -+ 5 -+ -+ -+ SQ11 -+ SQ11 -+ 6 -+ 5 -+ -+ -+ SQ12 -+ SQ12 -+ 12 -+ 5 -+ -+ -+ SQ13 -+ SQ13 -+ 18 -+ 5 -+ -+ -+ SQ14 -+ SQ14 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR4 -+ ADC_SQR4 -+ ADC regular sequence register 4 -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ15 -+ SQ15 -+ 0 -+ 5 -+ -+ -+ SQ16 -+ SQ16 -+ 6 -+ 5 -+ -+ -+ -+ -+ ADC_DR -+ ADC_DR -+ ADC regular Data Register -+ 0x40 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATA -+ RDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JSQR -+ ADC_JSQR -+ ADC injected sequence register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JL -+ JL -+ 0 -+ 2 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 2 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 7 -+ 2 -+ -+ -+ JSQ1 -+ JSQ1 -+ 9 -+ 5 -+ -+ -+ JSQ2 -+ JSQ2 -+ 15 -+ 5 -+ -+ -+ JSQ3 -+ JSQ3 -+ 21 -+ 5 -+ -+ -+ JSQ4 -+ JSQ4 -+ 27 -+ 5 -+ -+ -+ -+ -+ ADC_OFR1 -+ ADC_OFR1 -+ ADC offset register -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET1 -+ OFFSET1 -+ 0 -+ 26 -+ -+ -+ OFFSET1_CH -+ OFFSET1_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR2 -+ ADC_OFR2 -+ ADC offset register -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET2 -+ OFFSET2 -+ 0 -+ 26 -+ -+ -+ OFFSET2_CH -+ OFFSET2_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR3 -+ ADC_OFR3 -+ ADC offset register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET3 -+ OFFSET3 -+ 0 -+ 26 -+ -+ -+ OFFSET3_CH -+ OFFSET3_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR4 -+ ADC_OFR4 -+ ADC offset register -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET4 -+ OFFSET4 -+ 0 -+ 26 -+ -+ -+ OFFSET4_CH -+ OFFSET4_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_JDR1 -+ ADC_JDR1 -+ ADC injected data register -+ 0x80 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR2 -+ ADC_JDR2 -+ ADC injected data register -+ 0x84 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR3 -+ ADC_JDR3 -+ ADC injected data register -+ 0x88 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR4 -+ ADC_JDR4 -+ ADC injected data register -+ 0x8C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_AWD2CR -+ ADC_AWD2CR -+ ADC analog watchdog 2 configuration register -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AWD2CH -+ AWD2CH -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_AWD3CR -+ ADC_AWD3CR -+ ADC analog watchdog 3 configuration register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AWD3CH -+ AWD3CH -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_LTR2 -+ ADC_LTR2 -+ ADC watchdog lower threshold register 2 -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR2 -+ LTR2 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR2 -+ ADC_HTR2 -+ ADC watchdog higher threshold register 2 -+ 0xB4 -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR2 -+ HTR2 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_LTR3 -+ ADC_LTR3 -+ ADC watchdog lower threshold register 3 -+ 0xB8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR3 -+ LTR3 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR3 -+ ADC_HTR3 -+ ADC watchdog higher threshold register 3 -+ 0xBC -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR3 -+ HTR3 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_DIFSEL -+ ADC_DIFSEL -+ ADC differential mode selection register -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIFSEL -+ DIFSEL -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_CALFACT -+ ADC_CALFACT -+ ADC calibration factors register -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CALFACT_S -+ CALFACT_S -+ 0 -+ 11 -+ -+ -+ CALFACT_D -+ CALFACT_D -+ 16 -+ 11 -+ -+ -+ -+ -+ ADC_CALFACT2 -+ ADC_CALFACT2 -+ ADC calibration factor register 2 -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LINCALFACT -+ LINCALFACT -+ 0 -+ 30 -+ -+ -+ -+ -+ ADC2_OR -+ ADC2_OR -+ ADC2 option register -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VDDCOREEN -+ VDDCOREEN -+ 0 -+ 1 -+ -+ -+ -+ -+ -+ -+ ADC -+ ADC -+ ADC -+ 0x48003000 -+ -+ 0x0 -+ 0x100 -+ registers -+ -+ -+ -+ ADC_ISR -+ ADC_ISR -+ ADC interrupt and status register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADRDY -+ ADRDY -+ 0 -+ 1 -+ -+ -+ EOSMP -+ EOSMP -+ 1 -+ 1 -+ -+ -+ EOC -+ EOC -+ 2 -+ 1 -+ -+ -+ EOS -+ EOS -+ 3 -+ 1 -+ -+ -+ OVR -+ OVR -+ 4 -+ 1 -+ -+ -+ JEOC -+ JEOC -+ 5 -+ 1 -+ -+ -+ JEOS -+ JEOS -+ 6 -+ 1 -+ -+ -+ AWD1 -+ AWD1 -+ 7 -+ 1 -+ -+ -+ AWD2 -+ AWD2 -+ 8 -+ 1 -+ -+ -+ AWD3 -+ AWD3 -+ 9 -+ 1 -+ -+ -+ JQOVF -+ JQOVF -+ 10 -+ 1 -+ -+ -+ -+ -+ ADC_IER -+ ADC_IER -+ ADC interrupt enable register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADRDYIE -+ ADRDYIE -+ 0 -+ 1 -+ -+ -+ EOSMPIE -+ EOSMPIE -+ 1 -+ 1 -+ -+ -+ EOCIE -+ EOCIE -+ 2 -+ 1 -+ -+ -+ EOSIE -+ EOSIE -+ 3 -+ 1 -+ -+ -+ OVRIE -+ OVRIE -+ 4 -+ 1 -+ -+ -+ JEOCIE -+ JEOCIE -+ 5 -+ 1 -+ -+ -+ JEOSIE -+ JEOSIE -+ 6 -+ 1 -+ -+ -+ AWD1IE -+ AWD1IE -+ 7 -+ 1 -+ -+ -+ AWD2IE -+ AWD2IE -+ 8 -+ 1 -+ -+ -+ AWD3IE -+ AWD3IE -+ 9 -+ 1 -+ -+ -+ JQOVFIE -+ JQOVFIE -+ 10 -+ 1 -+ -+ -+ -+ -+ ADC_CR -+ ADC_CR -+ ADC control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x20000000 -+ -+ -+ ADEN -+ ADEN -+ 0 -+ 1 -+ -+ -+ ADDIS -+ ADDIS -+ 1 -+ 1 -+ -+ -+ ADSTART -+ ADSTART -+ 2 -+ 1 -+ -+ -+ JADSTART -+ JADSTART -+ 3 -+ 1 -+ -+ -+ ADSTP -+ ADSTP -+ 4 -+ 1 -+ -+ -+ JADSTP -+ JADSTP -+ 5 -+ 1 -+ -+ -+ BOOST -+ BOOST -+ 8 -+ 1 -+ -+ -+ ADCALLIN -+ ADCALLIN -+ 16 -+ 1 -+ -+ -+ LINCALRDYW1 -+ LINCALRDYW1 -+ 22 -+ 1 -+ -+ -+ LINCALRDYW2 -+ LINCALRDYW2 -+ 23 -+ 1 -+ -+ -+ LINCALRDYW3 -+ LINCALRDYW3 -+ 24 -+ 1 -+ -+ -+ LINCALRDYW4 -+ LINCALRDYW4 -+ 25 -+ 1 -+ -+ -+ LINCALRDYW5 -+ LINCALRDYW5 -+ 26 -+ 1 -+ -+ -+ LINCALRDYW6 -+ LINCALRDYW6 -+ 27 -+ 1 -+ -+ -+ ADVREGEN -+ ADVREGEN -+ 28 -+ 1 -+ -+ -+ DEEPPWD -+ DEEPPWD -+ 29 -+ 1 -+ -+ -+ ADCALDIF -+ ADCALDIF -+ 30 -+ 1 -+ -+ -+ ADCAL -+ ADCAL -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_CFGR -+ ADC_CFGR -+ ADC configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x80000000 -+ -+ -+ DMNGT -+ DMNGT -+ 0 -+ 2 -+ -+ -+ RES -+ RES -+ 2 -+ 3 -+ -+ -+ EXTSEL -+ EXTSEL -+ 5 -+ 5 -+ -+ -+ EXTEN -+ EXTEN -+ 10 -+ 2 -+ -+ -+ OVRMOD -+ OVRMOD -+ 12 -+ 1 -+ -+ -+ CONT -+ CONT -+ 13 -+ 1 -+ -+ -+ AUTDLY -+ AUTDLY -+ 14 -+ 1 -+ -+ -+ DISCEN -+ DISCEN -+ 16 -+ 1 -+ -+ -+ DISCNUM -+ DISCNUM -+ 17 -+ 3 -+ -+ -+ JDISCEN -+ JDISCEN -+ 20 -+ 1 -+ -+ -+ JQM -+ JQM -+ 21 -+ 1 -+ -+ -+ AWD1SGL -+ AWD1SGL -+ 22 -+ 1 -+ -+ -+ AWD1EN -+ AWD1EN -+ 23 -+ 1 -+ -+ -+ JAWD1EN -+ JAWD1EN -+ 24 -+ 1 -+ -+ -+ JAUTO -+ JAUTO -+ 25 -+ 1 -+ -+ -+ AWD1CH -+ AWD1CH -+ 26 -+ 5 -+ -+ -+ JQDIS -+ JQDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_CFGR2 -+ ADC_CFGR2 -+ ADC configuration register 2 -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ROVSE -+ ROVSE -+ 0 -+ 1 -+ -+ -+ JOVSE -+ JOVSE -+ 1 -+ 1 -+ -+ -+ OVSS -+ OVSS -+ 5 -+ 4 -+ -+ -+ TROVS -+ TROVS -+ 9 -+ 1 -+ -+ -+ ROVSM -+ ROVSM -+ 10 -+ 1 -+ -+ -+ RSHIFT1 -+ RSHIFT1 -+ 11 -+ 1 -+ -+ -+ RSHIFT2 -+ RSHIFT2 -+ 12 -+ 1 -+ -+ -+ RSHIFT3 -+ RSHIFT3 -+ 13 -+ 1 -+ -+ -+ RSHIFT4 -+ RSHIFT4 -+ 14 -+ 1 -+ -+ -+ OSVR -+ OSVR -+ 16 -+ 10 -+ -+ -+ LSHIFT -+ LSHIFT -+ 28 -+ 4 -+ -+ -+ -+ -+ ADC_SMPR1 -+ ADC_SMPR1 -+ ADC sample time register 1 -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMP0 -+ SMP0 -+ 0 -+ 3 -+ -+ -+ SMP1 -+ SMP1 -+ 3 -+ 3 -+ -+ -+ SMP2 -+ SMP2 -+ 6 -+ 3 -+ -+ -+ SMP3 -+ SMP3 -+ 9 -+ 3 -+ -+ -+ SMP4 -+ SMP4 -+ 12 -+ 3 -+ -+ -+ SMP5 -+ SMP5 -+ 15 -+ 3 -+ -+ -+ SMP6 -+ SMP6 -+ 18 -+ 3 -+ -+ -+ SMP7 -+ SMP7 -+ 21 -+ 3 -+ -+ -+ SMP8 -+ SMP8 -+ 24 -+ 3 -+ -+ -+ SMP9 -+ SMP9 -+ 27 -+ 3 -+ -+ -+ -+ -+ ADC_SMPR2 -+ ADC_SMPR2 -+ ADC sample time register 2 -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMP10 -+ SMP10 -+ 0 -+ 3 -+ -+ -+ SMP11 -+ SMP11 -+ 3 -+ 3 -+ -+ -+ SMP12 -+ SMP12 -+ 6 -+ 3 -+ -+ -+ SMP13 -+ SMP13 -+ 9 -+ 3 -+ -+ -+ SMP14 -+ SMP14 -+ 12 -+ 3 -+ -+ -+ SMP15 -+ SMP15 -+ 15 -+ 3 -+ -+ -+ SMP16 -+ SMP16 -+ 18 -+ 3 -+ -+ -+ SMP17 -+ SMP17 -+ 21 -+ 3 -+ -+ -+ SMP18 -+ SMP18 -+ 24 -+ 3 -+ -+ -+ SMP19 -+ SMP19 -+ 27 -+ 3 -+ -+ -+ -+ -+ ADC_PCSEL -+ ADC_PCSEL -+ ADC channel preselection register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PCSEL0 -+ PCSEL0 -+ 0 -+ 1 -+ -+ -+ PCSEL1 -+ PCSEL1 -+ 1 -+ 1 -+ -+ -+ PCSEL2 -+ PCSEL2 -+ 2 -+ 1 -+ -+ -+ PCSEL3 -+ PCSEL3 -+ 3 -+ 1 -+ -+ -+ PCSEL4 -+ PCSEL4 -+ 4 -+ 1 -+ -+ -+ PCSEL5 -+ PCSEL5 -+ 5 -+ 1 -+ -+ -+ PCSEL6 -+ PCSEL6 -+ 6 -+ 1 -+ -+ -+ PCSEL7 -+ PCSEL7 -+ 7 -+ 1 -+ -+ -+ PCSEL8 -+ PCSEL8 -+ 8 -+ 1 -+ -+ -+ PCSEL9 -+ PCSEL9 -+ 9 -+ 1 -+ -+ -+ PCSEL10 -+ PCSEL10 -+ 10 -+ 1 -+ -+ -+ PCSEL11 -+ PCSEL11 -+ 11 -+ 1 -+ -+ -+ PCSEL12 -+ PCSEL12 -+ 12 -+ 1 -+ -+ -+ PCSEL13 -+ PCSEL13 -+ 13 -+ 1 -+ -+ -+ PCSEL14 -+ PCSEL14 -+ 14 -+ 1 -+ -+ -+ PCSEL15 -+ PCSEL15 -+ 15 -+ 1 -+ -+ -+ PCSEL16 -+ PCSEL16 -+ 16 -+ 1 -+ -+ -+ PCSEL17 -+ PCSEL17 -+ 17 -+ 1 -+ -+ -+ PCSEL18 -+ PCSEL18 -+ 18 -+ 1 -+ -+ -+ PCSEL19 -+ PCSEL19 -+ 19 -+ 1 -+ -+ -+ -+ -+ ADC_LTR1 -+ ADC_LTR1 -+ ADC watchdog threshold register 1 -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR1 -+ LTR1 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR1 -+ ADC_HTR1 -+ ADC watchdog threshold register 1 -+ 0x24 -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR1 -+ HTR1 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_SQR1 -+ ADC_SQR1 -+ ADC regular sequence register 1 -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L -+ L -+ 0 -+ 4 -+ -+ -+ SQ1 -+ SQ1 -+ 6 -+ 5 -+ -+ -+ SQ2 -+ SQ2 -+ 12 -+ 5 -+ -+ -+ SQ3 -+ SQ3 -+ 18 -+ 5 -+ -+ -+ SQ4 -+ SQ4 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR2 -+ ADC_SQR2 -+ ADC regular sequence register 2 -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ5 -+ SQ5 -+ 0 -+ 5 -+ -+ -+ SQ6 -+ SQ6 -+ 6 -+ 5 -+ -+ -+ SQ7 -+ SQ7 -+ 12 -+ 5 -+ -+ -+ SQ8 -+ SQ8 -+ 18 -+ 5 -+ -+ -+ SQ9 -+ SQ9 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR3 -+ ADC_SQR3 -+ ADC regular sequence register 3 -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ10 -+ SQ10 -+ 0 -+ 5 -+ -+ -+ SQ11 -+ SQ11 -+ 6 -+ 5 -+ -+ -+ SQ12 -+ SQ12 -+ 12 -+ 5 -+ -+ -+ SQ13 -+ SQ13 -+ 18 -+ 5 -+ -+ -+ SQ14 -+ SQ14 -+ 24 -+ 5 -+ -+ -+ -+ -+ ADC_SQR4 -+ ADC_SQR4 -+ ADC regular sequence register 4 -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQ15 -+ SQ15 -+ 0 -+ 5 -+ -+ -+ SQ16 -+ SQ16 -+ 6 -+ 5 -+ -+ -+ -+ -+ ADC_DR -+ ADC_DR -+ ADC regular Data Register -+ 0x40 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATA -+ RDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JSQR -+ ADC_JSQR -+ ADC injected sequence register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JL -+ JL -+ 0 -+ 2 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 2 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 7 -+ 2 -+ -+ -+ JSQ1 -+ JSQ1 -+ 9 -+ 5 -+ -+ -+ JSQ2 -+ JSQ2 -+ 15 -+ 5 -+ -+ -+ JSQ3 -+ JSQ3 -+ 21 -+ 5 -+ -+ -+ JSQ4 -+ JSQ4 -+ 27 -+ 5 -+ -+ -+ -+ -+ ADC_OFR1 -+ ADC_OFR1 -+ ADC offset register -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET1 -+ OFFSET1 -+ 0 -+ 26 -+ -+ -+ OFFSET1_CH -+ OFFSET1_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR2 -+ ADC_OFR2 -+ ADC offset register -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET2 -+ OFFSET2 -+ 0 -+ 26 -+ -+ -+ OFFSET2_CH -+ OFFSET2_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR3 -+ ADC_OFR3 -+ ADC offset register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET3 -+ OFFSET3 -+ 0 -+ 26 -+ -+ -+ OFFSET3_CH -+ OFFSET3_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_OFR4 -+ ADC_OFR4 -+ ADC offset register -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OFFSET4 -+ OFFSET4 -+ 0 -+ 26 -+ -+ -+ OFFSET4_CH -+ OFFSET4_CH -+ 26 -+ 5 -+ -+ -+ SSATE -+ SSATE -+ 31 -+ 1 -+ -+ -+ -+ -+ ADC_JDR1 -+ ADC_JDR1 -+ ADC injected data register -+ 0x80 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR2 -+ ADC_JDR2 -+ ADC injected data register -+ 0x84 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR3 -+ ADC_JDR3 -+ ADC injected data register -+ 0x88 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_JDR4 -+ ADC_JDR4 -+ ADC injected data register -+ 0x8C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATA -+ JDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ ADC_AWD2CR -+ ADC_AWD2CR -+ ADC analog watchdog 2 configuration register -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AWD2CH -+ AWD2CH -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_AWD3CR -+ ADC_AWD3CR -+ ADC analog watchdog 3 configuration register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AWD3CH -+ AWD3CH -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_LTR2 -+ ADC_LTR2 -+ ADC watchdog lower threshold register 2 -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR2 -+ LTR2 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR2 -+ ADC_HTR2 -+ ADC watchdog higher threshold register 2 -+ 0xB4 -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR2 -+ HTR2 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_LTR3 -+ ADC_LTR3 -+ ADC watchdog lower threshold register 3 -+ 0xB8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTR3 -+ LTR3 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_HTR3 -+ ADC_HTR3 -+ ADC watchdog higher threshold register 3 -+ 0xBC -+ 0x20 -+ read-write -+ 0x03FFFFFF -+ -+ -+ HTR3 -+ HTR3 -+ 0 -+ 26 -+ -+ -+ -+ -+ ADC_DIFSEL -+ ADC_DIFSEL -+ ADC differential mode selection register -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIFSEL -+ DIFSEL -+ 0 -+ 20 -+ -+ -+ -+ -+ ADC_CALFACT -+ ADC_CALFACT -+ ADC calibration factors register -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CALFACT_S -+ CALFACT_S -+ 0 -+ 11 -+ -+ -+ CALFACT_D -+ CALFACT_D -+ 16 -+ 11 -+ -+ -+ -+ -+ ADC_CALFACT2 -+ ADC_CALFACT2 -+ ADC calibration factor register 2 -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LINCALFACT -+ LINCALFACT -+ 0 -+ 30 -+ -+ -+ -+ -+ -+ -+ ADC_common -+ Analog-to-Digital Converter -+ ADC -+ 0x48003300 -+ -+ 0x0 -+ 0x100 -+ registers -+ -+ -+ -+ CSR -+ CSR -+ ADC Common status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ADDRDY_MST -+ ADDRDY_MST -+ 0 -+ 1 -+ -+ -+ EOSMP_MST -+ EOSMP_MST -+ 1 -+ 1 -+ -+ -+ EOC_MST -+ EOC_MST -+ 2 -+ 1 -+ -+ -+ EOS_MST -+ EOS_MST -+ 3 -+ 1 -+ -+ -+ OVR_MST -+ OVR_MST -+ 4 -+ 1 -+ -+ -+ JEOC_MST -+ JEOC_MST -+ 5 -+ 1 -+ -+ -+ JEOS_MST -+ JEOS_MST -+ 6 -+ 1 -+ -+ -+ AWD1_MST -+ AWD1_MST -+ 7 -+ 1 -+ -+ -+ AWD2_MST -+ AWD2_MST -+ 8 -+ 1 -+ -+ -+ AWD3_MST -+ AWD3_MST -+ 9 -+ 1 -+ -+ -+ JQOVF_MST -+ JQOVF_MST -+ 10 -+ 1 -+ -+ -+ ADRDY_SLV -+ ADRDY_SLV -+ 16 -+ 1 -+ -+ -+ EOSMP_SLV -+ EOSMP_SLV -+ 17 -+ 1 -+ -+ -+ EOC_SLV -+ EOC_SLV -+ 18 -+ 1 -+ -+ -+ EOS_SLV -+ EOS_SLV -+ 19 -+ 1 -+ -+ -+ OVR_SLV -+ OVR_SLV -+ 20 -+ 1 -+ -+ -+ JEOC_SLV -+ JEOC_SLV -+ 21 -+ 1 -+ -+ -+ JEOS_SLV -+ JEOS_SLV -+ 22 -+ 1 -+ -+ -+ AWD1_SLV -+ AWD1_SLV -+ 23 -+ 1 -+ -+ -+ AWD2_SLV -+ AWD2_SLV -+ 24 -+ 1 -+ -+ -+ AWD3_SLV -+ AWD3_SLV -+ 25 -+ 1 -+ -+ -+ JQOVF_SLV -+ JQOVF_SLV -+ 26 -+ 1 -+ -+ -+ -+ -+ CCR -+ CCR -+ ADC common control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKMODE -+ ADC clock mode -+ 16 -+ 2 -+ -+ -+ PRESC -+ ADC prescaler -+ 18 -+ 4 -+ -+ -+ VREFEN -+ VREFINT enable -+ 22 -+ 1 -+ -+ -+ CH17SEL -+ CH17SEL -+ 23 -+ 1 -+ -+ -+ CH18SEL -+ CH18SEL -+ 24 -+ 1 -+ -+ -+ MDMA -+ MDMA -+ 14 -+ 2 -+ -+ -+ DMACFG -+ DMACFG -+ 13 -+ 1 -+ -+ -+ DELAY -+ DELAY -+ 8 -+ 3 -+ -+ -+ DUAL -+ DUAL -+ 0 -+ 5 -+ -+ -+ -+ -+ CDR -+ CDR -+ Common regular data register for dual mode -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATA_MST -+ RDATA_MST -+ 0 -+ 16 -+ -+ -+ RDATA_SLV -+ RDATA_SLV -+ 16 -+ 16 -+ -+ -+ -+ -+ CDR2 -+ CDR2 -+ Common regular data register for dual mode -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATA_ALT -+ RDATA_ALT -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ BSEC -+ BSEC2 -+ BSEC2 -+ 0x5C005000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ BSEC_OTP_CONFIG -+ BSEC_OTP_CONFIG -+ BSEC OTP configuration register -+ 0x0 -+ 0x20 -+ read-write -+ 0x0000000E -+ -+ -+ PWRUP -+ PWRUP -+ 0 -+ 1 -+ -+ -+ FRC -+ FRC -+ 1 -+ 2 -+ -+ -+ PRGWIDTH -+ PRGWIDTH -+ 3 -+ 4 -+ -+ -+ TREAD -+ TREAD -+ 7 -+ 2 -+ -+ -+ -+ -+ BSEC_OTP_CONTROL -+ BSEC_OTP_CONTROL -+ BSEC OTP control register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDR -+ ADDR -+ 0 -+ 7 -+ -+ -+ PROG -+ PROG -+ 8 -+ 1 -+ -+ -+ LOCK -+ LOCK -+ 9 -+ 1 -+ -+ -+ -+ -+ BSEC_OTP_WRDATA -+ BSEC_OTP_WRDATA -+ BSEC OTP write data register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WRDATA -+ WRDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_STATUS -+ BSEC_OTP_STATUS -+ BSEC OTP status register -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SECURE -+ SECURE -+ 0 -+ 1 -+ -+ -+ FULLDBG -+ FULLDBG -+ 1 -+ 1 -+ -+ -+ INVALID -+ INVALID -+ 2 -+ 1 -+ -+ -+ BUSY -+ BUSY -+ 3 -+ 1 -+ -+ -+ PROGFAIL -+ PROGFAIL -+ 4 -+ 1 -+ -+ -+ PWRON -+ PWRON -+ 5 -+ 1 -+ -+ -+ BIST1LOCK -+ BIST1LOCK -+ 6 -+ 1 -+ -+ -+ BIST2LOCK -+ BIST2LOCK -+ 7 -+ 1 -+ -+ -+ -+ -+ BSEC_OTP_LOCK -+ BSEC_OTP_LOCK -+ BSEC OTP lock configuration register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OTP -+ OTP -+ 0 -+ 1 -+ -+ -+ ROMLOCK -+ ROMLOCK -+ 1 -+ 1 -+ -+ -+ DENREG -+ DENREG -+ 2 -+ 1 -+ -+ -+ GPLOCK -+ GPLOCK -+ 4 -+ 1 -+ -+ -+ -+ -+ BSEC_DENABLE -+ BSEC_DENABLE -+ reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFTEN -+ DFTEN -+ 0 -+ 1 -+ -+ -+ DBGEN -+ DBGEN -+ 1 -+ 1 -+ -+ -+ NIDEN -+ NIDEN -+ 2 -+ 1 -+ -+ -+ DEVICEEN -+ DEVICEEN -+ 3 -+ 1 -+ -+ -+ HDPEN -+ HDPEN -+ 4 -+ 1 -+ -+ -+ SPIDEN -+ SPIDEN -+ 5 -+ 1 -+ -+ -+ SPNIDEN -+ SPNIDEN -+ 6 -+ 1 -+ -+ -+ CP15SDISABLE -+ CP15SDISABLE -+ 7 -+ 2 -+ -+ -+ CFGSDISABLE -+ CFGSDISABLE -+ 9 -+ 1 -+ -+ -+ DBGSWENABLE -+ DBGSWENABLE -+ 10 -+ 1 -+ -+ -+ -+ -+ BSEC_OTP_DISTURBED0 -+ BSEC_OTP_DISTURBED0 -+ BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIS -+ DIS -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DISTURBED1 -+ BSEC_OTP_DISTURBED1 -+ BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIS -+ DIS -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DISTURBED2 -+ BSEC_OTP_DISTURBED2 -+ BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. -+ 0x24 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIS -+ DIS -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_ERROR0 -+ BSEC_OTP_ERROR0 -+ BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. -+ 0x34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ERR -+ ERR -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_ERROR1 -+ BSEC_OTP_ERROR1 -+ BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ERR -+ ERR -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_ERROR2 -+ BSEC_OTP_ERROR2 -+ BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. -+ 0x3C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ERR -+ ERR -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_WRLOCK0 -+ BSEC_OTP_WRLOCK0 -+ BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). -+ 0x4C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WRLOCK -+ WRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_WRLOCK1 -+ BSEC_OTP_WRLOCK1 -+ BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). -+ 0x50 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WRLOCK -+ WRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_WRLOCK2 -+ BSEC_OTP_WRLOCK2 -+ BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). -+ 0x54 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WRLOCK -+ WRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SPLOCK0 -+ BSEC_OTP_SPLOCK0 -+ BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPLOCK -+ SPLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SPLOCK1 -+ BSEC_OTP_SPLOCK1 -+ BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPLOCK -+ SPLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SPLOCK2 -+ BSEC_OTP_SPLOCK2 -+ BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPLOCK -+ SPLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SWLOCK0 -+ BSEC_OTP_SWLOCK0 -+ BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. -+ 0x7C -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SWLOCK -+ SWLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SWLOCK1 -+ BSEC_OTP_SWLOCK1 -+ BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SWLOCK -+ SWLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SWLOCK2 -+ BSEC_OTP_SWLOCK2 -+ BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SWLOCK -+ SWLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SRLOCK0 -+ BSEC_OTP_SRLOCK0 -+ BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SRLOCK -+ SRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SRLOCK1 -+ BSEC_OTP_SRLOCK1 -+ BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SRLOCK -+ SRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_SRLOCK2 -+ BSEC_OTP_SRLOCK2 -+ BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SRLOCK -+ SRLOCK -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_JTAGIN -+ BSEC_JTAGIN -+ BSEC JTAG input register -+ 0xAC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 16 -+ -+ -+ -+ -+ BSEC_JTAGOUT -+ BSEC_JTAGOUT -+ BSEC JTAG output register -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 16 -+ -+ -+ -+ -+ BSEC_SCRATCH -+ BSEC_SCRATCH -+ BSEC scratch register -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA0 -+ BSEC_OTP_DATA0 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA1 -+ BSEC_OTP_DATA1 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA2 -+ BSEC_OTP_DATA2 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x208 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA3 -+ BSEC_OTP_DATA3 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA4 -+ BSEC_OTP_DATA4 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA5 -+ BSEC_OTP_DATA5 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x214 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA6 -+ BSEC_OTP_DATA6 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x218 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA7 -+ BSEC_OTP_DATA7 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x21C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA8 -+ BSEC_OTP_DATA8 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA9 -+ BSEC_OTP_DATA9 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA10 -+ BSEC_OTP_DATA10 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x228 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA11 -+ BSEC_OTP_DATA11 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x22C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA12 -+ BSEC_OTP_DATA12 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x230 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA13 -+ BSEC_OTP_DATA13 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x234 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA14 -+ BSEC_OTP_DATA14 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x238 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA15 -+ BSEC_OTP_DATA15 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x23C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA16 -+ BSEC_OTP_DATA16 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x240 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA17 -+ BSEC_OTP_DATA17 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x244 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA18 -+ BSEC_OTP_DATA18 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x248 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA19 -+ BSEC_OTP_DATA19 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x24C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA20 -+ BSEC_OTP_DATA20 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x250 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA21 -+ BSEC_OTP_DATA21 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x254 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA22 -+ BSEC_OTP_DATA22 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x258 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA23 -+ BSEC_OTP_DATA23 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x25C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA24 -+ BSEC_OTP_DATA24 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x260 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA25 -+ BSEC_OTP_DATA25 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x264 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA26 -+ BSEC_OTP_DATA26 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x268 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA27 -+ BSEC_OTP_DATA27 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x26C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA28 -+ BSEC_OTP_DATA28 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x270 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA29 -+ BSEC_OTP_DATA29 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x274 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA30 -+ BSEC_OTP_DATA30 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x278 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA31 -+ BSEC_OTP_DATA31 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x27C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA32 -+ BSEC_OTP_DATA32 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x280 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA33 -+ BSEC_OTP_DATA33 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x284 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA34 -+ BSEC_OTP_DATA34 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x288 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA35 -+ BSEC_OTP_DATA35 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x28C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA36 -+ BSEC_OTP_DATA36 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x290 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA37 -+ BSEC_OTP_DATA37 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x294 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA38 -+ BSEC_OTP_DATA38 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x298 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA39 -+ BSEC_OTP_DATA39 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x29C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA40 -+ BSEC_OTP_DATA40 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA41 -+ BSEC_OTP_DATA41 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA42 -+ BSEC_OTP_DATA42 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA43 -+ BSEC_OTP_DATA43 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA44 -+ BSEC_OTP_DATA44 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA45 -+ BSEC_OTP_DATA45 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA46 -+ BSEC_OTP_DATA46 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2B8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA47 -+ BSEC_OTP_DATA47 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2BC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA48 -+ BSEC_OTP_DATA48 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA49 -+ BSEC_OTP_DATA49 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA50 -+ BSEC_OTP_DATA50 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA51 -+ BSEC_OTP_DATA51 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA52 -+ BSEC_OTP_DATA52 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA53 -+ BSEC_OTP_DATA53 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA54 -+ BSEC_OTP_DATA54 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA55 -+ BSEC_OTP_DATA55 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA56 -+ BSEC_OTP_DATA56 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA57 -+ BSEC_OTP_DATA57 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA58 -+ BSEC_OTP_DATA58 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA59 -+ BSEC_OTP_DATA59 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA60 -+ BSEC_OTP_DATA60 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA61 -+ BSEC_OTP_DATA61 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA62 -+ BSEC_OTP_DATA62 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2F8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA63 -+ BSEC_OTP_DATA63 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x2FC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA64 -+ BSEC_OTP_DATA64 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA65 -+ BSEC_OTP_DATA65 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x304 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA66 -+ BSEC_OTP_DATA66 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x308 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA67 -+ BSEC_OTP_DATA67 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x30C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA68 -+ BSEC_OTP_DATA68 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA69 -+ BSEC_OTP_DATA69 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA70 -+ BSEC_OTP_DATA70 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x318 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA71 -+ BSEC_OTP_DATA71 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x31C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA72 -+ BSEC_OTP_DATA72 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA73 -+ BSEC_OTP_DATA73 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x324 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA74 -+ BSEC_OTP_DATA74 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x328 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA75 -+ BSEC_OTP_DATA75 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x32C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA76 -+ BSEC_OTP_DATA76 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x330 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA77 -+ BSEC_OTP_DATA77 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x334 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA78 -+ BSEC_OTP_DATA78 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x338 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA79 -+ BSEC_OTP_DATA79 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x33C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA80 -+ BSEC_OTP_DATA80 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x340 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA81 -+ BSEC_OTP_DATA81 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x344 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA82 -+ BSEC_OTP_DATA82 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x348 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA83 -+ BSEC_OTP_DATA83 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x34C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA84 -+ BSEC_OTP_DATA84 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x350 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA85 -+ BSEC_OTP_DATA85 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x354 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA86 -+ BSEC_OTP_DATA86 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x358 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA87 -+ BSEC_OTP_DATA87 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x35C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA88 -+ BSEC_OTP_DATA88 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x360 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA89 -+ BSEC_OTP_DATA89 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x364 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA90 -+ BSEC_OTP_DATA90 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x368 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA91 -+ BSEC_OTP_DATA91 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x36C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA92 -+ BSEC_OTP_DATA92 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x370 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA93 -+ BSEC_OTP_DATA93 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x374 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA94 -+ BSEC_OTP_DATA94 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x378 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_OTP_DATA95 -+ BSEC_OTP_DATA95 -+ Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. -+ 0x37C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_HWCFGR -+ BSEC_HWCFGR -+ BSEC hardware configuration register -+ 0xFF0 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ SIZE -+ SIZE -+ 0 -+ 4 -+ -+ -+ ECC_USE -+ ECC_USE -+ 4 -+ 4 -+ -+ -+ -+ -+ BSEC_VERR -+ BSEC_VERR -+ BSEC version register -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ BSEC_IPIDR -+ BSEC_IPIDR -+ BSEC identification register -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00100032 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ BSEC_SIDR -+ BSEC_SIDR -+ BSEC size identification register -+ 0xFFC -+ 0x20 -+ read-only -+ 0xA3C5DD04 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DCMI -+ DCMI -+ DCMI -+ 0x4C006000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DCMI_CR -+ DCMI_CR -+ DCMI control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CAPTURE -+ CAPTURE -+ 0 -+ 1 -+ -+ -+ CM -+ CM -+ 1 -+ 1 -+ -+ -+ CROP -+ CROP -+ 2 -+ 1 -+ -+ -+ JPEG -+ JPEG -+ 3 -+ 1 -+ -+ -+ ESS -+ ESS -+ 4 -+ 1 -+ -+ -+ PCKPOL -+ PCKPOL -+ 5 -+ 1 -+ -+ -+ HSPOL -+ HSPOL -+ 6 -+ 1 -+ -+ -+ VSPOL -+ VSPOL -+ 7 -+ 1 -+ -+ -+ FCRC -+ FCRC -+ 8 -+ 2 -+ -+ -+ EDM -+ EDM -+ 10 -+ 2 -+ -+ -+ ENABLE -+ ENABLE -+ 14 -+ 1 -+ -+ -+ BSM -+ BSM -+ 16 -+ 2 -+ -+ -+ OEBS -+ OEBS -+ 18 -+ 1 -+ -+ -+ LSM -+ LSM -+ 19 -+ 1 -+ -+ -+ OELS -+ OELS -+ 20 -+ 1 -+ -+ -+ -+ -+ DCMI_SR -+ DCMI_SR -+ DCMI status register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HSYNC -+ HSYNC -+ 0 -+ 1 -+ -+ -+ VSYNC -+ VSYNC -+ 1 -+ 1 -+ -+ -+ FNE -+ FNE -+ 2 -+ 1 -+ -+ -+ -+ -+ DCMI_RIS -+ DCMI_RIS -+ DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ FRAME_RIS -+ FRAME_RIS -+ 0 -+ 1 -+ -+ -+ OVR_RIS -+ OVR_RIS -+ 1 -+ 1 -+ -+ -+ ERR_RIS -+ ERR_RIS -+ 2 -+ 1 -+ -+ -+ VSYNC_RIS -+ VSYNC_RIS -+ 3 -+ 1 -+ -+ -+ LINE_RIS -+ LINE_RIS -+ 4 -+ 1 -+ -+ -+ -+ -+ DCMI_IER -+ DCMI_IER -+ The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FRAME_IE -+ FRAME_IE -+ 0 -+ 1 -+ -+ -+ OVR_IE -+ OVR_IE -+ 1 -+ 1 -+ -+ -+ ERR_IE -+ ERR_IE -+ 2 -+ 1 -+ -+ -+ VSYNC_IE -+ VSYNC_IE -+ 3 -+ 1 -+ -+ -+ LINE_IE -+ LINE_IE -+ 4 -+ 1 -+ -+ -+ -+ -+ DCMI_MIS -+ DCMI_MIS -+ This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ FRAME_MIS -+ FRAME_MIS -+ 0 -+ 1 -+ -+ -+ OVR_MIS -+ OVR_MIS -+ 1 -+ 1 -+ -+ -+ ERR_MIS -+ ERR_MIS -+ 2 -+ 1 -+ -+ -+ VSYNC_MIS -+ VSYNC_MIS -+ 3 -+ 1 -+ -+ -+ LINE_MIS -+ LINE_MIS -+ 4 -+ 1 -+ -+ -+ -+ -+ DCMI_ICR -+ DCMI_ICR -+ The DCMI_ICR register is write-only. -+ 0x14 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ FRAME_ISC -+ FRAME_ISC -+ 0 -+ 1 -+ -+ -+ OVR_ISC -+ OVR_ISC -+ 1 -+ 1 -+ -+ -+ ERR_ISC -+ ERR_ISC -+ 2 -+ 1 -+ -+ -+ VSYNC_ISC -+ VSYNC_ISC -+ 3 -+ 1 -+ -+ -+ LINE_ISC -+ LINE_ISC -+ 4 -+ 1 -+ -+ -+ -+ -+ DCMI_ESCR -+ DCMI_ESCR -+ DCMI embedded synchronization code register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FSC -+ FSC -+ 0 -+ 8 -+ -+ -+ LSC -+ LSC -+ 8 -+ 8 -+ -+ -+ LEC -+ LEC -+ 16 -+ 8 -+ -+ -+ FEC -+ FEC -+ 24 -+ 8 -+ -+ -+ -+ -+ DCMI_ESUR -+ DCMI_ESUR -+ DCMI embedded synchronization unmask register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FSU -+ FSU -+ 0 -+ 8 -+ -+ -+ LSU -+ LSU -+ 8 -+ 8 -+ -+ -+ LEU -+ LEU -+ 16 -+ 8 -+ -+ -+ FEU -+ FEU -+ 24 -+ 8 -+ -+ -+ -+ -+ DCMI_CWSTRT -+ DCMI_CWSTRT -+ DCMI crop window start -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HOFFCNT -+ HOFFCNT -+ 0 -+ 14 -+ -+ -+ VST -+ VST -+ 16 -+ 13 -+ -+ -+ -+ -+ DCMI_CWSIZE -+ DCMI_CWSIZE -+ DCMI crop window size -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CAPCNT -+ CAPCNT -+ 0 -+ 14 -+ -+ -+ VLINE -+ VLINE -+ 16 -+ 14 -+ -+ -+ -+ -+ DCMI_DR -+ DCMI_DR -+ DCMI data register -+ 0x28 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ Byte0 -+ Byte0 -+ 0 -+ 8 -+ -+ -+ Byte1 -+ Byte1 -+ 8 -+ 8 -+ -+ -+ Byte2 -+ Byte2 -+ 16 -+ 8 -+ -+ -+ Byte3 -+ Byte3 -+ 24 -+ 8 -+ -+ -+ -+ -+ -+ -+ CRYP1 -+ CRYP1 -+ CRYP1 -+ 0x54001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ CRYP_CR -+ CRYP_CR -+ CRYP control register -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ ALGODIR -+ ALGODIR -+ 2 -+ 1 -+ read-write -+ -+ -+ ALGOMODE -+ ALGOMODE -+ 3 -+ 3 -+ read-write -+ -+ -+ DATATYPE -+ DATATYPE -+ 6 -+ 2 -+ read-write -+ -+ -+ KEYSIZE -+ KEYSIZE -+ 8 -+ 2 -+ read-write -+ -+ -+ FFLUSH -+ FFLUSH -+ 14 -+ 1 -+ write-only -+ -+ -+ CRYPEN -+ CRYPEN -+ 15 -+ 1 -+ read-write -+ -+ -+ GCM_CCMPH -+ GCM_CCMPH -+ 16 -+ 2 -+ read-write -+ -+ -+ ALGOMODE3 -+ ALGOMODE3 -+ 19 -+ 1 -+ read-write -+ -+ -+ NPBLB -+ NPBLB -+ 20 -+ 4 -+ read-write -+ -+ -+ -+ -+ CRYP_SR -+ CRYP_SR -+ CRYP status register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000003 -+ -+ -+ IFEM -+ IFEM -+ 0 -+ 1 -+ -+ -+ IFNF -+ IFNF -+ 1 -+ 1 -+ -+ -+ OFNE -+ OFNE -+ 2 -+ 1 -+ -+ -+ OFFU -+ OFFU -+ 3 -+ 1 -+ -+ -+ BUSY -+ BUSY -+ 4 -+ 1 -+ -+ -+ -+ -+ CRYP_DIN -+ CRYP_DIN -+ The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATAIN -+ DATAIN -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_DOUT -+ CRYP_DOUT -+ The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DATAOUT -+ DATAOUT -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_DMACR -+ CRYP_DMACR -+ CRYP DMA control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIEN -+ DIEN -+ 0 -+ 1 -+ -+ -+ DOEN -+ DOEN -+ 1 -+ 1 -+ -+ -+ -+ -+ CRYP_IMSCR -+ CRYP_IMSCR -+ The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INIM -+ INIM -+ 0 -+ 1 -+ -+ -+ OUTIM -+ OUTIM -+ 1 -+ 1 -+ -+ -+ -+ -+ CRYP_RISR -+ CRYP_RISR -+ The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ INRIS -+ INRIS -+ 0 -+ 1 -+ -+ -+ OUTRIS -+ OUTRIS -+ 1 -+ 1 -+ -+ -+ -+ -+ CRYP_MISR -+ CRYP_MISR -+ The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ INMIS -+ INMIS -+ 0 -+ 1 -+ -+ -+ OUTMIS -+ OUTMIS -+ 1 -+ 1 -+ -+ -+ -+ -+ CRYP_K0LR -+ CRYP_K0LR -+ CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) -+ 0x20 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K0RR -+ CRYP_K0RR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x24 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K1LR -+ CRYP_K1LR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K1RR -+ CRYP_K1RR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x2C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K2LR -+ CRYP_K2LR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x30 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K2RR -+ CRYP_K2RR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x34 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K3LR -+ CRYP_K3LR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x38 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_K3RR -+ CRYP_K3RR -+ Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. -+ 0x3C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ K -+ K -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_IV0LR -+ CRYP_IV0LR -+ The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IV31 -+ IV31 -+ 0 -+ 1 -+ -+ -+ IV30 -+ IV30 -+ 1 -+ 1 -+ -+ -+ IV29 -+ IV29 -+ 2 -+ 1 -+ -+ -+ IV28 -+ IV28 -+ 3 -+ 1 -+ -+ -+ IV27 -+ IV27 -+ 4 -+ 1 -+ -+ -+ IV26 -+ IV26 -+ 5 -+ 1 -+ -+ -+ IV25 -+ IV25 -+ 6 -+ 1 -+ -+ -+ IV24 -+ IV24 -+ 7 -+ 1 -+ -+ -+ IV23 -+ IV23 -+ 8 -+ 1 -+ -+ -+ IV22 -+ IV22 -+ 9 -+ 1 -+ -+ -+ IV21 -+ IV21 -+ 10 -+ 1 -+ -+ -+ IV20 -+ IV20 -+ 11 -+ 1 -+ -+ -+ IV19 -+ IV19 -+ 12 -+ 1 -+ -+ -+ IV18 -+ IV18 -+ 13 -+ 1 -+ -+ -+ IV17 -+ IV17 -+ 14 -+ 1 -+ -+ -+ IV16 -+ IV16 -+ 15 -+ 1 -+ -+ -+ IV15 -+ IV15 -+ 16 -+ 1 -+ -+ -+ IV14 -+ IV14 -+ 17 -+ 1 -+ -+ -+ IV13 -+ IV13 -+ 18 -+ 1 -+ -+ -+ IV12 -+ IV12 -+ 19 -+ 1 -+ -+ -+ IV11 -+ IV11 -+ 20 -+ 1 -+ -+ -+ IV10 -+ IV10 -+ 21 -+ 1 -+ -+ -+ IV9 -+ IV9 -+ 22 -+ 1 -+ -+ -+ IV8 -+ IV8 -+ 23 -+ 1 -+ -+ -+ IV7 -+ IV7 -+ 24 -+ 1 -+ -+ -+ IV6 -+ IV6 -+ 25 -+ 1 -+ -+ -+ IV5 -+ IV5 -+ 26 -+ 1 -+ -+ -+ IV4 -+ IV4 -+ 27 -+ 1 -+ -+ -+ IV3 -+ IV3 -+ 28 -+ 1 -+ -+ -+ IV2 -+ IV2 -+ 29 -+ 1 -+ -+ -+ IV1 -+ IV1 -+ 30 -+ 1 -+ -+ -+ IV0 -+ IV0 -+ 31 -+ 1 -+ -+ -+ -+ -+ CRYP_IV0RR -+ CRYP_IV0RR -+ Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IV63 -+ IV63 -+ 0 -+ 1 -+ -+ -+ IV62 -+ IV62 -+ 1 -+ 1 -+ -+ -+ IV61 -+ IV61 -+ 2 -+ 1 -+ -+ -+ IV60 -+ IV60 -+ 3 -+ 1 -+ -+ -+ IV59 -+ IV59 -+ 4 -+ 1 -+ -+ -+ IV58 -+ IV58 -+ 5 -+ 1 -+ -+ -+ IV57 -+ IV57 -+ 6 -+ 1 -+ -+ -+ IV56 -+ IV56 -+ 7 -+ 1 -+ -+ -+ IV55 -+ IV55 -+ 8 -+ 1 -+ -+ -+ IV54 -+ IV54 -+ 9 -+ 1 -+ -+ -+ IV53 -+ IV53 -+ 10 -+ 1 -+ -+ -+ IV52 -+ IV52 -+ 11 -+ 1 -+ -+ -+ IV51 -+ IV51 -+ 12 -+ 1 -+ -+ -+ IV50 -+ IV50 -+ 13 -+ 1 -+ -+ -+ IV49 -+ IV49 -+ 14 -+ 1 -+ -+ -+ IV48 -+ IV48 -+ 15 -+ 1 -+ -+ -+ IV47 -+ IV47 -+ 16 -+ 1 -+ -+ -+ IV46 -+ IV46 -+ 17 -+ 1 -+ -+ -+ IV45 -+ IV45 -+ 18 -+ 1 -+ -+ -+ IV44 -+ IV44 -+ 19 -+ 1 -+ -+ -+ IV43 -+ IV43 -+ 20 -+ 1 -+ -+ -+ IV42 -+ IV42 -+ 21 -+ 1 -+ -+ -+ IV41 -+ IV41 -+ 22 -+ 1 -+ -+ -+ IV40 -+ IV40 -+ 23 -+ 1 -+ -+ -+ IV39 -+ IV39 -+ 24 -+ 1 -+ -+ -+ IV38 -+ IV38 -+ 25 -+ 1 -+ -+ -+ IV37 -+ IV37 -+ 26 -+ 1 -+ -+ -+ IV36 -+ IV36 -+ 27 -+ 1 -+ -+ -+ IV35 -+ IV35 -+ 28 -+ 1 -+ -+ -+ IV34 -+ IV34 -+ 29 -+ 1 -+ -+ -+ IV33 -+ IV33 -+ 30 -+ 1 -+ -+ -+ IV32 -+ IV32 -+ 31 -+ 1 -+ -+ -+ -+ -+ CRYP_IV1LR -+ CRYP_IV1LR -+ Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IV95 -+ IV95 -+ 0 -+ 1 -+ -+ -+ IV94 -+ IV94 -+ 1 -+ 1 -+ -+ -+ IV93 -+ IV93 -+ 2 -+ 1 -+ -+ -+ IV92 -+ IV92 -+ 3 -+ 1 -+ -+ -+ IV91 -+ IV91 -+ 4 -+ 1 -+ -+ -+ IV90 -+ IV90 -+ 5 -+ 1 -+ -+ -+ IV89 -+ IV89 -+ 6 -+ 1 -+ -+ -+ IV88 -+ IV88 -+ 7 -+ 1 -+ -+ -+ IV87 -+ IV87 -+ 8 -+ 1 -+ -+ -+ IV86 -+ IV86 -+ 9 -+ 1 -+ -+ -+ IV85 -+ IV85 -+ 10 -+ 1 -+ -+ -+ IV84 -+ IV84 -+ 11 -+ 1 -+ -+ -+ IV83 -+ IV83 -+ 12 -+ 1 -+ -+ -+ IV82 -+ IV82 -+ 13 -+ 1 -+ -+ -+ IV81 -+ IV81 -+ 14 -+ 1 -+ -+ -+ IV80 -+ IV80 -+ 15 -+ 1 -+ -+ -+ IV79 -+ IV79 -+ 16 -+ 1 -+ -+ -+ IV78 -+ IV78 -+ 17 -+ 1 -+ -+ -+ IV77 -+ IV77 -+ 18 -+ 1 -+ -+ -+ IV76 -+ IV76 -+ 19 -+ 1 -+ -+ -+ IV75 -+ IV75 -+ 20 -+ 1 -+ -+ -+ IV74 -+ IV74 -+ 21 -+ 1 -+ -+ -+ IV73 -+ IV73 -+ 22 -+ 1 -+ -+ -+ IV72 -+ IV72 -+ 23 -+ 1 -+ -+ -+ IV71 -+ IV71 -+ 24 -+ 1 -+ -+ -+ IV70 -+ IV70 -+ 25 -+ 1 -+ -+ -+ IV69 -+ IV69 -+ 26 -+ 1 -+ -+ -+ IV68 -+ IV68 -+ 27 -+ 1 -+ -+ -+ IV67 -+ IV67 -+ 28 -+ 1 -+ -+ -+ IV66 -+ IV66 -+ 29 -+ 1 -+ -+ -+ IV65 -+ IV65 -+ 30 -+ 1 -+ -+ -+ IV64 -+ IV64 -+ 31 -+ 1 -+ -+ -+ -+ -+ CRYP_IV1RR -+ CRYP_IV1RR -+ Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IV127 -+ IV127 -+ 0 -+ 1 -+ -+ -+ IV126 -+ IV126 -+ 1 -+ 1 -+ -+ -+ IV125 -+ IV125 -+ 2 -+ 1 -+ -+ -+ IV124 -+ IV124 -+ 3 -+ 1 -+ -+ -+ IV123 -+ IV123 -+ 4 -+ 1 -+ -+ -+ IV122 -+ IV122 -+ 5 -+ 1 -+ -+ -+ IV121 -+ IV121 -+ 6 -+ 1 -+ -+ -+ IV120 -+ IV120 -+ 7 -+ 1 -+ -+ -+ IV119 -+ IV119 -+ 8 -+ 1 -+ -+ -+ IV118 -+ IV118 -+ 9 -+ 1 -+ -+ -+ IV117 -+ IV117 -+ 10 -+ 1 -+ -+ -+ IV116 -+ IV116 -+ 11 -+ 1 -+ -+ -+ IV115 -+ IV115 -+ 12 -+ 1 -+ -+ -+ IV114 -+ IV114 -+ 13 -+ 1 -+ -+ -+ IV113 -+ IV113 -+ 14 -+ 1 -+ -+ -+ IV112 -+ IV112 -+ 15 -+ 1 -+ -+ -+ IV111 -+ IV111 -+ 16 -+ 1 -+ -+ -+ IV110 -+ IV110 -+ 17 -+ 1 -+ -+ -+ IV109 -+ IV109 -+ 18 -+ 1 -+ -+ -+ IV108 -+ IV108 -+ 19 -+ 1 -+ -+ -+ IV107 -+ IV107 -+ 20 -+ 1 -+ -+ -+ IV106 -+ IV106 -+ 21 -+ 1 -+ -+ -+ IV105 -+ IV105 -+ 22 -+ 1 -+ -+ -+ IV104 -+ IV104 -+ 23 -+ 1 -+ -+ -+ IV103 -+ IV103 -+ 24 -+ 1 -+ -+ -+ IV102 -+ IV102 -+ 25 -+ 1 -+ -+ -+ IV101 -+ IV101 -+ 26 -+ 1 -+ -+ -+ IV100 -+ IV100 -+ 27 -+ 1 -+ -+ -+ IV99 -+ IV99 -+ 28 -+ 1 -+ -+ -+ IV98 -+ IV98 -+ 29 -+ 1 -+ -+ -+ IV97 -+ IV97 -+ 30 -+ 1 -+ -+ -+ IV96 -+ IV96 -+ 31 -+ 1 -+ -+ -+ -+ -+ CRYP_CSGCMCCM0R -+ CRYP_CSGCMCCM0R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM0 -+ CSGCMCCM0 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM1R -+ CRYP_CSGCMCCM1R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM1 -+ CSGCMCCM1 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM2R -+ CRYP_CSGCMCCM2R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM2 -+ CSGCMCCM2 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM3R -+ CRYP_CSGCMCCM3R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM3 -+ CSGCMCCM3 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM4R -+ CRYP_CSGCMCCM4R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM4 -+ CSGCMCCM4 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM5R -+ CRYP_CSGCMCCM5R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM5 -+ CSGCMCCM5 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM6R -+ CRYP_CSGCMCCM6R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM6 -+ CSGCMCCM6 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCMCCM7R -+ CRYP_CSGCMCCM7R -+ These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCMCCM7 -+ CSGCMCCM7 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM0R -+ CRYP_CSGCM0R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM0 -+ CSGCM0 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM1R -+ CRYP_CSGCM1R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM1 -+ CSGCM1 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM2R -+ CRYP_CSGCM2R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x78 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM2 -+ CSGCM2 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM3R -+ CRYP_CSGCM3R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x7C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM3 -+ CSGCM3 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM4R -+ CRYP_CSGCM4R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM4 -+ CSGCM4 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM5R -+ CRYP_CSGCM5R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM5 -+ CSGCM5 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM6R -+ CRYP_CSGCM6R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM6 -+ CSGCM6 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_CSGCM7R -+ CRYP_CSGCM7R -+ Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSGCM7 -+ CSGCM7 -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_HWCFGR -+ CRYP_HWCFGR -+ CRYP hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000131 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 4 -+ -+ -+ CFG2 -+ CFG2 -+ 4 -+ 4 -+ -+ -+ CFG3 -+ CFG3 -+ 8 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 12 -+ 4 -+ -+ -+ -+ -+ CRYP_VERR -+ CRYP_VERR -+ CRYP HW Version Register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000022 -+ -+ -+ VER -+ VER -+ 0 -+ 8 -+ -+ -+ -+ -+ CRYP_IPIDR -+ CRYP_IPIDR -+ CRYP Identification -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00170011 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ CRYP_MID -+ CRYP_MID -+ CRYP HW Magic ID -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ MID -+ MID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ CRYP2 -+ 0x4C005000 -+ -+ -+ DAC1 -+ DAC1 -+ DAC1 -+ 0x40017000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DAC_CR -+ DAC_CR -+ DAC control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN1 -+ EN1 -+ 0 -+ 1 -+ -+ -+ TEN1 -+ TEN1 -+ 1 -+ 1 -+ -+ -+ TSEL10 -+ TSEL10 -+ 2 -+ 1 -+ -+ -+ TSEL11 -+ TSEL11 -+ 3 -+ 1 -+ -+ -+ TSEL12 -+ TSEL12 -+ 4 -+ 1 -+ -+ -+ TSEL13 -+ TSEL13 -+ 5 -+ 1 -+ -+ -+ WAVE1 -+ WAVE1 -+ 6 -+ 2 -+ -+ -+ MAMP1 -+ MAMP1 -+ 8 -+ 4 -+ -+ -+ DMAEN1 -+ DMAEN1 -+ 12 -+ 1 -+ -+ -+ DMAUDRIE1 -+ DMAUDRIE1 -+ 13 -+ 1 -+ -+ -+ CEN1 -+ CEN1 -+ 14 -+ 1 -+ -+ -+ HFSEL -+ HFSEL -+ 15 -+ 1 -+ -+ -+ EN2 -+ EN2 -+ 16 -+ 1 -+ -+ -+ TEN2 -+ TEN2 -+ 17 -+ 1 -+ -+ -+ TSEL20 -+ TSEL20 -+ 18 -+ 1 -+ -+ -+ TSEL21 -+ TSEL21 -+ 19 -+ 1 -+ -+ -+ TSEL22 -+ TSEL22 -+ 20 -+ 1 -+ -+ -+ TSEL23 -+ TSEL23 -+ 21 -+ 1 -+ -+ -+ WAVE2 -+ WAVE2 -+ 22 -+ 2 -+ -+ -+ MAMP2 -+ MAMP2 -+ 24 -+ 4 -+ -+ -+ DMAEN2 -+ DMAEN2 -+ 28 -+ 1 -+ -+ -+ DMAUDRIE2 -+ DMAUDRIE2 -+ 29 -+ 1 -+ -+ -+ CEN2 -+ CEN2 -+ 30 -+ 1 -+ -+ -+ -+ -+ DAC_SWTRGR -+ DAC_SWTRGR -+ DAC software trigger register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ SWTRIG1 -+ SWTRIG1 -+ 0 -+ 1 -+ -+ -+ SWTRIG2 -+ SWTRIG2 -+ 1 -+ 1 -+ -+ -+ -+ -+ DAC_DHR12R1 -+ DAC_DHR12R1 -+ DAC channel1 12-bit right-aligned data holding register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 0 -+ 12 -+ -+ -+ -+ -+ DAC_DHR12L1 -+ DAC_DHR12L1 -+ DAC channel1 12-bit left aligned data holding register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 4 -+ 12 -+ -+ -+ -+ -+ DAC_DHR8R1 -+ DAC_DHR8R1 -+ DAC channel1 8-bit right aligned data holding register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 0 -+ 8 -+ -+ -+ -+ -+ DAC_DHR12R2 -+ DAC_DHR12R2 -+ This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 0 -+ 12 -+ -+ -+ -+ -+ DAC_DHR12L2 -+ DAC_DHR12L2 -+ This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 4 -+ 12 -+ -+ -+ -+ -+ DAC_DHR8R2 -+ DAC_DHR8R2 -+ This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 0 -+ 8 -+ -+ -+ -+ -+ DAC_DHR12RD -+ DAC_DHR12RD -+ Dual DAC 12-bit right-aligned data holding register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 0 -+ 12 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 16 -+ 12 -+ -+ -+ -+ -+ DAC_DHR12LD -+ DAC_DHR12LD -+ Dual DAC 12-bit left aligned data holding register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 4 -+ 12 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 20 -+ 12 -+ -+ -+ -+ -+ DAC_DHR8RD -+ DAC_DHR8RD -+ Dual DAC 8-bit right aligned data holding register -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DACC1DHR -+ DACC1DHR -+ 0 -+ 8 -+ -+ -+ DACC2DHR -+ DACC2DHR -+ 8 -+ 8 -+ -+ -+ -+ -+ DAC_DOR1 -+ DAC_DOR1 -+ DAC channel1 data output register -+ 0x2C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DACC1DOR -+ DACC1DOR -+ 0 -+ 12 -+ -+ -+ -+ -+ DAC_DOR2 -+ DAC_DOR2 -+ This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DACC2DOR -+ DACC2DOR -+ 0 -+ 12 -+ -+ -+ -+ -+ DAC_SR -+ DAC_SR -+ DAC status register -+ 0x34 -+ 0x20 -+ 0x00000000 -+ -+ -+ DMAUDR1 -+ DMAUDR1 -+ 13 -+ 1 -+ read-write -+ -+ -+ CAL_FLAG1 -+ CAL_FLAG1 -+ 14 -+ 1 -+ read-only -+ -+ -+ BWST1 -+ BWST1 -+ 15 -+ 1 -+ read-only -+ -+ -+ DMAUDR2 -+ DMAUDR2 -+ 29 -+ 1 -+ read-write -+ -+ -+ CAL_FLAG2 -+ CAL_FLAG2 -+ 30 -+ 1 -+ read-only -+ -+ -+ BWST2 -+ BWST2 -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ DAC_CCR -+ DAC_CCR -+ DAC calibration control register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OTRIM1 -+ OTRIM1 -+ 0 -+ 5 -+ -+ -+ OTRIM2 -+ OTRIM2 -+ 16 -+ 5 -+ -+ -+ -+ -+ DAC_MCR -+ DAC_MCR -+ DAC mode control register -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MODE1 -+ MODE1 -+ 0 -+ 3 -+ -+ -+ MODE2 -+ MODE2 -+ 16 -+ 3 -+ -+ -+ -+ -+ DAC_SHSR1 -+ DAC_SHSR1 -+ DAC channel 1 sample and hold sample time register -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSAMPLE1 -+ TSAMPLE1 -+ 0 -+ 10 -+ -+ -+ -+ -+ DAC_SHSR2 -+ DAC_SHSR2 -+ This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSAMPLE2 -+ TSAMPLE2 -+ 0 -+ 10 -+ -+ -+ -+ -+ DAC_SHHR -+ DAC_SHHR -+ DAC sample and hold time register -+ 0x48 -+ 0x20 -+ read-write -+ 0x00010001 -+ -+ -+ THOLD1 -+ THOLD1 -+ 0 -+ 10 -+ -+ -+ THOLD2 -+ THOLD2 -+ 16 -+ 10 -+ -+ -+ -+ -+ DAC_SHRR -+ DAC_SHRR -+ DAC sample and hold refresh time register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00010001 -+ -+ -+ TREFRESH1 -+ TREFRESH1 -+ 0 -+ 8 -+ -+ -+ TREFRESH2 -+ TREFRESH2 -+ 16 -+ 8 -+ -+ -+ -+ -+ DAC_HWCFGR0 -+ DAC_HWCFGR0 -+ DAC IP hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00001111 -+ -+ -+ DUAL -+ DUAL -+ 0 -+ 4 -+ -+ -+ LFSR -+ LFSR -+ 4 -+ 4 -+ -+ -+ TRIANGLE -+ TRIANGLE -+ 8 -+ 4 -+ -+ -+ SAMPLE -+ SAMPLE -+ 12 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 16 -+ 8 -+ -+ -+ -+ -+ DAC_VERR -+ DAC_VERR -+ No -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000031 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DAC_IPIDR -+ DAC_IPIDR -+ No -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00110011 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DAC_SIDR -+ DAC_SIDR -+ No -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DDRCTRL -+ DDRCTRL -+ DDRCTRL -+ 0x5A003000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ DDRCTRL_MSTR -+ DDRCTRL_MSTR -+ DDRCTRL master register 0 -+ 0x0 -+ 0x20 -+ read-write -+ 0x00040001 -+ -+ -+ DDR3 -+ DDR3 -+ 0 -+ 1 -+ -+ -+ LPDDR2 -+ LPDDR2 -+ 2 -+ 1 -+ -+ -+ LPDDR3 -+ LPDDR3 -+ 3 -+ 1 -+ -+ -+ BURSTCHOP -+ BURSTCHOP -+ 9 -+ 1 -+ -+ -+ EN_2T_TIMING_MODE -+ EN_2T_TIMING_MODE -+ 10 -+ 1 -+ -+ -+ DATA_BUS_WIDTH -+ DATA_BUS_WIDTH -+ 12 -+ 2 -+ -+ -+ DLL_OFF_MODE -+ DLL_OFF_MODE -+ 15 -+ 1 -+ -+ -+ BURST_RDWR -+ BURST_RDWR -+ 16 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_STAT -+ DDRCTRL_STAT -+ DDRCTRL operating mode status register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OPERATING_MODE -+ OPERATING_MODE -+ 0 -+ 3 -+ -+ -+ SELFREF_TYPE -+ SELFREF_TYPE -+ 4 -+ 2 -+ -+ -+ SELFREF_CAM_NOT_EMPTY -+ SELFREF_CAM_NOT_EMPTY -+ 12 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_MRCTRL0 -+ DDRCTRL_MRCTRL0 -+ Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000010 -+ -+ -+ MR_TYPE -+ MR_TYPE -+ 0 -+ 1 -+ -+ -+ MR_RANK -+ MR_RANK -+ 4 -+ 1 -+ -+ -+ MR_ADDR -+ MR_ADDR -+ 12 -+ 4 -+ -+ -+ MR_WR -+ MR_WR -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_MRCTRL1 -+ DDRCTRL_MRCTRL1 -+ DDRCTRL mode register read/write control register 1 -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MR_DATA -+ MR_DATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DDRCTRL_MRSTAT -+ DDRCTRL_MRSTAT -+ DDRCTRL mode register read/write status register -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ MR_WR_BUSY -+ MR_WR_BUSY -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DERATEEN -+ DDRCTRL_DERATEEN -+ DDRCTRL temperature derate enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DERATE_ENABLE -+ DERATE_ENABLE -+ 0 -+ 1 -+ -+ -+ DERATE_VALUE -+ DERATE_VALUE -+ 1 -+ 2 -+ -+ -+ DERATE_BYTE -+ DERATE_BYTE -+ 4 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_DERATEINT -+ DDRCTRL_DERATEINT -+ DDRCTRL temperature derate interval register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00800000 -+ -+ -+ MR4_READ_INTERVAL -+ MR4_READ_INTERVAL -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRCTRL_PWRCTL -+ DDRCTRL_PWRCTL -+ DDRCTRL low power control register -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SELFREF_EN -+ SELFREF_EN -+ 0 -+ 1 -+ -+ -+ POWERDOWN_EN -+ POWERDOWN_EN -+ 1 -+ 1 -+ -+ -+ DEEPPOWERDOWN_EN -+ DEEPPOWERDOWN_EN -+ 2 -+ 1 -+ -+ -+ EN_DFI_DRAM_CLK_DISABLE -+ EN_DFI_DRAM_CLK_DISABLE -+ 3 -+ 1 -+ -+ -+ SELFREF_SW -+ SELFREF_SW -+ 5 -+ 1 -+ -+ -+ DIS_CAM_DRAIN_SELFREF -+ DIS_CAM_DRAIN_SELFREF -+ 7 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PWRTMG -+ DDRCTRL_PWRTMG -+ DDRCTRL low power timing register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00402010 -+ -+ -+ POWERDOWN_TO_X32 -+ POWERDOWN_TO_X32 -+ 0 -+ 5 -+ -+ -+ T_DPD_X4096 -+ T_DPD_X4096 -+ 8 -+ 8 -+ -+ -+ SELFREF_TO_X32 -+ SELFREF_TO_X32 -+ 16 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_HWLPCTL -+ DDRCTRL_HWLPCTL -+ DDRCTRL hardware low power control register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ HW_LP_EN -+ HW_LP_EN -+ 0 -+ 1 -+ -+ -+ HW_LP_EXIT_IDLE_EN -+ HW_LP_EXIT_IDLE_EN -+ 1 -+ 1 -+ -+ -+ HW_LP_IDLE_X32 -+ HW_LP_IDLE_X32 -+ 16 -+ 12 -+ -+ -+ -+ -+ DDRCTRL_RFSHCTL0 -+ DDRCTRL_RFSHCTL0 -+ DDRCTRL refresh control register 0 -+ 0x50 -+ 0x20 -+ read-write -+ 0x00210000 -+ -+ -+ PER_BANK_REFRESH -+ PER_BANK_REFRESH -+ 2 -+ 1 -+ -+ -+ REFRESH_BURST -+ REFRESH_BURST -+ 4 -+ 5 -+ -+ -+ REFRESH_TO_X32 -+ REFRESH_TO_X32 -+ 12 -+ 5 -+ -+ -+ REFRESH_MARGIN -+ REFRESH_MARGIN -+ 20 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_RFSHCTL3 -+ DDRCTRL_RFSHCTL3 -+ DDRCTRL refresh control register 3 -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIS_AUTO_REFRESH -+ DIS_AUTO_REFRESH -+ 0 -+ 1 -+ -+ -+ REFRESH_UPDATE_LEVEL -+ REFRESH_UPDATE_LEVEL -+ 1 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_RFSHTMG -+ DDRCTRL_RFSHTMG -+ DDRCTRL refresh timing register -+ 0x64 -+ 0x20 -+ read-write -+ 0x0062008C -+ -+ -+ T_RFC_MIN -+ T_RFC_MIN -+ 0 -+ 10 -+ -+ -+ LPDDR3_TREFBW_EN -+ LPDDR3_TREFBW_EN -+ 15 -+ 1 -+ -+ -+ T_RFC_NOM_X1_X32 -+ T_RFC_NOM_X1_X32 -+ 16 -+ 12 -+ -+ -+ T_RFC_NOM_X1_SEL -+ T_RFC_NOM_X1_SEL -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_CRCPARCTL0 -+ DDRCTRL_CRCPARCTL0 -+ DDRCTRL CRC parity control register 0 -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFI_ALERT_ERR_INT_EN -+ DFI_ALERT_ERR_INT_EN -+ 0 -+ 1 -+ -+ -+ DFI_ALERT_ERR_INT_CLR -+ DFI_ALERT_ERR_INT_CLR -+ 1 -+ 1 -+ -+ -+ DFI_ALERT_ERR_CNT_CLR -+ DFI_ALERT_ERR_CNT_CLR -+ 2 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_CRCPARSTAT -+ DDRCTRL_CRCPARSTAT -+ DDRCTRL CRC parity status register -+ 0xCC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFI_ALERT_ERR_CNT -+ DFI_ALERT_ERR_CNT -+ 0 -+ 16 -+ -+ -+ DFI_ALERT_ERR_INT -+ DFI_ALERT_ERR_INT -+ 16 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_INIT0 -+ DDRCTRL_INIT0 -+ DDRCTRL SDRAM initialization register 0 -+ 0xD0 -+ 0x20 -+ read-write -+ 0x0002004E -+ -+ -+ PRE_CKE_X1024 -+ PRE_CKE_X1024 -+ 0 -+ 12 -+ -+ -+ POST_CKE_X1024 -+ POST_CKE_X1024 -+ 16 -+ 10 -+ -+ -+ SKIP_DRAM_INIT -+ SKIP_DRAM_INIT -+ 30 -+ 2 -+ -+ -+ -+ -+ DDRCTRL_INIT1 -+ DDRCTRL_INIT1 -+ DDRCTRL SDRAM initialization register 1 -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRE_OCD_X32 -+ PRE_OCD_X32 -+ 0 -+ 4 -+ -+ -+ DRAM_RSTN_X1024 -+ DRAM_RSTN_X1024 -+ 16 -+ 9 -+ -+ -+ -+ -+ DDRCTRL_INIT2 -+ DDRCTRL_INIT2 -+ DDRCTRL SDRAM initialization register 2 -+ 0xD8 -+ 0x20 -+ read-write -+ 0x00000D05 -+ -+ -+ MIN_STABLE_CLOCK_X1 -+ MIN_STABLE_CLOCK_X1 -+ 0 -+ 4 -+ -+ -+ IDLE_AFTER_RESET_X32 -+ IDLE_AFTER_RESET_X32 -+ 8 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_INIT3 -+ DDRCTRL_INIT3 -+ DDRCTRL SDRAM initialization register 3 -+ 0xDC -+ 0x20 -+ read-write -+ 0x00000510 -+ -+ -+ EMR -+ EMR -+ 0 -+ 16 -+ -+ -+ MR -+ MR -+ 16 -+ 16 -+ -+ -+ -+ -+ DDRCTRL_INIT4 -+ DDRCTRL_INIT4 -+ DDRCTRL SDRAM initialization register 4 -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EMR3 -+ EMR3 -+ 0 -+ 16 -+ -+ -+ EMR2 -+ EMR2 -+ 16 -+ 16 -+ -+ -+ -+ -+ DDRCTRL_INIT5 -+ DDRCTRL_INIT5 -+ DDRCTRL SDRAM initialization register 5 -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00100004 -+ -+ -+ MAX_AUTO_INIT_X1024 -+ MAX_AUTO_INIT_X1024 -+ 0 -+ 10 -+ -+ -+ DEV_ZQINIT_X32 -+ DEV_ZQINIT_X32 -+ 16 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_DIMMCTL -+ DDRCTRL_DIMMCTL -+ DDRCTRL DIMM control register -+ 0xF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIMM_STAGGER_CS_EN -+ DIMM_STAGGER_CS_EN -+ 0 -+ 1 -+ -+ -+ DIMM_ADDR_MIRR_EN -+ DIMM_ADDR_MIRR_EN -+ 1 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG0 -+ DDRCTRL_DRAMTMG0 -+ DDRCTRL SDRAM timing register 0 -+ 0x100 -+ 0x20 -+ read-write -+ 0x0F101B0F -+ -+ -+ T_RAS_MIN -+ T_RAS_MIN -+ 0 -+ 6 -+ -+ -+ T_RAS_MAX -+ T_RAS_MAX -+ 8 -+ 7 -+ -+ -+ T_FAW -+ T_FAW -+ 16 -+ 6 -+ -+ -+ WR2PRE -+ WR2PRE -+ 24 -+ 7 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG1 -+ DDRCTRL_DRAMTMG1 -+ DDRCTRL SDRAM timing register 1 -+ 0x104 -+ 0x20 -+ read-write -+ 0x00080414 -+ -+ -+ T_RC -+ T_RC -+ 0 -+ 7 -+ -+ -+ RD2PRE -+ RD2PRE -+ 8 -+ 6 -+ -+ -+ T_XP -+ T_XP -+ 16 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG2 -+ DDRCTRL_DRAMTMG2 -+ DDRCTRL SDRAM timing register 2 -+ 0x108 -+ 0x20 -+ read-write -+ 0x0305060D -+ -+ -+ WR2RD -+ WR2RD -+ 0 -+ 6 -+ -+ -+ RD2WR -+ RD2WR -+ 8 -+ 6 -+ -+ -+ READ_LATENCY -+ READ_LATENCY -+ 16 -+ 6 -+ -+ -+ WRITE_LATENCY -+ WRITE_LATENCY -+ 24 -+ 6 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG3 -+ DDRCTRL_DRAMTMG3 -+ DDRCTRL SDRAM timing register 3 -+ 0x10C -+ 0x20 -+ read-write -+ 0x0050400C -+ -+ -+ T_MOD -+ T_MOD -+ 0 -+ 10 -+ -+ -+ T_MRD -+ T_MRD -+ 12 -+ 6 -+ -+ -+ T_MRW -+ T_MRW -+ 20 -+ 10 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG4 -+ DDRCTRL_DRAMTMG4 -+ DDRCTRL SDRAM timing register 4 -+ 0x110 -+ 0x20 -+ read-write -+ 0x05040405 -+ -+ -+ T_RP -+ T_RP -+ 0 -+ 5 -+ -+ -+ T_RRD -+ T_RRD -+ 8 -+ 4 -+ -+ -+ T_CCD -+ T_CCD -+ 16 -+ 4 -+ -+ -+ T_RCD -+ T_RCD -+ 24 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG5 -+ DDRCTRL_DRAMTMG5 -+ DDRCTRL SDRAM timing register 5 -+ 0x114 -+ 0x20 -+ read-write -+ 0x05050403 -+ -+ -+ T_CKE -+ T_CKE -+ 0 -+ 5 -+ -+ -+ T_CKESR -+ T_CKESR -+ 8 -+ 6 -+ -+ -+ T_CKSRE -+ T_CKSRE -+ 16 -+ 4 -+ -+ -+ T_CKSRX -+ T_CKSRX -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG6 -+ DDRCTRL_DRAMTMG6 -+ DDRCTRL SDRAM timing register 6 -+ 0x118 -+ 0x20 -+ read-write -+ 0x02020005 -+ -+ -+ T_CKCSX -+ T_CKCSX -+ 0 -+ 4 -+ -+ -+ T_CKDPDX -+ T_CKDPDX -+ 16 -+ 4 -+ -+ -+ T_CKDPDE -+ T_CKDPDE -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG7 -+ DDRCTRL_DRAMTMG7 -+ DDRCTRL SDRAM timing register 7 -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000202 -+ -+ -+ T_CKPDX -+ T_CKPDX -+ 0 -+ 4 -+ -+ -+ T_CKPDE -+ T_CKPDE -+ 8 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG8 -+ DDRCTRL_DRAMTMG8 -+ DDRCTRL SDRAM timing register 8 -+ 0x120 -+ 0x20 -+ read-write -+ 0x00004405 -+ -+ -+ T_XS_X32 -+ T_XS_X32 -+ 0 -+ 7 -+ -+ -+ T_XS_DLL_X32 -+ T_XS_DLL_X32 -+ 8 -+ 7 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG14 -+ DDRCTRL_DRAMTMG14 -+ DDRCTRL SDRAM timing register 14 -+ 0x138 -+ 0x20 -+ read-write -+ 0x000000A0 -+ -+ -+ T_XSR -+ T_XSR -+ 0 -+ 12 -+ -+ -+ -+ -+ DDRCTRL_DRAMTMG15 -+ DDRCTRL_DRAMTMG15 -+ DDRCTRL SDRAM timing register 15 -+ 0x13C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ T_STAB_X32 -+ T_STAB_X32 -+ 0 -+ 8 -+ -+ -+ EN_DFI_LP_T_STAB -+ EN_DFI_LP_T_STAB -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_ZQCTL0 -+ DDRCTRL_ZQCTL0 -+ DDRCTRL ZQ control register 0 -+ 0x180 -+ 0x20 -+ read-write -+ 0x02000040 -+ -+ -+ T_ZQ_SHORT_NOP -+ T_ZQ_SHORT_NOP -+ 0 -+ 10 -+ -+ -+ T_ZQ_LONG_NOP -+ T_ZQ_LONG_NOP -+ 16 -+ 11 -+ -+ -+ ZQ_RESISTOR_SHARED -+ ZQ_RESISTOR_SHARED -+ 29 -+ 1 -+ -+ -+ DIS_SRX_ZQCL -+ DIS_SRX_ZQCL -+ 30 -+ 1 -+ -+ -+ DIS_AUTO_ZQ -+ DIS_AUTO_ZQ -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_ZQCTL1 -+ DDRCTRL_ZQCTL1 -+ DDRCTRL ZQ control register 1 -+ 0x184 -+ 0x20 -+ read-write -+ 0x02000100 -+ -+ -+ T_ZQ_SHORT_INTERVAL_X1024 -+ T_ZQ_SHORT_INTERVAL_X1024 -+ 0 -+ 20 -+ -+ -+ T_ZQ_RESET_NOP -+ T_ZQ_RESET_NOP -+ 20 -+ 10 -+ -+ -+ -+ -+ DDRCTRL_ZQCTL2 -+ DDRCTRL_ZQCTL2 -+ DDRCTRL ZQ control register 2 -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ZQ_RESET -+ ZQ_RESET -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_ZQSTAT -+ DDRCTRL_ZQSTAT -+ DDRCTRL ZQ status register -+ 0x18C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ZQ_RESET_BUSY -+ ZQ_RESET_BUSY -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DFITMG0 -+ DDRCTRL_DFITMG0 -+ DDRCTRL DFI timing register 0 -+ 0x190 -+ 0x20 -+ read-write -+ 0x07020002 -+ -+ -+ DFI_TPHY_WRLAT -+ DFI_TPHY_WRLAT -+ 0 -+ 6 -+ -+ -+ DFI_TPHY_WRDATA -+ DFI_TPHY_WRDATA -+ 8 -+ 6 -+ -+ -+ DFI_T_RDDATA_EN -+ DFI_T_RDDATA_EN -+ 16 -+ 7 -+ -+ -+ DFI_T_CTRL_DELAY -+ DFI_T_CTRL_DELAY -+ 24 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DFITMG1 -+ DDRCTRL_DFITMG1 -+ DDRCTRL DFI timing register 1 -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000404 -+ -+ -+ DFI_T_DRAM_CLK_ENABLE -+ DFI_T_DRAM_CLK_ENABLE -+ 0 -+ 5 -+ -+ -+ DFI_T_DRAM_CLK_DISABLE -+ DFI_T_DRAM_CLK_DISABLE -+ 8 -+ 5 -+ -+ -+ DFI_T_WRDATA_DELAY -+ DFI_T_WRDATA_DELAY -+ 16 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DFILPCFG0 -+ DDRCTRL_DFILPCFG0 -+ DDRCTRL low power configuration register 0 -+ 0x198 -+ 0x20 -+ read-write -+ 0x07000000 -+ -+ -+ DFI_LP_EN_PD -+ DFI_LP_EN_PD -+ 0 -+ 1 -+ -+ -+ DFI_LP_WAKEUP_PD -+ DFI_LP_WAKEUP_PD -+ 4 -+ 4 -+ -+ -+ DFI_LP_EN_SR -+ DFI_LP_EN_SR -+ 8 -+ 1 -+ -+ -+ DFI_LP_WAKEUP_SR -+ DFI_LP_WAKEUP_SR -+ 12 -+ 4 -+ -+ -+ DFI_LP_EN_DPD -+ DFI_LP_EN_DPD -+ 16 -+ 1 -+ -+ -+ DFI_LP_WAKEUP_DPD -+ DFI_LP_WAKEUP_DPD -+ 20 -+ 4 -+ -+ -+ DFI_TLP_RESP -+ DFI_TLP_RESP -+ 24 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DFIUPD0 -+ DDRCTRL_DFIUPD0 -+ DDRCTRL DFI update register 0 -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00400003 -+ -+ -+ DFI_T_CTRLUP_MIN -+ DFI_T_CTRLUP_MIN -+ 0 -+ 10 -+ -+ -+ DFI_T_CTRLUP_MAX -+ DFI_T_CTRLUP_MAX -+ 16 -+ 10 -+ -+ -+ CTRLUPD_PRE_SRX -+ CTRLUPD_PRE_SRX -+ 29 -+ 1 -+ -+ -+ DIS_AUTO_CTRLUPD_SRX -+ DIS_AUTO_CTRLUPD_SRX -+ 30 -+ 1 -+ -+ -+ DIS_AUTO_CTRLUPD -+ DIS_AUTO_CTRLUPD -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DFIUPD1 -+ DDRCTRL_DFIUPD1 -+ DDRCTRL DFI update register 1 -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00010001 -+ -+ -+ DFI_T_CTRLUPD_INTERVAL_MAX_X1024 -+ DFI_T_CTRLUPD_INTERVAL_MAX_X1024 -+ 0 -+ 8 -+ -+ -+ DFI_T_CTRLUPD_INTERVAL_MIN_X1024 -+ DFI_T_CTRLUPD_INTERVAL_MIN_X1024 -+ 16 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_DFIUPD2 -+ DDRCTRL_DFIUPD2 -+ DDRCTRL DFI update register 2 -+ 0x1A8 -+ 0x20 -+ read-write -+ 0x80000000 -+ -+ -+ DFI_PHYUPD_EN -+ DFI_PHYUPD_EN -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DFIMISC -+ DDRCTRL_DFIMISC -+ DDRCTRL DFI miscellaneous control register -+ 0x1B0 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ DFI_INIT_COMPLETE_EN -+ DFI_INIT_COMPLETE_EN -+ 0 -+ 1 -+ -+ -+ CTL_IDLE_EN -+ CTL_IDLE_EN -+ 4 -+ 1 -+ -+ -+ DFI_INIT_START -+ DFI_INIT_START -+ 5 -+ 1 -+ -+ -+ DFI_FREQUENCY -+ DFI_FREQUENCY -+ 8 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_DFISTAT -+ DDRCTRL_DFISTAT -+ DDRCTRL DFI status register -+ 0x1BC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFI_INIT_COMPLETE -+ DFI_INIT_COMPLETE -+ 0 -+ 1 -+ -+ -+ DFI_LP_ACK -+ DFI_LP_ACK -+ 1 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DFIPHYMSTR -+ DDRCTRL_DFIPHYMSTR -+ DDRCTRL DFI PHY master register -+ 0x1C4 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ DFI_PHYMSTR_EN -+ DFI_PHYMSTR_EN -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP1 -+ DDRCTRL_ADDRMAP1 -+ DDRCTRL address map register 1 -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_BANK_B0 -+ ADDRMAP_BANK_B0 -+ 0 -+ 6 -+ -+ -+ ADDRMAP_BANK_B1 -+ ADDRMAP_BANK_B1 -+ 8 -+ 6 -+ -+ -+ ADDRMAP_BANK_B2 -+ ADDRMAP_BANK_B2 -+ 16 -+ 6 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP2 -+ DDRCTRL_ADDRMAP2 -+ DDRCTRL address map register 2 -+ 0x208 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_COL_B2 -+ ADDRMAP_COL_B2 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_COL_B3 -+ ADDRMAP_COL_B3 -+ 8 -+ 4 -+ -+ -+ ADDRMAP_COL_B4 -+ ADDRMAP_COL_B4 -+ 16 -+ 4 -+ -+ -+ ADDRMAP_COL_B5 -+ ADDRMAP_COL_B5 -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP3 -+ DDRCTRL_ADDRMAP3 -+ DDRCTRL address map register 3 -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_COL_B6 -+ ADDRMAP_COL_B6 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_COL_B7 -+ ADDRMAP_COL_B7 -+ 8 -+ 5 -+ -+ -+ ADDRMAP_COL_B8 -+ ADDRMAP_COL_B8 -+ 16 -+ 5 -+ -+ -+ ADDRMAP_COL_B9 -+ ADDRMAP_COL_B9 -+ 24 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP4 -+ DDRCTRL_ADDRMAP4 -+ DDRCTRL address map register 4 -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_COL_B10 -+ ADDRMAP_COL_B10 -+ 0 -+ 5 -+ -+ -+ ADDRMAP_COL_B11 -+ ADDRMAP_COL_B11 -+ 8 -+ 5 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP5 -+ DDRCTRL_ADDRMAP5 -+ DDRCTRL address map register 5 -+ 0x214 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_ROW_B0 -+ ADDRMAP_ROW_B0 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_ROW_B1 -+ ADDRMAP_ROW_B1 -+ 8 -+ 4 -+ -+ -+ ADDRMAP_ROW_B2_10 -+ ADDRMAP_ROW_B2_10 -+ 16 -+ 4 -+ -+ -+ ADDRMAP_ROW_B11 -+ ADDRMAP_ROW_B11 -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP6 -+ DDRCTRL_ADDRMAP6 -+ DDRCTRL address register 6 -+ 0x218 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_ROW_B12 -+ ADDRMAP_ROW_B12 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_ROW_B13 -+ ADDRMAP_ROW_B13 -+ 8 -+ 4 -+ -+ -+ ADDRMAP_ROW_B14 -+ ADDRMAP_ROW_B14 -+ 16 -+ 4 -+ -+ -+ ADDRMAP_ROW_B15 -+ ADDRMAP_ROW_B15 -+ 24 -+ 4 -+ -+ -+ LPDDR3_6GB_12GB -+ LPDDR3_6GB_12GB -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP9 -+ DDRCTRL_ADDRMAP9 -+ DDRCTRL address map register 9 -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_ROW_B2 -+ ADDRMAP_ROW_B2 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_ROW_B3 -+ ADDRMAP_ROW_B3 -+ 8 -+ 4 -+ -+ -+ ADDRMAP_ROW_B4 -+ ADDRMAP_ROW_B4 -+ 16 -+ 4 -+ -+ -+ ADDRMAP_ROW_B5 -+ ADDRMAP_ROW_B5 -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP10 -+ DDRCTRL_ADDRMAP10 -+ DDRCTRL address map register 10 -+ 0x228 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_ROW_B6 -+ ADDRMAP_ROW_B6 -+ 0 -+ 4 -+ -+ -+ ADDRMAP_ROW_B7 -+ ADDRMAP_ROW_B7 -+ 8 -+ 4 -+ -+ -+ ADDRMAP_ROW_B8 -+ ADDRMAP_ROW_B8 -+ 16 -+ 4 -+ -+ -+ ADDRMAP_ROW_B9 -+ ADDRMAP_ROW_B9 -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ADDRMAP11 -+ DDRCTRL_ADDRMAP11 -+ DDRCTRL address map register 11 -+ 0x22C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRMAP_ROW_B10 -+ ADDRMAP_ROW_B10 -+ 0 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ODTCFG -+ DDRCTRL_ODTCFG -+ DDRCTRL ODT configuration register -+ 0x240 -+ 0x20 -+ read-write -+ 0x04000400 -+ -+ -+ RD_ODT_DELAY -+ RD_ODT_DELAY -+ 2 -+ 5 -+ -+ -+ RD_ODT_HOLD -+ RD_ODT_HOLD -+ 8 -+ 4 -+ -+ -+ WR_ODT_DELAY -+ WR_ODT_DELAY -+ 16 -+ 5 -+ -+ -+ WR_ODT_HOLD -+ WR_ODT_HOLD -+ 24 -+ 4 -+ -+ -+ -+ -+ DDRCTRL_ODTMAP -+ DDRCTRL_ODTMAP -+ DDRCTRL ODT/Rank map register -+ 0x244 -+ 0x20 -+ read-write -+ 0x00000011 -+ -+ -+ RANK0_WR_ODT -+ RANK0_WR_ODT -+ 0 -+ 1 -+ -+ -+ RANK0_RD_ODT -+ RANK0_RD_ODT -+ 4 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_SCHED -+ DDRCTRL_SCHED -+ DDRCTRL scheduler control register -+ 0x250 -+ 0x20 -+ read-write -+ 0x00000805 -+ -+ -+ FORCE_LOW_PRI_N -+ FORCE_LOW_PRI_N -+ 0 -+ 1 -+ -+ -+ PREFER_WRITE -+ PREFER_WRITE -+ 1 -+ 1 -+ -+ -+ PAGECLOSE -+ PAGECLOSE -+ 2 -+ 1 -+ -+ -+ LPR_NUM_ENTRIES -+ LPR_NUM_ENTRIES -+ 8 -+ 4 -+ -+ -+ GO2CRITICAL_HYSTERESIS -+ GO2CRITICAL_HYSTERESIS -+ 16 -+ 8 -+ -+ -+ RDWR_IDLE_GAP -+ RDWR_IDLE_GAP -+ 24 -+ 7 -+ -+ -+ -+ -+ DDRCTRL_SCHED1 -+ DDRCTRL_SCHED1 -+ DDRCTRL scheduler control register 1 -+ 0x254 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAGECLOSE_TIMER -+ PAGECLOSE_TIMER -+ 0 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_PERFHPR1 -+ DDRCTRL_PERFHPR1 -+ DDRCTRL high priority read CAM register 1 -+ 0x25C -+ 0x20 -+ read-write -+ 0x0F000001 -+ -+ -+ HPR_MAX_STARVE -+ HPR_MAX_STARVE -+ 0 -+ 16 -+ -+ -+ HPR_XACT_RUN_LENGTH -+ HPR_XACT_RUN_LENGTH -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_PERFLPR1 -+ DDRCTRL_PERFLPR1 -+ DDRCTRL low priority read CAM register 1 -+ 0x264 -+ 0x20 -+ read-write -+ 0x0F00007F -+ -+ -+ LPR_MAX_STARVE -+ LPR_MAX_STARVE -+ 0 -+ 16 -+ -+ -+ LPR_XACT_RUN_LENGTH -+ LPR_XACT_RUN_LENGTH -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_PERFWR1 -+ DDRCTRL_PERFWR1 -+ DDRCTRL write CAM register 1 -+ 0x26C -+ 0x20 -+ read-write -+ 0x0F00007F -+ -+ -+ W_MAX_STARVE -+ W_MAX_STARVE -+ 0 -+ 16 -+ -+ -+ W_XACT_RUN_LENGTH -+ W_XACT_RUN_LENGTH -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRCTRL_DBG0 -+ DDRCTRL_DBG0 -+ DDRCTRL debug register 0 -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIS_WC -+ DIS_WC -+ 0 -+ 1 -+ -+ -+ DIS_COLLISION_PAGE_OPT -+ DIS_COLLISION_PAGE_OPT -+ 4 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DBG1 -+ DDRCTRL_DBG1 -+ DDRCTRL debug register 1 -+ 0x304 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIS_DQ -+ DIS_DQ -+ 0 -+ 1 -+ -+ -+ DIS_HIF -+ DIS_HIF -+ 1 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DBGCAM -+ DDRCTRL_DBGCAM -+ DDRCTRL CAM debug register -+ 0x308 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DBG_HPR_Q_DEPTH -+ DBG_HPR_Q_DEPTH -+ 0 -+ 5 -+ -+ -+ DBG_LPR_Q_DEPTH -+ DBG_LPR_Q_DEPTH -+ 8 -+ 5 -+ -+ -+ DBG_W_Q_DEPTH -+ DBG_W_Q_DEPTH -+ 16 -+ 5 -+ -+ -+ DBG_STALL -+ DBG_STALL -+ 24 -+ 1 -+ -+ -+ DBG_RD_Q_EMPTY -+ DBG_RD_Q_EMPTY -+ 25 -+ 1 -+ -+ -+ DBG_WR_Q_EMPTY -+ DBG_WR_Q_EMPTY -+ 26 -+ 1 -+ -+ -+ RD_DATA_PIPELINE_EMPTY -+ RD_DATA_PIPELINE_EMPTY -+ 28 -+ 1 -+ -+ -+ WR_DATA_PIPELINE_EMPTY -+ WR_DATA_PIPELINE_EMPTY -+ 29 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DBGCMD -+ DDRCTRL_DBGCMD -+ DDRCTRL command debug register -+ 0x30C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RANK0_REFRESH -+ RANK0_REFRESH -+ 0 -+ 1 -+ -+ -+ ZQ_CALIB_SHORT -+ ZQ_CALIB_SHORT -+ 4 -+ 1 -+ -+ -+ CTRLUPD -+ CTRLUPD -+ 5 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_DBGSTAT -+ DDRCTRL_DBGSTAT -+ DDRCTRL status debug register -+ 0x310 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RANK0_REFRESH_BUSY -+ RANK0_REFRESH_BUSY -+ 0 -+ 1 -+ -+ -+ ZQ_CALIB_SHORT_BUSY -+ ZQ_CALIB_SHORT_BUSY -+ 4 -+ 1 -+ -+ -+ CTRLUPD_BUSY -+ CTRLUPD_BUSY -+ 5 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_SWCTL -+ DDRCTRL_SWCTL -+ DDRCTRL software register programming control enable -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SW_DONE -+ SW_DONE -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_SWSTAT -+ DDRCTRL_SWSTAT -+ DDRCTRL software register programming control status -+ 0x324 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ SW_DONE_ACK -+ SW_DONE_ACK -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_POISONCFG -+ DDRCTRL_POISONCFG -+ AXI Poison configuration register common for all AXI ports. -+ 0x36C -+ 0x20 -+ read-write -+ 0x00110011 -+ -+ -+ WR_POISON_SLVERR_EN -+ WR_POISON_SLVERR_EN -+ 0 -+ 1 -+ -+ -+ WR_POISON_INTR_EN -+ WR_POISON_INTR_EN -+ 4 -+ 1 -+ -+ -+ WR_POISON_INTR_CLR -+ WR_POISON_INTR_CLR -+ 8 -+ 1 -+ -+ -+ RD_POISON_SLVERR_EN -+ RD_POISON_SLVERR_EN -+ 16 -+ 1 -+ -+ -+ RD_POISON_INTR_EN -+ RD_POISON_INTR_EN -+ 20 -+ 1 -+ -+ -+ RD_POISON_INTR_CLR -+ RD_POISON_INTR_CLR -+ 24 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_POISONSTAT -+ DDRCTRL_POISONSTAT -+ DDRCTRL AXI Poison status register -+ 0x370 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WR_POISON_INTR_0 -+ WR_POISON_INTR_0 -+ 0 -+ 1 -+ -+ -+ WR_POISON_INTR_1 -+ WR_POISON_INTR_1 -+ 1 -+ 1 -+ -+ -+ RD_POISON_INTR_0 -+ RD_POISON_INTR_0 -+ 16 -+ 1 -+ -+ -+ RD_POISON_INTR_1 -+ RD_POISON_INTR_1 -+ 17 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PSTAT -+ DDRCTRL_PSTAT -+ DDRCTRL port status register -+ 0x3FC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RD_PORT_BUSY_0 -+ RD_PORT_BUSY_0 -+ 0 -+ 1 -+ -+ -+ RD_PORT_BUSY_1 -+ RD_PORT_BUSY_1 -+ 1 -+ 1 -+ -+ -+ WR_PORT_BUSY_0 -+ WR_PORT_BUSY_0 -+ 16 -+ 1 -+ -+ -+ WR_PORT_BUSY_1 -+ WR_PORT_BUSY_1 -+ 17 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCCFG -+ DDRCTRL_PCCFG -+ DDRCTRL port common configuration register -+ 0x400 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GO2CRITICAL_EN -+ GO2CRITICAL_EN -+ 0 -+ 1 -+ -+ -+ PAGEMATCH_LIMIT -+ PAGEMATCH_LIMIT -+ 4 -+ 1 -+ -+ -+ BL_EXP_MODE -+ BL_EXP_MODE -+ 8 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCFGR_0 -+ DDRCTRL_PCFGR_0 -+ DDRCTRL port 0 configuration read register -+ 0x404 -+ 0x20 -+ read-write -+ 0x00004000 -+ -+ -+ RD_PORT_PRIORITY -+ RD_PORT_PRIORITY -+ 0 -+ 10 -+ -+ -+ RD_PORT_AGING_EN -+ RD_PORT_AGING_EN -+ 12 -+ 1 -+ -+ -+ RD_PORT_URGENT_EN -+ RD_PORT_URGENT_EN -+ 13 -+ 1 -+ -+ -+ RD_PORT_PAGEMATCH_EN -+ RD_PORT_PAGEMATCH_EN -+ 14 -+ 1 -+ -+ -+ RDWR_ORDERED_EN -+ RDWR_ORDERED_EN -+ 16 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCFGW_0 -+ DDRCTRL_PCFGW_0 -+ DDRCTRL port 0 configuration write register -+ 0x408 -+ 0x20 -+ read-write -+ 0x00004000 -+ -+ -+ WR_PORT_PRIORITY -+ WR_PORT_PRIORITY -+ 0 -+ 10 -+ -+ -+ WR_PORT_AGING_EN -+ WR_PORT_AGING_EN -+ 12 -+ 1 -+ -+ -+ WR_PORT_URGENT_EN -+ WR_PORT_URGENT_EN -+ 13 -+ 1 -+ -+ -+ WR_PORT_PAGEMATCH_EN -+ WR_PORT_PAGEMATCH_EN -+ 14 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCTRL_0 -+ DDRCTRL_PCTRL_0 -+ DDRCTRL port 0 control register -+ 0x490 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PORT_EN -+ PORT_EN -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCFGQOS0_0 -+ DDRCTRL_PCFGQOS0_0 -+ DDRCTRL port 0 read Q0S configuration register 0 -+ 0x494 -+ 0x20 -+ read-write -+ 0x02000E00 -+ -+ -+ RQOS_MAP_LEVEL1 -+ RQOS_MAP_LEVEL1 -+ 0 -+ 4 -+ -+ -+ RQOS_MAP_LEVEL2 -+ RQOS_MAP_LEVEL2 -+ 8 -+ 4 -+ -+ -+ RQOS_MAP_REGION0 -+ RQOS_MAP_REGION0 -+ 16 -+ 2 -+ -+ -+ RQOS_MAP_REGION1 -+ RQOS_MAP_REGION1 -+ 20 -+ 2 -+ -+ -+ RQOS_MAP_REGION2 -+ RQOS_MAP_REGION2 -+ 24 -+ 2 -+ -+ -+ -+ -+ DDRCTRL_PCFGQOS1_0 -+ DDRCTRL_PCFGQOS1_0 -+ DDRCTRL port 0 read Q0S configuration register 1 -+ 0x498 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RQOS_MAP_TIMEOUTB -+ RQOS_MAP_TIMEOUTB -+ 0 -+ 11 -+ -+ -+ RQOS_MAP_TIMEOUTR -+ RQOS_MAP_TIMEOUTR -+ 16 -+ 11 -+ -+ -+ -+ -+ DDRCTRL_PCFGWQOS0_0 -+ DDRCTRL_PCFGWQOS0_0 -+ DDRCTRL port 0 write Q0S configuration register 0 -+ 0x49C -+ 0x20 -+ read-write -+ 0x00000E00 -+ -+ -+ WQOS_MAP_LEVEL1 -+ WQOS_MAP_LEVEL1 -+ 0 -+ 4 -+ -+ -+ WQOS_MAP_LEVEL2 -+ WQOS_MAP_LEVEL2 -+ 8 -+ 4 -+ -+ -+ WQOS_MAP_REGION0 -+ WQOS_MAP_REGION0 -+ 16 -+ 2 -+ -+ -+ WQOS_MAP_REGION1 -+ WQOS_MAP_REGION1 -+ 20 -+ 2 -+ -+ -+ WQOS_MAP_REGION2 -+ WQOS_MAP_REGION2 -+ 24 -+ 2 -+ -+ -+ -+ -+ DDRCTRL_PCFGWQOS1_0 -+ DDRCTRL_PCFGWQOS1_0 -+ DDRCTRL port 0 write Q0S configuration register 1 -+ 0x4A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WQOS_MAP_TIMEOUT1 -+ WQOS_MAP_TIMEOUT1 -+ 0 -+ 11 -+ -+ -+ WQOS_MAP_TIMEOUT2 -+ WQOS_MAP_TIMEOUT2 -+ 16 -+ 11 -+ -+ -+ -+ -+ DDRCTRL_PCFGR_1 -+ DDRCTRL_PCFGR_1 -+ DDRCTRL port 1 configuration read register -+ 0x4B4 -+ 0x20 -+ read-write -+ 0x00004000 -+ -+ -+ RD_PORT_PRIORITY -+ RD_PORT_PRIORITY -+ 0 -+ 10 -+ -+ -+ RD_PORT_AGING_EN -+ RD_PORT_AGING_EN -+ 12 -+ 1 -+ -+ -+ RD_PORT_URGENT_EN -+ RD_PORT_URGENT_EN -+ 13 -+ 1 -+ -+ -+ RD_PORT_PAGEMATCH_EN -+ RD_PORT_PAGEMATCH_EN -+ 14 -+ 1 -+ -+ -+ RDWR_ORDERED_EN -+ RDWR_ORDERED_EN -+ 16 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCFGW_1 -+ DDRCTRL_PCFGW_1 -+ DDRCTRL port 1 configuration write register -+ 0x4B8 -+ 0x20 -+ read-write -+ 0x00004000 -+ -+ -+ WR_PORT_PRIORITY -+ WR_PORT_PRIORITY -+ 0 -+ 10 -+ -+ -+ WR_PORT_AGING_EN -+ WR_PORT_AGING_EN -+ 12 -+ 1 -+ -+ -+ WR_PORT_URGENT_EN -+ WR_PORT_URGENT_EN -+ 13 -+ 1 -+ -+ -+ WR_PORT_PAGEMATCH_EN -+ WR_PORT_PAGEMATCH_EN -+ 14 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCTRL_1 -+ DDRCTRL_PCTRL_1 -+ DDRCTRL port 1 control register -+ 0x540 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PORT_EN -+ PORT_EN -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRCTRL_PCFGQOS0_1 -+ DDRCTRL_PCFGQOS0_1 -+ DDRCTRL port 1 read Q0S configuration register 0 -+ 0x544 -+ 0x20 -+ read-write -+ 0x02000E00 -+ -+ -+ RQOS_MAP_LEVEL1 -+ RQOS_MAP_LEVEL1 -+ 0 -+ 4 -+ -+ -+ RQOS_MAP_LEVEL2 -+ RQOS_MAP_LEVEL2 -+ 8 -+ 4 -+ -+ -+ RQOS_MAP_REGION0 -+ RQOS_MAP_REGION0 -+ 16 -+ 2 -+ -+ -+ RQOS_MAP_REGION1 -+ RQOS_MAP_REGION1 -+ 20 -+ 2 -+ -+ -+ RQOS_MAP_REGION2 -+ RQOS_MAP_REGION2 -+ 24 -+ 2 -+ -+ -+ -+ -+ DDRCTRL_PCFGQOS1_1 -+ DDRCTRL_PCFGQOS1_1 -+ DDRCTRL port 1 read Q0S configuration register 1 -+ 0x548 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RQOS_MAP_TIMEOUTB -+ RQOS_MAP_TIMEOUTB -+ 0 -+ 11 -+ -+ -+ RQOS_MAP_TIMEOUTR -+ RQOS_MAP_TIMEOUTR -+ 16 -+ 11 -+ -+ -+ -+ -+ DDRCTRL_PCFGWQOS0_1 -+ DDRCTRL_PCFGWQOS0_1 -+ DDRCTRL port 1 write Q0S configuration register 0 -+ 0x54C -+ 0x20 -+ read-write -+ 0x00000E00 -+ -+ -+ WQOS_MAP_LEVEL1 -+ WQOS_MAP_LEVEL1 -+ 0 -+ 4 -+ -+ -+ WQOS_MAP_LEVEL2 -+ WQOS_MAP_LEVEL2 -+ 8 -+ 4 -+ -+ -+ WQOS_MAP_REGION0 -+ WQOS_MAP_REGION0 -+ 16 -+ 2 -+ -+ -+ WQOS_MAP_REGION1 -+ WQOS_MAP_REGION1 -+ 20 -+ 2 -+ -+ -+ WQOS_MAP_REGION2 -+ WQOS_MAP_REGION2 -+ 24 -+ 2 -+ -+ -+ -+ -+ DDRCTRL_PCFGWQOS1_1 -+ DDRCTRL_PCFGWQOS1_1 -+ DDRCTRL port 1 write Q0S configuration register 1 -+ 0x550 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WQOS_MAP_TIMEOUT1 -+ WQOS_MAP_TIMEOUT1 -+ 0 -+ 11 -+ -+ -+ WQOS_MAP_TIMEOUT2 -+ WQOS_MAP_TIMEOUT2 -+ 16 -+ 11 -+ -+ -+ -+ -+ -+ -+ DDRPERFM -+ DDRPERFM -+ DDRPERFM -+ 0x5A007000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DDRPERFM_CTL -+ DDRPERFM_CTL -+ Write-only register. A read request returns all zeros. -+ 0x0 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ START -+ START -+ 0 -+ 1 -+ -+ -+ STOP -+ STOP -+ 1 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_CFG -+ DDRPERFM_CFG -+ DDRPERFM configurationl register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 4 -+ -+ -+ SEL -+ SEL -+ 16 -+ 2 -+ -+ -+ -+ -+ DDRPERFM_STATUS -+ DDRPERFM_STATUS -+ DDRPERFM status register -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ COVF -+ COVF -+ 0 -+ 4 -+ -+ -+ BUSY -+ BUSY -+ 16 -+ 1 -+ -+ -+ TOVF -+ TOVF -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_CCR -+ DDRPERFM_CCR -+ Write-only register. A read request returns all zeros -+ 0xC -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CCLR -+ CCLR -+ 0 -+ 4 -+ -+ -+ TCLR -+ TCLR -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_IER -+ DDRPERFM_IER -+ DDRPERFM interrupt enable register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OVFIE -+ OVFIE -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_ISR -+ DDRPERFM_ISR -+ DDRPERFM interrupt status register -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OVFF -+ OVFF -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_ICR -+ DDRPERFM_ICR -+ Write-only register. A read request returns all zeros -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ OVF -+ OVF -+ 0 -+ 1 -+ -+ -+ -+ -+ DDRPERFM_TCNT -+ DDRPERFM_TCNT -+ DDRPERFM time counter register -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_CNT0 -+ DDRPERFM_CNT0 -+ DDRPERFM event counter 0 register -+ 0x60 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_CNT1 -+ DDRPERFM_CNT1 -+ DDRPERFM event counter 1 register -+ 0x68 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_CNT2 -+ DDRPERFM_CNT2 -+ DDRPERFM event counter 2 register -+ 0x70 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_CNT3 -+ DDRPERFM_CNT3 -+ DDRPERFM event counter 3 register -+ 0x78 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_HWCFG -+ DDRPERFM_HWCFG -+ DDRPERFM hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ NCNT -+ NCNT -+ 0 -+ 4 -+ -+ -+ -+ -+ DDRPERFM_VER -+ DDRPERFM_VER -+ DDRPERFM version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DDRPERFM_ID -+ DDRPERFM_ID -+ DDRPERFM ID register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140061 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPERFM_SID -+ DDRPERFM_SID -+ DDRPERFM magic ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DDRPHYC -+ DDRPHYC -+ DDRPHYC -+ 0x5A004000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ DDRPHYC_RIDR -+ DDRPHYC_RIDR -+ DDRPHYC revision ID register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00410010 -+ -+ -+ PUBMNR -+ PUBMNR -+ 0 -+ 4 -+ -+ -+ PUBMDR -+ PUBMDR -+ 4 -+ 4 -+ -+ -+ PUBMJR -+ PUBMJR -+ 8 -+ 4 -+ -+ -+ PHYMNR -+ PHYMNR -+ 12 -+ 4 -+ -+ -+ PHYMDR -+ PHYMDR -+ 16 -+ 4 -+ -+ -+ PHYMJR -+ PHYMJR -+ 20 -+ 4 -+ -+ -+ UDRID -+ UDRID -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRPHYC_PIR -+ DDRPHYC_PIR -+ DDRPHYC PHY initialization register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ INIT -+ INIT -+ 0 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 1 -+ 1 -+ -+ -+ DLLLOCK -+ DLLLOCK -+ 2 -+ 1 -+ -+ -+ ZCAL -+ ZCAL -+ 3 -+ 1 -+ -+ -+ ITMSRST -+ ITMSRST -+ 4 -+ 1 -+ -+ -+ DRAMRST -+ DRAMRST -+ 5 -+ 1 -+ -+ -+ DRAMINIT -+ DRAMINIT -+ 6 -+ 1 -+ -+ -+ QSTRN -+ QSTRN -+ 7 -+ 1 -+ -+ -+ RVTRN -+ RVTRN -+ 8 -+ 1 -+ -+ -+ ICPC -+ ICPC -+ 16 -+ 1 -+ -+ -+ DLLBYP -+ DLLBYP -+ 17 -+ 1 -+ -+ -+ CTLDINIT -+ CTLDINIT -+ 18 -+ 1 -+ -+ -+ CLRSR -+ CLRSR -+ 28 -+ 1 -+ -+ -+ LOCKBYP -+ LOCKBYP -+ 29 -+ 1 -+ -+ -+ ZCALBYP -+ ZCALBYP -+ 30 -+ 1 -+ -+ -+ INITBYP -+ INITBYP -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_PGCR -+ DDRPHYC_PGCR -+ DDRPHYC PHY global control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x01BC2E04 -+ -+ -+ ITMDMD -+ ITMDMD -+ 0 -+ 1 -+ -+ -+ DQSCFG -+ DQSCFG -+ 1 -+ 1 -+ -+ -+ DFTCMP -+ DFTCMP -+ 2 -+ 1 -+ -+ -+ DFTLMT -+ DFTLMT -+ 3 -+ 2 -+ -+ -+ DTOSEL -+ DTOSEL -+ 5 -+ 4 -+ -+ -+ CKEN -+ CKEN -+ 9 -+ 3 -+ -+ -+ CKDV -+ CKDV -+ 12 -+ 2 -+ -+ -+ CKINV -+ CKINV -+ 14 -+ 1 -+ -+ -+ IOLB -+ IOLB -+ 15 -+ 1 -+ -+ -+ IODDRM -+ IODDRM -+ 16 -+ 2 -+ -+ -+ RANKEN -+ RANKEN -+ 18 -+ 4 -+ -+ -+ ZKSEL -+ ZKSEL -+ 22 -+ 2 -+ -+ -+ PDDISDX -+ PDDISDX -+ 24 -+ 1 -+ -+ -+ RFSHDT -+ RFSHDT -+ 25 -+ 4 -+ -+ -+ LBDQSS -+ LBDQSS -+ 29 -+ 1 -+ -+ -+ LBGDQS -+ LBGDQS -+ 30 -+ 1 -+ -+ -+ LBMODE -+ LBMODE -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_PGSR -+ DDRPHYC_PGSR -+ DDRPHYC PHY global status register -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDONE -+ IDONE -+ 0 -+ 1 -+ -+ -+ DLDONE -+ DLDONE -+ 1 -+ 1 -+ -+ -+ ZCDDONE -+ ZCDDONE -+ 2 -+ 1 -+ -+ -+ DIDONE -+ DIDONE -+ 3 -+ 1 -+ -+ -+ DTDONE -+ DTDONE -+ 4 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 5 -+ 1 -+ -+ -+ DTIERR -+ DTIERR -+ 6 -+ 1 -+ -+ -+ DFTERR -+ DFTERR -+ 7 -+ 1 -+ -+ -+ RVERR -+ RVERR -+ 8 -+ 1 -+ -+ -+ RVEIRR -+ RVEIRR -+ 9 -+ 1 -+ -+ -+ TQ -+ TQ -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DLLGCR -+ DDRPHYC_DLLGCR -+ DDRPHYC DDR global control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x03737000 -+ -+ -+ DRES -+ DRES -+ 0 -+ 2 -+ -+ -+ IPUMP -+ IPUMP -+ 2 -+ 3 -+ -+ -+ TESTEN -+ TESTEN -+ 5 -+ 1 -+ -+ -+ DTC -+ DTC -+ 6 -+ 3 -+ -+ -+ ATC -+ ATC -+ 9 -+ 2 -+ -+ -+ TESTSW -+ TESTSW -+ 11 -+ 1 -+ -+ -+ MBIAS -+ MBIAS -+ 12 -+ 8 -+ -+ -+ SBIAS2_0 -+ SBIAS2_0 -+ 20 -+ 3 -+ -+ -+ BPS200 -+ BPS200 -+ 23 -+ 1 -+ -+ -+ SBIAS5_3 -+ SBIAS5_3 -+ 24 -+ 3 -+ -+ -+ FDTRMSL -+ FDTRMSL -+ 27 -+ 2 -+ -+ -+ LOCKDET -+ LOCKDET -+ 29 -+ 1 -+ -+ -+ DLLRSVD2 -+ DLLRSVD2 -+ 30 -+ 2 -+ -+ -+ -+ -+ DDRPHYC_ACDLLCR -+ DDRPHYC_ACDLLCR -+ DDRPHYC AC DLL control register -+ 0x14 -+ 0x20 -+ read-write -+ 0x40000000 -+ -+ -+ MFBDLY -+ MFBDLY -+ 6 -+ 3 -+ -+ -+ MFWDLY -+ MFWDLY -+ 9 -+ 3 -+ -+ -+ ATESTEN -+ ATESTEN -+ 18 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 30 -+ 1 -+ -+ -+ DLLDIS -+ DLLDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_PTR0 -+ DDRPHYC_PTR0 -+ DDRPHYC PT register 0 -+ 0x18 -+ 0x20 -+ read-write -+ 0x0022AF9B -+ -+ -+ TDLLSRST -+ TDLLSRST -+ 0 -+ 6 -+ -+ -+ TDLLLOCK -+ TDLLLOCK -+ 6 -+ 12 -+ -+ -+ TITMSRST -+ TITMSRST -+ 18 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_PTR1 -+ DDRPHYC_PTR1 -+ DDRPHYC PT register 1 -+ 0x1C -+ 0x20 -+ read-write -+ 0x0604111D -+ -+ -+ TDINIT0 -+ TDINIT0 -+ 0 -+ 19 -+ -+ -+ TDINIT1 -+ TDINIT1 -+ 19 -+ 8 -+ -+ -+ -+ -+ DDRPHYC_PTR2 -+ DDRPHYC_PTR2 -+ DDRPHYC PT register 2 -+ 0x20 -+ 0x20 -+ read-write -+ 0x042DA072 -+ -+ -+ TDINIT2 -+ TDINIT2 -+ 0 -+ 17 -+ -+ -+ TDINIT3 -+ TDINIT3 -+ 17 -+ 10 -+ -+ -+ -+ -+ DDRPHYC_ACIOCR -+ DDRPHYC_ACIOCR -+ DDRPHYC ACIOC register -+ 0x24 -+ 0x20 -+ read-write -+ 0x33C03812 -+ -+ -+ ACIOM -+ ACIOM -+ 0 -+ 1 -+ -+ -+ ACOE -+ ACOE -+ 1 -+ 1 -+ -+ -+ ACODT -+ ACODT -+ 2 -+ 1 -+ -+ -+ ACPDD -+ ACPDD -+ 3 -+ 1 -+ -+ -+ ACPDR -+ ACPDR -+ 4 -+ 1 -+ -+ -+ CKODT -+ CKODT -+ 5 -+ 3 -+ -+ -+ CKPDD -+ CKPDD -+ 8 -+ 3 -+ -+ -+ CKPDR -+ CKPDR -+ 11 -+ 3 -+ -+ -+ RANKODT -+ RANKODT -+ 14 -+ 1 -+ -+ -+ CSPDD -+ CSPDD -+ 18 -+ 1 -+ -+ -+ RANKPDR -+ RANKPDR -+ 22 -+ 1 -+ -+ -+ RSTODT -+ RSTODT -+ 26 -+ 1 -+ -+ -+ RSTPDD -+ RSTPDD -+ 27 -+ 1 -+ -+ -+ RSTPDR -+ RSTPDR -+ 28 -+ 1 -+ -+ -+ RSTIOM -+ RSTIOM -+ 29 -+ 1 -+ -+ -+ ACSR -+ ACSR -+ 30 -+ 2 -+ -+ -+ -+ -+ DDRPHYC_DXCCR -+ DDRPHYC_DXCCR -+ DDRPHYC DXCC register -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000800 -+ -+ -+ DXODT -+ DXODT -+ 0 -+ 1 -+ -+ -+ DXIOM -+ DXIOM -+ 1 -+ 1 -+ -+ -+ DXPDD -+ DXPDD -+ 2 -+ 1 -+ -+ -+ DXPDR -+ DXPDR -+ 3 -+ 1 -+ -+ -+ DQSRES -+ DQSRES -+ 4 -+ 4 -+ -+ -+ DQSNRES -+ DQSNRES -+ 8 -+ 4 -+ -+ -+ DQSNRST -+ DQSNRST -+ 14 -+ 1 -+ -+ -+ RVSEL -+ RVSEL -+ 15 -+ 1 -+ -+ -+ AWDT -+ AWDT -+ 16 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DSGCR -+ DDRPHYC_DSGCR -+ DDRPHYC DSGC register -+ 0x2C -+ 0x20 -+ read-write -+ 0xFA00001F -+ -+ -+ PUREN -+ PUREN -+ 0 -+ 1 -+ -+ -+ BDISEN -+ BDISEN -+ 1 -+ 1 -+ -+ -+ ZUEN -+ ZUEN -+ 2 -+ 1 -+ -+ -+ LPIOPD -+ LPIOPD -+ 3 -+ 1 -+ -+ -+ LPDLLPD -+ LPDLLPD -+ 4 -+ 1 -+ -+ -+ DQSGX -+ DQSGX -+ 5 -+ 3 -+ -+ -+ DQSGE -+ DQSGE -+ 8 -+ 3 -+ -+ -+ NOBUB -+ NOBUB -+ 11 -+ 1 -+ -+ -+ FXDLAT -+ FXDLAT -+ 12 -+ 1 -+ -+ -+ CKEPDD -+ CKEPDD -+ 16 -+ 1 -+ -+ -+ ODTPDD -+ ODTPDD -+ 20 -+ 1 -+ -+ -+ NL2PD -+ NL2PD -+ 24 -+ 1 -+ -+ -+ NL2OE -+ NL2OE -+ 25 -+ 1 -+ -+ -+ TPDPD -+ TPDPD -+ 26 -+ 1 -+ -+ -+ TPDOE -+ TPDOE -+ 27 -+ 1 -+ -+ -+ CKOE -+ CKOE -+ 28 -+ 1 -+ -+ -+ ODTOE -+ ODTOE -+ 29 -+ 1 -+ -+ -+ RSTOE -+ RSTOE -+ 30 -+ 1 -+ -+ -+ CKEOE -+ CKEOE -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DCR -+ DDRPHYC_DCR -+ DDRPHYC DC register -+ 0x30 -+ 0x20 -+ read-write -+ 0x0000000B -+ -+ -+ DDRMD -+ DDRMD -+ 0 -+ 3 -+ -+ -+ DDR8BNK -+ DDR8BNK -+ 3 -+ 1 -+ -+ -+ PDQ -+ PDQ -+ 4 -+ 3 -+ -+ -+ MPRDQ -+ MPRDQ -+ 7 -+ 1 -+ -+ -+ DDRTYPE -+ DDRTYPE -+ 8 -+ 2 -+ -+ -+ NOSRA -+ NOSRA -+ 27 -+ 1 -+ -+ -+ DDR2T -+ DDR2T -+ 28 -+ 1 -+ -+ -+ UDIMM -+ UDIMM -+ 29 -+ 1 -+ -+ -+ RDIMM -+ RDIMM -+ 30 -+ 1 -+ -+ -+ TPD -+ TPD -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DTPR0 -+ DDRPHYC_DTPR0 -+ DDRPHYC DTP register 0 -+ 0x34 -+ 0x20 -+ read-write -+ 0x3012666E -+ -+ -+ TMRD -+ TMRD -+ 0 -+ 2 -+ -+ -+ TRTP -+ TRTP -+ 2 -+ 3 -+ -+ -+ TWTR -+ TWTR -+ 5 -+ 3 -+ -+ -+ TRP -+ TRP -+ 8 -+ 4 -+ -+ -+ TRCD -+ TRCD -+ 12 -+ 4 -+ -+ -+ TRAS -+ TRAS -+ 16 -+ 5 -+ -+ -+ TRRD -+ TRRD -+ 21 -+ 4 -+ -+ -+ TRC -+ TRC -+ 25 -+ 6 -+ -+ -+ TCCD -+ TCCD -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DTPR1 -+ DDRPHYC_DTPR1 -+ DDRPHYC DTP register 1 -+ 0x38 -+ 0x20 -+ read-write -+ 0x0A030090 -+ -+ -+ TAOND -+ TAOND -+ 0 -+ 2 -+ -+ -+ TRTW -+ TRTW -+ 2 -+ 1 -+ -+ -+ TFAW -+ TFAW -+ 3 -+ 6 -+ -+ -+ TMOD -+ TMOD -+ 9 -+ 2 -+ -+ -+ TRTODT -+ TRTODT -+ 11 -+ 1 -+ -+ -+ TRFC -+ TRFC -+ 16 -+ 8 -+ -+ -+ TDQSCKMIN -+ TDQSCKMIN -+ 24 -+ 3 -+ -+ -+ TDQSCKMAX -+ TDQSCKMAX -+ 27 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DTPR2 -+ DDRPHYC_DTPR2 -+ DDRPHYC DTP register 2 -+ 0x3C -+ 0x20 -+ read-write -+ 0x20040D84 -+ -+ -+ TXS -+ TXS -+ 0 -+ 10 -+ -+ -+ TXP -+ TXP -+ 10 -+ 5 -+ -+ -+ TCKE -+ TCKE -+ 15 -+ 4 -+ -+ -+ TDLLK -+ TDLLK -+ 19 -+ 10 -+ -+ -+ -+ -+ DDRPHYC_DDR3_MR0 -+ DDRPHYC_DDR3_MR0 -+ DDRPHYC MR0 register for DDR3 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000A52 -+ -+ -+ BL -+ BL -+ 0 -+ 2 -+ -+ -+ CL0 -+ CL0 -+ 2 -+ 1 -+ -+ -+ BT -+ BT -+ 3 -+ 1 -+ -+ -+ CL -+ CL -+ 4 -+ 3 -+ -+ -+ TM -+ TM -+ 7 -+ 1 -+ -+ -+ DR -+ DR -+ 8 -+ 1 -+ -+ -+ WR -+ WR -+ 9 -+ 3 -+ -+ -+ PD -+ PD -+ 12 -+ 1 -+ -+ -+ RSVD -+ RSVD -+ 13 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DDR3_MR1 -+ DDRPHYC_DDR3_MR1 -+ DDRPHYC MR1 register for DDR3 -+ 0x44 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DE -+ DE -+ 0 -+ 1 -+ -+ -+ DIC0 -+ DIC0 -+ 1 -+ 1 -+ -+ -+ RTT0 -+ RTT0 -+ 2 -+ 1 -+ -+ -+ AL -+ AL -+ 3 -+ 2 -+ -+ -+ DIC1 -+ DIC1 -+ 5 -+ 1 -+ -+ -+ RTT1 -+ RTT1 -+ 6 -+ 1 -+ -+ -+ LEVEL -+ LEVEL -+ 7 -+ 1 -+ -+ -+ RTT2 -+ RTT2 -+ 9 -+ 1 -+ -+ -+ TDQS -+ TDQS -+ 11 -+ 1 -+ -+ -+ QOFF -+ QOFF -+ 12 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DDR3_MR2 -+ DDRPHYC_DDR3_MR2 -+ DDRPHYC MR2 register for DDR3 -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PASR -+ PASR -+ 0 -+ 3 -+ -+ -+ CWL -+ CWL -+ 3 -+ 3 -+ -+ -+ ASR -+ ASR -+ 6 -+ 1 -+ -+ -+ SRT -+ SRT -+ 7 -+ 1 -+ -+ -+ RTTWR -+ RTTWR -+ 9 -+ 2 -+ -+ -+ -+ -+ DDRPHYC_DDR3_MR3 -+ DDRPHYC_DDR3_MR3 -+ DDRPHYC MR3 register for DDR3 -+ 0x4C -+ 0x8 -+ read-write -+ 0x00000000 -+ -+ -+ MPRLOC -+ MPRLOC -+ 0 -+ 2 -+ -+ -+ MPR -+ MPR -+ 2 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_ODTCR -+ DDRPHYC_ODTCR -+ DDRPHYC ODTC register -+ 0x50 -+ 0x20 -+ read-write -+ 0x84210000 -+ -+ -+ RDODT -+ RDODT -+ 0 -+ 1 -+ -+ -+ WRODT -+ WRODT -+ 16 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DTAR -+ DDRPHYC_DTAR -+ DDRPHYC DTA register -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTCOL -+ DTCOL -+ 0 -+ 12 -+ -+ -+ DTROW -+ DTROW -+ 12 -+ 16 -+ -+ -+ DTBANK -+ DTBANK -+ 28 -+ 3 -+ -+ -+ DTMPR -+ DTMPR -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DTDR0 -+ DDRPHYC_DTDR0 -+ DDRPHYC DTD register 0 -+ 0x58 -+ 0x20 -+ read-write -+ 0xDD22EE11 -+ -+ -+ DTBYTE0 -+ DTBYTE0 -+ 0 -+ 8 -+ -+ -+ DTBYTE1 -+ DTBYTE1 -+ 8 -+ 8 -+ -+ -+ DTBYTE2 -+ DTBYTE2 -+ 16 -+ 8 -+ -+ -+ DTBYTE3 -+ DTBYTE3 -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRPHYC_DTDR1 -+ DDRPHYC_DTDR1 -+ DDRPHYC DTD register 1 -+ 0x5C -+ 0x20 -+ read-write -+ 0x7788BB44 -+ -+ -+ DTBYTE4 -+ DTBYTE4 -+ 0 -+ 8 -+ -+ -+ DTBYTE5 -+ DTBYTE5 -+ 8 -+ 8 -+ -+ -+ DTBYTE6 -+ DTBYTE6 -+ 16 -+ 8 -+ -+ -+ DTBYTE7 -+ DTBYTE7 -+ 24 -+ 8 -+ -+ -+ -+ -+ DDRPHYC_GPR0 -+ DDRPHYC_GPR0 -+ DDRPHYC general purpose register 0 -+ 0x178 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPR0 -+ GPR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPHYC_GPR1 -+ DDRPHYC_GPR1 -+ DDRPHYC general purpose register 1 -+ 0x17C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPR1 -+ GPR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ DDRPHYC_ZQ0CR0 -+ DDRPHYC_ZQ0CR0 -+ DDRPHYC ZQ0C register 0 -+ 0x180 -+ 0x20 -+ read-write -+ 0x0000014A -+ -+ -+ ZDATA -+ ZDATA -+ 0 -+ 20 -+ -+ -+ ZDEN -+ ZDEN -+ 28 -+ 1 -+ -+ -+ ZCALBYP -+ ZCALBYP -+ 29 -+ 1 -+ -+ -+ ZCAL -+ ZCAL -+ 30 -+ 1 -+ -+ -+ ZQPD -+ ZQPD -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_ZQ0CR1 -+ DDRPHYC_ZQ0CR1 -+ DDRPHYC ZQ0CR1 register -+ 0x184 -+ 0x8 -+ read-write -+ 0x0000007B -+ -+ -+ ZPROG -+ ZPROG -+ 0 -+ 8 -+ -+ -+ -+ -+ DDRPHYC_ZQ0SR0 -+ DDRPHYC_ZQ0SR0 -+ DDRPHYC ZQ0S register 0 -+ 0x188 -+ 0x20 -+ read-only -+ 0x0000014A -+ -+ -+ ZCTRL -+ ZCTRL -+ 0 -+ 20 -+ -+ -+ ZERR -+ ZERR -+ 30 -+ 1 -+ -+ -+ ZDONE -+ ZDONE -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_ZQ0SR1 -+ DDRPHYC_ZQ0SR1 -+ DDRPHYC ZQ0S register 1 -+ 0x18C -+ 0x8 -+ read-only -+ 0x00000000 -+ -+ -+ ZPD -+ ZPD -+ 0 -+ 2 -+ -+ -+ ZPU -+ ZPU -+ 2 -+ 2 -+ -+ -+ OPD -+ OPD -+ 4 -+ 2 -+ -+ -+ OPU -+ OPU -+ 6 -+ 2 -+ -+ -+ -+ -+ DDRPHYC_DX0GCR -+ DDRPHYC_DX0GCR -+ DDRPHYC byte lane 0 GC register -+ 0x1C0 -+ 0x20 -+ read-write -+ 0x0000EE81 -+ -+ -+ DXEN -+ DXEN -+ 0 -+ 1 -+ -+ -+ DQSODT -+ DQSODT -+ 1 -+ 1 -+ -+ -+ DQODT -+ DQODT -+ 2 -+ 1 -+ -+ -+ DXIOM -+ DXIOM -+ 3 -+ 1 -+ -+ -+ DXPDD -+ DXPDD -+ 4 -+ 1 -+ -+ -+ DXPDR -+ DXPDR -+ 5 -+ 1 -+ -+ -+ DQSRPD -+ DQSRPD -+ 6 -+ 1 -+ -+ -+ DSEN -+ DSEN -+ 7 -+ 2 -+ -+ -+ DQSRTT -+ DQSRTT -+ 9 -+ 1 -+ -+ -+ DQRTT -+ DQRTT -+ 10 -+ 1 -+ -+ -+ RTTOH -+ RTTOH -+ 11 -+ 2 -+ -+ -+ RTTOAL -+ RTTOAL -+ 13 -+ 1 -+ -+ -+ R0RVSL -+ R0RVSL -+ 14 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX0GSR0 -+ DDRPHYC_DX0GSR0 -+ DDRPHYC byte lane 0 GS register 0 -+ 0x1C4 -+ 0x10 -+ read-only -+ 0x00000000 -+ -+ -+ DTDONE -+ DTDONE -+ 0 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 4 -+ 1 -+ -+ -+ DTIERR -+ DTIERR -+ 8 -+ 1 -+ -+ -+ DTPASS -+ DTPASS -+ 13 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX0GSR1 -+ DDRPHYC_DX0GSR1 -+ DDRPHYC byte lane 0 GS register 1 -+ 0x1C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFTERR -+ DFTERR -+ 0 -+ 1 -+ -+ -+ DQSDFT -+ DQSDFT -+ 4 -+ 2 -+ -+ -+ RVERR -+ RVERR -+ 12 -+ 1 -+ -+ -+ RVIERR -+ RVIERR -+ 16 -+ 1 -+ -+ -+ RVPASS -+ RVPASS -+ 20 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX0DLLCR -+ DDRPHYC_DX0DLLCR -+ DDRPHYC byte lane 0 DLLC register -+ 0x1CC -+ 0x20 -+ read-write -+ 0x40000000 -+ -+ -+ SFBDLY -+ SFBDLY -+ 0 -+ 3 -+ -+ -+ SFWDLY -+ SFWDLY -+ 3 -+ 3 -+ -+ -+ MFBDLY -+ MFBDLY -+ 6 -+ 3 -+ -+ -+ MFWDLY -+ MFWDLY -+ 9 -+ 3 -+ -+ -+ SSTART -+ SSTART -+ 12 -+ 2 -+ -+ -+ SDPHASE -+ SDPHASE -+ 14 -+ 4 -+ -+ -+ ATESTEN -+ ATESTEN -+ 18 -+ 1 -+ -+ -+ SDLBMODE -+ SDLBMODE -+ 19 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 30 -+ 1 -+ -+ -+ DLLDIS -+ DLLDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DX0DQTR -+ DDRPHYC_DX0DQTR -+ DDRPHYC byte lane 0 DQT register -+ 0x1D0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ DQDLY0 -+ DQDLY0 -+ 0 -+ 4 -+ -+ -+ DQDLY1 -+ DQDLY1 -+ 4 -+ 4 -+ -+ -+ DQDLY2 -+ DQDLY2 -+ 8 -+ 4 -+ -+ -+ DQDLY3 -+ DQDLY3 -+ 12 -+ 4 -+ -+ -+ DQDLY4 -+ DQDLY4 -+ 16 -+ 4 -+ -+ -+ DQDLY5 -+ DQDLY5 -+ 20 -+ 4 -+ -+ -+ DQDLY6 -+ DQDLY6 -+ 24 -+ 4 -+ -+ -+ DQDLY7 -+ DQDLY7 -+ 28 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX0DQSTR -+ DDRPHYC_DX0DQSTR -+ DDRPHYC byte lane 0 DQST register -+ 0x1D4 -+ 0x20 -+ read-write -+ 0x3DB02000 -+ -+ -+ R0DGSL -+ R0DGSL -+ 0 -+ 3 -+ -+ -+ R0DGPS -+ R0DGPS -+ 12 -+ 2 -+ -+ -+ DQSDLY -+ DQSDLY -+ 20 -+ 3 -+ -+ -+ DQSNDLY -+ DQSNDLY -+ 23 -+ 3 -+ -+ -+ DMDLY -+ DMDLY -+ 26 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX1GCR -+ DDRPHYC_DX1GCR -+ DDRPHYC byte lane 1 GC register -+ 0x200 -+ 0x20 -+ read-write -+ 0x0000EE81 -+ -+ -+ DXEN -+ DXEN -+ 0 -+ 1 -+ -+ -+ DQSODT -+ DQSODT -+ 1 -+ 1 -+ -+ -+ DQODT -+ DQODT -+ 2 -+ 1 -+ -+ -+ DXIOM -+ DXIOM -+ 3 -+ 1 -+ -+ -+ DXPDD -+ DXPDD -+ 4 -+ 1 -+ -+ -+ DXPDR -+ DXPDR -+ 5 -+ 1 -+ -+ -+ DQSRPD -+ DQSRPD -+ 6 -+ 1 -+ -+ -+ DSEN -+ DSEN -+ 7 -+ 2 -+ -+ -+ DQSRTT -+ DQSRTT -+ 9 -+ 1 -+ -+ -+ DQRTT -+ DQRTT -+ 10 -+ 1 -+ -+ -+ RTTOH -+ RTTOH -+ 11 -+ 2 -+ -+ -+ RTTOAL -+ RTTOAL -+ 13 -+ 1 -+ -+ -+ R0RVSL -+ R0RVSL -+ 14 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX1GSR0 -+ DDRPHYC_DX1GSR0 -+ DDRPHYC byte lane 1 GS register 0 -+ 0x204 -+ 0x10 -+ read-only -+ 0x00000000 -+ -+ -+ DTDONE -+ DTDONE -+ 0 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 4 -+ 1 -+ -+ -+ DTIERR -+ DTIERR -+ 8 -+ 1 -+ -+ -+ DTPASS -+ DTPASS -+ 13 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX1GSR1 -+ DDRPHYC_DX1GSR1 -+ DDRPHYC byte lane 1 GS register 1 -+ 0x208 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFTERR -+ DFTERR -+ 0 -+ 1 -+ -+ -+ DQSDFT -+ DQSDFT -+ 4 -+ 2 -+ -+ -+ RVERR -+ RVERR -+ 12 -+ 1 -+ -+ -+ RVIERR -+ RVIERR -+ 16 -+ 1 -+ -+ -+ RVPASS -+ RVPASS -+ 20 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX1DLLCR -+ DDRPHYC_DX1DLLCR -+ DDRPHYC byte lane 1 DLLC register -+ 0x20C -+ 0x20 -+ read-write -+ 0x40000000 -+ -+ -+ SFBDLY -+ SFBDLY -+ 0 -+ 3 -+ -+ -+ SFWDLY -+ SFWDLY -+ 3 -+ 3 -+ -+ -+ MFBDLY -+ MFBDLY -+ 6 -+ 3 -+ -+ -+ MFWDLY -+ MFWDLY -+ 9 -+ 3 -+ -+ -+ SSTART -+ SSTART -+ 12 -+ 2 -+ -+ -+ SDPHASE -+ SDPHASE -+ 14 -+ 4 -+ -+ -+ ATESTEN -+ ATESTEN -+ 18 -+ 1 -+ -+ -+ SDLBMODE -+ SDLBMODE -+ 19 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 30 -+ 1 -+ -+ -+ DLLDIS -+ DLLDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DX1DQTR -+ DDRPHYC_DX1DQTR -+ DDRPHYC byte lane 1 DQT register -+ 0x210 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ DQDLY0 -+ DQDLY0 -+ 0 -+ 4 -+ -+ -+ DQDLY1 -+ DQDLY1 -+ 4 -+ 4 -+ -+ -+ DQDLY2 -+ DQDLY2 -+ 8 -+ 4 -+ -+ -+ DQDLY3 -+ DQDLY3 -+ 12 -+ 4 -+ -+ -+ DQDLY4 -+ DQDLY4 -+ 16 -+ 4 -+ -+ -+ DQDLY5 -+ DQDLY5 -+ 20 -+ 4 -+ -+ -+ DQDLY6 -+ DQDLY6 -+ 24 -+ 4 -+ -+ -+ DQDLY7 -+ DQDLY7 -+ 28 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX1DQSTR -+ DDRPHYC_DX1DQSTR -+ DDRPHYC byte lane 1 DQST register -+ 0x214 -+ 0x20 -+ read-write -+ 0x3DB02000 -+ -+ -+ R0DGSL -+ R0DGSL -+ 0 -+ 3 -+ -+ -+ R0DGPS -+ R0DGPS -+ 12 -+ 2 -+ -+ -+ DQSDLY -+ DQSDLY -+ 20 -+ 3 -+ -+ -+ DQSNDLY -+ DQSNDLY -+ 23 -+ 3 -+ -+ -+ DMDLY -+ DMDLY -+ 26 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX2GCR -+ DDRPHYC_DX2GCR -+ DDRPHYC byte lane 2 GC register -+ 0x240 -+ 0x20 -+ read-write -+ 0x0000EE81 -+ -+ -+ DXEN -+ DXEN -+ 0 -+ 1 -+ -+ -+ DQSODT -+ DQSODT -+ 1 -+ 1 -+ -+ -+ DQODT -+ DQODT -+ 2 -+ 1 -+ -+ -+ DXIOM -+ DXIOM -+ 3 -+ 1 -+ -+ -+ DXPDD -+ DXPDD -+ 4 -+ 1 -+ -+ -+ DXPDR -+ DXPDR -+ 5 -+ 1 -+ -+ -+ DQSRPD -+ DQSRPD -+ 6 -+ 1 -+ -+ -+ DSEN -+ DSEN -+ 7 -+ 2 -+ -+ -+ DQSRTT -+ DQSRTT -+ 9 -+ 1 -+ -+ -+ DQRTT -+ DQRTT -+ 10 -+ 1 -+ -+ -+ RTTOH -+ RTTOH -+ 11 -+ 2 -+ -+ -+ RTTOAL -+ RTTOAL -+ 13 -+ 1 -+ -+ -+ R0RVSL -+ R0RVSL -+ 14 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX2GSR0 -+ DDRPHYC_DX2GSR0 -+ DDRPHYC byte lane 2 GS register 0 -+ 0x244 -+ 0x10 -+ read-only -+ 0x00000000 -+ -+ -+ DTDONE -+ DTDONE -+ 0 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 4 -+ 1 -+ -+ -+ DTIERR -+ DTIERR -+ 8 -+ 1 -+ -+ -+ DTPASS -+ DTPASS -+ 13 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX2GSR1 -+ DDRPHYC_DX2GSR1 -+ DDRPHYC byte lane 2 GS register 1 -+ 0x248 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFTERR -+ DFTERR -+ 0 -+ 1 -+ -+ -+ DQSDFT -+ DQSDFT -+ 4 -+ 2 -+ -+ -+ RVERR -+ RVERR -+ 12 -+ 1 -+ -+ -+ RVIERR -+ RVIERR -+ 16 -+ 1 -+ -+ -+ RVPASS -+ RVPASS -+ 20 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX2DLLCR -+ DDRPHYC_DX2DLLCR -+ DDRPHYC byte lane 2 DLLC register -+ 0x24C -+ 0x20 -+ read-write -+ 0x40000000 -+ -+ -+ SFBDLY -+ SFBDLY -+ 0 -+ 3 -+ -+ -+ SFWDLY -+ SFWDLY -+ 3 -+ 3 -+ -+ -+ MFBDLY -+ MFBDLY -+ 6 -+ 3 -+ -+ -+ MFWDLY -+ MFWDLY -+ 9 -+ 3 -+ -+ -+ SSTART -+ SSTART -+ 12 -+ 2 -+ -+ -+ SDPHASE -+ SDPHASE -+ 14 -+ 4 -+ -+ -+ ATESTEN -+ ATESTEN -+ 18 -+ 1 -+ -+ -+ SDLBMODE -+ SDLBMODE -+ 19 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 30 -+ 1 -+ -+ -+ DLLDIS -+ DLLDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DX2DQTR -+ DDRPHYC_DX2DQTR -+ DDRPHYC byte lane 2 DQT register -+ 0x250 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ DQDLY0 -+ DQDLY0 -+ 0 -+ 4 -+ -+ -+ DQDLY1 -+ DQDLY1 -+ 4 -+ 4 -+ -+ -+ DQDLY2 -+ DQDLY2 -+ 8 -+ 4 -+ -+ -+ DQDLY3 -+ DQDLY3 -+ 12 -+ 4 -+ -+ -+ DQDLY4 -+ DQDLY4 -+ 16 -+ 4 -+ -+ -+ DQDLY5 -+ DQDLY5 -+ 20 -+ 4 -+ -+ -+ DQDLY6 -+ DQDLY6 -+ 24 -+ 4 -+ -+ -+ DQDLY7 -+ DQDLY7 -+ 28 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX2DQSTR -+ DDRPHYC_DX2DQSTR -+ DDRPHYC byte lane 2 DQST register -+ 0x254 -+ 0x20 -+ read-write -+ 0x3DB02000 -+ -+ -+ R0DGSL -+ R0DGSL -+ 0 -+ 3 -+ -+ -+ R0DGPS -+ R0DGPS -+ 12 -+ 2 -+ -+ -+ DQSDLY -+ DQSDLY -+ 20 -+ 3 -+ -+ -+ DQSNDLY -+ DQSNDLY -+ 23 -+ 3 -+ -+ -+ DMDLY -+ DMDLY -+ 26 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX3GCR -+ DDRPHYC_DX3GCR -+ DDRPHYC byte lane 3 GC register -+ 0x280 -+ 0x20 -+ read-write -+ 0x0000EE81 -+ -+ -+ DXEN -+ DXEN -+ 0 -+ 1 -+ -+ -+ DQSODT -+ DQSODT -+ 1 -+ 1 -+ -+ -+ DQODT -+ DQODT -+ 2 -+ 1 -+ -+ -+ DXIOM -+ DXIOM -+ 3 -+ 1 -+ -+ -+ DXPDD -+ DXPDD -+ 4 -+ 1 -+ -+ -+ DXPDR -+ DXPDR -+ 5 -+ 1 -+ -+ -+ DQSRPD -+ DQSRPD -+ 6 -+ 1 -+ -+ -+ DSEN -+ DSEN -+ 7 -+ 2 -+ -+ -+ DQSRTT -+ DQSRTT -+ 9 -+ 1 -+ -+ -+ DQRTT -+ DQRTT -+ 10 -+ 1 -+ -+ -+ RTTOH -+ RTTOH -+ 11 -+ 2 -+ -+ -+ RTTOAL -+ RTTOAL -+ 13 -+ 1 -+ -+ -+ R0RVSL -+ R0RVSL -+ 14 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX3GSR0 -+ DDRPHYC_DX3GSR0 -+ DDRPHYC byte lane 3 GS register 0 -+ 0x284 -+ 0x10 -+ read-only -+ 0x00000000 -+ -+ -+ DTDONE -+ DTDONE -+ 0 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 4 -+ 1 -+ -+ -+ DTIERR -+ DTIERR -+ 8 -+ 1 -+ -+ -+ DTPASS -+ DTPASS -+ 13 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX3GSR1 -+ DDRPHYC_DX3GSR1 -+ DDRPHYC byte lane 3 GS register 1 -+ 0x288 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DFTERR -+ DFTERR -+ 0 -+ 1 -+ -+ -+ DQSDFT -+ DQSDFT -+ 4 -+ 2 -+ -+ -+ RVERR -+ RVERR -+ 12 -+ 1 -+ -+ -+ RVIERR -+ RVIERR -+ 16 -+ 1 -+ -+ -+ RVPASS -+ RVPASS -+ 20 -+ 3 -+ -+ -+ -+ -+ DDRPHYC_DX3DLLCR -+ DDRPHYC_DX3DLLCR -+ DDRPHYC byte lane 3 DLLC register -+ 0x28C -+ 0x20 -+ read-write -+ 0x40000000 -+ -+ -+ SFBDLY -+ SFBDLY -+ 0 -+ 3 -+ -+ -+ SFWDLY -+ SFWDLY -+ 3 -+ 3 -+ -+ -+ MFBDLY -+ MFBDLY -+ 6 -+ 3 -+ -+ -+ MFWDLY -+ MFWDLY -+ 9 -+ 3 -+ -+ -+ SSTART -+ SSTART -+ 12 -+ 2 -+ -+ -+ SDPHASE -+ SDPHASE -+ 14 -+ 4 -+ -+ -+ ATESTEN -+ ATESTEN -+ 18 -+ 1 -+ -+ -+ SDLBMODE -+ SDLBMODE -+ 19 -+ 1 -+ -+ -+ DLLSRST -+ DLLSRST -+ 30 -+ 1 -+ -+ -+ DLLDIS -+ DLLDIS -+ 31 -+ 1 -+ -+ -+ -+ -+ DDRPHYC_DX3DQTR -+ DDRPHYC_DX3DQTR -+ DDRPHYC byte lane 3 DQT register -+ 0x290 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ DQDLY0 -+ DQDLY0 -+ 0 -+ 4 -+ -+ -+ DQDLY1 -+ DQDLY1 -+ 4 -+ 4 -+ -+ -+ DQDLY2 -+ DQDLY2 -+ 8 -+ 4 -+ -+ -+ DQDLY3 -+ DQDLY3 -+ 12 -+ 4 -+ -+ -+ DQDLY4 -+ DQDLY4 -+ 16 -+ 4 -+ -+ -+ DQDLY5 -+ DQDLY5 -+ 20 -+ 4 -+ -+ -+ DQDLY6 -+ DQDLY6 -+ 24 -+ 4 -+ -+ -+ DQDLY7 -+ DQDLY7 -+ 28 -+ 4 -+ -+ -+ -+ -+ DDRPHYC_DX3DQSTR -+ DDRPHYC_DX3DQSTR -+ DDRPHYC byte lane 3 DQST register -+ 0x294 -+ 0x20 -+ read-write -+ 0x3DB02000 -+ -+ -+ R0DGSL -+ R0DGSL -+ 0 -+ 3 -+ -+ -+ R0DGPS -+ R0DGPS -+ 12 -+ 2 -+ -+ -+ DQSDLY -+ DQSDLY -+ 20 -+ 3 -+ -+ -+ DQSNDLY -+ DQSNDLY -+ 23 -+ 3 -+ -+ -+ DMDLY -+ DMDLY -+ 26 -+ 4 -+ -+ -+ -+ -+ -+ -+ DLYBSD1 -+ DLYBSD1 -+ DLYBSD1 -+ 0x58006000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ DLYB_CR -+ DLYB_CR -+ DLYB control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DEN -+ DEN -+ 0 -+ 1 -+ -+ -+ SEN -+ SEN -+ 1 -+ 1 -+ -+ -+ -+ -+ DLYB_CFGR -+ DLYB_CFGR -+ DLYB configuration register -+ 0x4 -+ 0x20 -+ 0x00000000 -+ -+ -+ SEL -+ SEL -+ 0 -+ 4 -+ read-write -+ -+ -+ UNIT -+ UNIT -+ 8 -+ 7 -+ read-write -+ -+ -+ LNG -+ LNG -+ 16 -+ 12 -+ read-only -+ -+ -+ LNGF -+ LNGF -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ DLYB_VERR -+ DLYB_VERR -+ DLYB IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DLYB_IPIDR -+ DLYB_IPIDR -+ DLYB IP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140051 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DLYB_SIDR -+ DLYB_SIDR -+ DLYB size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DLYBSD2 -+ 0x58008000 -+ -+ -+ DLYBSD3 -+ 0x48005000 -+ -+ -+ DFSDM1 -+ DFSDM1 -+ DFSDM1 -+ 0x4400D000 -+ -+ 0x0 -+ 0x800 -+ registers -+ -+ -+ -+ DFSDM_CH0CFGR1 -+ DFSDM_CH0CFGR1 -+ This register specifies the parameters used by channel y. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH0CFGR2 -+ DFSDM_CH0CFGR2 -+ This register specifies the parameters used by channel y. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH0AWSCDR -+ DFSDM_CH0AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH0WDATR -+ DFSDM_CH0WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH0DATINR -+ DFSDM_CH0DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH0DLYR -+ DFSDM_CH0DLYR -+ DFSDM channel 0 delay register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH1CFGR1 -+ DFSDM_CH1CFGR1 -+ This register specifies the parameters used by channel y. -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH1CFGR2 -+ DFSDM_CH1CFGR2 -+ This register specifies the parameters used by channel y. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH1AWSCDR -+ DFSDM_CH1AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH1WDATR -+ DFSDM_CH1WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0x2C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH1DATINR -+ DFSDM_CH1DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH1DLYR -+ DFSDM_CH1DLYR -+ DFSDM channel 1 delay register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH2CFGR1 -+ DFSDM_CH2CFGR1 -+ This register specifies the parameters used by channel y. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH2CFGR2 -+ DFSDM_CH2CFGR2 -+ This register specifies the parameters used by channel y. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH2AWSCDR -+ DFSDM_CH2AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH2WDATR -+ DFSDM_CH2WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0x4C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH2DATINR -+ DFSDM_CH2DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH2DLYR -+ DFSDM_CH2DLYR -+ DFSDM channel 2 delay register -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH3CFGR1 -+ DFSDM_CH3CFGR1 -+ This register specifies the parameters used by channel y. -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH3CFGR2 -+ DFSDM_CH3CFGR2 -+ This register specifies the parameters used by channel y. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH3AWSCDR -+ DFSDM_CH3AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH3WDATR -+ DFSDM_CH3WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0x6C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH3DATINR -+ DFSDM_CH3DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH3DLYR -+ DFSDM_CH3DLYR -+ DFSDM channel 3 delay register -+ 0x74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH4CFGR1 -+ DFSDM_CH4CFGR1 -+ This register specifies the parameters used by channel y. -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH4CFGR2 -+ DFSDM_CH4CFGR2 -+ This register specifies the parameters used by channel y. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH4AWSCDR -+ DFSDM_CH4AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH4WDATR -+ DFSDM_CH4WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0x8C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH4DATINR -+ DFSDM_CH4DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH4DLYR -+ DFSDM_CH4DLYR -+ DFSDM channel 4 delay register -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH5CFGR1 -+ DFSDM_CH5CFGR1 -+ This register specifies the parameters used by channel y. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH5CFGR2 -+ DFSDM_CH5CFGR2 -+ This register specifies the parameters used by channel y. -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH5AWSCDR -+ DFSDM_CH5AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH5WDATR -+ DFSDM_CH5WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0xAC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH5DATINR -+ DFSDM_CH5DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH5DLYR -+ DFSDM_CH5DLYR -+ DFSDM channel 5 delay register -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH6CFGR1 -+ DFSDM_CH6CFGR1 -+ This register specifies the parameters used by channel y. -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH6CFGR2 -+ DFSDM_CH6CFGR2 -+ This register specifies the parameters used by channel y. -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH6AWSCDR -+ DFSDM_CH6AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH6WDATR -+ DFSDM_CH6WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0xCC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH6DATINR -+ DFSDM_CH6DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH6DLYR -+ DFSDM_CH6DLYR -+ DFSDM channel 6 delay register -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_CH7CFGR1 -+ DFSDM_CH7CFGR1 -+ This register specifies the parameters used by channel y. -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SITP -+ SITP -+ 0 -+ 2 -+ -+ -+ SPICKSEL -+ SPICKSEL -+ 2 -+ 2 -+ -+ -+ SCDEN -+ SCDEN -+ 5 -+ 1 -+ -+ -+ CKABEN -+ CKABEN -+ 6 -+ 1 -+ -+ -+ CHEN -+ CHEN -+ 7 -+ 1 -+ -+ -+ CHINSEL -+ CHINSEL -+ 8 -+ 1 -+ -+ -+ DATMPX -+ DATMPX -+ 12 -+ 2 -+ -+ -+ DATPACK -+ DATPACK -+ 14 -+ 2 -+ -+ -+ CKOUTDIV -+ CKOUTDIV -+ 16 -+ 8 -+ -+ -+ CKOUTSRC -+ CKOUTSRC -+ 30 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ DFSDM_CH7CFGR2 -+ DFSDM_CH7CFGR2 -+ This register specifies the parameters used by channel y. -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTRBS -+ DTRBS -+ 3 -+ 5 -+ -+ -+ OFFSET -+ OFFSET -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_CH7AWSCDR -+ DFSDM_CH7AWSCDR -+ Short-circuit detector and analog watchdog settings for channel y. -+ 0xE8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCDT -+ SCDT -+ 0 -+ 8 -+ -+ -+ BKSCD -+ BKSCD -+ 12 -+ 4 -+ -+ -+ AWFOSR -+ AWFOSR -+ 16 -+ 5 -+ -+ -+ AWFORD -+ AWFORD -+ 22 -+ 2 -+ -+ -+ -+ -+ DFSDM_CH7WDATR -+ DFSDM_CH7WDATR -+ This register contains the data resulting from the analog watchdog filter associated to the input channel y. -+ 0xEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WDATA -+ WDATA -+ 0 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH7DATINR -+ DFSDM_CH7DATINR -+ This register contains 16-bit input data to be processed by DFSDM filter module. -+ 0xF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INDAT0 -+ INDAT0 -+ 0 -+ 16 -+ -+ -+ INDAT1 -+ INDAT1 -+ 16 -+ 16 -+ -+ -+ -+ -+ DFSDM_CH7DLYR -+ DFSDM_CH7DLYR -+ DFSDM channel 7 delay register -+ 0xF4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLSSKP -+ PLSSKP -+ 0 -+ 6 -+ -+ -+ -+ -+ DFSDM_FLT0CR1 -+ DFSDM_FLT0CR1 -+ DFSDM filter 0 control register 1 -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT0CR2 -+ DFSDM_FLT0CR2 -+ DFSDM filter 0 control register 2 -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0ISR -+ DFSDM_FLT0ISR -+ DFSDM filter 0 interrupt and status register -+ 0x108 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0ICR -+ DFSDM_FLT0ICR -+ DFSDM filter 0 interrupt flag clear register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0JCHGR -+ DFSDM_FLT0JCHGR -+ DFSDM filter 0 injected channel group selection register -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0FCR -+ DFSDM_FLT0FCR -+ DFSDM filter 0 control register -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT0JDATAR -+ DFSDM_FLT0JDATAR -+ DFSDM filter 0 data register for injected group -+ 0x118 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT0RDATAR -+ DFSDM_FLT0RDATAR -+ DFSDM filter 0 data register for the regular channel -+ 0x11C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT0AWHTR -+ DFSDM_FLT0AWHTR -+ DFSDM filter 0 analog watchdog high threshold register -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT0AWLTR -+ DFSDM_FLT0AWLTR -+ DFSDM filter 0 analog watchdog low threshold register -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT0AWSR -+ DFSDM_FLT0AWSR -+ DFSDM filter 0 analog watchdog status register -+ 0x128 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0AWCFR -+ DFSDM_FLT0AWCFR -+ DFSDM filter 0 analog watchdog clear flag register -+ 0x12C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT0EXMAX -+ DFSDM_FLT0EXMAX -+ DFSDM filter 0 extremes detector maximum register -+ 0x130 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT0EXMIN -+ DFSDM_FLT0EXMIN -+ DFSDM filter 0 extremes detector minimum register -+ 0x134 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT0CNVTIMR -+ DFSDM_FLT0CNVTIMR -+ DFSDM filter 0 conversion timer register -+ 0x138 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_FLT1CR1 -+ DFSDM_FLT1CR1 -+ DFSDM filter 1 control register 1 -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT1CR2 -+ DFSDM_FLT1CR2 -+ DFSDM filter 1 control register 2 -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1ISR -+ DFSDM_FLT1ISR -+ DFSDM filter 1 interrupt and status register -+ 0x188 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1ICR -+ DFSDM_FLT1ICR -+ DFSDM filter 1 interrupt flag clear register -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1JCHGR -+ DFSDM_FLT1JCHGR -+ DFSDM filter 1 injected channel group selection register -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1FCR -+ DFSDM_FLT1FCR -+ DFSDM filter 1 control register -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT1JDATAR -+ DFSDM_FLT1JDATAR -+ DFSDM filter 1 data register for injected group -+ 0x198 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT1RDATAR -+ DFSDM_FLT1RDATAR -+ DFSDM filter 1 data register for the regular channel -+ 0x19C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT1AWHTR -+ DFSDM_FLT1AWHTR -+ DFSDM filter 1 analog watchdog high threshold register -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT1AWLTR -+ DFSDM_FLT1AWLTR -+ DFSDM filter 1 analog watchdog low threshold register -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT1AWSR -+ DFSDM_FLT1AWSR -+ DFSDM filter 1 analog watchdog status register -+ 0x1A8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1AWCFR -+ DFSDM_FLT1AWCFR -+ DFSDM filter 1 analog watchdog clear flag register -+ 0x1AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT1EXMAX -+ DFSDM_FLT1EXMAX -+ DFSDM filter 1 extremes detector maximum register -+ 0x1B0 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT1EXMIN -+ DFSDM_FLT1EXMIN -+ DFSDM filter 1 extremes detector minimum register -+ 0x1B4 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT1CNVTIMR -+ DFSDM_FLT1CNVTIMR -+ DFSDM filter 1 conversion timer register -+ 0x1B8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_FLT2CR1 -+ DFSDM_FLT2CR1 -+ DFSDM filter 2 control register 1 -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT2CR2 -+ DFSDM_FLT2CR2 -+ DFSDM filter 2 control register 2 -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2ISR -+ DFSDM_FLT2ISR -+ DFSDM filter 2 interrupt and status register -+ 0x208 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2ICR -+ DFSDM_FLT2ICR -+ DFSDM filter 2 interrupt flag clear register -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2JCHGR -+ DFSDM_FLT2JCHGR -+ DFSDM filter 2 injected channel group selection register -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2FCR -+ DFSDM_FLT2FCR -+ DFSDM filter 2 control register -+ 0x214 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT2JDATAR -+ DFSDM_FLT2JDATAR -+ DFSDM filter 2 data register for injected group -+ 0x218 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT2RDATAR -+ DFSDM_FLT2RDATAR -+ DFSDM filter 2 data register for the regular channel -+ 0x21C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT2AWHTR -+ DFSDM_FLT2AWHTR -+ DFSDM filter 2 analog watchdog high threshold register -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT2AWLTR -+ DFSDM_FLT2AWLTR -+ DFSDM filter 2 analog watchdog low threshold register -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT2AWSR -+ DFSDM_FLT2AWSR -+ DFSDM filter 2 analog watchdog status register -+ 0x228 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2AWCFR -+ DFSDM_FLT2AWCFR -+ DFSDM filter 2 analog watchdog clear flag register -+ 0x22C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT2EXMAX -+ DFSDM_FLT2EXMAX -+ DFSDM filter 2 extremes detector maximum register -+ 0x230 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT2EXMIN -+ DFSDM_FLT2EXMIN -+ DFSDM filter 2 extremes detector minimum register -+ 0x234 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT2CNVTIMR -+ DFSDM_FLT2CNVTIMR -+ DFSDM filter 2 conversion timer register -+ 0x238 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_FLT3CR1 -+ DFSDM_FLT3CR1 -+ DFSDM filter 3 control register 1 -+ 0x280 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT3CR2 -+ DFSDM_FLT3CR2 -+ DFSDM filter 3 control register 2 -+ 0x284 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3ISR -+ DFSDM_FLT3ISR -+ DFSDM filter 3 interrupt and status register -+ 0x288 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3ICR -+ DFSDM_FLT3ICR -+ DFSDM filter 3 interrupt flag clear register -+ 0x28C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3JCHGR -+ DFSDM_FLT3JCHGR -+ DFSDM filter 3 injected channel group selection register -+ 0x290 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3FCR -+ DFSDM_FLT3FCR -+ DFSDM filter 3 control register -+ 0x294 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT3JDATAR -+ DFSDM_FLT3JDATAR -+ DFSDM filter 3 data register for injected group -+ 0x298 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT3RDATAR -+ DFSDM_FLT3RDATAR -+ DFSDM filter 3 data register for the regular channel -+ 0x29C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT3AWHTR -+ DFSDM_FLT3AWHTR -+ DFSDM filter 3 analog watchdog high threshold register -+ 0x2A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT3AWLTR -+ DFSDM_FLT3AWLTR -+ DFSDM filter 3 analog watchdog low threshold register -+ 0x2A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT3AWSR -+ DFSDM_FLT3AWSR -+ DFSDM filter 3 analog watchdog status register -+ 0x2A8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3AWCFR -+ DFSDM_FLT3AWCFR -+ DFSDM filter 3 analog watchdog clear flag register -+ 0x2AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT3EXMAX -+ DFSDM_FLT3EXMAX -+ DFSDM filter 3 extremes detector maximum register -+ 0x2B0 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT3EXMIN -+ DFSDM_FLT3EXMIN -+ DFSDM filter 3 extremes detector minimum register -+ 0x2B4 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT3CNVTIMR -+ DFSDM_FLT3CNVTIMR -+ DFSDM filter 3 conversion timer register -+ 0x2B8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_FLT4CR1 -+ DFSDM_FLT4CR1 -+ DFSDM filter 4 control register 1 -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT4CR2 -+ DFSDM_FLT4CR2 -+ DFSDM filter 4 control register 2 -+ 0x304 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4ISR -+ DFSDM_FLT4ISR -+ DFSDM filter 4 interrupt and status register -+ 0x308 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4ICR -+ DFSDM_FLT4ICR -+ DFSDM filter 4 interrupt flag clear register -+ 0x30C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4JCHGR -+ DFSDM_FLT4JCHGR -+ DFSDM filter 4 injected channel group selection register -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4FCR -+ DFSDM_FLT4FCR -+ DFSDM filter 4 control register -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT4JDATAR -+ DFSDM_FLT4JDATAR -+ DFSDM filter 4 data register for injected group -+ 0x318 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT4RDATAR -+ DFSDM_FLT4RDATAR -+ DFSDM filter 4 data register for the regular channel -+ 0x31C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT4AWHTR -+ DFSDM_FLT4AWHTR -+ DFSDM filter 4 analog watchdog high threshold register -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT4AWLTR -+ DFSDM_FLT4AWLTR -+ DFSDM filter 4 analog watchdog low threshold register -+ 0x324 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT4AWSR -+ DFSDM_FLT4AWSR -+ DFSDM filter 4 analog watchdog status register -+ 0x328 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4AWCFR -+ DFSDM_FLT4AWCFR -+ DFSDM filter 4 analog watchdog clear flag register -+ 0x32C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT4EXMAX -+ DFSDM_FLT4EXMAX -+ DFSDM filter 4 extremes detector maximum register -+ 0x330 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT4EXMIN -+ DFSDM_FLT4EXMIN -+ DFSDM filter 4 extremes detector minimum register -+ 0x334 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT4CNVTIMR -+ DFSDM_FLT4CNVTIMR -+ DFSDM filter 4 conversion timer register -+ 0x338 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_FLT5CR1 -+ DFSDM_FLT5CR1 -+ DFSDM filter 5 control register 1 -+ 0x380 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DFEN -+ DFEN -+ 0 -+ 1 -+ -+ -+ JSWSTART -+ JSWSTART -+ 1 -+ 1 -+ -+ -+ JSYNC -+ JSYNC -+ 3 -+ 1 -+ -+ -+ JSCAN -+ JSCAN -+ 4 -+ 1 -+ -+ -+ JDMAEN -+ JDMAEN -+ 5 -+ 1 -+ -+ -+ JEXTSEL -+ JEXTSEL -+ 8 -+ 5 -+ -+ -+ JEXTEN -+ JEXTEN -+ 13 -+ 2 -+ -+ -+ RSWSTART -+ RSWSTART -+ 17 -+ 1 -+ -+ -+ RCONT -+ RCONT -+ 18 -+ 1 -+ -+ -+ RSYNC -+ RSYNC -+ 19 -+ 1 -+ -+ -+ RDMAEN -+ RDMAEN -+ 21 -+ 1 -+ -+ -+ RCH -+ RCH -+ 24 -+ 3 -+ -+ -+ FAST -+ FAST -+ 29 -+ 1 -+ -+ -+ AWFSEL -+ AWFSEL -+ 30 -+ 1 -+ -+ -+ -+ -+ DFSDM_FLT5CR2 -+ DFSDM_FLT5CR2 -+ DFSDM filter 5 control register 2 -+ 0x384 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ JEOCIE -+ JEOCIE -+ 0 -+ 1 -+ -+ -+ REOCIE -+ REOCIE -+ 1 -+ 1 -+ -+ -+ JOVRIE -+ JOVRIE -+ 2 -+ 1 -+ -+ -+ ROVRIE -+ ROVRIE -+ 3 -+ 1 -+ -+ -+ AWDIE -+ AWDIE -+ 4 -+ 1 -+ -+ -+ SCDIE -+ SCDIE -+ 5 -+ 1 -+ -+ -+ CKABIE -+ CKABIE -+ 6 -+ 1 -+ -+ -+ EXCH -+ EXCH -+ 8 -+ 8 -+ -+ -+ AWDCH -+ AWDCH -+ 16 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5ISR -+ DFSDM_FLT5ISR -+ DFSDM filter 5 interrupt and status register -+ 0x388 -+ 0x20 -+ read-only -+ 0x00FF0000 -+ -+ -+ JEOCF -+ JEOCF -+ 0 -+ 1 -+ -+ -+ REOCF -+ REOCF -+ 1 -+ 1 -+ -+ -+ JOVRF -+ JOVRF -+ 2 -+ 1 -+ -+ -+ ROVRF -+ ROVRF -+ 3 -+ 1 -+ -+ -+ AWDF -+ AWDF -+ 4 -+ 1 -+ -+ -+ JCIP -+ JCIP -+ 13 -+ 1 -+ -+ -+ RCIP -+ RCIP -+ 14 -+ 1 -+ -+ -+ CKABF -+ CKABF -+ 16 -+ 8 -+ -+ -+ SCDF -+ SCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5ICR -+ DFSDM_FLT5ICR -+ DFSDM filter 5 interrupt flag clear register -+ 0x38C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRJOVRF -+ CLRJOVRF -+ 2 -+ 1 -+ -+ -+ CLRROVRF -+ CLRROVRF -+ 3 -+ 1 -+ -+ -+ CLRCKABF -+ CLRCKABF -+ 16 -+ 8 -+ -+ -+ CLRSCDF -+ CLRSCDF -+ 24 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5JCHGR -+ DFSDM_FLT5JCHGR -+ DFSDM filter 5 injected channel group selection register -+ 0x390 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ JCHG -+ JCHG -+ 0 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5FCR -+ DFSDM_FLT5FCR -+ DFSDM filter 5 control register -+ 0x394 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IOSR -+ IOSR -+ 0 -+ 8 -+ -+ -+ FOSR -+ FOSR -+ 16 -+ 10 -+ -+ -+ FORD -+ FORD -+ 29 -+ 3 -+ -+ -+ -+ -+ DFSDM_FLT5JDATAR -+ DFSDM_FLT5JDATAR -+ DFSDM filter 5 data register for injected group -+ 0x398 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ JDATACH -+ JDATACH -+ 0 -+ 3 -+ -+ -+ JDATA -+ JDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT5RDATAR -+ DFSDM_FLT5RDATAR -+ DFSDM filter 5 data register for the regular channel -+ 0x39C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDATACH -+ RDATACH -+ 0 -+ 3 -+ -+ -+ RPEND -+ RPEND -+ 4 -+ 1 -+ -+ -+ RDATA -+ RDATA -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT5AWHTR -+ DFSDM_FLT5AWHTR -+ DFSDM filter 5 analog watchdog high threshold register -+ 0x3A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWH -+ BKAWH -+ 0 -+ 4 -+ -+ -+ AWHT -+ AWHT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT5AWLTR -+ DFSDM_FLT5AWLTR -+ DFSDM filter 5 analog watchdog low threshold register -+ 0x3A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKAWL -+ BKAWL -+ 0 -+ 4 -+ -+ -+ AWLT -+ AWLT -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT5AWSR -+ DFSDM_FLT5AWSR -+ DFSDM filter 5 analog watchdog status register -+ 0x3A8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AWLTF -+ AWLTF -+ 0 -+ 8 -+ -+ -+ AWHTF -+ AWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5AWCFR -+ DFSDM_FLT5AWCFR -+ DFSDM filter 5 analog watchdog clear flag register -+ 0x3AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRAWLTF -+ CLRAWLTF -+ 0 -+ 8 -+ -+ -+ CLRAWHTF -+ CLRAWHTF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_FLT5EXMAX -+ DFSDM_FLT5EXMAX -+ DFSDM filter 5 extremes detector maximum register -+ 0x3B0 -+ 0x20 -+ read-only -+ 0x80000000 -+ -+ -+ EXMAXCH -+ EXMAXCH -+ 0 -+ 3 -+ -+ -+ EXMAX -+ EXMAX -+ 8 -+ 24 -+ -+ -+ -+ -+ DFSDM_FLT5EXMIN -+ DFSDM_FLT5EXMIN -+ DFSDM filter 5 extremes detector minimum register -+ 0x3B4 -+ 0x20 -+ 0x7FFFFF00 -+ -+ -+ EXMINCH -+ EXMINCH -+ 0 -+ 3 -+ read-only -+ -+ -+ EXMIN -+ EXMIN -+ 8 -+ 24 -+ read-write -+ -+ -+ -+ -+ DFSDM_FLT5CNVTIMR -+ DFSDM_FLT5CNVTIMR -+ DFSDM filter 5 conversion timer register -+ 0x3B8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNVCNT -+ CNVCNT -+ 4 -+ 28 -+ -+ -+ -+ -+ DFSDM_HWCFGR -+ DFSDM_HWCFGR -+ This register specifies the hardware configuration of DFSDM peripheral. -+ 0x7F0 -+ 0x20 -+ read-only -+ 0x00000608 -+ -+ -+ NBT -+ NBT -+ 0 -+ 8 -+ -+ -+ NBF -+ NBF -+ 8 -+ 8 -+ -+ -+ -+ -+ DFSDM_VERR -+ DFSDM_VERR -+ This register specifies the version of DFSDM peripheral. -+ 0x7F4 -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DFSDM_IPIDR -+ DFSDM_IPIDR -+ This register specifies the identification of DFSDM peripheral. -+ 0x7F8 -+ 0x20 -+ read-only -+ 0x00110031 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DFSDM_SIDR -+ DFSDM_SIDR -+ This register specifies the size allocated to DFSDM registers. -+ 0x7FC -+ 0x20 -+ read-only -+ 0xA3C5DD02 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DMA1 -+ DMA1 -+ DMA1 -+ 0x48000000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DMA_LISR -+ DMA_LISR -+ DMA low interrupt status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ FEIF0 -+ FEIF0 -+ 0 -+ 1 -+ -+ -+ DMEIF0 -+ DMEIF0 -+ 2 -+ 1 -+ -+ -+ TEIF0 -+ TEIF0 -+ 3 -+ 1 -+ -+ -+ HTIF0 -+ HTIF0 -+ 4 -+ 1 -+ -+ -+ TCIF0 -+ TCIF0 -+ 5 -+ 1 -+ -+ -+ FEIF1 -+ FEIF1 -+ 6 -+ 1 -+ -+ -+ DMEIF1 -+ DMEIF1 -+ 8 -+ 1 -+ -+ -+ TEIF1 -+ TEIF1 -+ 9 -+ 1 -+ -+ -+ HTIF1 -+ HTIF1 -+ 10 -+ 1 -+ -+ -+ TCIF1 -+ TCIF1 -+ 11 -+ 1 -+ -+ -+ FEIF2 -+ FEIF2 -+ 16 -+ 1 -+ -+ -+ DMEIF2 -+ DMEIF2 -+ 18 -+ 1 -+ -+ -+ TEIF2 -+ TEIF2 -+ 19 -+ 1 -+ -+ -+ HTIF2 -+ HTIF2 -+ 20 -+ 1 -+ -+ -+ TCIF2 -+ TCIF2 -+ 21 -+ 1 -+ -+ -+ FEIF3 -+ FEIF3 -+ 22 -+ 1 -+ -+ -+ DMEIF3 -+ DMEIF3 -+ 24 -+ 1 -+ -+ -+ TEIF3 -+ TEIF3 -+ 25 -+ 1 -+ -+ -+ HTIF3 -+ HTIF3 -+ 26 -+ 1 -+ -+ -+ TCIF3 -+ TCIF3 -+ 27 -+ 1 -+ -+ -+ -+ -+ DMA_HISR -+ DMA_HISR -+ DMA high interrupt status register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ FEIF4 -+ FEIF4 -+ 0 -+ 1 -+ -+ -+ DMEIF4 -+ DMEIF4 -+ 2 -+ 1 -+ -+ -+ TEIF4 -+ TEIF4 -+ 3 -+ 1 -+ -+ -+ HTIF4 -+ HTIF4 -+ 4 -+ 1 -+ -+ -+ TCIF4 -+ TCIF4 -+ 5 -+ 1 -+ -+ -+ FEIF5 -+ FEIF5 -+ 6 -+ 1 -+ -+ -+ DMEIF5 -+ DMEIF5 -+ 8 -+ 1 -+ -+ -+ TEIF5 -+ TEIF5 -+ 9 -+ 1 -+ -+ -+ HTIF5 -+ HTIF5 -+ 10 -+ 1 -+ -+ -+ TCIF5 -+ TCIF5 -+ 11 -+ 1 -+ -+ -+ FEIF6 -+ FEIF6 -+ 16 -+ 1 -+ -+ -+ DMEIF6 -+ DMEIF6 -+ 18 -+ 1 -+ -+ -+ TEIF6 -+ TEIF6 -+ 19 -+ 1 -+ -+ -+ HTIF6 -+ HTIF6 -+ 20 -+ 1 -+ -+ -+ TCIF6 -+ TCIF6 -+ 21 -+ 1 -+ -+ -+ FEIF7 -+ FEIF7 -+ 22 -+ 1 -+ -+ -+ DMEIF7 -+ DMEIF7 -+ 24 -+ 1 -+ -+ -+ TEIF7 -+ TEIF7 -+ 25 -+ 1 -+ -+ -+ HTIF7 -+ HTIF7 -+ 26 -+ 1 -+ -+ -+ TCIF7 -+ TCIF7 -+ 27 -+ 1 -+ -+ -+ -+ -+ DMA_LIFCR -+ DMA_LIFCR -+ DMA low interrupt flag clear register -+ 0x8 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CFEIF0 -+ CFEIF0 -+ 0 -+ 1 -+ -+ -+ CDMEIF0 -+ CDMEIF0 -+ 2 -+ 1 -+ -+ -+ CTEIF0 -+ CTEIF0 -+ 3 -+ 1 -+ -+ -+ CHTIF0 -+ CHTIF0 -+ 4 -+ 1 -+ -+ -+ CTCIF0 -+ CTCIF0 -+ 5 -+ 1 -+ -+ -+ CFEIF1 -+ CFEIF1 -+ 6 -+ 1 -+ -+ -+ CDMEIF1 -+ CDMEIF1 -+ 8 -+ 1 -+ -+ -+ CTEIF1 -+ CTEIF1 -+ 9 -+ 1 -+ -+ -+ CHTIF1 -+ CHTIF1 -+ 10 -+ 1 -+ -+ -+ CTCIF1 -+ CTCIF1 -+ 11 -+ 1 -+ -+ -+ CFEIF2 -+ CFEIF2 -+ 16 -+ 1 -+ -+ -+ CDMEIF2 -+ CDMEIF2 -+ 18 -+ 1 -+ -+ -+ CTEIF2 -+ CTEIF2 -+ 19 -+ 1 -+ -+ -+ CHTIF2 -+ CHTIF2 -+ 20 -+ 1 -+ -+ -+ CTCIF2 -+ CTCIF2 -+ 21 -+ 1 -+ -+ -+ CFEIF3 -+ CFEIF3 -+ 22 -+ 1 -+ -+ -+ CDMEIF3 -+ CDMEIF3 -+ 24 -+ 1 -+ -+ -+ CTEIF3 -+ CTEIF3 -+ 25 -+ 1 -+ -+ -+ CHTIF3 -+ CHTIF3 -+ 26 -+ 1 -+ -+ -+ CTCIF3 -+ CTCIF3 -+ 27 -+ 1 -+ -+ -+ -+ -+ DMA_HIFCR -+ DMA_HIFCR -+ DMA high interrupt flag clear register -+ 0xC -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CFEIF4 -+ CFEIF4 -+ 0 -+ 1 -+ -+ -+ CDMEIF4 -+ CDMEIF4 -+ 2 -+ 1 -+ -+ -+ CTEIF4 -+ CTEIF4 -+ 3 -+ 1 -+ -+ -+ CHTIF4 -+ CHTIF4 -+ 4 -+ 1 -+ -+ -+ CTCIF4 -+ CTCIF4 -+ 5 -+ 1 -+ -+ -+ CFEIF5 -+ CFEIF5 -+ 6 -+ 1 -+ -+ -+ CDMEIF5 -+ CDMEIF5 -+ 8 -+ 1 -+ -+ -+ CTEIF5 -+ CTEIF5 -+ 9 -+ 1 -+ -+ -+ CHTIF5 -+ CHTIF5 -+ 10 -+ 1 -+ -+ -+ CTCIF5 -+ CTCIF5 -+ 11 -+ 1 -+ -+ -+ CFEIF6 -+ CFEIF6 -+ 16 -+ 1 -+ -+ -+ CDMEIF6 -+ CDMEIF6 -+ 18 -+ 1 -+ -+ -+ CTEIF6 -+ CTEIF6 -+ 19 -+ 1 -+ -+ -+ CHTIF6 -+ CHTIF6 -+ 20 -+ 1 -+ -+ -+ CTCIF6 -+ CTCIF6 -+ 21 -+ 1 -+ -+ -+ CFEIF7 -+ CFEIF7 -+ 22 -+ 1 -+ -+ -+ CDMEIF7 -+ CDMEIF7 -+ 24 -+ 1 -+ -+ -+ CTEIF7 -+ CTEIF7 -+ 25 -+ 1 -+ -+ -+ CHTIF7 -+ CHTIF7 -+ 26 -+ 1 -+ -+ -+ CTCIF7 -+ CTCIF7 -+ 27 -+ 1 -+ -+ -+ -+ -+ DMA_S0CR -+ DMA_S0CR -+ This register is used to configure the concerned stream. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S0NDTR -+ DMA_S0NDTR -+ DMA stream 0 number of data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S0PAR -+ DMA_S0PAR -+ DMA stream 0 peripheral address register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S0M0AR -+ DMA_S0M0AR -+ DMA stream 0 memory 0 address register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S0M1AR -+ DMA_S0M1AR -+ DMA stream 0 memory 1 address register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S0FCR -+ DMA_S0FCR -+ DMA stream 0 FIFO control register -+ 0x24 -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S1CR -+ DMA_S1CR -+ This register is used to configure the concerned stream. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S1NDTR -+ DMA_S1NDTR -+ DMA stream 1 number of data register -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S1PAR -+ DMA_S1PAR -+ DMA stream 1 peripheral address register -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S1M0AR -+ DMA_S1M0AR -+ DMA stream 1 memory 0 address register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S1M1AR -+ DMA_S1M1AR -+ DMA stream 1 memory 1 address register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S1FCR -+ DMA_S1FCR -+ DMA stream 1 FIFO control register -+ 0x3C -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S2CR -+ DMA_S2CR -+ This register is used to configure the concerned stream. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S2NDTR -+ DMA_S2NDTR -+ DMA stream 2 number of data register -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S2PAR -+ DMA_S2PAR -+ DMA stream 2 peripheral address register -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S2M0AR -+ DMA_S2M0AR -+ DMA stream 2 memory 0 address register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S2M1AR -+ DMA_S2M1AR -+ DMA stream 2 memory 1 address register -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S2FCR -+ DMA_S2FCR -+ DMA stream 2 FIFO control register -+ 0x54 -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S3CR -+ DMA_S3CR -+ This register is used to configure the concerned stream. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S3NDTR -+ DMA_S3NDTR -+ DMA stream 3 number of data register -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S3PAR -+ DMA_S3PAR -+ DMA stream 3 peripheral address register -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S3M0AR -+ DMA_S3M0AR -+ DMA stream 3 memory 0 address register -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S3M1AR -+ DMA_S3M1AR -+ DMA stream 3 memory 1 address register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S3FCR -+ DMA_S3FCR -+ DMA stream 3 FIFO control register -+ 0x6C -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S4CR -+ DMA_S4CR -+ This register is used to configure the concerned stream. -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S4NDTR -+ DMA_S4NDTR -+ DMA stream 4 number of data register -+ 0x74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S4PAR -+ DMA_S4PAR -+ DMA stream 4 peripheral address register -+ 0x78 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S4M0AR -+ DMA_S4M0AR -+ DMA stream 4 memory 0 address register -+ 0x7C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S4M1AR -+ DMA_S4M1AR -+ DMA stream 4 memory 1 address register -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S4FCR -+ DMA_S4FCR -+ DMA stream 4 FIFO control register -+ 0x84 -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S5CR -+ DMA_S5CR -+ This register is used to configure the concerned stream. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S5NDTR -+ DMA_S5NDTR -+ DMA stream 5 number of data register -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S5PAR -+ DMA_S5PAR -+ DMA stream 5 peripheral address register -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S5M0AR -+ DMA_S5M0AR -+ DMA stream 5 memory 0 address register -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S5M1AR -+ DMA_S5M1AR -+ DMA stream 5 memory 1 address register -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S5FCR -+ DMA_S5FCR -+ DMA stream 5 FIFO control register -+ 0x9C -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S6CR -+ DMA_S6CR -+ This register is used to configure the concerned stream. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S6NDTR -+ DMA_S6NDTR -+ DMA stream 6 number of data register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S6PAR -+ DMA_S6PAR -+ DMA stream 6 peripheral address register -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S6M0AR -+ DMA_S6M0AR -+ DMA stream 6 memory 0 address register -+ 0xAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S6M1AR -+ DMA_S6M1AR -+ DMA stream 6 memory 1 address register -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S6FCR -+ DMA_S6FCR -+ DMA stream 6 FIFO control register -+ 0xB4 -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_S7CR -+ DMA_S7CR -+ This register is used to configure the concerned stream. -+ 0xB8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ DMEIE -+ DMEIE -+ 1 -+ 1 -+ -+ -+ TEIE -+ TEIE -+ 2 -+ 1 -+ -+ -+ HTIE -+ HTIE -+ 3 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 4 -+ 1 -+ -+ -+ PFCTRL -+ PFCTRL -+ 5 -+ 1 -+ -+ -+ DIR -+ DIR -+ 6 -+ 2 -+ -+ -+ CIRC -+ CIRC -+ 8 -+ 1 -+ -+ -+ PINC -+ PINC -+ 9 -+ 1 -+ -+ -+ MINC -+ MINC -+ 10 -+ 1 -+ -+ -+ PSIZE -+ PSIZE -+ 11 -+ 2 -+ -+ -+ MSIZE -+ MSIZE -+ 13 -+ 2 -+ -+ -+ PINCOS -+ PINCOS -+ 15 -+ 1 -+ -+ -+ PL -+ PL -+ 16 -+ 2 -+ -+ -+ DBM -+ DBM -+ 18 -+ 1 -+ -+ -+ CT -+ CT -+ 19 -+ 1 -+ -+ -+ PBURST -+ PBURST -+ 21 -+ 2 -+ -+ -+ MBURST -+ MBURST -+ 23 -+ 2 -+ -+ -+ -+ -+ DMA_S7NDTR -+ DMA_S7NDTR -+ DMA stream 7 number of data register -+ 0xBC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NDT -+ NDT -+ 0 -+ 16 -+ -+ -+ -+ -+ DMA_S7PAR -+ DMA_S7PAR -+ DMA stream 7 peripheral address register -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PAR -+ PAR -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S7M0AR -+ DMA_S7M0AR -+ DMA stream 7 memory 0 address register -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M0A -+ M0A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S7M1AR -+ DMA_S7M1AR -+ DMA stream 7 memory 1 address register -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ M1A -+ M1A -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_S7FCR -+ DMA_S7FCR -+ DMA stream 7 FIFO control register -+ 0xCC -+ 0x20 -+ 0x00000021 -+ -+ -+ FTH -+ FTH -+ 0 -+ 2 -+ read-write -+ -+ -+ DMDIS -+ DMDIS -+ 2 -+ 1 -+ read-write -+ -+ -+ FS -+ FS -+ 3 -+ 3 -+ read-only -+ -+ -+ FEIE -+ FEIE -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ DMA_HWCFGR2 -+ DMA_HWCFGR2 -+ DMA hardware configuration 2register -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ FIFO_SIZE -+ FIFO_SIZE -+ 0 -+ 2 -+ -+ -+ WRITE_BUFFERABLE -+ WRITE_BUFFERABLE -+ 4 -+ 1 -+ -+ -+ CHSEL_WIDTH -+ CHSEL_WIDTH -+ 8 -+ 3 -+ -+ -+ -+ -+ DMA_HWCFGR1 -+ DMA_HWCFGR1 -+ DMA hardware configuration 1 register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x22222222 -+ -+ -+ DMA_DEF0 -+ DMA_DEF0 -+ 0 -+ 2 -+ -+ -+ DMA_DEF1 -+ DMA_DEF1 -+ 4 -+ 2 -+ -+ -+ DMA_DEF2 -+ DMA_DEF2 -+ 8 -+ 2 -+ -+ -+ DMA_DEF3 -+ DMA_DEF3 -+ 12 -+ 2 -+ -+ -+ DMA_DEF4 -+ DMA_DEF4 -+ 16 -+ 2 -+ -+ -+ DMA_DEF5 -+ DMA_DEF5 -+ 20 -+ 2 -+ -+ -+ DMA_DEF6 -+ DMA_DEF6 -+ 24 -+ 2 -+ -+ -+ DMA_DEF7 -+ DMA_DEF7 -+ 28 -+ 2 -+ -+ -+ -+ -+ DMA_VERR -+ DMA_VERR -+ This register identifies the version of the IP. -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DMA_IPDR -+ DMA_IPDR -+ DMA IP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00100002 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DMA_SIDR -+ DMA_SIDR -+ DMA size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DMA2 -+ 0x48001000 -+ -+ -+ DMAMUX1 -+ DMAMUX1 -+ DMAMUX1 -+ 0x48002000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DMAMUX_C0CR -+ DMAMUX_C0CR -+ DMAMUX request line multiplexer channel 0 configuration register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C1CR -+ DMAMUX_C1CR -+ DMAMUX request line multiplexer channel 1 configuration register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C2CR -+ DMAMUX_C2CR -+ DMAMUX request line multiplexer channel 2 configuration register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C3CR -+ DMAMUX_C3CR -+ DMAMUX request line multiplexer channel 3 configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C4CR -+ DMAMUX_C4CR -+ DMAMUX request line multiplexer channel 4 configuration register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C5CR -+ DMAMUX_C5CR -+ DMAMUX request line multiplexer channel 5 configuration register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C6CR -+ DMAMUX_C6CR -+ DMAMUX request line multiplexer channel 6 configuration register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C7CR -+ DMAMUX_C7CR -+ DMAMUX request line multiplexer channel 7 configuration register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C8CR -+ DMAMUX_C8CR -+ DMAMUX request line multiplexer channel 8 configuration register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C9CR -+ DMAMUX_C9CR -+ DMAMUX request line multiplexer channel 9 configuration register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C10CR -+ DMAMUX_C10CR -+ DMAMUX request line multiplexer channel 10 configuration register -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C11CR -+ DMAMUX_C11CR -+ DMAMUX request line multiplexer channel 11 configuration register -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C12CR -+ DMAMUX_C12CR -+ DMAMUX request line multiplexer channel 12 configuration register -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C13CR -+ DMAMUX_C13CR -+ DMAMUX request line multiplexer channel 13 configuration register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C14CR -+ DMAMUX_C14CR -+ DMAMUX request line multiplexer channel 14 configuration register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_C15CR -+ DMAMUX_C15CR -+ DMAMUX request line multiplexer channel 15 configuration register -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAREQ_ID -+ DMAREQ_ID -+ 0 -+ 7 -+ -+ -+ SOIE -+ SOIE -+ 8 -+ 1 -+ -+ -+ EGE -+ EGE -+ 9 -+ 1 -+ -+ -+ SE -+ SE -+ 16 -+ 1 -+ -+ -+ SPOL -+ SPOL -+ 17 -+ 2 -+ -+ -+ NBREQ -+ NBREQ -+ 19 -+ 5 -+ -+ -+ SYNC_ID -+ SYNC_ID -+ 24 -+ 3 -+ -+ -+ -+ -+ DMAMUX_CSR -+ DMAMUX_CSR -+ DMAMUX request line multiplexer interrupt channel status register -+ 0x80 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SOF0 -+ SOF0 -+ 0 -+ 1 -+ -+ -+ SOF1 -+ SOF1 -+ 1 -+ 1 -+ -+ -+ SOF2 -+ SOF2 -+ 2 -+ 1 -+ -+ -+ SOF3 -+ SOF3 -+ 3 -+ 1 -+ -+ -+ SOF4 -+ SOF4 -+ 4 -+ 1 -+ -+ -+ SOF5 -+ SOF5 -+ 5 -+ 1 -+ -+ -+ SOF6 -+ SOF6 -+ 6 -+ 1 -+ -+ -+ SOF7 -+ SOF7 -+ 7 -+ 1 -+ -+ -+ SOF8 -+ SOF8 -+ 8 -+ 1 -+ -+ -+ SOF9 -+ SOF9 -+ 9 -+ 1 -+ -+ -+ SOF10 -+ SOF10 -+ 10 -+ 1 -+ -+ -+ SOF11 -+ SOF11 -+ 11 -+ 1 -+ -+ -+ SOF12 -+ SOF12 -+ 12 -+ 1 -+ -+ -+ SOF13 -+ SOF13 -+ 13 -+ 1 -+ -+ -+ SOF14 -+ SOF14 -+ 14 -+ 1 -+ -+ -+ SOF15 -+ SOF15 -+ 15 -+ 1 -+ -+ -+ -+ -+ DMAMUX_CFR -+ DMAMUX_CFR -+ DMAMUX request line multiplexer interrupt clear flag register -+ 0x84 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CSOF0 -+ CSOF0 -+ 0 -+ 1 -+ -+ -+ CSOF1 -+ CSOF1 -+ 1 -+ 1 -+ -+ -+ CSOF2 -+ CSOF2 -+ 2 -+ 1 -+ -+ -+ CSOF3 -+ CSOF3 -+ 3 -+ 1 -+ -+ -+ CSOF4 -+ CSOF4 -+ 4 -+ 1 -+ -+ -+ CSOF5 -+ CSOF5 -+ 5 -+ 1 -+ -+ -+ CSOF6 -+ CSOF6 -+ 6 -+ 1 -+ -+ -+ CSOF7 -+ CSOF7 -+ 7 -+ 1 -+ -+ -+ CSOF8 -+ CSOF8 -+ 8 -+ 1 -+ -+ -+ CSOF9 -+ CSOF9 -+ 9 -+ 1 -+ -+ -+ CSOF10 -+ CSOF10 -+ 10 -+ 1 -+ -+ -+ CSOF11 -+ CSOF11 -+ 11 -+ 1 -+ -+ -+ CSOF12 -+ CSOF12 -+ 12 -+ 1 -+ -+ -+ CSOF13 -+ CSOF13 -+ 13 -+ 1 -+ -+ -+ CSOF14 -+ CSOF14 -+ 14 -+ 1 -+ -+ -+ CSOF15 -+ CSOF15 -+ 15 -+ 1 -+ -+ -+ -+ -+ DMAMUX_RG0CR -+ DMAMUX_RG0CR -+ DMAMUX request generator channel 0 configuration register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG1CR -+ DMAMUX_RG1CR -+ DMAMUX request generator channel 1 configuration register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG2CR -+ DMAMUX_RG2CR -+ DMAMUX request generator channel 2 configuration register -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG3CR -+ DMAMUX_RG3CR -+ DMAMUX request generator channel 3 configuration register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG4CR -+ DMAMUX_RG4CR -+ DMAMUX request generator channel 4 configuration register -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG5CR -+ DMAMUX_RG5CR -+ DMAMUX request generator channel 5 configuration register -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG6CR -+ DMAMUX_RG6CR -+ DMAMUX request generator channel 6 configuration register -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RG7CR -+ DMAMUX_RG7CR -+ DMAMUX request generator channel 7 configuration register -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SIG_ID -+ SIG_ID -+ 0 -+ 3 -+ -+ -+ OIE -+ OIE -+ 8 -+ 1 -+ -+ -+ GE -+ GE -+ 16 -+ 1 -+ -+ -+ GPOL -+ GPOL -+ 17 -+ 2 -+ -+ -+ GNBREQ -+ GNBREQ -+ 19 -+ 5 -+ -+ -+ -+ -+ DMAMUX_RGSR -+ DMAMUX_RGSR -+ DMAMUX request generator interrupt status register -+ 0x140 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OF0 -+ OF0 -+ 0 -+ 1 -+ -+ -+ OF1 -+ OF1 -+ 1 -+ 1 -+ -+ -+ OF2 -+ OF2 -+ 2 -+ 1 -+ -+ -+ OF3 -+ OF3 -+ 3 -+ 1 -+ -+ -+ OF4 -+ OF4 -+ 4 -+ 1 -+ -+ -+ OF5 -+ OF5 -+ 5 -+ 1 -+ -+ -+ OF6 -+ OF6 -+ 6 -+ 1 -+ -+ -+ OF7 -+ OF7 -+ 7 -+ 1 -+ -+ -+ -+ -+ DMAMUX_RGCFR -+ DMAMUX_RGCFR -+ DMAMUX request generator interrupt clear flag register -+ 0x144 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ COF0 -+ COF0 -+ 0 -+ 1 -+ -+ -+ COF1 -+ COF1 -+ 1 -+ 1 -+ -+ -+ COF2 -+ COF2 -+ 2 -+ 1 -+ -+ -+ COF3 -+ COF3 -+ 3 -+ 1 -+ -+ -+ COF4 -+ COF4 -+ 4 -+ 1 -+ -+ -+ COF5 -+ COF5 -+ 5 -+ 1 -+ -+ -+ COF6 -+ COF6 -+ 6 -+ 1 -+ -+ -+ COF7 -+ COF7 -+ 7 -+ 1 -+ -+ -+ -+ -+ DMAMUX_HWCFGR2 -+ DMAMUX_HWCFGR2 -+ DMAMUX hardware configuration 2 register -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000008 -+ -+ -+ NUM_DMA_EXT_REQ -+ NUM_DMA_EXT_REQ -+ 0 -+ 8 -+ -+ -+ -+ -+ DMAMUX_HWCFGR1 -+ DMAMUX_HWCFGR1 -+ DMAMUX hardware configuration 1 register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x08086C10 -+ -+ -+ NUM_DMA_STREAMS -+ NUM_DMA_STREAMS -+ 0 -+ 8 -+ -+ -+ NUM_DMA_PERIPH_REQ -+ NUM_DMA_PERIPH_REQ -+ 8 -+ 8 -+ -+ -+ NUM_DMA_TRIG -+ NUM_DMA_TRIG -+ 16 -+ 8 -+ -+ -+ NUM_DMA_REQGEN -+ NUM_DMA_REQGEN -+ 24 -+ 8 -+ -+ -+ -+ -+ DMAMUX_VERR -+ DMAMUX_VERR -+ This register identifies the IP version. -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DMAMUX_IPIDR -+ DMAMUX_IPIDR -+ This register identifies the IP. -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00100011 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DMAMUX_SIDR -+ DMAMUX_SIDR -+ DMAMUX size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DSIHOST1 -+ DSIHOST1 -+ DSIHOST1 -+ 0x5A000000 -+ -+ 0x0 -+ 0x800 -+ registers -+ -+ -+ -+ DSI_VR -+ DSI_VR -+ DSI Host version register -+ 0x0 -+ 0x20 -+ read-only -+ 0x3133312A -+ -+ -+ VERSION -+ VERSION -+ 0 -+ 32 -+ -+ -+ -+ -+ DSI_CR -+ DSI_CR -+ DSI Host control register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ -+ -+ DSI_CCR -+ DSI_CCR -+ DSI Host clock control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXECKDIV -+ TXECKDIV -+ 0 -+ 8 -+ -+ -+ TOCKDIV -+ TOCKDIV -+ 8 -+ 8 -+ -+ -+ -+ -+ DSI_LVCIDR -+ DSI_LVCIDR -+ DSI Host LTDC VCID register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VCID -+ VCID -+ 0 -+ 2 -+ -+ -+ -+ -+ DSI_LCOLCR -+ DSI_LCOLCR -+ DSI Host LTDC color coding register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ COLC -+ COLC -+ 0 -+ 4 -+ -+ -+ LPE -+ LPE -+ 8 -+ 1 -+ -+ -+ -+ -+ DSI_LPCR -+ DSI_LPCR -+ DSI Host LTDC polarity configuration register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DEP -+ DEP -+ 0 -+ 1 -+ -+ -+ VSP -+ VSP -+ 1 -+ 1 -+ -+ -+ HSP -+ HSP -+ 2 -+ 1 -+ -+ -+ -+ -+ DSI_LPMCR -+ DSI_LPMCR -+ DSI Host low-power mode configuration register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VLPSIZE -+ VLPSIZE -+ 0 -+ 8 -+ -+ -+ LPSIZE -+ LPSIZE -+ 16 -+ 8 -+ -+ -+ -+ -+ DSI_PCR -+ DSI_PCR -+ DSI Host protocol configuration register -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ETTXE -+ ETTXE -+ 0 -+ 1 -+ -+ -+ ETRXE -+ ETRXE -+ 1 -+ 1 -+ -+ -+ BTAE -+ BTAE -+ 2 -+ 1 -+ -+ -+ ECCRXE -+ ECCRXE -+ 3 -+ 1 -+ -+ -+ CRCRXE -+ CRCRXE -+ 4 -+ 1 -+ -+ -+ -+ -+ DSI_GVCIDR -+ DSI_GVCIDR -+ DSI Host generic VCID register -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VCID -+ VCID -+ 0 -+ 2 -+ -+ -+ -+ -+ DSI_MCR -+ DSI_MCR -+ DSI Host mode configuration register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ CMDM -+ CMDM -+ 0 -+ 1 -+ -+ -+ -+ -+ DSI_VMCR -+ DSI_VMCR -+ DSI Host video mode configuration register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VMT -+ VMT -+ 0 -+ 2 -+ -+ -+ LPVSAE -+ LPVSAE -+ 8 -+ 1 -+ -+ -+ LPVBPE -+ LPVBPE -+ 9 -+ 1 -+ -+ -+ LPVFPE -+ LPVFPE -+ 10 -+ 1 -+ -+ -+ LPVAE -+ LPVAE -+ 11 -+ 1 -+ -+ -+ LPHBPE -+ LPHBPE -+ 12 -+ 1 -+ -+ -+ LPHFPE -+ LPHFPE -+ 13 -+ 1 -+ -+ -+ FBTAAE -+ FBTAAE -+ 14 -+ 1 -+ -+ -+ LPCE -+ LPCE -+ 15 -+ 1 -+ -+ -+ PGE -+ PGE -+ 16 -+ 1 -+ -+ -+ PGM -+ PGM -+ 20 -+ 1 -+ -+ -+ PGO -+ PGO -+ 24 -+ 1 -+ -+ -+ -+ -+ DSI_VPCR -+ DSI_VPCR -+ DSI Host video packet configuration register -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VPSIZE -+ VPSIZE -+ 0 -+ 14 -+ -+ -+ -+ -+ DSI_VCCR -+ DSI_VCCR -+ DSI Host video chunks configuration register -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NUMC -+ NUMC -+ 0 -+ 13 -+ -+ -+ -+ -+ DSI_VNPCR -+ DSI_VNPCR -+ DSI Host video null packet configuration register -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NPSIZE -+ NPSIZE -+ 0 -+ 13 -+ -+ -+ -+ -+ DSI_VHSACR -+ DSI_VHSACR -+ DSI Host video HSA configuration register -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HSA -+ HSA -+ 0 -+ 12 -+ -+ -+ -+ -+ DSI_VHBPCR -+ DSI_VHBPCR -+ DSI Host video HBP configuration register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HBP -+ HBP -+ 0 -+ 12 -+ -+ -+ -+ -+ DSI_VLCR -+ DSI_VLCR -+ DSI Host video line configuration register -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HLINE -+ HLINE -+ 0 -+ 15 -+ -+ -+ -+ -+ DSI_VVSACR -+ DSI_VVSACR -+ DSI Host video VSA configuration register -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VSA -+ VSA -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVBPCR -+ DSI_VVBPCR -+ DSI Host video VBP configuration register -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VBP -+ VBP -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVFPCR -+ DSI_VVFPCR -+ DSI Host video VFP configuration register -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VFP -+ VFP -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVACR -+ DSI_VVACR -+ DSI Host video VA configuration register -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VA -+ VA -+ 0 -+ 14 -+ -+ -+ -+ -+ DSI_LCCR -+ DSI_LCCR -+ DSI Host LTDC command configuration register -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMDSIZE -+ CMDSIZE -+ 0 -+ 16 -+ -+ -+ -+ -+ DSI_CMCR -+ DSI_CMCR -+ DSI Host command mode configuration register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TEARE -+ TEARE -+ 0 -+ 1 -+ -+ -+ ARE -+ ARE -+ 1 -+ 1 -+ -+ -+ GSW0TX -+ GSW0TX -+ 8 -+ 1 -+ -+ -+ GSW1TX -+ GSW1TX -+ 9 -+ 1 -+ -+ -+ GSW2TX -+ GSW2TX -+ 10 -+ 1 -+ -+ -+ GSR0TX -+ GSR0TX -+ 11 -+ 1 -+ -+ -+ GSR1TX -+ GSR1TX -+ 12 -+ 1 -+ -+ -+ GSR2TX -+ GSR2TX -+ 13 -+ 1 -+ -+ -+ GLWTX -+ GLWTX -+ 14 -+ 1 -+ -+ -+ DSW0TX -+ DSW0TX -+ 16 -+ 1 -+ -+ -+ DSW1TX -+ DSW1TX -+ 17 -+ 1 -+ -+ -+ DSR0TX -+ DSR0TX -+ 18 -+ 1 -+ -+ -+ DLWTX -+ DLWTX -+ 19 -+ 1 -+ -+ -+ MRDPS -+ MRDPS -+ 24 -+ 1 -+ -+ -+ -+ -+ DSI_GHCR -+ DSI_GHCR -+ DSI Host generic header configuration register -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DT -+ DT -+ 0 -+ 6 -+ -+ -+ VCID -+ VCID -+ 6 -+ 2 -+ -+ -+ WCLSB -+ WCLSB -+ 8 -+ 8 -+ -+ -+ WCMSB -+ WCMSB -+ 16 -+ 8 -+ -+ -+ -+ -+ DSI_GPDR -+ DSI_GPDR -+ DSI Host generic payload data register -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA1 -+ DATA1 -+ 0 -+ 8 -+ -+ -+ DATA2 -+ DATA2 -+ 8 -+ 8 -+ -+ -+ DATA3 -+ DATA3 -+ 16 -+ 8 -+ -+ -+ DATA4 -+ DATA4 -+ 24 -+ 8 -+ -+ -+ -+ -+ DSI_GPSR -+ DSI_GPSR -+ DSI Host generic packet status register -+ 0x74 -+ 0x20 -+ read-only -+ 0x00000015 -+ -+ -+ CMDFE -+ CMDFE -+ 0 -+ 1 -+ -+ -+ CMDFF -+ CMDFF -+ 1 -+ 1 -+ -+ -+ PWRFE -+ PWRFE -+ 2 -+ 1 -+ -+ -+ PWRFF -+ PWRFF -+ 3 -+ 1 -+ -+ -+ PRDFE -+ PRDFE -+ 4 -+ 1 -+ -+ -+ PRDFF -+ PRDFF -+ 5 -+ 1 -+ -+ -+ RCB -+ RCB -+ 6 -+ 1 -+ -+ -+ -+ -+ DSI_TCCR0 -+ DSI_TCCR0 -+ DSI Host timeout counter configuration register 0 -+ 0x78 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPRX_TOCNT -+ LPRX_TOCNT -+ 0 -+ 16 -+ -+ -+ HSTX_TOCNT -+ HSTX_TOCNT -+ 16 -+ 16 -+ -+ -+ -+ -+ DSI_TCCR1 -+ DSI_TCCR1 -+ DSI Host timeout counter configuration register 1 -+ 0x7C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HSRD_TOCNT -+ HSRD_TOCNT -+ 0 -+ 16 -+ -+ -+ -+ -+ DSI_TCCR2 -+ DSI_TCCR2 -+ DSI Host timeout counter configuration register 2 -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPRD_TOCNT -+ LPRD_TOCNT -+ 0 -+ 16 -+ -+ -+ -+ -+ DSI_TCCR3 -+ DSI_TCCR3 -+ DSI Host timeout counter configuration register 3 -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HSWR_TOCNT -+ HSWR_TOCNT -+ 0 -+ 16 -+ -+ -+ PM -+ PM -+ 24 -+ 1 -+ -+ -+ -+ -+ DSI_TCCR4 -+ DSI_TCCR4 -+ DSI Host timeout counter configuration register 4 -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPWR_TOCNT -+ LPWR_TOCNT -+ 0 -+ 16 -+ -+ -+ -+ -+ DSI_TCCR5 -+ DSI_TCCR5 -+ DSI Host timeout counter configuration register 5 -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BTA_TOCNT -+ BTA_TOCNT -+ 0 -+ 16 -+ -+ -+ -+ -+ DSI_CLCR -+ DSI_CLCR -+ DSI Host clock lane configuration register -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DPCC -+ DPCC -+ 0 -+ 1 -+ -+ -+ ACR -+ ACR -+ 1 -+ 1 -+ -+ -+ -+ -+ DSI_CLTCR -+ DSI_CLTCR -+ DSI Host clock lane timer configuration register -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LP2HS_TIME -+ LP2HS_TIME -+ 0 -+ 10 -+ -+ -+ HS2LP_TIME -+ HS2LP_TIME -+ 16 -+ 10 -+ -+ -+ -+ -+ DSI_DLTCR -+ DSI_DLTCR -+ DSI Host data lane timer configuration register -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LP2HS_TIME -+ LP2HS_TIME -+ 0 -+ 10 -+ -+ -+ HS2LP_TIME -+ HS2LP_TIME -+ 16 -+ 10 -+ -+ -+ -+ -+ DSI_PCTLR -+ DSI_PCTLR -+ DSI Host PHY control register -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DEN -+ DEN -+ 1 -+ 1 -+ -+ -+ CKE -+ CKE -+ 2 -+ 1 -+ -+ -+ -+ -+ DSI_PCONFR -+ DSI_PCONFR -+ DSI Host PHY configuration register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ NL -+ NL -+ 0 -+ 2 -+ -+ -+ SW_TIME -+ SW_TIME -+ 8 -+ 8 -+ -+ -+ -+ -+ DSI_PUCR -+ DSI_PUCR -+ DSI Host PHY ULPS control register -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ URCL -+ URCL -+ 0 -+ 1 -+ -+ -+ UECL -+ UECL -+ 1 -+ 1 -+ -+ -+ URDL -+ URDL -+ 2 -+ 1 -+ -+ -+ UEDL -+ UEDL -+ 3 -+ 1 -+ -+ -+ -+ -+ DSI_PTTCR -+ DSI_PTTCR -+ DSI Host PHY TX triggers configuration register -+ 0xAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TX_TRIG -+ TX_TRIG -+ 0 -+ 4 -+ -+ -+ -+ -+ DSI_PSR -+ DSI_PSR -+ DSI Host PHY status register -+ 0xB0 -+ 0x20 -+ read-only -+ 0x00001528 -+ -+ -+ PD -+ PD -+ 1 -+ 1 -+ -+ -+ PSSC -+ PSSC -+ 2 -+ 1 -+ -+ -+ UANC -+ UANC -+ 3 -+ 1 -+ -+ -+ PSS0 -+ PSS0 -+ 4 -+ 1 -+ -+ -+ UAN0 -+ UAN0 -+ 5 -+ 1 -+ -+ -+ RUE0 -+ RUE0 -+ 6 -+ 1 -+ -+ -+ PSS1 -+ PSS1 -+ 7 -+ 1 -+ -+ -+ UAN1 -+ UAN1 -+ 8 -+ 1 -+ -+ -+ -+ -+ DSI_ISR0 -+ DSI_ISR0 -+ DSI Host interrupt and status register 0 -+ 0xBC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AE0 -+ AE0 -+ 0 -+ 1 -+ -+ -+ AE1 -+ AE1 -+ 1 -+ 1 -+ -+ -+ AE2 -+ AE2 -+ 2 -+ 1 -+ -+ -+ AE3 -+ AE3 -+ 3 -+ 1 -+ -+ -+ AE4 -+ AE4 -+ 4 -+ 1 -+ -+ -+ AE5 -+ AE5 -+ 5 -+ 1 -+ -+ -+ AE6 -+ AE6 -+ 6 -+ 1 -+ -+ -+ AE7 -+ AE7 -+ 7 -+ 1 -+ -+ -+ AE8 -+ AE8 -+ 8 -+ 1 -+ -+ -+ AE9 -+ AE9 -+ 9 -+ 1 -+ -+ -+ AE10 -+ AE10 -+ 10 -+ 1 -+ -+ -+ AE11 -+ AE11 -+ 11 -+ 1 -+ -+ -+ AE12 -+ AE12 -+ 12 -+ 1 -+ -+ -+ AE13 -+ AE13 -+ 13 -+ 1 -+ -+ -+ AE14 -+ AE14 -+ 14 -+ 1 -+ -+ -+ AE15 -+ AE15 -+ 15 -+ 1 -+ -+ -+ PE0 -+ PE0 -+ 16 -+ 1 -+ -+ -+ PE1 -+ PE1 -+ 17 -+ 1 -+ -+ -+ PE2 -+ PE2 -+ 18 -+ 1 -+ -+ -+ PE3 -+ PE3 -+ 19 -+ 1 -+ -+ -+ PE4 -+ PE4 -+ 20 -+ 1 -+ -+ -+ -+ -+ DSI_ISR1 -+ DSI_ISR1 -+ DSI Host interrupt and status register 1 -+ 0xC0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TOHSTX -+ TOHSTX -+ 0 -+ 1 -+ -+ -+ TOLPRX -+ TOLPRX -+ 1 -+ 1 -+ -+ -+ ECCSE -+ ECCSE -+ 2 -+ 1 -+ -+ -+ ECCME -+ ECCME -+ 3 -+ 1 -+ -+ -+ CRCE -+ CRCE -+ 4 -+ 1 -+ -+ -+ PSE -+ PSE -+ 5 -+ 1 -+ -+ -+ EOTPE -+ EOTPE -+ 6 -+ 1 -+ -+ -+ LPWRE -+ LPWRE -+ 7 -+ 1 -+ -+ -+ GCWRE -+ GCWRE -+ 8 -+ 1 -+ -+ -+ GPWRE -+ GPWRE -+ 9 -+ 1 -+ -+ -+ GPTXE -+ GPTXE -+ 10 -+ 1 -+ -+ -+ GPRDE -+ GPRDE -+ 11 -+ 1 -+ -+ -+ GPRXE -+ GPRXE -+ 12 -+ 1 -+ -+ -+ -+ -+ DSI_IER0 -+ DSI_IER0 -+ DSI Host interrupt enable register 0 -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AE0IE -+ AE0IE -+ 0 -+ 1 -+ -+ -+ AE1IE -+ AE1IE -+ 1 -+ 1 -+ -+ -+ AE2IE -+ AE2IE -+ 2 -+ 1 -+ -+ -+ AE3IE -+ AE3IE -+ 3 -+ 1 -+ -+ -+ AE4IE -+ AE4IE -+ 4 -+ 1 -+ -+ -+ AE5IE -+ AE5IE -+ 5 -+ 1 -+ -+ -+ AE6IE -+ AE6IE -+ 6 -+ 1 -+ -+ -+ AE7IE -+ AE7IE -+ 7 -+ 1 -+ -+ -+ AE8IE -+ AE8IE -+ 8 -+ 1 -+ -+ -+ AE9IE -+ AE9IE -+ 9 -+ 1 -+ -+ -+ AE10IE -+ AE10IE -+ 10 -+ 1 -+ -+ -+ AE11IE -+ AE11IE -+ 11 -+ 1 -+ -+ -+ AE12IE -+ AE12IE -+ 12 -+ 1 -+ -+ -+ AE13IE -+ AE13IE -+ 13 -+ 1 -+ -+ -+ AE14IE -+ AE14IE -+ 14 -+ 1 -+ -+ -+ AE15IE -+ AE15IE -+ 15 -+ 1 -+ -+ -+ PE0IE -+ PE0IE -+ 16 -+ 1 -+ -+ -+ PE1IE -+ PE1IE -+ 17 -+ 1 -+ -+ -+ PE2IE -+ PE2IE -+ 18 -+ 1 -+ -+ -+ PE3IE -+ PE3IE -+ 19 -+ 1 -+ -+ -+ PE4IE -+ PE4IE -+ 20 -+ 1 -+ -+ -+ -+ -+ DSI_IER1 -+ DSI_IER1 -+ DSI Host interrupt enable register 1 -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TOHSTXIE -+ TOHSTXIE -+ 0 -+ 1 -+ -+ -+ TOLPRXIE -+ TOLPRXIE -+ 1 -+ 1 -+ -+ -+ ECCSEIE -+ ECCSEIE -+ 2 -+ 1 -+ -+ -+ ECCMEIE -+ ECCMEIE -+ 3 -+ 1 -+ -+ -+ CRCEIE -+ CRCEIE -+ 4 -+ 1 -+ -+ -+ PSEIE -+ PSEIE -+ 5 -+ 1 -+ -+ -+ EOTPEIE -+ EOTPEIE -+ 6 -+ 1 -+ -+ -+ LPWREIE -+ LPWREIE -+ 7 -+ 1 -+ -+ -+ GCWREIE -+ GCWREIE -+ 8 -+ 1 -+ -+ -+ GPWREIE -+ GPWREIE -+ 9 -+ 1 -+ -+ -+ GPTXEIE -+ GPTXEIE -+ 10 -+ 1 -+ -+ -+ GPRDEIE -+ GPRDEIE -+ 11 -+ 1 -+ -+ -+ GPRXEIE -+ GPRXEIE -+ 12 -+ 1 -+ -+ -+ -+ -+ DSI_FIR0 -+ DSI_FIR0 -+ DSI Host force interrupt register 0 -+ 0xD8 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ FAE0 -+ FAE0 -+ 0 -+ 1 -+ -+ -+ FAE1 -+ FAE1 -+ 1 -+ 1 -+ -+ -+ FAE2 -+ FAE2 -+ 2 -+ 1 -+ -+ -+ FAE3 -+ FAE3 -+ 3 -+ 1 -+ -+ -+ FAE4 -+ FAE4 -+ 4 -+ 1 -+ -+ -+ FAE5 -+ FAE5 -+ 5 -+ 1 -+ -+ -+ FAE6 -+ FAE6 -+ 6 -+ 1 -+ -+ -+ FAE7 -+ FAE7 -+ 7 -+ 1 -+ -+ -+ FAE8 -+ FAE8 -+ 8 -+ 1 -+ -+ -+ FAE9 -+ FAE9 -+ 9 -+ 1 -+ -+ -+ FAE10 -+ FAE10 -+ 10 -+ 1 -+ -+ -+ FAE11 -+ FAE11 -+ 11 -+ 1 -+ -+ -+ FAE12 -+ FAE12 -+ 12 -+ 1 -+ -+ -+ FAE13 -+ FAE13 -+ 13 -+ 1 -+ -+ -+ FAE14 -+ FAE14 -+ 14 -+ 1 -+ -+ -+ FAE15 -+ FAE15 -+ 15 -+ 1 -+ -+ -+ FPE0 -+ FPE0 -+ 16 -+ 1 -+ -+ -+ FPE1 -+ FPE1 -+ 17 -+ 1 -+ -+ -+ FPE2 -+ FPE2 -+ 18 -+ 1 -+ -+ -+ FPE3 -+ FPE3 -+ 19 -+ 1 -+ -+ -+ FPE4 -+ FPE4 -+ 20 -+ 1 -+ -+ -+ -+ -+ DSI_FIR1 -+ DSI_FIR1 -+ DSI Host force interrupt register 1 -+ 0xDC -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ FTOHSTX -+ FTOHSTX -+ 0 -+ 1 -+ -+ -+ FTOLPRX -+ FTOLPRX -+ 1 -+ 1 -+ -+ -+ FECCSE -+ FECCSE -+ 2 -+ 1 -+ -+ -+ FECCME -+ FECCME -+ 3 -+ 1 -+ -+ -+ FCRCE -+ FCRCE -+ 4 -+ 1 -+ -+ -+ FPSE -+ FPSE -+ 5 -+ 1 -+ -+ -+ FEOTPE -+ FEOTPE -+ 6 -+ 1 -+ -+ -+ FLPWRE -+ FLPWRE -+ 7 -+ 1 -+ -+ -+ FGCWRE -+ FGCWRE -+ 8 -+ 1 -+ -+ -+ FGPWRE -+ FGPWRE -+ 9 -+ 1 -+ -+ -+ FGPTXE -+ FGPTXE -+ 10 -+ 1 -+ -+ -+ FGPRDE -+ FGPRDE -+ 11 -+ 1 -+ -+ -+ FGPRXE -+ FGPRXE -+ 12 -+ 1 -+ -+ -+ -+ -+ DSI_DLTRCR -+ DSI_DLTRCR -+ DSI Host data lane timer read configuration register -+ 0xF4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MRD_TIME -+ MRD_TIME -+ 0 -+ 15 -+ -+ -+ -+ -+ DSI_VSCR -+ DSI_VSCR -+ DSI Host video shadow control register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ UR -+ UR -+ 8 -+ 1 -+ -+ -+ -+ -+ DSI_LCVCIDR -+ DSI_LCVCIDR -+ DSI Host LTDC current VCID register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VCID -+ VCID -+ 0 -+ 2 -+ -+ -+ -+ -+ DSI_LCCCR -+ DSI_LCCCR -+ DSI Host LTDC current color coding register -+ 0x110 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ COLC -+ COLC -+ 0 -+ 4 -+ -+ -+ LPE -+ LPE -+ 8 -+ 1 -+ -+ -+ -+ -+ DSI_LPMCCR -+ DSI_LPMCCR -+ DSI Host low-power mode current configuration register -+ 0x118 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VLPSIZE -+ VLPSIZE -+ 0 -+ 8 -+ -+ -+ LPSIZE -+ LPSIZE -+ 16 -+ 8 -+ -+ -+ -+ -+ DSI_VMCCR -+ DSI_VMCCR -+ DSI Host video mode current configuration register -+ 0x138 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VMT -+ VMT -+ 0 -+ 2 -+ -+ -+ LPVSAE -+ LPVSAE -+ 2 -+ 1 -+ -+ -+ LPVBPE -+ LPVBPE -+ 3 -+ 1 -+ -+ -+ LPVFPE -+ LPVFPE -+ 4 -+ 1 -+ -+ -+ LPVAE -+ LPVAE -+ 5 -+ 1 -+ -+ -+ LPHBPE -+ LPHBPE -+ 6 -+ 1 -+ -+ -+ LPHFE -+ LPHFE -+ 7 -+ 1 -+ -+ -+ FBTAAE -+ FBTAAE -+ 8 -+ 1 -+ -+ -+ LPCE -+ LPCE -+ 9 -+ 1 -+ -+ -+ -+ -+ DSI_VPCCR -+ DSI_VPCCR -+ DSI Host video packet current configuration register -+ 0x13C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VPSIZE -+ VPSIZE -+ 0 -+ 14 -+ -+ -+ -+ -+ DSI_VCCCR -+ DSI_VCCCR -+ DSI Host video chunks current configuration register -+ 0x140 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ NUMC -+ NUMC -+ 0 -+ 13 -+ -+ -+ -+ -+ DSI_VNPCCR -+ DSI_VNPCCR -+ DSI Host video null packet current configuration register -+ 0x144 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ NPSIZE -+ NPSIZE -+ 0 -+ 13 -+ -+ -+ -+ -+ DSI_VHSACCR -+ DSI_VHSACCR -+ DSI Host video HSA current configuration register -+ 0x148 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HSA -+ HSA -+ 0 -+ 12 -+ -+ -+ -+ -+ DSI_VHBPCCR -+ DSI_VHBPCCR -+ DSI Host video HBP current configuration register -+ 0x14C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HBP -+ HBP -+ 0 -+ 12 -+ -+ -+ -+ -+ DSI_VLCCR -+ DSI_VLCCR -+ DSI Host video line current configuration register -+ 0x150 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HLINE -+ HLINE -+ 0 -+ 15 -+ -+ -+ -+ -+ DSI_VVSACCR -+ DSI_VVSACCR -+ DSI Host video VSA current configuration register -+ 0x154 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VSA -+ VSA -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVBPCCR -+ DSI_VVBPCCR -+ DSI Host video VBP current configuration register -+ 0x158 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VBP -+ VBP -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVFPCCR -+ DSI_VVFPCCR -+ DSI Host video VFP current configuration register -+ 0x15C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VFP -+ VFP -+ 0 -+ 10 -+ -+ -+ -+ -+ DSI_VVACCR -+ DSI_VVACCR -+ DSI Host video VA current configuration register -+ 0x160 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ VA -+ VA -+ 0 -+ 14 -+ -+ -+ -+ -+ DSI_WCFGR -+ DSI_WCFGR -+ DSI wrapper configuration register -+ 0x400 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DSIM -+ DSIM -+ 0 -+ 1 -+ -+ -+ COLMUX -+ COLMUX -+ 1 -+ 3 -+ -+ -+ TESRC -+ TESRC -+ 4 -+ 1 -+ -+ -+ TEPOL -+ TEPOL -+ 5 -+ 1 -+ -+ -+ AR -+ AR -+ 6 -+ 1 -+ -+ -+ VSPOL -+ VSPOL -+ 7 -+ 1 -+ -+ -+ -+ -+ DSI_WCR -+ DSI_WCR -+ DSI wrapper control register -+ 0x404 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ COLM -+ COLM -+ 0 -+ 1 -+ -+ -+ SHTDN -+ SHTDN -+ 1 -+ 1 -+ -+ -+ LTDCEN -+ LTDCEN -+ 2 -+ 1 -+ -+ -+ DSIEN -+ DSIEN -+ 3 -+ 1 -+ -+ -+ -+ -+ DSI_WIER -+ DSI_WIER -+ DSI wrapper interrupt enable register -+ 0x408 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TEIE -+ TEIE -+ 0 -+ 1 -+ -+ -+ ERIE -+ ERIE -+ 1 -+ 1 -+ -+ -+ PLLLIE -+ PLLLIE -+ 9 -+ 1 -+ -+ -+ PLLUIE -+ PLLUIE -+ 10 -+ 1 -+ -+ -+ RRIE -+ RRIE -+ 13 -+ 1 -+ -+ -+ -+ -+ DSI_WISR -+ DSI_WISR -+ DSI wrapper interrupt and status register -+ 0x40C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ ERIF -+ ERIF -+ 1 -+ 1 -+ -+ -+ BUSY -+ BUSY -+ 2 -+ 1 -+ -+ -+ PLLLS -+ PLLLS -+ 8 -+ 1 -+ -+ -+ PLLLIF -+ PLLLIF -+ 9 -+ 1 -+ -+ -+ PLLUIF -+ PLLUIF -+ 10 -+ 1 -+ -+ -+ RRS -+ RRS -+ 12 -+ 1 -+ -+ -+ RRIF -+ RRIF -+ 13 -+ 1 -+ -+ -+ -+ -+ DSI_WIFCR -+ DSI_WIFCR -+ DSI wrapper interrupt flag clear register -+ 0x410 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CERIF -+ CERIF -+ 1 -+ 1 -+ -+ -+ CPLLLIF -+ CPLLLIF -+ 9 -+ 1 -+ -+ -+ CPLLUIF -+ CPLLUIF -+ 10 -+ 1 -+ -+ -+ CRRIF -+ CRRIF -+ 13 -+ 1 -+ -+ -+ -+ -+ DSI_WPCR0 -+ DSI_WPCR0 -+ DSI wrapper PHY configuration register 0 -+ 0x418 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIX4 -+ UIX4 -+ 0 -+ 6 -+ -+ -+ SWCL -+ SWCL -+ 6 -+ 1 -+ -+ -+ SWDL0 -+ SWDL0 -+ 7 -+ 1 -+ -+ -+ SWDL1 -+ SWDL1 -+ 8 -+ 1 -+ -+ -+ HSICL -+ HSICL -+ 9 -+ 1 -+ -+ -+ HSIDL0 -+ HSIDL0 -+ 10 -+ 1 -+ -+ -+ HSIDL1 -+ HSIDL1 -+ 11 -+ 1 -+ -+ -+ FTXSMCL -+ FTXSMCL -+ 12 -+ 1 -+ -+ -+ FTXSMDL -+ FTXSMDL -+ 13 -+ 1 -+ -+ -+ CDOFFDL -+ CDOFFDL -+ 14 -+ 1 -+ -+ -+ TDDL -+ TDDL -+ 16 -+ 1 -+ -+ -+ -+ -+ DSI_WPCR1 -+ DSI_WPCR1 -+ This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). -+ 0x41C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SKEWCL -+ SKEWCL -+ 0 -+ 2 -+ -+ -+ SKEWDL -+ SKEWDL -+ 2 -+ 2 -+ -+ -+ LPTXSRCL -+ LPTXSRCL -+ 6 -+ 2 -+ -+ -+ LPTXSRDL -+ LPTXSRDL -+ 8 -+ 2 -+ -+ -+ SDDCCL -+ SDDCCL -+ 12 -+ 1 -+ -+ -+ SDDCDL -+ SDDCDL -+ 13 -+ 1 -+ -+ -+ HSTXSRUCL -+ HSTXSRUCL -+ 16 -+ 1 -+ -+ -+ HSTXSRDCL -+ HSTXSRDCL -+ 17 -+ 1 -+ -+ -+ HSTXSRUDL -+ HSTXSRUDL -+ 18 -+ 1 -+ -+ -+ HSTXSRDDL -+ HSTXSRDDL -+ 19 -+ 1 -+ -+ -+ -+ -+ DSI_WRPCR -+ DSI_WRPCR -+ DSI wrapper regulator and PLL control register -+ 0x430 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PLLEN -+ PLLEN -+ 0 -+ 1 -+ -+ -+ NDIV -+ NDIV -+ 2 -+ 7 -+ -+ -+ IDF -+ IDF -+ 11 -+ 4 -+ -+ -+ ODF -+ ODF -+ 16 -+ 2 -+ -+ -+ REGEN -+ REGEN -+ 24 -+ 1 -+ -+ -+ BGREN -+ BGREN -+ 28 -+ 1 -+ -+ -+ -+ -+ DSI_HWCFGR -+ DSI_HWCFGR -+ DSI Host hardware configuration register -+ 0x7F0 -+ 0x20 -+ read-only -+ 0x00005A01 -+ -+ -+ TECHNO -+ TECHNO -+ 0 -+ 4 -+ -+ -+ FIFOSIZE -+ FIFOSIZE -+ 4 -+ 12 -+ -+ -+ -+ -+ DSI_VERR -+ DSI_VERR -+ DSI Host version register -+ 0x7F4 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ DSI_IPIDR -+ DSI_IPIDR -+ DSI Host identification register -+ 0x7F8 -+ 0x20 -+ read-only -+ 0x00160071 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ DSI_SIDR -+ DSI_SIDR -+ DSI Host size identification register -+ 0x7FC -+ 0x20 -+ read-only -+ 0xA3C5DD02 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ DTS -+ DTS register block -+ DTS -+ 0x50028000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ DTS_CFGR1 -+ DTS_CFGR1 -+ DTS_CFGR1 is the configuration register for temperature sensor 1. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS1_EN -+ TS1_EN -+ 0 -+ 1 -+ -+ -+ TS1_START -+ TS1_START -+ 4 -+ 1 -+ -+ -+ TS1_INTRIG_SEL -+ TS1_INTRIG_SEL -+ 8 -+ 4 -+ -+ -+ TS1_SMP_TIME -+ TS1_SMP_TIME -+ 16 -+ 4 -+ -+ -+ REFCLK_SEL -+ REFCLK_SEL -+ 20 -+ 1 -+ -+ -+ Q_MEAS_opt -+ Q_MEAS_opt -+ 21 -+ 1 -+ -+ -+ HSREF_CLK_DIV -+ HSREF_CLK_DIV -+ 24 -+ 7 -+ -+ -+ -+ -+ DTS_T0VALR1 -+ DTS_T0VALR1 -+ DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TS1_FMT0 -+ TS1_FMT0 -+ 0 -+ 16 -+ -+ -+ TS1_T0 -+ TS1_T0 -+ 16 -+ 2 -+ -+ -+ -+ -+ DTS_RAMPVALR -+ DTS_RAMPVALR -+ The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TS1_RAMP_COEFF -+ TS1_RAMP_COEFF -+ 0 -+ 16 -+ -+ -+ -+ -+ DTS_ITR1 -+ DTS_ITR1 -+ DTS_ITR1 contains the threshold values for sensor 1. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS1_LITTHD -+ TS1_LITTHD -+ 0 -+ 16 -+ -+ -+ TS1_HITTHD -+ TS1_HITTHD -+ 16 -+ 16 -+ -+ -+ -+ -+ DTS_DR -+ DTS_DR -+ The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS1_MFREQ -+ TS1_MFREQ -+ 0 -+ 16 -+ -+ -+ -+ -+ DTS_SR -+ DTS_SR -+ Temperature sensor status register -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TS1_ITEF -+ TS1_ITEF -+ 0 -+ 1 -+ -+ -+ TS1_ITLF -+ TS1_ITLF -+ 1 -+ 1 -+ -+ -+ TS1_ITHF -+ TS1_ITHF -+ 2 -+ 1 -+ -+ -+ TS1_AITEF -+ TS1_AITEF -+ 4 -+ 1 -+ -+ -+ TS1_AITLF -+ TS1_AITLF -+ 5 -+ 1 -+ -+ -+ TS1_AITHF -+ TS1_AITHF -+ 6 -+ 1 -+ -+ -+ TS1_RDY -+ TS1_RDY -+ 15 -+ 1 -+ -+ -+ -+ -+ DTS_ITENR -+ DTS_ITENR -+ Temperature sensor interrupt enable register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS1_ITEEN -+ TS1_ITEEN -+ 0 -+ 1 -+ -+ -+ TS1_ITLEN -+ TS1_ITLEN -+ 1 -+ 1 -+ -+ -+ TS1_ITHEN -+ TS1_ITHEN -+ 2 -+ 1 -+ -+ -+ TS1_AITEEN -+ TS1_AITEEN -+ 4 -+ 1 -+ -+ -+ TS1_AITLEN -+ TS1_AITLEN -+ 5 -+ 1 -+ -+ -+ TS1_AITHEN -+ TS1_AITHEN -+ 6 -+ 1 -+ -+ -+ -+ -+ DTS_ICIFR -+ DTS_ICIFR -+ DTS_ICIFR is the control register for the interrupt flags. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS1_CITEF -+ TS1_CITEF -+ 0 -+ 1 -+ -+ -+ TS1_CITLF -+ TS1_CITLF -+ 1 -+ 1 -+ -+ -+ TS1_CITHF -+ TS1_CITHF -+ 2 -+ 1 -+ -+ -+ TS1_CAITEF -+ TS1_CAITEF -+ 4 -+ 1 -+ -+ -+ TS1_CAITLF -+ TS1_CAITLF -+ 5 -+ 1 -+ -+ -+ TS1_CAITHF -+ TS1_CAITHF -+ 6 -+ 1 -+ -+ -+ -+ -+ DTS_OR -+ DTS_OR -+ The DTS_OR contains general-purpose option bits. -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TS_Op0 -+ TS_Op0 -+ 0 -+ 1 -+ -+ -+ TS_Op1 -+ TS_Op1 -+ 1 -+ 1 -+ -+ -+ TS_Op2 -+ TS_Op2 -+ 2 -+ 1 -+ -+ -+ TS_Op3 -+ TS_Op3 -+ 3 -+ 1 -+ -+ -+ TS_Op4 -+ TS_Op4 -+ 4 -+ 1 -+ -+ -+ TS_Op5 -+ TS_Op5 -+ 5 -+ 1 -+ -+ -+ TS_Op6 -+ TS_Op6 -+ 6 -+ 1 -+ -+ -+ TS_Op7 -+ TS_Op7 -+ 7 -+ 1 -+ -+ -+ TS_Op8 -+ TS_Op8 -+ 8 -+ 1 -+ -+ -+ TS_Op9 -+ TS_Op9 -+ 9 -+ 1 -+ -+ -+ TS_Op10 -+ TS_Op10 -+ 10 -+ 1 -+ -+ -+ TS_Op11 -+ TS_Op11 -+ 11 -+ 1 -+ -+ -+ TS_Op12 -+ TS_Op12 -+ 12 -+ 1 -+ -+ -+ TS_Op13 -+ TS_Op13 -+ 13 -+ 1 -+ -+ -+ TS_Op14 -+ TS_Op14 -+ 14 -+ 1 -+ -+ -+ TS_Op15 -+ TS_Op15 -+ 15 -+ 1 -+ -+ -+ TS_Op16 -+ TS_Op16 -+ 16 -+ 1 -+ -+ -+ TS_Op17 -+ TS_Op17 -+ 17 -+ 1 -+ -+ -+ TS_Op18 -+ TS_Op18 -+ 18 -+ 1 -+ -+ -+ TS_Op19 -+ TS_Op19 -+ 19 -+ 1 -+ -+ -+ TS_Op20 -+ TS_Op20 -+ 20 -+ 1 -+ -+ -+ TS_Op21 -+ TS_Op21 -+ 21 -+ 1 -+ -+ -+ TS_Op22 -+ TS_Op22 -+ 22 -+ 1 -+ -+ -+ TS_Op23 -+ TS_Op23 -+ 23 -+ 1 -+ -+ -+ TS_Op24 -+ TS_Op24 -+ 24 -+ 1 -+ -+ -+ TS_Op25 -+ TS_Op25 -+ 25 -+ 1 -+ -+ -+ TS_Op26 -+ TS_Op26 -+ 26 -+ 1 -+ -+ -+ TS_Op27 -+ TS_Op27 -+ 27 -+ 1 -+ -+ -+ TS_Op28 -+ TS_Op28 -+ 28 -+ 1 -+ -+ -+ TS_Op29 -+ TS_Op29 -+ 29 -+ 1 -+ -+ -+ TS_Op30 -+ TS_Op30 -+ 30 -+ 1 -+ -+ -+ TS_Op31 -+ TS_Op31 -+ 31 -+ 1 -+ -+ -+ -+ -+ -+ -+ ETH_MAC_MMC -+ ETH_MAC_MMC -+ Ethernet -+ 0x5800A000 -+ -+ 0x0 -+ 0xBD4 -+ registers -+ -+ -+ -+ ETH_MACCR -+ ETH_MACCR -+ The MAC Configuration Register establishes -+ the operating mode of the MAC. -+ 0x00 -+ 0x20 -+ read-write -+ 0x00008000 -+ -+ -+ RE -+ RE -+ 0 -+ 1 -+ read-write -+ -+ -+ TE -+ TE -+ 1 -+ 1 -+ read-write -+ -+ -+ PRELEN -+ PRELEN -+ 2 -+ 2 -+ read-write -+ -+ -+ DC -+ DC -+ 4 -+ 1 -+ read-write -+ -+ -+ BL -+ BL -+ 5 -+ 2 -+ read-write -+ -+ -+ DR -+ DR -+ 8 -+ 1 -+ read-write -+ -+ -+ DCRS -+ DCRS -+ 9 -+ 1 -+ read-write -+ -+ -+ DO -+ DO -+ 10 -+ 1 -+ read-write -+ -+ -+ ECRSFD -+ ECRSFD -+ 11 -+ 1 -+ read-write -+ -+ -+ LM -+ LM -+ 12 -+ 1 -+ read-write -+ -+ -+ DM -+ DM -+ 13 -+ 1 -+ read-write -+ -+ -+ FES -+ FES -+ 14 -+ 1 -+ read-write -+ -+ -+ PS -+ PS -+ 15 -+ 1 -+ read-write -+ -+ -+ JE -+ JE -+ 16 -+ 1 -+ read-write -+ -+ -+ JD -+ JD -+ 17 -+ 1 -+ read-write -+ -+ -+ BE -+ BE -+ 18 -+ 1 -+ read-write -+ -+ -+ WD -+ WD -+ 19 -+ 1 -+ read-write -+ -+ -+ ACS -+ ACS -+ 20 -+ 1 -+ read-write -+ -+ -+ CST -+ CST -+ 21 -+ 1 -+ read-write -+ -+ -+ S2KP -+ S2KP -+ 22 -+ 1 -+ read-write -+ -+ -+ GPSLCE -+ GPSLCE -+ 23 -+ 1 -+ read-write -+ -+ -+ IPG -+ IPG -+ 24 -+ 3 -+ read-write -+ -+ -+ IPC -+ IPC -+ 27 -+ 1 -+ read-write -+ -+ -+ SARC -+ SARC -+ 28 -+ 3 -+ read-write -+ -+ -+ ARPEN -+ ARPEN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACECR -+ ETH_MACECR -+ The MAC Extended Configuration Register -+ establishes the operating mode of the MAC. -+ 0x04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPSL -+ GPSL -+ 0 -+ 14 -+ read-write -+ -+ -+ DCRCC -+ DCRCC -+ 16 -+ 1 -+ read-write -+ -+ -+ SPEN -+ SPEN -+ 17 -+ 1 -+ read-write -+ -+ -+ USP -+ USP -+ 18 -+ 1 -+ read-write -+ -+ -+ EIPGEN -+ EIPGEN -+ 24 -+ 1 -+ read-write -+ -+ -+ EIPG -+ EIPG -+ 25 -+ 5 -+ read-write -+ -+ -+ -+ -+ ETH_MACPFR -+ ETH_MACPFR -+ The MAC Packet Filter register contains the -+ filter controls for receiving packets. Some of the -+ controls from this register go to the address check block -+ of the MAC which performs the first level of address -+ filtering. The second level of filtering is performed on -+ the incoming packet based on other controls such as Pass -+ Bad Packets and Pass Control Packets. -+ 0x08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PR -+ PR -+ 0 -+ 1 -+ read-write -+ -+ -+ HUC -+ HUC -+ 1 -+ 1 -+ read-write -+ -+ -+ HMC -+ HMC -+ 2 -+ 1 -+ read-write -+ -+ -+ DAIF -+ DAIF -+ 3 -+ 1 -+ read-write -+ -+ -+ PM -+ PM -+ 4 -+ 1 -+ read-write -+ -+ -+ DBF -+ DBF -+ 5 -+ 1 -+ read-write -+ -+ -+ PCF -+ PCF -+ 6 -+ 2 -+ read-write -+ -+ -+ SAIF -+ SAIF -+ 8 -+ 1 -+ read-write -+ -+ -+ SAF -+ SAF -+ 9 -+ 1 -+ read-write -+ -+ -+ HPF -+ HPF -+ 10 -+ 1 -+ read-write -+ -+ -+ VTFE -+ VTFE -+ 16 -+ 1 -+ read-write -+ -+ -+ IPFE -+ IPFE -+ 20 -+ 1 -+ read-write -+ -+ -+ DNTU -+ DNTU -+ 21 -+ 1 -+ read-write -+ -+ -+ RA -+ RA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACWTR -+ ETH_MACWTR -+ The Watchdog Timeout register controls the -+ watchdog timeout for received packets. -+ 0x0C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WTO -+ WTO -+ 0 -+ 4 -+ read-write -+ -+ -+ PWE -+ PWE -+ 8 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACHT0R -+ ETH_MACHT0R -+ The Hash Table Register 0 contains the first -+ 32 bits of the Hash table (64 bits). For Hash filtering, -+ the content of the destination address in the incoming -+ packet is passed through the CRC logic and the upper six -+ bits of the CRC register are used to index the content of -+ the Hash table. The most significant bits determines the -+ register to be used (Hash Table Register 0 or 1). The -+ Hash value of the destination address is calculated in -+ the following way: Calculate the 32-bit CRC for the DA -+ (See IEEE 802.3, Section 3.2.8 for the steps to calculate -+ CRC32). Perform bitwise reversal for the value obtained -+ in Step 1. Take the upper 7 or 8 bits from the value -+ obtained in Step 2. If the corresponding bit value of the -+ register is 1, the packet is accepted. Otherwise, it is -+ rejected. If the PM bit is set in ETH_MACPFR, all -+ multicast packets are accepted regardless of the -+ multicast Hash values. If the Hash Table register is -+ configured to be double-synchronized to the GMII clock -+ domain, the synchronization is triggered only when -+ Bits[31:24] (in little-endian mode) or Bits[7:0] (in -+ big-endian mode) of the Hash Table Register X registers -+ are written. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HT31T0 -+ HT31T0 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACHT1R -+ ETH_MACHT1R -+ The Hash Table Register 1contains the last -+ 32 bits of the Hash table (64 bits). For Hash filtering, -+ the content of the destination address in the incoming -+ packet is passed through the CRC logic and the upper six -+ bits of the CRC register are used to index the content of -+ the Hash table. The most significant bits determines the -+ register to be used (Hash Table Register 0 or 1). The -+ Hash value of the destination address is calculated in -+ the following way: Calculate the 32-bit CRC for the DA -+ (See IEEE 802.3, Section 3.2.8 for the steps to calculate -+ CRC32). Perform bitwise reversal for the value obtained -+ in Step 1. Take the upper 7 or 8 bits from the value -+ obtained in Step 2. If the corresponding bit value of the -+ register is 1, the packet is accepted. Otherwise, it is -+ rejected. If the PM bit is set in ETH_MACPFR, all -+ multicast packets are accepted regardless of the -+ multicast Hash values. If the Hash Table register is -+ configured to be double-synchronized to the GMII clock -+ domain, the synchronization is triggered only when -+ Bits[31:24] (in little-endian mode) or Bits[7:0] (in -+ big-endian mode) of the Hash Table Register X registers -+ are written. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HT63T32 -+ HT63T32 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACVTR -+ ETH_MACVTR -+ The VLAN Tag register identifies the IEEE -+ 802.1Q VLAN type packets. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VL -+ VL -+ 0 -+ 16 -+ read-write -+ -+ -+ ETV -+ ETV -+ 16 -+ 1 -+ read-write -+ -+ -+ VTIM -+ VTIM -+ 17 -+ 1 -+ read-write -+ -+ -+ ESVL -+ ESVL -+ 18 -+ 1 -+ read-write -+ -+ -+ ERSVLM -+ ERSVLM -+ 19 -+ 1 -+ read-write -+ -+ -+ DOVLTC -+ DOVLTC -+ 20 -+ 1 -+ read-write -+ -+ -+ EVLS -+ EVLS -+ 21 -+ 2 -+ read-write -+ -+ -+ EVLRXS -+ EVLRXS -+ 24 -+ 1 -+ read-write -+ -+ -+ VTHM -+ VTHM -+ 25 -+ 1 -+ read-write -+ -+ -+ EDVLP -+ EDVLP -+ 26 -+ 1 -+ read-write -+ -+ -+ ERIVLT -+ ERIVLT -+ 27 -+ 1 -+ read-write -+ -+ -+ EIVLS -+ EIVLS -+ 28 -+ 2 -+ read-write -+ -+ -+ EIVLRXS -+ EIVLRXS -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACVHTR -+ ETH_MACVHTR -+ When the ERSVLM bit of ETH_MACHT1R register -+ is set, the 16-bit VLAN Hash Table register is used for -+ group address filtering based on the VLAN tag. For Hash -+ filtering, the content of the 16-bit VLAN tag or 12-bit -+ VLAN ID (based on the ETV bit of ETH_MACVTR register) in -+ the incoming packet is passed through the CRC logic. The -+ upper four bits of the calculated CRC are used to index -+ the contents of the VLAN Hash table. For example, a Hash -+ value of 1000 selects Bit 8 of the VLAN Hash table. The -+ Hash value of the destination address is calculated in -+ the following way: Calculate the 32-bit CRC for the VLAN -+ tag or ID (For steps to calculate CRC32, see Section -+ 3.2.8 of IEEE 802.3). Perform bitwise reversal for the -+ value obtained in step 1. Take the upper four bits from -+ the value obtained in step 2. If the VLAN Hash Table -+ register is configured to be double-synchronized to the -+ GMII clock domain, the synchronization is triggered only -+ when Bits[15:8] (in little-endian mode) or Bits[7:0] (in -+ big-endian mode) of this register are -+ written. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VLHT -+ VLHT -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACVIR -+ ETH_MACVIR -+ The VLAN Tag Inclusion or Replacement -+ register contains the VLAN tag for insertion or -+ replacement in the Transmit packets. It also contains the -+ VLAN tag insertion controls. -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VLT -+ VLT -+ 0 -+ 16 -+ read-write -+ -+ -+ VLC -+ VLC -+ 16 -+ 2 -+ read-write -+ -+ -+ VLP -+ VLP -+ 18 -+ 1 -+ read-write -+ -+ -+ CSVL -+ CSVL -+ 19 -+ 1 -+ read-write -+ -+ -+ VLTI -+ VLTI -+ 20 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACIVIR -+ ETH_MACIVIR -+ The Inner VLAN Tag Inclusion or Replacement -+ register contains the inner VLAN tag to be inserted or -+ replaced in the Transmit packet. It also contains the -+ inner VLAN tag insertion controls. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VLT -+ VLT -+ 0 -+ 16 -+ read-write -+ -+ -+ VLC -+ VLC -+ 16 -+ 2 -+ read-write -+ -+ -+ VLP -+ VLP -+ 18 -+ 1 -+ read-write -+ -+ -+ CSVL -+ CSVL -+ 19 -+ 1 -+ read-write -+ -+ -+ VLTI -+ VLTI -+ 20 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACQ0TxFCR -+ ETH_MACQ0TxFCR -+ The Flow Control register controls the -+ generation and reception of the Control (Pause Command) -+ packets by the Flow control module of the MAC. A Write to -+ a register with the Busy bit set to 1 triggers the Flow -+ Control block to generate a Pause packet. The fields of -+ the control packet are selected as specified in the -+ 802.3x specification, and the Pause Time value from this -+ register is used in the Pause Time field of the control -+ packet. The Busy bit remains set until the control packet -+ is transferred onto the cable. The application must make -+ sure that the Busy bit is cleared before writing to the -+ register. -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FCB_BPA -+ FCB_BPA -+ 0 -+ 1 -+ read-write -+ -+ -+ TFE -+ TFE -+ 1 -+ 1 -+ read-write -+ -+ -+ PLT -+ PLT -+ 4 -+ 3 -+ read-write -+ -+ -+ DZPQ -+ DZPQ -+ 7 -+ 1 -+ read-write -+ -+ -+ PT -+ PT -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACRxFCR -+ ETH_MACRxFCR -+ The Receive Flow Control register controls -+ the pausing of MAC Transmit based on the received Pause -+ packet. -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RFE -+ RFE -+ 0 -+ 1 -+ read-write -+ -+ -+ UP -+ UP -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACTxQPMR -+ ETH_MACTxQPMR -+ The transmit queue priority mapping 0 -+ register contains the priority values assigned to Tx -+ queue 0 and tx queue 1. -+ 0x98 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PSTQ0 -+ PSTQ0 -+ 0 -+ 8 -+ read-only -+ -+ -+ PSTQ1 -+ PSTQ1 -+ 8 -+ 8 -+ read-only -+ -+ -+ -+ -+ ETH_MACRxQC0R -+ ETH_MACRxQC0R -+ The Receive Queue Control 0 register -+ controls the queue management in the MAC -+ Receiver. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXQ0EN -+ RXQ0EN -+ 0 -+ 2 -+ read-write -+ -+ -+ RXQ1EN -+ RXQ1EN -+ 2 -+ 2 -+ read-write -+ -+ -+ -+ -+ ETH_MACRxQC1R -+ ETH_MACRxQC1R -+ The Receive Queue Control 1 register -+ controls queue 1 management in the MAC -+ receiver. -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AVCPQ -+ AVCPQ -+ 0 -+ 3 -+ read-write -+ -+ -+ AVPTPQ -+ AVPTPQ -+ 4 -+ 3 -+ read-write -+ -+ -+ UPQ -+ UPQ -+ 12 -+ 3 -+ read-write -+ -+ -+ MCBCQ -+ MCBCQ -+ 16 -+ 3 -+ read-write -+ -+ -+ MCBCQEN -+ MCBCQEN -+ 20 -+ 1 -+ read-write -+ -+ -+ TACPQE -+ TACPQE -+ 21 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACRxQC2R -+ ETH_MACRxQC2R -+ This register controls the routing of tagged -+ packets based on the USP (user priority) field of the -+ received packets to the Rx queue 0 and 1. -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PSRQ0 -+ PSRQ0 -+ 0 -+ 8 -+ read-write -+ -+ -+ PSRQ1 -+ PSRQ1 -+ 8 -+ 8 -+ read-write -+ -+ -+ -+ -+ ETH_MACISR -+ ETH_MACISR -+ The Interrupt Status register contains the -+ status of interrupts. -+ 0xB0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RGSMIIIS -+ RGSMIIIS -+ 0 -+ 1 -+ read-only -+ -+ -+ PHYIS -+ PHYIS -+ 3 -+ 1 -+ read-only -+ -+ -+ PMTIS -+ PMTIS -+ 4 -+ 1 -+ read-only -+ -+ -+ LPIIS -+ LPIIS -+ 5 -+ 1 -+ read-only -+ -+ -+ MMCIS -+ MMCIS -+ 8 -+ 1 -+ read-only -+ -+ -+ MMCRXIS -+ MMCRXIS -+ 9 -+ 1 -+ read-only -+ -+ -+ MMCTXIS -+ MMCTXIS -+ 10 -+ 1 -+ read-only -+ -+ -+ TSIS -+ TSIS -+ 12 -+ 1 -+ read-only -+ -+ -+ TXSTSIS -+ TXSTSIS -+ 13 -+ 1 -+ read-only -+ -+ -+ RXSTSIS -+ RXSTSIS -+ 14 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MACIER -+ ETH_MACIER -+ The Interrupt Enable register contains the -+ masks for generating the interrupts. -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RGSMIIIE -+ RGSMIIIE -+ 0 -+ 1 -+ read-write -+ -+ -+ PHYIE -+ PHYIE -+ 3 -+ 1 -+ read-write -+ -+ -+ PMTIE -+ PMTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ LPIIE -+ LPIIE -+ 5 -+ 1 -+ read-write -+ -+ -+ TSIE -+ TSIE -+ 12 -+ 1 -+ read-write -+ -+ -+ TXSTSIE -+ TXSTSIE -+ 13 -+ 1 -+ read-write -+ -+ -+ RXSTSIE -+ RXSTSIE -+ 14 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACRxTxSR -+ ETH_MACRxTxSR -+ The Receive Transmit Status register -+ contains the Receive and Transmit Error -+ status. -+ 0xB8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TJT -+ TJT -+ 0 -+ 1 -+ read-only -+ -+ -+ NCARR -+ NCARR -+ 1 -+ 1 -+ read-only -+ -+ -+ LCARR -+ LCARR -+ 2 -+ 1 -+ read-only -+ -+ -+ EXDEF -+ EXDEF -+ 3 -+ 1 -+ read-only -+ -+ -+ LCOL -+ LCOL -+ 4 -+ 1 -+ read-only -+ -+ -+ EXCOL -+ EXCOL -+ 5 -+ 1 -+ read-only -+ -+ -+ RWT -+ RWT -+ 8 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MACPCSR -+ ETH_MACPCSR -+ The PMT Control and Status Register is -+ present only when you select the PMT module in -+ coreConsultant. -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PWRDWN -+ PWRDWN -+ 0 -+ 1 -+ read-write -+ -+ -+ MGKPKTEN -+ MGKPKTEN -+ 1 -+ 1 -+ read-write -+ -+ -+ RWKPKTEN -+ RWKPKTEN -+ 2 -+ 1 -+ read-write -+ -+ -+ MGKPRCVD -+ MGKPRCVD -+ 5 -+ 1 -+ read-only -+ -+ -+ RWKPRCVD -+ RWKPRCVD -+ 6 -+ 1 -+ read-only -+ -+ -+ GLBLUCAST -+ GLBLUCAST -+ 9 -+ 1 -+ read-write -+ -+ -+ RWKPFE -+ RWKPFE -+ 10 -+ 1 -+ read-write -+ -+ -+ RWKPTR -+ RWKPTR -+ 24 -+ 5 -+ read-only -+ -+ -+ RWKFILTRST -+ RWKFILTRST -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACRWKPFR -+ ETH_MACRWKPFR -+ The LPI Control and Status Register controls -+ the LPI functions and provides the LPI interrupt status. -+ The status bits are cleared when this register is -+ read. -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TLPIEN -+ TLPIEN -+ 0 -+ 1 -+ read-only -+ -+ -+ TLPIEX -+ TLPIEX -+ 1 -+ 1 -+ read-only -+ -+ -+ RLPIEN -+ RLPIEN -+ 2 -+ 1 -+ read-only -+ -+ -+ RLPIEX -+ RLPIEX -+ 3 -+ 1 -+ read-only -+ -+ -+ TLPIST -+ TLPIST -+ 8 -+ 1 -+ read-only -+ -+ -+ RLPIST -+ RLPIST -+ 9 -+ 1 -+ read-only -+ -+ -+ LPIEN -+ LPIEN -+ 16 -+ 1 -+ read-write -+ -+ -+ PLS -+ PLS -+ 17 -+ 1 -+ read-write -+ -+ -+ PLSEN -+ PLSEN -+ 18 -+ 1 -+ read-write -+ -+ -+ LPITXA -+ LPITXA -+ 19 -+ 1 -+ read-write -+ -+ -+ LPITE -+ LPITE -+ 20 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACLCSR -+ ETH_MACLCSR -+ The LPI Control and Status Register controls -+ the LPI functions and provides the LPI interrupt status. -+ The status bits are cleared when this register is -+ read. -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TLPIEN -+ TLPIEN -+ 0 -+ 1 -+ read-only -+ -+ -+ TLPIEX -+ TLPIEX -+ 1 -+ 1 -+ read-only -+ -+ -+ RLPIEN -+ RLPIEN -+ 2 -+ 1 -+ read-only -+ -+ -+ RLPIEX -+ RLPIEX -+ 3 -+ 1 -+ read-only -+ -+ -+ TLPIST -+ TLPIST -+ 8 -+ 1 -+ read-only -+ -+ -+ RLPIST -+ RLPIST -+ 9 -+ 1 -+ read-only -+ -+ -+ LPIEN -+ LPIEN -+ 16 -+ 1 -+ read-write -+ -+ -+ PLS -+ PLS -+ 17 -+ 1 -+ read-write -+ -+ -+ PLSEN -+ PLSEN -+ 18 -+ 1 -+ read-write -+ -+ -+ LPITXA -+ LPITXA -+ 19 -+ 1 -+ read-write -+ -+ -+ LPITE -+ LPITE -+ 20 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACLTCR -+ ETH_MACLTCR -+ The LPI Timers Control register controls the -+ timeout values in the LPI states. It specifies the time -+ for which the MAC transmits the LPI pattern and also the -+ time for which the MAC waits before resuming the normal -+ transmission. -+ 0xD4 -+ 0x20 -+ read-write -+ 0x03E80000 -+ -+ -+ TWT -+ TWT -+ 0 -+ 16 -+ read-write -+ -+ -+ LST -+ LST -+ 16 -+ 10 -+ read-write -+ -+ -+ -+ -+ ETH_MACLETR -+ ETH_MACLETR -+ The LPI Entry Timer Register is used to -+ store the LPI Idle Timer Value in -+ Micro-Seconds. -+ 0xD8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPIET -+ LPIET -+ 3 -+ 17 -+ read-write -+ -+ -+ -+ -+ ETH_MAC1USTCR -+ ETH_MAC1USTCR -+ This register controls the generation of the -+ Reference time (1-microsecond tick) for all the LPI -+ timers. This timer has to be programmed by the software -+ initially. -+ 0xDC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIC_1US_CNTR -+ TIC_1US_CNTR -+ 0 -+ 12 -+ read-write -+ -+ -+ -+ -+ ETH_MACPHYCSR -+ ETH_MACPHYCSR -+ The PHY Interface Control and Status -+ register indicates the status signals received by the, -+ RGMII interface from the PHY. -+ 0xF8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TC -+ TC -+ 0 -+ 1 -+ read-write -+ -+ -+ LUD -+ LUD -+ 1 -+ 1 -+ read-write -+ -+ -+ LNKMOD -+ LNKMOD -+ 16 -+ 1 -+ read-only -+ -+ -+ LNKSPEED -+ LNKSPEED -+ 17 -+ 2 -+ read-only -+ -+ -+ LNKSTS -+ LNKSTS -+ 19 -+ 1 -+ read-only -+ -+ -+ JABTO -+ JABTO -+ 20 -+ 1 -+ read-only -+ -+ -+ FALSCARDET -+ FALSCARDET -+ 21 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MACVR -+ ETH_MACVR -+ The version register identifies the version -+ of the Ethernet peripheral. -+ 0x110 -+ 0x20 -+ read-only -+ 0x00004042 -+ -+ -+ SNPSVER -+ SNPSVER -+ 0 -+ 8 -+ read-only -+ -+ -+ USERVER -+ USERVER -+ 8 -+ 8 -+ read-only -+ -+ -+ -+ -+ ETH_MACDR -+ ETH_MACDR -+ The Debug register provides the debug status -+ of various MAC blocks. -+ 0x114 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RPESTS -+ RPESTS -+ 0 -+ 1 -+ read-only -+ -+ -+ RFCFCSTS -+ RFCFCSTS -+ 1 -+ 2 -+ read-only -+ -+ -+ TPESTS -+ TPESTS -+ 16 -+ 1 -+ read-only -+ -+ -+ TFCSTS -+ TFCSTS -+ 17 -+ 2 -+ read-only -+ -+ -+ -+ -+ ETH_MACHWF1R -+ ETH_MACHWF1R -+ This register indicates the presence of -+ second set of the optional features or functions of the -+ Ethernet peripheral. The software driver can use this -+ register to dynamically enable or disable the programs -+ related to the optional blocks. -+ 0x120 -+ 0x20 -+ read-only -+ 0x11141945 -+ -+ -+ RXFIFOSIZE -+ RXFIFOSIZE -+ 0 -+ 5 -+ read-only -+ -+ -+ TXFIFOSIZE -+ TXFIFOSIZE -+ 6 -+ 5 -+ read-only -+ -+ -+ OSTEN -+ OSTEN -+ 11 -+ 1 -+ read-only -+ -+ -+ PTOEN -+ PTOEN -+ 12 -+ 1 -+ read-only -+ -+ -+ ADVTHWORD -+ ADVTHWORD -+ 13 -+ 1 -+ read-only -+ -+ -+ ADDR64 -+ ADDR64 -+ 14 -+ 2 -+ read-only -+ -+ -+ DCBEN -+ DCBEN -+ 16 -+ 1 -+ read-only -+ -+ -+ SPHEN -+ SPHEN -+ 17 -+ 1 -+ read-only -+ -+ -+ TSOEN -+ TSOEN -+ 18 -+ 1 -+ read-only -+ -+ -+ DBGMEMA -+ DBGMEMA -+ 19 -+ 1 -+ read-only -+ -+ -+ AVSEL -+ AVSEL -+ 20 -+ 1 -+ read-only -+ -+ -+ HASHTBLSZ -+ HASHTBLSZ -+ 24 -+ 2 -+ read-only -+ -+ -+ L3L4FNUM -+ L3L4FNUM -+ 27 -+ 4 -+ read-only -+ -+ -+ -+ -+ ETH_MACHWF2R -+ ETH_MACHWF2R -+ This register indicates the presence of -+ third set of the optional features or functions of the -+ Ethernet peripheral. The software driver can use this -+ register to dynamically enable or disable the programs -+ related to the optional blocks. -+ 0x124 -+ 0x20 -+ read-only -+ 0x41040041 -+ -+ -+ RXQCNT -+ RXQCNT -+ 0 -+ 4 -+ read-only -+ -+ -+ TXQCNT -+ TXQCNT -+ 6 -+ 4 -+ read-only -+ -+ -+ RXCHCNT -+ RXCHCNT -+ 12 -+ 4 -+ read-only -+ -+ -+ TXCHCNT -+ TXCHCNT -+ 18 -+ 4 -+ read-only -+ -+ -+ PPSOUTNUM -+ PPSOUTNUM -+ 24 -+ 3 -+ read-only -+ -+ -+ AUXSNAPNUM -+ AUXSNAPNUM -+ 28 -+ 3 -+ read-only -+ -+ -+ -+ -+ ETH_MACMDIOAR -+ ETH_MACMDIOAR -+ The MDIO Address register controls the -+ management cycles to external PHY through a management -+ interface. -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GB -+ GB -+ 0 -+ 1 -+ read-write -+ -+ -+ C45E -+ C45E -+ 1 -+ 1 -+ read-write -+ -+ -+ GOC -+ GOC -+ 2 -+ 2 -+ read-write -+ -+ -+ SKAP -+ SKAP -+ 4 -+ 1 -+ read-write -+ -+ -+ CR -+ CR -+ 8 -+ 4 -+ read-write -+ -+ -+ NTC -+ NTC -+ 12 -+ 3 -+ read-write -+ -+ -+ RDA -+ RDA -+ 16 -+ 5 -+ read-write -+ -+ -+ PA -+ PA -+ 21 -+ 5 -+ read-write -+ -+ -+ BTB -+ BTB -+ 26 -+ 1 -+ read-write -+ -+ -+ PSE -+ PSE -+ 27 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACMDIODR -+ ETH_MACMDIODR -+ The MDIO Data register stores the Write data -+ to be written to the PHY register located at the address -+ specified in ETH_MACMDIOAR. This register also stores the -+ Read data from the PHY register located at the address -+ specified by MDIO Address register. -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GD -+ GD -+ 0 -+ 16 -+ read-write -+ -+ -+ RA -+ RA -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACA0HR -+ ETH_MACA0HR -+ The MAC Address0 High register holds the -+ upper 16 bits of the first 6-byte MAC address of the -+ station. The first DA byte that is received on the GMII -+ interface corresponds to the LS byte (Bits [7:0]) of the -+ MAC Address Low register. For example, if 0x112233445566 -+ is received (0x11 in lane 0 of the first column) on the -+ GMII as the destination address, then the MacAddress0 -+ Register [47:0] is compared with 0x665544332211. If the -+ MAC address registers are configured to be -+ double-synchronized to the GMII clock domains, then the -+ synchronization is triggered only when Bits[31:24] (in -+ little-endian mode) or Bits[7:0] (in big-endian mode) of -+ the MAC Address0 Low Register are written. For proper -+ synchronization updates, the consecutive writes to this -+ Address Low Register should be performed after at least -+ four clock cycles in the destination clock -+ domain. -+ 0x300 -+ 0x20 -+ read-write -+ 0x8000FFFF -+ -+ -+ ADDRHI -+ ADDRHI -+ 0 -+ 16 -+ read-write -+ -+ -+ AE -+ AE -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MACA0LR -+ ETH_MACA0LR -+ The MAC Address x Low register holds the -+ lower 32 bits of the 6-byte first MAC address of the -+ station. -+ 0x304 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ ADDRLO -+ ADDRLO -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACA1HR -+ ETH_MACA1HR -+ The MAC Address x High register holds the -+ upper 16 bits of the second 6-byte MAC address of the -+ station. -+ 0x308 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ ADDRHI -+ ADDRHI -+ 0 -+ 16 -+ read-write -+ -+ -+ MBC -+ MBC -+ 24 -+ 6 -+ read-write -+ -+ -+ SA -+ SA -+ 30 -+ 1 -+ read-write -+ -+ -+ AE -+ AE -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACA1LR -+ ETH_MACA1LR -+ The MAC Address x Low register holds the -+ lower 32 bits of the 6-byte first MAC address of the -+ station. -+ 0x30C -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ ADDRLO -+ ADDRLO -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACA2HR -+ ETH_MACA2HR -+ The MAC Address x High register holds the -+ upper 16 bits of the second 6-byte MAC address of the -+ station. -+ 0x310 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ ADDRHI -+ ADDRHI -+ 0 -+ 16 -+ read-write -+ -+ -+ MBC -+ MBC -+ 24 -+ 6 -+ read-write -+ -+ -+ SA -+ SA -+ 30 -+ 1 -+ read-write -+ -+ -+ AE -+ AE -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACA2LR -+ ETH_MACA2LR -+ The MAC Address x Low register holds the -+ lower 32 bits of the 6-byte first MAC address of the -+ station. -+ 0x314 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ ADDRLO -+ ADDRLO -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACA3HR -+ ETH_MACA3HR -+ The MAC Address x High register holds the -+ upper 16 bits of the second 6-byte MAC address of the -+ station. -+ 0x318 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ ADDRHI -+ ADDRHI -+ 0 -+ 16 -+ read-write -+ -+ -+ MBC -+ MBC -+ 24 -+ 6 -+ read-write -+ -+ -+ SA -+ SA -+ 30 -+ 1 -+ read-write -+ -+ -+ AE -+ AE -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACA3LR -+ ETH_MACA3LR -+ The MAC Address x Low register holds the -+ lower 32 bits of the 6-byte first MAC address of the -+ station. -+ 0x31C -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ ADDRLO -+ ADDRLO -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ MMC_CONTROL -+ MMC_CONTROL -+ This register configures the MMC operating -+ mode. -+ 0x700 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNTRST -+ CNTRST -+ 0 -+ 1 -+ read-write -+ -+ -+ CNTSTOPRO -+ CNTSTOPRO -+ 1 -+ 1 -+ read-write -+ -+ -+ RSTONRD -+ RSTONRD -+ 2 -+ 1 -+ read-write -+ -+ -+ CNTFREEZ -+ CNTFREEZ -+ 3 -+ 1 -+ read-write -+ -+ -+ CNTPRST -+ CNTPRST -+ 4 -+ 1 -+ read-write -+ -+ -+ CNTPRSTLVL -+ CNTPRSTLVL -+ 5 -+ 1 -+ read-write -+ -+ -+ UCDBC -+ UCDBC -+ 8 -+ 1 -+ read-write -+ -+ -+ -+ -+ MMC_RX_INTERRUPT -+ MMC_RX_INTERRUPT -+ This register maintains the interrupts -+ generated from all Receive statistics counters. The MMC -+ Receive Interrupt register maintains the interrupts that -+ are generated when the following occur: Receive statistic -+ counters reach half of their maximum values (0x8000_0000 -+ for 32 bit counter and 0x8000 for 16 bit counter). -+ Receive statistic counters cross their maximum values -+ (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit -+ counter). When the Counter Stop Rollover is set, -+ interrupts are set but the counter remains at all-ones. -+ The MMC Receive Interrupt register is a 32 bit register. -+ An interrupt bit is cleared when the respective MMC -+ counter that caused the interrupt is read. The least -+ significant byte lane (Bits[7:0]) of the respective -+ counter must be read to clear the interrupt -+ bit. -+ 0x704 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXCRCERPIS -+ RXCRCERPIS -+ 5 -+ 1 -+ read-only -+ -+ -+ RXALGNERPIS -+ RXALGNERPIS -+ 6 -+ 1 -+ read-only -+ -+ -+ RXUCGPIS -+ RXUCGPIS -+ 17 -+ 1 -+ read-only -+ -+ -+ RXLPIUSCIS -+ RXLPIUSCIS -+ 26 -+ 1 -+ read-only -+ -+ -+ RXLPITRCIS -+ RXLPITRCIS -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ MMC_TX_INTERRUPT -+ MMC_TX_INTERRUPT -+ This register maintains the interrupts -+ generated from all Transmit statistics counters. The MMC -+ Transmit Interrupt register maintains the interrupts -+ generated when transmit statistic counters reach half -+ their maximum values (0x8000_0000 for 32 bit counter and -+ 0x8000 for 16 bit counter), and when they cross their -+ maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF -+ for 16-bit counter). When Counter Stop Rollover is set, -+ the interrupts are set but the counter remains at -+ all-ones. The MMC Transmit Interrupt register is a 32 bit -+ register. An interrupt bit is cleared when the respective -+ MMC counter that caused the interrupt is read. The least -+ significant byte lane (Bits[7:0]) of the respective -+ counter must be read to clear the interrupt -+ bit. -+ 0x708 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXSCOLGPIS -+ TXSCOLGPIS -+ 14 -+ 1 -+ read-only -+ -+ -+ TXMCOLGPIS -+ TXMCOLGPIS -+ 15 -+ 1 -+ read-only -+ -+ -+ TXGPKTIS -+ TXGPKTIS -+ 21 -+ 1 -+ read-only -+ -+ -+ TXLPIUSCIS -+ TXLPIUSCIS -+ 26 -+ 1 -+ read-only -+ -+ -+ TXLPITRCIS -+ TXLPITRCIS -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ MMC_RX_INTERRUPT_MASK -+ MMC_RX_INTERRUPT_MASK -+ The MMC Receive Interrupt Mask register -+ maintains the masks for the interrupts generated when -+ receive statistic counters reach half of their maximum -+ value or the maximum values. -+ 0x70C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXCRCERPIM -+ RXCRCERPIM -+ 5 -+ 1 -+ read-write -+ -+ -+ RXALGNERPIM -+ RXALGNERPIM -+ 6 -+ 1 -+ read-write -+ -+ -+ RXUCGPIM -+ RXUCGPIM -+ 17 -+ 1 -+ read-write -+ -+ -+ RXLPIUSCIM -+ RXLPIUSCIM -+ 26 -+ 1 -+ read-write -+ -+ -+ RXLPITRCIM -+ RXLPITRCIM -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ MMC_TX_INTERRUPT_MASK -+ MMC_TX_INTERRUPT_MASK -+ This register maintains the masks for -+ interrupts generated from all Transmit statistics -+ counters. The MMC Transmit Interrupt Mask register -+ maintains the masks for the interrupts generated when the -+ transmit statistic counters reach half of their maximum -+ value or the maximum values. This register is 32 bit -+ wide. This register is present only when any one of the -+ MMC Transmit Counters is selected during core -+ configuration. -+ 0x710 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXSCOLGPIM -+ TXSCOLGPIM -+ 14 -+ 1 -+ read-write -+ -+ -+ TXMCOLGPIM -+ TXMCOLGPIM -+ 15 -+ 1 -+ read-write -+ -+ -+ TXGPKTIM -+ TXGPKTIM -+ 21 -+ 1 -+ read-write -+ -+ -+ TXLPIUSCIM -+ TXLPIUSCIM -+ 26 -+ 1 -+ read-write -+ -+ -+ TXLPITRCIM -+ TXLPITRCIM -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ TX_SINGLE_COLLISION_GOOD_PACKETS -+ -+ TX_SINGLE_COLLISION_GOOD_PACKETS -+ This register provides the number of -+ successfully transmitted packets by Ethernet peripheral -+ after a single collision in the half-duplex -+ mode. -+ 0x74C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXSNGLCOLG -+ TXSNGLCOLG -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TX_MULTIPLE_COLLISION_GOOD_PACKETS -+ -+ TX_MULTIPLE_COLLISION_GOOD_PACKETS -+ This register provides the number of -+ successfully transmitted packets by Ethernet peripheral -+ after multiple collisions in the half-duplex -+ mode. -+ 0x750 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXMULTCOLG -+ TXMULTCOLG -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TX_PACKET_COUNT_GOOD -+ TX_PACKET_COUNT_GOOD -+ This register provides the number of good -+ packets transmitted by Ethernet peripheral. -+ 0x768 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXPKTG -+ TXPKTG -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ RX_CRC_ERROR_PACKETS -+ RX_CRC_ERROR_PACKETS -+ This register provides the number of packets -+ received by Ethernet peripheral with CRC -+ error. -+ 0x794 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXCRCERR -+ RXCRCERR -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ RX_ALIGNMENT_ERROR_PACKETS -+ RX_ALIGNMENT_ERROR_PACKETS -+ This register provides the number of packets -+ received by Ethernet peripheral with alignment (dribble) -+ error. It is valid only in 10/100 mode. -+ 0x798 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXALGNERR -+ RXALGNERR -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ RX_UNICAST_PACKETS_GOOD -+ RX_UNICAST_PACKETS_GOOD -+ This register provides the number of good -+ unicast packets received by Ethernet -+ peripheral. -+ 0x7C4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXUCASTG -+ RXUCASTG -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TX_LPI_USEC_CNTR -+ TX_LPI_USEC_CNTR -+ This register provides the number of -+ microseconds Tx LPI is asserted by Ethernet -+ peripheral. -+ 0x7EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXLPIUSC -+ TXLPIUSC -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TX_LPI_TRAN_CNTR -+ TX_LPI_TRAN_CNTR -+ This register provides the number of times -+ Ethernet peripheral has entered Tx LPI. -+ 0x7F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXLPITRC -+ TXLPITRC -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ RX_LPI_USEC_CNTR -+ RX_LPI_USEC_CNTR -+ This register provides the number of -+ microseconds Rx LPI is sampled by Ethernet -+ peripheral. -+ 0x7F4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXLPIUSC -+ RXLPIUSC -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ RX_LPI_TRAN_CNTR -+ RX_LPI_TRAN_CNTR -+ This register provides the number of times -+ Ethernet peripheral has entered Rx LPI. -+ 0x7F8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXLPITRC -+ RXLPITRC -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ ETH_MACL3L4C0R -+ ETH_MACL3L4C0R -+ The Layer 3 and Layer 4 Control register -+ controls the operations of filter 0 of Layer 3 and Layer -+ 4. This register is reserved if the Layer 3 and Layer 4 -+ Filtering feature is not selected during core -+ configuration. -+ 0x900 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3PEN0 -+ L3PEN0 -+ 0 -+ 1 -+ read-write -+ -+ -+ L3SAM0 -+ L3SAM0 -+ 2 -+ 1 -+ read-write -+ -+ -+ L3SAIM0 -+ L3SAIM0 -+ 3 -+ 1 -+ read-write -+ -+ -+ L3DAM0 -+ L3DAM0 -+ 4 -+ 1 -+ read-write -+ -+ -+ L3DAIM0 -+ L3DAIM0 -+ 5 -+ 1 -+ read-write -+ -+ -+ L3HSBM0 -+ L3HSBM0 -+ 6 -+ 5 -+ read-write -+ -+ -+ L3HDBM0 -+ L3HDBM0 -+ 11 -+ 5 -+ read-write -+ -+ -+ L4PEN0 -+ L4PEN0 -+ 16 -+ 1 -+ read-write -+ -+ -+ L4SPM0 -+ L4SPM0 -+ 18 -+ 1 -+ read-write -+ -+ -+ L4SPIM0 -+ L4SPIM0 -+ 19 -+ 1 -+ read-write -+ -+ -+ L4DPM0 -+ L4DPM0 -+ 20 -+ 1 -+ read-write -+ -+ -+ L4DPIM0 -+ L4DPIM0 -+ 21 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACL4A0R -+ ETH_MACL4A0R -+ Layer4 address filter 0 -+ register -+ 0x904 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L4SP0 -+ L4SP0 -+ 0 -+ 16 -+ read-write -+ -+ -+ L4DP0 -+ L4DP0 -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A00R -+ ETH_MACL3A00R -+ For IPv4 packets, the Layer 3 Address 0 -+ Register 0 register contains the 32-bit IP Source Address -+ field. For IPv6 packets, it contains Bits[31:0] of the -+ 128-bit IP Source Address or Destination Address -+ field. -+ 0x910 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A00 -+ L3A00 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A10R -+ ETH_MACL3A10R -+ For IPv4 packets, the Layer 3 Address 1 -+ Register 0 register contains the 32-bit IP Destination -+ Address field. For IPv6 packets, it contains Bits[63:32] -+ of the 128-bit IP Source Address or Destination Address -+ field. -+ 0x914 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A10 -+ L3A10 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A20 -+ ETH_MACL3A20 -+ The Layer 3 Address 2 Register 0 register is -+ reserved for IPv4 packets. For IPv6 packets, it contains -+ Bits[95:64] of 128-bit IP Source Address or Destination -+ Address field. -+ 0x918 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A20 -+ L3A20 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A30 -+ ETH_MACL3A30 -+ The Layer 3 Address 3 Register 0 register is -+ reserved for IPv4 packets. For IPv6 packets, it contains -+ Bits[127:96] of 128-bit IP Source Address or Destination -+ Address field. -+ 0x91C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A30 -+ L3A30 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3L4C1R -+ ETH_MACL3L4C1R -+ The Layer 3 and Layer 4 Control register -+ controls the operations of filter 0 of Layer 3 and Layer -+ 4. -+ 0x930 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3PEN1 -+ L3PEN1 -+ 0 -+ 1 -+ read-write -+ -+ -+ L3SAM1 -+ L3SAM1 -+ 2 -+ 1 -+ read-write -+ -+ -+ L3SAIM1 -+ L3SAIM1 -+ 3 -+ 1 -+ read-write -+ -+ -+ L3DAM1 -+ L3DAM1 -+ 4 -+ 1 -+ read-write -+ -+ -+ L3DAIM1 -+ L3DAIM1 -+ 5 -+ 1 -+ read-write -+ -+ -+ L3HSBM1 -+ L3HSBM1 -+ 6 -+ 5 -+ read-write -+ -+ -+ L3HDBM1 -+ L3HDBM1 -+ 11 -+ 5 -+ read-write -+ -+ -+ L4PEN1 -+ L4PEN1 -+ 16 -+ 1 -+ read-write -+ -+ -+ L4SPM1 -+ L4SPM1 -+ 18 -+ 1 -+ read-write -+ -+ -+ L4SPIM1 -+ L4SPIM1 -+ 19 -+ 1 -+ read-write -+ -+ -+ L4DPM1 -+ L4DPM1 -+ 20 -+ 1 -+ read-write -+ -+ -+ L4DPIM1 -+ L4DPIM1 -+ 21 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACL4A1R -+ ETH_MACL4A1R -+ The Layer 4 Address 0 register and registers -+ 580 through 667 are reserved (RO with default value) if -+ Enable Layer 3 and Layer 4 Packet Filter option is not -+ selected while configuring the core. You can configure -+ the Layer 3 and Layer 4 Address Registers to be -+ double-synchronized by selecting the Synchronize Layer 3 -+ and Layer 4 Address Registers to Rx Clock Domain option -+ while configuring the core. When you select this option, -+ the synchronization is triggered only when Bits[31:24] -+ (in little-endian mode) or Bits[7:0] (in big-endian mode) -+ of the Layer 3 and Layer 4 Address Registers are written. -+ For proper synchronization updates, you should perform -+ consecutive writes to same Layer 3 and Layer 4 Address -+ Registers after at least four clock cycles delay of the -+ destination clock. -+ 0x934 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L4SP1 -+ L4SP1 -+ 0 -+ 16 -+ read-write -+ -+ -+ L4DP1 -+ L4DP1 -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A01R -+ ETH_MACL3A01R -+ For IPv4 packets, the Layer 3 Address 0 -+ Register 0 register contains the 32-bit IP Source Address -+ field. For IPv6 packets, it contains Bits[31:0] of the -+ 128-bit IP Source Address or Destination Address -+ field. -+ 0x940 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A01 -+ L3A01 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A11R -+ ETH_MACL3A11R -+ For IPv4 packets, the Layer 3 Address 1 -+ Register 0 register contains the 32-bit IP Destination -+ Address field. For IPv6 packets, it contains Bits[63:32] -+ of the 128-bit IP Source Address or Destination Address -+ field. -+ 0x944 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A11 -+ L3A11 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A21R -+ ETH_MACL3A21R -+ The Layer 3 Address 2 Register 0 register is -+ reserved for IPv4 packets. For IPv6 packets, it contains -+ Bits[95:64] of 128-bit IP Source Address or Destination -+ Address field. -+ 0x948 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A21 -+ L3A21 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACL3A31R -+ ETH_MACL3A31R -+ The Layer 3 Address 3 Register 0 register is -+ reserved for IPv4 packets. For IPv6 packets, it contains -+ Bits[127:96] of 128-bit IP Source Address or Destination -+ Address field. -+ 0x94C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ L3A31 -+ L3A31 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACARPAR -+ ETH_MACARPAR -+ The ARP Address register contains the IPv4 -+ Destination Address of the MAC. -+ 0xAE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ARPPA -+ ARPPA -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSCR -+ ETH_MACTSCR -+ This register controls the operation of the -+ System Time generator and processing of PTP packets for -+ timestamping in the Receiver. -+ 0xB00 -+ 0x20 -+ read-write -+ 0x00002000 -+ -+ -+ TSENA -+ TSENA -+ 0 -+ 1 -+ read-write -+ -+ -+ TSCFUPDT -+ TSCFUPDT -+ 1 -+ 1 -+ read-write -+ -+ -+ TSINIT -+ TSINIT -+ 2 -+ 1 -+ read-write -+ -+ -+ TSUPDT -+ TSUPDT -+ 3 -+ 1 -+ read-write -+ -+ -+ TSADDREG -+ TSADDREG -+ 5 -+ 1 -+ read-write -+ -+ -+ TSENALL -+ TSENALL -+ 8 -+ 1 -+ read-write -+ -+ -+ TSCTRLSSR -+ TSCTRLSSR -+ 9 -+ 1 -+ read-write -+ -+ -+ TSVER2ENA -+ TSVER2ENA -+ 10 -+ 1 -+ read-write -+ -+ -+ TSIPENA -+ TSIPENA -+ 11 -+ 1 -+ read-write -+ -+ -+ TSIPV6ENA -+ TSIPV6ENA -+ 12 -+ 1 -+ read-write -+ -+ -+ TSIPV4ENA -+ TSIPV4ENA -+ 13 -+ 1 -+ read-write -+ -+ -+ TSEVNTENA -+ TSEVNTENA -+ 14 -+ 1 -+ read-write -+ -+ -+ TSMSTRENA -+ TSMSTRENA -+ 15 -+ 1 -+ read-write -+ -+ -+ SNAPTYPSEL -+ SNAPTYPSEL -+ 16 -+ 2 -+ read-write -+ -+ -+ TSENMACADDR -+ TSENMACADDR -+ 18 -+ 1 -+ read-write -+ -+ -+ CSC -+ CSC -+ 19 -+ 1 -+ read-only -+ -+ -+ TXTSSTSM -+ TXTSSTSM -+ 24 -+ 1 -+ read-write -+ -+ -+ AV8021ASMEN -+ AV8021ASMEN -+ 28 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACSSIR -+ ETH_MACSSIR -+ The Sub-second Increment register is present -+ only when the IEEE 1588 timestamp feature is selected -+ without an external timestamp input. In Coarse Update -+ mode [Bit 1 in ETH_MACTSCR register, the value in this -+ register is added to the system time every clock cycle of -+ HCLK. In Fine Update mode, the value in this register is -+ added to the system time whenever the Accumulator gets an -+ overflow. -+ 0xB04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SNSINC -+ SNSINC -+ 8 -+ 8 -+ read-write -+ -+ -+ SSINC -+ SSINC -+ 16 -+ 8 -+ read-write -+ -+ -+ -+ -+ ETH_MACSTSR -+ ETH_MACSTSR -+ The System Time Seconds register, along with -+ System Time Nanoseconds register, indicates the current -+ value of the system time maintained by the MAC. Though it -+ is updated on a continuous basis, there is some delay -+ from the actual time because of clock domain transfer -+ latencies (from HCLK to CSR clock). This register is -+ present only when the IEEE 1588 Timestamp feature is -+ selected without external timestamp input. -+ 0xB08 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TSS -+ TSS -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ ETH_MACSTNR -+ ETH_MACSTNR -+ The System Time Nanoseconds register, along -+ with System Time Seconds register, indicates the current -+ value of the system time maintained by the MAC. This -+ register is present only when the IEEE 1588 Timestamp -+ feature is selected without external timestamp -+ input. -+ 0xB0C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TSSS -+ TSSS -+ 0 -+ 31 -+ read-only -+ -+ -+ -+ -+ ETH_MACSTSUR -+ ETH_MACSTSUR -+ The System Time Seconds Update register, -+ along with the System Time Nanoseconds Update register, -+ initializes or updates the system time maintained by the -+ MAC. You must write both registers before setting the -+ TSINIT or TSUPDT bits in ETH_MACTSCR register. This -+ register is present only when the IEEE 1588 Timestamp -+ feature is selected without external timestamp -+ input. -+ 0xB10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSS -+ TSS -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACSTNUR -+ ETH_MACSTNUR -+ This register is present only when the IEEE -+ 1588 timestamp feature is selected without external -+ timestamp input. -+ 0xB14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSSS -+ TSSS -+ 0 -+ 31 -+ read-write -+ -+ -+ ADDSUB -+ ADDSUB -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSAR -+ ETH_MACTSAR -+ The Timestamp Addend register is present -+ only when the IEEE 1588 Timestamp feature is selected -+ without external timestamp input. This register value is -+ used only when the system time is configured for Fine -+ Update mode (TSCFUPDT bit in the ETH_MACTSCR register). -+ The content of this register is added to a 32-bit -+ accumulator in every clock cycle (of HCLK) and the system -+ time is updated whenever the accumulator -+ overflows. -+ 0xB18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSAR -+ TSAR -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSSR -+ ETH_MACTSSR -+ The Timestamp Status register is present -+ only when the IEEE 1588 Timestamp feature is selected. -+ All bits except Bits[27:25] gets cleared when the -+ application reads this register. -+ 0xB20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TSSOVF -+ TSSOVF -+ 0 -+ 1 -+ read-only -+ -+ -+ TSTARGT0 -+ TSTARGT0 -+ 1 -+ 1 -+ read-only -+ -+ -+ AUXTSTRIG -+ AUXTSTRIG -+ 2 -+ 1 -+ read-only -+ -+ -+ TSTRGTERR0 -+ TSTRGTERR0 -+ 3 -+ 1 -+ read-only -+ -+ -+ TXTSSIS -+ TXTSSIS -+ 15 -+ 1 -+ read-only -+ -+ -+ ATSSTN -+ ATSSTN -+ 16 -+ 4 -+ read-only -+ -+ -+ ATSSTM -+ ATSSTM -+ 24 -+ 1 -+ read-only -+ -+ -+ ATSNS -+ ATSNS -+ 25 -+ 5 -+ read-only -+ -+ -+ -+ -+ ETH_MACTxTSSNR -+ ETH_MACTxTSSNR -+ This register contains the nanosecond part -+ of timestamp captured for Transmit packets when Tx status -+ is disabled. -+ 0xB30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXTSSLO -+ TXTSSLO -+ 0 -+ 31 -+ read-only -+ -+ -+ TXTSSMIS -+ TXTSSMIS -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MACTxTSSSR -+ ETH_MACTxTSSSR -+ The register contains the higher 32 bits of -+ the timestamp (in seconds) captured when a PTP packet is -+ transmitted. -+ 0xB34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXTSSHI -+ TXTSSHI -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ ETH_MACACR -+ ETH_MACACR -+ The Auxiliary Timestamp Control register -+ controls the Auxiliary Timestamp snapshot. -+ 0xB40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ATSFC -+ ATSFC -+ 0 -+ 1 -+ read-write -+ -+ -+ ATSEN0 -+ ATSEN0 -+ 4 -+ 1 -+ read-write -+ -+ -+ ATSEN1 -+ ATSEN1 -+ 5 -+ 1 -+ read-write -+ -+ -+ ATSEN2 -+ ATSEN2 -+ 6 -+ 1 -+ read-write -+ -+ -+ ATSEN3 -+ ATSEN3 -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACATSNR -+ ETH_MACATSNR -+ The Auxiliary Timestamp Nanoseconds -+ register, along with ETH_MACATSSR, gives the 64-bit -+ timestamp stored as auxiliary snapshot. These two -+ registers form the read port of a 64-bit wide FIFO with a -+ depth of 4 words. You can store multiple snapshots in -+ this FIFO. Bits[29:25] in ETH_MACTSSR indicate the -+ fill-level of the FIFO. The top of the FIFO is removed -+ only when the last byte of MAC Register 91 (Auxiliary -+ Timestamp - Seconds Register) is read. In the -+ little-endian mode, this means when Bits[31:24] are read -+ and in big-endian mode, Bits[7:0] are read. -+ 0xB48 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AUXTSLO -+ AUXTSLO -+ 0 -+ 31 -+ read-only -+ -+ -+ -+ -+ ETH_MACATSSR -+ ETH_MACATSSR -+ The Auxiliary Timestamp - Seconds register -+ contains the lower 32 bits of the Seconds field of the -+ auxiliary timestamp register. -+ 0xB4C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AUXTSHI -+ AUXTSHI -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ ETH_MACTSIACR -+ ETH_MACTSIACR -+ The MAC Timestamp Ingress Asymmetry -+ Correction register contains the Ingress Asymmetry -+ Correction value to be used while updating correction -+ field in PDelay_Resp PTP messages. -+ 0xB50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSTIAC -+ OSTIAC -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSEACR -+ ETH_MACTSEACR -+ The MAC Timestamp Egress Asymmetry -+ Correction register contains the Egress Asymmetry -+ Correction value to be used while updating the correction -+ field in PDelay_Req PTP messages. -+ 0xB54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSTEAC -+ OSTEAC -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSICNR -+ ETH_MACTSICNR -+ This register contains the correction value -+ in nanoseconds to be used with the captured timestamp -+ value in the ingress path. -+ 0xB58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSIC -+ TSIC -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACTSECNR -+ ETH_MACTSECNR -+ This register contains the correction value -+ in nanoseconds to be used with the captured timestamp -+ value in the egress path. -+ 0xB5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEC -+ TSEC -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACPPSCR -+ ETH_MACPPSCR -+ The PPS Control register is present only -+ when the Timestamp feature is selected and External -+ Timestamp is not enabled. Bits[30:24] of this register -+ are valid only when four Flexible PPS outputs are -+ selected. Bits[22:16] are valid only when three or more -+ Flexible PPS outputs are selected. Bits[14:8] are valid -+ only when two or more Flexible PPS outputs are selected. -+ Bits[6:4] are valid only when Flexible PPS feature is -+ selected. -+ 0xB70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PPSCTRL -+ PPSCTRL -+ 0 -+ 4 -+ read-write -+ -+ -+ PPSEN0 -+ PPSEN0 -+ 4 -+ 1 -+ read-write -+ -+ -+ TRGTMODSEL0 -+ TRGTMODSEL0 -+ 5 -+ 2 -+ read-write -+ -+ -+ -+ -+ ETH_MACPPSTTSR -+ ETH_MACPPSTTSR -+ The PPS Target Time Seconds register, along -+ with PPS Target Time Nanoseconds register, is used to -+ schedule an interrupt event [Bit 1 of ETH_MACTSSR] when -+ the system time exceeds the value programmed in these -+ registers. -+ 0xB80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSTRH0 -+ TSTRH0 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACPPSTTNR -+ ETH_MACPPSTTNR -+ The PPS Target Time Nanoseconds register is -+ present only when more than one Flexible PPS output is -+ selected. -+ 0xB84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TTSL0 -+ TTSL0 -+ 0 -+ 31 -+ read-write -+ -+ -+ TRGTBUSY0 -+ TRGTBUSY0 -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MACPPSIR -+ ETH_MACPPSIR -+ The PPS Interval register contains the -+ number of units of sub-second increment value between the -+ rising edges of PPS signal output -+ (ptp_pps_o[0]). -+ 0xB88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PPSINT0 -+ PPSINT0 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACPPSWR -+ ETH_MACPPSWR -+ The PPS Width register contains the number -+ of units of sub-second increment value between the rising -+ and corresponding falling edges of PPS signal output -+ (ptp_pps_o). -+ 0xB8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PPSWIDTH0 -+ PPSWIDTH0 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACPOCR -+ ETH_MACPOCR -+ This register controls the PTP Offload -+ Engine operation. This register is available only when -+ the Enable PTP Timestamp Offload feature is -+ selected. -+ 0xBC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PTOEN -+ PTOEN -+ 0 -+ 1 -+ read-write -+ -+ -+ ASYNCEN -+ ASYNCEN -+ 1 -+ 1 -+ read-write -+ -+ -+ APDREQEN -+ APDREQEN -+ 2 -+ 1 -+ read-write -+ -+ -+ ASYNCTRIG -+ ASYNCTRIG -+ 4 -+ 1 -+ read-write -+ -+ -+ APDREQTRIG -+ APDREQTRIG -+ 5 -+ 1 -+ read-write -+ -+ -+ DRRDIS -+ DRRDIS -+ 6 -+ 1 -+ read-write -+ -+ -+ DN -+ DN -+ 8 -+ 8 -+ read-write -+ -+ -+ -+ -+ ETH_MACSPI0R -+ ETH_MACSPI0R -+ This register contains Bits[31:0] of the -+ 80-bit Source Port Identity of the PTP node. This -+ register is available only when the Enable PTP Timestamp -+ Offload feature is selected. -+ 0xBC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI0 -+ SPI0 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACSPI1R -+ ETH_MACSPI1R -+ This register contains Bits[63:32] of the -+ 80-bit Source Port Identity of the PTP node. This -+ register is available only when the Enable PTP Timestamp -+ Offload feature is selected. -+ 0xBC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI1 -+ SPI1 -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ ETH_MACSPI2R -+ ETH_MACSPI2R -+ This register contains Bits[79:64] of the -+ 80-bit Source Port Identity of the PTP -+ node. -+ 0xBCC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI2 -+ SPI2 -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ ETH_MACLMIR -+ ETH_MACLMIR -+ This register contains the periodic -+ intervals for automatic PTP packet -+ generation. -+ 0xBD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LSI -+ LSI -+ 0 -+ 8 -+ read-write -+ -+ -+ DRSYNCR -+ DRSYNCR -+ 8 -+ 3 -+ read-write -+ -+ -+ LMPDRI -+ LMPDRI -+ 24 -+ 8 -+ read-write -+ -+ -+ -+ -+ -+ -+ ETH_MTL -+ ETH_MTL -+ Ethernet -+ 0x5800AC00 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ ETH_MTLOMR -+ ETH_MTLOMR -+ The Operating Mode register establishes the -+ Transmit and Receive operating modes and -+ commands. -+ 0x000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTXSTS -+ DTXSTS -+ 1 -+ 1 -+ read-write -+ -+ -+ RAA -+ RAA -+ 2 -+ 1 -+ read-write -+ -+ -+ SCHALG -+ SCHALG -+ 5 -+ 2 -+ read-write -+ -+ -+ CNTPRST -+ CNTPRST -+ 8 -+ 1 -+ read-write -+ -+ -+ CNTCLR -+ CNTCLR -+ 9 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MTLISR -+ ETH_MTLISR -+ The software driver (application) reads this -+ register during interrupt service routine or polling to -+ determine the interrupt status of MTL queues and the -+ MAC. -+ 0x020 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ Q0IS -+ Q0IS -+ 0 -+ 1 -+ read-only -+ -+ -+ Q1IS -+ Q1IS -+ 1 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ0OMR -+ ETH_MTLTxQ0OMR -+ Tx queue 0 operating mode -+ Register -+ 0x0100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FTQ -+ FTQ -+ 0 -+ 1 -+ read-write -+ -+ -+ TSF -+ TSF -+ 1 -+ 1 -+ read-write -+ -+ -+ TXQEN -+ TXQEN -+ 2 -+ 2 -+ read-write -+ -+ -+ TTC -+ TTC -+ 4 -+ 2 -+ read-write -+ -+ -+ TQS -+ TQS -+ 16 -+ 9 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ1OMR -+ ETH_MTLTxQ1OMR -+ Tx queue 1 operating mode -+ Register -+ 0x0140 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FTQ -+ FTQ -+ 0 -+ 1 -+ read-write -+ -+ -+ TSF -+ TSF -+ 1 -+ 1 -+ read-write -+ -+ -+ TXQEN -+ TXQEN -+ 2 -+ 2 -+ read-write -+ -+ -+ TTC -+ TTC -+ 4 -+ 2 -+ read-write -+ -+ -+ TQS -+ TQS -+ 16 -+ 9 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ0UR -+ ETH_MTLTxQ0UR -+ Tx queue 0 underflow register -+ 0x0104 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ UFFRMCNT -+ UFFRMCNT -+ 0 -+ 11 -+ read-only -+ -+ -+ UFCNTOVF -+ UFCNTOVF -+ 11 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ1UR -+ ETH_MTLTxQ1UR -+ Tx queue 1 underflow register -+ 0x0144 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ UFFRMCNT -+ UFFRMCNT -+ 0 -+ 11 -+ read-only -+ -+ -+ UFCNTOVF -+ UFCNTOVF -+ 11 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ0DR -+ ETH_MTLTxQ0DR -+ Tx queue 0 underflow register -+ 0x0108 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXQPAUSED -+ TXQPAUSED -+ 0 -+ 1 -+ read-only -+ -+ -+ TRCSTS -+ TRCSTS -+ 1 -+ 2 -+ read-only -+ -+ -+ TWCSTS -+ TWCSTS -+ 3 -+ 1 -+ read-only -+ -+ -+ TXQSTS -+ TXQSTS -+ 4 -+ 1 -+ read-only -+ -+ -+ TXSTSFSTS -+ TXSTSFSTS -+ 5 -+ 1 -+ read-only -+ -+ -+ PTXQ -+ PTXQ -+ 16 -+ 3 -+ read-only -+ -+ -+ STXSTSF -+ STXSTSF -+ 20 -+ 3 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ1DR -+ ETH_MTLTxQ1DR -+ Tx queue 1 underflow register -+ 0x0148 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXQPAUSED -+ TXQPAUSED -+ 0 -+ 1 -+ read-only -+ -+ -+ TRCSTS -+ TRCSTS -+ 1 -+ 2 -+ read-only -+ -+ -+ TWCSTS -+ TWCSTS -+ 3 -+ 1 -+ read-only -+ -+ -+ TXQSTS -+ TXQSTS -+ 4 -+ 1 -+ read-only -+ -+ -+ TXSTSFSTS -+ TXSTSFSTS -+ 5 -+ 1 -+ read-only -+ -+ -+ PTXQ -+ PTXQ -+ 16 -+ 3 -+ read-only -+ -+ -+ STXSTSF -+ STXSTSF -+ 20 -+ 3 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ0ESR -+ ETH_MTLTxQ0ESR -+ Tx queue x ETS status Register -+ 0x0114 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ABS -+ ABS -+ 0 -+ 24 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ1ESR -+ ETH_MTLTxQ1ESR -+ Tx queue x ETS status Register -+ 0x0154 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ABS -+ ABS -+ 0 -+ 24 -+ read-only -+ -+ -+ -+ -+ ETH_MTLQ0ICSR -+ ETH_MTLQ0ICSR -+ Queue 0 interrupt control status -+ Register -+ 0x012C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXUNFIS -+ TXUNFIS -+ 0 -+ 1 -+ read-only -+ -+ -+ ABPSIS -+ ABPSIS -+ 1 -+ 1 -+ read-write -+ -+ -+ TXUIE -+ TXUIE -+ 8 -+ 1 -+ read-write -+ -+ -+ ABPSIE -+ ABPSIE -+ 9 -+ 1 -+ read-write -+ -+ -+ RXOVFIS -+ RXOVFIS -+ 16 -+ 1 -+ read-write -+ -+ -+ RXOIE -+ RXOIE -+ 24 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MTLQ1ICSR -+ ETH_MTLQ1ICSR -+ Queue 1 interrupt control status -+ Register -+ 0x016C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXUNFIS -+ TXUNFIS -+ 0 -+ 1 -+ read-only -+ -+ -+ ABPSIS -+ ABPSIS -+ 1 -+ 1 -+ read-write -+ -+ -+ TXUIE -+ TXUIE -+ 8 -+ 1 -+ read-write -+ -+ -+ ABPSIE -+ ABPSIE -+ 9 -+ 1 -+ read-write -+ -+ -+ RXOVFIS -+ RXOVFIS -+ 16 -+ 1 -+ read-write -+ -+ -+ RXOIE -+ RXOIE -+ 24 -+ 1 -+ read-write -+ -+ -+ -+ -+ ETH_MTLRxQ0OMR -+ ETH_MTLRxQ0OMR -+ Rx queue 0 operating mode -+ register -+ 0x0130 -+ 0x20 -+ read-write -+ 0x00700000 -+ -+ -+ RTC -+ RTC -+ 0 -+ 2 -+ read-write -+ -+ -+ FUP -+ FUP -+ 3 -+ 1 -+ read-write -+ -+ -+ FEP -+ FEP -+ 4 -+ 1 -+ read-write -+ -+ -+ RSF -+ RSF -+ 5 -+ 1 -+ read-write -+ -+ -+ DIS_TCP_EF -+ DIS_TCP_EF -+ 6 -+ 1 -+ read-write -+ -+ -+ EHFC -+ EHFC -+ 7 -+ 1 -+ read-write -+ -+ -+ RFA -+ RFA -+ 8 -+ 3 -+ read-write -+ -+ -+ RFD -+ RFD -+ 14 -+ 3 -+ read-write -+ -+ -+ RQS -+ RQS -+ 20 -+ 4 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ1OMR -+ ETH_MTLRxQ1OMR -+ Rx queue 1 operating mode -+ register -+ 0x0170 -+ 0x20 -+ read-write -+ 0x00700000 -+ -+ -+ RTC -+ RTC -+ 0 -+ 2 -+ read-write -+ -+ -+ FUP -+ FUP -+ 3 -+ 1 -+ read-write -+ -+ -+ FEP -+ FEP -+ 4 -+ 1 -+ read-write -+ -+ -+ RSF -+ RSF -+ 5 -+ 1 -+ read-write -+ -+ -+ DIS_TCP_EF -+ DIS_TCP_EF -+ 6 -+ 1 -+ read-write -+ -+ -+ EHFC -+ EHFC -+ 7 -+ 1 -+ read-write -+ -+ -+ RFA -+ RFA -+ 8 -+ 3 -+ read-write -+ -+ -+ RFD -+ RFD -+ 14 -+ 3 -+ read-write -+ -+ -+ RQS -+ RQS -+ 20 -+ 4 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ0MPOCR -+ ETH_MTLRxQ0MPOCR -+ Rx queue 0 missed packet and overflow -+ counter register -+ 0x0134 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OVFPKTCNT -+ OVFPKTCNT -+ 0 -+ 11 -+ read-only -+ -+ -+ OVFCNTOVF -+ OVFCNTOVF -+ 11 -+ 1 -+ read-only -+ -+ -+ MISPKTCNT -+ MISPKTCNT -+ 16 -+ 11 -+ read-only -+ -+ -+ MISCNTOVF -+ MISCNTOVF -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ1MPOCR -+ ETH_MTLRxQ1MPOCR -+ Rx queue 1 missed packet and overflow -+ counter register -+ 0x0174 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OVFPKTCNT -+ OVFPKTCNT -+ 0 -+ 11 -+ read-only -+ -+ -+ OVFCNTOVF -+ OVFCNTOVF -+ 11 -+ 1 -+ read-only -+ -+ -+ MISPKTCNT -+ MISPKTCNT -+ 16 -+ 11 -+ read-only -+ -+ -+ MISCNTOVF -+ MISCNTOVF -+ 27 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ0DR -+ ETH_MTLRxQ0DR -+ Rx queue i debug register -+ 0x0138 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RWCSTS -+ RWCSTS -+ 0 -+ 1 -+ read-only -+ -+ -+ RRCSTS -+ RRCSTS -+ 1 -+ 2 -+ read-only -+ -+ -+ RXQSTS -+ RXQSTS -+ 4 -+ 2 -+ read-only -+ -+ -+ PRXQ -+ PRXQ -+ 16 -+ 14 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ1DR -+ ETH_MTLRxQ1DR -+ Rx queue i debug register -+ 0x0178 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RWCSTS -+ RWCSTS -+ 0 -+ 1 -+ read-only -+ -+ -+ RRCSTS -+ RRCSTS -+ 1 -+ 2 -+ read-only -+ -+ -+ RXQSTS -+ RXQSTS -+ 4 -+ 2 -+ read-only -+ -+ -+ PRXQ -+ PRXQ -+ 16 -+ 14 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ0CR -+ ETH_MTLRxQ0CR -+ Rx queue 0 control register -+ 0x013C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXQ_WEGT -+ RXQ_WEGT -+ 0 -+ 3 -+ read-only -+ -+ -+ RXQ_FRM_ARBIT -+ RXQ_FRM_ARBIT -+ 3 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLRxQ1CR -+ ETH_MTLRxQ1CR -+ Rx queue 1 control register -+ 0x017C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXQ_WEGT -+ RXQ_WEGT -+ 0 -+ 3 -+ read-only -+ -+ -+ RXQ_FRM_ARBIT -+ RXQ_FRM_ARBIT -+ 3 -+ 1 -+ read-only -+ -+ -+ -+ -+ ETH_MTLTxQ1ECR -+ ETH_MTLTxQ1ECR -+ The Queue ETS Control register controls the -+ enhanced transmission selection operation. -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AVALG -+ AVALG -+ 2 -+ 1 -+ read-write -+ -+ -+ CC -+ CC -+ 3 -+ 1 -+ read-write -+ -+ -+ SLC -+ SLC -+ 4 -+ 3 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ1QWR -+ ETH_MTLTxQ1QWR -+ This register provides the average traffic -+ transmitted on queue 1. -+ 0x158 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISCQW -+ ISCQW -+ 0 -+ 21 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ1SSCR -+ ETH_MTLTxQ1SSCR -+ The sendSlopeCredit register contains the -+ sendSlope credit value required for the credit-based -+ shaper algorithm for the Queue. -+ 0x15C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SSC -+ SSC -+ 0 -+ 14 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ1HCR -+ ETH_MTLTxQ1HCR -+ The hiCredit register contains the hiCredit -+ value required for the credit-based shaper algorithm for -+ the Queue. -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HC -+ HC -+ 0 -+ 29 -+ read-write -+ -+ -+ -+ -+ ETH_MTLTxQ1LCR -+ ETH_MTLTxQ1LCR -+ The loCredit register contains the loCredit -+ value required for the credit-based shaper algorithm for -+ the Queue. -+ 0x164 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LC -+ LC -+ 0 -+ 29 -+ read-write -+ -+ -+ -+ -+ -+ -+ ETH_DMA -+ ETH_DMA -+ Ethernet -+ 0x5800B000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ ETH_DMAMR -+ ETH_DMAMR -+ DMA mode register -+ 0x0000 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ SWR -+ Software Reset -+ 0 -+ 1 -+ -+ -+ TAA -+ TAA -+ 2 -+ 3 -+ -+ -+ TXPR -+ Transmit priority -+ 11 -+ 1 -+ -+ -+ PR -+ Priority ratio -+ 12 -+ 3 -+ -+ -+ INTM -+ Interrupt Mode -+ 16 -+ 2 -+ -+ -+ -+ -+ ETH_DMASBMR -+ ETH_DMASBMR -+ System bus mode register -+ 0x0004 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ FB -+ Fixed Burst Length -+ 0 -+ 1 -+ -+ -+ BLEN4 -+ BLEN4 -+ 1 -+ 1 -+ -+ -+ BLEN8 -+ BLEN8 -+ 2 -+ 1 -+ -+ -+ BLEN16 -+ BLEN16 -+ 3 -+ 1 -+ -+ -+ BLEN32 -+ BLEN32 -+ 4 -+ 1 -+ -+ -+ BLEN64 -+ BLEN64 -+ 5 -+ 1 -+ -+ -+ BLEN128 -+ BLEN128 -+ 6 -+ 1 -+ -+ -+ BLEN256 -+ BLEN256 -+ 7 -+ 1 -+ -+ -+ AAL -+ Address-Aligned Beats -+ 12 -+ 1 -+ -+ -+ ONEKBBE -+ ONEKBBE -+ 13 -+ 1 -+ -+ -+ RD_OSR_LMT -+ RD_OSR_LMT -+ 16 -+ 2 -+ -+ -+ WR_OSR_LMT -+ WR_OSR_LMT -+ 24 -+ 2 -+ -+ -+ LPI_XIT_PKT -+ LPI_XIT_PKT -+ 30 -+ 1 -+ -+ -+ EN_LPI -+ EN_LPI -+ 31 -+ 1 -+ -+ -+ -+ -+ ETH_DMAISR -+ ETH_DMAISR -+ Interrupt status register -+ 0x0008 -+ 0x20 -+ read-only -+ 0x0008000 -+ -+ -+ DC0IS -+ DMA Channel Interrupt -+ Status -+ 0 -+ 1 -+ -+ -+ DC1IS -+ DC1IS -+ 1 -+ 1 -+ -+ -+ MTLIS -+ MTL Interrupt Status -+ 16 -+ 1 -+ -+ -+ MACIS -+ MAC Interrupt Status -+ 17 -+ 1 -+ -+ -+ -+ -+ ETH_DMADSR -+ ETH_DMADSR -+ Debug status register -+ 0x000C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AXWHSTS -+ AHB Master Write Channel -+ 0 -+ 1 -+ -+ -+ AXRHSTS -+ AXRHSTS -+ 1 -+ 1 -+ -+ -+ RPS0 -+ RPS0 -+ 8 -+ 4 -+ -+ -+ TPS0 -+ TPS0 -+ 12 -+ 4 -+ -+ -+ RPS1 -+ RPS1 -+ 16 -+ 4 -+ -+ -+ TPS1 -+ TPS1 -+ 20 -+ 4 -+ -+ -+ -+ -+ ETH_DMAA4TxACR -+ ETH_DMAA4TxACR -+ AXI4 transmit channel ACE control -+ register -+ 0x0020 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TDRC -+ TDRC -+ 0 -+ 4 -+ -+ -+ TEC -+ TEC -+ 8 -+ 4 -+ -+ -+ THC -+ THC -+ 16 -+ 4 -+ -+ -+ -+ -+ ETH_DMAA4RxACR -+ ETH_DMAA4RxACR -+ AXI4 receive channel ACE control -+ register -+ 0x0024 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RDWC -+ RDWC -+ 0 -+ 4 -+ -+ -+ RPC -+ RPC -+ 8 -+ 4 -+ -+ -+ RHC -+ RHC -+ 16 -+ 4 -+ -+ -+ RDC -+ RDC -+ 24 -+ 2 -+ -+ -+ -+ -+ ETH_DMAA4DACR -+ ETH_DMAA4DACR -+ AXI4 descriptor ACE control -+ register -+ 0x0028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TDWC -+ TDWC -+ 0 -+ 4 -+ -+ -+ TDWD -+ TDWD -+ 4 -+ 2 -+ -+ -+ RDRC -+ RDRC -+ 8 -+ 4 -+ -+ -+ RDP -+ RDP -+ 16 -+ 3 -+ -+ -+ WRP -+ WRP -+ 20 -+ 3 -+ -+ -+ -+ -+ ETH_DMAC0CR -+ ETH_DMAC0CR -+ Channel 0 control register -+ 0x0100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MSS -+ MSS -+ 0 -+ 14 -+ -+ -+ PBLX8 -+ PBLX8 -+ 16 -+ 1 -+ -+ -+ DSL -+ DSL -+ 18 -+ 3 -+ -+ -+ -+ -+ ETH_DMAC1CR -+ ETH_DMAC1CR -+ Channel 1 control register -+ 0x0180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MSS -+ MSS -+ 0 -+ 14 -+ -+ -+ PBLX8 -+ PBLX8 -+ 16 -+ 1 -+ -+ -+ DSL -+ DSL -+ 18 -+ 3 -+ -+ -+ -+ -+ ETH_DMAC0TxCR -+ ETH_DMAC0TxCR -+ Channel 0 transmit control -+ register -+ 0x0104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ST -+ ST -+ 0 -+ 1 -+ -+ -+ TCW -+ TCW -+ 1 -+ 3 -+ -+ -+ OSF -+ OSF -+ 4 -+ 1 -+ -+ -+ TSE -+ TSE -+ 12 -+ 1 -+ -+ -+ TXPBL -+ TXPBL -+ 16 -+ 6 -+ -+ -+ TQOS -+ TQOS -+ 24 -+ 4 -+ -+ -+ -+ -+ ETH_DMAC1TxCR -+ ETH_DMAC1TxCR -+ Channel 1 transmit control -+ register -+ 0x0184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ST -+ ST -+ 0 -+ 1 -+ -+ -+ TCW -+ TCW -+ 1 -+ 3 -+ -+ -+ OSF -+ OSF -+ 4 -+ 1 -+ -+ -+ TSE -+ TSE -+ 12 -+ 1 -+ -+ -+ TXPBL -+ TXPBL -+ 16 -+ 6 -+ -+ -+ TQOS -+ TQOS -+ 24 -+ 4 -+ -+ -+ -+ -+ ETH_DMAC0RxCR -+ ETH_DMAC0RxCR -+ Channel receive control -+ register -+ 0x0108 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ SR -+ Start or Stop Receive -+ Command -+ 0 -+ 1 -+ -+ -+ RBSZ -+ Receive Buffer size -+ 1 -+ 14 -+ -+ -+ RXPBL -+ RXPBL -+ 16 -+ 6 -+ -+ -+ RQOS -+ RQOS -+ 24 -+ 4 -+ -+ -+ RPF -+ DMA Rx Channel Packet -+ Flush -+ 31 -+ 1 -+ -+ -+ -+ -+ ETH_DMAC0TxDLAR -+ ETH_DMAC0TxDLAR -+ Channel i Tx descriptor list address -+ register -+ 0x0114 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDESLA -+ Start of Transmit List -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC1TxDLAR -+ ETH_DMAC1TxDLAR -+ Channel i Tx descriptor list address -+ register -+ 0x0194 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDESLA -+ Start of Transmit List -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC0RxDLAR -+ ETH_DMAC0RxDLAR -+ Channel Rx descriptor list address -+ register -+ 0x011C -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ RDESLA -+ Start of Receive List -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC0TxDTPR -+ ETH_DMAC0TxDTPR -+ Channel Tx descriptor tail pointer -+ register -+ 0x0120 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDT -+ Transmit Descriptor Tail -+ Pointer -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC1TxDTPR -+ ETH_DMAC1TxDTPR -+ Channel Tx descriptor tail pointer -+ register -+ 0x01A0 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDT -+ Transmit Descriptor Tail -+ Pointer -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC0RxDTPR -+ ETH_DMAC0RxDTPR -+ Channel Rx descriptor tail pointer -+ register -+ 0x0128 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ RDT -+ Receive Descriptor Tail -+ Pointer -+ 3 -+ 29 -+ -+ -+ -+ -+ ETH_DMAC0TxRLR -+ ETH_DMAC0TxRLR -+ Channel Tx descriptor ring length -+ register -+ 0x012C -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDRL -+ Transmit Descriptor Ring -+ Length -+ 0 -+ 10 -+ -+ -+ -+ -+ ETH_DMAC1TxRLR -+ ETH_DMAC1TxRLR -+ Channel Tx descriptor ring length -+ register -+ 0x01AC -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TDRL -+ Transmit Descriptor Ring -+ Length -+ 0 -+ 10 -+ -+ -+ -+ -+ ETH_DMAC0RxRLR -+ ETH_DMAC0RxRLR -+ Channel Rx descriptor ring length -+ register -+ 0x0130 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ RDRL -+ Receive Descriptor Ring -+ Length -+ 0 -+ 10 -+ -+ -+ -+ -+ ETH_DMAC0IER -+ ETH_DMACIER -+ Channel interrupt enable -+ register -+ 0x0134 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ TIE -+ Transmit Interrupt Enable -+ 0 -+ 1 -+ -+ -+ TXSE -+ Transmit Stopped Enable -+ 1 -+ 1 -+ -+ -+ TBUE -+ Transmit Buffer Unavailable -+ Enable -+ 2 -+ 1 -+ -+ -+ RIE -+ Receive Interrupt Enable -+ 6 -+ 1 -+ -+ -+ RBUE -+ Receive Buffer Unavailable -+ Enable -+ 7 -+ 1 -+ -+ -+ RSE -+ Receive Stopped Enable -+ 8 -+ 1 -+ -+ -+ RWTE -+ Receive Watchdog Timeout -+ Enable -+ 9 -+ 1 -+ -+ -+ ETIE -+ Early Transmit Interrupt -+ Enable -+ 10 -+ 1 -+ -+ -+ ERIE -+ Early Receive Interrupt -+ Enable -+ 11 -+ 1 -+ -+ -+ FBEE -+ Fatal Bus Error Enable -+ 12 -+ 1 -+ -+ -+ CDEE -+ Context Descriptor Error -+ Enable -+ 13 -+ 1 -+ -+ -+ AIE -+ Abnormal Interrupt Summary -+ Enable -+ 14 -+ 1 -+ -+ -+ NIE -+ Normal Interrupt Summary -+ Enable -+ 15 -+ 1 -+ -+ -+ -+ -+ ETH_DMAC1IER -+ ETH_DMAC1IER -+ Channel interrupt enable -+ register -+ 0x01B4 -+ 0x20 -+ read-write -+ 0x0008000 -+ -+ -+ TIE -+ Transmit Interrupt Enable -+ 0 -+ 1 -+ -+ -+ TXSE -+ Transmit Stopped Enable -+ 1 -+ 1 -+ -+ -+ TBUE -+ Transmit Buffer Unavailable -+ Enable -+ 2 -+ 1 -+ -+ -+ RIE -+ Receive Interrupt Enable -+ 6 -+ 1 -+ -+ -+ RBUE -+ Receive Buffer Unavailable -+ Enable -+ 7 -+ 1 -+ -+ -+ RSE -+ Receive Stopped Enable -+ 8 -+ 1 -+ -+ -+ RWTE -+ Receive Watchdog Timeout -+ Enable -+ 9 -+ 1 -+ -+ -+ ETIE -+ Early Transmit Interrupt -+ Enable -+ 10 -+ 1 -+ -+ -+ ERIE -+ Early Receive Interrupt -+ Enable -+ 11 -+ 1 -+ -+ -+ FBEE -+ Fatal Bus Error Enable -+ 12 -+ 1 -+ -+ -+ CDEE -+ Context Descriptor Error -+ Enable -+ 13 -+ 1 -+ -+ -+ AIE -+ Abnormal Interrupt Summary -+ Enable -+ 14 -+ 1 -+ -+ -+ NIE -+ Normal Interrupt Summary -+ Enable -+ 15 -+ 1 -+ -+ -+ -+ -+ ETH_DMAC0RxIWTR -+ ETH_DMAC0RxIWTR -+ Channel Rx interrupt watchdog timer -+ register -+ 0x0138 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ RWT -+ Receive Interrupt Watchdog Timer -+ Count -+ 0 -+ 8 -+ -+ -+ -+ -+ ETH_DMAC0SFCSR -+ ETH_DMAC0SFCSR -+ Channel i slot function control status -+ register -+ 0x013C -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ ESC -+ ESC -+ 0 -+ 1 -+ -+ -+ ASC -+ ASC -+ 1 -+ 1 -+ -+ -+ RSN -+ RSN -+ 16 -+ 4 -+ -+ -+ -+ -+ ETH_DMAC1SFCSR -+ ETH_DMAC1SFCSR -+ Channel i slot function control status -+ register -+ 0x01BC -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ ESC -+ ESC -+ 0 -+ 1 -+ -+ -+ ASC -+ ASC -+ 1 -+ 1 -+ -+ -+ RSN -+ RSN -+ 16 -+ 4 -+ -+ -+ -+ -+ ETH_DMAC0CATxDR -+ ETH_DMAC0CATxDR -+ Channel current application transmit -+ descriptor register -+ 0x0144 -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURTDESAPTR -+ Application Transmit Descriptor Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC1CATxDR -+ ETH_DMAC1CATxDR -+ Channel current application transmit -+ descriptor register -+ 0x01C4 -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURTDESAPTR -+ Application Transmit Descriptor Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC0CARxDR -+ ETH_DMAC0CARxDR -+ Channel 0 current application receive -+ descriptor register -+ DMAC1CATxDR -+ 0x014C -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURRDESAPTR -+ Application Transmit Descriptor Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC0CATxBR -+ ETH_DMAC0CATxBR -+ Channel 0 current application transmit -+ buffer register -+ 0x0154 -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURTBUFAPTR -+ Application Transmit Buffer Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC1CATxBR -+ ETH_DMAC1CATxBR -+ Channel 0 current application transmit -+ buffer register -+ 0x01D4 -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURTBUFAPTR -+ Application Transmit Buffer Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC0CARxBR -+ ETH_DMACCARxBR -+ Channel current application receive buffer -+ register -+ 0x015C -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ CURRBUFAPTR -+ Application Receive Buffer Address -+ Pointer -+ 0 -+ 32 -+ -+ -+ -+ -+ ETH_DMAC0SR -+ ETH_DMAC0SR -+ Channel status register -+ 0x0160 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TI -+ Transmit Interrupt -+ 0 -+ 1 -+ -+ -+ TPS -+ Transmit Process Stopped -+ 1 -+ 1 -+ -+ -+ TBU -+ Transmit Buffer -+ Unavailable -+ 2 -+ 1 -+ -+ -+ RI -+ Receive Interrupt -+ 6 -+ 1 -+ -+ -+ RBU -+ Receive Buffer Unavailable -+ 7 -+ 1 -+ -+ -+ RPS -+ Receive Process Stopped -+ 8 -+ 1 -+ -+ -+ RWT -+ Receive Watchdog Timeout -+ 9 -+ 1 -+ -+ -+ ETI -+ Early Transmit Interrupt -+ 10 -+ 1 -+ -+ -+ ERI -+ Early Receive Interrupt -+ 11 -+ 1 -+ -+ -+ FBE -+ Fatal Bus Error -+ 12 -+ 1 -+ -+ -+ CDE -+ Context Descriptor Error -+ 13 -+ 1 -+ -+ -+ AIS -+ Abnormal Interrupt Summary -+ 14 -+ 1 -+ -+ -+ NIS -+ Normal Interrupt Summary -+ 15 -+ 1 -+ -+ -+ TEB -+ Tx DMA Error Bits -+ 16 -+ 3 -+ -+ -+ REB -+ Rx DMA Error Bits -+ 19 -+ 3 -+ -+ -+ -+ -+ ETH_DMAC1SR -+ ETH_DMAC1SR -+ Channel status register -+ 0x01E0 -+ 0x20 -+ read-write -+ 0x0000000 -+ -+ -+ TI -+ Transmit Interrupt -+ 0 -+ 1 -+ -+ -+ TPS -+ Transmit Process Stopped -+ 1 -+ 1 -+ -+ -+ TBU -+ Transmit Buffer -+ Unavailable -+ 2 -+ 1 -+ -+ -+ RI -+ Receive Interrupt -+ 6 -+ 1 -+ -+ -+ RBU -+ Receive Buffer Unavailable -+ 7 -+ 1 -+ -+ -+ RPS -+ Receive Process Stopped -+ 8 -+ 1 -+ -+ -+ RWT -+ Receive Watchdog Timeout -+ 9 -+ 1 -+ -+ -+ ETI -+ Early Transmit Interrupt -+ 10 -+ 1 -+ -+ -+ ERI -+ Early Receive Interrupt -+ 11 -+ 1 -+ -+ -+ FBE -+ Fatal Bus Error -+ 12 -+ 1 -+ -+ -+ CDE -+ Context Descriptor Error -+ 13 -+ 1 -+ -+ -+ AIS -+ Abnormal Interrupt Summary -+ 14 -+ 1 -+ -+ -+ NIS -+ Normal Interrupt Summary -+ 15 -+ 1 -+ -+ -+ TEB -+ Tx DMA Error Bits -+ 16 -+ 3 -+ -+ -+ REB -+ Rx DMA Error Bits -+ 19 -+ 3 -+ -+ -+ -+ -+ ETH_DMAC0MFCR -+ ETH_DMAC0MFCR -+ Channel missed frame count -+ register -+ 0x016C -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ MFC -+ Dropped Packet Counters -+ 0 -+ 11 -+ -+ -+ MFCO -+ Overflow status of the MFC -+ Counter -+ 15 -+ 1 -+ -+ -+ -+ -+ ETH_DMAC1MFCR -+ ETH_DMAC1MFCR -+ Channel missed frame count -+ register -+ 0x01EC -+ 0x20 -+ read-only -+ 0x0000000 -+ -+ -+ MFC -+ Dropped Packet Counters -+ 0 -+ 11 -+ -+ -+ MFCO -+ Overflow status of the MFC -+ Counter -+ 15 -+ 1 -+ -+ -+ -+ -+ -+ -+ EXTI -+ EXTI -+ EXTI -+ 0x5000D000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ PVD_AVD -+ PVD AND AVD detector through EXTI -+ 1 -+ -+ -+ EXTI0 -+ EXTI Line 0 interrupt -+ 6 -+ -+ -+ EXTI1 -+ EXTI Line 1 interrupt -+ 7 -+ -+ -+ EXTI2 -+ EXTI Line 2 interrupt -+ 8 -+ -+ -+ EXTI3 -+ EXTI Line 3 interrupt -+ 9 -+ -+ -+ EXTI4 -+ EXTI Line 4 interrupt -+ 10 -+ -+ -+ EXTI5 -+ EXTI line 5 interrupt -+ 23 -+ -+ -+ EXTI10 -+ EXTI line 10 interrupt -+ 40 -+ -+ -+ EXTI11 -+ EXTI line 11 interrupt -+ 42 -+ -+ -+ EXTI11 -+ EXTI line 11 interrupt -+ 42 -+ -+ -+ EXTI6 -+ EXTI line 6 interrupt -+ 64 -+ -+ -+ EXTI7 -+ EXTI line 7 interrupt -+ 65 -+ -+ -+ EXTI8 -+ EXTI line 8 interrupt -+ 66 -+ -+ -+ EXTI9 -+ EXTI line 9 interrupt -+ 67 -+ -+ -+ EXTI12 -+ EXTI line 12 interrupt -+ 76 -+ -+ -+ EXTI13 -+ EXTI line 13 interrupt -+ 77 -+ -+ -+ EXTI14 -+ EXTI line 14 interrupt -+ 121 -+ -+ -+ EXTI15 -+ EXTI line 15 interrupt -+ 127 -+ -+ -+ -+ EXTI_RTSR1 -+ EXTI_RTSR1 -+ Contains only register bits for configurable events. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RT0 -+ RT0 -+ 0 -+ 1 -+ -+ -+ RT1 -+ RT1 -+ 1 -+ 1 -+ -+ -+ RT2 -+ RT2 -+ 2 -+ 1 -+ -+ -+ RT3 -+ RT3 -+ 3 -+ 1 -+ -+ -+ RT4 -+ RT4 -+ 4 -+ 1 -+ -+ -+ RT5 -+ RT5 -+ 5 -+ 1 -+ -+ -+ RT6 -+ RT6 -+ 6 -+ 1 -+ -+ -+ RT7 -+ RT7 -+ 7 -+ 1 -+ -+ -+ RT8 -+ RT8 -+ 8 -+ 1 -+ -+ -+ RT9 -+ RT9 -+ 9 -+ 1 -+ -+ -+ RT10 -+ RT10 -+ 10 -+ 1 -+ -+ -+ RT11 -+ RT11 -+ 11 -+ 1 -+ -+ -+ RT12 -+ RT12 -+ 12 -+ 1 -+ -+ -+ RT13 -+ RT13 -+ 13 -+ 1 -+ -+ -+ RT14 -+ RT14 -+ 14 -+ 1 -+ -+ -+ RT15 -+ RT15 -+ 15 -+ 1 -+ -+ -+ RT16 -+ RT16 -+ 16 -+ 1 -+ -+ -+ -+ -+ EXTI_FTSR1 -+ EXTI_FTSR1 -+ Contains only register bits for configurable events. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FT0 -+ FT0 -+ 0 -+ 1 -+ -+ -+ FT1 -+ FT1 -+ 1 -+ 1 -+ -+ -+ FT2 -+ FT2 -+ 2 -+ 1 -+ -+ -+ FT3 -+ FT3 -+ 3 -+ 1 -+ -+ -+ FT4 -+ FT4 -+ 4 -+ 1 -+ -+ -+ FT5 -+ FT5 -+ 5 -+ 1 -+ -+ -+ FT6 -+ FT6 -+ 6 -+ 1 -+ -+ -+ FT7 -+ FT7 -+ 7 -+ 1 -+ -+ -+ FT8 -+ FT8 -+ 8 -+ 1 -+ -+ -+ FT9 -+ FT9 -+ 9 -+ 1 -+ -+ -+ FT10 -+ FT10 -+ 10 -+ 1 -+ -+ -+ FT11 -+ FT11 -+ 11 -+ 1 -+ -+ -+ FT12 -+ FT12 -+ 12 -+ 1 -+ -+ -+ FT13 -+ FT13 -+ 13 -+ 1 -+ -+ -+ FT14 -+ FT14 -+ 14 -+ 1 -+ -+ -+ FT15 -+ FT15 -+ 15 -+ 1 -+ -+ -+ FT16 -+ FT16 -+ 16 -+ 1 -+ -+ -+ -+ -+ EXTI_SWIER1 -+ EXTI_SWIER1 -+ Contains only register bits for configurable events. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SWI0 -+ SWI0 -+ 0 -+ 1 -+ -+ -+ SWI1 -+ SWI1 -+ 1 -+ 1 -+ -+ -+ SWI2 -+ SWI2 -+ 2 -+ 1 -+ -+ -+ SWI3 -+ SWI3 -+ 3 -+ 1 -+ -+ -+ SWI4 -+ SWI4 -+ 4 -+ 1 -+ -+ -+ SWI5 -+ SWI5 -+ 5 -+ 1 -+ -+ -+ SWI6 -+ SWI6 -+ 6 -+ 1 -+ -+ -+ SWI7 -+ SWI7 -+ 7 -+ 1 -+ -+ -+ SWI8 -+ SWI8 -+ 8 -+ 1 -+ -+ -+ SWI9 -+ SWI9 -+ 9 -+ 1 -+ -+ -+ SWI10 -+ SWI10 -+ 10 -+ 1 -+ -+ -+ SWI11 -+ SWI11 -+ 11 -+ 1 -+ -+ -+ SWI12 -+ SWI12 -+ 12 -+ 1 -+ -+ -+ SWI13 -+ SWI13 -+ 13 -+ 1 -+ -+ -+ SWI14 -+ SWI14 -+ 14 -+ 1 -+ -+ -+ SWI15 -+ SWI15 -+ 15 -+ 1 -+ -+ -+ SWI16 -+ SWI16 -+ 16 -+ 1 -+ -+ -+ -+ -+ EXTI_RPR1 -+ EXTI_RPR1 -+ Contains only register bits for configurable events. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RPIF0 -+ RPIF0 -+ 0 -+ 1 -+ -+ -+ RPIF1 -+ RPIF1 -+ 1 -+ 1 -+ -+ -+ RPIF2 -+ RPIF2 -+ 2 -+ 1 -+ -+ -+ RPIF3 -+ RPIF3 -+ 3 -+ 1 -+ -+ -+ RPIF4 -+ RPIF4 -+ 4 -+ 1 -+ -+ -+ RPIF5 -+ RPIF5 -+ 5 -+ 1 -+ -+ -+ RPIF6 -+ RPIF6 -+ 6 -+ 1 -+ -+ -+ RPIF7 -+ RPIF7 -+ 7 -+ 1 -+ -+ -+ RPIF8 -+ RPIF8 -+ 8 -+ 1 -+ -+ -+ RPIF9 -+ RPIF9 -+ 9 -+ 1 -+ -+ -+ RPIF10 -+ RPIF10 -+ 10 -+ 1 -+ -+ -+ RPIF11 -+ RPIF11 -+ 11 -+ 1 -+ -+ -+ RPIF12 -+ RPIF12 -+ 12 -+ 1 -+ -+ -+ RPIF13 -+ RPIF13 -+ 13 -+ 1 -+ -+ -+ RPIF14 -+ RPIF14 -+ 14 -+ 1 -+ -+ -+ RPIF15 -+ RPIF15 -+ 15 -+ 1 -+ -+ -+ RPIF16 -+ RPIF16 -+ 16 -+ 1 -+ -+ -+ -+ -+ EXTI_FPR1 -+ EXTI_FPR1 -+ Contains only register bits for configurable events. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FPIF0 -+ FPIF0 -+ 0 -+ 1 -+ -+ -+ FPIF1 -+ FPIF1 -+ 1 -+ 1 -+ -+ -+ FPIF2 -+ FPIF2 -+ 2 -+ 1 -+ -+ -+ FPIF3 -+ FPIF3 -+ 3 -+ 1 -+ -+ -+ FPIF4 -+ FPIF4 -+ 4 -+ 1 -+ -+ -+ FPIF5 -+ FPIF5 -+ 5 -+ 1 -+ -+ -+ FPIF6 -+ FPIF6 -+ 6 -+ 1 -+ -+ -+ FPIF7 -+ FPIF7 -+ 7 -+ 1 -+ -+ -+ FPIF8 -+ FPIF8 -+ 8 -+ 1 -+ -+ -+ FPIF9 -+ FPIF9 -+ 9 -+ 1 -+ -+ -+ FPIF10 -+ FPIF10 -+ 10 -+ 1 -+ -+ -+ FPIF11 -+ FPIF11 -+ 11 -+ 1 -+ -+ -+ FPIF12 -+ FPIF12 -+ 12 -+ 1 -+ -+ -+ FPIF13 -+ FPIF13 -+ 13 -+ 1 -+ -+ -+ FPIF14 -+ FPIF14 -+ 14 -+ 1 -+ -+ -+ FPIF15 -+ FPIF15 -+ 15 -+ 1 -+ -+ -+ FPIF16 -+ FPIF16 -+ 16 -+ 1 -+ -+ -+ -+ -+ EXTI_TZENR1 -+ EXTI_TZENR1 -+ This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TZEN0 -+ TZEN0 -+ 0 -+ 1 -+ -+ -+ TZEN1 -+ TZEN1 -+ 1 -+ 1 -+ -+ -+ TZEN2 -+ TZEN2 -+ 2 -+ 1 -+ -+ -+ TZEN3 -+ TZEN3 -+ 3 -+ 1 -+ -+ -+ TZEN4 -+ TZEN4 -+ 4 -+ 1 -+ -+ -+ TZEN5 -+ TZEN5 -+ 5 -+ 1 -+ -+ -+ TZEN6 -+ TZEN6 -+ 6 -+ 1 -+ -+ -+ TZEN7 -+ TZEN7 -+ 7 -+ 1 -+ -+ -+ TZEN8 -+ TZEN8 -+ 8 -+ 1 -+ -+ -+ TZEN9 -+ TZEN9 -+ 9 -+ 1 -+ -+ -+ TZEN10 -+ TZEN10 -+ 10 -+ 1 -+ -+ -+ TZEN11 -+ TZEN11 -+ 11 -+ 1 -+ -+ -+ TZEN12 -+ TZEN12 -+ 12 -+ 1 -+ -+ -+ TZEN13 -+ TZEN13 -+ 13 -+ 1 -+ -+ -+ TZEN14 -+ TZEN14 -+ 14 -+ 1 -+ -+ -+ TZEN15 -+ TZEN15 -+ 15 -+ 1 -+ -+ -+ TZEN17 -+ TZEN17 -+ 17 -+ 1 -+ -+ -+ TZEN18 -+ TZEN18 -+ 18 -+ 1 -+ -+ -+ TZEN19 -+ TZEN19 -+ 19 -+ 1 -+ -+ -+ TZEN24 -+ TZEN24 -+ 24 -+ 1 -+ -+ -+ TZEN26 -+ TZEN26 -+ 26 -+ 1 -+ -+ -+ -+ -+ EXTI_RTSR2 -+ EXTI_RTSR2 -+ Contains only register bits for configurable events. -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_FTSR2 -+ EXTI_FTSR2 -+ Contains only register bits for configurable events. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_SWIER2 -+ EXTI_SWIER2 -+ Contains only register bits for configurable events. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_RPR2 -+ EXTI_RPR2 -+ Contains only register bits for configurable events. -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_FPR2 -+ EXTI_FPR2 -+ Contains only register bits for configurable events. -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_TZENR2 -+ EXTI_TZENR2 -+ This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TZEN41 -+ TZEN41 -+ 9 -+ 1 -+ -+ -+ TZEN54 -+ TZEN54 -+ 22 -+ 1 -+ -+ -+ TZEN55 -+ TZEN55 -+ 23 -+ 1 -+ -+ -+ TZEN56 -+ TZEN56 -+ 24 -+ 1 -+ -+ -+ TZEN57 -+ TZEN57 -+ 25 -+ 1 -+ -+ -+ TZEN58 -+ TZEN58 -+ 26 -+ 1 -+ -+ -+ TZEN59 -+ TZEN59 -+ 27 -+ 1 -+ -+ -+ TZEN60 -+ TZEN60 -+ 28 -+ 1 -+ -+ -+ -+ -+ EXTI_RTSR3 -+ EXTI_RTSR3 -+ Contains only register bits for configurable events. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RT65 -+ RT65 -+ 1 -+ 1 -+ -+ -+ RT66 -+ RT66 -+ 2 -+ 1 -+ -+ -+ RT68 -+ RT68 -+ 4 -+ 1 -+ -+ -+ RT73 -+ RT73 -+ 9 -+ 1 -+ -+ -+ RT74 -+ RT74 -+ 10 -+ 1 -+ -+ -+ -+ -+ EXTI_FTSR3 -+ EXTI_FTSR3 -+ Contains only register bits for configurable events. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FT65 -+ FT65 -+ 1 -+ 1 -+ -+ -+ FT66 -+ FT66 -+ 2 -+ 1 -+ -+ -+ FT68 -+ FT68 -+ 4 -+ 1 -+ -+ -+ FT73 -+ FT73 -+ 9 -+ 1 -+ -+ -+ FT74 -+ FT74 -+ 10 -+ 1 -+ -+ -+ -+ -+ EXTI_SWIER3 -+ EXTI_SWIER3 -+ Contains only register bits for configurable events. -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SWI65 -+ SWI65 -+ 1 -+ 1 -+ -+ -+ SWI66 -+ SWI66 -+ 2 -+ 1 -+ -+ -+ SWI68 -+ SWI68 -+ 4 -+ 1 -+ -+ -+ SWI73 -+ SWI73 -+ 9 -+ 1 -+ -+ -+ SWI74 -+ SWI74 -+ 10 -+ 1 -+ -+ -+ -+ -+ EXTI_RPR3 -+ EXTI_RPR3 -+ Contains only register bits for configurable events. -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RPIF65 -+ RPIF65 -+ 1 -+ 1 -+ -+ -+ RPIF66 -+ RPIF66 -+ 2 -+ 1 -+ -+ -+ RPIF68 -+ RPIF68 -+ 4 -+ 1 -+ -+ -+ RPIF73 -+ RPIF73 -+ 9 -+ 1 -+ -+ -+ RPIF74 -+ RPIF74 -+ 10 -+ 1 -+ -+ -+ -+ -+ EXTI_FPR3 -+ EXTI_FPR3 -+ Contains only register bits for configurable events. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FPIF65 -+ FPIF65 -+ 1 -+ 1 -+ -+ -+ FPIF66 -+ FPIF66 -+ 2 -+ 1 -+ -+ -+ FPIF68 -+ FPIF68 -+ 4 -+ 1 -+ -+ -+ FPIF73 -+ FPIF73 -+ 9 -+ 1 -+ -+ -+ FPIF74 -+ FPIF74 -+ 10 -+ 1 -+ -+ -+ -+ -+ EXTI_TZENR3 -+ EXTI_TZENR3 -+ This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_EXTICR1 -+ EXTI_EXTICR1 -+ EXTIm fields contain only the number of bits in line with the nb_ioport configuration. -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI0 -+ EXTI0 -+ 0 -+ 8 -+ -+ -+ EXTI1 -+ EXTI1 -+ 8 -+ 8 -+ -+ -+ EXTI2 -+ EXTI2 -+ 16 -+ 8 -+ -+ -+ EXTI3 -+ EXTI3 -+ 24 -+ 8 -+ -+ -+ -+ -+ EXTI_EXTICR2 -+ EXTI_EXTICR2 -+ EXTIm fields contain only the number of bits in line with the nb_ioport configuration. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI4 -+ EXTI4 -+ 0 -+ 8 -+ -+ -+ EXTI5 -+ EXTI5 -+ 8 -+ 8 -+ -+ -+ EXTI6 -+ EXTI6 -+ 16 -+ 8 -+ -+ -+ EXTI7 -+ EXTI7 -+ 24 -+ 8 -+ -+ -+ -+ -+ EXTI_EXTICR3 -+ EXTI_EXTICR3 -+ EXTIm fields contain only the number of bits in line with the nb_ioport configuration. -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI8 -+ EXTI8 -+ 0 -+ 8 -+ -+ -+ EXTI9 -+ EXTI9 -+ 8 -+ 8 -+ -+ -+ EXTI10 -+ EXTI10 -+ 16 -+ 8 -+ -+ -+ EXTI11 -+ EXTI11 -+ 24 -+ 8 -+ -+ -+ -+ -+ EXTI_EXTICR4 -+ EXTI_EXTICR4 -+ EXTIm fields contain only the number of bits in line with the nb_ioport configuration. -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI12 -+ EXTI12 -+ 0 -+ 8 -+ -+ -+ EXTI13 -+ EXTI13 -+ 8 -+ 8 -+ -+ -+ EXTI14 -+ EXTI14 -+ 16 -+ 8 -+ -+ -+ EXTI15 -+ EXTI15 -+ 24 -+ 8 -+ -+ -+ -+ -+ EXTI_IMR1 -+ EXTI_IMR1 -+ Contains register bits for configurable events and Direct events. -+ 0x80 -+ 0x20 -+ read-write -+ 0xFFFE0000 -+ -+ -+ IM0 -+ IM0 -+ 0 -+ 1 -+ -+ -+ IM1 -+ IM1 -+ 1 -+ 1 -+ -+ -+ IM2 -+ IM2 -+ 2 -+ 1 -+ -+ -+ IM3 -+ IM3 -+ 3 -+ 1 -+ -+ -+ IM4 -+ IM4 -+ 4 -+ 1 -+ -+ -+ IM5 -+ IM5 -+ 5 -+ 1 -+ -+ -+ IM6 -+ IM6 -+ 6 -+ 1 -+ -+ -+ IM7 -+ IM7 -+ 7 -+ 1 -+ -+ -+ IM8 -+ IM8 -+ 8 -+ 1 -+ -+ -+ IM9 -+ IM9 -+ 9 -+ 1 -+ -+ -+ IM10 -+ IM10 -+ 10 -+ 1 -+ -+ -+ IM11 -+ IM11 -+ 11 -+ 1 -+ -+ -+ IM12 -+ IM12 -+ 12 -+ 1 -+ -+ -+ IM13 -+ IM13 -+ 13 -+ 1 -+ -+ -+ IM14 -+ IM14 -+ 14 -+ 1 -+ -+ -+ IM15 -+ IM15 -+ 15 -+ 1 -+ -+ -+ IM16 -+ IM16 -+ 16 -+ 1 -+ -+ -+ IM17 -+ IM17 -+ 17 -+ 1 -+ -+ -+ IM18 -+ IM18 -+ 18 -+ 1 -+ -+ -+ IM19 -+ IM19 -+ 19 -+ 1 -+ -+ -+ IM20 -+ IM20 -+ 20 -+ 1 -+ -+ -+ IM21 -+ IM21 -+ 21 -+ 1 -+ -+ -+ IM22 -+ IM22 -+ 22 -+ 1 -+ -+ -+ IM23 -+ IM23 -+ 23 -+ 1 -+ -+ -+ IM24 -+ IM24 -+ 24 -+ 1 -+ -+ -+ IM25 -+ IM25 -+ 25 -+ 1 -+ -+ -+ IM26 -+ IM26 -+ 26 -+ 1 -+ -+ -+ IM27 -+ IM27 -+ 27 -+ 1 -+ -+ -+ IM28 -+ IM28 -+ 28 -+ 1 -+ -+ -+ IM29 -+ IM29 -+ 29 -+ 1 -+ -+ -+ IM30 -+ IM30 -+ 30 -+ 1 -+ -+ -+ IM31 -+ IM31 -+ 31 -+ 1 -+ -+ -+ -+ -+ EXTI_EMR1 -+ EXTI_EMR1 -+ EXTI CPU wakeup with event mask register -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EM0 -+ EM0 -+ 0 -+ 1 -+ -+ -+ EM1 -+ EM1 -+ 1 -+ 1 -+ -+ -+ EM2 -+ EM2 -+ 2 -+ 1 -+ -+ -+ EM3 -+ EM3 -+ 3 -+ 1 -+ -+ -+ EM4 -+ EM4 -+ 4 -+ 1 -+ -+ -+ EM5 -+ EM5 -+ 5 -+ 1 -+ -+ -+ EM6 -+ EM6 -+ 6 -+ 1 -+ -+ -+ EM7 -+ EM7 -+ 7 -+ 1 -+ -+ -+ EM8 -+ EM8 -+ 8 -+ 1 -+ -+ -+ EM9 -+ EM9 -+ 9 -+ 1 -+ -+ -+ EM10 -+ EM10 -+ 10 -+ 1 -+ -+ -+ EM11 -+ EM11 -+ 11 -+ 1 -+ -+ -+ EM12 -+ EM12 -+ 12 -+ 1 -+ -+ -+ EM13 -+ EM13 -+ 13 -+ 1 -+ -+ -+ EM14 -+ EM14 -+ 14 -+ 1 -+ -+ -+ EM15 -+ EM15 -+ 15 -+ 1 -+ -+ -+ EM17 -+ EM17 -+ 17 -+ 1 -+ -+ -+ EM18 -+ EM18 -+ 18 -+ 1 -+ -+ -+ EM19 -+ EM19 -+ 19 -+ 1 -+ -+ -+ -+ -+ EXTI_IMR2 -+ EXTI_IMR2 -+ Contains register bits for configurable events and direct events. -+ 0x90 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ IM32 -+ IM32 -+ 0 -+ 1 -+ -+ -+ IM33 -+ IM33 -+ 1 -+ 1 -+ -+ -+ IM34 -+ IM34 -+ 2 -+ 1 -+ -+ -+ IM35 -+ IM35 -+ 3 -+ 1 -+ -+ -+ IM36 -+ IM36 -+ 4 -+ 1 -+ -+ -+ IM37 -+ IM37 -+ 5 -+ 1 -+ -+ -+ IM38 -+ IM38 -+ 6 -+ 1 -+ -+ -+ IM39 -+ IM39 -+ 7 -+ 1 -+ -+ -+ IM40 -+ IM40 -+ 8 -+ 1 -+ -+ -+ IM41 -+ IM41 -+ 9 -+ 1 -+ -+ -+ IM42 -+ IM42 -+ 10 -+ 1 -+ -+ -+ IM43 -+ IM43 -+ 11 -+ 1 -+ -+ -+ IM44 -+ IM44 -+ 12 -+ 1 -+ -+ -+ IM45 -+ IM45 -+ 13 -+ 1 -+ -+ -+ IM46 -+ IM46 -+ 14 -+ 1 -+ -+ -+ IM47 -+ IM47 -+ 15 -+ 1 -+ -+ -+ IM48 -+ IM48 -+ 16 -+ 1 -+ -+ -+ IM49 -+ IM49 -+ 17 -+ 1 -+ -+ -+ IM50 -+ IM50 -+ 18 -+ 1 -+ -+ -+ IM51 -+ IM51 -+ 19 -+ 1 -+ -+ -+ IM52 -+ IM52 -+ 20 -+ 1 -+ -+ -+ IM53 -+ IM53 -+ 21 -+ 1 -+ -+ -+ IM54 -+ IM54 -+ 22 -+ 1 -+ -+ -+ IM55 -+ IM55 -+ 23 -+ 1 -+ -+ -+ IM56 -+ IM56 -+ 24 -+ 1 -+ -+ -+ IM57 -+ IM57 -+ 25 -+ 1 -+ -+ -+ IM58 -+ IM58 -+ 26 -+ 1 -+ -+ -+ IM59 -+ IM59 -+ 27 -+ 1 -+ -+ -+ IM60 -+ IM60 -+ 28 -+ 1 -+ -+ -+ IM61 -+ IM61 -+ 29 -+ 1 -+ -+ -+ IM62 -+ IM62 -+ 30 -+ 1 -+ -+ -+ IM63 -+ IM63 -+ 31 -+ 1 -+ -+ -+ -+ -+ EXTI_EMR2 -+ EXTI_EMR2 -+ EXTI CPU wakeup with event mask register -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_IMR3 -+ EXTI_IMR3 -+ Contains register bits for configurable events and direct events. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000DE9 -+ -+ -+ IM64 -+ IM64 -+ 0 -+ 1 -+ -+ -+ IM65 -+ IM65 -+ 1 -+ 1 -+ -+ -+ IM66 -+ IM66 -+ 2 -+ 1 -+ -+ -+ IM67 -+ IM67 -+ 3 -+ 1 -+ -+ -+ IM68 -+ IM68 -+ 4 -+ 1 -+ -+ -+ IM69 -+ IM69 -+ 5 -+ 1 -+ -+ -+ IM70 -+ IM70 -+ 6 -+ 1 -+ -+ -+ IM71 -+ IM71 -+ 7 -+ 1 -+ -+ -+ IM72 -+ IM72 -+ 8 -+ 1 -+ -+ -+ IM73 -+ IM73 -+ 9 -+ 1 -+ -+ -+ IM74 -+ IM74 -+ 10 -+ 1 -+ -+ -+ IM75 -+ IM75 -+ 11 -+ 1 -+ -+ -+ -+ -+ EXTI_EMR3 -+ EXTI_EMR3 -+ EXTI CPU wakeup with event mask register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EM66 -+ EM66 -+ 2 -+ 1 -+ -+ -+ -+ -+ EXTI_C2IMR1 -+ EXTI_C2IMR1 -+ Contains register bits for configurable events and Direct events. -+ 0xC0 -+ 0x20 -+ read-write -+ 0xFFFE0000 -+ -+ -+ IM0 -+ IM0 -+ 0 -+ 1 -+ -+ -+ IM1 -+ IM1 -+ 1 -+ 1 -+ -+ -+ IM2 -+ IM2 -+ 2 -+ 1 -+ -+ -+ IM3 -+ IM3 -+ 3 -+ 1 -+ -+ -+ IM4 -+ IM4 -+ 4 -+ 1 -+ -+ -+ IM5 -+ IM5 -+ 5 -+ 1 -+ -+ -+ IM6 -+ IM6 -+ 6 -+ 1 -+ -+ -+ IM7 -+ IM7 -+ 7 -+ 1 -+ -+ -+ IM8 -+ IM8 -+ 8 -+ 1 -+ -+ -+ IM9 -+ IM9 -+ 9 -+ 1 -+ -+ -+ IM10 -+ IM10 -+ 10 -+ 1 -+ -+ -+ IM11 -+ IM11 -+ 11 -+ 1 -+ -+ -+ IM12 -+ IM12 -+ 12 -+ 1 -+ -+ -+ IM13 -+ IM13 -+ 13 -+ 1 -+ -+ -+ IM14 -+ IM14 -+ 14 -+ 1 -+ -+ -+ IM15 -+ IM15 -+ 15 -+ 1 -+ -+ -+ IM16 -+ IM16 -+ 16 -+ 1 -+ -+ -+ IM17 -+ IM17 -+ 17 -+ 1 -+ -+ -+ IM18 -+ IM18 -+ 18 -+ 1 -+ -+ -+ IM19 -+ IM19 -+ 19 -+ 1 -+ -+ -+ IM20 -+ IM20 -+ 20 -+ 1 -+ -+ -+ IM21 -+ IM21 -+ 21 -+ 1 -+ -+ -+ IM22 -+ IM22 -+ 22 -+ 1 -+ -+ -+ IM23 -+ IM23 -+ 23 -+ 1 -+ -+ -+ IM24 -+ IM24 -+ 24 -+ 1 -+ -+ -+ IM25 -+ IM25 -+ 25 -+ 1 -+ -+ -+ IM26 -+ IM26 -+ 26 -+ 1 -+ -+ -+ IM27 -+ IM27 -+ 27 -+ 1 -+ -+ -+ IM28 -+ IM28 -+ 28 -+ 1 -+ -+ -+ IM29 -+ IM29 -+ 29 -+ 1 -+ -+ -+ IM30 -+ IM30 -+ 30 -+ 1 -+ -+ -+ IM31 -+ IM31 -+ 31 -+ 1 -+ -+ -+ -+ -+ EXTI_C2EMR1 -+ EXTI_C2EMR1 -+ EXTI CPU2 wakeup with event mask register -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EM0 -+ EM0 -+ 0 -+ 1 -+ -+ -+ EM1 -+ EM1 -+ 1 -+ 1 -+ -+ -+ EM2 -+ EM2 -+ 2 -+ 1 -+ -+ -+ EM3 -+ EM3 -+ 3 -+ 1 -+ -+ -+ EM4 -+ EM4 -+ 4 -+ 1 -+ -+ -+ EM5 -+ EM5 -+ 5 -+ 1 -+ -+ -+ EM6 -+ EM6 -+ 6 -+ 1 -+ -+ -+ EM7 -+ EM7 -+ 7 -+ 1 -+ -+ -+ EM8 -+ EM8 -+ 8 -+ 1 -+ -+ -+ EM9 -+ EM9 -+ 9 -+ 1 -+ -+ -+ EM10 -+ EM10 -+ 10 -+ 1 -+ -+ -+ EM11 -+ EM11 -+ 11 -+ 1 -+ -+ -+ EM12 -+ EM12 -+ 12 -+ 1 -+ -+ -+ EM13 -+ EM13 -+ 13 -+ 1 -+ -+ -+ EM14 -+ EM14 -+ 14 -+ 1 -+ -+ -+ EM15 -+ EM15 -+ 15 -+ 1 -+ -+ -+ EM17 -+ EM17 -+ 17 -+ 1 -+ -+ -+ EM18 -+ EM18 -+ 18 -+ 1 -+ -+ -+ EM19 -+ EM19 -+ 19 -+ 1 -+ -+ -+ -+ -+ EXTI_C2IMR2 -+ EXTI_C2IMR2 -+ Contains register bits for configurable events and direct events. -+ 0xD0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ IM32 -+ IM32 -+ 0 -+ 1 -+ -+ -+ IM33 -+ IM33 -+ 1 -+ 1 -+ -+ -+ IM34 -+ IM34 -+ 2 -+ 1 -+ -+ -+ IM35 -+ IM35 -+ 3 -+ 1 -+ -+ -+ IM36 -+ IM36 -+ 4 -+ 1 -+ -+ -+ IM37 -+ IM37 -+ 5 -+ 1 -+ -+ -+ IM38 -+ IM38 -+ 6 -+ 1 -+ -+ -+ IM39 -+ IM39 -+ 7 -+ 1 -+ -+ -+ IM40 -+ IM40 -+ 8 -+ 1 -+ -+ -+ IM41 -+ IM41 -+ 9 -+ 1 -+ -+ -+ IM42 -+ IM42 -+ 10 -+ 1 -+ -+ -+ IM43 -+ IM43 -+ 11 -+ 1 -+ -+ -+ IM44 -+ IM44 -+ 12 -+ 1 -+ -+ -+ IM45 -+ IM45 -+ 13 -+ 1 -+ -+ -+ IM46 -+ IM46 -+ 14 -+ 1 -+ -+ -+ IM47 -+ IM47 -+ 15 -+ 1 -+ -+ -+ IM48 -+ IM48 -+ 16 -+ 1 -+ -+ -+ IM49 -+ IM49 -+ 17 -+ 1 -+ -+ -+ IM50 -+ IM50 -+ 18 -+ 1 -+ -+ -+ IM51 -+ IM51 -+ 19 -+ 1 -+ -+ -+ IM52 -+ IM52 -+ 20 -+ 1 -+ -+ -+ IM53 -+ IM53 -+ 21 -+ 1 -+ -+ -+ IM54 -+ IM54 -+ 22 -+ 1 -+ -+ -+ IM55 -+ IM55 -+ 23 -+ 1 -+ -+ -+ IM56 -+ IM56 -+ 24 -+ 1 -+ -+ -+ IM57 -+ IM57 -+ 25 -+ 1 -+ -+ -+ IM58 -+ IM58 -+ 26 -+ 1 -+ -+ -+ IM59 -+ IM59 -+ 27 -+ 1 -+ -+ -+ IM60 -+ IM60 -+ 28 -+ 1 -+ -+ -+ IM61 -+ IM61 -+ 29 -+ 1 -+ -+ -+ IM62 -+ IM62 -+ 30 -+ 1 -+ -+ -+ IM63 -+ IM63 -+ 31 -+ 1 -+ -+ -+ -+ -+ EXTI_C2EMR2 -+ EXTI_C2EMR2 -+ EXTI CPU2 wakeup with event mask register -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EXTI_C2IMR3 -+ EXTI_C2IMR3 -+ Contains register bits for configurable events and direct events. -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000DE9 -+ -+ -+ IM64 -+ IM64 -+ 0 -+ 1 -+ -+ -+ IM65 -+ IM65 -+ 1 -+ 1 -+ -+ -+ IM66 -+ IM66 -+ 2 -+ 1 -+ -+ -+ IM67 -+ IM67 -+ 3 -+ 1 -+ -+ -+ IM68 -+ IM68 -+ 4 -+ 1 -+ -+ -+ IM69 -+ IM69 -+ 5 -+ 1 -+ -+ -+ IM70 -+ IM70 -+ 6 -+ 1 -+ -+ -+ IM71 -+ IM71 -+ 7 -+ 1 -+ -+ -+ IM72 -+ IM72 -+ 8 -+ 1 -+ -+ -+ IM73 -+ IM73 -+ 9 -+ 1 -+ -+ -+ IM74 -+ IM74 -+ 10 -+ 1 -+ -+ -+ IM75 -+ IM75 -+ 11 -+ 1 -+ -+ -+ -+ -+ EXTI_C2EMR3 -+ EXTI_C2EMR3 -+ EXTI CPU2 wakeup with event mask register -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EM66 -+ EM66 -+ 2 -+ 1 -+ -+ -+ -+ -+ EXTI_HWCFGR13 -+ EXTI_HWCFGR13 -+ EXTI hardware configuration register 13 -+ 0x3C0 -+ 0x20 -+ read-only -+ 0x050EFFFF -+ -+ -+ TZ -+ TZ -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR12 -+ EXTI_HWCFGR12 -+ EXTI hardware configuration register 12 -+ 0x3C4 -+ 0x20 -+ read-only -+ 0x050EFFFF -+ -+ -+ TZ -+ TZ -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR11 -+ EXTI_HWCFGR11 -+ EXTI hardware configuration register 11 -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x050EFFFF -+ -+ -+ TZ -+ TZ -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR10 -+ EXTI_HWCFGR10 -+ EXTI hardware configuration register 10 -+ 0x3CC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EXTI_HWCFGR9 -+ EXTI_HWCFGR9 -+ EXTI hardware configuration register 9 -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EXTI_HWCFGR8 -+ EXTI_HWCFGR8 -+ EXTI hardware configuration register 8 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EXTI_HWCFGR7 -+ EXTI_HWCFGR7 -+ EXTI hardware configuration register 7 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0x000EFFFF -+ -+ -+ CPUEVENT -+ CPUEVENT -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR6 -+ EXTI_HWCFGR6 -+ EXTI hardware configuration register 6 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x000EFFFF -+ -+ -+ CPUEVENT -+ CPUEVENT -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR5 -+ EXTI_HWCFGR5 -+ EXTI hardware configuration register 5 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x000EFFFF -+ -+ -+ CPUEVENT -+ CPUEVENT -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR4 -+ EXTI_HWCFGR4 -+ EXTI hardware configuration register 4 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x0001FFFF -+ -+ -+ EVENT_TRG -+ EVENT_TRG -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR3 -+ EXTI_HWCFGR3 -+ EXTI hardware configuration register 3 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x0001FFFF -+ -+ -+ EVENT_TRG -+ EVENT_TRG -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR2 -+ EXTI_HWCFGR2 -+ EXTI hardware configuration register 2 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x0001FFFF -+ -+ -+ EVENT_TRG -+ EVENT_TRG -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_HWCFGR1 -+ EXTI_HWCFGR1 -+ EXTI hardware configuration register 1 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x000B214B -+ -+ -+ NBEVENTS -+ NBEVENTS -+ 0 -+ 8 -+ -+ -+ NBCPUS -+ NBCPUS -+ 8 -+ 4 -+ -+ -+ CPUEVTEN -+ CPUEVTEN -+ 12 -+ 4 -+ -+ -+ NBIOPORT -+ NBIOPORT -+ 16 -+ 8 -+ -+ -+ -+ -+ EXTI_VERR -+ EXTI_VERR -+ EXTI IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000030 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ EXTI_IPIDR -+ EXTI_IPIDR -+ EXTI identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000E0001 -+ -+ -+ IPID -+ IPID -+ 0 -+ 32 -+ -+ -+ -+ -+ EXTI_SIDR -+ EXTI_SIDR -+ EXTI size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ FDCAN1 -+ FDCAN1 -+ FDCAN1 -+ 0x4400E000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ FDCAN_CREL -+ FDCAN_CREL -+ FDCAN core release register -+ 0x0 -+ 0x20 -+ read-only -+ 0x32141218 -+ -+ -+ DAY -+ DAY -+ 0 -+ 8 -+ -+ -+ MON -+ MON -+ 8 -+ 8 -+ -+ -+ YEAR -+ YEAR -+ 16 -+ 4 -+ -+ -+ SUBSTEP -+ SUBSTEP -+ 20 -+ 4 -+ -+ -+ STEP -+ STEP -+ 24 -+ 4 -+ -+ -+ REL -+ REL -+ 28 -+ 4 -+ -+ -+ -+ -+ FDCAN_ENDN -+ FDCAN_ENDN -+ FDCAN Endian register -+ 0x4 -+ 0x20 -+ read-only -+ 0x87654321 -+ -+ -+ ETV -+ ETV -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_DBTP -+ FDCAN_DBTP -+ This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000A33 -+ -+ -+ DSJW -+ DSJW -+ 0 -+ 4 -+ -+ -+ DTSEG2 -+ DTSEG2 -+ 4 -+ 4 -+ -+ -+ DTSEG1 -+ DTSEG1 -+ 8 -+ 5 -+ -+ -+ DBRP -+ DBRP -+ 16 -+ 5 -+ -+ -+ TDC -+ TDC -+ 23 -+ 1 -+ -+ -+ -+ -+ FDCAN_TEST -+ FDCAN_TEST -+ Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. -+ 0x10 -+ 0x20 -+ 0x00000000 -+ -+ -+ LBCK -+ LBCK -+ 4 -+ 1 -+ read-write -+ -+ -+ TX -+ TX -+ 5 -+ 2 -+ read-write -+ -+ -+ RX -+ RX -+ 7 -+ 1 -+ read-only -+ -+ -+ -+ -+ FDCAN_RWD -+ FDCAN_RWD -+ The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. -+ 0x14 -+ 0x20 -+ 0x00000000 -+ -+ -+ WDC -+ WDC -+ 0 -+ 8 -+ read-write -+ -+ -+ WDV -+ WDV -+ 8 -+ 8 -+ read-only -+ -+ -+ -+ -+ FDCAN_CCCR -+ FDCAN_CCCR -+ For details about setting and resetting of single bits see Software initialization. -+ 0x18 -+ 0x20 -+ 0x00000001 -+ -+ -+ INIT -+ INIT -+ 0 -+ 1 -+ read-write -+ -+ -+ CCE -+ CCE -+ 1 -+ 1 -+ read-write -+ -+ -+ ASM -+ ASM -+ 2 -+ 1 -+ read-write -+ -+ -+ CSA -+ CSA -+ 3 -+ 1 -+ read-only -+ -+ -+ CSR -+ CSR -+ 4 -+ 1 -+ read-write -+ -+ -+ MON -+ MON -+ 5 -+ 1 -+ read-write -+ -+ -+ DAR -+ DAR -+ 6 -+ 1 -+ read-write -+ -+ -+ TEST -+ TEST -+ 7 -+ 1 -+ read-write -+ -+ -+ FDOE -+ FDOE -+ 8 -+ 1 -+ read-write -+ -+ -+ BRSE -+ BRSE -+ 9 -+ 1 -+ read-write -+ -+ -+ PXHD -+ PXHD -+ 12 -+ 1 -+ read-write -+ -+ -+ EFBI -+ EFBI -+ 13 -+ 1 -+ read-write -+ -+ -+ TXP -+ TXP -+ 14 -+ 1 -+ read-write -+ -+ -+ NISO -+ NISO -+ 15 -+ 1 -+ read-write -+ -+ -+ -+ -+ FDCAN_NBTP -+ FDCAN_NBTP -+ This register is dedicated to the nominal bit timing used during the arbitration phase. -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000A33 -+ -+ -+ NTSEG2 -+ NTSEG2 -+ 0 -+ 7 -+ -+ -+ NTSEG1 -+ NTSEG1 -+ 8 -+ 8 -+ -+ -+ NBRP -+ NBRP -+ 16 -+ 9 -+ -+ -+ NSJW -+ NSJW -+ 25 -+ 7 -+ -+ -+ -+ -+ FDCAN_TSCC -+ FDCAN_TSCC -+ FDCAN timestamp counter configuration register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSS -+ TSS -+ 0 -+ 2 -+ -+ -+ TCP -+ TCP -+ 16 -+ 4 -+ -+ -+ -+ -+ FDCAN_TSCV -+ FDCAN_TSCV -+ FDCAN timestamp counter value register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSC -+ TSC -+ 0 -+ 16 -+ -+ -+ -+ -+ FDCAN_TOCC -+ FDCAN_TOCC -+ FDCAN timeout counter configuration register -+ 0x28 -+ 0x20 -+ read-write -+ 0xFFFF0000 -+ -+ -+ ETOC -+ ETOC -+ 0 -+ 1 -+ -+ -+ TOS -+ TOS -+ 1 -+ 2 -+ -+ -+ TOP -+ TOP -+ 16 -+ 16 -+ -+ -+ -+ -+ FDCAN_TOCV -+ FDCAN_TOCV -+ FDCAN timeout counter value register -+ 0x2C -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ TOC -+ TOC -+ 0 -+ 16 -+ -+ -+ -+ -+ FDCAN_ECR -+ FDCAN_ECR -+ FDCAN error counter register -+ 0x40 -+ 0x20 -+ 0x00000000 -+ -+ -+ TEC -+ TEC -+ 0 -+ 8 -+ read-only -+ -+ -+ TREC -+ TREC -+ 8 -+ 7 -+ read-only -+ -+ -+ RP -+ RP -+ 15 -+ 1 -+ read-only -+ -+ -+ CEL -+ CEL -+ 16 -+ 8 -+ read-write -+ -+ -+ -+ -+ FDCAN_PSR -+ FDCAN_PSR -+ FDCAN protocol status register -+ 0x44 -+ 0x20 -+ 0x00000707 -+ -+ -+ LEC -+ LEC -+ 0 -+ 3 -+ read-only -+ -+ -+ ACT -+ ACT -+ 3 -+ 2 -+ read-only -+ -+ -+ EP -+ EP -+ 5 -+ 1 -+ read-only -+ -+ -+ EW -+ EW -+ 6 -+ 1 -+ read-only -+ -+ -+ BO -+ BO -+ 7 -+ 1 -+ read-only -+ -+ -+ DLEC -+ DLEC -+ 8 -+ 3 -+ read-only -+ -+ -+ RESI -+ RESI -+ 11 -+ 1 -+ read-write -+ -+ -+ RBRS -+ RBRS -+ 12 -+ 1 -+ read-write -+ -+ -+ REDL -+ REDL -+ 13 -+ 1 -+ read-write -+ -+ -+ PXE -+ PXE -+ 14 -+ 1 -+ read-write -+ -+ -+ TDCV -+ TDCV -+ 16 -+ 7 -+ read-only -+ -+ -+ -+ -+ FDCAN_TDCR -+ FDCAN_TDCR -+ FDCAN transmitter delay compensation register -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TDCF -+ TDCF -+ 0 -+ 7 -+ -+ -+ TDCO -+ TDCO -+ 8 -+ 7 -+ -+ -+ -+ -+ FDCAN_IR -+ FDCAN_IR -+ The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RF0N -+ RF0N -+ 0 -+ 1 -+ -+ -+ RF0W -+ RF0W -+ 1 -+ 1 -+ -+ -+ RF0F -+ RF0F -+ 2 -+ 1 -+ -+ -+ RF0L -+ RF0L -+ 3 -+ 1 -+ -+ -+ RF1N -+ RF1N -+ 4 -+ 1 -+ -+ -+ RF1W -+ RF1W -+ 5 -+ 1 -+ -+ -+ RF1F -+ RF1F -+ 6 -+ 1 -+ -+ -+ RF1L -+ RF1L -+ 7 -+ 1 -+ -+ -+ HPM -+ HPM -+ 8 -+ 1 -+ -+ -+ TC -+ TC -+ 9 -+ 1 -+ -+ -+ TCF -+ TCF -+ 10 -+ 1 -+ -+ -+ TFE -+ TFE -+ 11 -+ 1 -+ -+ -+ TEFN -+ TEFN -+ 12 -+ 1 -+ -+ -+ TEFW -+ TEFW -+ 13 -+ 1 -+ -+ -+ TEFF -+ TEFF -+ 14 -+ 1 -+ -+ -+ TEFL -+ TEFL -+ 15 -+ 1 -+ -+ -+ TSW -+ TSW -+ 16 -+ 1 -+ -+ -+ MRAF -+ MRAF -+ 17 -+ 1 -+ -+ -+ TOO -+ TOO -+ 18 -+ 1 -+ -+ -+ DRX -+ DRX -+ 19 -+ 1 -+ -+ -+ ELO -+ ELO -+ 22 -+ 1 -+ -+ -+ EP -+ EP -+ 23 -+ 1 -+ -+ -+ EW -+ EW -+ 24 -+ 1 -+ -+ -+ BO -+ BO -+ 25 -+ 1 -+ -+ -+ WDI -+ WDI -+ 26 -+ 1 -+ -+ -+ PEA -+ PEA -+ 27 -+ 1 -+ -+ -+ PED -+ PED -+ 28 -+ 1 -+ -+ -+ ARA -+ ARA -+ 29 -+ 1 -+ -+ -+ -+ -+ FDCAN_IE -+ FDCAN_IE -+ The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RF0NE -+ RF0NE -+ 0 -+ 1 -+ -+ -+ RF0WE -+ RF0WE -+ 1 -+ 1 -+ -+ -+ RF0FE -+ RF0FE -+ 2 -+ 1 -+ -+ -+ RF0LE -+ RF0LE -+ 3 -+ 1 -+ -+ -+ RF1NE -+ RF1NE -+ 4 -+ 1 -+ -+ -+ RF1WE -+ RF1WE -+ 5 -+ 1 -+ -+ -+ RF1FE -+ RF1FE -+ 6 -+ 1 -+ -+ -+ RF1LE -+ RF1LE -+ 7 -+ 1 -+ -+ -+ HPME -+ HPME -+ 8 -+ 1 -+ -+ -+ TCE -+ TCE -+ 9 -+ 1 -+ -+ -+ TCFE -+ TCFE -+ 10 -+ 1 -+ -+ -+ TFEE -+ TFEE -+ 11 -+ 1 -+ -+ -+ TEFNE -+ TEFNE -+ 12 -+ 1 -+ -+ -+ TEFWE -+ TEFWE -+ 13 -+ 1 -+ -+ -+ TEFFE -+ TEFFE -+ 14 -+ 1 -+ -+ -+ TEFLE -+ TEFLE -+ 15 -+ 1 -+ -+ -+ TSWE -+ TSWE -+ 16 -+ 1 -+ -+ -+ MRAFE -+ MRAFE -+ 17 -+ 1 -+ -+ -+ TOOE -+ TOOE -+ 18 -+ 1 -+ -+ -+ DRXE -+ DRXE -+ 19 -+ 1 -+ -+ -+ BECE -+ BECE -+ 20 -+ 1 -+ -+ -+ BEUE -+ BEUE -+ 21 -+ 1 -+ -+ -+ ELOE -+ ELOE -+ 22 -+ 1 -+ -+ -+ EPE -+ EPE -+ 23 -+ 1 -+ -+ -+ EWE -+ EWE -+ 24 -+ 1 -+ -+ -+ BOE -+ BOE -+ 25 -+ 1 -+ -+ -+ WDIE -+ WDIE -+ 26 -+ 1 -+ -+ -+ PEAE -+ PEAE -+ 27 -+ 1 -+ -+ -+ PEDE -+ PEDE -+ 28 -+ 1 -+ -+ -+ ARAE -+ ARAE -+ 29 -+ 1 -+ -+ -+ -+ -+ FDCAN_ILS -+ FDCAN_ILS -+ This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RF0NL -+ RF0NL -+ 0 -+ 1 -+ -+ -+ RF0WL -+ RF0WL -+ 1 -+ 1 -+ -+ -+ RF0FL -+ RF0FL -+ 2 -+ 1 -+ -+ -+ RF0LL -+ RF0LL -+ 3 -+ 1 -+ -+ -+ RF1NL -+ RF1NL -+ 4 -+ 1 -+ -+ -+ RF1WL -+ RF1WL -+ 5 -+ 1 -+ -+ -+ RF1FL -+ RF1FL -+ 6 -+ 1 -+ -+ -+ RF1LL -+ RF1LL -+ 7 -+ 1 -+ -+ -+ HPML -+ HPML -+ 8 -+ 1 -+ -+ -+ TCL -+ TCL -+ 9 -+ 1 -+ -+ -+ TCFL -+ TCFL -+ 10 -+ 1 -+ -+ -+ TFEL -+ TFEL -+ 11 -+ 1 -+ -+ -+ TEFNL -+ TEFNL -+ 12 -+ 1 -+ -+ -+ TEFWL -+ TEFWL -+ 13 -+ 1 -+ -+ -+ TEFFL -+ TEFFL -+ 14 -+ 1 -+ -+ -+ TEFLL -+ TEFLL -+ 15 -+ 1 -+ -+ -+ TSWL -+ TSWL -+ 16 -+ 1 -+ -+ -+ MRAFL -+ MRAFL -+ 17 -+ 1 -+ -+ -+ TOOL -+ TOOL -+ 18 -+ 1 -+ -+ -+ DRXL -+ DRXL -+ 19 -+ 1 -+ -+ -+ BECL -+ BECL -+ 20 -+ 1 -+ -+ -+ BEUL -+ BEUL -+ 21 -+ 1 -+ -+ -+ ELOL -+ ELOL -+ 22 -+ 1 -+ -+ -+ EPL -+ EPL -+ 23 -+ 1 -+ -+ -+ EWL -+ EWL -+ 24 -+ 1 -+ -+ -+ BOL -+ BOL -+ 25 -+ 1 -+ -+ -+ WDIL -+ WDIL -+ 26 -+ 1 -+ -+ -+ PEAL -+ PEAL -+ 27 -+ 1 -+ -+ -+ PEDL -+ PEDL -+ 28 -+ 1 -+ -+ -+ ARAL -+ ARAL -+ 29 -+ 1 -+ -+ -+ -+ -+ FDCAN_ILE -+ FDCAN_ILE -+ Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EINT0 -+ EINT0 -+ 0 -+ 1 -+ -+ -+ EINT1 -+ EINT1 -+ 1 -+ 1 -+ -+ -+ -+ -+ FDCAN_GFC -+ FDCAN_GFC -+ Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RRFE -+ RRFE -+ 0 -+ 1 -+ -+ -+ RRFS -+ RRFS -+ 1 -+ 1 -+ -+ -+ ANFE -+ ANFE -+ 2 -+ 2 -+ -+ -+ ANFS -+ ANFS -+ 4 -+ 2 -+ -+ -+ -+ -+ FDCAN_SIDFC -+ FDCAN_SIDFC -+ Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FLSSA -+ FLSSA -+ 2 -+ 14 -+ -+ -+ LSS -+ LSS -+ 16 -+ 8 -+ -+ -+ -+ -+ FDCAN_XIDFC -+ FDCAN_XIDFC -+ Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FLESA -+ FLESA -+ 2 -+ 14 -+ -+ -+ LSE -+ LSE -+ 16 -+ 8 -+ -+ -+ -+ -+ FDCAN_XIDAM -+ FDCAN_XIDAM -+ FDCAN extended ID and mask register -+ 0x90 -+ 0x20 -+ read-write -+ 0x1FFFFFFF -+ -+ -+ EIDM -+ EIDM -+ 0 -+ 29 -+ -+ -+ -+ -+ FDCAN_HPMS -+ FDCAN_HPMS -+ This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. -+ 0x94 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ BIDX -+ BIDX -+ 0 -+ 6 -+ -+ -+ MSI -+ MSI -+ 6 -+ 2 -+ -+ -+ FIDX -+ FIDX -+ 8 -+ 7 -+ -+ -+ FLST -+ FLST -+ 15 -+ 1 -+ -+ -+ -+ -+ FDCAN_NDAT1 -+ FDCAN_NDAT1 -+ FDCAN new data 1 register -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ND0 -+ ND0 -+ 0 -+ 1 -+ -+ -+ ND1 -+ ND1 -+ 1 -+ 1 -+ -+ -+ ND2 -+ ND2 -+ 2 -+ 1 -+ -+ -+ ND3 -+ ND3 -+ 3 -+ 1 -+ -+ -+ ND4 -+ ND4 -+ 4 -+ 1 -+ -+ -+ ND5 -+ ND5 -+ 5 -+ 1 -+ -+ -+ ND6 -+ ND6 -+ 6 -+ 1 -+ -+ -+ ND7 -+ ND7 -+ 7 -+ 1 -+ -+ -+ ND8 -+ ND8 -+ 8 -+ 1 -+ -+ -+ ND9 -+ ND9 -+ 9 -+ 1 -+ -+ -+ ND10 -+ ND10 -+ 10 -+ 1 -+ -+ -+ ND11 -+ ND11 -+ 11 -+ 1 -+ -+ -+ ND12 -+ ND12 -+ 12 -+ 1 -+ -+ -+ ND13 -+ ND13 -+ 13 -+ 1 -+ -+ -+ ND14 -+ ND14 -+ 14 -+ 1 -+ -+ -+ ND15 -+ ND15 -+ 15 -+ 1 -+ -+ -+ ND16 -+ ND16 -+ 16 -+ 1 -+ -+ -+ ND17 -+ ND17 -+ 17 -+ 1 -+ -+ -+ ND18 -+ ND18 -+ 18 -+ 1 -+ -+ -+ ND19 -+ ND19 -+ 19 -+ 1 -+ -+ -+ ND20 -+ ND20 -+ 20 -+ 1 -+ -+ -+ ND21 -+ ND21 -+ 21 -+ 1 -+ -+ -+ ND22 -+ ND22 -+ 22 -+ 1 -+ -+ -+ ND23 -+ ND23 -+ 23 -+ 1 -+ -+ -+ ND24 -+ ND24 -+ 24 -+ 1 -+ -+ -+ ND25 -+ ND25 -+ 25 -+ 1 -+ -+ -+ ND26 -+ ND26 -+ 26 -+ 1 -+ -+ -+ ND27 -+ ND27 -+ 27 -+ 1 -+ -+ -+ ND28 -+ ND28 -+ 28 -+ 1 -+ -+ -+ ND29 -+ ND29 -+ 29 -+ 1 -+ -+ -+ ND30 -+ ND30 -+ 30 -+ 1 -+ -+ -+ ND31 -+ ND31 -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_NDAT2 -+ FDCAN_NDAT2 -+ FDCAN new data 2 register -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ND32 -+ ND32 -+ 0 -+ 1 -+ -+ -+ ND33 -+ ND33 -+ 1 -+ 1 -+ -+ -+ ND34 -+ ND34 -+ 2 -+ 1 -+ -+ -+ ND35 -+ ND35 -+ 3 -+ 1 -+ -+ -+ ND36 -+ ND36 -+ 4 -+ 1 -+ -+ -+ ND37 -+ ND37 -+ 5 -+ 1 -+ -+ -+ ND38 -+ ND38 -+ 6 -+ 1 -+ -+ -+ ND39 -+ ND39 -+ 7 -+ 1 -+ -+ -+ ND40 -+ ND40 -+ 8 -+ 1 -+ -+ -+ ND41 -+ ND41 -+ 9 -+ 1 -+ -+ -+ ND42 -+ ND42 -+ 10 -+ 1 -+ -+ -+ ND43 -+ ND43 -+ 11 -+ 1 -+ -+ -+ ND44 -+ ND44 -+ 12 -+ 1 -+ -+ -+ ND45 -+ ND45 -+ 13 -+ 1 -+ -+ -+ ND46 -+ ND46 -+ 14 -+ 1 -+ -+ -+ ND47 -+ ND47 -+ 15 -+ 1 -+ -+ -+ ND48 -+ ND48 -+ 16 -+ 1 -+ -+ -+ ND49 -+ ND49 -+ 17 -+ 1 -+ -+ -+ ND50 -+ ND50 -+ 18 -+ 1 -+ -+ -+ ND51 -+ ND51 -+ 19 -+ 1 -+ -+ -+ ND52 -+ ND52 -+ 20 -+ 1 -+ -+ -+ ND53 -+ ND53 -+ 21 -+ 1 -+ -+ -+ ND54 -+ ND54 -+ 22 -+ 1 -+ -+ -+ ND55 -+ ND55 -+ 23 -+ 1 -+ -+ -+ ND56 -+ ND56 -+ 24 -+ 1 -+ -+ -+ ND57 -+ ND57 -+ 25 -+ 1 -+ -+ -+ ND58 -+ ND58 -+ 26 -+ 1 -+ -+ -+ ND59 -+ ND59 -+ 27 -+ 1 -+ -+ -+ ND60 -+ ND60 -+ 28 -+ 1 -+ -+ -+ ND61 -+ ND61 -+ 29 -+ 1 -+ -+ -+ ND62 -+ ND62 -+ 30 -+ 1 -+ -+ -+ ND63 -+ ND63 -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_RXF0C -+ FDCAN_RXF0C -+ FDCAN Rx FIFO 0 configuration register -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ F0SA -+ F0SA -+ 2 -+ 14 -+ -+ -+ F0S -+ F0S -+ 16 -+ 7 -+ -+ -+ F0WM -+ F0WM -+ 24 -+ 7 -+ -+ -+ F0OM -+ F0OM -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_RXF0S -+ FDCAN_RXF0S -+ FDCAN Rx FIFO 0 status register -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ F0FL -+ F0FL -+ 0 -+ 7 -+ -+ -+ F0GI -+ F0GI -+ 8 -+ 6 -+ -+ -+ F0PI -+ F0PI -+ 16 -+ 6 -+ -+ -+ F0F -+ F0F -+ 24 -+ 1 -+ -+ -+ RF0L -+ RF0L -+ 25 -+ 1 -+ -+ -+ -+ -+ FDCAN_RXF0A -+ FDCAN_RXF0A -+ FDCAN Rx FIFO 0 acknowledge register -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ F0AI -+ F0AI -+ 0 -+ 6 -+ -+ -+ -+ -+ FDCAN_RXBC -+ FDCAN_RXBC -+ FDCAN Rx buffer configuration register -+ 0xAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RBSA -+ RBSA -+ 2 -+ 14 -+ -+ -+ -+ -+ FDCAN_RXF1C -+ FDCAN_RXF1C -+ FDCAN Rx FIFO 1 configuration register -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ F1SA -+ F1SA -+ 2 -+ 14 -+ -+ -+ F1S -+ F1S -+ 16 -+ 7 -+ -+ -+ F1WM -+ F1WM -+ 24 -+ 7 -+ -+ -+ F1OM -+ F1OM -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_RXF1S -+ FDCAN_RXF1S -+ FDCAN Rx FIFO 1 status register -+ 0xB4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ F1FL -+ F1FL -+ 0 -+ 7 -+ -+ -+ F1GI -+ F1GI -+ 8 -+ 6 -+ -+ -+ F1PI -+ F1PI -+ 16 -+ 6 -+ -+ -+ F1F -+ F1F -+ 24 -+ 1 -+ -+ -+ RF1L -+ RF1L -+ 25 -+ 1 -+ -+ -+ DMS -+ DMS -+ 30 -+ 2 -+ -+ -+ -+ -+ FDCAN_RXF1A -+ FDCAN_RXF1A -+ FDCAN Rx FIFO 1 acknowledge register -+ 0xB8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ F1AI -+ F1AI -+ 0 -+ 6 -+ -+ -+ -+ -+ FDCAN_RXESC -+ FDCAN_RXESC -+ Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. -+ 0xBC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ F0DS -+ F0DS -+ 0 -+ 3 -+ -+ -+ F1DS -+ F1DS -+ 4 -+ 3 -+ -+ -+ RBDS -+ RBDS -+ 8 -+ 3 -+ -+ -+ -+ -+ FDCAN_TXBC -+ FDCAN_TXBC -+ FDCAN Tx buffer configuration register -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TBSA -+ TBSA -+ 2 -+ 14 -+ -+ -+ NDTB -+ NDTB -+ 16 -+ 6 -+ -+ -+ TFQS -+ TFQS -+ 24 -+ 6 -+ -+ -+ TFQM -+ TFQM -+ 30 -+ 1 -+ -+ -+ -+ -+ FDCAN_TXFQS -+ FDCAN_TXFQS -+ The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). -+ 0xC4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TFFL -+ TFFL -+ 0 -+ 6 -+ -+ -+ TFGI -+ TFGI -+ 8 -+ 5 -+ -+ -+ TFQPI -+ TFQPI -+ 16 -+ 5 -+ -+ -+ TFQF -+ TFQF -+ 21 -+ 1 -+ -+ -+ -+ -+ FDCAN_TXESC -+ FDCAN_TXESC -+ Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only. -+ 0xC8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TBDS -+ TBDS -+ 0 -+ 3 -+ -+ -+ -+ -+ FDCAN_TXBAR -+ FDCAN_TXBAR -+ FDCAN Tx buffer add request register -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AR -+ AR -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXBCR -+ FDCAN_TXBCR -+ FDCAN Tx buffer cancellation request register -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CR -+ CR -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXBTO -+ FDCAN_TXBTO -+ FDCAN Tx buffer transmission occurred register -+ 0xD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TO -+ TO -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXBCF -+ FDCAN_TXBCF -+ FDCAN Tx buffer cancellation finished register -+ 0xDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CF -+ CF -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXBTIE -+ FDCAN_TXBTIE -+ FDCAN Tx buffer transmission interrupt enable register -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIE -+ TIE -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXBCIE -+ FDCAN_TXBCIE -+ FDCAN Tx buffer cancellation finished interrupt enable register -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFIE -+ CFIE -+ 0 -+ 32 -+ -+ -+ -+ -+ FDCAN_TXEFC -+ FDCAN_TXEFC -+ FDCAN Tx event FIFO configuration register -+ 0xF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EFSA -+ EFSA -+ 2 -+ 14 -+ -+ -+ EFS -+ EFS -+ 16 -+ 6 -+ -+ -+ EFWM -+ EFWM -+ 24 -+ 6 -+ -+ -+ -+ -+ FDCAN_TXEFS -+ FDCAN_TXEFS -+ FDCAN Tx event FIFO status register -+ 0xF4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EFFL -+ EFFL -+ 0 -+ 6 -+ -+ -+ EFGI -+ EFGI -+ 8 -+ 5 -+ -+ -+ EFPI -+ EFPI -+ 16 -+ 5 -+ -+ -+ EFF -+ EFF -+ 24 -+ 1 -+ -+ -+ TEFL -+ TEFL -+ 25 -+ 1 -+ -+ -+ -+ -+ FDCAN_TXEFA -+ FDCAN_TXEFA -+ FDCAN Tx event FIFO acknowledge register -+ 0xF8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EFAI -+ EFAI -+ 0 -+ 5 -+ -+ -+ -+ -+ FDCAN_TTTMC -+ FDCAN_TTTMC -+ FDCAN TT trigger memory configuration register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TMSA -+ TMSA -+ 2 -+ 14 -+ -+ -+ TME -+ TME -+ 16 -+ 7 -+ -+ -+ -+ -+ FDCAN_TTRMC -+ FDCAN_TTRMC -+ FDCAN TT reference message configuration register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RID -+ RID -+ 0 -+ 29 -+ -+ -+ XTD -+ XTD -+ 30 -+ 1 -+ -+ -+ RMPS -+ RMPS -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTOCF -+ FDCAN_TTOCF -+ FDCAN TT operation configuration register -+ 0x108 -+ 0x20 -+ read-write -+ 0x00010000 -+ -+ -+ OM -+ OM -+ 0 -+ 2 -+ -+ -+ GEN -+ GEN -+ 3 -+ 1 -+ -+ -+ TM -+ TM -+ 4 -+ 1 -+ -+ -+ LDSDL -+ LDSDL -+ 5 -+ 3 -+ -+ -+ IRTO -+ IRTO -+ 8 -+ 7 -+ -+ -+ EECS -+ EECS -+ 15 -+ 1 -+ -+ -+ AWL -+ AWL -+ 16 -+ 8 -+ -+ -+ EGTF -+ EGTF -+ 24 -+ 1 -+ -+ -+ ECC -+ ECC -+ 25 -+ 1 -+ -+ -+ EVTP -+ EVTP -+ 26 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTMLM -+ FDCAN_TTMLM -+ FDCAN TT matrix limits register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCM -+ CCM -+ 0 -+ 6 -+ -+ -+ CSS -+ CSS -+ 6 -+ 2 -+ -+ -+ TXEW -+ TXEW -+ 8 -+ 4 -+ -+ -+ ENTT -+ ENTT -+ 16 -+ 12 -+ -+ -+ -+ -+ FDCAN_TURCF -+ FDCAN_TURCF -+ The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NCL -+ NCL -+ 0 -+ 16 -+ -+ -+ DC -+ DC -+ 16 -+ 14 -+ -+ -+ ELT -+ ELT -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTOCN -+ FDCAN_TTOCN -+ FDCAN TT operation control register -+ 0x114 -+ 0x20 -+ 0x00000000 -+ -+ -+ SGT -+ SGT -+ 0 -+ 1 -+ read-write -+ -+ -+ ECS -+ ECS -+ 1 -+ 1 -+ read-write -+ -+ -+ SWP -+ SWP -+ 2 -+ 1 -+ read-write -+ -+ -+ SWS -+ SWS -+ 3 -+ 2 -+ read-write -+ -+ -+ RTIE -+ RTIE -+ 5 -+ 1 -+ read-write -+ -+ -+ TMC -+ TMC -+ 6 -+ 2 -+ read-write -+ -+ -+ TTIE -+ TTIE -+ 8 -+ 1 -+ read-write -+ -+ -+ GCS -+ GCS -+ 9 -+ 1 -+ read-write -+ -+ -+ FGP -+ FGP -+ 10 -+ 1 -+ read-write -+ -+ -+ TMG -+ TMG -+ 11 -+ 1 -+ read-write -+ -+ -+ NIG -+ NIG -+ 12 -+ 1 -+ read-write -+ -+ -+ ESCN -+ ESCN -+ 13 -+ 1 -+ read-write -+ -+ -+ LCKC -+ LCKC -+ 15 -+ 1 -+ read-only -+ -+ -+ -+ -+ FDCAN_TTGTP -+ FDCAN_TTGTP -+ If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TP -+ TP -+ 0 -+ 16 -+ -+ -+ CTP -+ CTP -+ 16 -+ 16 -+ -+ -+ -+ -+ FDCAN_TTTMK -+ FDCAN_TTTMK -+ A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. -+ 0x11C -+ 0x20 -+ 0x00000000 -+ -+ -+ TM -+ TM -+ 0 -+ 16 -+ read-write -+ -+ -+ TICC -+ TICC -+ 16 -+ 7 -+ read-write -+ -+ -+ LCKM -+ LCKM -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ FDCAN_TTIR -+ FDCAN_TTIR -+ The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SBC -+ SBC -+ 0 -+ 1 -+ -+ -+ SMC -+ SMC -+ 1 -+ 1 -+ -+ -+ CSM -+ CSM -+ 2 -+ 1 -+ -+ -+ SOG -+ SOG -+ 3 -+ 1 -+ -+ -+ RTMI -+ RTMI -+ 4 -+ 1 -+ -+ -+ TTMI -+ TTMI -+ 5 -+ 1 -+ -+ -+ SWE -+ SWE -+ 6 -+ 1 -+ -+ -+ GTW -+ GTW -+ 7 -+ 1 -+ -+ -+ GTD -+ GTD -+ 8 -+ 1 -+ -+ -+ GTE -+ GTE -+ 9 -+ 1 -+ -+ -+ TXU -+ TXU -+ 10 -+ 1 -+ -+ -+ TXO -+ TXO -+ 11 -+ 1 -+ -+ -+ SE1 -+ SE1 -+ 12 -+ 1 -+ -+ -+ SE2 -+ SE2 -+ 13 -+ 1 -+ -+ -+ ELC -+ ELC -+ 14 -+ 1 -+ -+ -+ IWTG -+ IWTG -+ 15 -+ 1 -+ -+ -+ WT -+ WT -+ 16 -+ 1 -+ -+ -+ AW -+ AW -+ 17 -+ 1 -+ -+ -+ CER -+ CER -+ 18 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTIE -+ FDCAN_TTIE -+ The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SBCE -+ SBCE -+ 0 -+ 1 -+ -+ -+ SMCE -+ SMCE -+ 1 -+ 1 -+ -+ -+ CSME -+ CSME -+ 2 -+ 1 -+ -+ -+ SOGE -+ SOGE -+ 3 -+ 1 -+ -+ -+ RTMIE -+ RTMIE -+ 4 -+ 1 -+ -+ -+ TTMIE -+ TTMIE -+ 5 -+ 1 -+ -+ -+ SWEE -+ SWEE -+ 6 -+ 1 -+ -+ -+ GTWE -+ GTWE -+ 7 -+ 1 -+ -+ -+ GTDE -+ GTDE -+ 8 -+ 1 -+ -+ -+ GTEE -+ GTEE -+ 9 -+ 1 -+ -+ -+ TXUE -+ TXUE -+ 10 -+ 1 -+ -+ -+ TXOE -+ TXOE -+ 11 -+ 1 -+ -+ -+ SE1E -+ SE1E -+ 12 -+ 1 -+ -+ -+ SE2E -+ SE2E -+ 13 -+ 1 -+ -+ -+ ELCE -+ ELCE -+ 14 -+ 1 -+ -+ -+ IWTE -+ IWTE -+ 15 -+ 1 -+ -+ -+ WTE -+ WTE -+ 16 -+ 1 -+ -+ -+ AWE -+ AWE -+ 17 -+ 1 -+ -+ -+ CERE -+ CERE -+ 18 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTILS -+ FDCAN_TTILS -+ The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SBCL -+ SBCL -+ 0 -+ 1 -+ -+ -+ SMCL -+ SMCL -+ 1 -+ 1 -+ -+ -+ CSML -+ CSML -+ 2 -+ 1 -+ -+ -+ SOGL -+ SOGL -+ 3 -+ 1 -+ -+ -+ RTMIL -+ RTMIL -+ 4 -+ 1 -+ -+ -+ TTMIL -+ TTMIL -+ 5 -+ 1 -+ -+ -+ SWEL -+ SWEL -+ 6 -+ 1 -+ -+ -+ GTWL -+ GTWL -+ 7 -+ 1 -+ -+ -+ GTDL -+ GTDL -+ 8 -+ 1 -+ -+ -+ GTEL -+ GTEL -+ 9 -+ 1 -+ -+ -+ TXUL -+ TXUL -+ 10 -+ 1 -+ -+ -+ TXOL -+ TXOL -+ 11 -+ 1 -+ -+ -+ SE1L -+ SE1L -+ 12 -+ 1 -+ -+ -+ SE2L -+ SE2L -+ 13 -+ 1 -+ -+ -+ ELCL -+ ELCL -+ 14 -+ 1 -+ -+ -+ IWTL -+ IWTL -+ 15 -+ 1 -+ -+ -+ WTL -+ WTL -+ 16 -+ 1 -+ -+ -+ AWL -+ AWL -+ 17 -+ 1 -+ -+ -+ CERL -+ CERL -+ 18 -+ 1 -+ -+ -+ -+ -+ FDCAN_TTOST -+ FDCAN_TTOST -+ FDCAN TT operation status register -+ 0x12C -+ 0x20 -+ read-only -+ 0x00000080 -+ -+ -+ EL -+ EL -+ 0 -+ 2 -+ -+ -+ MS -+ MS -+ 2 -+ 2 -+ -+ -+ SYS -+ SYS -+ 4 -+ 2 -+ -+ -+ QGTP -+ QGTP -+ 6 -+ 1 -+ -+ -+ QCS -+ QCS -+ 7 -+ 1 -+ -+ -+ RTO -+ RTO -+ 8 -+ 8 -+ -+ -+ WGTD -+ WGTD -+ 22 -+ 1 -+ -+ -+ GFI -+ GFI -+ 23 -+ 1 -+ -+ -+ TMP -+ TMP -+ 24 -+ 3 -+ -+ -+ GSI -+ GSI -+ 27 -+ 1 -+ -+ -+ WFE -+ WFE -+ 28 -+ 1 -+ -+ -+ AWE -+ AWE -+ 29 -+ 1 -+ -+ -+ WECS -+ WECS -+ 30 -+ 1 -+ -+ -+ SPL -+ SPL -+ 31 -+ 1 -+ -+ -+ -+ -+ FDCAN_TURNA -+ FDCAN_TURNA -+ There is no drift compensation in TTCAN level 1. -+ 0x130 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ NAV -+ NAV -+ 0 -+ 18 -+ -+ -+ -+ -+ FDCAN_TTLGT -+ FDCAN_TTLGT -+ FDCAN TT local and global time register -+ 0x134 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ LT -+ LT -+ 0 -+ 16 -+ -+ -+ GT -+ GT -+ 16 -+ 16 -+ -+ -+ -+ -+ FDCAN_TTCTC -+ FDCAN_TTCTC -+ FDCAN TT cycle time and count register -+ 0x138 -+ 0x20 -+ read-only -+ 0x003F0000 -+ -+ -+ CT -+ CT -+ 0 -+ 16 -+ -+ -+ CC -+ CC -+ 16 -+ 6 -+ -+ -+ -+ -+ FDCAN_TTCPT -+ FDCAN_TTCPT -+ FDCAN TT capture time register -+ 0x13C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CCV -+ CCV -+ 0 -+ 6 -+ -+ -+ SWV -+ SWV -+ 16 -+ 16 -+ -+ -+ -+ -+ FDCAN_TTCSM -+ FDCAN_TTCSM -+ FDCAN TT cycle sync mark register -+ 0x140 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CSM -+ CSM -+ 0 -+ 16 -+ -+ -+ -+ -+ FDCAN_TTTS -+ FDCAN_TTTS -+ The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SWTDEL -+ SWTDEL -+ 0 -+ 2 -+ -+ -+ EVTSEL -+ EVTSEL -+ 4 -+ 2 -+ -+ -+ -+ -+ -+ -+ FDCAN2 -+ 0x4400F000 -+ -+ -+ CCU -+ CCU -+ CCU -+ 0x44010000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ FCCAN_CCU_CREL -+ FCCAN_CCU_CREL -+ Clock calibration unit core release register -+ 0x0 -+ 0x20 -+ read-only -+ 0x11141218 -+ -+ -+ DAY -+ DAY -+ 0 -+ 8 -+ -+ -+ MON -+ MON -+ 8 -+ 8 -+ -+ -+ YEAR -+ YEAR -+ 16 -+ 4 -+ -+ -+ SUBSTEP -+ SUBSTEP -+ 20 -+ 4 -+ -+ -+ STEP -+ STEP -+ 24 -+ 4 -+ -+ -+ REL -+ REL -+ 28 -+ 4 -+ -+ -+ -+ -+ FCCAN_CCU_CCFG -+ FCCAN_CCU_CCFG -+ Calibration configuration register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000004 -+ -+ -+ TQBT -+ TQBT -+ 0 -+ 5 -+ -+ -+ BCC -+ BCC -+ 6 -+ 1 -+ -+ -+ CFL -+ CFL -+ 7 -+ 1 -+ -+ -+ OCPM -+ OCPM -+ 8 -+ 8 -+ -+ -+ CDIV -+ CDIV -+ 16 -+ 4 -+ -+ -+ SWR -+ SWR -+ 31 -+ 1 -+ -+ -+ -+ -+ FCCAN_CCU_CSTAT -+ FCCAN_CCU_CSTAT -+ Calibration status register -+ 0x8 -+ 0x20 -+ read-only -+ 0x0203FFFF -+ -+ -+ OCPC -+ OCPC -+ 0 -+ 18 -+ -+ -+ TQC -+ TQC -+ 18 -+ 11 -+ -+ -+ CALS -+ CALS -+ 30 -+ 2 -+ -+ -+ -+ -+ FCCAN_CCU_CWD -+ FCCAN_CCU_CWD -+ The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset. -+ 0xC -+ 0x20 -+ 0x00000000 -+ -+ -+ WDC -+ WDC -+ 0 -+ 16 -+ read-write -+ -+ -+ WDV -+ WDV -+ 16 -+ 16 -+ read-only -+ -+ -+ -+ -+ FCCAN_CCU_IR -+ FCCAN_CCU_IR -+ The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CWE -+ CWE -+ 0 -+ 1 -+ -+ -+ CSC -+ CSC -+ 1 -+ 1 -+ -+ -+ -+ -+ FCCAN_CCU_IE -+ FCCAN_CCU_IE -+ The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CWEE -+ CWEE -+ 0 -+ 1 -+ -+ -+ CSCE -+ CSCE -+ 1 -+ 1 -+ -+ -+ -+ -+ -+ -+ FMC -+ FMC register block -+ FMC -+ 0x58002000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ FMC_BCR1 -+ FMC_BCR1 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. -+ 0x0 -+ 0x20 -+ read-write -+ 0x000030DB -+ -+ -+ MBKEN -+ MBKEN -+ 0 -+ 1 -+ -+ -+ MUXEN -+ MUXEN -+ 1 -+ 1 -+ -+ -+ MTYP -+ MTYP -+ 2 -+ 2 -+ -+ -+ MWID -+ MWID -+ 4 -+ 2 -+ -+ -+ FACCEN -+ FACCEN -+ 6 -+ 1 -+ -+ -+ BURSTEN -+ BURSTEN -+ 8 -+ 1 -+ -+ -+ WAITPOL -+ WAITPOL -+ 9 -+ 1 -+ -+ -+ WAITCFG -+ WAITCFG -+ 11 -+ 1 -+ -+ -+ WREN -+ WREN -+ 12 -+ 1 -+ -+ -+ WAITEN -+ WAITEN -+ 13 -+ 1 -+ -+ -+ EXTMOD -+ EXTMOD -+ 14 -+ 1 -+ -+ -+ ASYNCWAIT -+ ASYNCWAIT -+ 15 -+ 1 -+ -+ -+ CPSIZE -+ CPSIZE -+ 16 -+ 3 -+ -+ -+ CBURSTRW -+ CBURSTRW -+ 19 -+ 1 -+ -+ -+ CCLKEN -+ CCLKEN -+ 20 -+ 1 -+ -+ -+ NBLSET -+ NBLSET -+ 22 -+ 2 -+ -+ -+ FMCEN -+ FMCEN -+ 31 -+ 1 -+ -+ -+ -+ -+ FMC_BTR1 -+ FMC_BTR1 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). -+ 0x4 -+ 0x20 -+ read-write -+ 0x0FFFFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ CLKDIV -+ CLKDIV -+ 20 -+ 4 -+ -+ -+ DATLAT -+ DATLAT -+ 24 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BCR2 -+ FMC_BCR2 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. -+ 0x8 -+ 0x20 -+ read-write -+ 0x000030DB -+ -+ -+ MBKEN -+ MBKEN -+ 0 -+ 1 -+ -+ -+ MUXEN -+ MUXEN -+ 1 -+ 1 -+ -+ -+ MTYP -+ MTYP -+ 2 -+ 2 -+ -+ -+ MWID -+ MWID -+ 4 -+ 2 -+ -+ -+ FACCEN -+ FACCEN -+ 6 -+ 1 -+ -+ -+ BURSTEN -+ BURSTEN -+ 8 -+ 1 -+ -+ -+ WAITPOL -+ WAITPOL -+ 9 -+ 1 -+ -+ -+ WAITCFG -+ WAITCFG -+ 11 -+ 1 -+ -+ -+ WREN -+ WREN -+ 12 -+ 1 -+ -+ -+ WAITEN -+ WAITEN -+ 13 -+ 1 -+ -+ -+ EXTMOD -+ EXTMOD -+ 14 -+ 1 -+ -+ -+ ASYNCWAIT -+ ASYNCWAIT -+ 15 -+ 1 -+ -+ -+ CPSIZE -+ CPSIZE -+ 16 -+ 3 -+ -+ -+ CBURSTRW -+ CBURSTRW -+ 19 -+ 1 -+ -+ -+ CCLKEN -+ CCLKEN -+ 20 -+ 1 -+ -+ -+ NBLSET -+ NBLSET -+ 22 -+ 2 -+ -+ -+ FMCEN -+ FMCEN -+ 31 -+ 1 -+ -+ -+ -+ -+ FMC_BTR2 -+ FMC_BTR2 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). -+ 0xC -+ 0x20 -+ read-write -+ 0x0FFFFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ CLKDIV -+ CLKDIV -+ 20 -+ 4 -+ -+ -+ DATLAT -+ DATLAT -+ 24 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BCR3 -+ FMC_BCR3 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. -+ 0x10 -+ 0x20 -+ read-write -+ 0x000030DB -+ -+ -+ MBKEN -+ MBKEN -+ 0 -+ 1 -+ -+ -+ MUXEN -+ MUXEN -+ 1 -+ 1 -+ -+ -+ MTYP -+ MTYP -+ 2 -+ 2 -+ -+ -+ MWID -+ MWID -+ 4 -+ 2 -+ -+ -+ FACCEN -+ FACCEN -+ 6 -+ 1 -+ -+ -+ BURSTEN -+ BURSTEN -+ 8 -+ 1 -+ -+ -+ WAITPOL -+ WAITPOL -+ 9 -+ 1 -+ -+ -+ WAITCFG -+ WAITCFG -+ 11 -+ 1 -+ -+ -+ WREN -+ WREN -+ 12 -+ 1 -+ -+ -+ WAITEN -+ WAITEN -+ 13 -+ 1 -+ -+ -+ EXTMOD -+ EXTMOD -+ 14 -+ 1 -+ -+ -+ ASYNCWAIT -+ ASYNCWAIT -+ 15 -+ 1 -+ -+ -+ CPSIZE -+ CPSIZE -+ 16 -+ 3 -+ -+ -+ CBURSTRW -+ CBURSTRW -+ 19 -+ 1 -+ -+ -+ CCLKEN -+ CCLKEN -+ 20 -+ 1 -+ -+ -+ NBLSET -+ NBLSET -+ 22 -+ 2 -+ -+ -+ FMCEN -+ FMCEN -+ 31 -+ 1 -+ -+ -+ -+ -+ FMC_BTR3 -+ FMC_BTR3 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). -+ 0x14 -+ 0x20 -+ read-write -+ 0x0FFFFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ CLKDIV -+ CLKDIV -+ 20 -+ 4 -+ -+ -+ DATLAT -+ DATLAT -+ 24 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BCR4 -+ FMC_BCR4 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. -+ 0x18 -+ 0x20 -+ read-write -+ 0x000030DB -+ -+ -+ MBKEN -+ MBKEN -+ 0 -+ 1 -+ -+ -+ MUXEN -+ MUXEN -+ 1 -+ 1 -+ -+ -+ MTYP -+ MTYP -+ 2 -+ 2 -+ -+ -+ MWID -+ MWID -+ 4 -+ 2 -+ -+ -+ FACCEN -+ FACCEN -+ 6 -+ 1 -+ -+ -+ BURSTEN -+ BURSTEN -+ 8 -+ 1 -+ -+ -+ WAITPOL -+ WAITPOL -+ 9 -+ 1 -+ -+ -+ WAITCFG -+ WAITCFG -+ 11 -+ 1 -+ -+ -+ WREN -+ WREN -+ 12 -+ 1 -+ -+ -+ WAITEN -+ WAITEN -+ 13 -+ 1 -+ -+ -+ EXTMOD -+ EXTMOD -+ 14 -+ 1 -+ -+ -+ ASYNCWAIT -+ ASYNCWAIT -+ 15 -+ 1 -+ -+ -+ CPSIZE -+ CPSIZE -+ 16 -+ 3 -+ -+ -+ CBURSTRW -+ CBURSTRW -+ 19 -+ 1 -+ -+ -+ CCLKEN -+ CCLKEN -+ 20 -+ 1 -+ -+ -+ NBLSET -+ NBLSET -+ 22 -+ 2 -+ -+ -+ FMCEN -+ FMCEN -+ 31 -+ 1 -+ -+ -+ -+ -+ FMC_BTR4 -+ FMC_BTR4 -+ This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x0FFFFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ CLKDIV -+ CLKDIV -+ 20 -+ 4 -+ -+ -+ DATLAT -+ DATLAT -+ 24 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_PCSCNTR -+ FMC_PCSCNTR -+ This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CSCOUNT -+ CSCOUNT -+ 0 -+ 16 -+ -+ -+ CNTB1EN -+ CNTB1EN -+ 16 -+ 1 -+ -+ -+ CNTB2EN -+ CNTB2EN -+ 17 -+ 1 -+ -+ -+ CNTB3EN -+ CNTB3EN -+ 18 -+ 1 -+ -+ -+ CNTB4EN -+ CNTB4EN -+ 19 -+ 1 -+ -+ -+ -+ -+ FMC_PCR -+ FMC_PCR -+ NAND Flash Programmable control register -+ 0x80 -+ 0x20 -+ read-write -+ 0x0007FE08 -+ -+ -+ PWAITEN -+ PWAITEN -+ 1 -+ 1 -+ -+ -+ PBKEN -+ PBKEN -+ 2 -+ 1 -+ -+ -+ PWID -+ PWID -+ 4 -+ 2 -+ -+ -+ ECCEN -+ ECCEN -+ 6 -+ 1 -+ -+ -+ ECCALG -+ ECCALG -+ 8 -+ 1 -+ -+ -+ TCLR -+ TCLR -+ 9 -+ 4 -+ -+ -+ TAR -+ TAR -+ 13 -+ 4 -+ -+ -+ ECCSS -+ ECCSS -+ 17 -+ 3 -+ -+ -+ TCEH -+ TCEH -+ 20 -+ 4 -+ -+ -+ BCHECC -+ BCHECC -+ 24 -+ 1 -+ -+ -+ WEN -+ WEN -+ 25 -+ 1 -+ -+ -+ -+ -+ FMC_SR -+ FMC_SR -+ This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits. -+ 0x84 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ ISOST -+ ISOST -+ 0 -+ 2 -+ -+ -+ PEF -+ PEF -+ 4 -+ 1 -+ -+ -+ NWRF -+ NWRF -+ 6 -+ 1 -+ -+ -+ -+ -+ FMC_PMEM -+ FMC_PMEM -+ The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses. -+ 0x88 -+ 0x20 -+ read-write -+ 0x0A0A0A0A -+ -+ -+ MEMSET -+ MEMSET -+ 0 -+ 8 -+ -+ -+ MEMWAIT -+ MEMWAIT -+ 8 -+ 8 -+ -+ -+ MEMHOLD -+ MEMHOLD -+ 16 -+ 8 -+ -+ -+ MEMHIZ -+ MEMHIZ -+ 24 -+ 8 -+ -+ -+ -+ -+ FMC_PATT -+ FMC_PATT -+ The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function). -+ 0x8C -+ 0x20 -+ read-write -+ 0x0A0A0A0A -+ -+ -+ ATTSET -+ ATTSET -+ 0 -+ 8 -+ -+ -+ ATTWAIT -+ ATTWAIT -+ 8 -+ 8 -+ -+ -+ ATTHOLD -+ ATTHOLD -+ 16 -+ 8 -+ -+ -+ ATTHIZ -+ ATTHIZ -+ 24 -+ 8 -+ -+ -+ -+ -+ FMC_HPR -+ FMC_HPR -+ This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. -+ 0x90 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HPR -+ HPR -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_HECCR -+ FMC_HECCR -+ This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. -+ 0x94 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HECC -+ HECC -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_BWTR1 -+ FMC_BWTR1 -+ This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. -+ 0x104 -+ 0x20 -+ read-write -+ 0x000FFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BWTR2 -+ FMC_BWTR2 -+ This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. -+ 0x10C -+ 0x20 -+ read-write -+ 0x000FFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BWTR3 -+ FMC_BWTR3 -+ This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. -+ 0x114 -+ 0x20 -+ read-write -+ 0x000FFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_BWTR4 -+ FMC_BWTR4 -+ This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. -+ 0x11C -+ 0x20 -+ read-write -+ 0x000FFFFF -+ -+ -+ ADDSET -+ ADDSET -+ 0 -+ 4 -+ -+ -+ ADDHLD -+ ADDHLD -+ 4 -+ 4 -+ -+ -+ DATAST -+ DATAST -+ 8 -+ 8 -+ -+ -+ BUSTURN -+ BUSTURN -+ 16 -+ 4 -+ -+ -+ ACCMOD -+ ACCMOD -+ 28 -+ 2 -+ -+ -+ DATAHLD -+ DATAHLD -+ 30 -+ 2 -+ -+ -+ -+ -+ FMC_CSQCR -+ FMC_CSQCR -+ FMC NAND Command Sequencer Control Register -+ 0x200 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CSQSTART -+ CSQSTART -+ 0 -+ 1 -+ -+ -+ -+ -+ FMC_CSQCFGR1 -+ FMC_CSQCFGR1 -+ FMC NAND Command Sequencer Configuration Register 1 -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMD2EN -+ CMD2EN -+ 1 -+ 1 -+ -+ -+ DMADEN -+ DMADEN -+ 2 -+ 1 -+ -+ -+ ACYNBR -+ ACYNBR -+ 4 -+ 3 -+ -+ -+ CMD1 -+ CMD1 -+ 8 -+ 8 -+ -+ -+ CMD2 -+ CMD2 -+ 16 -+ 8 -+ -+ -+ CMD1T -+ CMD1T -+ 24 -+ 1 -+ -+ -+ CMD2T -+ CMD2T -+ 25 -+ 1 -+ -+ -+ -+ -+ FMC_CSQCFGR2 -+ FMC_CSQCFGR2 -+ This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. . -+ 0x208 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SQSDTEN -+ SQSDTEN -+ 0 -+ 1 -+ -+ -+ RCMD2EN -+ RCMD2EN -+ 1 -+ 1 -+ -+ -+ DMASEN -+ DMASEN -+ 2 -+ 1 -+ -+ -+ RCMD1 -+ RCMD1 -+ 8 -+ 8 -+ -+ -+ RCMD2 -+ RCMD2 -+ 16 -+ 8 -+ -+ -+ RCMD1T -+ RCMD1T -+ 24 -+ 1 -+ -+ -+ RCMD2T -+ RCMD2T -+ 25 -+ 1 -+ -+ -+ -+ -+ FMC_CSQCFGR3 -+ FMC_CSQCFGR3 -+ FMC NAND sequencer configuration register 3 -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SNBR -+ SNBR -+ 8 -+ 6 -+ -+ -+ AC1T -+ AC1T -+ 16 -+ 1 -+ -+ -+ AC2T -+ AC2T -+ 17 -+ 1 -+ -+ -+ AC3T -+ AC3T -+ 18 -+ 1 -+ -+ -+ AC4T -+ AC4T -+ 19 -+ 1 -+ -+ -+ AC5T -+ AC5T -+ 20 -+ 1 -+ -+ -+ SDT -+ SDT -+ 21 -+ 1 -+ -+ -+ RAC1T -+ RAC1T -+ 22 -+ 1 -+ -+ -+ RAC2T -+ RAC2T -+ 23 -+ 1 -+ -+ -+ -+ -+ FMC_CSQAR1 -+ FMC_CSQAR1 -+ This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer. -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDC1 -+ ADDC1 -+ 0 -+ 8 -+ -+ -+ ADDC2 -+ ADDC2 -+ 8 -+ 8 -+ -+ -+ ADDC3 -+ ADDC3 -+ 16 -+ 8 -+ -+ -+ ADDC4 -+ ADDC4 -+ 24 -+ 8 -+ -+ -+ -+ -+ FMC_CSQAR2 -+ FMC_CSQAR2 -+ This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable. -+ 0x214 -+ 0x20 -+ read-write -+ 0x00020000 -+ -+ -+ ADDC5 -+ ADDC5 -+ 0 -+ 8 -+ -+ -+ NANDCEN0 -+ NANDCEN0 -+ 10 -+ 1 -+ -+ -+ NANDCEN1 -+ NANDCEN1 -+ 11 -+ 1 -+ -+ -+ SAO -+ SAO -+ 16 -+ 16 -+ -+ -+ -+ -+ FMC_CSQIER -+ FMC_CSQIER -+ FMC NAND Command Sequencer Interrupt Enable Register -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TCIE -+ TCIE -+ 0 -+ 1 -+ -+ -+ SCIE -+ SCIE -+ 1 -+ 1 -+ -+ -+ SEIE -+ SEIE -+ 2 -+ 1 -+ -+ -+ SUEIE -+ SUEIE -+ 3 -+ 1 -+ -+ -+ CMDTCIE -+ CMDTCIE -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_CSQISR -+ FMC_CSQISR -+ FMC NAND Command Sequencer Interrupt Status Register -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TCF -+ TCF -+ 0 -+ 1 -+ -+ -+ SCF -+ SCF -+ 1 -+ 1 -+ -+ -+ SEF -+ SEF -+ 2 -+ 1 -+ -+ -+ SUEF -+ SUEF -+ 3 -+ 1 -+ -+ -+ CMDTCF -+ CMDTCF -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_CSQICR -+ FMC_CSQICR -+ FMC NAND Command Sequencer Interrupt Clear Register -+ 0x228 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTCF -+ CTCF -+ 0 -+ 1 -+ -+ -+ CSCF -+ CSCF -+ 1 -+ 1 -+ -+ -+ CSEF -+ CSEF -+ 2 -+ 1 -+ -+ -+ CSUEF -+ CSUEF -+ 3 -+ 1 -+ -+ -+ CCMDTCF -+ CCMDTCF -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_CSQEMSR -+ FMC_CSQEMSR -+ This register holds a sector error mapping status when the whole transfer is complete. -+ 0x230 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SEM -+ SEM -+ 0 -+ 16 -+ -+ -+ -+ -+ FMC_BCHIER -+ FMC_BCHIER -+ FMC BCH Interrupt enable register -+ 0x250 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DUEIE -+ DUEIE -+ 0 -+ 1 -+ -+ -+ DERIE -+ DERIE -+ 1 -+ 1 -+ -+ -+ DEFIE -+ DEFIE -+ 2 -+ 1 -+ -+ -+ DSRIE -+ DSRIE -+ 3 -+ 1 -+ -+ -+ EPBRIE -+ EPBRIE -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_BCHISR -+ FMC_BCHISR -+ This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared. -+ 0x254 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DUEF -+ DUEF -+ 0 -+ 1 -+ -+ -+ DERF -+ DERF -+ 1 -+ 1 -+ -+ -+ DEFF -+ DEFF -+ 2 -+ 1 -+ -+ -+ DSRF -+ DSRF -+ 3 -+ 1 -+ -+ -+ EPBRF -+ EPBRF -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_BCHICR -+ FMC_BCHICR -+ FMC BCH Interrupt Clear Register -+ 0x258 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CDUEF -+ CDUEF -+ 0 -+ 1 -+ -+ -+ CDERF -+ CDERF -+ 1 -+ 1 -+ -+ -+ CDEFF -+ CDEFF -+ 2 -+ 1 -+ -+ -+ CDSRF -+ CDSRF -+ 3 -+ 1 -+ -+ -+ CEPBRF -+ CEPBRF -+ 4 -+ 1 -+ -+ -+ -+ -+ FMC_BCHPBR1 -+ FMC_BCHPBR1 -+ These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant. -+ 0x260 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ BCHPB -+ BCHPB -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_BCHPBR2 -+ FMC_BCHPBR2 -+ FMC BCH Parity Bits Register 2 -+ 0x264 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ BCHPB -+ BCHPB -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_BCHPBR3 -+ FMC_BCHPBR3 -+ FMC BCH Parity Bits Register 3 -+ 0x268 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ BCHPB -+ BCHPB -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_BCHPBR4 -+ FMC_BCHPBR4 -+ FMC BCH Parity Bits Register 4 -+ 0x26C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ BCHPB -+ BCHPB -+ 0 -+ 8 -+ -+ -+ -+ -+ FMC_BCHDSR0 -+ FMC_BCHDSR0 -+ This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. . -+ 0x27C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DUE -+ DUE -+ 0 -+ 1 -+ -+ -+ DEF -+ DEF -+ 1 -+ 1 -+ -+ -+ DEN -+ DEN -+ 4 -+ 4 -+ -+ -+ -+ -+ FMC_BCHDSR1 -+ FMC_BCHDSR1 -+ The maximum error correction capability of the BCH block embedded in the FMC is 8 errors -+ 0x280 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EBP1 -+ EBP1 -+ 0 -+ 13 -+ -+ -+ EBP2 -+ EBP2 -+ 16 -+ 13 -+ -+ -+ -+ -+ FMC_BCHDSR2 -+ FMC_BCHDSR2 -+ The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively. -+ 0x284 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EBP3 -+ EBP3 -+ 0 -+ 13 -+ -+ -+ EBP4 -+ EBP4 -+ 16 -+ 13 -+ -+ -+ -+ -+ FMC_BCHDSR3 -+ FMC_BCHDSR3 -+ The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. -+ 0x288 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EBP5 -+ EBP5 -+ 0 -+ 13 -+ -+ -+ EBP6 -+ EBP6 -+ 16 -+ 13 -+ -+ -+ -+ -+ FMC_BCHDSR4 -+ FMC_BCHDSR4 -+ The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. . -+ 0x28C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EBP7 -+ EBP7 -+ 0 -+ 13 -+ -+ -+ EBP8 -+ EBP8 -+ 16 -+ 13 -+ -+ -+ -+ -+ FMC_HWCFGR2 -+ FMC_HWCFGR2 -+ FMC Hardware configuration register 2 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00DC8762 -+ -+ -+ RD_LN2DPTH -+ RD_LN2DPTH -+ 0 -+ 4 -+ -+ -+ NOR_BASE -+ NOR_BASE -+ 4 -+ 4 -+ -+ -+ SDRAM_RBASE -+ SDRAM_RBASE -+ 8 -+ 4 -+ -+ -+ NAND_BASE -+ NAND_BASE -+ 12 -+ 4 -+ -+ -+ SDRAM1_BASE -+ SDRAM1_BASE -+ 16 -+ 4 -+ -+ -+ SDRAM2_BASE -+ SDRAM2_BASE -+ 20 -+ 4 -+ -+ -+ -+ -+ FMC_HWCFGR1 -+ FMC_HWCFGR1 -+ FMC Hardware configuration register 1 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x2232B011 -+ -+ -+ NAND_SEL -+ NAND_SEL -+ 0 -+ 1 -+ -+ -+ NAND_ECC -+ NAND_ECC -+ 4 -+ 1 -+ -+ -+ SDRAM_SEL -+ SDRAM_SEL -+ 8 -+ 1 -+ -+ -+ ID_SIZE -+ ID_SIZE -+ 12 -+ 4 -+ -+ -+ WA_LN2DPTH -+ WA_LN2DPTH -+ 16 -+ 4 -+ -+ -+ WD_LN2DPTH -+ WD_LN2DPTH -+ 20 -+ 4 -+ -+ -+ WR_LN2DPTH -+ WR_LN2DPTH -+ 24 -+ 4 -+ -+ -+ RA_LN2DPTH -+ RA_LN2DPTH -+ 28 -+ 4 -+ -+ -+ -+ -+ FMC_VERR -+ FMC_VERR -+ FMC Version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ FMC_IPIDR -+ FMC_IPIDR -+ FMC Identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140001 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ FMC_SIDR -+ FMC_SIDR -+ FMC Size Identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GICD -+ GICD -+ GICD -+ 0xA0021000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ GICD_CTLR -+ GICD_CTLR -+ GICD control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLEGRP0 -+ ENABLEGRP0 -+ 0 -+ 1 -+ -+ -+ ENABLEGRP1 -+ ENABLEGRP1 -+ 1 -+ 1 -+ -+ -+ -+ -+ GICD_TYPER -+ GICD_TYPER -+ GICD interrupt controller type register -+ 0x4 -+ 0x20 -+ read-only -+ 0x0000FC28 -+ -+ -+ ITLINESNUMBER -+ ITLINESNUMBER -+ 0 -+ 5 -+ -+ -+ CPUNUMBER -+ CPUNUMBER -+ 5 -+ 3 -+ -+ -+ SECURITYEXTN -+ SECURITYEXTN -+ 10 -+ 1 -+ -+ -+ LSPI -+ LSPI -+ 11 -+ 5 -+ -+ -+ -+ -+ GICD_IIDR -+ GICD_IIDR -+ GICD implementer identification register -+ 0x8 -+ 0x20 -+ read-only -+ 0x0100143B -+ -+ -+ IMPLEMENTER -+ IMPLEMENTER -+ 0 -+ 12 -+ -+ -+ VARIANT -+ VARIANT -+ 12 -+ 4 -+ -+ -+ REVISION -+ REVISION -+ 16 -+ 4 -+ -+ -+ PRODUCTID -+ PRODUCTID -+ 24 -+ 8 -+ -+ -+ -+ -+ GICD_IGROUPR0 -+ GICD_IGROUPR0 -+ For interrupts ID -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR0 -+ IGROUPR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR1 -+ GICD_IGROUPR1 -+ For interrupts ID -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR1 -+ IGROUPR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR2 -+ GICD_IGROUPR2 -+ For interrupts ID -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR2 -+ IGROUPR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR3 -+ GICD_IGROUPR3 -+ For interrupts ID = x*32 to ID = x*32+31 -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR3 -+ IGROUPR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR4 -+ GICD_IGROUPR4 -+ For interrupts ID = x*32 to ID = x*32+31 -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR4 -+ IGROUPR4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR5 -+ GICD_IGROUPR5 -+ For interrupts ID -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR5 -+ IGROUPR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR6 -+ GICD_IGROUPR6 -+ For interrupts ID -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR6 -+ IGROUPR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR7 -+ GICD_IGROUPR7 -+ For interrupts ID -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR7 -+ IGROUPR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IGROUPR8 -+ GICD_IGROUPR8 -+ For interrupts ID -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IGROUPR8 -+ IGROUPR8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER0 -+ GICD_ISENABLER0 -+ For interrupts ID = 0 to ID = 31 -+ 0x100 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ ISENABLER0 -+ ISENABLER0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER1 -+ GICD_ISENABLER1 -+ For interrupts ID -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER1 -+ ISENABLER1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER2 -+ GICD_ISENABLER2 -+ For interrupts ID -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER2 -+ ISENABLER2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER3 -+ GICD_ISENABLER3 -+ For interrupts ID -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER3 -+ ISENABLER3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER4 -+ GICD_ISENABLER4 -+ For interrupts ID -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER4 -+ ISENABLER4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER5 -+ GICD_ISENABLER5 -+ For interrupts ID -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER5 -+ ISENABLER5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER6 -+ GICD_ISENABLER6 -+ For interrupts ID -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER6 -+ ISENABLER6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER7 -+ GICD_ISENABLER7 -+ For interrupts ID -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER7 -+ ISENABLER7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISENABLER8 -+ GICD_ISENABLER8 -+ For interrupts ID -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISENABLER8 -+ ISENABLER8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER0 -+ GICD_ICENABLER0 -+ For interrupts ID = 0 to ID = 31 -+ 0x180 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ ICENABLER0 -+ ICENABLER0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER1 -+ GICD_ICENABLER1 -+ For interrupts ID -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER1 -+ ICENABLER1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER2 -+ GICD_ICENABLER2 -+ For interrupts ID -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER2 -+ ICENABLER2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER3 -+ GICD_ICENABLER3 -+ For interrupts ID -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER3 -+ ICENABLER3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER4 -+ GICD_ICENABLER4 -+ For interrupts ID -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER4 -+ ICENABLER4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER5 -+ GICD_ICENABLER5 -+ For interrupts ID -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER5 -+ ICENABLER5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER6 -+ GICD_ICENABLER6 -+ For interrupts ID -+ 0x198 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER6 -+ ICENABLER6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER7 -+ GICD_ICENABLER7 -+ For interrupts ID -+ 0x19C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER7 -+ ICENABLER7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICENABLER8 -+ GICD_ICENABLER8 -+ For interrupts ID -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICENABLER8 -+ ICENABLER8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR0 -+ GICD_ISPENDR0 -+ For interrupts ID -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR0 -+ ISPENDR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR1 -+ GICD_ISPENDR1 -+ For interrupts ID -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR1 -+ ISPENDR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR2 -+ GICD_ISPENDR2 -+ For interrupts ID -+ 0x208 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR2 -+ ISPENDR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR3 -+ GICD_ISPENDR3 -+ For interrupts ID -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR3 -+ ISPENDR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR4 -+ GICD_ISPENDR4 -+ For interrupts ID -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR4 -+ ISPENDR4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR5 -+ GICD_ISPENDR5 -+ For interrupts ID -+ 0x214 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR5 -+ ISPENDR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR6 -+ GICD_ISPENDR6 -+ For interrupts ID -+ 0x218 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR6 -+ ISPENDR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR7 -+ GICD_ISPENDR7 -+ For interrupts ID -+ 0x21C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR7 -+ ISPENDR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISPENDR8 -+ GICD_ISPENDR8 -+ For interrupts ID -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPENDR8 -+ ISPENDR8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR0 -+ GICD_ICPENDR0 -+ For interrupts ID -+ 0x280 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR0 -+ ICPENDR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR1 -+ GICD_ICPENDR1 -+ For interrupts ID -+ 0x284 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR1 -+ ICPENDR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR2 -+ GICD_ICPENDR2 -+ For interrupts ID -+ 0x288 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR2 -+ ICPENDR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR3 -+ GICD_ICPENDR3 -+ For interrupts ID -+ 0x28C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR3 -+ ICPENDR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR4 -+ GICD_ICPENDR4 -+ For interrupts ID -+ 0x290 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR4 -+ ICPENDR4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR5 -+ GICD_ICPENDR5 -+ For interrupts ID -+ 0x294 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR5 -+ ICPENDR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR6 -+ GICD_ICPENDR6 -+ For interrupts ID -+ 0x298 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR6 -+ ICPENDR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR7 -+ GICD_ICPENDR7 -+ For interrupts ID -+ 0x29C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR7 -+ ICPENDR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICPENDR8 -+ GICD_ICPENDR8 -+ For interrupts ID -+ 0x2A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPENDR8 -+ ICPENDR8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER0 -+ GICD_ISACTIVER0 -+ For interrupts ID -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER0 -+ ISACTIVER0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER1 -+ GICD_ISACTIVER1 -+ For interrupts ID -+ 0x304 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER1 -+ ISACTIVER1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER2 -+ GICD_ISACTIVER2 -+ For interrupts ID -+ 0x308 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER2 -+ ISACTIVER2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER3 -+ GICD_ISACTIVER3 -+ For interrupts ID -+ 0x30C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER3 -+ ISACTIVER3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER4 -+ GICD_ISACTIVER4 -+ For interrupts ID -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER4 -+ ISACTIVER4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER5 -+ GICD_ISACTIVER5 -+ For interrupts ID -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER5 -+ ISACTIVER5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER6 -+ GICD_ISACTIVER6 -+ For interrupts ID -+ 0x318 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER6 -+ ISACTIVER6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER7 -+ GICD_ISACTIVER7 -+ For interrupts ID -+ 0x31C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER7 -+ ISACTIVER7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ISACTIVER8 -+ GICD_ISACTIVER8 -+ For interrupts ID -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISACTIVER8 -+ ISACTIVER8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER0 -+ GICD_ICACTIVER0 -+ For interrupts ID -+ 0x380 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER0 -+ ICACTIVER0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER1 -+ GICD_ICACTIVER1 -+ For interrupts ID -+ 0x384 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER1 -+ ICACTIVER1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER2 -+ GICD_ICACTIVER2 -+ For interrupts ID -+ 0x388 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER2 -+ ICACTIVER2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER3 -+ GICD_ICACTIVER3 -+ For interrupts ID -+ 0x38C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER3 -+ ICACTIVER3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER4 -+ GICD_ICACTIVER4 -+ For interrupts ID -+ 0x390 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER4 -+ ICACTIVER4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER5 -+ GICD_ICACTIVER5 -+ For interrupts ID -+ 0x394 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER5 -+ ICACTIVER5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER6 -+ GICD_ICACTIVER6 -+ For interrupts ID -+ 0x398 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER6 -+ ICACTIVER6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER7 -+ GICD_ICACTIVER7 -+ For interrupts ID -+ 0x39C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER7 -+ ICACTIVER7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_ICACTIVER8 -+ GICD_ICACTIVER8 -+ For interrupts ID -+ 0x3A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICACTIVER8 -+ ICACTIVER8 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_IPRIORITYR0 -+ GICD_IPRIORITYR0 -+ GICD interrupt priority register 0 -+ 0x400 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR1 -+ GICD_IPRIORITYR1 -+ GICD interrupt priority register 1 -+ 0x404 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR2 -+ GICD_IPRIORITYR2 -+ GICD interrupt priority register 2 -+ 0x408 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR3 -+ GICD_IPRIORITYR3 -+ GICD interrupt priority register 3 -+ 0x40C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR4 -+ GICD_IPRIORITYR4 -+ GICD interrupt priority register 4 -+ 0x410 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR5 -+ GICD_IPRIORITYR5 -+ GICD interrupt priority register 5 -+ 0x414 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR6 -+ GICD_IPRIORITYR6 -+ GICD interrupt priority register 6 -+ 0x418 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR7 -+ GICD_IPRIORITYR7 -+ GICD interrupt priority register 7 -+ 0x41C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR8 -+ GICD_IPRIORITYR8 -+ GICD interrupt priority register 8 -+ 0x420 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR9 -+ GICD_IPRIORITYR9 -+ GICD interrupt priority register 9 -+ 0x424 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR10 -+ GICD_IPRIORITYR10 -+ GICD interrupt priority register 10 -+ 0x428 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR11 -+ GICD_IPRIORITYR11 -+ GICD interrupt priority register 11 -+ 0x42C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR12 -+ GICD_IPRIORITYR12 -+ GICD interrupt priority register 12 -+ 0x430 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR13 -+ GICD_IPRIORITYR13 -+ GICD interrupt priority register 13 -+ 0x434 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR14 -+ GICD_IPRIORITYR14 -+ GICD interrupt priority register 14 -+ 0x438 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR15 -+ GICD_IPRIORITYR15 -+ GICD interrupt priority register 15 -+ 0x43C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR16 -+ GICD_IPRIORITYR16 -+ GICD interrupt priority register 16 -+ 0x440 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR17 -+ GICD_IPRIORITYR17 -+ GICD interrupt priority register 17 -+ 0x444 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR18 -+ GICD_IPRIORITYR18 -+ GICD interrupt priority register 18 -+ 0x448 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR19 -+ GICD_IPRIORITYR19 -+ GICD interrupt priority register 19 -+ 0x44C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR20 -+ GICD_IPRIORITYR20 -+ GICD interrupt priority register 20 -+ 0x450 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR21 -+ GICD_IPRIORITYR21 -+ GICD interrupt priority register 21 -+ 0x454 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR22 -+ GICD_IPRIORITYR22 -+ GICD interrupt priority register 22 -+ 0x458 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR23 -+ GICD_IPRIORITYR23 -+ GICD interrupt priority register 23 -+ 0x45C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR24 -+ GICD_IPRIORITYR24 -+ GICD interrupt priority register 24 -+ 0x460 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR25 -+ GICD_IPRIORITYR25 -+ GICD interrupt priority register 25 -+ 0x464 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR26 -+ GICD_IPRIORITYR26 -+ GICD interrupt priority register 26 -+ 0x468 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR27 -+ GICD_IPRIORITYR27 -+ GICD interrupt priority register 27 -+ 0x46C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR28 -+ GICD_IPRIORITYR28 -+ GICD interrupt priority register 28 -+ 0x470 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR29 -+ GICD_IPRIORITYR29 -+ GICD interrupt priority register 29 -+ 0x474 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR30 -+ GICD_IPRIORITYR30 -+ GICD interrupt priority register 30 -+ 0x478 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR31 -+ GICD_IPRIORITYR31 -+ GICD interrupt priority register 31 -+ 0x47C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR32 -+ GICD_IPRIORITYR32 -+ GICD interrupt priority register 32 -+ 0x480 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR33 -+ GICD_IPRIORITYR33 -+ GICD interrupt priority register 33 -+ 0x484 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR34 -+ GICD_IPRIORITYR34 -+ GICD interrupt priority register 34 -+ 0x488 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR35 -+ GICD_IPRIORITYR35 -+ GICD interrupt priority register 35 -+ 0x48C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR36 -+ GICD_IPRIORITYR36 -+ GICD interrupt priority register 36 -+ 0x490 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR37 -+ GICD_IPRIORITYR37 -+ GICD interrupt priority register 37 -+ 0x494 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR38 -+ GICD_IPRIORITYR38 -+ GICD interrupt priority register 38 -+ 0x498 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR39 -+ GICD_IPRIORITYR39 -+ GICD interrupt priority register 39 -+ 0x49C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR40 -+ GICD_IPRIORITYR40 -+ GICD interrupt priority register 40 -+ 0x4A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR41 -+ GICD_IPRIORITYR41 -+ GICD interrupt priority register 41 -+ 0x4A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR42 -+ GICD_IPRIORITYR42 -+ GICD interrupt priority register 42 -+ 0x4A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR43 -+ GICD_IPRIORITYR43 -+ GICD interrupt priority register 43 -+ 0x4AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR44 -+ GICD_IPRIORITYR44 -+ GICD interrupt priority register 44 -+ 0x4B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR45 -+ GICD_IPRIORITYR45 -+ GICD interrupt priority register 45 -+ 0x4B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR46 -+ GICD_IPRIORITYR46 -+ GICD interrupt priority register 46 -+ 0x4B8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR47 -+ GICD_IPRIORITYR47 -+ GICD interrupt priority register 47 -+ 0x4BC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR48 -+ GICD_IPRIORITYR48 -+ GICD interrupt priority register 48 -+ 0x4C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR49 -+ GICD_IPRIORITYR49 -+ GICD interrupt priority register 49 -+ 0x4C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR50 -+ GICD_IPRIORITYR50 -+ GICD interrupt priority register 50 -+ 0x4C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR51 -+ GICD_IPRIORITYR51 -+ GICD interrupt priority register 51 -+ 0x4CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR52 -+ GICD_IPRIORITYR52 -+ GICD interrupt priority register 52 -+ 0x4D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR53 -+ GICD_IPRIORITYR53 -+ GICD interrupt priority register 53 -+ 0x4D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR54 -+ GICD_IPRIORITYR54 -+ GICD interrupt priority register 54 -+ 0x4D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR55 -+ GICD_IPRIORITYR55 -+ GICD interrupt priority register 55 -+ 0x4DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR56 -+ GICD_IPRIORITYR56 -+ GICD interrupt priority register 56 -+ 0x4E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR57 -+ GICD_IPRIORITYR57 -+ GICD interrupt priority register 57 -+ 0x4E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR58 -+ GICD_IPRIORITYR58 -+ GICD interrupt priority register 58 -+ 0x4E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR59 -+ GICD_IPRIORITYR59 -+ GICD interrupt priority register 59 -+ 0x4EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR60 -+ GICD_IPRIORITYR60 -+ GICD interrupt priority register 60 -+ 0x4F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR61 -+ GICD_IPRIORITYR61 -+ GICD interrupt priority register 61 -+ 0x4F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR62 -+ GICD_IPRIORITYR62 -+ GICD interrupt priority register 62 -+ 0x4F8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR63 -+ GICD_IPRIORITYR63 -+ GICD interrupt priority register 63 -+ 0x4FC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR64 -+ GICD_IPRIORITYR64 -+ GICD interrupt priority register 64 -+ 0x500 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR65 -+ GICD_IPRIORITYR65 -+ GICD interrupt priority register 65 -+ 0x504 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR66 -+ GICD_IPRIORITYR66 -+ GICD interrupt priority register 66 -+ 0x508 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR67 -+ GICD_IPRIORITYR67 -+ GICD interrupt priority register 67 -+ 0x50C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR68 -+ GICD_IPRIORITYR68 -+ GICD interrupt priority register 68 -+ 0x510 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR69 -+ GICD_IPRIORITYR69 -+ GICD interrupt priority register 69 -+ 0x514 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR70 -+ GICD_IPRIORITYR70 -+ GICD interrupt priority register 70 -+ 0x518 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_IPRIORITYR71 -+ GICD_IPRIORITYR71 -+ GICD interrupt priority register 71 -+ 0x51C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY0 -+ PRIORITY0 -+ 3 -+ 5 -+ -+ -+ PRIORITY1 -+ PRIORITY1 -+ 11 -+ 5 -+ -+ -+ PRIORITY2 -+ PRIORITY2 -+ 19 -+ 5 -+ -+ -+ PRIORITY3 -+ PRIORITY3 -+ 27 -+ 5 -+ -+ -+ -+ -+ GICD_ITARGETSR0 -+ GICD_ITARGETSR0 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x800 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR1 -+ GICD_ITARGETSR1 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x804 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR2 -+ GICD_ITARGETSR2 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x808 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR3 -+ GICD_ITARGETSR3 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x80C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR4 -+ GICD_ITARGETSR4 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x810 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR5 -+ GICD_ITARGETSR5 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x814 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR6 -+ GICD_ITARGETSR6 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x818 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR7 -+ GICD_ITARGETSR7 -+ For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. -+ 0x81C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR8 -+ GICD_ITARGETSR8 -+ GICD interrupt processor target register 8 -+ 0x820 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR9 -+ GICD_ITARGETSR9 -+ GICD interrupt processor target register 9 -+ 0x824 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR10 -+ GICD_ITARGETSR10 -+ GICD interrupt processor target register 10 -+ 0x828 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR11 -+ GICD_ITARGETSR11 -+ GICD interrupt processor target register 11 -+ 0x82C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR12 -+ GICD_ITARGETSR12 -+ GICD interrupt processor target register 12 -+ 0x830 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR13 -+ GICD_ITARGETSR13 -+ GICD interrupt processor target register 13 -+ 0x834 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR14 -+ GICD_ITARGETSR14 -+ GICD interrupt processor target register 14 -+ 0x838 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR15 -+ GICD_ITARGETSR15 -+ GICD interrupt processor target register 15 -+ 0x83C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR16 -+ GICD_ITARGETSR16 -+ GICD interrupt processor target register 16 -+ 0x840 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR17 -+ GICD_ITARGETSR17 -+ GICD interrupt processor target register 17 -+ 0x844 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR18 -+ GICD_ITARGETSR18 -+ GICD interrupt processor target register 18 -+ 0x848 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR19 -+ GICD_ITARGETSR19 -+ GICD interrupt processor target register 19 -+ 0x84C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR20 -+ GICD_ITARGETSR20 -+ GICD interrupt processor target register 20 -+ 0x850 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR21 -+ GICD_ITARGETSR21 -+ GICD interrupt processor target register 21 -+ 0x854 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR22 -+ GICD_ITARGETSR22 -+ GICD interrupt processor target register 22 -+ 0x858 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR23 -+ GICD_ITARGETSR23 -+ GICD interrupt processor target register 23 -+ 0x85C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR24 -+ GICD_ITARGETSR24 -+ GICD interrupt processor target register 24 -+ 0x860 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR25 -+ GICD_ITARGETSR25 -+ GICD interrupt processor target register 25 -+ 0x864 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR26 -+ GICD_ITARGETSR26 -+ GICD interrupt processor target register 26 -+ 0x868 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR27 -+ GICD_ITARGETSR27 -+ GICD interrupt processor target register 27 -+ 0x86C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR28 -+ GICD_ITARGETSR28 -+ GICD interrupt processor target register 28 -+ 0x870 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR29 -+ GICD_ITARGETSR29 -+ GICD interrupt processor target register 29 -+ 0x874 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR30 -+ GICD_ITARGETSR30 -+ GICD interrupt processor target register 30 -+ 0x878 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR31 -+ GICD_ITARGETSR31 -+ GICD interrupt processor target register 31 -+ 0x87C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR32 -+ GICD_ITARGETSR32 -+ GICD interrupt processor target register 32 -+ 0x880 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR33 -+ GICD_ITARGETSR33 -+ GICD interrupt processor target register 33 -+ 0x884 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR34 -+ GICD_ITARGETSR34 -+ GICD interrupt processor target register 34 -+ 0x888 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR35 -+ GICD_ITARGETSR35 -+ GICD interrupt processor target register 35 -+ 0x88C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR36 -+ GICD_ITARGETSR36 -+ GICD interrupt processor target register 36 -+ 0x890 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR37 -+ GICD_ITARGETSR37 -+ GICD interrupt processor target register 37 -+ 0x894 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR38 -+ GICD_ITARGETSR38 -+ GICD interrupt processor target register 38 -+ 0x898 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR39 -+ GICD_ITARGETSR39 -+ GICD interrupt processor target register 39 -+ 0x89C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR40 -+ GICD_ITARGETSR40 -+ GICD interrupt processor target register 40 -+ 0x8A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR41 -+ GICD_ITARGETSR41 -+ GICD interrupt processor target register 41 -+ 0x8A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR42 -+ GICD_ITARGETSR42 -+ GICD interrupt processor target register 42 -+ 0x8A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR43 -+ GICD_ITARGETSR43 -+ GICD interrupt processor target register 43 -+ 0x8AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR44 -+ GICD_ITARGETSR44 -+ GICD interrupt processor target register 44 -+ 0x8B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR45 -+ GICD_ITARGETSR45 -+ GICD interrupt processor target register 45 -+ 0x8B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR46 -+ GICD_ITARGETSR46 -+ GICD interrupt processor target register 46 -+ 0x8B8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR47 -+ GICD_ITARGETSR47 -+ GICD interrupt processor target register 47 -+ 0x8BC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR48 -+ GICD_ITARGETSR48 -+ GICD interrupt processor target register 48 -+ 0x8C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR49 -+ GICD_ITARGETSR49 -+ GICD interrupt processor target register 49 -+ 0x8C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR50 -+ GICD_ITARGETSR50 -+ GICD interrupt processor target register 50 -+ 0x8C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR51 -+ GICD_ITARGETSR51 -+ GICD interrupt processor target register 51 -+ 0x8CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR52 -+ GICD_ITARGETSR52 -+ GICD interrupt processor target register 52 -+ 0x8D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR53 -+ GICD_ITARGETSR53 -+ GICD interrupt processor target register 53 -+ 0x8D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR54 -+ GICD_ITARGETSR54 -+ GICD interrupt processor target register 54 -+ 0x8D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR55 -+ GICD_ITARGETSR55 -+ GICD interrupt processor target register 55 -+ 0x8DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR56 -+ GICD_ITARGETSR56 -+ GICD interrupt processor target register 56 -+ 0x8E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR57 -+ GICD_ITARGETSR57 -+ GICD interrupt processor target register 57 -+ 0x8E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR58 -+ GICD_ITARGETSR58 -+ GICD interrupt processor target register 58 -+ 0x8E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR59 -+ GICD_ITARGETSR59 -+ GICD interrupt processor target register 59 -+ 0x8EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR60 -+ GICD_ITARGETSR60 -+ GICD interrupt processor target register 60 -+ 0x8F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR61 -+ GICD_ITARGETSR61 -+ GICD interrupt processor target register 61 -+ 0x8F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR62 -+ GICD_ITARGETSR62 -+ GICD interrupt processor target register 62 -+ 0x8F8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR63 -+ GICD_ITARGETSR63 -+ GICD interrupt processor target register 63 -+ 0x8FC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR64 -+ GICD_ITARGETSR64 -+ GICD interrupt processor target register 64 -+ 0x900 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR65 -+ GICD_ITARGETSR65 -+ GICD interrupt processor target register 65 -+ 0x904 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR66 -+ GICD_ITARGETSR66 -+ GICD interrupt processor target register 66 -+ 0x908 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR67 -+ GICD_ITARGETSR67 -+ GICD interrupt processor target register 67 -+ 0x90C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR68 -+ GICD_ITARGETSR68 -+ GICD interrupt processor target register 68 -+ 0x910 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR69 -+ GICD_ITARGETSR69 -+ GICD interrupt processor target register 69 -+ 0x914 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR70 -+ GICD_ITARGETSR70 -+ GICD interrupt processor target register 70 -+ 0x918 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ITARGETSR71 -+ GICD_ITARGETSR71 -+ GICD interrupt processor target register 71 -+ 0x91C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPU_TARGETS0 -+ CPU_TARGETS0 -+ 0 -+ 2 -+ -+ -+ CPU_TARGETS1 -+ CPU_TARGETS1 -+ 8 -+ 2 -+ -+ -+ CPU_TARGETS2 -+ CPU_TARGETS2 -+ 16 -+ 2 -+ -+ -+ CPU_TARGETS3 -+ CPU_TARGETS3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR0 -+ GICD_ICFGR0 -+ GICD interrupt configuration register -+ 0xC00 -+ 0x20 -+ read-write -+ 0xAAAAAAAA -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR1 -+ GICD_ICFGR1 -+ GICD interrupt configuration register -+ 0xC04 -+ 0x20 -+ read-write -+ 0x55540000 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR2 -+ GICD_ICFGR2 -+ GICD interrupt configuration register 2 -+ 0xC08 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR3 -+ GICD_ICFGR3 -+ GICD interrupt configuration register 3 -+ 0xC0C -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR4 -+ GICD_ICFGR4 -+ GICD interrupt configuration register 4 -+ 0xC10 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR5 -+ GICD_ICFGR5 -+ GICD interrupt configuration register 5 -+ 0xC14 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR6 -+ GICD_ICFGR6 -+ GICD interrupt configuration register 6 -+ 0xC18 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR7 -+ GICD_ICFGR7 -+ GICD interrupt configuration register 7 -+ 0xC1C -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR8 -+ GICD_ICFGR8 -+ GICD interrupt configuration register 8 -+ 0xC20 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR9 -+ GICD_ICFGR9 -+ GICD interrupt configuration register 9 -+ 0xC24 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR10 -+ GICD_ICFGR10 -+ GICD interrupt configuration register 10 -+ 0xC28 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR11 -+ GICD_ICFGR11 -+ GICD interrupt configuration register 11 -+ 0xC2C -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR12 -+ GICD_ICFGR12 -+ GICD interrupt configuration register 12 -+ 0xC30 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR13 -+ GICD_ICFGR13 -+ GICD interrupt configuration register 13 -+ 0xC34 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR14 -+ GICD_ICFGR14 -+ GICD interrupt configuration register 14 -+ 0xC38 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR15 -+ GICD_ICFGR15 -+ GICD interrupt configuration register 15 -+ 0xC3C -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR16 -+ GICD_ICFGR16 -+ GICD interrupt configuration register 16 -+ 0xC40 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_ICFGR17 -+ GICD_ICFGR17 -+ GICD interrupt configuration register 17 -+ 0xC44 -+ 0x20 -+ read-write -+ 0x55555555 -+ -+ -+ INT_CONFIG0 -+ INT_CONFIG0 -+ 0 -+ 2 -+ -+ -+ INT_CONFIG1 -+ INT_CONFIG1 -+ 2 -+ 2 -+ -+ -+ INT_CONFIG2 -+ INT_CONFIG2 -+ 4 -+ 2 -+ -+ -+ INT_CONFIG3 -+ INT_CONFIG3 -+ 6 -+ 2 -+ -+ -+ INT_CONFIG4 -+ INT_CONFIG4 -+ 8 -+ 2 -+ -+ -+ INT_CONFIG5 -+ INT_CONFIG5 -+ 10 -+ 2 -+ -+ -+ INT_CONFIG6 -+ INT_CONFIG6 -+ 12 -+ 2 -+ -+ -+ INT_CONFIG7 -+ INT_CONFIG7 -+ 14 -+ 2 -+ -+ -+ INT_CONFIG8 -+ INT_CONFIG8 -+ 16 -+ 2 -+ -+ -+ INT_CONFIG9 -+ INT_CONFIG9 -+ 18 -+ 2 -+ -+ -+ INT_CONFIG10 -+ INT_CONFIG10 -+ 20 -+ 2 -+ -+ -+ INT_CONFIG11 -+ INT_CONFIG11 -+ 22 -+ 2 -+ -+ -+ INT_CONFIG12 -+ INT_CONFIG12 -+ 24 -+ 2 -+ -+ -+ INT_CONFIG13 -+ INT_CONFIG13 -+ 26 -+ 2 -+ -+ -+ INT_CONFIG14 -+ INT_CONFIG14 -+ 28 -+ 2 -+ -+ -+ INT_CONFIG15 -+ INT_CONFIG15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GICD_PPISR -+ GICD_PPISR -+ GICD private peripheral interrupt status register -+ 0xD00 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PPI6 -+ PPI6 -+ 9 -+ 1 -+ -+ -+ PPI5 -+ PPI5 -+ 10 -+ 1 -+ -+ -+ PPI4 -+ PPI4 -+ 11 -+ 1 -+ -+ -+ PPI0 -+ PPI0 -+ 12 -+ 1 -+ -+ -+ PPI1 -+ PPI1 -+ 13 -+ 1 -+ -+ -+ PPI2 -+ PPI2 -+ 14 -+ 1 -+ -+ -+ PPI3 -+ PPI3 -+ 15 -+ 1 -+ -+ -+ -+ -+ GICD_SPISR1 -+ GICD_SPISR1 -+ For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32] -+ 0xD08 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR1 -+ SPISR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR2 -+ GICD_SPISR2 -+ For interrupts ID -+ 0xD0C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR2 -+ SPISR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR3 -+ GICD_SPISR3 -+ For interrupts ID -+ 0xD10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR3 -+ SPISR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR4 -+ GICD_SPISR4 -+ For interrupts ID -+ 0xD14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR4 -+ SPISR4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR5 -+ GICD_SPISR5 -+ For interrupts ID -+ 0xD18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR5 -+ SPISR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR6 -+ GICD_SPISR6 -+ For interrupts ID -+ 0xD1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR6 -+ SPISR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SPISR7 -+ GICD_SPISR7 -+ For interrupts ID -+ 0xD20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SPISR7 -+ SPISR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_SGIR -+ GICD_SGIR -+ GICD software generated interrupt register -+ 0xF00 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ SGIINTID -+ SGIINTID -+ 0 -+ 4 -+ -+ -+ NSATT -+ NSATT -+ 15 -+ 1 -+ -+ -+ CPUTARGETLIST -+ CPUTARGETLIST -+ 16 -+ 2 -+ -+ -+ TARGETLISTFILTER -+ TARGETLISTFILTER -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_CPENDSGIR0 -+ GICD_CPENDSGIR0 -+ For SGI x*4 to SGI x*4+3 -+ 0xF10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_CLEAR_PENDING0 -+ SGI_CLEAR_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING1 -+ SGI_CLEAR_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING2 -+ SGI_CLEAR_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING3 -+ SGI_CLEAR_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_CPENDSGIR1 -+ GICD_CPENDSGIR1 -+ For SGI x*4 to SGI x*4+3 -+ 0xF14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_CLEAR_PENDING0 -+ SGI_CLEAR_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING1 -+ SGI_CLEAR_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING2 -+ SGI_CLEAR_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING3 -+ SGI_CLEAR_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_CPENDSGIR2 -+ GICD_CPENDSGIR2 -+ For SGI x*4 to SGI x*4+3 -+ 0xF18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_CLEAR_PENDING0 -+ SGI_CLEAR_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING1 -+ SGI_CLEAR_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING2 -+ SGI_CLEAR_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING3 -+ SGI_CLEAR_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_CPENDSGIR3 -+ GICD_CPENDSGIR3 -+ For SGI x*4 to SGI x*4+3 -+ 0xF1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_CLEAR_PENDING0 -+ SGI_CLEAR_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING1 -+ SGI_CLEAR_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING2 -+ SGI_CLEAR_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_CLEAR_PENDING3 -+ SGI_CLEAR_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_SPENDSGIR0 -+ GICD_SPENDSGIR0 -+ For SGI x*4 to SGI x*4+3 -+ 0xF20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_SET_PENDING0 -+ SGI_SET_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_SET_PENDING1 -+ SGI_SET_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_SET_PENDING2 -+ SGI_SET_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_SET_PENDING3 -+ SGI_SET_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_SPENDSGIR1 -+ GICD_SPENDSGIR1 -+ For SGI x*4 to SGI x*4+3 -+ 0xF24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_SET_PENDING0 -+ SGI_SET_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_SET_PENDING1 -+ SGI_SET_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_SET_PENDING2 -+ SGI_SET_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_SET_PENDING3 -+ SGI_SET_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_SPENDSGIR2 -+ GICD_SPENDSGIR2 -+ For SGI x*4 to SGI x*4+3 -+ 0xF28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_SET_PENDING0 -+ SGI_SET_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_SET_PENDING1 -+ SGI_SET_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_SET_PENDING2 -+ SGI_SET_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_SET_PENDING3 -+ SGI_SET_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_SPENDSGIR3 -+ GICD_SPENDSGIR3 -+ For SGI x*4 to SGI x*4+3 -+ 0xF2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SGI_SET_PENDING0 -+ SGI_SET_PENDING0 -+ 0 -+ 2 -+ -+ -+ SGI_SET_PENDING1 -+ SGI_SET_PENDING1 -+ 8 -+ 2 -+ -+ -+ SGI_SET_PENDING2 -+ SGI_SET_PENDING2 -+ 16 -+ 2 -+ -+ -+ SGI_SET_PENDING3 -+ SGI_SET_PENDING3 -+ 24 -+ 2 -+ -+ -+ -+ -+ GICD_PIDR4 -+ GICD_PIDR4 -+ GICD peripheral ID4 register -+ 0xFD0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ PIDR4 -+ PIDR4 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR5 -+ GICD_PIDR5 -+ GICD peripheral ID5 to ID7 register 5 -+ 0xFD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR5 -+ PIDR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR6 -+ GICD_PIDR6 -+ GICD peripheral ID5 to ID7 register 6 -+ 0xFD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR6 -+ PIDR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR7 -+ GICD_PIDR7 -+ GICD peripheral ID5 to ID7 register 7 -+ 0xFDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR7 -+ PIDR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR0 -+ GICD_PIDR0 -+ GICD peripheral ID0 register -+ 0xFE0 -+ 0x20 -+ read-only -+ 0x00000090 -+ -+ -+ PIDR0 -+ PIDR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR1 -+ GICD_PIDR1 -+ GICD peripheral ID1 register -+ 0xFE4 -+ 0x20 -+ read-only -+ 0x000000B4 -+ -+ -+ PIDR1 -+ PIDR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR2 -+ GICD_PIDR2 -+ GICD peripheral ID2 register -+ 0xFE8 -+ 0x20 -+ read-only -+ 0x0000002B -+ -+ -+ PIDR2 -+ PIDR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_PIDR3 -+ GICD_PIDR3 -+ GICD peripheral ID3 register -+ 0xFEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR3 -+ PIDR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_CIDR0 -+ GICD_CIDR0 -+ GICD component ID0 register -+ 0xFF0 -+ 0x20 -+ read-only -+ 0x0000000D -+ -+ -+ CIDR0 -+ CIDR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_CIDR1 -+ GICD_CIDR1 -+ GICD component ID1 register -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x000000F0 -+ -+ -+ CIDR1 -+ CIDR1 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_CIDR2 -+ GICD_CIDR2 -+ GICD component ID2 register -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00000005 -+ -+ -+ CIDR2 -+ CIDR2 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICD_CIDR3 -+ GICD_CIDR3 -+ GICD component ID3 register -+ 0xFFC -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ CIDR3 -+ CIDR3 -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GICC -+ GICC -+ GICC -+ 0xA0022000 -+ -+ 0x0 -+ 0x2000 -+ registers -+ -+ -+ -+ GICC_CTLR -+ GICC_CTLR -+ GICC control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLEGRP0 -+ ENABLEGRP0 -+ 0 -+ 1 -+ -+ -+ ENABLEGRP1 -+ ENABLEGRP1 -+ 1 -+ 1 -+ -+ -+ ACKCTL -+ ACKCTL -+ 2 -+ 1 -+ -+ -+ FIQEN -+ FIQEN -+ 3 -+ 1 -+ -+ -+ CBPR -+ CBPR -+ 4 -+ 1 -+ -+ -+ FIQBYPDISGRP0 -+ FIQBYPDISGRP0 -+ 5 -+ 1 -+ -+ -+ IRQBYPDISGRP0 -+ IRQBYPDISGRP0 -+ 6 -+ 1 -+ -+ -+ FIQBYPDISGRP1 -+ FIQBYPDISGRP1 -+ 7 -+ 1 -+ -+ -+ IRQBYPDISGRP1 -+ IRQBYPDISGRP1 -+ 8 -+ 1 -+ -+ -+ EOIMODES -+ EOIMODES -+ 9 -+ 1 -+ -+ -+ EOIMODENS -+ EOIMODENS -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_PMR -+ GICC_PMR -+ GICC input priority mask register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY -+ PRIORITY -+ 3 -+ 5 -+ -+ -+ -+ -+ GICC_BPR -+ GICC_BPR -+ GICC binary point register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000002 -+ -+ -+ BINARY_POINT -+ BINARY_POINT -+ 0 -+ 3 -+ -+ -+ -+ -+ GICC_IAR -+ GICC_IAR -+ GICC interrupt acknowledge register -+ 0xC -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_EOIR -+ GICC_EOIR -+ GICC end of interrupt register -+ 0x10 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOIINTID -+ EOIINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_RPR -+ GICC_RPR -+ GICC running priority register -+ 0x14 -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ PRIORITY -+ PRIORITY -+ 3 -+ 5 -+ -+ -+ -+ -+ GICC_HPPIR -+ GICC_HPPIR -+ GICC highest priority pending interrupt register -+ 0x18 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ PENDINTID -+ PENDINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_ABPR -+ GICC_ABPR -+ GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR. -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ BINARY_POINT -+ BINARY_POINT -+ 0 -+ 3 -+ -+ -+ -+ -+ GICC_AIAR -+ GICC_AIAR -+ GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR. -+ 0x20 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_AEOIR -+ GICC_AEOIR -+ GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used. -+ 0x24 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOIINTID -+ EOIINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_AHPPIR -+ GICC_AHPPIR -+ ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR. -+ 0x28 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ PENDINTID -+ PENDINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICC_APR0 -+ GICC_APR0 -+ GICC active priority register -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ APR0 -+ APR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICC_NSAPR0 -+ GICC_NSAPR0 -+ GICC non-secure active priority register -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAPR0 -+ NSAPR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICC_IIDR -+ GICC_IIDR -+ GICC interface identification register -+ 0xFC -+ 0x20 -+ read-only -+ 0x0102143B -+ -+ -+ IMPLEMENTER -+ IMPLEMENTER -+ 0 -+ 12 -+ -+ -+ REVISION -+ REVISION -+ 12 -+ 4 -+ -+ -+ ARCH -+ ARCH -+ 16 -+ 4 -+ -+ -+ PRODUCTID -+ PRODUCTID -+ 20 -+ 12 -+ -+ -+ -+ -+ GICC_DIR -+ GICC_DIR -+ GICC deactivate interrupt register -+ 0x1000 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ -+ -+ GICH -+ GICH -+ GICH -+ 0xA0024000 -+ -+ 0x0 -+ 0x2000 -+ registers -+ -+ -+ -+ GICH_HCR -+ GICH_HCR -+ GICH hypervisor control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ UIE -+ UIE -+ 1 -+ 1 -+ -+ -+ LRENPIE -+ LRENPIE -+ 2 -+ 1 -+ -+ -+ NPIE -+ NPIE -+ 3 -+ 1 -+ -+ -+ VGRP0EIE -+ VGRP0EIE -+ 4 -+ 1 -+ -+ -+ VGRP0DIE -+ VGRP0DIE -+ 5 -+ 1 -+ -+ -+ VGRP1EIE -+ VGRP1EIE -+ 6 -+ 1 -+ -+ -+ VGRP1DIE -+ VGRP1DIE -+ 7 -+ 1 -+ -+ -+ EOICOUNT -+ EOICOUNT -+ 27 -+ 5 -+ -+ -+ -+ -+ GICH_VTR -+ GICH_VTR -+ GICH VGIC type register -+ 0x4 -+ 0x20 -+ read-only -+ 0x90000003 -+ -+ -+ LISTREGS -+ LISTREGS -+ 0 -+ 5 -+ -+ -+ PREBITS -+ PREBITS -+ 26 -+ 3 -+ -+ -+ PRIBITS -+ PRIBITS -+ 29 -+ 3 -+ -+ -+ -+ -+ GICH_VMCR -+ GICH_VMCR -+ GICH virtual machine control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x004D0000 -+ -+ -+ VMGRP0EN -+ VMGRP0EN -+ 0 -+ 1 -+ -+ -+ VMGRP1EN -+ VMGRP1EN -+ 1 -+ 1 -+ -+ -+ VMACKCTL -+ VMACKCTL -+ 2 -+ 1 -+ -+ -+ VMFIQEN -+ VMFIQEN -+ 3 -+ 1 -+ -+ -+ VMCBPR -+ VMCBPR -+ 4 -+ 1 -+ -+ -+ VEM -+ VEM -+ 9 -+ 1 -+ -+ -+ VMABP -+ VMABP -+ 18 -+ 3 -+ -+ -+ VMBP -+ VMBP -+ 21 -+ 3 -+ -+ -+ VMPRIMASK -+ VMPRIMASK -+ 27 -+ 5 -+ -+ -+ -+ -+ GICH_MISR -+ GICH_MISR -+ GICH maintenance interrupt status register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EOI -+ EOI -+ 0 -+ 1 -+ -+ -+ U -+ U -+ 1 -+ 1 -+ -+ -+ LRENP -+ LRENP -+ 2 -+ 1 -+ -+ -+ NP -+ NP -+ 3 -+ 1 -+ -+ -+ VGRP0E -+ VGRP0E -+ 4 -+ 1 -+ -+ -+ VGRP0D -+ VGRP0D -+ 5 -+ 1 -+ -+ -+ VGRP1E -+ VGRP1E -+ 6 -+ 1 -+ -+ -+ VGRP1D -+ VGRP1D -+ 7 -+ 1 -+ -+ -+ -+ -+ GICH_EISR0 -+ GICH_EISR0 -+ GICH end of interrupt status register -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EISR0 -+ EISR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICH_ELSR0 -+ GICH_ELSR0 -+ GICH empty list status register -+ 0x30 -+ 0x20 -+ read-only -+ 0x0000000F -+ -+ -+ ELSR0 -+ ELSR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICH_APR0 -+ GICH_APR0 -+ GICH active priority register -+ 0xF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ APR0 -+ APR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICH_LR0 -+ GICH_LR0 -+ GICH list register 0 -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VIRTUALID -+ VIRTUALID -+ 0 -+ 10 -+ -+ -+ PHYSICALID -+ PHYSICALID -+ 10 -+ 10 -+ -+ -+ PRIORITY -+ PRIORITY -+ 23 -+ 5 -+ -+ -+ STATE -+ STATE -+ 28 -+ 2 -+ -+ -+ GRP1 -+ GRP1 -+ 30 -+ 1 -+ -+ -+ HW -+ HW -+ 31 -+ 1 -+ -+ -+ -+ -+ GICH_LR1 -+ GICH_LR1 -+ GICH list register 1 -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VIRTUALID -+ VIRTUALID -+ 0 -+ 10 -+ -+ -+ PHYSICALID -+ PHYSICALID -+ 10 -+ 10 -+ -+ -+ PRIORITY -+ PRIORITY -+ 23 -+ 5 -+ -+ -+ STATE -+ STATE -+ 28 -+ 2 -+ -+ -+ GRP1 -+ GRP1 -+ 30 -+ 1 -+ -+ -+ HW -+ HW -+ 31 -+ 1 -+ -+ -+ -+ -+ GICH_LR2 -+ GICH_LR2 -+ GICH list register 2 -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VIRTUALID -+ VIRTUALID -+ 0 -+ 10 -+ -+ -+ PHYSICALID -+ PHYSICALID -+ 10 -+ 10 -+ -+ -+ PRIORITY -+ PRIORITY -+ 23 -+ 5 -+ -+ -+ STATE -+ STATE -+ 28 -+ 2 -+ -+ -+ GRP1 -+ GRP1 -+ 30 -+ 1 -+ -+ -+ HW -+ HW -+ 31 -+ 1 -+ -+ -+ -+ -+ GICH_LR3 -+ GICH_LR3 -+ GICH list register 3 -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VIRTUALID -+ VIRTUALID -+ 0 -+ 10 -+ -+ -+ PHYSICALID -+ PHYSICALID -+ 10 -+ 10 -+ -+ -+ PRIORITY -+ PRIORITY -+ 23 -+ 5 -+ -+ -+ STATE -+ STATE -+ 28 -+ 2 -+ -+ -+ GRP1 -+ GRP1 -+ 30 -+ 1 -+ -+ -+ HW -+ HW -+ 31 -+ 1 -+ -+ -+ -+ -+ -+ -+ GICV -+ GICV -+ GICV -+ 0xA0026000 -+ -+ 0x0 -+ 0x2000 -+ registers -+ -+ -+ -+ GICV_CTLR -+ GICV_CTLR -+ GICV virtual machine control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLEGRP0 -+ ENABLEGRP0 -+ 0 -+ 1 -+ -+ -+ ENABLEGRP1 -+ ENABLEGRP1 -+ 1 -+ 1 -+ -+ -+ ACKCTL -+ ACKCTL -+ 2 -+ 1 -+ -+ -+ FIQEN -+ FIQEN -+ 3 -+ 1 -+ -+ -+ CBPR -+ CBPR -+ 4 -+ 1 -+ -+ -+ EOIMODE -+ EOIMODE -+ 9 -+ 1 -+ -+ -+ -+ -+ GICV_PMR -+ GICV_PMR -+ GICV VM priority mask register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRIORITY -+ PRIORITY -+ 3 -+ 5 -+ -+ -+ -+ -+ GICV_BPR -+ GICV_BPR -+ GICV VM binary point register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000002 -+ -+ -+ BINARY_POINT -+ BINARY_POINT -+ 0 -+ 3 -+ -+ -+ -+ -+ GICV_IAR -+ GICV_IAR -+ GICV VM interrupt acknowledge register -+ 0xC -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_EOIR -+ GICV_EOIR -+ GICV VM end of interrupt register -+ 0x10 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOIINTID -+ EOIINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_RPR -+ GICV_RPR -+ GICV VM running priority register -+ 0x14 -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ PRIORITY -+ PRIORITY -+ 3 -+ 5 -+ -+ -+ -+ -+ GICV_HPPIR -+ GICV_HPPIR -+ GICV VM highest priority pending interrupt register -+ 0x18 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ PENDINTID -+ PENDINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_ABPR -+ GICV_ABPR -+ GICV VM aliased binary point register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ BINARY_POINT -+ BINARY_POINT -+ 0 -+ 3 -+ -+ -+ -+ -+ GICV_AIAR -+ GICV_AIAR -+ GICV VM aliased interrupt register -+ 0x20 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_AEOIR -+ GICV_AEOIR -+ GICV VM aliased end of interrupt register -+ 0x24 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOIINTID -+ EOIINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_AHPPIR -+ GICV_AHPPIR -+ GICV VM aliased highest priority pending interrupt register -+ 0x28 -+ 0x20 -+ read-only -+ 0x000003FF -+ -+ -+ PENDINTID -+ PENDINTID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ GICV_APR0 -+ GICV_APR0 -+ The GICV_APR0 is an alias of GICH_APR. -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ APR0 -+ APR0 -+ 0 -+ 32 -+ -+ -+ -+ -+ GICV_IIDR -+ GICV_IIDR -+ The GICV_IIDR is an alias of GICC_IIDR. -+ 0xFC -+ 0x20 -+ read-only -+ 0x0102143B -+ -+ -+ IIDR -+ IIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GICV_DIR -+ GICV_DIR -+ GICV VM deactivate interrupt register -+ 0x1000 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ INTERRUPT_ID -+ INTERRUPT_ID -+ 0 -+ 10 -+ -+ -+ CPUID -+ CPUID -+ 10 -+ 1 -+ -+ -+ -+ -+ -+ -+ TIM1 -+ TIM1 -+ TIM1 -+ 0x44000000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM1_CR1 -+ TIM1_CR1 -+ TIM1 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM1_CR2 -+ TIM1_CR2 -+ TIM1 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM1_SMCR -+ TIM1_SMCR -+ TIM1 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM1_DIER -+ TIM1_DIER -+ TIM1 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM1_SR -+ TIM1_SR -+ TIM1 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM1_EGR -+ TIM1_EGR -+ TIM1 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM1_CCMR1ALTERNATE1 -+ TIM1_CCMR1ALTERNATE1 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM1_CCMR2ALTERNATE17 -+ TIM1_CCMR2ALTERNATE17 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM1_CCER -+ TIM1_CCER -+ TIM1 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM1_CNT -+ TIM1_CNT -+ TIM1 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM1_PSC -+ TIM1_PSC -+ TIM1 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_ARR -+ TIM1_ARR -+ TIM1 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_RCR -+ TIM1_RCR -+ TIM1 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_CCR1 -+ TIM1_CCR1 -+ TIM1 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_CCR2 -+ TIM1_CCR2 -+ TIM1 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_CCR3 -+ TIM1_CCR3 -+ TIM1 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_CCR4 -+ TIM1_CCR4 -+ TIM1 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_BDTR -+ TIM1_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM1_DCR -+ TIM1_DCR -+ TIM1 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM1_DMAR -+ TIM1_DMAR -+ TIM1 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM1_CCMR3 -+ TIM1_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM1_CCR5 -+ TIM1_CCR5 -+ TIM1 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM1_CCR6 -+ TIM1_CCR6 -+ TIM1 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM1_AF1 -+ TIM1_AF1 -+ TIM1 alternate function option register 1 -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BKINE -+ BKINE -+ 0 -+ 1 -+ -+ -+ BKDF1BK0E -+ BKDF1BK0E -+ 8 -+ 1 -+ -+ -+ BKINP -+ BKINP -+ 9 -+ 1 -+ -+ -+ ETRSEL -+ ETRSEL -+ 14 -+ 4 -+ -+ -+ -+ -+ TIM1_AF2 -+ TIM1_AF2 -+ TIM1 Alternate function register 2 -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BK2INE -+ BK2INE -+ 0 -+ 1 -+ -+ -+ BK2DF1BK1E -+ BK2DF1BK1E -+ 8 -+ 1 -+ -+ -+ BK2INP -+ BK2INP -+ 9 -+ 1 -+ -+ -+ -+ -+ TIM1_TISEL -+ TIM1_TISEL -+ TIM1 timer input selection register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ -+ -+ TI2SEL -+ TI2SEL -+ 8 -+ 4 -+ -+ -+ TI3SEL -+ TI3SEL -+ 16 -+ 4 -+ -+ -+ TI4SEL -+ TI4SEL -+ 24 -+ 4 -+ -+ -+ -+ -+ -+ -+ TIM2 -+ TIM2 -+ TIM2 -+ 0x40000000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM2_CR1 -+ TIM2_CR1 -+ TIM2 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM2_CR2 -+ TIM2_CR2 -+ TIM2 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM2_SMCR -+ TIM2_SMCR -+ TIM2 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM2_DIER -+ TIM2_DIER -+ TIM2 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM2_SR -+ TIM2_SR -+ TIM2 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM2_EGR -+ TIM2_EGR -+ TIM2 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM2_CCMR1ALTERNATE2 -+ TIM2_CCMR1ALTERNATE2 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM2_CCMR2ALTERNATE18 -+ TIM2_CCMR2ALTERNATE18 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM2_CCER -+ TIM2_CCER -+ TIM2 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM2_CNT -+ TIM2_CNT -+ TIM2 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM2_PSC -+ TIM2_PSC -+ TIM2 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_ARR -+ TIM2_ARR -+ TIM2 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_RCR -+ TIM2_RCR -+ TIM2 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_CCR1 -+ TIM2_CCR1 -+ TIM2 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_CCR2 -+ TIM2_CCR2 -+ TIM2 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_CCR3 -+ TIM2_CCR3 -+ TIM2 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_CCR4 -+ TIM2_CCR4 -+ TIM2 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM2_BDTR -+ TIM2_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM2_DCR -+ TIM2_DCR -+ TIM2 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM2_DMAR -+ TIM2_DMAR -+ TIM2 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM2_CCMR3 -+ TIM2_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM2_CCR5 -+ TIM2_CCR5 -+ TIM2 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM2_CCR6 -+ TIM2_CCR6 -+ TIM2 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM3 -+ TIM3 -+ TIM3 -+ 0x40001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM3_CR1 -+ TIM3_CR1 -+ TIM3 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM3_CR2 -+ TIM3_CR2 -+ TIM3 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM3_SMCR -+ TIM3_SMCR -+ TIM3 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM3_DIER -+ TIM3_DIER -+ TIM3 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM3_SR -+ TIM3_SR -+ TIM3 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM3_EGR -+ TIM3_EGR -+ TIM3 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM3_CCMR1ALTERNATE3 -+ TIM3_CCMR1ALTERNATE3 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM3_CCMR2ALTERNATE19 -+ TIM3_CCMR2ALTERNATE19 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM3_CCER -+ TIM3_CCER -+ TIM3 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM3_CNT -+ TIM3_CNT -+ TIM3 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM3_PSC -+ TIM3_PSC -+ TIM3 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_ARR -+ TIM3_ARR -+ TIM3 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_RCR -+ TIM3_RCR -+ TIM3 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_CCR1 -+ TIM3_CCR1 -+ TIM3 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_CCR2 -+ TIM3_CCR2 -+ TIM3 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_CCR3 -+ TIM3_CCR3 -+ TIM3 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_CCR4 -+ TIM3_CCR4 -+ TIM3 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM3_BDTR -+ TIM3_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM3_DCR -+ TIM3_DCR -+ TIM3 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM3_DMAR -+ TIM3_DMAR -+ TIM3 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM3_CCMR3 -+ TIM3_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM3_CCR5 -+ TIM3_CCR5 -+ TIM3 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM3_CCR6 -+ TIM3_CCR6 -+ TIM3 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM4 -+ TIM4 -+ TIM4 -+ 0x40002000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM4_CR1 -+ TIM4_CR1 -+ TIM4 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM4_CR2 -+ TIM4_CR2 -+ TIM4 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM4_SMCR -+ TIM4_SMCR -+ TIM4 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM4_DIER -+ TIM4_DIER -+ TIM4 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM4_SR -+ TIM4_SR -+ TIM4 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM4_EGR -+ TIM4_EGR -+ TIM4 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM4_CCMR1ALTERNATE4 -+ TIM4_CCMR1ALTERNATE4 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM4_CCMR2ALTERNATE20 -+ TIM4_CCMR2ALTERNATE20 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM4_CCER -+ TIM4_CCER -+ TIM4 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM4_CNT -+ TIM4_CNT -+ TIM4 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM4_PSC -+ TIM4_PSC -+ TIM4 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_ARR -+ TIM4_ARR -+ TIM4 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_RCR -+ TIM4_RCR -+ TIM4 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_CCR1 -+ TIM4_CCR1 -+ TIM4 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_CCR2 -+ TIM4_CCR2 -+ TIM4 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_CCR3 -+ TIM4_CCR3 -+ TIM4 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_CCR4 -+ TIM4_CCR4 -+ TIM4 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM4_BDTR -+ TIM4_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM4_DCR -+ TIM4_DCR -+ TIM4 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM4_DMAR -+ TIM4_DMAR -+ TIM4 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM4_CCMR3 -+ TIM4_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM4_CCR5 -+ TIM4_CCR5 -+ TIM4 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM4_CCR6 -+ TIM4_CCR6 -+ TIM4 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM5 -+ TIM5 -+ TIM5 -+ 0x40003000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM5_CR1 -+ TIM5_CR1 -+ TIM5 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM5_CR2 -+ TIM5_CR2 -+ TIM5 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM5_SMCR -+ TIM5_SMCR -+ TIM5 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM5_DIER -+ TIM5_DIER -+ TIM5 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM5_SR -+ TIM5_SR -+ TIM5 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM5_EGR -+ TIM5_EGR -+ TIM5 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM5_CCMR1ALTERNATE5 -+ TIM5_CCMR1ALTERNATE5 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM5_CCMR2ALTERNATE21 -+ TIM5_CCMR2ALTERNATE21 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM5_CCER -+ TIM5_CCER -+ TIM5 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM5_CNT -+ TIM5_CNT -+ TIM5 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM5_PSC -+ TIM5_PSC -+ TIM5 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_ARR -+ TIM5_ARR -+ TIM5 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_RCR -+ TIM5_RCR -+ TIM5 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_CCR1 -+ TIM5_CCR1 -+ TIM5 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_CCR2 -+ TIM5_CCR2 -+ TIM5 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_CCR3 -+ TIM5_CCR3 -+ TIM5 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_CCR4 -+ TIM5_CCR4 -+ TIM5 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM5_BDTR -+ TIM5_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM5_DCR -+ TIM5_DCR -+ TIM5 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM5_DMAR -+ TIM5_DMAR -+ TIM5 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM5_CCMR3 -+ TIM5_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM5_CCR5 -+ TIM5_CCR5 -+ TIM5 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM5_CCR6 -+ TIM5_CCR6 -+ TIM5 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM6 -+ TIM6 -+ TIM6 -+ 0x40004000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM6_CR1 -+ TIM6_CR1 -+ TIM6 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM6_CR2 -+ TIM6_CR2 -+ TIM6 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM6_SMCR -+ TIM6_SMCR -+ TIM6 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM6_DIER -+ TIM6_DIER -+ TIM6 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM6_SR -+ TIM6_SR -+ TIM6 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM6_EGR -+ TIM6_EGR -+ TIM6 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM6_CCMR1ALTERNATE6 -+ TIM6_CCMR1ALTERNATE6 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM6_CCMR2ALTERNATE22 -+ TIM6_CCMR2ALTERNATE22 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM6_CCER -+ TIM6_CCER -+ TIM6 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM6_CNT -+ TIM6_CNT -+ TIM6 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM6_PSC -+ TIM6_PSC -+ TIM6 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_ARR -+ TIM6_ARR -+ TIM6 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_RCR -+ TIM6_RCR -+ TIM6 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_CCR1 -+ TIM6_CCR1 -+ TIM6 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_CCR2 -+ TIM6_CCR2 -+ TIM6 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_CCR3 -+ TIM6_CCR3 -+ TIM6 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_CCR4 -+ TIM6_CCR4 -+ TIM6 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM6_BDTR -+ TIM6_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM6_DCR -+ TIM6_DCR -+ TIM6 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM6_DMAR -+ TIM6_DMAR -+ TIM6 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM6_CCMR3 -+ TIM6_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM6_CCR5 -+ TIM6_CCR5 -+ TIM6 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM6_CCR6 -+ TIM6_CCR6 -+ TIM6 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM7 -+ TIM7 -+ TIM7 -+ 0x40005000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM7_CR1 -+ TIM7_CR1 -+ TIM7 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM7_CR2 -+ TIM7_CR2 -+ TIM7 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM7_SMCR -+ TIM7_SMCR -+ TIM7 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM7_DIER -+ TIM7_DIER -+ TIM7 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM7_SR -+ TIM7_SR -+ TIM7 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM7_EGR -+ TIM7_EGR -+ TIM7 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM7_CCMR1ALTERNATE7 -+ TIM7_CCMR1ALTERNATE7 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM7_CCMR2ALTERNATE23 -+ TIM7_CCMR2ALTERNATE23 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM7_CCER -+ TIM7_CCER -+ TIM7 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM7_CNT -+ TIM7_CNT -+ TIM7 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM7_PSC -+ TIM7_PSC -+ TIM7 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_ARR -+ TIM7_ARR -+ TIM7 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_RCR -+ TIM7_RCR -+ TIM7 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_CCR1 -+ TIM7_CCR1 -+ TIM7 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_CCR2 -+ TIM7_CCR2 -+ TIM7 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_CCR3 -+ TIM7_CCR3 -+ TIM7 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_CCR4 -+ TIM7_CCR4 -+ TIM7 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM7_BDTR -+ TIM7_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM7_DCR -+ TIM7_DCR -+ TIM7 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM7_DMAR -+ TIM7_DMAR -+ TIM7 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM7_CCMR3 -+ TIM7_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM7_CCR5 -+ TIM7_CCR5 -+ TIM7 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM7_CCR6 -+ TIM7_CCR6 -+ TIM7 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ -+ -+ TIM8 -+ TIM8 -+ TIM8 -+ 0x44001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM8_CR1 -+ TIM8_CR1 -+ TIM8 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ DIR -+ DIR -+ 4 -+ 1 -+ -+ -+ CMS -+ CMS -+ 5 -+ 2 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM8_CR2 -+ TIM8_CR2 -+ TIM8 control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ -+ -+ OIS2N -+ OIS2N -+ 11 -+ 1 -+ -+ -+ OIS3 -+ OIS3 -+ 12 -+ 1 -+ -+ -+ OIS3N -+ OIS3N -+ 13 -+ 1 -+ -+ -+ OIS4 -+ OIS4 -+ 14 -+ 1 -+ -+ -+ OIS5 -+ OIS5 -+ 16 -+ 1 -+ -+ -+ OIS6 -+ OIS6 -+ 18 -+ 1 -+ -+ -+ MMS2 -+ MMS2 -+ 20 -+ 4 -+ -+ -+ -+ -+ TIM8_SMCR -+ TIM8_SMCR -+ TIM8 slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SMS -+ SMS -+ 0 -+ 3 -+ -+ -+ TS -+ TS -+ 4 -+ 3 -+ -+ -+ MSM -+ MSM -+ 7 -+ 1 -+ -+ -+ ETF -+ ETF -+ 8 -+ 4 -+ -+ -+ ETPS -+ ETPS -+ 12 -+ 2 -+ -+ -+ ECE -+ ECE -+ 14 -+ 1 -+ -+ -+ ETP -+ ETP -+ 15 -+ 1 -+ -+ -+ SMS3 -+ SMS3 -+ 16 -+ 1 -+ -+ -+ TS3 -+ TS3 -+ 20 -+ 1 -+ -+ -+ TS4 -+ TS4 -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM8_DIER -+ TIM8_DIER -+ TIM8 DMA/interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ -+ -+ CC3IE -+ CC3IE -+ 3 -+ 1 -+ -+ -+ CC4IE -+ CC4IE -+ 4 -+ 1 -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ -+ -+ CC3DE -+ CC3DE -+ 11 -+ 1 -+ -+ -+ CC4DE -+ CC4DE -+ 12 -+ 1 -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ -+ -+ -+ -+ TIM8_SR -+ TIM8_SR -+ TIM8 status register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ -+ -+ CC3IF -+ CC3IF -+ 3 -+ 1 -+ -+ -+ CC4IF -+ CC4IF -+ 4 -+ 1 -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ -+ -+ B2IF -+ B2IF -+ 8 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ -+ -+ CC3OF -+ CC3OF -+ 11 -+ 1 -+ -+ -+ CC4OF -+ CC4OF -+ 12 -+ 1 -+ -+ -+ SBIF -+ SBIF -+ 13 -+ 1 -+ -+ -+ CC5IF -+ CC5IF -+ 16 -+ 1 -+ -+ -+ CC6IF -+ CC6IF -+ 17 -+ 1 -+ -+ -+ -+ -+ TIM8_EGR -+ TIM8_EGR -+ TIM8 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ CC2G -+ CC2G -+ 2 -+ 1 -+ -+ -+ CC3G -+ CC3G -+ 3 -+ 1 -+ -+ -+ CC4G -+ CC4G -+ 4 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ TG -+ TG -+ 6 -+ 1 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ B2G -+ B2G -+ 8 -+ 1 -+ -+ -+ -+ -+ TIM8_CCMR1ALTERNATE8 -+ TIM8_CCMR1ALTERNATE8 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ IC1PSC -+ IC1PSC -+ 2 -+ 2 -+ -+ -+ IC1F -+ IC1F -+ 4 -+ 4 -+ -+ -+ CC2S -+ CC2S -+ 8 -+ 2 -+ -+ -+ IC2PSC -+ IC2PSC -+ 10 -+ 2 -+ -+ -+ IC2F -+ IC2F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM8_CCMR2ALTERNATE24 -+ TIM8_CCMR2ALTERNATE24 -+ The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC3S -+ CC3S -+ 0 -+ 2 -+ -+ -+ IC3PSC -+ IC3PSC -+ 2 -+ 2 -+ -+ -+ IC3F -+ IC3F -+ 4 -+ 4 -+ -+ -+ CC4S -+ CC4S -+ 8 -+ 2 -+ -+ -+ IC4PSC -+ IC4PSC -+ 10 -+ 2 -+ -+ -+ IC4F -+ IC4F -+ 12 -+ 4 -+ -+ -+ -+ -+ TIM8_CCER -+ TIM8_CCER -+ TIM8 capture/compare enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ -+ -+ CC2NE -+ CC2NE -+ 6 -+ 1 -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ -+ -+ CC3E -+ CC3E -+ 8 -+ 1 -+ -+ -+ CC3P -+ CC3P -+ 9 -+ 1 -+ -+ -+ CC3NE -+ CC3NE -+ 10 -+ 1 -+ -+ -+ CC3NP -+ CC3NP -+ 11 -+ 1 -+ -+ -+ CC4E -+ CC4E -+ 12 -+ 1 -+ -+ -+ CC4P -+ CC4P -+ 13 -+ 1 -+ -+ -+ CC4NP -+ CC4NP -+ 15 -+ 1 -+ -+ -+ CC5E -+ CC5E -+ 16 -+ 1 -+ -+ -+ CC5P -+ CC5P -+ 17 -+ 1 -+ -+ -+ CC6E -+ CC6E -+ 20 -+ 1 -+ -+ -+ CC6P -+ CC6P -+ 21 -+ 1 -+ -+ -+ -+ -+ TIM8_CNT -+ TIM8_CNT -+ TIM8 counter -+ 0x24 -+ 0x20 -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM8_PSC -+ TIM8_PSC -+ TIM8 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_ARR -+ TIM8_ARR -+ TIM8 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_RCR -+ TIM8_RCR -+ TIM8 repetition counter register -+ 0x30 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ REP -+ REP -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_CCR1 -+ TIM8_CCR1 -+ TIM8 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_CCR2 -+ TIM8_CCR2 -+ TIM8 capture/compare register 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_CCR3 -+ TIM8_CCR3 -+ TIM8 capture/compare register 3 -+ 0x3C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR3 -+ CCR3 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_CCR4 -+ TIM8_CCR4 -+ TIM8 capture/compare register 4 -+ 0x40 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR4 -+ CCR4 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_BDTR -+ TIM8_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ -+ -+ BK2F -+ BK2F -+ 20 -+ 4 -+ -+ -+ BK2E -+ BK2E -+ 24 -+ 1 -+ -+ -+ BK2P -+ BK2P -+ 25 -+ 1 -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ -+ -+ BK2DSRM -+ BK2DSRM -+ 27 -+ 1 -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ -+ -+ BK2BID -+ BK2BID -+ 29 -+ 1 -+ -+ -+ -+ -+ TIM8_DCR -+ TIM8_DCR -+ TIM8 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ -+ -+ -+ -+ TIM8_DMAR -+ TIM8_DMAR -+ TIM8 DMA address for full transfer -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ TIM8_CCMR3 -+ TIM8_CCMR3 -+ The channels 5 and 6 can only be configured in output. Output compare mode: -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC5FE -+ OC5FE -+ 2 -+ 1 -+ -+ -+ OC5PE -+ OC5PE -+ 3 -+ 1 -+ -+ -+ OC5M -+ OC5M -+ 4 -+ 3 -+ -+ -+ OC5CE -+ OC5CE -+ 7 -+ 1 -+ -+ -+ OC6FE -+ OC6FE -+ 10 -+ 1 -+ -+ -+ OC6PE -+ OC6PE -+ 11 -+ 1 -+ -+ -+ OC6M -+ OC6M -+ 12 -+ 3 -+ -+ -+ OC6CE -+ OC6CE -+ 15 -+ 1 -+ -+ -+ OC5M3 -+ OC5M3 -+ 16 -+ 1 -+ -+ -+ OC6M3 -+ OC6M3 -+ 24 -+ 1 -+ -+ -+ -+ -+ TIM8_CCR5 -+ TIM8_CCR5 -+ TIM8 capture/compare register 5 -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCR5 -+ CCR5 -+ 0 -+ 16 -+ -+ -+ GC5C1 -+ GC5C1 -+ 29 -+ 1 -+ -+ -+ GC5C2 -+ GC5C2 -+ 30 -+ 1 -+ -+ -+ GC5C3 -+ GC5C3 -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM8_CCR6 -+ TIM8_CCR6 -+ TIM8 capture/compare register 6 -+ 0x5C -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR6 -+ CCR6 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM8_AF1 -+ TIM8_AF1 -+ TIM8 Alternate function option register 1 -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BKINE -+ BKINE -+ 0 -+ 1 -+ -+ -+ BKDF1BK2E -+ BKDF1BK2E -+ 8 -+ 1 -+ -+ -+ BKINP -+ BKINP -+ 9 -+ 1 -+ -+ -+ ETRSEL -+ ETRSEL -+ 14 -+ 4 -+ -+ -+ -+ -+ TIM8_AF2 -+ TIM8_AF2 -+ TIM8 Alternate function option register 2 -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BK2INE -+ BK2INE -+ 0 -+ 1 -+ -+ -+ BK2DF1BK3E -+ BK2DF1BK3E -+ 8 -+ 1 -+ -+ -+ BK2INP -+ BK2INP -+ 9 -+ 1 -+ -+ -+ -+ -+ TIM8_TISEL -+ TIM8_TISEL -+ TIM8 timer input selection register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ -+ -+ TI2SEL -+ TI2SEL -+ 8 -+ 4 -+ -+ -+ TI3SEL -+ TI3SEL -+ 16 -+ 4 -+ -+ -+ TI4SEL -+ TI4SEL -+ 24 -+ 4 -+ -+ -+ -+ -+ -+ -+ TIM13 -+ TIM13 -+ TIM13 -+ 0x40007000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM13_CR1 -+ TIM13_CR1 -+ TIM13 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM13_DIER -+ TIM13_DIER -+ TIM13 Interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ -+ -+ TIM13_SR -+ TIM13_SR -+ TIM13 status register -+ 0x10 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ -+ -+ TIM13_EGR -+ TIM13_EGR -+ TIM13 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ -+ -+ TIM13_CCMR1 -+ TIM13_CCMR1 -+ The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ OC1FE -+ OC1FE -+ 2 -+ 1 -+ -+ -+ OC1PE -+ OC1PE -+ 3 -+ 1 -+ -+ -+ OC1M -+ OC1M -+ 4 -+ 3 -+ -+ -+ OC1M3 -+ OC1M3 -+ 16 -+ 1 -+ -+ -+ -+ -+ TIM13_CCER -+ TIM13_CCER -+ TIM13 capture/compare enable register -+ 0x20 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ -+ -+ TIM13_CNT -+ TIM13_CNT -+ TIM13 counter -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM13_PSC -+ TIM13_PSC -+ TIM13 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM13_ARR -+ TIM13_ARR -+ TIM13 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM13_CCR1 -+ TIM13_CCR1 -+ TIM13 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM13_TISEL -+ TIM13_TISEL -+ TIM13 timer input selection register -+ 0x68 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ -+ -+ -+ -+ -+ -+ TIM14 -+ TIM14 -+ TIM14 -+ 0x40008000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM14_CR1 -+ TIM14_CR1 -+ TIM14 control register 1 -+ 0x0 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ -+ -+ -+ -+ TIM14_DIER -+ TIM14_DIER -+ TIM14 Interrupt enable register -+ 0xC -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ -+ -+ -+ -+ TIM14_SR -+ TIM14_SR -+ TIM14 status register -+ 0x10 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ -+ -+ -+ -+ TIM14_EGR -+ TIM14_EGR -+ TIM14 event generation register -+ 0x14 -+ 0x10 -+ write-only -+ 0x00000000 -+ -+ -+ UG -+ UG -+ 0 -+ 1 -+ -+ -+ CC1G -+ CC1G -+ 1 -+ 1 -+ -+ -+ -+ -+ TIM14_CCMR1 -+ TIM14_CCMR1 -+ The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CC1S -+ CC1S -+ 0 -+ 2 -+ -+ -+ OC1FE -+ OC1FE -+ 2 -+ 1 -+ -+ -+ OC1PE -+ OC1PE -+ 3 -+ 1 -+ -+ -+ OC1M -+ OC1M -+ 4 -+ 3 -+ -+ -+ OC1M3 -+ OC1M3 -+ 16 -+ 1 -+ -+ -+ -+ -+ TIM14_CCER -+ TIM14_CCER -+ TIM14 capture/compare enable register -+ 0x20 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ -+ -+ -+ -+ TIM14_CNT -+ TIM14_CNT -+ TIM14 counter -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ -+ -+ -+ -+ TIM14_PSC -+ TIM14_PSC -+ TIM14 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM14_ARR -+ TIM14_ARR -+ TIM14 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0x0000FFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM14_CCR1 -+ TIM14_CCR1 -+ TIM14 capture/compare register 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ -+ -+ -+ -+ TIM14_TISEL -+ TIM14_TISEL -+ TIM14 timer input selection register -+ 0x68 -+ 0x10 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ -+ -+ -+ -+ -+ -+ I2C2 -+ I2C2 -+ I2C2_IPXACT -+ 0x40013000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ I2C_CR1 -+ I2C_CR1 -+ Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PE -+ PE -+ 0 -+ 1 -+ -+ -+ TXIE -+ TXIE -+ 1 -+ 1 -+ -+ -+ RXIE -+ RXIE -+ 2 -+ 1 -+ -+ -+ ADDRIE -+ ADDRIE -+ 3 -+ 1 -+ -+ -+ NACKIE -+ NACKIE -+ 4 -+ 1 -+ -+ -+ STOPIE -+ STOPIE -+ 5 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 6 -+ 1 -+ -+ -+ ERRIE -+ ERRIE -+ 7 -+ 1 -+ -+ -+ DNF -+ DNF -+ 8 -+ 4 -+ -+ -+ ANFOFF -+ ANFOFF -+ 12 -+ 1 -+ -+ -+ TXDMAEN -+ TXDMAEN -+ 14 -+ 1 -+ -+ -+ RXDMAEN -+ RXDMAEN -+ 15 -+ 1 -+ -+ -+ SBC -+ SBC -+ 16 -+ 1 -+ -+ -+ NOSTRETCH -+ NOSTRETCH -+ 17 -+ 1 -+ -+ -+ WUPEN -+ WUPEN -+ 18 -+ 1 -+ -+ -+ GCEN -+ GCEN -+ 19 -+ 1 -+ -+ -+ SMBHEN -+ SMBHEN -+ 20 -+ 1 -+ -+ -+ SMBDEN -+ SMBDEN -+ 21 -+ 1 -+ -+ -+ ALERTEN -+ ALERTEN -+ 22 -+ 1 -+ -+ -+ PECEN -+ PECEN -+ 23 -+ 1 -+ -+ -+ -+ -+ I2C_CR2 -+ I2C_CR2 -+ Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SADD -+ SADD -+ 0 -+ 10 -+ -+ -+ RD_WRN -+ RD_WRN -+ 10 -+ 1 -+ -+ -+ ADD10 -+ ADD10 -+ 11 -+ 1 -+ -+ -+ HEAD10R -+ HEAD10R -+ 12 -+ 1 -+ -+ -+ START -+ START -+ 13 -+ 1 -+ -+ -+ STOP -+ STOP -+ 14 -+ 1 -+ -+ -+ NACK -+ NACK -+ 15 -+ 1 -+ -+ -+ NBYTES -+ NBYTES -+ 16 -+ 8 -+ -+ -+ RELOAD -+ RELOAD -+ 24 -+ 1 -+ -+ -+ AUTOEND -+ AUTOEND -+ 25 -+ 1 -+ -+ -+ PECBYTE -+ PECBYTE -+ 26 -+ 1 -+ -+ -+ -+ -+ I2C_OAR1 -+ I2C_OAR1 -+ Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OA1 -+ OA1 -+ 0 -+ 10 -+ -+ -+ OA1MODE -+ OA1MODE -+ 10 -+ 1 -+ -+ -+ OA1EN -+ OA1EN -+ 15 -+ 1 -+ -+ -+ -+ -+ I2C_OAR2 -+ I2C_OAR2 -+ Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OA2 -+ OA2 -+ 1 -+ 7 -+ -+ -+ OA2MSK -+ OA2MSK -+ 8 -+ 3 -+ -+ -+ OA2EN -+ OA2EN -+ 15 -+ 1 -+ -+ -+ -+ -+ I2C_TIMINGR -+ I2C_TIMINGR -+ Access: No wait states -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SCLL -+ SCLL -+ 0 -+ 8 -+ -+ -+ SCLH -+ SCLH -+ 8 -+ 8 -+ -+ -+ SDADEL -+ SDADEL -+ 16 -+ 4 -+ -+ -+ SCLDEL -+ SCLDEL -+ 20 -+ 4 -+ -+ -+ PRESC -+ PRESC -+ 28 -+ 4 -+ -+ -+ -+ -+ I2C_TIMEOUTR -+ I2C_TIMEOUTR -+ Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIMEOUTA -+ TIMEOUTA -+ 0 -+ 12 -+ -+ -+ TIDLE -+ TIDLE -+ 12 -+ 1 -+ -+ -+ TIMOUTEN -+ TIMOUTEN -+ 15 -+ 1 -+ -+ -+ TIMEOUTB -+ TIMEOUTB -+ 16 -+ 12 -+ -+ -+ TEXTEN -+ TEXTEN -+ 31 -+ 1 -+ -+ -+ -+ -+ I2C_ISR -+ I2C_ISR -+ Access: No wait states -+ 0x18 -+ 0x20 -+ 0x00000001 -+ -+ -+ TXE -+ TXE -+ 0 -+ 1 -+ read-write -+ -+ -+ TXIS -+ TXIS -+ 1 -+ 1 -+ read-write -+ -+ -+ RXNE -+ RXNE -+ 2 -+ 1 -+ read-only -+ -+ -+ ADDR -+ ADDR -+ 3 -+ 1 -+ read-only -+ -+ -+ NACKF -+ NACKF -+ 4 -+ 1 -+ read-only -+ -+ -+ STOPF -+ STOPF -+ 5 -+ 1 -+ read-only -+ -+ -+ TC -+ TC -+ 6 -+ 1 -+ read-only -+ -+ -+ TCR -+ TCR -+ 7 -+ 1 -+ read-only -+ -+ -+ BERR -+ BERR -+ 8 -+ 1 -+ read-only -+ -+ -+ ARLO -+ ARLO -+ 9 -+ 1 -+ read-only -+ -+ -+ OVR -+ OVR -+ 10 -+ 1 -+ read-only -+ -+ -+ PECERR -+ PECERR -+ 11 -+ 1 -+ read-only -+ -+ -+ TIMEOUT -+ TIMEOUT -+ 12 -+ 1 -+ read-only -+ -+ -+ ALERT -+ ALERT -+ 13 -+ 1 -+ read-only -+ -+ -+ BUSY -+ BUSY -+ 15 -+ 1 -+ read-only -+ -+ -+ DIR -+ DIR -+ 16 -+ 1 -+ read-only -+ -+ -+ ADDCODE -+ ADDCODE -+ 17 -+ 7 -+ read-only -+ -+ -+ -+ -+ I2C_ICR -+ I2C_ICR -+ Access: No wait states -+ 0x1C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ ADDRCF -+ ADDRCF -+ 3 -+ 1 -+ -+ -+ NACKCF -+ NACKCF -+ 4 -+ 1 -+ -+ -+ STOPCF -+ STOPCF -+ 5 -+ 1 -+ -+ -+ BERRCF -+ BERRCF -+ 8 -+ 1 -+ -+ -+ ARLOCF -+ ARLOCF -+ 9 -+ 1 -+ -+ -+ OVRCF -+ OVRCF -+ 10 -+ 1 -+ -+ -+ PECCF -+ PECCF -+ 11 -+ 1 -+ -+ -+ TIMOUTCF -+ TIMOUTCF -+ 12 -+ 1 -+ -+ -+ ALERTCF -+ ALERTCF -+ 13 -+ 1 -+ -+ -+ -+ -+ I2C_PECR -+ I2C_PECR -+ Access: No wait states -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PEC -+ PEC -+ 0 -+ 8 -+ -+ -+ -+ -+ I2C_RXDR -+ I2C_RXDR -+ Access: No wait states -+ 0x24 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXDATA -+ RXDATA -+ 0 -+ 8 -+ -+ -+ -+ -+ I2C_TXDR -+ I2C_TXDR -+ Access: No wait states -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXDATA -+ TXDATA -+ 0 -+ 8 -+ -+ -+ -+ -+ I2C_HWCFGR -+ I2C_HWCFGR -+ I2C hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000111 -+ -+ -+ SMBUS -+ SMBUS -+ 0 -+ 4 -+ -+ -+ ASYN -+ ASYN -+ 4 -+ 4 -+ -+ -+ WKP -+ WKP -+ 8 -+ 4 -+ -+ -+ -+ -+ I2C_VERR -+ I2C_VERR -+ I2C version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000012 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ I2C_IPIDR -+ I2C_IPIDR -+ I2C identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130012 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ I2C_SIDR -+ I2C_SIDR -+ I2C size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ I2C1 -+ 0x40012000 -+ -+ -+ I2C3 -+ 0x40014000 -+ -+ -+ I2C4 -+ 0x5C002000 -+ -+ -+ I2C5 -+ 0x40015000 -+ -+ -+ I2C6 -+ 0x5C009000 -+ -+ -+ RTC -+ RTC -+ RTC -+ 0x5C004000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ RTC_WKUP_ALARM -+ RTC Tamper or TimeStamp -+ 3 -+ -+ -+ RTC_WKUP_ALARM_S -+ RTC wakeup timer and alarms (A and B) secure interrupt -+ 198 -+ -+ -+ RTC_TS -+ RTC timestamp interrupt -+ 41 -+ -+ -+ RTC_TS_S -+ RTC timestamp secure interrupt -+ 199 -+ -+ -+ -+ RTC_TR -+ RTC_TR -+ The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SU -+ SU -+ 0 -+ 4 -+ -+ -+ ST -+ ST -+ 4 -+ 3 -+ -+ -+ MNU -+ MNU -+ 8 -+ 4 -+ -+ -+ MNT -+ MNT -+ 12 -+ 3 -+ -+ -+ HU -+ HU -+ 16 -+ 4 -+ -+ -+ HT -+ HT -+ 20 -+ 2 -+ -+ -+ PM -+ PM -+ 22 -+ 1 -+ -+ -+ -+ -+ RTC_DR -+ RTC_DR -+ The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00002101 -+ -+ -+ DU -+ DU -+ 0 -+ 4 -+ -+ -+ DT -+ DT -+ 4 -+ 2 -+ -+ -+ MU -+ MU -+ 8 -+ 4 -+ -+ -+ MT -+ MT -+ 12 -+ 1 -+ -+ -+ WDU -+ WDU -+ 13 -+ 3 -+ -+ -+ YU -+ YU -+ 16 -+ 4 -+ -+ -+ YT -+ YT -+ 20 -+ 4 -+ -+ -+ -+ -+ RTC_SSR -+ RTC_SSR -+ RTC sub second register -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SS -+ SS -+ 0 -+ 16 -+ -+ -+ -+ -+ RTC_ICSR -+ RTC_ICSR -+ This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0xC -+ 0x20 -+ 0x00000007 -+ -+ -+ ALRAWF -+ ALRAWF -+ 0 -+ 1 -+ read-only -+ -+ -+ ALRBWF -+ ALRBWF -+ 1 -+ 1 -+ read-only -+ -+ -+ WUTWF -+ WUTWF -+ 2 -+ 1 -+ read-only -+ -+ -+ SHPF -+ SHPF -+ 3 -+ 1 -+ read-only -+ -+ -+ INITS -+ INITS -+ 4 -+ 1 -+ read-only -+ -+ -+ RSF -+ RSF -+ 5 -+ 1 -+ read-write -+ -+ -+ INITF -+ INITF -+ 6 -+ 1 -+ read-only -+ -+ -+ INIT -+ INIT -+ 7 -+ 1 -+ read-write -+ -+ -+ RECALPF -+ RECALPF -+ 16 -+ 1 -+ read-only -+ -+ -+ -+ -+ RTC_PRER -+ RTC_PRER -+ This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x10 -+ 0x20 -+ read-write -+ 0x007F00FF -+ -+ -+ PREDIV_S -+ PREDIV_S -+ 0 -+ 15 -+ -+ -+ PREDIV_A -+ PREDIV_A -+ 16 -+ 7 -+ -+ -+ -+ -+ RTC_WUTR -+ RTC_WUTR -+ This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x14 -+ 0x20 -+ read-write -+ 0x0000FFFF -+ -+ -+ WUT -+ WUT -+ 0 -+ 16 -+ -+ -+ -+ -+ RTC_CR -+ RTC_CR -+ This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x18 -+ 0x20 -+ 0x00000000 -+ -+ -+ WUCKSEL -+ WUCKSEL -+ 0 -+ 3 -+ read-write -+ -+ -+ TSEDGE -+ TSEDGE -+ 3 -+ 1 -+ read-write -+ -+ -+ REFCKON -+ REFCKON -+ 4 -+ 1 -+ read-write -+ -+ -+ BYPSHAD -+ BYPSHAD -+ 5 -+ 1 -+ read-write -+ -+ -+ FMT -+ FMT -+ 6 -+ 1 -+ read-write -+ -+ -+ ALRAE -+ ALRAE -+ 8 -+ 1 -+ read-write -+ -+ -+ ALRBE -+ ALRBE -+ 9 -+ 1 -+ read-write -+ -+ -+ WUTE -+ WUTE -+ 10 -+ 1 -+ read-write -+ -+ -+ TSE -+ TSE -+ 11 -+ 1 -+ read-write -+ -+ -+ ALRAIE -+ ALRAIE -+ 12 -+ 1 -+ read-write -+ -+ -+ ALRBIE -+ ALRBIE -+ 13 -+ 1 -+ read-write -+ -+ -+ WUTIE -+ WUTIE -+ 14 -+ 1 -+ read-write -+ -+ -+ TSIE -+ TSIE -+ 15 -+ 1 -+ read-write -+ -+ -+ ADD1H -+ ADD1H -+ 16 -+ 1 -+ write-only -+ -+ -+ SUB1H -+ SUB1H -+ 17 -+ 1 -+ write-only -+ -+ -+ BKP -+ BKP -+ 18 -+ 1 -+ read-write -+ -+ -+ COSEL -+ COSEL -+ 19 -+ 1 -+ read-write -+ -+ -+ POL -+ POL -+ 20 -+ 1 -+ read-write -+ -+ -+ OSEL -+ OSEL -+ 21 -+ 2 -+ read-write -+ -+ -+ COE -+ COE -+ 23 -+ 1 -+ read-write -+ -+ -+ ITSE -+ ITSE -+ 24 -+ 1 -+ read-write -+ -+ -+ TAMPTS -+ TAMPTS -+ 25 -+ 1 -+ read-write -+ -+ -+ TAMPOE -+ TAMPOE -+ 26 -+ 1 -+ read-write -+ -+ -+ TAMPALRM_PU -+ TAMPALRM_PU -+ 29 -+ 1 -+ read-write -+ -+ -+ TAMPALRM_TYPE -+ TAMPALRM_TYPE -+ 30 -+ 1 -+ read-write -+ -+ -+ OUT2EN -+ OUT2EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ RTC_SMCR -+ RTC_SMCR -+ This register can be written only when the APB access is secure. -+ 0x20 -+ 0x20 -+ read-write -+ 0x0000E00F -+ -+ -+ ALRADPROT -+ ALRADPROT -+ 0 -+ 1 -+ -+ -+ ALRBDPROT -+ ALRBDPROT -+ 1 -+ 1 -+ -+ -+ WUTDPROT -+ WUTDPROT -+ 2 -+ 1 -+ -+ -+ TSDPROT -+ TSDPROT -+ 3 -+ 1 -+ -+ -+ CALDPROT -+ CALDPROT -+ 13 -+ 1 -+ -+ -+ INITDPROT -+ INITDPROT -+ 14 -+ 1 -+ -+ -+ DECPROT -+ DECPROT -+ 15 -+ 1 -+ -+ -+ -+ -+ RTC_WPR -+ RTC_WPR -+ RTC write protection register -+ 0x24 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ KEY -+ KEY -+ 0 -+ 8 -+ -+ -+ -+ -+ RTC_CALR -+ RTC_CALR -+ This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CALM -+ CALM -+ 0 -+ 9 -+ -+ -+ CALW16 -+ CALW16 -+ 13 -+ 1 -+ -+ -+ CALW8 -+ CALW8 -+ 14 -+ 1 -+ -+ -+ CALP -+ CALP -+ 15 -+ 1 -+ -+ -+ -+ -+ RTC_SHIFTR -+ RTC_SHIFTR -+ This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x2C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ SUBFS -+ SUBFS -+ 0 -+ 15 -+ -+ -+ ADD1S -+ ADD1S -+ 31 -+ 1 -+ -+ -+ -+ -+ RTC_TSTR -+ RTC_TSTR -+ The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SU -+ SU -+ 0 -+ 4 -+ -+ -+ ST -+ ST -+ 4 -+ 3 -+ -+ -+ MNU -+ MNU -+ 8 -+ 4 -+ -+ -+ MNT -+ MNT -+ 12 -+ 3 -+ -+ -+ HU -+ HU -+ 16 -+ 4 -+ -+ -+ HT -+ HT -+ 20 -+ 2 -+ -+ -+ PM -+ PM -+ 22 -+ 1 -+ -+ -+ -+ -+ RTC_TSDR -+ RTC_TSDR -+ The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DU -+ DU -+ 0 -+ 4 -+ -+ -+ DT -+ DT -+ 4 -+ 2 -+ -+ -+ MU -+ MU -+ 8 -+ 4 -+ -+ -+ MT -+ MT -+ 12 -+ 1 -+ -+ -+ WDU -+ WDU -+ 13 -+ 3 -+ -+ -+ -+ -+ RTC_TSSSR -+ RTC_TSSSR -+ The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ SS -+ SS -+ 0 -+ 16 -+ -+ -+ -+ -+ RTC_ALRMAR -+ RTC_ALRMAR -+ This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SU -+ SU -+ 0 -+ 4 -+ -+ -+ ST -+ ST -+ 4 -+ 3 -+ -+ -+ MSK1 -+ MSK1 -+ 7 -+ 1 -+ -+ -+ MNU -+ MNU -+ 8 -+ 4 -+ -+ -+ MNT -+ MNT -+ 12 -+ 3 -+ -+ -+ MSK2 -+ MSK2 -+ 15 -+ 1 -+ -+ -+ HU -+ HU -+ 16 -+ 4 -+ -+ -+ HT -+ HT -+ 20 -+ 2 -+ -+ -+ PM -+ PM -+ 22 -+ 1 -+ -+ -+ MSK3 -+ MSK3 -+ 23 -+ 1 -+ -+ -+ DU -+ DU -+ 24 -+ 4 -+ -+ -+ DT -+ DT -+ 28 -+ 2 -+ -+ -+ WDSEL -+ WDSEL -+ 30 -+ 1 -+ -+ -+ MSK4 -+ MSK4 -+ 31 -+ 1 -+ -+ -+ -+ -+ RTC_ALRMASSR -+ RTC_ALRMASSR -+ This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SS -+ SS -+ 0 -+ 15 -+ -+ -+ MASKSS -+ MASKSS -+ 24 -+ 4 -+ -+ -+ -+ -+ RTC_ALRMBR -+ RTC_ALRMBR -+ This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SU -+ SU -+ 0 -+ 4 -+ -+ -+ ST -+ ST -+ 4 -+ 3 -+ -+ -+ MSK1 -+ MSK1 -+ 7 -+ 1 -+ -+ -+ MNU -+ MNU -+ 8 -+ 4 -+ -+ -+ MNT -+ MNT -+ 12 -+ 3 -+ -+ -+ MSK2 -+ MSK2 -+ 15 -+ 1 -+ -+ -+ HU -+ HU -+ 16 -+ 4 -+ -+ -+ HT -+ HT -+ 20 -+ 2 -+ -+ -+ PM -+ PM -+ 22 -+ 1 -+ -+ -+ MSK3 -+ MSK3 -+ 23 -+ 1 -+ -+ -+ DU -+ DU -+ 24 -+ 4 -+ -+ -+ DT -+ DT -+ 28 -+ 2 -+ -+ -+ WDSEL -+ WDSEL -+ 30 -+ 1 -+ -+ -+ MSK4 -+ MSK4 -+ 31 -+ 1 -+ -+ -+ -+ -+ RTC_ALRMBSSR -+ RTC_ALRMBSSR -+ This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SS -+ SS -+ 0 -+ 15 -+ -+ -+ MASKSS -+ MASKSS -+ 24 -+ 4 -+ -+ -+ -+ -+ RTC_SR -+ RTC_SR -+ This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x50 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ALRAF -+ ALRAF -+ 0 -+ 1 -+ -+ -+ ALRBF -+ ALRBF -+ 1 -+ 1 -+ -+ -+ WUTF -+ WUTF -+ 2 -+ 1 -+ -+ -+ TSF -+ TSF -+ 3 -+ 1 -+ -+ -+ TSOVF -+ TSOVF -+ 4 -+ 1 -+ -+ -+ ITSF -+ ITSF -+ 5 -+ 1 -+ -+ -+ -+ -+ RTC_MISR -+ RTC_MISR -+ RTC non-secure masked interrupt status register -+ 0x54 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ALRAMF -+ ALRAMF -+ 0 -+ 1 -+ -+ -+ ALRBMF -+ ALRBMF -+ 1 -+ 1 -+ -+ -+ WUTMF -+ WUTMF -+ 2 -+ 1 -+ -+ -+ TSMF -+ TSMF -+ 3 -+ 1 -+ -+ -+ TSOVMF -+ TSOVMF -+ 4 -+ 1 -+ -+ -+ ITSMF -+ ITSMF -+ 5 -+ 1 -+ -+ -+ -+ -+ RTC_SMISR -+ RTC_SMISR -+ This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x58 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ALRAMF -+ ALRAMF -+ 0 -+ 1 -+ -+ -+ ALRBMF -+ ALRBMF -+ 1 -+ 1 -+ -+ -+ WUTMF -+ WUTMF -+ 2 -+ 1 -+ -+ -+ TSMF -+ TSMF -+ 3 -+ 1 -+ -+ -+ TSOVMF -+ TSOVMF -+ 4 -+ 1 -+ -+ -+ ITSMF -+ ITSMF -+ 5 -+ 1 -+ -+ -+ -+ -+ RTC_SCR -+ RTC_SCR -+ This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. -+ 0x5C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CALRAF -+ CALRAF -+ 0 -+ 1 -+ -+ -+ CALRBF -+ CALRBF -+ 1 -+ 1 -+ -+ -+ CWUTF -+ CWUTF -+ 2 -+ 1 -+ -+ -+ CTSF -+ CTSF -+ 3 -+ 1 -+ -+ -+ CTSOVF -+ CTSOVF -+ 4 -+ 1 -+ -+ -+ CITSF -+ CITSF -+ 5 -+ 1 -+ -+ -+ -+ -+ RTC_CFGR -+ RTC_CFGR -+ RTC configuration register -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OUT2_RMP -+ OUT2_RMP -+ 0 -+ 1 -+ -+ -+ LSCOEN -+ LSCOEN -+ 1 -+ 2 -+ -+ -+ -+ -+ RTC_HWCFGR -+ RTC_HWCFGR -+ RTC hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x01031111 -+ -+ -+ ALARMB -+ ALARMB -+ 0 -+ 4 -+ -+ -+ WAKEUP -+ WAKEUP -+ 4 -+ 4 -+ -+ -+ SMOOTH_CALIB -+ SMOOTH_CALIB -+ 8 -+ 4 -+ -+ -+ TIMESTAMP -+ TIMESTAMP -+ 12 -+ 4 -+ -+ -+ OPTIONREG_OUT -+ OPTIONREG_OUT -+ 16 -+ 8 -+ -+ -+ TRUST_ZONE -+ TRUST_ZONE -+ 24 -+ 4 -+ -+ -+ -+ -+ RTC_VERR -+ RTC_VERR -+ RTC version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ RTC_IPIDR -+ RTC_IPIDR -+ RTC identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120033 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ RTC_SIDR -+ RTC_SIDR -+ RTC size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ TAMP -+ TAMP -+ TAMP -+ 0x5C00A000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ TAMP -+ Tamper interrupt (include LSECSS interrupts) -+ 2 -+ -+ -+ TAMP_S -+ TAMP tamper secure interrupt -+ 197 -+ -+ -+ -+ TAMP_CR1 -+ TAMP_CR1 -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFF0000 -+ -+ -+ TAMP1E -+ TAMP1E -+ 0 -+ 1 -+ -+ -+ TAMP2E -+ TAMP2E -+ 1 -+ 1 -+ -+ -+ TAMP3E -+ TAMP3E -+ 2 -+ 1 -+ -+ -+ ITAMP1E -+ ITAMP1E -+ 16 -+ 1 -+ -+ -+ ITAMP2E -+ ITAMP2E -+ 17 -+ 1 -+ -+ -+ ITAMP3E -+ ITAMP3E -+ 18 -+ 1 -+ -+ -+ ITAMP4E -+ ITAMP4E -+ 19 -+ 1 -+ -+ -+ ITAMP5E -+ ITAMP5E -+ 20 -+ 1 -+ -+ -+ ITAMP8E -+ ITAMP8E -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_CR2 -+ TAMP_CR2 -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TAMP1NOER -+ TAMP1NOER -+ 0 -+ 1 -+ -+ -+ TAMP2NOER -+ TAMP2NOER -+ 1 -+ 1 -+ -+ -+ TAMP3NOER -+ TAMP3NOER -+ 2 -+ 1 -+ -+ -+ TAMP1MSK -+ TAMP1MSK -+ 16 -+ 1 -+ -+ -+ TAMP2MSK -+ TAMP2MSK -+ 17 -+ 1 -+ -+ -+ TAMP3MSK -+ TAMP3MSK -+ 18 -+ 1 -+ -+ -+ TAMP1TRG -+ TAMP1TRG -+ 24 -+ 1 -+ -+ -+ TAMP2TRG -+ TAMP2TRG -+ 25 -+ 1 -+ -+ -+ TAMP3TRG -+ TAMP3TRG -+ 26 -+ 1 -+ -+ -+ -+ -+ TAMP_FLTCR -+ TAMP_FLTCR -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TAMPFREQ -+ TAMPFREQ -+ 0 -+ 3 -+ -+ -+ TAMPFLT -+ TAMPFLT -+ 3 -+ 2 -+ -+ -+ TAMPPRCH -+ TAMPPRCH -+ 5 -+ 2 -+ -+ -+ TAMPPUDIS -+ TAMPPUDIS -+ 7 -+ 1 -+ -+ -+ -+ -+ TAMP_ATCR1 -+ TAMP_ATCR1 -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00070000 -+ -+ -+ TAMP1AM -+ TAMP1AM -+ 0 -+ 1 -+ -+ -+ TAMP2AM -+ TAMP2AM -+ 1 -+ 1 -+ -+ -+ TAMP3AM -+ TAMP3AM -+ 2 -+ 1 -+ -+ -+ ATOSEL1 -+ ATOSEL1 -+ 8 -+ 2 -+ -+ -+ ATOSEL2 -+ ATOSEL2 -+ 10 -+ 2 -+ -+ -+ ATOSEL3 -+ ATOSEL3 -+ 12 -+ 2 -+ -+ -+ ATCKSEL -+ ATCKSEL -+ 16 -+ 3 -+ -+ -+ ATPER -+ ATPER -+ 24 -+ 3 -+ -+ -+ ATOSHARE -+ ATOSHARE -+ 30 -+ 1 -+ -+ -+ FLTEN -+ FLTEN -+ 31 -+ 1 -+ -+ -+ -+ -+ TAMP_ATSEEDR -+ TAMP_ATSEEDR -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x14 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ SEED -+ SEED -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_ATOR -+ TAMP_ATOR -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PRNG -+ PRNG -+ 0 -+ 8 -+ -+ -+ SEEDF -+ SEEDF -+ 14 -+ 1 -+ -+ -+ INITS -+ INITS -+ 15 -+ 1 -+ -+ -+ -+ -+ TAMP_SMCR -+ TAMP_SMCR -+ This register can be written only when the APB access is secure. -+ 0x20 -+ 0x20 -+ read-write -+ 0x80000000 -+ -+ -+ BKPRWDPROT -+ BKPRWDPROT -+ 0 -+ 8 -+ -+ -+ BKPWDPROT -+ BKPWDPROT -+ 16 -+ 8 -+ -+ -+ TAMPDPROT -+ TAMPDPROT -+ 31 -+ 1 -+ -+ -+ -+ -+ TAMP_IER -+ TAMP_IER -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TAMP1IE -+ TAMP1IE -+ 0 -+ 1 -+ -+ -+ TAMP2IE -+ TAMP2IE -+ 1 -+ 1 -+ -+ -+ TAMP3IE -+ TAMP3IE -+ 2 -+ 1 -+ -+ -+ ITAMP1IE -+ ITAMP1IE -+ 16 -+ 1 -+ -+ -+ ITAMP2IE -+ ITAMP2IE -+ 17 -+ 1 -+ -+ -+ ITAMP3IE -+ ITAMP3IE -+ 18 -+ 1 -+ -+ -+ ITAMP4IE -+ ITAMP4IE -+ 19 -+ 1 -+ -+ -+ ITAMP5IE -+ ITAMP5IE -+ 20 -+ 1 -+ -+ -+ ITAMP8IE -+ ITAMP8IE -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_SR -+ TAMP_SR -+ This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TAMP1F -+ TAMP1F -+ 0 -+ 1 -+ -+ -+ TAMP2F -+ TAMP2F -+ 1 -+ 1 -+ -+ -+ TAMP3F -+ TAMP3F -+ 2 -+ 1 -+ -+ -+ ITAMP1F -+ ITAMP1F -+ 16 -+ 1 -+ -+ -+ ITAMP2F -+ ITAMP2F -+ 17 -+ 1 -+ -+ -+ ITAMP3F -+ ITAMP3F -+ 18 -+ 1 -+ -+ -+ ITAMP4F -+ ITAMP4F -+ 19 -+ 1 -+ -+ -+ ITAMP5F -+ ITAMP5F -+ 20 -+ 1 -+ -+ -+ ITAMP8F -+ ITAMP8F -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_MISR -+ TAMP_MISR -+ TAMP non-secure masked interrupt status register -+ 0x34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TAMP1MF -+ TAMP1MF -+ 0 -+ 1 -+ -+ -+ TAMP2MF -+ TAMP2MF -+ 1 -+ 1 -+ -+ -+ TAMP3MF -+ TAMP3MF -+ 2 -+ 1 -+ -+ -+ ITAMP1MF -+ ITAMP1MF -+ 16 -+ 1 -+ -+ -+ ITAMP2MF -+ ITAMP2MF -+ 17 -+ 1 -+ -+ -+ ITAMP3MF -+ ITAMP3MF -+ 18 -+ 1 -+ -+ -+ ITAMP4MF -+ ITAMP4MF -+ 19 -+ 1 -+ -+ -+ ITAMP5MF -+ ITAMP5MF -+ 20 -+ 1 -+ -+ -+ ITAMP8MF -+ ITAMP8MF -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_SMISR -+ TAMP_SMISR -+ TAMP secure masked interrupt status register -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TAMP1MF -+ TAMP1MF -+ 0 -+ 1 -+ -+ -+ TAMP2MF -+ TAMP2MF -+ 1 -+ 1 -+ -+ -+ TAMP3MF -+ TAMP3MF -+ 2 -+ 1 -+ -+ -+ ITAMP1MF -+ ITAMP1MF -+ 16 -+ 1 -+ -+ -+ ITAMP2MF -+ ITAMP2MF -+ 17 -+ 1 -+ -+ -+ ITAMP3MF -+ ITAMP3MF -+ 18 -+ 1 -+ -+ -+ ITAMP4MF -+ ITAMP4MF -+ 19 -+ 1 -+ -+ -+ ITAMP5MF -+ ITAMP5MF -+ 20 -+ 1 -+ -+ -+ ITAMP8MF -+ ITAMP8MF -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_SCR -+ TAMP_SCR -+ TAMP status clear register -+ 0x3C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTAMP1F -+ CTAMP1F -+ 0 -+ 1 -+ -+ -+ CTAMP2F -+ CTAMP2F -+ 1 -+ 1 -+ -+ -+ CTAMP3F -+ CTAMP3F -+ 2 -+ 1 -+ -+ -+ CITAMP1F -+ CITAMP1F -+ 16 -+ 1 -+ -+ -+ CITAMP2F -+ CITAMP2F -+ 17 -+ 1 -+ -+ -+ CITAMP3F -+ CITAMP3F -+ 18 -+ 1 -+ -+ -+ CITAMP4F -+ CITAMP4F -+ 19 -+ 1 -+ -+ -+ CITAMP5F -+ CITAMP5F -+ 20 -+ 1 -+ -+ -+ CITAMP8F -+ CITAMP8F -+ 23 -+ 1 -+ -+ -+ -+ -+ TAMP_COUNTR -+ TAMP_COUNTR -+ TAMP monotonic counter register -+ 0x40 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ COUNT -+ COUNT -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_CFGR -+ TAMP_CFGR -+ TAMP configuration register -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OUT3_RMP -+ OUT3_RMP -+ 0 -+ 1 -+ -+ -+ -+ -+ TAMP_BKP0R -+ TAMP_BKP0R -+ TAMP backup 0 register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP1R -+ TAMP_BKP1R -+ TAMP backup 1 register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP2R -+ TAMP_BKP2R -+ TAMP backup 2 register -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP3R -+ TAMP_BKP3R -+ TAMP backup 3 register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP4R -+ TAMP_BKP4R -+ TAMP backup 4 register -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP5R -+ TAMP_BKP5R -+ TAMP backup 5 register -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP6R -+ TAMP_BKP6R -+ TAMP backup 6 register -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP7R -+ TAMP_BKP7R -+ TAMP backup 7 register -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP8R -+ TAMP_BKP8R -+ TAMP backup 8 register -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP9R -+ TAMP_BKP9R -+ TAMP backup 9 register -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP10R -+ TAMP_BKP10R -+ TAMP backup 10 register -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP11R -+ TAMP_BKP11R -+ TAMP backup 11 register -+ 0x12C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP12R -+ TAMP_BKP12R -+ TAMP backup 12 register -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP13R -+ TAMP_BKP13R -+ TAMP backup 13 register -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP14R -+ TAMP_BKP14R -+ TAMP backup 14 register -+ 0x138 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP15R -+ TAMP_BKP15R -+ TAMP backup 15 register -+ 0x13C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP16R -+ TAMP_BKP16R -+ TAMP backup 16 register -+ 0x140 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP17R -+ TAMP_BKP17R -+ TAMP backup 17 register -+ 0x144 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP18R -+ TAMP_BKP18R -+ TAMP backup 18 register -+ 0x148 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP19R -+ TAMP_BKP19R -+ TAMP backup 19 register -+ 0x14C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP20R -+ TAMP_BKP20R -+ TAMP backup 20 register -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP21R -+ TAMP_BKP21R -+ TAMP backup 21 register -+ 0x154 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP22R -+ TAMP_BKP22R -+ TAMP backup 22 register -+ 0x158 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP23R -+ TAMP_BKP23R -+ TAMP backup 23 register -+ 0x15C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP24R -+ TAMP_BKP24R -+ TAMP backup 24 register -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP25R -+ TAMP_BKP25R -+ TAMP backup 25 register -+ 0x164 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP26R -+ TAMP_BKP26R -+ TAMP backup 26 register -+ 0x168 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP27R -+ TAMP_BKP27R -+ TAMP backup 27 register -+ 0x16C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP28R -+ TAMP_BKP28R -+ TAMP backup 28 register -+ 0x170 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP29R -+ TAMP_BKP29R -+ TAMP backup 29 register -+ 0x174 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP30R -+ TAMP_BKP30R -+ TAMP backup 30 register -+ 0x178 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_BKP31R -+ TAMP_BKP31R -+ TAMP backup 31 register -+ 0x17C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BKP -+ BKP -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_HWCFGR2 -+ TAMP_HWCFGR2 -+ TAMP hardware configuration register 2 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000101 -+ -+ -+ OPTIONREG_OUT -+ OPTIONREG_OUT -+ 0 -+ 8 -+ -+ -+ TRUST_ZONE -+ TRUST_ZONE -+ 8 -+ 4 -+ -+ -+ -+ -+ TAMP_HWCFGR1 -+ TAMP_HWCFGR1 -+ TAMP hardware configuration register 1 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x009D1320 -+ -+ -+ BACKUP_REGS -+ BACKUP_REGS -+ 0 -+ 8 -+ -+ -+ TAMPER -+ TAMPER -+ 8 -+ 4 -+ -+ -+ ACTIVE_TAMPER -+ ACTIVE_TAMPER -+ 12 -+ 4 -+ -+ -+ INT_TAMPER -+ INT_TAMPER -+ 16 -+ 16 -+ -+ -+ -+ -+ TAMP_VERR -+ TAMP_VERR -+ TAMP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ TAMP_IPIDR -+ TAMP_IPIDR -+ TAMP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00121033 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ TAMP_SIDR -+ TAMP_SIDR -+ TAMP size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ STGENC -+ STGENC -+ STGENC -+ 0x5C008000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ STGENC_CNTCR -+ STGENC_CNTCR -+ STGENC control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ HLTDBG -+ HLTDBG -+ 1 -+ 1 -+ -+ -+ -+ -+ STGENC_CNTSR -+ STGENC_CNTSR -+ STGENC status register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ HLTDBG -+ HLTDBG -+ 1 -+ 1 -+ -+ -+ -+ -+ STGENC_CNTCVL -+ STGENC_CNTCVL -+ the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNTCVL_L_32 -+ CNTCVL_L_32 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_CNTCVU -+ STGENC_CNTCVU -+ the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNTCVU_U_32 -+ CNTCVU_U_32 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_CNTFID0 -+ STGENC_CNTFID0 -+ the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FREQ -+ FREQ -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_PIDR4 -+ STGENC_PIDR4 -+ STGENC peripheral ID4 register -+ 0xFD0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ DES_2 -+ DES_2 -+ 0 -+ 4 -+ -+ -+ SIZE -+ SIZE -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENC_PIDR5 -+ STGENC_PIDR5 -+ STGENC peripheral ID5 register -+ 0xFD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR5 -+ PIDR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_PIDR6 -+ STGENC_PIDR6 -+ STGENC peripheral ID6 register -+ 0xFD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR6 -+ PIDR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_PIDR7 -+ STGENC_PIDR7 -+ STGENC peripheral ID7 register -+ 0xFDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR7 -+ PIDR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENC_PIDR0 -+ STGENC_PIDR0 -+ STGENC peripheral ID0 register -+ 0xFE0 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ PART_0 -+ PART_0 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENC_PIDR1 -+ STGENC_PIDR1 -+ STGENC peripheral ID1 register -+ 0xFE4 -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ PART_1 -+ PART_1 -+ 0 -+ 4 -+ -+ -+ DES_0 -+ DES_0 -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENC_PIDR2 -+ STGENC_PIDR2 -+ STGENC peripheral ID2 register -+ 0xFE8 -+ 0x20 -+ read-only -+ 0x0000001B -+ -+ -+ DES_1 -+ DES_1 -+ 0 -+ 3 -+ -+ -+ JEDEC -+ JEDEC -+ 3 -+ 1 -+ -+ -+ REVISION -+ REVISION -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENC_PIDR3 -+ STGENC_PIDR3 -+ STGENC peripheral ID3 register -+ 0xFEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMOD -+ CMOD -+ 0 -+ 4 -+ -+ -+ REVAND -+ REVAND -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENC_CIDR0 -+ STGENC_CIDR0 -+ STGENC component ID0 register -+ 0xFF0 -+ 0x20 -+ read-only -+ 0x0000000D -+ -+ -+ PRMBL_0 -+ PRMBL_0 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENC_CIDR1 -+ STGENC_CIDR1 -+ STGENC component ID1 register -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x000000F0 -+ -+ -+ PRMBL_1 -+ PRMBL_1 -+ 0 -+ 4 -+ -+ -+ CLASS -+ CLASS -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENC_CIDR2 -+ STGENC_CIDR2 -+ STGENC component ID2 register -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00000050 -+ -+ -+ PRMBL_2 -+ PRMBL_2 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENC_CIDR3 -+ STGENC_CIDR3 -+ STGENC component ID3 register -+ 0xFFC -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ PRMBL_3 -+ PRMBL_3 -+ 0 -+ 8 -+ -+ -+ -+ -+ -+ -+ STGENR -+ STGENR -+ STGENR -+ 0x5A005000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ STGENR_CNTCVL -+ STGENR_CNTCVL -+ the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNTCVL_L_32 -+ CNTCVL_L_32 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENR_CNTCVU -+ STGENR_CNTCVU -+ the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNTCVU_U_32 -+ CNTCVU_U_32 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENR_PIDR4 -+ STGENR_PIDR4 -+ STGENR peripheral ID4 register -+ 0xFD0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ DES_2 -+ DES_2 -+ 0 -+ 4 -+ -+ -+ SIZE -+ SIZE -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENR_PIDR5 -+ STGENR_PIDR5 -+ STGENR peripheral ID5 register -+ 0xFD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR5 -+ PIDR5 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENR_PIDR6 -+ STGENR_PIDR6 -+ STGENR peripheral ID6 register -+ 0xFD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR6 -+ PIDR6 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENR_PIDR7 -+ STGENR_PIDR7 -+ STGENR peripheral ID7 register -+ 0xFDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PIDR7 -+ PIDR7 -+ 0 -+ 32 -+ -+ -+ -+ -+ STGENR_PIDR0 -+ STGENR_PIDR0 -+ STGENR peripheral ID0 register -+ 0xFE0 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ PART_0 -+ PART_0 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENR_PIDR1 -+ STGENR_PIDR1 -+ STGENR peripheral ID1 register -+ 0xFE4 -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ PART_1 -+ PART_1 -+ 0 -+ 4 -+ -+ -+ DES_0 -+ DES_0 -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENR_PIDR2 -+ STGENR_PIDR2 -+ STGENR peripheral ID2 register -+ 0xFE8 -+ 0x20 -+ read-only -+ 0x0000001B -+ -+ -+ DES_1 -+ DES_1 -+ 0 -+ 3 -+ -+ -+ JEDEC -+ JEDEC -+ 3 -+ 1 -+ -+ -+ REVISION -+ REVISION -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENR_PIDR3 -+ STGENR_PIDR3 -+ STGENR peripheral ID3 register -+ 0xFEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMOD -+ CMOD -+ 0 -+ 4 -+ -+ -+ REVAND -+ REVAND -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENR_CIDR0 -+ STGENR_CIDR0 -+ STGENR component ID0 register -+ 0xFF0 -+ 0x20 -+ read-only -+ 0x0000000D -+ -+ -+ PRMBL_0 -+ PRMBL_0 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENR_CIDR1 -+ STGENR_CIDR1 -+ STGENR component ID1 register -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x000000F0 -+ -+ -+ PRMBL_1 -+ PRMBL_1 -+ 0 -+ 4 -+ -+ -+ CLASS -+ CLASS -+ 4 -+ 4 -+ -+ -+ -+ -+ STGENR_CIDR2 -+ STGENR_CIDR2 -+ STGENR component ID2 register -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00000050 -+ -+ -+ PRMBL_2 -+ PRMBL_2 -+ 0 -+ 8 -+ -+ -+ -+ -+ STGENR_CIDR3 -+ STGENR_CIDR3 -+ STGENR component ID3 register -+ 0xFFC -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ PRMBL_3 -+ PRMBL_3 -+ 0 -+ 8 -+ -+ -+ -+ -+ -+ -+ ETZPC -+ ETZPC -+ ETZPC -+ 0x5C007000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ ETZPC_TZMA0_SIZE -+ ETZPC_TZMA0_SIZE -+ ETZPC ROM secure size definition -+ 0x0 -+ 0x20 -+ read-write -+ 0x000003FF -+ -+ -+ R0SIZE -+ R0SIZE -+ 0 -+ 10 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ ETZPC_TZMA1_SIZE -+ ETZPC_TZMA1_SIZE -+ ETZPC RAM secure size definition -+ 0x4 -+ 0x20 -+ read-write -+ 0x000003FF -+ -+ -+ R0SIZE -+ R0SIZE -+ 0 -+ 10 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ ETZPC_DECPROT0 -+ ETZPC_DECPROT0 -+ Register reset values -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT1 -+ ETZPC_DECPROT1 -+ Register reset values -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT2 -+ ETZPC_DECPROT2 -+ Register reset values -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT3 -+ ETZPC_DECPROT3 -+ Register reset values -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT4 -+ ETZPC_DECPROT4 -+ Register reset values -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT5 -+ ETZPC_DECPROT5 -+ Register reset values -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DECPROT0 -+ DECPROT0 -+ 0 -+ 2 -+ -+ -+ DECPROT1 -+ DECPROT1 -+ 2 -+ 2 -+ -+ -+ DECPROT2 -+ DECPROT2 -+ 4 -+ 2 -+ -+ -+ DECPROT3 -+ DECPROT3 -+ 6 -+ 2 -+ -+ -+ DECPROT4 -+ DECPROT4 -+ 8 -+ 2 -+ -+ -+ DECPROT5 -+ DECPROT5 -+ 10 -+ 2 -+ -+ -+ DECPROT6 -+ DECPROT6 -+ 12 -+ 2 -+ -+ -+ DECPROT7 -+ DECPROT7 -+ 14 -+ 2 -+ -+ -+ DECPROT8 -+ DECPROT8 -+ 16 -+ 2 -+ -+ -+ DECPROT9 -+ DECPROT9 -+ 18 -+ 2 -+ -+ -+ DECPROT10 -+ DECPROT10 -+ 20 -+ 2 -+ -+ -+ DECPROT11 -+ DECPROT11 -+ 22 -+ 2 -+ -+ -+ DECPROT12 -+ DECPROT12 -+ 24 -+ 2 -+ -+ -+ DECPROT13 -+ DECPROT13 -+ 26 -+ 2 -+ -+ -+ DECPROT14 -+ DECPROT14 -+ 28 -+ 2 -+ -+ -+ DECPROT15 -+ DECPROT15 -+ 30 -+ 2 -+ -+ -+ -+ -+ ETZPC_DECPROT_LOCK0 -+ ETZPC_DECPROT_LOCK0 -+ ETZPC decprot lock 0 register -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LOCK0 -+ LOCK0 -+ 0 -+ 1 -+ -+ -+ LOCK1 -+ LOCK1 -+ 1 -+ 1 -+ -+ -+ LOCK2 -+ LOCK2 -+ 2 -+ 1 -+ -+ -+ LOCK3 -+ LOCK3 -+ 3 -+ 1 -+ -+ -+ LOCK4 -+ LOCK4 -+ 4 -+ 1 -+ -+ -+ LOCK5 -+ LOCK5 -+ 5 -+ 1 -+ -+ -+ LOCK6 -+ LOCK6 -+ 6 -+ 1 -+ -+ -+ LOCK7 -+ LOCK7 -+ 7 -+ 1 -+ -+ -+ LOCK8 -+ LOCK8 -+ 8 -+ 1 -+ -+ -+ LOCK9 -+ LOCK9 -+ 9 -+ 1 -+ -+ -+ LOCK10 -+ LOCK10 -+ 10 -+ 1 -+ -+ -+ LOCK11 -+ LOCK11 -+ 11 -+ 1 -+ -+ -+ LOCK12 -+ LOCK12 -+ 12 -+ 1 -+ -+ -+ LOCK13 -+ LOCK13 -+ 13 -+ 1 -+ -+ -+ LOCK14 -+ LOCK14 -+ 14 -+ 1 -+ -+ -+ LOCK15 -+ LOCK15 -+ 15 -+ 1 -+ -+ -+ LOCK16 -+ LOCK16 -+ 16 -+ 1 -+ -+ -+ LOCK17 -+ LOCK17 -+ 17 -+ 1 -+ -+ -+ LOCK18 -+ LOCK18 -+ 18 -+ 1 -+ -+ -+ LOCK19 -+ LOCK19 -+ 19 -+ 1 -+ -+ -+ LOCK20 -+ LOCK20 -+ 20 -+ 1 -+ -+ -+ LOCK21 -+ LOCK21 -+ 21 -+ 1 -+ -+ -+ LOCK22 -+ LOCK22 -+ 22 -+ 1 -+ -+ -+ LOCK23 -+ LOCK23 -+ 23 -+ 1 -+ -+ -+ LOCK24 -+ LOCK24 -+ 24 -+ 1 -+ -+ -+ LOCK25 -+ LOCK25 -+ 25 -+ 1 -+ -+ -+ LOCK26 -+ LOCK26 -+ 26 -+ 1 -+ -+ -+ LOCK27 -+ LOCK27 -+ 27 -+ 1 -+ -+ -+ LOCK28 -+ LOCK28 -+ 28 -+ 1 -+ -+ -+ LOCK29 -+ LOCK29 -+ 29 -+ 1 -+ -+ -+ LOCK30 -+ LOCK30 -+ 30 -+ 1 -+ -+ -+ LOCK31 -+ LOCK31 -+ 31 -+ 1 -+ -+ -+ -+ -+ ETZPC_DECPROT_LOCK1 -+ ETZPC_DECPROT_LOCK1 -+ ETZPC decprot lock 1 register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LOCK0 -+ LOCK0 -+ 0 -+ 1 -+ -+ -+ LOCK1 -+ LOCK1 -+ 1 -+ 1 -+ -+ -+ LOCK2 -+ LOCK2 -+ 2 -+ 1 -+ -+ -+ LOCK3 -+ LOCK3 -+ 3 -+ 1 -+ -+ -+ LOCK4 -+ LOCK4 -+ 4 -+ 1 -+ -+ -+ LOCK5 -+ LOCK5 -+ 5 -+ 1 -+ -+ -+ LOCK6 -+ LOCK6 -+ 6 -+ 1 -+ -+ -+ LOCK7 -+ LOCK7 -+ 7 -+ 1 -+ -+ -+ LOCK8 -+ LOCK8 -+ 8 -+ 1 -+ -+ -+ LOCK9 -+ LOCK9 -+ 9 -+ 1 -+ -+ -+ LOCK10 -+ LOCK10 -+ 10 -+ 1 -+ -+ -+ LOCK11 -+ LOCK11 -+ 11 -+ 1 -+ -+ -+ LOCK12 -+ LOCK12 -+ 12 -+ 1 -+ -+ -+ LOCK13 -+ LOCK13 -+ 13 -+ 1 -+ -+ -+ LOCK14 -+ LOCK14 -+ 14 -+ 1 -+ -+ -+ LOCK15 -+ LOCK15 -+ 15 -+ 1 -+ -+ -+ LOCK16 -+ LOCK16 -+ 16 -+ 1 -+ -+ -+ LOCK17 -+ LOCK17 -+ 17 -+ 1 -+ -+ -+ LOCK18 -+ LOCK18 -+ 18 -+ 1 -+ -+ -+ LOCK19 -+ LOCK19 -+ 19 -+ 1 -+ -+ -+ LOCK20 -+ LOCK20 -+ 20 -+ 1 -+ -+ -+ LOCK21 -+ LOCK21 -+ 21 -+ 1 -+ -+ -+ LOCK22 -+ LOCK22 -+ 22 -+ 1 -+ -+ -+ LOCK23 -+ LOCK23 -+ 23 -+ 1 -+ -+ -+ LOCK24 -+ LOCK24 -+ 24 -+ 1 -+ -+ -+ LOCK25 -+ LOCK25 -+ 25 -+ 1 -+ -+ -+ LOCK26 -+ LOCK26 -+ 26 -+ 1 -+ -+ -+ LOCK27 -+ LOCK27 -+ 27 -+ 1 -+ -+ -+ LOCK28 -+ LOCK28 -+ 28 -+ 1 -+ -+ -+ LOCK29 -+ LOCK29 -+ 29 -+ 1 -+ -+ -+ LOCK30 -+ LOCK30 -+ 30 -+ 1 -+ -+ -+ LOCK31 -+ LOCK31 -+ 31 -+ 1 -+ -+ -+ -+ -+ ETZPC_DECPROT_LOCK2 -+ ETZPC_DECPROT_LOCK2 -+ ETZPC decprot lock 2 register -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LOCK0 -+ LOCK0 -+ 0 -+ 1 -+ -+ -+ LOCK1 -+ LOCK1 -+ 1 -+ 1 -+ -+ -+ LOCK2 -+ LOCK2 -+ 2 -+ 1 -+ -+ -+ LOCK3 -+ LOCK3 -+ 3 -+ 1 -+ -+ -+ LOCK4 -+ LOCK4 -+ 4 -+ 1 -+ -+ -+ LOCK5 -+ LOCK5 -+ 5 -+ 1 -+ -+ -+ LOCK6 -+ LOCK6 -+ 6 -+ 1 -+ -+ -+ LOCK7 -+ LOCK7 -+ 7 -+ 1 -+ -+ -+ LOCK8 -+ LOCK8 -+ 8 -+ 1 -+ -+ -+ LOCK9 -+ LOCK9 -+ 9 -+ 1 -+ -+ -+ LOCK10 -+ LOCK10 -+ 10 -+ 1 -+ -+ -+ LOCK11 -+ LOCK11 -+ 11 -+ 1 -+ -+ -+ LOCK12 -+ LOCK12 -+ 12 -+ 1 -+ -+ -+ LOCK13 -+ LOCK13 -+ 13 -+ 1 -+ -+ -+ LOCK14 -+ LOCK14 -+ 14 -+ 1 -+ -+ -+ LOCK15 -+ LOCK15 -+ 15 -+ 1 -+ -+ -+ LOCK16 -+ LOCK16 -+ 16 -+ 1 -+ -+ -+ LOCK17 -+ LOCK17 -+ 17 -+ 1 -+ -+ -+ LOCK18 -+ LOCK18 -+ 18 -+ 1 -+ -+ -+ LOCK19 -+ LOCK19 -+ 19 -+ 1 -+ -+ -+ LOCK20 -+ LOCK20 -+ 20 -+ 1 -+ -+ -+ LOCK21 -+ LOCK21 -+ 21 -+ 1 -+ -+ -+ LOCK22 -+ LOCK22 -+ 22 -+ 1 -+ -+ -+ LOCK23 -+ LOCK23 -+ 23 -+ 1 -+ -+ -+ LOCK24 -+ LOCK24 -+ 24 -+ 1 -+ -+ -+ LOCK25 -+ LOCK25 -+ 25 -+ 1 -+ -+ -+ LOCK26 -+ LOCK26 -+ 26 -+ 1 -+ -+ -+ LOCK27 -+ LOCK27 -+ 27 -+ 1 -+ -+ -+ LOCK28 -+ LOCK28 -+ 28 -+ 1 -+ -+ -+ LOCK29 -+ LOCK29 -+ 29 -+ 1 -+ -+ -+ LOCK30 -+ LOCK30 -+ 30 -+ 1 -+ -+ -+ LOCK31 -+ LOCK31 -+ 31 -+ 1 -+ -+ -+ -+ -+ ETZPC_HWCFGR -+ ETZPC_HWCFGR -+ ETZPC IP HW configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00006002 -+ -+ -+ NUM_TZMA -+ NUM_TZMA -+ 0 -+ 8 -+ -+ -+ NUM_PER_SEC -+ NUM_PER_SEC -+ 8 -+ 8 -+ -+ -+ NUM_AHB_SEC -+ NUM_AHB_SEC -+ 16 -+ 8 -+ -+ -+ CHUNKS1N4 -+ CHUNKS1N4 -+ 24 -+ 8 -+ -+ -+ -+ -+ ETZPC_VERR -+ ETZPC_VERR -+ ETZPC IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ ETZPC_IDR -+ ETZPC_IDR -+ ETZPC IP version register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00100061 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ ETZPC_SIDR -+ ETZPC_SIDR -+ ETZPC IP version register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ IWDG1 -+ IWDG1 -+ IWDG1 -+ 0x5C003000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ IWDG_KR -+ IWDG_KR -+ Key register -+ 0x0 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ KEY -+ KEY -+ 0 -+ 16 -+ -+ -+ -+ -+ IWDG_PR -+ IWDG_PR -+ Prescaler register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000007 -+ -+ -+ PR -+ PR -+ 0 -+ 3 -+ -+ -+ -+ -+ IWDG_RLR -+ IWDG_RLR -+ Reload register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ RL -+ RL -+ 0 -+ 12 -+ -+ -+ -+ -+ IWDG_SR -+ IWDG_SR -+ Status register -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PVU -+ PVU -+ 0 -+ 1 -+ -+ -+ RVU -+ RVU -+ 1 -+ 1 -+ -+ -+ WVU -+ WVU -+ 2 -+ 1 -+ -+ -+ -+ -+ IWDG_WINR -+ IWDG_WINR -+ Window register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ WIN -+ WIN -+ 0 -+ 12 -+ -+ -+ -+ -+ IWDG_HWCFGR -+ IWDG_HWCFGR -+ IWDG hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000071 -+ -+ -+ WINDOW -+ WINDOW -+ 0 -+ 4 -+ -+ -+ PR_DEFAULT -+ PR_DEFAULT -+ 4 -+ 4 -+ -+ -+ -+ -+ IWDG_VERR -+ IWDG_VERR -+ IWDG version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000023 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ IWDG_IDR -+ IWDG_IDR -+ IWDG identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120041 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ IWDG_SIDR -+ IWDG_SIDR -+ IWDG size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ IWDG2 -+ 0x5A002000 -+ -+ -+ SPI1 -+ SPI1 -+ SPI1 -+ 0x44004000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ SPI2S_CR1 -+ SPI2S_CR1 -+ SPI/I2S control register 1 -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ SPE -+ SPE -+ 0 -+ 1 -+ read-write -+ -+ -+ MASRX -+ MASRX -+ 8 -+ 1 -+ read-write -+ -+ -+ CSTART -+ CSTART -+ 9 -+ 1 -+ read-write -+ -+ -+ CSUSP -+ CSUSP -+ 10 -+ 1 -+ write-only -+ -+ -+ HDDIR -+ HDDIR -+ 11 -+ 1 -+ read-write -+ -+ -+ SSI -+ SSI -+ 12 -+ 1 -+ read-write -+ -+ -+ CRC33_17 -+ CRC33_17 -+ 13 -+ 1 -+ read-write -+ -+ -+ RCRCINI -+ RCRCINI -+ 14 -+ 1 -+ read-write -+ -+ -+ TCRCINI -+ TCRCINI -+ 15 -+ 1 -+ read-write -+ -+ -+ IOLOCK -+ IOLOCK -+ 16 -+ 1 -+ read-write -+ -+ -+ -+ -+ SPI2S_IER -+ SPI2S_IER -+ SPI/I2S interrupt enable register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXPIE -+ RXPIE -+ 0 -+ 1 -+ -+ -+ TXPIE -+ TXPIE -+ 1 -+ 1 -+ -+ -+ DXPIE -+ DXPIE -+ 2 -+ 1 -+ -+ -+ EOTIE -+ EOTIE -+ 3 -+ 1 -+ -+ -+ TXTFIE -+ TXTFIE -+ 4 -+ 1 -+ -+ -+ UDRIE -+ UDRIE -+ 5 -+ 1 -+ -+ -+ OVRIE -+ OVRIE -+ 6 -+ 1 -+ -+ -+ CRCEIE -+ CRCEIE -+ 7 -+ 1 -+ -+ -+ TIFREIE -+ TIFREIE -+ 8 -+ 1 -+ -+ -+ MODFIE -+ MODFIE -+ 9 -+ 1 -+ -+ -+ TSERFIE -+ TSERFIE -+ 10 -+ 1 -+ -+ -+ -+ -+ SPI2S_SR -+ SPI2S_SR -+ SPI/I2S status register -+ 0x14 -+ 0x20 -+ read-only -+ 0x00001002 -+ -+ -+ RXP -+ RXP -+ 0 -+ 1 -+ -+ -+ TXP -+ TXP -+ 1 -+ 1 -+ -+ -+ DXP -+ DXP -+ 2 -+ 1 -+ -+ -+ EOT -+ EOT -+ 3 -+ 1 -+ -+ -+ TXTF -+ TXTF -+ 4 -+ 1 -+ -+ -+ UDR -+ UDR -+ 5 -+ 1 -+ -+ -+ OVR -+ OVR -+ 6 -+ 1 -+ -+ -+ CRCE -+ CRCE -+ 7 -+ 1 -+ -+ -+ TIFRE -+ TIFRE -+ 8 -+ 1 -+ -+ -+ MODF -+ MODF -+ 9 -+ 1 -+ -+ -+ TSERF -+ TSERF -+ 10 -+ 1 -+ -+ -+ SUSP -+ SUSP -+ 11 -+ 1 -+ -+ -+ TXC -+ TXC -+ 12 -+ 1 -+ -+ -+ RXPLVL -+ RXPLVL -+ 13 -+ 2 -+ -+ -+ RXWNE -+ RXWNE -+ 15 -+ 1 -+ -+ -+ CTSIZE -+ CTSIZE -+ 16 -+ 16 -+ -+ -+ -+ -+ SPI2S_IFCR -+ SPI2S_IFCR -+ SPI/I2S interrupt/status flags clear register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOTC -+ EOTC -+ 3 -+ 1 -+ -+ -+ TXTFC -+ TXTFC -+ 4 -+ 1 -+ -+ -+ UDRC -+ UDRC -+ 5 -+ 1 -+ -+ -+ OVRC -+ OVRC -+ 6 -+ 1 -+ -+ -+ CRCEC -+ CRCEC -+ 7 -+ 1 -+ -+ -+ TIFREC -+ TIFREC -+ 8 -+ 1 -+ -+ -+ MODFC -+ MODFC -+ 9 -+ 1 -+ -+ -+ TSERFC -+ TSERFC -+ 10 -+ 1 -+ -+ -+ SUSPC -+ SUSPC -+ 11 -+ 1 -+ -+ -+ -+ -+ SPI2S_TXDR -+ SPI2S_TXDR -+ SPI/I2S transmit data register -+ 0x20 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ TXDR -+ TXDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI2S_RXDR -+ SPI2S_RXDR -+ SPI/I2S receive data register -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXDR -+ RXDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_CR2 -+ SPI_CR2 -+ SPI control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSIZE -+ TSIZE -+ 0 -+ 16 -+ -+ -+ TSER -+ TSER -+ 16 -+ 16 -+ -+ -+ -+ -+ SPI_CFG1 -+ SPI_CFG1 -+ Content of this register is write protected when SPI is enabled -+ 0x8 -+ 0x20 -+ read-write -+ 0x00070007 -+ -+ -+ DSIZE -+ DSIZE -+ 0 -+ 5 -+ -+ -+ FTHLV -+ FTHLV -+ 5 -+ 4 -+ -+ -+ UDRCFG -+ UDRCFG -+ 9 -+ 2 -+ -+ -+ UDRDET -+ UDRDET -+ 11 -+ 2 -+ -+ -+ RXDMAEN -+ RXDMAEN -+ 14 -+ 1 -+ -+ -+ TXDMAEN -+ TXDMAEN -+ 15 -+ 1 -+ -+ -+ CRCSIZE -+ CRCSIZE -+ 16 -+ 5 -+ -+ -+ CRCEN -+ CRCEN -+ 22 -+ 1 -+ -+ -+ MBR -+ MBR -+ 28 -+ 3 -+ -+ -+ -+ -+ SPI_CFG2 -+ SPI_CFG2 -+ The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MSSI -+ MSSI -+ 0 -+ 4 -+ -+ -+ MIDI -+ MIDI -+ 4 -+ 4 -+ -+ -+ IOSWP -+ IOSWP -+ 15 -+ 1 -+ -+ -+ COMM -+ COMM -+ 17 -+ 2 -+ -+ -+ SP -+ SP -+ 19 -+ 3 -+ -+ -+ MASTER -+ MASTER -+ 22 -+ 1 -+ -+ -+ LSBFRST -+ LSBFRST -+ 23 -+ 1 -+ -+ -+ CPHA -+ CPHA -+ 24 -+ 1 -+ -+ -+ CPOL -+ CPOL -+ 25 -+ 1 -+ -+ -+ SSM -+ SSM -+ 26 -+ 1 -+ -+ -+ SSIOP -+ SSIOP -+ 28 -+ 1 -+ -+ -+ SSOE -+ SSOE -+ 29 -+ 1 -+ -+ -+ SSOM -+ SSOM -+ 30 -+ 1 -+ -+ -+ AFCNTR -+ AFCNTR -+ 31 -+ 1 -+ -+ -+ -+ -+ SPI_CRCPOLY -+ SPI_CRCPOLY -+ SPI polynomial register -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000107 -+ -+ -+ CRCPOLY -+ CRCPOLY -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_TXCRC -+ SPI_TXCRC -+ SPI transmitter CRC register -+ 0x44 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXCRC -+ TXCRC -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_RXCRC -+ SPI_RXCRC -+ SPI receiver CRC register -+ 0x48 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXCRC -+ RXCRC -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_UDRDR -+ SPI_UDRDR -+ SPI underrun data register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UDRDR -+ UDRDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_I2SCFGR -+ SPI_I2SCFGR -+ All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2SMOD -+ I2SMOD -+ 0 -+ 1 -+ -+ -+ I2SCFG -+ I2SCFG -+ 1 -+ 3 -+ -+ -+ I2SSTD -+ I2SSTD -+ 4 -+ 2 -+ -+ -+ PCMSYNC -+ PCMSYNC -+ 7 -+ 1 -+ -+ -+ DATLEN -+ DATLEN -+ 8 -+ 2 -+ -+ -+ CHLEN -+ CHLEN -+ 10 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 11 -+ 1 -+ -+ -+ FIXCH -+ FIXCH -+ 12 -+ 1 -+ -+ -+ WSINV -+ WSINV -+ 13 -+ 1 -+ -+ -+ DATFMT -+ DATFMT -+ 14 -+ 1 -+ -+ -+ I2SDIV -+ I2SDIV -+ 16 -+ 8 -+ -+ -+ ODD -+ ODD -+ 24 -+ 1 -+ -+ -+ MCKOE -+ MCKOE -+ 25 -+ 1 -+ -+ -+ -+ -+ SPI_I2S_HWCFGR -+ SPI_I2S_HWCFGR -+ SPI/I2S hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXFCFG -+ TXFCFG -+ 0 -+ 4 -+ -+ -+ RXFCFG -+ RXFCFG -+ 4 -+ 4 -+ -+ -+ CRCCFG -+ CRCCFG -+ 8 -+ 4 -+ -+ -+ I2SCFG -+ I2SCFG -+ 12 -+ 4 -+ -+ -+ DSCFG -+ DSCFG -+ 16 -+ 4 -+ -+ -+ -+ -+ SPI_VERR -+ SPI_VERR -+ SPI/I2S version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ SPI_IPIDR -+ SPI_IPIDR -+ SPI/I2S identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130022 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_SIDR -+ SPI_SIDR -+ SPI/I2S size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ -+ SPI2 -+ SPI2 -+ SPI2 -+ 0x4000B000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ SPI2S_CR1 -+ SPI2S_CR1 -+ SPI/I2S control register 1 -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ SPE -+ SPE -+ 0 -+ 1 -+ read-write -+ -+ -+ MASRX -+ MASRX -+ 8 -+ 1 -+ read-write -+ -+ -+ CSTART -+ CSTART -+ 9 -+ 1 -+ read-write -+ -+ -+ CSUSP -+ CSUSP -+ 10 -+ 1 -+ write-only -+ -+ -+ HDDIR -+ HDDIR -+ 11 -+ 1 -+ read-write -+ -+ -+ SSI -+ SSI -+ 12 -+ 1 -+ read-write -+ -+ -+ CRC33_17 -+ CRC33_17 -+ 13 -+ 1 -+ read-write -+ -+ -+ RCRCINI -+ RCRCINI -+ 14 -+ 1 -+ read-write -+ -+ -+ TCRCINI -+ TCRCINI -+ 15 -+ 1 -+ read-write -+ -+ -+ IOLOCK -+ IOLOCK -+ 16 -+ 1 -+ read-write -+ -+ -+ -+ -+ SPI2S_IER -+ SPI2S_IER -+ SPI/I2S interrupt enable register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXPIE -+ RXPIE -+ 0 -+ 1 -+ -+ -+ TXPIE -+ TXPIE -+ 1 -+ 1 -+ -+ -+ DXPIE -+ DXPIE -+ 2 -+ 1 -+ -+ -+ EOTIE -+ EOTIE -+ 3 -+ 1 -+ -+ -+ TXTFIE -+ TXTFIE -+ 4 -+ 1 -+ -+ -+ UDRIE -+ UDRIE -+ 5 -+ 1 -+ -+ -+ OVRIE -+ OVRIE -+ 6 -+ 1 -+ -+ -+ CRCEIE -+ CRCEIE -+ 7 -+ 1 -+ -+ -+ TIFREIE -+ TIFREIE -+ 8 -+ 1 -+ -+ -+ MODFIE -+ MODFIE -+ 9 -+ 1 -+ -+ -+ TSERFIE -+ TSERFIE -+ 10 -+ 1 -+ -+ -+ -+ -+ SPI2S_SR -+ SPI2S_SR -+ SPI/I2S status register -+ 0x14 -+ 0x20 -+ read-only -+ 0x00001002 -+ -+ -+ RXP -+ RXP -+ 0 -+ 1 -+ -+ -+ TXP -+ TXP -+ 1 -+ 1 -+ -+ -+ DXP -+ DXP -+ 2 -+ 1 -+ -+ -+ EOT -+ EOT -+ 3 -+ 1 -+ -+ -+ TXTF -+ TXTF -+ 4 -+ 1 -+ -+ -+ UDR -+ UDR -+ 5 -+ 1 -+ -+ -+ OVR -+ OVR -+ 6 -+ 1 -+ -+ -+ CRCE -+ CRCE -+ 7 -+ 1 -+ -+ -+ TIFRE -+ TIFRE -+ 8 -+ 1 -+ -+ -+ MODF -+ MODF -+ 9 -+ 1 -+ -+ -+ TSERF -+ TSERF -+ 10 -+ 1 -+ -+ -+ SUSP -+ SUSP -+ 11 -+ 1 -+ -+ -+ TXC -+ TXC -+ 12 -+ 1 -+ -+ -+ RXPLVL -+ RXPLVL -+ 13 -+ 2 -+ -+ -+ RXWNE -+ RXWNE -+ 15 -+ 1 -+ -+ -+ CTSIZE -+ CTSIZE -+ 16 -+ 16 -+ -+ -+ -+ -+ SPI2S_IFCR -+ SPI2S_IFCR -+ SPI/I2S interrupt/status flags clear register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ EOTC -+ EOTC -+ 3 -+ 1 -+ -+ -+ TXTFC -+ TXTFC -+ 4 -+ 1 -+ -+ -+ UDRC -+ UDRC -+ 5 -+ 1 -+ -+ -+ OVRC -+ OVRC -+ 6 -+ 1 -+ -+ -+ CRCEC -+ CRCEC -+ 7 -+ 1 -+ -+ -+ TIFREC -+ TIFREC -+ 8 -+ 1 -+ -+ -+ MODFC -+ MODFC -+ 9 -+ 1 -+ -+ -+ TSERFC -+ TSERFC -+ 10 -+ 1 -+ -+ -+ SUSPC -+ SUSPC -+ 11 -+ 1 -+ -+ -+ -+ -+ SPI2S_TXDR -+ SPI2S_TXDR -+ SPI/I2S transmit data register -+ 0x20 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ TXDR -+ TXDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI2S_RXDR -+ SPI2S_RXDR -+ SPI/I2S receive data register -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXDR -+ RXDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_CR2 -+ SPI_CR2 -+ SPI control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSIZE -+ TSIZE -+ 0 -+ 16 -+ -+ -+ TSER -+ TSER -+ 16 -+ 16 -+ -+ -+ -+ -+ SPI_CFG1 -+ SPI_CFG1 -+ Content of this register is write protected when SPI is enabled -+ 0x8 -+ 0x20 -+ read-write -+ 0x00070007 -+ -+ -+ DSIZE -+ DSIZE -+ 0 -+ 5 -+ -+ -+ FTHLV -+ FTHLV -+ 5 -+ 4 -+ -+ -+ UDRCFG -+ UDRCFG -+ 9 -+ 2 -+ -+ -+ UDRDET -+ UDRDET -+ 11 -+ 2 -+ -+ -+ RXDMAEN -+ RXDMAEN -+ 14 -+ 1 -+ -+ -+ TXDMAEN -+ TXDMAEN -+ 15 -+ 1 -+ -+ -+ CRCSIZE -+ CRCSIZE -+ 16 -+ 5 -+ -+ -+ CRCEN -+ CRCEN -+ 22 -+ 1 -+ -+ -+ MBR -+ MBR -+ 28 -+ 3 -+ -+ -+ -+ -+ SPI_CFG2 -+ SPI_CFG2 -+ The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MSSI -+ MSSI -+ 0 -+ 4 -+ -+ -+ MIDI -+ MIDI -+ 4 -+ 4 -+ -+ -+ IOSWP -+ IOSWP -+ 15 -+ 1 -+ -+ -+ COMM -+ COMM -+ 17 -+ 2 -+ -+ -+ SP -+ SP -+ 19 -+ 3 -+ -+ -+ MASTER -+ MASTER -+ 22 -+ 1 -+ -+ -+ LSBFRST -+ LSBFRST -+ 23 -+ 1 -+ -+ -+ CPHA -+ CPHA -+ 24 -+ 1 -+ -+ -+ CPOL -+ CPOL -+ 25 -+ 1 -+ -+ -+ SSM -+ SSM -+ 26 -+ 1 -+ -+ -+ SSIOP -+ SSIOP -+ 28 -+ 1 -+ -+ -+ SSOE -+ SSOE -+ 29 -+ 1 -+ -+ -+ SSOM -+ SSOM -+ 30 -+ 1 -+ -+ -+ AFCNTR -+ AFCNTR -+ 31 -+ 1 -+ -+ -+ -+ -+ SPI_CRCPOLY -+ SPI_CRCPOLY -+ SPI polynomial register -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000107 -+ -+ -+ CRCPOLY -+ CRCPOLY -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_TXCRC -+ SPI_TXCRC -+ SPI transmitter CRC register -+ 0x44 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXCRC -+ TXCRC -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_RXCRC -+ SPI_RXCRC -+ SPI receiver CRC register -+ 0x48 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXCRC -+ RXCRC -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_UDRDR -+ SPI_UDRDR -+ SPI underrun data register -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UDRDR -+ UDRDR -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_I2SCFGR -+ SPI_I2SCFGR -+ All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2SMOD -+ I2SMOD -+ 0 -+ 1 -+ -+ -+ I2SCFG -+ I2SCFG -+ 1 -+ 3 -+ -+ -+ I2SSTD -+ I2SSTD -+ 4 -+ 2 -+ -+ -+ PCMSYNC -+ PCMSYNC -+ 7 -+ 1 -+ -+ -+ DATLEN -+ DATLEN -+ 8 -+ 2 -+ -+ -+ CHLEN -+ CHLEN -+ 10 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 11 -+ 1 -+ -+ -+ FIXCH -+ FIXCH -+ 12 -+ 1 -+ -+ -+ WSINV -+ WSINV -+ 13 -+ 1 -+ -+ -+ DATFMT -+ DATFMT -+ 14 -+ 1 -+ -+ -+ I2SDIV -+ I2SDIV -+ 16 -+ 8 -+ -+ -+ ODD -+ ODD -+ 24 -+ 1 -+ -+ -+ MCKOE -+ MCKOE -+ 25 -+ 1 -+ -+ -+ -+ -+ SPI_I2S_HWCFGR -+ SPI_I2S_HWCFGR -+ SPI/I2S hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TXFCFG -+ TXFCFG -+ 0 -+ 4 -+ -+ -+ RXFCFG -+ RXFCFG -+ 4 -+ 4 -+ -+ -+ CRCCFG -+ CRCCFG -+ 8 -+ 4 -+ -+ -+ I2SCFG -+ I2SCFG -+ 12 -+ 4 -+ -+ -+ DSCFG -+ DSCFG -+ 16 -+ 4 -+ -+ -+ -+ -+ SPI_VERR -+ SPI_VERR -+ SPI/I2S version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ SPI_IPIDR -+ SPI_IPIDR -+ SPI/I2S identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130022 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ SPI_SIDR -+ SPI_SIDR -+ SPI/I2S size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ -+ SPI3 -+ 0x4000C000 -+ -+ -+ SPI4 -+ 0x44005000 -+ -+ -+ SPI5 -+ 0x44009000 -+ -+ -+ SPI6 -+ 0x5C001000 -+ -+ -+ USART1 -+ Universal synchronous asynchronous receiver transmitter -+ USART -+ 0x5C000000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ CR1 -+ CR1 -+ Control register 1 -+ 0x0 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ RXFFIE -+ RXFIFO Full interrupt enable -+ 31 -+ 1 -+ -+ -+ TXFEIE -+ TXFIFO empty interrupt enable -+ 30 -+ 1 -+ -+ -+ FIFOEN -+ FIFO mode enable -+ 29 -+ 1 -+ -+ -+ M1 -+ Word length -+ 28 -+ 1 -+ -+ -+ EOBIE -+ End of Block interrupt enable -+ 27 -+ 1 -+ -+ -+ RTOIE -+ Receiver timeout interrupt enable -+ 26 -+ 1 -+ -+ -+ DEAT -+ DEAT -+ 21 -+ 5 -+ -+ -+ DEDT -+ DEDT -+ 16 -+ 5 -+ -+ -+ OVER8 -+ Oversampling mode -+ 15 -+ 1 -+ -+ -+ CMIE -+ Character match interrupt enable -+ 14 -+ 1 -+ -+ -+ MME -+ Mute mode enable -+ 13 -+ 1 -+ -+ -+ M0 -+ Word length -+ 12 -+ 1 -+ -+ -+ WAKE -+ Receiver wakeup method -+ 11 -+ 1 -+ -+ -+ PCE -+ Parity control enable -+ 10 -+ 1 -+ -+ -+ PS -+ Parity selection -+ 9 -+ 1 -+ -+ -+ PEIE -+ PE interrupt enable -+ 8 -+ 1 -+ -+ -+ TXEIE -+ interrupt enable -+ 7 -+ 1 -+ -+ -+ TCIE -+ Transmission complete interrupt enable -+ 6 -+ 1 -+ -+ -+ RXNEIE -+ RXNE interrupt enable -+ 5 -+ 1 -+ -+ -+ IDLEIE -+ IDLE interrupt enable -+ 4 -+ 1 -+ -+ -+ TE -+ Transmitter enable -+ 3 -+ 1 -+ -+ -+ RE -+ Receiver enable -+ 2 -+ 1 -+ -+ -+ UESM -+ USART enable in Stop mode -+ 1 -+ 1 -+ -+ -+ UE -+ USART enable -+ 0 -+ 1 -+ -+ -+ -+ -+ CR2 -+ CR2 -+ Control register 2 -+ 0x4 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ ADD4_7 -+ Address of the USART node -+ 28 -+ 4 -+ -+ -+ ADD0_3 -+ Address of the USART node -+ 24 -+ 4 -+ -+ -+ RTOEN -+ Receiver timeout enable -+ 23 -+ 1 -+ -+ -+ ABRMOD -+ Auto baud rate mode -+ 21 -+ 2 -+ -+ -+ ABREN -+ Auto baud rate enable -+ 20 -+ 1 -+ -+ -+ MSBFIRST -+ Most significant bit first -+ 19 -+ 1 -+ -+ -+ TAINV -+ Binary data inversion -+ 18 -+ 1 -+ -+ -+ TXINV -+ TX pin active level inversion -+ 17 -+ 1 -+ -+ -+ RXINV -+ RX pin active level inversion -+ 16 -+ 1 -+ -+ -+ SWAP -+ Swap TX/RX pins -+ 15 -+ 1 -+ -+ -+ LINEN -+ LIN mode enable -+ 14 -+ 1 -+ -+ -+ STOP -+ STOP bits -+ 12 -+ 2 -+ -+ -+ CLKEN -+ Clock enable -+ 11 -+ 1 -+ -+ -+ CPOL -+ Clock polarity -+ 10 -+ 1 -+ -+ -+ CPHA -+ Clock phase -+ 9 -+ 1 -+ -+ -+ LBCL -+ Last bit clock pulse -+ 8 -+ 1 -+ -+ -+ LBDIE -+ LIN break detection interrupt enable -+ 6 -+ 1 -+ -+ -+ LBDL -+ LIN break detection length -+ 5 -+ 1 -+ -+ -+ ADDM7 -+ 7-bit Address Detection/4-bit Address Detection -+ 4 -+ 1 -+ -+ -+ DIS_NSS -+ When the DSI_NSS bit is set, the NSS pin input will be ignored -+ 3 -+ 1 -+ -+ -+ SLVEN -+ Synchronous Slave mode enable -+ 0 -+ 1 -+ -+ -+ -+ -+ CR3 -+ CR3 -+ Control register 3 -+ 0x8 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ TXFTCFG -+ TXFIFO threshold configuration -+ 29 -+ 3 -+ -+ -+ RXFTIE -+ RXFIFO threshold interrupt enable -+ 28 -+ 1 -+ -+ -+ RXFTCFG -+ Receive FIFO threshold configuration -+ 25 -+ 3 -+ -+ -+ TCBGTIE -+ Tr Complete before guard time, interrupt enable -+ 24 -+ 1 -+ -+ -+ TXFTIE -+ threshold interrupt enable -+ 23 -+ 1 -+ -+ -+ WUFIE -+ Wakeup from Stop mode interrupt enable -+ 22 -+ 1 -+ -+ -+ WUS -+ Wakeup from Stop mode interrupt flag selection -+ 20 -+ 2 -+ -+ -+ SCARCNT -+ Smartcard auto-retry count -+ 17 -+ 3 -+ -+ -+ DEP -+ Driver enable polarity selection -+ 15 -+ 1 -+ -+ -+ DEM -+ Driver enable mode -+ 14 -+ 1 -+ -+ -+ DDRE -+ DMA Disable on Reception Error -+ 13 -+ 1 -+ -+ -+ OVRDIS -+ Overrun Disable -+ 12 -+ 1 -+ -+ -+ ONEBIT -+ One sample bit method enable -+ 11 -+ 1 -+ -+ -+ CTSIE -+ CTS interrupt enable -+ 10 -+ 1 -+ -+ -+ CTSE -+ CTS enable -+ 9 -+ 1 -+ -+ -+ RTSE -+ RTS enable -+ 8 -+ 1 -+ -+ -+ DMAT -+ DMA enable transmitter -+ 7 -+ 1 -+ -+ -+ DMAR -+ DMA enable receiver -+ 6 -+ 1 -+ -+ -+ SCEN -+ Smartcard mode enable -+ 5 -+ 1 -+ -+ -+ NACK -+ Smartcard NACK enable -+ 4 -+ 1 -+ -+ -+ HDSEL -+ Half-duplex selection -+ 3 -+ 1 -+ -+ -+ IRLP -+ Ir low-power -+ 2 -+ 1 -+ -+ -+ IREN -+ Ir mode enable -+ 1 -+ 1 -+ -+ -+ EIE -+ Error interrupt enable -+ 0 -+ 1 -+ -+ -+ -+ -+ BRR -+ BRR -+ Baud rate register -+ 0xC -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ BRR_4_15 -+ BRR_4_15 -+ 4 -+ 12 -+ -+ -+ BRR_0_3 -+ BRR_0_3 -+ 0 -+ 4 -+ -+ -+ -+ -+ GTPR -+ GTPR -+ Guard time and prescaler register -+ 0x10 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ GT -+ Guard time value -+ 8 -+ 8 -+ -+ -+ PSC -+ Prescaler value -+ 0 -+ 8 -+ -+ -+ -+ -+ RTOR -+ RTOR -+ Receiver timeout register -+ 0x14 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ BLEN -+ Block Length -+ 24 -+ 8 -+ -+ -+ RTO -+ Receiver timeout value -+ 0 -+ 24 -+ -+ -+ -+ -+ RQR -+ RQR -+ Request register -+ 0x18 -+ 0x20 -+ write-only -+ 0x0000 -+ -+ -+ TXFRQ -+ Transmit data flush request -+ 4 -+ 1 -+ -+ -+ RXFRQ -+ Receive data flush request -+ 3 -+ 1 -+ -+ -+ MMRQ -+ Mute mode request -+ 2 -+ 1 -+ -+ -+ SBKRQ -+ Send break request -+ 1 -+ 1 -+ -+ -+ ABRRQ -+ Auto baud rate request -+ 0 -+ 1 -+ -+ -+ -+ -+ ISR -+ ISR -+ Interrupt & status register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00C0 -+ -+ -+ TXFT -+ TXFIFO threshold flag -+ 27 -+ 1 -+ -+ -+ RXFT -+ RXFIFO threshold flag -+ 26 -+ 1 -+ -+ -+ TCBGT -+ Transmission complete before guard time flag -+ 25 -+ 1 -+ -+ -+ RXFF -+ RXFIFO Full -+ 24 -+ 1 -+ -+ -+ TXFE -+ TXFIFO Empty -+ 23 -+ 1 -+ -+ -+ REACK -+ REACK -+ 22 -+ 1 -+ -+ -+ TEACK -+ TEACK -+ 21 -+ 1 -+ -+ -+ WUF -+ WUF -+ 20 -+ 1 -+ -+ -+ RWU -+ RWU -+ 19 -+ 1 -+ -+ -+ SBKF -+ SBKF -+ 18 -+ 1 -+ -+ -+ CMF -+ CMF -+ 17 -+ 1 -+ -+ -+ BUSY -+ BUSY -+ 16 -+ 1 -+ -+ -+ ABRF -+ ABRF -+ 15 -+ 1 -+ -+ -+ ABRE -+ ABRE -+ 14 -+ 1 -+ -+ -+ UDR -+ SPI slave underrun error flag -+ 13 -+ 1 -+ -+ -+ EOBF -+ EOBF -+ 12 -+ 1 -+ -+ -+ RTOF -+ RTOF -+ 11 -+ 1 -+ -+ -+ CTS -+ CTS -+ 10 -+ 1 -+ -+ -+ CTSIF -+ CTSIF -+ 9 -+ 1 -+ -+ -+ LBDF -+ LBDF -+ 8 -+ 1 -+ -+ -+ TXE -+ TXE -+ 7 -+ 1 -+ -+ -+ TC -+ TC -+ 6 -+ 1 -+ -+ -+ RXNE -+ RXNE -+ 5 -+ 1 -+ -+ -+ IDLE -+ IDLE -+ 4 -+ 1 -+ -+ -+ ORE -+ ORE -+ 3 -+ 1 -+ -+ -+ NF -+ NF -+ 2 -+ 1 -+ -+ -+ FE -+ FE -+ 1 -+ 1 -+ -+ -+ PE -+ PE -+ 0 -+ 1 -+ -+ -+ -+ -+ ICR -+ ICR -+ Interrupt flag clear register -+ 0x20 -+ 0x20 -+ write-only -+ 0x0000 -+ -+ -+ WUCF -+ Wakeup from Stop mode clear flag -+ 20 -+ 1 -+ -+ -+ CMCF -+ Character match clear flag -+ 17 -+ 1 -+ -+ -+ UDRCF -+ SPI slave underrun clear flag -+ 13 -+ 1 -+ -+ -+ EOBCF -+ End of block clear flag -+ 12 -+ 1 -+ -+ -+ RTOCF -+ Receiver timeout clear flag -+ 11 -+ 1 -+ -+ -+ CTSCF -+ CTS clear flag -+ 9 -+ 1 -+ -+ -+ LBDCF -+ LIN break detection clear flag -+ 8 -+ 1 -+ -+ -+ TCBGTCF -+ Transmission complete before Guard time clear flag -+ 7 -+ 1 -+ -+ -+ TCCF -+ Transmission complete clear flag -+ 6 -+ 1 -+ -+ -+ TXFECF -+ TXFIFO empty clear flag -+ 5 -+ 1 -+ -+ -+ IDLECF -+ Idle line detected clear flag -+ 4 -+ 1 -+ -+ -+ ORECF -+ Overrun error clear flag -+ 3 -+ 1 -+ -+ -+ NCF -+ Noise detected clear flag -+ 2 -+ 1 -+ -+ -+ FECF -+ Framing error clear flag -+ 1 -+ 1 -+ -+ -+ PECF -+ Parity error clear flag -+ 0 -+ 1 -+ -+ -+ -+ -+ RDR -+ RDR -+ Receive data register -+ 0x24 -+ 0x20 -+ read-only -+ 0x0000 -+ -+ -+ RDR -+ Receive data value -+ 0 -+ 9 -+ -+ -+ -+ -+ TDR -+ TDR -+ Transmit data register -+ 0x28 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ TDR -+ Transmit data value -+ 0 -+ 9 -+ -+ -+ -+ -+ PRESC -+ PRESC -+ Prescaler register -+ 0x2C -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ PRESCALER -+ Clock prescaler -+ 0 -+ 4 -+ -+ -+ -+ -+ HWCFGR2 -+ HWCFGR2 -+ USART Hardware Configuration register 2 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 4 -+ -+ -+ CFG2 -+ CFG2 -+ 4 -+ 4 -+ -+ -+ -+ -+ HWCFGR1 -+ HWCFGR1 -+ USART Hardware Configuration register 1 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 4 -+ -+ -+ CFG2 -+ CFG2 -+ 4 -+ 4 -+ -+ -+ CFG3 -+ CFG3 -+ 8 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 12 -+ 4 -+ -+ -+ CFG5 -+ CFG5 -+ 16 -+ 4 -+ -+ -+ CFG6 -+ CFG6 -+ 20 -+ 4 -+ -+ -+ CFG7 -+ CFG7 -+ 24 -+ 4 -+ -+ -+ CFG8 -+ CFG8 -+ 28 -+ 4 -+ -+ -+ -+ -+ VERR -+ VERR -+ EXTI IP Version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000023 -+ -+ -+ MINREV -+ Minor Revision number -+ 0 -+ 4 -+ -+ -+ MAJREV -+ Major Revision number -+ 4 -+ 4 -+ -+ -+ -+ -+ IPIDR -+ IPIDR -+ EXTI Identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130003 -+ -+ -+ IPID -+ IP Identification -+ 0 -+ 32 -+ -+ -+ -+ -+ SIDR -+ SIDR -+ EXTI Size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ Size Identification -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ USART2 -+ 0x4000E000 -+ -+ -+ USART3 -+ 0x4000F000 -+ -+ -+ UART4 -+ 0x40010000 -+ -+ -+ UART5 -+ 0x40011000 -+ -+ -+ USART6 -+ 0x44003000 -+ -+ -+ UART7 -+ 0x40018000 -+ -+ -+ UART8 -+ 0x40019000 -+ -+ -+ LTDC -+ LTDC -+ LTDC -+ 0x5A001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LTDC_IDR -+ LTDC_IDR -+ LTDC identification register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00010300 -+ -+ -+ REV -+ REV -+ 0 -+ 8 -+ -+ -+ MINVER -+ MINVER -+ 8 -+ 8 -+ -+ -+ MAJVER -+ MAJVER -+ 16 -+ 8 -+ -+ -+ -+ -+ LTDC_LCR -+ LTDC_LCR -+ LDTC layer count register -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000002 -+ -+ -+ LNBR -+ LNBR -+ 0 -+ 8 -+ -+ -+ -+ -+ LTDC_SSCR -+ LTDC_SSCR -+ This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ VSH -+ VSH -+ 0 -+ 12 -+ -+ -+ HSW -+ HSW -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_BPCR -+ LTDC_BPCR -+ This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AVBP -+ AVBP -+ 0 -+ 12 -+ -+ -+ AHBP -+ AHBP -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_AWCR -+ LTDC_AWCR -+ This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AAH -+ AAH -+ 0 -+ 12 -+ -+ -+ AAW -+ AAW -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_TWCR -+ LTDC_TWCR -+ This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TOTALH -+ TOTALH -+ 0 -+ 12 -+ -+ -+ TOTALW -+ TOTALW -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_GCR -+ LTDC_GCR -+ This register defines the global configuration of the LCD-TFT controller. -+ 0x18 -+ 0x20 -+ 0x00002220 -+ -+ -+ LTDCEN -+ LTDCEN -+ 0 -+ 1 -+ read-write -+ -+ -+ DBW -+ DBW -+ 4 -+ 3 -+ read-only -+ -+ -+ DGW -+ DGW -+ 8 -+ 3 -+ read-only -+ -+ -+ DRW -+ DRW -+ 12 -+ 3 -+ read-only -+ -+ -+ DEN -+ DEN -+ 16 -+ 1 -+ read-write -+ -+ -+ PCPOL -+ PCPOL -+ 28 -+ 1 -+ read-write -+ -+ -+ DEPOL -+ DEPOL -+ 29 -+ 1 -+ read-write -+ -+ -+ VSPOL -+ VSPOL -+ 30 -+ 1 -+ read-write -+ -+ -+ HSPOL -+ HSPOL -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ LTDC_GC1R -+ LTDC_GC1R -+ LTDC global configuration 1 register -+ 0x1C -+ 0x20 -+ read-only -+ 0x6BE2D888 -+ -+ -+ WBCH -+ WBCH -+ 0 -+ 4 -+ -+ -+ WGCH -+ WGCH -+ 4 -+ 4 -+ -+ -+ WRCH -+ WRCH -+ 8 -+ 4 -+ -+ -+ PRBEN -+ PRBEN -+ 12 -+ 1 -+ -+ -+ DT -+ DT -+ 14 -+ 2 -+ -+ -+ GCT -+ GCT -+ 17 -+ 3 -+ -+ -+ SHREN -+ SHREN -+ 21 -+ 1 -+ -+ -+ BCP -+ BCP -+ 22 -+ 1 -+ -+ -+ BBEN -+ BBEN -+ 23 -+ 1 -+ -+ -+ LNIP -+ LNIP -+ 24 -+ 1 -+ -+ -+ TP -+ TP -+ 25 -+ 1 -+ -+ -+ IPP -+ IPP -+ 26 -+ 1 -+ -+ -+ SPP -+ SPP -+ 27 -+ 1 -+ -+ -+ DWP -+ DWP -+ 28 -+ 1 -+ -+ -+ STREN -+ STREN -+ 29 -+ 1 -+ -+ -+ BMEN -+ BMEN -+ 31 -+ 1 -+ -+ -+ -+ -+ LTDC_GC2R -+ LTDC_GC2R -+ LTDC global configuration 2 register -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000030 -+ -+ -+ EDCEN -+ EDCEN -+ 0 -+ 1 -+ -+ -+ STSAEN -+ STSAEN -+ 1 -+ 1 -+ -+ -+ DVAEN -+ DVAEN -+ 2 -+ 1 -+ -+ -+ DPAEN -+ DPAEN -+ 3 -+ 1 -+ -+ -+ BW -+ BW -+ 4 -+ 3 -+ -+ -+ EDCA -+ EDCA -+ 7 -+ 1 -+ -+ -+ -+ -+ LTDC_SRCR -+ LTDC_SRCR -+ This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IMR -+ IMR -+ 0 -+ 1 -+ -+ -+ VBR -+ VBR -+ 1 -+ 1 -+ -+ -+ -+ -+ LTDC_BCCR -+ LTDC_BCCR -+ This register defines the background color (RGB888). -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BCBLUE -+ BCBLUE -+ 0 -+ 8 -+ -+ -+ BCGREEN -+ BCGREEN -+ 8 -+ 8 -+ -+ -+ BCRED -+ BCRED -+ 16 -+ 8 -+ -+ -+ -+ -+ LTDC_IER -+ LTDC_IER -+ This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LIE -+ LIE -+ 0 -+ 1 -+ -+ -+ FUIE -+ FUIE -+ 1 -+ 1 -+ -+ -+ TERRIE -+ TERRIE -+ 2 -+ 1 -+ -+ -+ RRIE -+ RRIE -+ 3 -+ 1 -+ -+ -+ -+ -+ LTDC_ISR -+ LTDC_ISR -+ This register returns the interrupt status flag. -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ LIF -+ LIF -+ 0 -+ 1 -+ -+ -+ FUIF -+ FUIF -+ 1 -+ 1 -+ -+ -+ TERRIF -+ TERRIF -+ 2 -+ 1 -+ -+ -+ RRIF -+ RRIF -+ 3 -+ 1 -+ -+ -+ -+ -+ LTDC_ICR -+ LTDC_ICR -+ LTDC Interrupt Clear Register -+ 0x3C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CLIF -+ CLIF -+ 0 -+ 1 -+ -+ -+ CFUIF -+ CFUIF -+ 1 -+ 1 -+ -+ -+ CTERRIF -+ CTERRIF -+ 2 -+ 1 -+ -+ -+ CRRIF -+ CRRIF -+ 3 -+ 1 -+ -+ -+ -+ -+ LTDC_LIPCR -+ LTDC_LIPCR -+ This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LIPOS -+ LIPOS -+ 0 -+ 12 -+ -+ -+ -+ -+ LTDC_CPSR -+ LTDC_CPSR -+ LTDC current position status register -+ 0x44 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CYPOS -+ CYPOS -+ 0 -+ 16 -+ -+ -+ CXPOS -+ CXPOS -+ 16 -+ 16 -+ -+ -+ -+ -+ LTDC_CDSR -+ LTDC_CDSR -+ This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. -+ 0x48 -+ 0x20 -+ read-only -+ 0x0000000F -+ -+ -+ VDES -+ VDES -+ 0 -+ 1 -+ -+ -+ HDES -+ HDES -+ 1 -+ 1 -+ -+ -+ VSYNCS -+ VSYNCS -+ 2 -+ 1 -+ -+ -+ HSYNCS -+ HSYNCS -+ 3 -+ 1 -+ -+ -+ -+ -+ LTDC_L1CR -+ LTDC_L1CR -+ LTDC layer 1 control register -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LEN -+ LEN -+ 0 -+ 1 -+ -+ -+ COLKEN -+ COLKEN -+ 1 -+ 1 -+ -+ -+ CLUTEN -+ CLUTEN -+ 4 -+ 1 -+ -+ -+ -+ -+ LTDC_L1WHPCR -+ LTDC_L1WHPCR -+ This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WHSTPOS -+ WHSTPOS -+ 0 -+ 12 -+ -+ -+ WHSPPOS -+ WHSPPOS -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_L1WVPCR -+ LTDC_L1WVPCR -+ This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WVSTPOS -+ WVSTPOS -+ 0 -+ 12 -+ -+ -+ WVSPPOS -+ WVSPPOS -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_L1CKCR -+ LTDC_L1CKCR -+ This register defines the color key value (RGB), that is used by the color keying. -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKBLUE -+ CKBLUE -+ 0 -+ 8 -+ -+ -+ CKGREEN -+ CKGREEN -+ 8 -+ 8 -+ -+ -+ CKRED -+ CKRED -+ 16 -+ 8 -+ -+ -+ -+ -+ LTDC_L1PFCR -+ LTDC_L1PFCR -+ This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PF -+ PF -+ 0 -+ 3 -+ -+ -+ -+ -+ LTDC_L1CACR -+ LTDC_L1CACR -+ This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. -+ 0x98 -+ 0x20 -+ read-write -+ 0x000000FF -+ -+ -+ CONSTA -+ CONSTA -+ 0 -+ 8 -+ -+ -+ -+ -+ LTDC_L1DCCR -+ LTDC_L1DCCR -+ This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCBLUE -+ DCBLUE -+ 0 -+ 8 -+ -+ -+ DCGREEN -+ DCGREEN -+ 8 -+ 8 -+ -+ -+ DCRED -+ DCRED -+ 16 -+ 8 -+ -+ -+ DCALPHA -+ DCALPHA -+ 24 -+ 8 -+ -+ -+ -+ -+ LTDC_L1BFCR -+ LTDC_L1BFCR -+ This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000607 -+ -+ -+ BF2 -+ BF2 -+ 0 -+ 3 -+ -+ -+ BF1 -+ BF1 -+ 8 -+ 3 -+ -+ -+ -+ -+ LTDC_L1CFBAR -+ LTDC_L1CFBAR -+ This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. -+ 0xAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBADD -+ CFBADD -+ 0 -+ 32 -+ -+ -+ -+ -+ LTDC_L1CFBLR -+ LTDC_L1CFBLR -+ This register defines the color frame buffer line length and pitch. -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBLL -+ CFBLL -+ 0 -+ 14 -+ -+ -+ CFBP -+ CFBP -+ 16 -+ 14 -+ -+ -+ -+ -+ LTDC_L1CFBLNR -+ LTDC_L1CFBLNR -+ This register defines the number of lines in the color frame buffer. -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBLNBR -+ CFBLNBR -+ 0 -+ 12 -+ -+ -+ -+ -+ LTDC_L1CLUTWR -+ LTDC_L1CLUTWR -+ This register defines the CLUT address and the RGB value. -+ 0xC4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BLUE -+ BLUE -+ 0 -+ 8 -+ -+ -+ GREEN -+ GREEN -+ 8 -+ 8 -+ -+ -+ RED -+ RED -+ 16 -+ 8 -+ -+ -+ CLUTADD -+ CLUTADD -+ 24 -+ 8 -+ -+ -+ -+ -+ LTDC_L2CR -+ LTDC_L2CR -+ LTDC layer 2 control register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LEN -+ LEN -+ 0 -+ 1 -+ -+ -+ COLKEN -+ COLKEN -+ 1 -+ 1 -+ -+ -+ CLUTEN -+ CLUTEN -+ 4 -+ 1 -+ -+ -+ -+ -+ LTDC_L2WHPCR -+ LTDC_L2WHPCR -+ This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WHSTPOS -+ WHSTPOS -+ 0 -+ 12 -+ -+ -+ WHSPPOS -+ WHSPPOS -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_L2WVPCR -+ LTDC_L2WVPCR -+ This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WVSTPOS -+ WVSTPOS -+ 0 -+ 12 -+ -+ -+ WVSPPOS -+ WVSPPOS -+ 16 -+ 12 -+ -+ -+ -+ -+ LTDC_L2CKCR -+ LTDC_L2CKCR -+ This register defines the color key value (RGB), that is used by the color keying. -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKBLUE -+ CKBLUE -+ 0 -+ 8 -+ -+ -+ CKGREEN -+ CKGREEN -+ 8 -+ 8 -+ -+ -+ CKRED -+ CKRED -+ 16 -+ 8 -+ -+ -+ -+ -+ LTDC_L2PFCR -+ LTDC_L2PFCR -+ This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PF -+ PF -+ 0 -+ 3 -+ -+ -+ -+ -+ LTDC_L2CACR -+ LTDC_L2CACR -+ This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. -+ 0x118 -+ 0x20 -+ read-write -+ 0x000000FF -+ -+ -+ CONSTA -+ CONSTA -+ 0 -+ 8 -+ -+ -+ -+ -+ LTDC_L2DCCR -+ LTDC_L2DCCR -+ This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCBLUE -+ DCBLUE -+ 0 -+ 8 -+ -+ -+ DCGREEN -+ DCGREEN -+ 8 -+ 8 -+ -+ -+ DCRED -+ DCRED -+ 16 -+ 8 -+ -+ -+ DCALPHA -+ DCALPHA -+ 24 -+ 8 -+ -+ -+ -+ -+ LTDC_L2BFCR -+ LTDC_L2BFCR -+ This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000607 -+ -+ -+ BF2 -+ BF2 -+ 0 -+ 3 -+ -+ -+ BF1 -+ BF1 -+ 8 -+ 3 -+ -+ -+ -+ -+ LTDC_L2CFBAR -+ LTDC_L2CFBAR -+ This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. -+ 0x12C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBADD -+ CFBADD -+ 0 -+ 32 -+ -+ -+ -+ -+ LTDC_L2CFBLR -+ LTDC_L2CFBLR -+ This register defines the color frame buffer line length and pitch. -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBLL -+ CFBLL -+ 0 -+ 14 -+ -+ -+ CFBP -+ CFBP -+ 16 -+ 14 -+ -+ -+ -+ -+ LTDC_L2CFBLNR -+ LTDC_L2CFBLNR -+ This register defines the number of lines in the color frame buffer. -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CFBLNBR -+ CFBLNBR -+ 0 -+ 12 -+ -+ -+ -+ -+ LTDC_L2CLUTWR -+ LTDC_L2CLUTWR -+ This register defines the CLUT address and the RGB value. -+ 0x144 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BLUE -+ BLUE -+ 0 -+ 8 -+ -+ -+ GREEN -+ GREEN -+ 8 -+ 8 -+ -+ -+ RED -+ RED -+ 16 -+ 8 -+ -+ -+ CLUTADD -+ CLUTADD -+ 24 -+ 8 -+ -+ -+ -+ -+ -+ -+ USBPHYC -+ USBPHYC -+ USBPHYC -+ 0x5A006000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ USBPHYC_PLL -+ USBPHYC_PLL -+ This register is used to control the PLL of the HS PHY. -+ 0x0 -+ 0x20 -+ read-write -+ 0xC0000000 -+ -+ -+ PLLNDIV -+ PLLNDIV -+ 0 -+ 7 -+ -+ -+ PLLODF -+ PLLODF -+ 7 -+ 3 -+ -+ -+ PLLFRACIN -+ PLLFRACIN -+ 10 -+ 16 -+ -+ -+ PLLEN -+ PLLEN -+ 26 -+ 1 -+ -+ -+ PLLSTRB -+ PLLSTRB -+ 27 -+ 1 -+ -+ -+ PLLSTRBYP -+ PLLSTRBYP -+ 28 -+ 1 -+ -+ -+ PLLFRACCTL -+ PLLFRACCTL -+ 29 -+ 1 -+ -+ -+ PLLDITHEN0 -+ PLLDITHEN0 -+ 30 -+ 1 -+ -+ -+ PLLDITHEN1 -+ PLLDITHEN1 -+ 31 -+ 1 -+ -+ -+ -+ -+ USBPHYC_MISC -+ USBPHYC_MISC -+ This register is used to control the switch between controllers for the HS PHY. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SWITHOST -+ SWITHOST -+ 0 -+ 1 -+ -+ -+ PPCKDIS -+ PPCKDIS -+ 1 -+ 2 -+ -+ -+ -+ -+ USBPHYC_TUNE1 -+ USBPHYC_TUNE1 -+ This register is used to control the tune interface of the HS PHY, port #x. -+ 0x10C -+ 0x20 -+ read-write -+ 0x04070004 -+ -+ -+ INCURREN -+ INCURREN -+ 0 -+ 1 -+ -+ -+ INCURRINT -+ INCURRINT -+ 1 -+ 1 -+ -+ -+ LFSCAPEN -+ LFSCAPEN -+ 2 -+ 1 -+ -+ -+ HSDRVSLEW -+ HSDRVSLEW -+ 3 -+ 1 -+ -+ -+ HSDRVDCCUR -+ HSDRVDCCUR -+ 4 -+ 1 -+ -+ -+ HSDRVDCLEV -+ HSDRVDCLEV -+ 5 -+ 1 -+ -+ -+ HSDRVCURINCR -+ HSDRVCURINCR -+ 6 -+ 1 -+ -+ -+ FSDRVRFADJ -+ FSDRVRFADJ -+ 7 -+ 1 -+ -+ -+ HSDRVRFRED -+ HSDRVRFRED -+ 8 -+ 1 -+ -+ -+ HSDRVCHKITRM -+ HSDRVCHKITRM -+ 9 -+ 4 -+ -+ -+ HSDRVCHKZTRM -+ HSDRVCHKZTRM -+ 13 -+ 2 -+ -+ -+ OTPCOMP -+ OTPCOMP -+ 15 -+ 5 -+ -+ -+ SQLCHCTL -+ SQLCHCTL -+ 20 -+ 2 -+ -+ -+ HDRXGNEQEN -+ HDRXGNEQEN -+ 22 -+ 1 -+ -+ -+ HSRXOFF -+ HSRXOFF -+ 23 -+ 2 -+ -+ -+ HSFALLPREEM -+ HSFALLPREEM -+ 25 -+ 1 -+ -+ -+ SHTCCTCTLPROT -+ SHTCCTCTLPROT -+ 26 -+ 1 -+ -+ -+ STAGSEL -+ STAGSEL -+ 27 -+ 1 -+ -+ -+ -+ -+ USBPHYC_TUNE2 -+ USBPHYC_TUNE2 -+ This register is used to control the tune interface of the HS PHY, port #x. -+ 0x20C -+ 0x20 -+ read-write -+ 0x04070004 -+ -+ -+ INCURREN -+ INCURREN -+ 0 -+ 1 -+ -+ -+ INCURRINT -+ INCURRINT -+ 1 -+ 1 -+ -+ -+ LFSCAPEN -+ LFSCAPEN -+ 2 -+ 1 -+ -+ -+ HSDRVSLEW -+ HSDRVSLEW -+ 3 -+ 1 -+ -+ -+ HSDRVDCCUR -+ HSDRVDCCUR -+ 4 -+ 1 -+ -+ -+ HSDRVDCLEV -+ HSDRVDCLEV -+ 5 -+ 1 -+ -+ -+ HSDRVCURINCR -+ HSDRVCURINCR -+ 6 -+ 1 -+ -+ -+ FSDRVRFADJ -+ FSDRVRFADJ -+ 7 -+ 1 -+ -+ -+ HSDRVRFRED -+ HSDRVRFRED -+ 8 -+ 1 -+ -+ -+ HSDRVCHKITRM -+ HSDRVCHKITRM -+ 9 -+ 4 -+ -+ -+ HSDRVCHKZTRM -+ HSDRVCHKZTRM -+ 13 -+ 2 -+ -+ -+ OTPCOMP -+ OTPCOMP -+ 15 -+ 5 -+ -+ -+ SQLCHCTL -+ SQLCHCTL -+ 20 -+ 2 -+ -+ -+ HDRXGNEQEN -+ HDRXGNEQEN -+ 22 -+ 1 -+ -+ -+ HSRXOFF -+ HSRXOFF -+ 23 -+ 2 -+ -+ -+ HSFALLPREEM -+ HSFALLPREEM -+ 25 -+ 1 -+ -+ -+ SHTCCTCTLPROT -+ SHTCCTCTLPROT -+ 26 -+ 1 -+ -+ -+ STAGSEL -+ STAGSEL -+ 27 -+ 1 -+ -+ -+ -+ -+ USBPHYC_VERR -+ USBPHYC_VERR -+ This register defines the version of this IP. -+ 0xFFC -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ -+ -+ CRC1 -+ CRC1 -+ CRC1 -+ 0x58009000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ CRC_DR -+ CRC_DR -+ CRC data register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ DR -+ DR -+ 0 -+ 32 -+ -+ -+ -+ -+ CRC_IDR -+ CRC_IDR -+ CRC independent data register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDR -+ IDR -+ 0 -+ 32 -+ -+ -+ -+ -+ CRC_CR -+ CRC_CR -+ CRC control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RESET -+ RESET -+ 0 -+ 1 -+ -+ -+ POLYSIZE -+ POLYSIZE -+ 3 -+ 2 -+ -+ -+ REV_IN -+ REV_IN -+ 5 -+ 2 -+ -+ -+ REV_OUT -+ REV_OUT -+ 7 -+ 1 -+ -+ -+ -+ -+ CRC_INIT -+ CRC_INIT -+ CRC initial value -+ 0x10 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ CRC_INIT -+ CRC_INIT -+ 0 -+ 32 -+ -+ -+ -+ -+ CRC_POL -+ CRC_POL -+ CRC polynomial -+ 0x14 -+ 0x20 -+ read-write -+ 0x04C11DB7 -+ -+ -+ POL -+ POL -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ CRC2 -+ 0x4C004000 -+ -+ -+ SDMMC1 -+ SDMMC1 -+ SDMMC2 -+ 0x58005000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ SDMMC_POWER -+ SDMMC_POWER -+ SDMMC power control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PWRCTRL -+ PWRCTRL -+ 0 -+ 2 -+ -+ -+ VSWITCH -+ VSWITCH -+ 2 -+ 1 -+ -+ -+ VSWITCHEN -+ VSWITCHEN -+ 3 -+ 1 -+ -+ -+ DIRPOL -+ DIRPOL -+ 4 -+ 1 -+ -+ -+ -+ -+ SDMMC_CLKCR -+ SDMMC_CLKCR -+ The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLKDIV -+ CLKDIV -+ 0 -+ 10 -+ -+ -+ PWRSAV -+ PWRSAV -+ 12 -+ 1 -+ -+ -+ WIDBUS -+ WIDBUS -+ 14 -+ 2 -+ -+ -+ NEGEDGE -+ NEGEDGE -+ 16 -+ 1 -+ -+ -+ HWFC_EN -+ HWFC_EN -+ 17 -+ 1 -+ -+ -+ DDR -+ DDR -+ 18 -+ 1 -+ -+ -+ BUSSPEED -+ BUSSPEED -+ 19 -+ 1 -+ -+ -+ SELCLKRX -+ SELCLKRX -+ 20 -+ 2 -+ -+ -+ -+ -+ SDMMC_ARGR -+ SDMMC_ARGR -+ The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMDARG -+ CMDARG -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_CMDR -+ SDMMC_CMDR -+ The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMDINDEX -+ CMDINDEX -+ 0 -+ 6 -+ -+ -+ CMDTRANS -+ CMDTRANS -+ 6 -+ 1 -+ -+ -+ CMDSTOP -+ CMDSTOP -+ 7 -+ 1 -+ -+ -+ WAITRESP -+ WAITRESP -+ 8 -+ 2 -+ -+ -+ WAITINT -+ WAITINT -+ 10 -+ 1 -+ -+ -+ WAITPEND -+ WAITPEND -+ 11 -+ 1 -+ -+ -+ CPSMEN -+ CPSMEN -+ 12 -+ 1 -+ -+ -+ DTHOLD -+ DTHOLD -+ 13 -+ 1 -+ -+ -+ BOOTMODE -+ BOOTMODE -+ 14 -+ 1 -+ -+ -+ BOOTEN -+ BOOTEN -+ 15 -+ 1 -+ -+ -+ CMDSUSPEND -+ CMDSUSPEND -+ 16 -+ 1 -+ -+ -+ -+ -+ SDMMC_RESPCMDR -+ SDMMC_RESPCMDR -+ The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RESPCMD -+ RESPCMD -+ 0 -+ 6 -+ -+ -+ -+ -+ SDMMC_RESP1R -+ SDMMC_RESP1R -+ The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CARDSTATUS1 -+ CARDSTATUS1 -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_RESP2R -+ SDMMC_RESP2R -+ The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CARDSTATUS2 -+ CARDSTATUS2 -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_RESP3R -+ SDMMC_RESP3R -+ The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CARDSTATUS3 -+ CARDSTATUS3 -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_RESP4R -+ SDMMC_RESP4R -+ The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CARDSTATUS4 -+ CARDSTATUS4 -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_DTIMER -+ SDMMC_DTIMER -+ The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATATIME -+ DATATIME -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_DLENR -+ SDMMC_DLENR -+ The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATALENGTH -+ DATALENGTH -+ 0 -+ 25 -+ -+ -+ -+ -+ SDMMC_DCTRL -+ SDMMC_DCTRL -+ The SDMMC_DCTRL register control the data path state machine (DPSM). -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTEN -+ DTEN -+ 0 -+ 1 -+ -+ -+ DTDIR -+ DTDIR -+ 1 -+ 1 -+ -+ -+ DTMODE -+ DTMODE -+ 2 -+ 2 -+ -+ -+ DBLOCKSIZE -+ DBLOCKSIZE -+ 4 -+ 4 -+ -+ -+ RWSTART -+ RWSTART -+ 8 -+ 1 -+ -+ -+ RWSTOP -+ RWSTOP -+ 9 -+ 1 -+ -+ -+ RWMOD -+ RWMOD -+ 10 -+ 1 -+ -+ -+ SDIOEN -+ SDIOEN -+ 11 -+ 1 -+ -+ -+ BOOTACKEN -+ BOOTACKEN -+ 12 -+ 1 -+ -+ -+ FIFORST -+ FIFORST -+ 13 -+ 1 -+ -+ -+ -+ -+ SDMMC_DCNTR -+ SDMMC_DCNTR -+ The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DATACOUNT -+ DATACOUNT -+ 0 -+ 25 -+ -+ -+ -+ -+ SDMMC_STAR -+ SDMMC_STAR -+ The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) -+ 0x34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CCRCFAIL -+ CCRCFAIL -+ 0 -+ 1 -+ -+ -+ DCRCFAIL -+ DCRCFAIL -+ 1 -+ 1 -+ -+ -+ CTIMEOUT -+ CTIMEOUT -+ 2 -+ 1 -+ -+ -+ DTIMEOUT -+ DTIMEOUT -+ 3 -+ 1 -+ -+ -+ TXUNDERR -+ TXUNDERR -+ 4 -+ 1 -+ -+ -+ RXOVERR -+ RXOVERR -+ 5 -+ 1 -+ -+ -+ CMDREND -+ CMDREND -+ 6 -+ 1 -+ -+ -+ CMDSENT -+ CMDSENT -+ 7 -+ 1 -+ -+ -+ DATAEND -+ DATAEND -+ 8 -+ 1 -+ -+ -+ DHOLD -+ DHOLD -+ 9 -+ 1 -+ -+ -+ DBCKEND -+ DBCKEND -+ 10 -+ 1 -+ -+ -+ DABORT -+ DABORT -+ 11 -+ 1 -+ -+ -+ DPSMACT -+ DPSMACT -+ 12 -+ 1 -+ -+ -+ CPSMACT -+ CPSMACT -+ 13 -+ 1 -+ -+ -+ TXFIFOHE -+ TXFIFOHE -+ 14 -+ 1 -+ -+ -+ RXFIFOHF -+ RXFIFOHF -+ 15 -+ 1 -+ -+ -+ TXFIFOF -+ TXFIFOF -+ 16 -+ 1 -+ -+ -+ RXFIFOF -+ RXFIFOF -+ 17 -+ 1 -+ -+ -+ TXFIFOE -+ TXFIFOE -+ 18 -+ 1 -+ -+ -+ RXFIFOE -+ RXFIFOE -+ 19 -+ 1 -+ -+ -+ BUSYD0 -+ BUSYD0 -+ 20 -+ 1 -+ -+ -+ BUSYD0END -+ BUSYD0END -+ 21 -+ 1 -+ -+ -+ SDIOIT -+ SDIOIT -+ 22 -+ 1 -+ -+ -+ ACKFAIL -+ ACKFAIL -+ 23 -+ 1 -+ -+ -+ ACKTIMEOUT -+ ACKTIMEOUT -+ 24 -+ 1 -+ -+ -+ VSWEND -+ VSWEND -+ 25 -+ 1 -+ -+ -+ CKSTOP -+ CKSTOP -+ 26 -+ 1 -+ -+ -+ IDMATE -+ IDMATE -+ 27 -+ 1 -+ -+ -+ IDMABTC -+ IDMABTC -+ 28 -+ 1 -+ -+ -+ -+ -+ SDMMC_ICR -+ SDMMC_ICR -+ The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCRCFAILC -+ CCRCFAILC -+ 0 -+ 1 -+ -+ -+ DCRCFAILC -+ DCRCFAILC -+ 1 -+ 1 -+ -+ -+ CTIMEOUTC -+ CTIMEOUTC -+ 2 -+ 1 -+ -+ -+ DTIMEOUTC -+ DTIMEOUTC -+ 3 -+ 1 -+ -+ -+ TXUNDERRC -+ TXUNDERRC -+ 4 -+ 1 -+ -+ -+ RXOVERRC -+ RXOVERRC -+ 5 -+ 1 -+ -+ -+ CMDRENDC -+ CMDRENDC -+ 6 -+ 1 -+ -+ -+ CMDSENTC -+ CMDSENTC -+ 7 -+ 1 -+ -+ -+ DATAENDC -+ DATAENDC -+ 8 -+ 1 -+ -+ -+ DHOLDC -+ DHOLDC -+ 9 -+ 1 -+ -+ -+ DBCKENDC -+ DBCKENDC -+ 10 -+ 1 -+ -+ -+ DABORTC -+ DABORTC -+ 11 -+ 1 -+ -+ -+ BUSYD0ENDC -+ BUSYD0ENDC -+ 21 -+ 1 -+ -+ -+ SDIOITC -+ SDIOITC -+ 22 -+ 1 -+ -+ -+ ACKFAILC -+ ACKFAILC -+ 23 -+ 1 -+ -+ -+ ACKTIMEOUTC -+ ACKTIMEOUTC -+ 24 -+ 1 -+ -+ -+ VSWENDC -+ VSWENDC -+ 25 -+ 1 -+ -+ -+ CKSTOPC -+ CKSTOPC -+ 26 -+ 1 -+ -+ -+ IDMATEC -+ IDMATEC -+ 27 -+ 1 -+ -+ -+ IDMABTCC -+ IDMABTCC -+ 28 -+ 1 -+ -+ -+ -+ -+ SDMMC_MASKR -+ SDMMC_MASKR -+ The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CCRCFAILIE -+ CCRCFAILIE -+ 0 -+ 1 -+ -+ -+ DCRCFAILIE -+ DCRCFAILIE -+ 1 -+ 1 -+ -+ -+ CTIMEOUTIE -+ CTIMEOUTIE -+ 2 -+ 1 -+ -+ -+ DTIMEOUTIE -+ DTIMEOUTIE -+ 3 -+ 1 -+ -+ -+ TXUNDERRIE -+ TXUNDERRIE -+ 4 -+ 1 -+ -+ -+ RXOVERRIE -+ RXOVERRIE -+ 5 -+ 1 -+ -+ -+ CMDRENDIE -+ CMDRENDIE -+ 6 -+ 1 -+ -+ -+ CMDSENTIE -+ CMDSENTIE -+ 7 -+ 1 -+ -+ -+ DATAENDIE -+ DATAENDIE -+ 8 -+ 1 -+ -+ -+ DHOLDIE -+ DHOLDIE -+ 9 -+ 1 -+ -+ -+ DBCKENDIE -+ DBCKENDIE -+ 10 -+ 1 -+ -+ -+ DABORTIE -+ DABORTIE -+ 11 -+ 1 -+ -+ -+ TXFIFOHEIE -+ TXFIFOHEIE -+ 14 -+ 1 -+ -+ -+ RXFIFOHFIE -+ RXFIFOHFIE -+ 15 -+ 1 -+ -+ -+ RXFIFOFIE -+ RXFIFOFIE -+ 17 -+ 1 -+ -+ -+ TXFIFOEIE -+ TXFIFOEIE -+ 18 -+ 1 -+ -+ -+ BUSYD0ENDIE -+ BUSYD0ENDIE -+ 21 -+ 1 -+ -+ -+ SDIOITIE -+ SDIOITIE -+ 22 -+ 1 -+ -+ -+ ACKFAILIE -+ ACKFAILIE -+ 23 -+ 1 -+ -+ -+ ACKTIMEOUTIE -+ ACKTIMEOUTIE -+ 24 -+ 1 -+ -+ -+ VSWENDIE -+ VSWENDIE -+ 25 -+ 1 -+ -+ -+ CKSTOPIE -+ CKSTOPIE -+ 26 -+ 1 -+ -+ -+ IDMABTCIE -+ IDMABTCIE -+ 28 -+ 1 -+ -+ -+ -+ -+ SDMMC_ACKTIMER -+ SDMMC_ACKTIMER -+ The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ACKTIME -+ ACKTIME -+ 0 -+ 25 -+ -+ -+ -+ -+ SDMMC_IDMACTRLR -+ SDMMC_IDMACTRLR -+ The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDMAEN -+ IDMAEN -+ 0 -+ 1 -+ -+ -+ IDMABMODE -+ IDMABMODE -+ 1 -+ 1 -+ -+ -+ -+ -+ SDMMC_IDMABSIZER -+ SDMMC_IDMABSIZER -+ The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDMABNDT -+ IDMABNDT -+ 5 -+ 12 -+ -+ -+ -+ -+ SDMMC_IDMABASER -+ SDMMC_IDMABASER -+ The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDMABASE -+ IDMABASE -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_IDMALAR -+ SDMMC_IDMALAR -+ SDMMC IDMA linked list address register -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDMALA -+ IDMALA -+ 2 -+ 14 -+ -+ -+ ABR -+ ABR -+ 29 -+ 1 -+ -+ -+ ULS -+ ULS -+ 30 -+ 1 -+ -+ -+ ULA -+ ULA -+ 31 -+ 1 -+ -+ -+ -+ -+ SDMMC_IDMABAR -+ SDMMC_IDMABAR -+ SDMMC IDMA linked list memory base register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IDMABA -+ IDMABA -+ 2 -+ 30 -+ -+ -+ -+ -+ SDMMC_FIFOR0 -+ SDMMC_FIFOR0 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR1 -+ SDMMC_FIFOR1 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR2 -+ SDMMC_FIFOR2 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR3 -+ SDMMC_FIFOR3 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR4 -+ SDMMC_FIFOR4 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR5 -+ SDMMC_FIFOR5 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR6 -+ SDMMC_FIFOR6 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR7 -+ SDMMC_FIFOR7 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR8 -+ SDMMC_FIFOR8 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR9 -+ SDMMC_FIFOR9 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR10 -+ SDMMC_FIFOR10 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR11 -+ SDMMC_FIFOR11 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR12 -+ SDMMC_FIFOR12 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR13 -+ SDMMC_FIFOR13 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR14 -+ SDMMC_FIFOR14 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xB8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_FIFOR15 -+ SDMMC_FIFOR15 -+ The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. -+ 0xBC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FIFODATA -+ FIFODATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_VERR -+ SDMMC_VERR -+ SDMMC version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ SDMMC_IPIDR -+ SDMMC_IPIDR -+ SDMMC identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140022 -+ -+ -+ IP_ID -+ IP_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ SDMMC_SIDR -+ SDMMC_SIDR -+ SDMMC size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ SDMMC2 -+ 0x58007000 -+ -+ -+ SDMMC3 -+ 0x48004000 -+ -+ -+ QUADSPI -+ QUADSPI1 -+ QUADSPI1 -+ 0x58003000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ QUADSPI_CR -+ QUADSPI_CR -+ QUADSPI control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ ABORT -+ ABORT -+ 1 -+ 1 -+ -+ -+ DMAEN -+ DMAEN -+ 2 -+ 1 -+ -+ -+ TCEN -+ TCEN -+ 3 -+ 1 -+ -+ -+ SSHIFT -+ SSHIFT -+ 4 -+ 1 -+ -+ -+ DFM -+ DFM -+ 6 -+ 1 -+ -+ -+ FSEL -+ FSEL -+ 7 -+ 1 -+ -+ -+ FTHRES -+ FTHRES -+ 8 -+ 4 -+ -+ -+ TEIE -+ TEIE -+ 16 -+ 1 -+ -+ -+ TCIE -+ TCIE -+ 17 -+ 1 -+ -+ -+ FTIE -+ FTIE -+ 18 -+ 1 -+ -+ -+ SMIE -+ SMIE -+ 19 -+ 1 -+ -+ -+ TOIE -+ TOIE -+ 20 -+ 1 -+ -+ -+ APMS -+ APMS -+ 22 -+ 1 -+ -+ -+ PMM -+ PMM -+ 23 -+ 1 -+ -+ -+ PRESCALER -+ PRESCALER -+ 24 -+ 8 -+ -+ -+ -+ -+ QUADSPI_DCR -+ QUADSPI_DCR -+ QUADSPI device configuration register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKMODE -+ CKMODE -+ 0 -+ 1 -+ -+ -+ CSHT -+ CSHT -+ 8 -+ 3 -+ -+ -+ FSIZE -+ FSIZE -+ 16 -+ 5 -+ -+ -+ -+ -+ QUADSPI_SR -+ QUADSPI_SR -+ QUADSPI status register -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEF -+ TEF -+ 0 -+ 1 -+ -+ -+ TCF -+ TCF -+ 1 -+ 1 -+ -+ -+ FTF -+ FTF -+ 2 -+ 1 -+ -+ -+ SMF -+ SMF -+ 3 -+ 1 -+ -+ -+ TOF -+ TOF -+ 4 -+ 1 -+ -+ -+ BUSY -+ BUSY -+ 5 -+ 1 -+ -+ -+ FLEVEL -+ FLEVEL -+ 8 -+ 5 -+ -+ -+ -+ -+ QUADSPI_FCR -+ QUADSPI_FCR -+ QUADSPI flag clear register -+ 0xC -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEF -+ CTEF -+ 0 -+ 1 -+ -+ -+ CTCF -+ CTCF -+ 1 -+ 1 -+ -+ -+ CSMF -+ CSMF -+ 3 -+ 1 -+ -+ -+ CTOF -+ CTOF -+ 4 -+ 1 -+ -+ -+ -+ -+ QUADSPI_DLR -+ QUADSPI_DLR -+ QUADSPI data length register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DL -+ DL -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_CCR -+ QUADSPI_CCR -+ QUADSPI communication configuration register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INSTRUCTION -+ INSTRUCTION -+ 0 -+ 8 -+ -+ -+ IMODE -+ IMODE -+ 8 -+ 2 -+ -+ -+ ADMODE -+ ADMODE -+ 10 -+ 2 -+ -+ -+ ADSIZE -+ ADSIZE -+ 12 -+ 2 -+ -+ -+ ABMODE -+ ABMODE -+ 14 -+ 2 -+ -+ -+ ABSIZE -+ ABSIZE -+ 16 -+ 2 -+ -+ -+ DCYC -+ DCYC -+ 18 -+ 5 -+ -+ -+ DMODE -+ DMODE -+ 24 -+ 2 -+ -+ -+ FMODE -+ FMODE -+ 26 -+ 2 -+ -+ -+ SIOO -+ SIOO -+ 28 -+ 1 -+ -+ -+ FRCM -+ FRCM -+ 29 -+ 1 -+ -+ -+ DHHC -+ DHHC -+ 30 -+ 1 -+ -+ -+ DDRM -+ DDRM -+ 31 -+ 1 -+ -+ -+ -+ -+ QUADSPI_AR -+ QUADSPI_AR -+ QUADSPI address register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADDRESS -+ ADDRESS -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_ABR -+ QUADSPI_ABR -+ QUADSPI alternate bytes registers -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ALTERNATE -+ ALTERNATE -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_DR -+ QUADSPI_DR -+ QUADSPI data register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_PSMKR -+ QUADSPI_PSMKR -+ QUADSPI polling status mask register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MASK -+ MASK -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_PSMAR -+ QUADSPI_PSMAR -+ QUADSPI polling status match register -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MATCH -+ MATCH -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_PIR -+ QUADSPI_PIR -+ QUADSPI polling interval register -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INTERVAL -+ INTERVAL -+ 0 -+ 16 -+ -+ -+ -+ -+ QUADSPI_LPTR -+ QUADSPI_LPTR -+ QUADSPI low-power timeout register -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIMEOUT -+ TIMEOUT -+ 0 -+ 16 -+ -+ -+ -+ -+ QUADSPI_HWCFGR -+ QUADSPI_HWCFGR -+ QUADSPI HW configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x0000B058 -+ -+ -+ FIFOSIZE -+ FIFOSIZE -+ 0 -+ 4 -+ -+ -+ FIFOPTR -+ FIFOPTR -+ 4 -+ 4 -+ -+ -+ PRESCVAL -+ PRESCVAL -+ 8 -+ 4 -+ -+ -+ IDLENGTH -+ IDLENGTH -+ 12 -+ 4 -+ -+ -+ -+ -+ QUADSPI_VERR -+ QUADSPI_VERR -+ QUADSPI version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000041 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ QUADSPI_IPIDR -+ QUADSPI_IPIDR -+ QUADSPI identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140031 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ QUADSPI_SIDR -+ QUADSPI_SIDR -+ QUADSPI size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ MDMA -+ MDMA1 -+ MDMA1 -+ 0x58000000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ MDMA_GISR0 -+ MDMA_GISR0 -+ MDMA global interrupt/status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ GIF0 -+ GIF0 -+ 0 -+ 1 -+ -+ -+ GIF1 -+ GIF1 -+ 1 -+ 1 -+ -+ -+ GIF2 -+ GIF2 -+ 2 -+ 1 -+ -+ -+ GIF3 -+ GIF3 -+ 3 -+ 1 -+ -+ -+ GIF4 -+ GIF4 -+ 4 -+ 1 -+ -+ -+ GIF5 -+ GIF5 -+ 5 -+ 1 -+ -+ -+ GIF6 -+ GIF6 -+ 6 -+ 1 -+ -+ -+ GIF7 -+ GIF7 -+ 7 -+ 1 -+ -+ -+ GIF8 -+ GIF8 -+ 8 -+ 1 -+ -+ -+ GIF9 -+ GIF9 -+ 9 -+ 1 -+ -+ -+ GIF10 -+ GIF10 -+ 10 -+ 1 -+ -+ -+ GIF11 -+ GIF11 -+ 11 -+ 1 -+ -+ -+ GIF12 -+ GIF12 -+ 12 -+ 1 -+ -+ -+ GIF13 -+ GIF13 -+ 13 -+ 1 -+ -+ -+ GIF14 -+ GIF14 -+ 14 -+ 1 -+ -+ -+ GIF15 -+ GIF15 -+ 15 -+ 1 -+ -+ -+ GIF16 -+ GIF16 -+ 16 -+ 1 -+ -+ -+ GIF17 -+ GIF17 -+ 17 -+ 1 -+ -+ -+ GIF18 -+ GIF18 -+ 18 -+ 1 -+ -+ -+ GIF19 -+ GIF19 -+ 19 -+ 1 -+ -+ -+ GIF20 -+ GIF20 -+ 20 -+ 1 -+ -+ -+ GIF21 -+ GIF21 -+ 21 -+ 1 -+ -+ -+ GIF22 -+ GIF22 -+ 22 -+ 1 -+ -+ -+ GIF23 -+ GIF23 -+ 23 -+ 1 -+ -+ -+ GIF24 -+ GIF24 -+ 24 -+ 1 -+ -+ -+ GIF25 -+ GIF25 -+ 25 -+ 1 -+ -+ -+ GIF26 -+ GIF26 -+ 26 -+ 1 -+ -+ -+ GIF27 -+ GIF27 -+ 27 -+ 1 -+ -+ -+ GIF28 -+ GIF28 -+ 28 -+ 1 -+ -+ -+ GIF29 -+ GIF29 -+ 29 -+ 1 -+ -+ -+ GIF30 -+ GIF30 -+ 30 -+ 1 -+ -+ -+ GIF31 -+ GIF31 -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_SGISR0 -+ MDMA_SGISR0 -+ MDMA secure global interrupt/status register -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ GIF0 -+ GIF0 -+ 0 -+ 1 -+ -+ -+ GIF1 -+ GIF1 -+ 1 -+ 1 -+ -+ -+ GIF2 -+ GIF2 -+ 2 -+ 1 -+ -+ -+ GIF3 -+ GIF3 -+ 3 -+ 1 -+ -+ -+ GIF4 -+ GIF4 -+ 4 -+ 1 -+ -+ -+ GIF5 -+ GIF5 -+ 5 -+ 1 -+ -+ -+ GIF6 -+ GIF6 -+ 6 -+ 1 -+ -+ -+ GIF7 -+ GIF7 -+ 7 -+ 1 -+ -+ -+ GIF8 -+ GIF8 -+ 8 -+ 1 -+ -+ -+ GIF9 -+ GIF9 -+ 9 -+ 1 -+ -+ -+ GIF10 -+ GIF10 -+ 10 -+ 1 -+ -+ -+ GIF11 -+ GIF11 -+ 11 -+ 1 -+ -+ -+ GIF12 -+ GIF12 -+ 12 -+ 1 -+ -+ -+ GIF13 -+ GIF13 -+ 13 -+ 1 -+ -+ -+ GIF14 -+ GIF14 -+ 14 -+ 1 -+ -+ -+ GIF15 -+ GIF15 -+ 15 -+ 1 -+ -+ -+ GIF16 -+ GIF16 -+ 16 -+ 1 -+ -+ -+ GIF17 -+ GIF17 -+ 17 -+ 1 -+ -+ -+ GIF18 -+ GIF18 -+ 18 -+ 1 -+ -+ -+ GIF19 -+ GIF19 -+ 19 -+ 1 -+ -+ -+ GIF20 -+ GIF20 -+ 20 -+ 1 -+ -+ -+ GIF21 -+ GIF21 -+ 21 -+ 1 -+ -+ -+ GIF22 -+ GIF22 -+ 22 -+ 1 -+ -+ -+ GIF23 -+ GIF23 -+ 23 -+ 1 -+ -+ -+ GIF24 -+ GIF24 -+ 24 -+ 1 -+ -+ -+ GIF25 -+ GIF25 -+ 25 -+ 1 -+ -+ -+ GIF26 -+ GIF26 -+ 26 -+ 1 -+ -+ -+ GIF27 -+ GIF27 -+ 27 -+ 1 -+ -+ -+ GIF28 -+ GIF28 -+ 28 -+ 1 -+ -+ -+ GIF29 -+ GIF29 -+ 29 -+ 1 -+ -+ -+ GIF30 -+ GIF30 -+ 30 -+ 1 -+ -+ -+ GIF31 -+ GIF31 -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C0ISR -+ MDMA_C0ISR -+ MDMA channel 0 interrupt/status register -+ 0x40 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C0IFCR -+ MDMA_C0IFCR -+ MDMA channel 0 interrupt flag clear register -+ 0x44 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C0ESR -+ MDMA_C0ESR -+ MDMA channel 0 error status register -+ 0x48 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C0CR -+ MDMA_C0CR -+ This register is used to control the concerned channel. -+ 0x4C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C0TCR -+ MDMA_C0TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C0BNDTR -+ MDMA_C0BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C0SAR -+ MDMA_C0SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C0DAR -+ MDMA_C0DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C0BRUR -+ MDMA_C0BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C0LAR -+ MDMA_C0LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C0TBR -+ MDMA_C0TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C0MAR -+ MDMA_C0MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C0MDR -+ MDMA_C0MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C1ISR -+ MDMA_C1ISR -+ MDMA channel 1 interrupt/status register -+ 0x80 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C1IFCR -+ MDMA_C1IFCR -+ MDMA channel 1 interrupt flag clear register -+ 0x84 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C1ESR -+ MDMA_C1ESR -+ MDMA channel 1 error status register -+ 0x88 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C1CR -+ MDMA_C1CR -+ This register is used to control the concerned channel. -+ 0x8C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C1TCR -+ MDMA_C1TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C1BNDTR -+ MDMA_C1BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C1SAR -+ MDMA_C1SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C1DAR -+ MDMA_C1DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C1BRUR -+ MDMA_C1BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C1LAR -+ MDMA_C1LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C1TBR -+ MDMA_C1TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0xA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C1MAR -+ MDMA_C1MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0xB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C1MDR -+ MDMA_C1MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0xB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C2ISR -+ MDMA_C2ISR -+ MDMA channel 2 interrupt/status register -+ 0xC0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C2IFCR -+ MDMA_C2IFCR -+ MDMA channel 2 interrupt flag clear register -+ 0xC4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C2ESR -+ MDMA_C2ESR -+ MDMA channel 2 error status register -+ 0xC8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C2CR -+ MDMA_C2CR -+ This register is used to control the concerned channel. -+ 0xCC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C2TCR -+ MDMA_C2TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C2BNDTR -+ MDMA_C2BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C2SAR -+ MDMA_C2SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0xD8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C2DAR -+ MDMA_C2DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0xDC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C2BRUR -+ MDMA_C2BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C2LAR -+ MDMA_C2LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C2TBR -+ MDMA_C2TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0xE8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C2MAR -+ MDMA_C2MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0xF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C2MDR -+ MDMA_C2MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0xF4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C3ISR -+ MDMA_C3ISR -+ MDMA channel 3 interrupt/status register -+ 0x100 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C3IFCR -+ MDMA_C3IFCR -+ MDMA channel 3 interrupt flag clear register -+ 0x104 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C3ESR -+ MDMA_C3ESR -+ MDMA channel 3 error status register -+ 0x108 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C3CR -+ MDMA_C3CR -+ This register is used to control the concerned channel. -+ 0x10C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C3TCR -+ MDMA_C3TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C3BNDTR -+ MDMA_C3BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C3SAR -+ MDMA_C3SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C3DAR -+ MDMA_C3DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C3BRUR -+ MDMA_C3BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C3LAR -+ MDMA_C3LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C3TBR -+ MDMA_C3TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C3MAR -+ MDMA_C3MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C3MDR -+ MDMA_C3MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C4ISR -+ MDMA_C4ISR -+ MDMA channel 4 interrupt/status register -+ 0x140 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C4IFCR -+ MDMA_C4IFCR -+ MDMA channel 4 interrupt flag clear register -+ 0x144 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C4ESR -+ MDMA_C4ESR -+ MDMA channel 4 error status register -+ 0x148 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C4CR -+ MDMA_C4CR -+ This register is used to control the concerned channel. -+ 0x14C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C4TCR -+ MDMA_C4TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C4BNDTR -+ MDMA_C4BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x154 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C4SAR -+ MDMA_C4SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x158 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C4DAR -+ MDMA_C4DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x15C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C4BRUR -+ MDMA_C4BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C4LAR -+ MDMA_C4LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x164 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C4TBR -+ MDMA_C4TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x168 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C4MAR -+ MDMA_C4MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x170 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C4MDR -+ MDMA_C4MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x174 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C5ISR -+ MDMA_C5ISR -+ MDMA channel 5 interrupt/status register -+ 0x180 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C5IFCR -+ MDMA_C5IFCR -+ MDMA channel 5 interrupt flag clear register -+ 0x184 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C5ESR -+ MDMA_C5ESR -+ MDMA channel 5 error status register -+ 0x188 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C5CR -+ MDMA_C5CR -+ This register is used to control the concerned channel. -+ 0x18C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C5TCR -+ MDMA_C5TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C5BNDTR -+ MDMA_C5BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C5SAR -+ MDMA_C5SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x198 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C5DAR -+ MDMA_C5DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x19C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C5BRUR -+ MDMA_C5BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C5LAR -+ MDMA_C5LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C5TBR -+ MDMA_C5TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x1A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C5MAR -+ MDMA_C5MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x1B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C5MDR -+ MDMA_C5MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x1B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C6ISR -+ MDMA_C6ISR -+ MDMA channel 6 interrupt/status register -+ 0x1C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C6IFCR -+ MDMA_C6IFCR -+ MDMA channel 6 interrupt flag clear register -+ 0x1C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C6ESR -+ MDMA_C6ESR -+ MDMA channel 6 error status register -+ 0x1C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C6CR -+ MDMA_C6CR -+ This register is used to control the concerned channel. -+ 0x1CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C6TCR -+ MDMA_C6TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x1D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C6BNDTR -+ MDMA_C6BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x1D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C6SAR -+ MDMA_C6SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x1D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C6DAR -+ MDMA_C6DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x1DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C6BRUR -+ MDMA_C6BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x1E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C6LAR -+ MDMA_C6LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x1E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C6TBR -+ MDMA_C6TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x1E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C6MAR -+ MDMA_C6MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x1F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C6MDR -+ MDMA_C6MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x1F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C7ISR -+ MDMA_C7ISR -+ MDMA channel 7 interrupt/status register -+ 0x200 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C7IFCR -+ MDMA_C7IFCR -+ MDMA channel 7 interrupt flag clear register -+ 0x204 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C7ESR -+ MDMA_C7ESR -+ MDMA channel 7 error status register -+ 0x208 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C7CR -+ MDMA_C7CR -+ This register is used to control the concerned channel. -+ 0x20C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C7TCR -+ MDMA_C7TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C7BNDTR -+ MDMA_C7BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x214 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C7SAR -+ MDMA_C7SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x218 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C7DAR -+ MDMA_C7DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x21C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C7BRUR -+ MDMA_C7BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C7LAR -+ MDMA_C7LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C7TBR -+ MDMA_C7TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x228 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C7MAR -+ MDMA_C7MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x230 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C7MDR -+ MDMA_C7MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x234 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C8ISR -+ MDMA_C8ISR -+ MDMA channel 8 interrupt/status register -+ 0x240 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C8IFCR -+ MDMA_C8IFCR -+ MDMA channel 8 interrupt flag clear register -+ 0x244 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C8ESR -+ MDMA_C8ESR -+ MDMA channel 8 error status register -+ 0x248 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C8CR -+ MDMA_C8CR -+ This register is used to control the concerned channel. -+ 0x24C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C8TCR -+ MDMA_C8TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x250 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C8BNDTR -+ MDMA_C8BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x254 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C8SAR -+ MDMA_C8SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x258 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C8DAR -+ MDMA_C8DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x25C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C8BRUR -+ MDMA_C8BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x260 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C8LAR -+ MDMA_C8LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x264 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C8TBR -+ MDMA_C8TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x268 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C8MAR -+ MDMA_C8MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x270 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C8MDR -+ MDMA_C8MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x274 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C9ISR -+ MDMA_C9ISR -+ MDMA channel 9 interrupt/status register -+ 0x280 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C9IFCR -+ MDMA_C9IFCR -+ MDMA channel 9 interrupt flag clear register -+ 0x284 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C9ESR -+ MDMA_C9ESR -+ MDMA channel 9 error status register -+ 0x288 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C9CR -+ MDMA_C9CR -+ This register is used to control the concerned channel. -+ 0x28C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C9TCR -+ MDMA_C9TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x290 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C9BNDTR -+ MDMA_C9BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x294 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C9SAR -+ MDMA_C9SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x298 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C9DAR -+ MDMA_C9DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x29C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C9BRUR -+ MDMA_C9BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x2A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C9LAR -+ MDMA_C9LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x2A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C9TBR -+ MDMA_C9TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x2A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C9MAR -+ MDMA_C9MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x2B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C9MDR -+ MDMA_C9MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x2B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C10ISR -+ MDMA_C10ISR -+ MDMA channel 10 interrupt/status register -+ 0x2C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C10IFCR -+ MDMA_C10IFCR -+ MDMA channel 10 interrupt flag clear register -+ 0x2C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C10ESR -+ MDMA_C10ESR -+ MDMA channel 10 error status register -+ 0x2C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C10CR -+ MDMA_C10CR -+ This register is used to control the concerned channel. -+ 0x2CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C10TCR -+ MDMA_C10TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x2D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C10BNDTR -+ MDMA_C10BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x2D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C10SAR -+ MDMA_C10SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x2D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C10DAR -+ MDMA_C10DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x2DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C10BRUR -+ MDMA_C10BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x2E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C10LAR -+ MDMA_C10LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x2E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C10TBR -+ MDMA_C10TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x2E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C10MAR -+ MDMA_C10MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x2F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C10MDR -+ MDMA_C10MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x2F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C11ISR -+ MDMA_C11ISR -+ MDMA channel 11 interrupt/status register -+ 0x300 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C11IFCR -+ MDMA_C11IFCR -+ MDMA channel 11 interrupt flag clear register -+ 0x304 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C11ESR -+ MDMA_C11ESR -+ MDMA channel 11 error status register -+ 0x308 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C11CR -+ MDMA_C11CR -+ This register is used to control the concerned channel. -+ 0x30C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C11TCR -+ MDMA_C11TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C11BNDTR -+ MDMA_C11BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C11SAR -+ MDMA_C11SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x318 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C11DAR -+ MDMA_C11DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x31C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C11BRUR -+ MDMA_C11BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C11LAR -+ MDMA_C11LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x324 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C11TBR -+ MDMA_C11TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x328 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C11MAR -+ MDMA_C11MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x330 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C11MDR -+ MDMA_C11MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x334 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C12ISR -+ MDMA_C12ISR -+ MDMA channel 12 interrupt/status register -+ 0x340 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C12IFCR -+ MDMA_C12IFCR -+ MDMA channel 12 interrupt flag clear register -+ 0x344 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C12ESR -+ MDMA_C12ESR -+ MDMA channel 12 error status register -+ 0x348 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C12CR -+ MDMA_C12CR -+ This register is used to control the concerned channel. -+ 0x34C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C12TCR -+ MDMA_C12TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x350 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C12BNDTR -+ MDMA_C12BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x354 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C12SAR -+ MDMA_C12SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x358 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C12DAR -+ MDMA_C12DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x35C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C12BRUR -+ MDMA_C12BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x360 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C12LAR -+ MDMA_C12LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x364 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C12TBR -+ MDMA_C12TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x368 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C12MAR -+ MDMA_C12MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x370 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C12MDR -+ MDMA_C12MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x374 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C13ISR -+ MDMA_C13ISR -+ MDMA channel 13 interrupt/status register -+ 0x380 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C13IFCR -+ MDMA_C13IFCR -+ MDMA channel 13 interrupt flag clear register -+ 0x384 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C13ESR -+ MDMA_C13ESR -+ MDMA channel 13 error status register -+ 0x388 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C13CR -+ MDMA_C13CR -+ This register is used to control the concerned channel. -+ 0x38C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C13TCR -+ MDMA_C13TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x390 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C13BNDTR -+ MDMA_C13BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x394 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C13SAR -+ MDMA_C13SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x398 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C13DAR -+ MDMA_C13DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x39C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C13BRUR -+ MDMA_C13BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x3A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C13LAR -+ MDMA_C13LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x3A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C13TBR -+ MDMA_C13TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x3A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C13MAR -+ MDMA_C13MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x3B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C13MDR -+ MDMA_C13MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x3B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C14ISR -+ MDMA_C14ISR -+ MDMA channel 14 interrupt/status register -+ 0x3C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C14IFCR -+ MDMA_C14IFCR -+ MDMA channel 14 interrupt flag clear register -+ 0x3C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C14ESR -+ MDMA_C14ESR -+ MDMA channel 14 error status register -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C14CR -+ MDMA_C14CR -+ This register is used to control the concerned channel. -+ 0x3CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C14TCR -+ MDMA_C14TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x3D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C14BNDTR -+ MDMA_C14BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x3D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C14SAR -+ MDMA_C14SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x3D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C14DAR -+ MDMA_C14DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x3DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C14BRUR -+ MDMA_C14BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x3E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C14LAR -+ MDMA_C14LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x3E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C14TBR -+ MDMA_C14TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x3E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C14MAR -+ MDMA_C14MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x3F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C14MDR -+ MDMA_C14MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x3F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C15ISR -+ MDMA_C15ISR -+ MDMA channel 15 interrupt/status register -+ 0x400 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C15IFCR -+ MDMA_C15IFCR -+ MDMA channel 15 interrupt flag clear register -+ 0x404 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C15ESR -+ MDMA_C15ESR -+ MDMA channel 15 error status register -+ 0x408 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C15CR -+ MDMA_C15CR -+ This register is used to control the concerned channel. -+ 0x40C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C15TCR -+ MDMA_C15TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x410 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C15BNDTR -+ MDMA_C15BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x414 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C15SAR -+ MDMA_C15SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x418 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C15DAR -+ MDMA_C15DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x41C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C15BRUR -+ MDMA_C15BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x420 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C15LAR -+ MDMA_C15LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x424 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C15TBR -+ MDMA_C15TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x428 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C15MAR -+ MDMA_C15MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x430 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C15MDR -+ MDMA_C15MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x434 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C16ISR -+ MDMA_C16ISR -+ MDMA channel 16 interrupt/status register -+ 0x440 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C16IFCR -+ MDMA_C16IFCR -+ MDMA channel 16 interrupt flag clear register -+ 0x444 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C16ESR -+ MDMA_C16ESR -+ MDMA channel 16 error status register -+ 0x448 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C16CR -+ MDMA_C16CR -+ This register is used to control the concerned channel. -+ 0x44C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C16TCR -+ MDMA_C16TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x450 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C16BNDTR -+ MDMA_C16BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x454 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C16SAR -+ MDMA_C16SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x458 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C16DAR -+ MDMA_C16DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x45C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C16BRUR -+ MDMA_C16BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x460 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C16LAR -+ MDMA_C16LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x464 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C16TBR -+ MDMA_C16TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x468 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C16MAR -+ MDMA_C16MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x470 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C16MDR -+ MDMA_C16MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x474 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C17ISR -+ MDMA_C17ISR -+ MDMA channel 17 interrupt/status register -+ 0x480 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C17IFCR -+ MDMA_C17IFCR -+ MDMA channel 17 interrupt flag clear register -+ 0x484 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C17ESR -+ MDMA_C17ESR -+ MDMA channel 17 error status register -+ 0x488 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C17CR -+ MDMA_C17CR -+ This register is used to control the concerned channel. -+ 0x48C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C17TCR -+ MDMA_C17TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x490 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C17BNDTR -+ MDMA_C17BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x494 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C17SAR -+ MDMA_C17SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x498 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C17DAR -+ MDMA_C17DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x49C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C17BRUR -+ MDMA_C17BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x4A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C17LAR -+ MDMA_C17LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x4A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C17TBR -+ MDMA_C17TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x4A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C17MAR -+ MDMA_C17MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x4B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C17MDR -+ MDMA_C17MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x4B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C18ISR -+ MDMA_C18ISR -+ MDMA channel 18 interrupt/status register -+ 0x4C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C18IFCR -+ MDMA_C18IFCR -+ MDMA channel 18 interrupt flag clear register -+ 0x4C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C18ESR -+ MDMA_C18ESR -+ MDMA channel 18 error status register -+ 0x4C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C18CR -+ MDMA_C18CR -+ This register is used to control the concerned channel. -+ 0x4CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C18TCR -+ MDMA_C18TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x4D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C18BNDTR -+ MDMA_C18BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x4D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C18SAR -+ MDMA_C18SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x4D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C18DAR -+ MDMA_C18DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x4DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C18BRUR -+ MDMA_C18BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x4E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C18LAR -+ MDMA_C18LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x4E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C18TBR -+ MDMA_C18TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x4E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C18MAR -+ MDMA_C18MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x4F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C18MDR -+ MDMA_C18MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x4F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C19ISR -+ MDMA_C19ISR -+ MDMA channel 19 interrupt/status register -+ 0x500 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C19IFCR -+ MDMA_C19IFCR -+ MDMA channel 19 interrupt flag clear register -+ 0x504 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C19ESR -+ MDMA_C19ESR -+ MDMA channel 19 error status register -+ 0x508 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C19CR -+ MDMA_C19CR -+ This register is used to control the concerned channel. -+ 0x50C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C19TCR -+ MDMA_C19TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x510 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C19BNDTR -+ MDMA_C19BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x514 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C19SAR -+ MDMA_C19SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x518 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C19DAR -+ MDMA_C19DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x51C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C19BRUR -+ MDMA_C19BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x520 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C19LAR -+ MDMA_C19LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x524 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C19TBR -+ MDMA_C19TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x528 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C19MAR -+ MDMA_C19MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x530 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C19MDR -+ MDMA_C19MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x534 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C20ISR -+ MDMA_C20ISR -+ MDMA channel 20 interrupt/status register -+ 0x540 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C20IFCR -+ MDMA_C20IFCR -+ MDMA channel 20 interrupt flag clear register -+ 0x544 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C20ESR -+ MDMA_C20ESR -+ MDMA channel 20 error status register -+ 0x548 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C20CR -+ MDMA_C20CR -+ This register is used to control the concerned channel. -+ 0x54C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C20TCR -+ MDMA_C20TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x550 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C20BNDTR -+ MDMA_C20BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x554 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C20SAR -+ MDMA_C20SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x558 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C20DAR -+ MDMA_C20DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x55C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C20BRUR -+ MDMA_C20BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x560 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C20LAR -+ MDMA_C20LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x564 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C20TBR -+ MDMA_C20TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x568 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C20MAR -+ MDMA_C20MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x570 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C20MDR -+ MDMA_C20MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x574 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C21ISR -+ MDMA_C21ISR -+ MDMA channel 21 interrupt/status register -+ 0x580 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C21IFCR -+ MDMA_C21IFCR -+ MDMA channel 21 interrupt flag clear register -+ 0x584 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C21ESR -+ MDMA_C21ESR -+ MDMA channel 21 error status register -+ 0x588 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C21CR -+ MDMA_C21CR -+ This register is used to control the concerned channel. -+ 0x58C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C21TCR -+ MDMA_C21TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x590 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C21BNDTR -+ MDMA_C21BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x594 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C21SAR -+ MDMA_C21SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x598 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C21DAR -+ MDMA_C21DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x59C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C21BRUR -+ MDMA_C21BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x5A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C21LAR -+ MDMA_C21LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x5A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C21TBR -+ MDMA_C21TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x5A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C21MAR -+ MDMA_C21MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x5B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C21MDR -+ MDMA_C21MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x5B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C22ISR -+ MDMA_C22ISR -+ MDMA channel 22 interrupt/status register -+ 0x5C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C22IFCR -+ MDMA_C22IFCR -+ MDMA channel 22 interrupt flag clear register -+ 0x5C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C22ESR -+ MDMA_C22ESR -+ MDMA channel 22 error status register -+ 0x5C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C22CR -+ MDMA_C22CR -+ This register is used to control the concerned channel. -+ 0x5CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C22TCR -+ MDMA_C22TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x5D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C22BNDTR -+ MDMA_C22BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x5D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C22SAR -+ MDMA_C22SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x5D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C22DAR -+ MDMA_C22DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x5DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C22BRUR -+ MDMA_C22BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x5E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C22LAR -+ MDMA_C22LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x5E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C22TBR -+ MDMA_C22TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x5E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C22MAR -+ MDMA_C22MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x5F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C22MDR -+ MDMA_C22MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x5F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C23ISR -+ MDMA_C23ISR -+ MDMA channel 23 interrupt/status register -+ 0x600 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C23IFCR -+ MDMA_C23IFCR -+ MDMA channel 23 interrupt flag clear register -+ 0x604 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C23ESR -+ MDMA_C23ESR -+ MDMA channel 23 error status register -+ 0x608 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C23CR -+ MDMA_C23CR -+ This register is used to control the concerned channel. -+ 0x60C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C23TCR -+ MDMA_C23TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x610 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C23BNDTR -+ MDMA_C23BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x614 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C23SAR -+ MDMA_C23SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x618 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C23DAR -+ MDMA_C23DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x61C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C23BRUR -+ MDMA_C23BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x620 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C23LAR -+ MDMA_C23LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x624 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C23TBR -+ MDMA_C23TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x628 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C23MAR -+ MDMA_C23MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x630 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C23MDR -+ MDMA_C23MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x634 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C24ISR -+ MDMA_C24ISR -+ MDMA channel 24 interrupt/status register -+ 0x640 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C24IFCR -+ MDMA_C24IFCR -+ MDMA channel 24 interrupt flag clear register -+ 0x644 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C24ESR -+ MDMA_C24ESR -+ MDMA channel 24 error status register -+ 0x648 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C24CR -+ MDMA_C24CR -+ This register is used to control the concerned channel. -+ 0x64C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C24TCR -+ MDMA_C24TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x650 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C24BNDTR -+ MDMA_C24BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x654 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C24SAR -+ MDMA_C24SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x658 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C24DAR -+ MDMA_C24DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x65C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C24BRUR -+ MDMA_C24BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x660 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C24LAR -+ MDMA_C24LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x664 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C24TBR -+ MDMA_C24TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x668 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C24MAR -+ MDMA_C24MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x670 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C24MDR -+ MDMA_C24MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x674 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C25ISR -+ MDMA_C25ISR -+ MDMA channel 25 interrupt/status register -+ 0x680 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C25IFCR -+ MDMA_C25IFCR -+ MDMA channel 25 interrupt flag clear register -+ 0x684 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C25ESR -+ MDMA_C25ESR -+ MDMA channel 25 error status register -+ 0x688 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C25CR -+ MDMA_C25CR -+ This register is used to control the concerned channel. -+ 0x68C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C25TCR -+ MDMA_C25TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x690 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C25BNDTR -+ MDMA_C25BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x694 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C25SAR -+ MDMA_C25SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x698 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C25DAR -+ MDMA_C25DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x69C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C25BRUR -+ MDMA_C25BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x6A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C25LAR -+ MDMA_C25LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x6A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C25TBR -+ MDMA_C25TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x6A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C25MAR -+ MDMA_C25MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x6B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C25MDR -+ MDMA_C25MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x6B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C26ISR -+ MDMA_C26ISR -+ MDMA channel 26 interrupt/status register -+ 0x6C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C26IFCR -+ MDMA_C26IFCR -+ MDMA channel 26 interrupt flag clear register -+ 0x6C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C26ESR -+ MDMA_C26ESR -+ MDMA channel 26 error status register -+ 0x6C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C26CR -+ MDMA_C26CR -+ This register is used to control the concerned channel. -+ 0x6CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C26TCR -+ MDMA_C26TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x6D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C26BNDTR -+ MDMA_C26BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x6D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C26SAR -+ MDMA_C26SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x6D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C26DAR -+ MDMA_C26DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x6DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C26BRUR -+ MDMA_C26BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x6E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C26LAR -+ MDMA_C26LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x6E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C26TBR -+ MDMA_C26TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x6E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C26MAR -+ MDMA_C26MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x6F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C26MDR -+ MDMA_C26MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x6F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C27ISR -+ MDMA_C27ISR -+ MDMA channel 27 interrupt/status register -+ 0x700 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C27IFCR -+ MDMA_C27IFCR -+ MDMA channel 27 interrupt flag clear register -+ 0x704 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C27ESR -+ MDMA_C27ESR -+ MDMA channel 27 error status register -+ 0x708 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C27CR -+ MDMA_C27CR -+ This register is used to control the concerned channel. -+ 0x70C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C27TCR -+ MDMA_C27TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x710 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C27BNDTR -+ MDMA_C27BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x714 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C27SAR -+ MDMA_C27SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x718 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C27DAR -+ MDMA_C27DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x71C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C27BRUR -+ MDMA_C27BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x720 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C27LAR -+ MDMA_C27LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x724 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C27TBR -+ MDMA_C27TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x728 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C27MAR -+ MDMA_C27MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x730 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C27MDR -+ MDMA_C27MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x734 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C28ISR -+ MDMA_C28ISR -+ MDMA channel 28 interrupt/status register -+ 0x740 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C28IFCR -+ MDMA_C28IFCR -+ MDMA channel 28 interrupt flag clear register -+ 0x744 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C28ESR -+ MDMA_C28ESR -+ MDMA channel 28 error status register -+ 0x748 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C28CR -+ MDMA_C28CR -+ This register is used to control the concerned channel. -+ 0x74C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C28TCR -+ MDMA_C28TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x750 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C28BNDTR -+ MDMA_C28BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x754 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C28SAR -+ MDMA_C28SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x758 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C28DAR -+ MDMA_C28DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x75C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C28BRUR -+ MDMA_C28BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x760 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C28LAR -+ MDMA_C28LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x764 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C28TBR -+ MDMA_C28TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x768 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C28MAR -+ MDMA_C28MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x770 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C28MDR -+ MDMA_C28MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x774 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C29ISR -+ MDMA_C29ISR -+ MDMA channel 29 interrupt/status register -+ 0x780 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C29IFCR -+ MDMA_C29IFCR -+ MDMA channel 29 interrupt flag clear register -+ 0x784 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C29ESR -+ MDMA_C29ESR -+ MDMA channel 29 error status register -+ 0x788 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C29CR -+ MDMA_C29CR -+ This register is used to control the concerned channel. -+ 0x78C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C29TCR -+ MDMA_C29TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x790 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C29BNDTR -+ MDMA_C29BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x794 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C29SAR -+ MDMA_C29SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x798 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C29DAR -+ MDMA_C29DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x79C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C29BRUR -+ MDMA_C29BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x7A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C29LAR -+ MDMA_C29LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x7A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C29TBR -+ MDMA_C29TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x7A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C29MAR -+ MDMA_C29MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x7B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C29MDR -+ MDMA_C29MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x7B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C30ISR -+ MDMA_C30ISR -+ MDMA channel 30 interrupt/status register -+ 0x7C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C30IFCR -+ MDMA_C30IFCR -+ MDMA channel 30 interrupt flag clear register -+ 0x7C4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C30ESR -+ MDMA_C30ESR -+ MDMA channel 30 error status register -+ 0x7C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C30CR -+ MDMA_C30CR -+ This register is used to control the concerned channel. -+ 0x7CC -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C30TCR -+ MDMA_C30TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x7D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C30BNDTR -+ MDMA_C30BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x7D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C30SAR -+ MDMA_C30SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x7D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C30DAR -+ MDMA_C30DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x7DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C30BRUR -+ MDMA_C30BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x7E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C30LAR -+ MDMA_C30LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x7E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C30TBR -+ MDMA_C30TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x7E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C30MAR -+ MDMA_C30MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x7F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C30MDR -+ MDMA_C30MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x7F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C31ISR -+ MDMA_C31ISR -+ MDMA channel 31 interrupt/status register -+ 0x800 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEIF -+ TEIF -+ 0 -+ 1 -+ -+ -+ CTCIF -+ CTCIF -+ 1 -+ 1 -+ -+ -+ BRTIF -+ BRTIF -+ 2 -+ 1 -+ -+ -+ BTIF -+ BTIF -+ 3 -+ 1 -+ -+ -+ TCIF -+ TCIF -+ 4 -+ 1 -+ -+ -+ CRQA -+ CRQA -+ 16 -+ 1 -+ -+ -+ -+ -+ MDMA_C31IFCR -+ MDMA_C31IFCR -+ MDMA channel 31 interrupt flag clear register -+ 0x804 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CTEIF -+ CTEIF -+ 0 -+ 1 -+ -+ -+ CCTCIF -+ CCTCIF -+ 1 -+ 1 -+ -+ -+ CBRTIF -+ CBRTIF -+ 2 -+ 1 -+ -+ -+ CBTIF -+ CBTIF -+ 3 -+ 1 -+ -+ -+ CLTCIF -+ CLTCIF -+ 4 -+ 1 -+ -+ -+ -+ -+ MDMA_C31ESR -+ MDMA_C31ESR -+ MDMA channel 31 error status register -+ 0x808 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ TEA -+ TEA -+ 0 -+ 7 -+ -+ -+ TED -+ TED -+ 7 -+ 1 -+ -+ -+ TELD -+ TELD -+ 8 -+ 1 -+ -+ -+ TEMD -+ TEMD -+ 9 -+ 1 -+ -+ -+ ASE -+ ASE -+ 10 -+ 1 -+ -+ -+ BSE -+ BSE -+ 11 -+ 1 -+ -+ -+ -+ -+ MDMA_C31CR -+ MDMA_C31CR -+ This register is used to control the concerned channel. -+ 0x80C -+ 0x20 -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ TEIE -+ TEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ CTCIE -+ CTCIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BRTIE -+ BRTIE -+ 3 -+ 1 -+ read-write -+ -+ -+ BTIE -+ BTIE -+ 4 -+ 1 -+ read-write -+ -+ -+ TCIE -+ TCIE -+ 5 -+ 1 -+ read-write -+ -+ -+ PL -+ PL -+ 6 -+ 2 -+ read-write -+ -+ -+ BEX -+ BEX -+ 12 -+ 1 -+ read-write -+ -+ -+ HEX -+ HEX -+ 13 -+ 1 -+ read-write -+ -+ -+ WEX -+ WEX -+ 14 -+ 1 -+ read-write -+ -+ -+ SWRQ -+ SWRQ -+ 16 -+ 1 -+ write-only -+ -+ -+ -+ -+ MDMA_C31TCR -+ MDMA_C31TCR -+ This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). -+ 0x810 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SINC -+ SINC -+ 0 -+ 2 -+ -+ -+ DINC -+ DINC -+ 2 -+ 2 -+ -+ -+ SSIZE -+ SSIZE -+ 4 -+ 2 -+ -+ -+ DSIZE -+ DSIZE -+ 6 -+ 2 -+ -+ -+ SINCOS -+ SINCOS -+ 8 -+ 2 -+ -+ -+ DINCOS -+ DINCOS -+ 10 -+ 2 -+ -+ -+ SBURST -+ SBURST -+ 12 -+ 3 -+ -+ -+ DBURST -+ DBURST -+ 15 -+ 3 -+ -+ -+ TLEN -+ TLEN -+ 18 -+ 7 -+ -+ -+ PKE -+ PKE -+ 25 -+ 1 -+ -+ -+ PAM -+ PAM -+ 26 -+ 2 -+ -+ -+ TRGM -+ TRGM -+ 28 -+ 2 -+ -+ -+ SWRM -+ SWRM -+ 30 -+ 1 -+ -+ -+ BWM -+ BWM -+ 31 -+ 1 -+ -+ -+ -+ -+ MDMA_C31BNDTR -+ MDMA_C31BNDTR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). -+ 0x814 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BNDT -+ BNDT -+ 0 -+ 17 -+ -+ -+ BRSUM -+ BRSUM -+ 18 -+ 1 -+ -+ -+ BRDUM -+ BRDUM -+ 19 -+ 1 -+ -+ -+ BRC -+ BRC -+ 20 -+ 12 -+ -+ -+ -+ -+ MDMA_C31SAR -+ MDMA_C31SAR -+ In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). -+ 0x818 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAR -+ SAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C31DAR -+ MDMA_C31DAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M -+ 0x81C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DAR -+ DAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C31BRUR -+ MDMA_C31BRUR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). -+ 0x820 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SUV -+ SUV -+ 0 -+ 16 -+ -+ -+ DUV -+ DUV -+ 16 -+ 16 -+ -+ -+ -+ -+ MDMA_C31LAR -+ MDMA_C31LAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. -+ 0x824 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LAR -+ LAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C31TBR -+ MDMA_C31TBR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). -+ 0x828 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TSEL -+ TSEL -+ 0 -+ 6 -+ -+ -+ SBUS -+ SBUS -+ 16 -+ 1 -+ -+ -+ DBUS -+ DBUS -+ 17 -+ 1 -+ -+ -+ -+ -+ MDMA_C31MAR -+ MDMA_C31MAR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). -+ 0x830 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MAR -+ MAR -+ 0 -+ 32 -+ -+ -+ -+ -+ MDMA_C31MDR -+ MDMA_C31MDR -+ In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). -+ 0x834 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDR -+ MDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOA -+ GPIOA -+ GPIOA -+ 0x50002000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOA_MODER -+ GPIOA_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOA_OTYPER -+ GPIOA_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOA_OSPEEDR -+ GPIOA_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOA_PUPDR -+ GPIOA_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOA_IDR -+ GPIOA_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOA_ODR -+ GPIOA_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOA_BSRR -+ GPIOA_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOA_LCKR -+ GPIOA_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOA_AFRL -+ GPIOA_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOA_AFRH -+ GPIOA_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOA_BRR -+ GPIOA_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOA_HWCFGR10 -+ GPIOA_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOA_HWCFGR9 -+ GPIOA_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOA_HWCFGR8 -+ GPIOA_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOA_HWCFGR7 -+ GPIOA_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOA_HWCFGR6 -+ GPIOA_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_HWCFGR5 -+ GPIOA_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_HWCFGR4 -+ GPIOA_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_HWCFGR3 -+ GPIOA_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOA_HWCFGR2 -+ GPIOA_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_HWCFGR1 -+ GPIOA_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_HWCFGR0 -+ GPIOA_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOA_VERR -+ GPIOA_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOA_IPIDR -+ GPIOA_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOA_SIDR -+ GPIOA_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOB -+ GPIOB -+ GPIOB -+ 0x50003000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOB_MODER -+ GPIOB_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOB_OTYPER -+ GPIOB_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOB_OSPEEDR -+ GPIOB_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOB_PUPDR -+ GPIOB_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOB_IDR -+ GPIOB_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOB_ODR -+ GPIOB_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOB_BSRR -+ GPIOB_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOB_LCKR -+ GPIOB_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOB_AFRL -+ GPIOB_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOB_AFRH -+ GPIOB_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOB_BRR -+ GPIOB_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOB_HWCFGR10 -+ GPIOB_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOB_HWCFGR9 -+ GPIOB_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOB_HWCFGR8 -+ GPIOB_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOB_HWCFGR7 -+ GPIOB_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOB_HWCFGR6 -+ GPIOB_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_HWCFGR5 -+ GPIOB_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_HWCFGR4 -+ GPIOB_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_HWCFGR3 -+ GPIOB_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOB_HWCFGR2 -+ GPIOB_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_HWCFGR1 -+ GPIOB_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_HWCFGR0 -+ GPIOB_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOB_VERR -+ GPIOB_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOB_IPIDR -+ GPIOB_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOB_SIDR -+ GPIOB_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOC -+ GPIOC -+ GPIOC -+ 0x50004000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOC_MODER -+ GPIOC_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOC_OTYPER -+ GPIOC_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOC_OSPEEDR -+ GPIOC_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOC_PUPDR -+ GPIOC_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOC_IDR -+ GPIOC_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOC_ODR -+ GPIOC_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOC_BSRR -+ GPIOC_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOC_LCKR -+ GPIOC_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOC_AFRL -+ GPIOC_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOC_AFRH -+ GPIOC_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOC_BRR -+ GPIOC_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOC_HWCFGR10 -+ GPIOC_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOC_HWCFGR9 -+ GPIOC_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOC_HWCFGR8 -+ GPIOC_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOC_HWCFGR7 -+ GPIOC_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOC_HWCFGR6 -+ GPIOC_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_HWCFGR5 -+ GPIOC_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_HWCFGR4 -+ GPIOC_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_HWCFGR3 -+ GPIOC_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOC_HWCFGR2 -+ GPIOC_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_HWCFGR1 -+ GPIOC_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_HWCFGR0 -+ GPIOC_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOC_VERR -+ GPIOC_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOC_IPIDR -+ GPIOC_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOC_SIDR -+ GPIOC_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOD -+ GPIOD -+ GPIOD -+ 0x50005000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOD_MODER -+ GPIOD_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOD_OTYPER -+ GPIOD_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOD_OSPEEDR -+ GPIOD_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOD_PUPDR -+ GPIOD_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOD_IDR -+ GPIOD_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOD_ODR -+ GPIOD_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOD_BSRR -+ GPIOD_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOD_LCKR -+ GPIOD_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOD_AFRL -+ GPIOD_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOD_AFRH -+ GPIOD_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOD_BRR -+ GPIOD_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOD_HWCFGR10 -+ GPIOD_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOD_HWCFGR9 -+ GPIOD_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOD_HWCFGR8 -+ GPIOD_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOD_HWCFGR7 -+ GPIOD_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOD_HWCFGR6 -+ GPIOD_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_HWCFGR5 -+ GPIOD_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_HWCFGR4 -+ GPIOD_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_HWCFGR3 -+ GPIOD_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOD_HWCFGR2 -+ GPIOD_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_HWCFGR1 -+ GPIOD_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_HWCFGR0 -+ GPIOD_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOD_VERR -+ GPIOD_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOD_IPIDR -+ GPIOD_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOD_SIDR -+ GPIOD_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOE -+ GPIOE -+ GPIOE -+ 0x50006000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOE_MODER -+ GPIOE_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOE_OTYPER -+ GPIOE_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOE_OSPEEDR -+ GPIOE_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOE_PUPDR -+ GPIOE_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOE_IDR -+ GPIOE_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOE_ODR -+ GPIOE_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOE_BSRR -+ GPIOE_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOE_LCKR -+ GPIOE_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOE_AFRL -+ GPIOE_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOE_AFRH -+ GPIOE_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOE_BRR -+ GPIOE_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOE_HWCFGR10 -+ GPIOE_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOE_HWCFGR9 -+ GPIOE_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOE_HWCFGR8 -+ GPIOE_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOE_HWCFGR7 -+ GPIOE_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOE_HWCFGR6 -+ GPIOE_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_HWCFGR5 -+ GPIOE_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_HWCFGR4 -+ GPIOE_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_HWCFGR3 -+ GPIOE_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOE_HWCFGR2 -+ GPIOE_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_HWCFGR1 -+ GPIOE_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_HWCFGR0 -+ GPIOE_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOE_VERR -+ GPIOE_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOE_IPIDR -+ GPIOE_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOE_SIDR -+ GPIOE_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOF -+ GPIOF -+ GPIOF -+ 0x50007000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOF_MODER -+ GPIOF_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOF_OTYPER -+ GPIOF_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOF_OSPEEDR -+ GPIOF_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOF_PUPDR -+ GPIOF_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOF_IDR -+ GPIOF_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOF_ODR -+ GPIOF_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOF_BSRR -+ GPIOF_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOF_LCKR -+ GPIOF_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOF_AFRL -+ GPIOF_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOF_AFRH -+ GPIOF_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOF_BRR -+ GPIOF_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOF_HWCFGR10 -+ GPIOF_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOF_HWCFGR9 -+ GPIOF_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOF_HWCFGR8 -+ GPIOF_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOF_HWCFGR7 -+ GPIOF_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOF_HWCFGR6 -+ GPIOF_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_HWCFGR5 -+ GPIOF_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_HWCFGR4 -+ GPIOF_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_HWCFGR3 -+ GPIOF_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOF_HWCFGR2 -+ GPIOF_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_HWCFGR1 -+ GPIOF_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_HWCFGR0 -+ GPIOF_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOF_VERR -+ GPIOF_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOF_IPIDR -+ GPIOF_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOF_SIDR -+ GPIOF_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOG -+ GPIOG -+ GPIOG -+ 0x50008000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOG_MODER -+ GPIOG_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOG_OTYPER -+ GPIOG_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOG_OSPEEDR -+ GPIOG_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOG_PUPDR -+ GPIOG_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOG_IDR -+ GPIOG_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOG_ODR -+ GPIOG_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOG_BSRR -+ GPIOG_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOG_LCKR -+ GPIOG_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOG_AFRL -+ GPIOG_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOG_AFRH -+ GPIOG_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOG_BRR -+ GPIOG_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOG_HWCFGR10 -+ GPIOG_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOG_HWCFGR9 -+ GPIOG_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOG_HWCFGR8 -+ GPIOG_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOG_HWCFGR7 -+ GPIOG_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOG_HWCFGR6 -+ GPIOG_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_HWCFGR5 -+ GPIOG_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_HWCFGR4 -+ GPIOG_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_HWCFGR3 -+ GPIOG_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOG_HWCFGR2 -+ GPIOG_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_HWCFGR1 -+ GPIOG_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_HWCFGR0 -+ GPIOG_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOG_VERR -+ GPIOG_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOG_IPIDR -+ GPIOG_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOG_SIDR -+ GPIOG_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOH -+ GPIOH -+ GPIOH -+ 0x50009000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOH_MODER -+ GPIOH_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOH_OTYPER -+ GPIOH_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOH_OSPEEDR -+ GPIOH_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOH_PUPDR -+ GPIOH_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOH_IDR -+ GPIOH_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOH_ODR -+ GPIOH_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOH_BSRR -+ GPIOH_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOH_LCKR -+ GPIOH_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOH_AFRL -+ GPIOH_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOH_AFRH -+ GPIOH_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOH_BRR -+ GPIOH_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOH_HWCFGR10 -+ GPIOH_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOH_HWCFGR9 -+ GPIOH_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOH_HWCFGR8 -+ GPIOH_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOH_HWCFGR7 -+ GPIOH_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOH_HWCFGR6 -+ GPIOH_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_HWCFGR5 -+ GPIOH_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_HWCFGR4 -+ GPIOH_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_HWCFGR3 -+ GPIOH_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOH_HWCFGR2 -+ GPIOH_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_HWCFGR1 -+ GPIOH_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_HWCFGR0 -+ GPIOH_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOH_VERR -+ GPIOH_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOH_IPIDR -+ GPIOH_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOH_SIDR -+ GPIOH_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOI -+ GPIOI -+ GPIOI -+ 0x5000A000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOI_MODER -+ GPIOI_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOI_OTYPER -+ GPIOI_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOI_OSPEEDR -+ GPIOI_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOI_PUPDR -+ GPIOI_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOI_IDR -+ GPIOI_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOI_ODR -+ GPIOI_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOI_BSRR -+ GPIOI_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOI_LCKR -+ GPIOI_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOI_AFRL -+ GPIOI_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOI_AFRH -+ GPIOI_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOI_BRR -+ GPIOI_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOI_HWCFGR10 -+ GPIOI_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOI_HWCFGR9 -+ GPIOI_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOI_HWCFGR8 -+ GPIOI_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOI_HWCFGR7 -+ GPIOI_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOI_HWCFGR6 -+ GPIOI_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_HWCFGR5 -+ GPIOI_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_HWCFGR4 -+ GPIOI_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_HWCFGR3 -+ GPIOI_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOI_HWCFGR2 -+ GPIOI_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_HWCFGR1 -+ GPIOI_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_HWCFGR0 -+ GPIOI_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOI_VERR -+ GPIOI_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOI_IPIDR -+ GPIOI_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOI_SIDR -+ GPIOI_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOJ -+ GPIOJ -+ GPIOJ -+ 0x5000B000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOJ_MODER -+ GPIOJ_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOJ_OTYPER -+ GPIOJ_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOJ_OSPEEDR -+ GPIOJ_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOJ_PUPDR -+ GPIOJ_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOJ_IDR -+ GPIOJ_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOJ_ODR -+ GPIOJ_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOJ_BSRR -+ GPIOJ_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOJ_LCKR -+ GPIOJ_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOJ_AFRL -+ GPIOJ_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOJ_AFRH -+ GPIOJ_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOJ_BRR -+ GPIOJ_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOJ_HWCFGR10 -+ GPIOJ_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOJ_HWCFGR9 -+ GPIOJ_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOJ_HWCFGR8 -+ GPIOJ_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOJ_HWCFGR7 -+ GPIOJ_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOJ_HWCFGR6 -+ GPIOJ_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_HWCFGR5 -+ GPIOJ_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_HWCFGR4 -+ GPIOJ_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_HWCFGR3 -+ GPIOJ_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOJ_HWCFGR2 -+ GPIOJ_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_HWCFGR1 -+ GPIOJ_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_HWCFGR0 -+ GPIOJ_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOJ_VERR -+ GPIOJ_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOJ_IPIDR -+ GPIOJ_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOJ_SIDR -+ GPIOJ_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOK -+ GPIOK -+ GPIOK -+ 0x5000C000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOK_MODER -+ GPIOK_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOK_OTYPER -+ GPIOK_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOK_OSPEEDR -+ GPIOK_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOK_PUPDR -+ GPIOK_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOK_IDR -+ GPIOK_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOK_ODR -+ GPIOK_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOK_BSRR -+ GPIOK_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOK_LCKR -+ GPIOK_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOK_AFRL -+ GPIOK_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOK_AFRH -+ GPIOK_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOK_BRR -+ GPIOK_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOK_HWCFGR10 -+ GPIOK_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOK_HWCFGR9 -+ GPIOK_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOK_HWCFGR8 -+ GPIOK_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOK_HWCFGR7 -+ GPIOK_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOK_HWCFGR6 -+ GPIOK_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_HWCFGR5 -+ GPIOK_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_HWCFGR4 -+ GPIOK_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_HWCFGR3 -+ GPIOK_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOK_HWCFGR2 -+ GPIOK_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_HWCFGR1 -+ GPIOK_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_HWCFGR0 -+ GPIOK_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOK_VERR -+ GPIOK_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOK_IPIDR -+ GPIOK_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOK_SIDR -+ GPIOK_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ GPIOZ -+ GPIOZ -+ GPIOZ -+ 0x54004000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ GPIOZ_MODER -+ GPIOZ_MODER -+ GPIO port mode register -+ 0x0 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ MODER0 -+ MODER0 -+ 0 -+ 2 -+ -+ -+ MODER1 -+ MODER1 -+ 2 -+ 2 -+ -+ -+ MODER2 -+ MODER2 -+ 4 -+ 2 -+ -+ -+ MODER3 -+ MODER3 -+ 6 -+ 2 -+ -+ -+ MODER4 -+ MODER4 -+ 8 -+ 2 -+ -+ -+ MODER5 -+ MODER5 -+ 10 -+ 2 -+ -+ -+ MODER6 -+ MODER6 -+ 12 -+ 2 -+ -+ -+ MODER7 -+ MODER7 -+ 14 -+ 2 -+ -+ -+ MODER8 -+ MODER8 -+ 16 -+ 2 -+ -+ -+ MODER9 -+ MODER9 -+ 18 -+ 2 -+ -+ -+ MODER10 -+ MODER10 -+ 20 -+ 2 -+ -+ -+ MODER11 -+ MODER11 -+ 22 -+ 2 -+ -+ -+ MODER12 -+ MODER12 -+ 24 -+ 2 -+ -+ -+ MODER13 -+ MODER13 -+ 26 -+ 2 -+ -+ -+ MODER14 -+ MODER14 -+ 28 -+ 2 -+ -+ -+ MODER15 -+ MODER15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOZ_OTYPER -+ GPIOZ_OTYPER -+ GPIO port output type register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OT0 -+ OT0 -+ 0 -+ 1 -+ -+ -+ OT1 -+ OT1 -+ 1 -+ 1 -+ -+ -+ OT2 -+ OT2 -+ 2 -+ 1 -+ -+ -+ OT3 -+ OT3 -+ 3 -+ 1 -+ -+ -+ OT4 -+ OT4 -+ 4 -+ 1 -+ -+ -+ OT5 -+ OT5 -+ 5 -+ 1 -+ -+ -+ OT6 -+ OT6 -+ 6 -+ 1 -+ -+ -+ OT7 -+ OT7 -+ 7 -+ 1 -+ -+ -+ OT8 -+ OT8 -+ 8 -+ 1 -+ -+ -+ OT9 -+ OT9 -+ 9 -+ 1 -+ -+ -+ OT10 -+ OT10 -+ 10 -+ 1 -+ -+ -+ OT11 -+ OT11 -+ 11 -+ 1 -+ -+ -+ OT12 -+ OT12 -+ 12 -+ 1 -+ -+ -+ OT13 -+ OT13 -+ 13 -+ 1 -+ -+ -+ OT14 -+ OT14 -+ 14 -+ 1 -+ -+ -+ OT15 -+ OT15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOZ_OSPEEDR -+ GPIOZ_OSPEEDR -+ GPIO port output speed register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OSPEEDR0 -+ OSPEEDR0 -+ 0 -+ 2 -+ -+ -+ OSPEEDR1 -+ OSPEEDR1 -+ 2 -+ 2 -+ -+ -+ OSPEEDR2 -+ OSPEEDR2 -+ 4 -+ 2 -+ -+ -+ OSPEEDR3 -+ OSPEEDR3 -+ 6 -+ 2 -+ -+ -+ OSPEEDR4 -+ OSPEEDR4 -+ 8 -+ 2 -+ -+ -+ OSPEEDR5 -+ OSPEEDR5 -+ 10 -+ 2 -+ -+ -+ OSPEEDR6 -+ OSPEEDR6 -+ 12 -+ 2 -+ -+ -+ OSPEEDR7 -+ OSPEEDR7 -+ 14 -+ 2 -+ -+ -+ OSPEEDR8 -+ OSPEEDR8 -+ 16 -+ 2 -+ -+ -+ OSPEEDR9 -+ OSPEEDR9 -+ 18 -+ 2 -+ -+ -+ OSPEEDR10 -+ OSPEEDR10 -+ 20 -+ 2 -+ -+ -+ OSPEEDR11 -+ OSPEEDR11 -+ 22 -+ 2 -+ -+ -+ OSPEEDR12 -+ OSPEEDR12 -+ 24 -+ 2 -+ -+ -+ OSPEEDR13 -+ OSPEEDR13 -+ 26 -+ 2 -+ -+ -+ OSPEEDR14 -+ OSPEEDR14 -+ 28 -+ 2 -+ -+ -+ OSPEEDR15 -+ OSPEEDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOZ_PUPDR -+ GPIOZ_PUPDR -+ GPIO port pull-up/pull-down register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PUPDR0 -+ PUPDR0 -+ 0 -+ 2 -+ -+ -+ PUPDR1 -+ PUPDR1 -+ 2 -+ 2 -+ -+ -+ PUPDR2 -+ PUPDR2 -+ 4 -+ 2 -+ -+ -+ PUPDR3 -+ PUPDR3 -+ 6 -+ 2 -+ -+ -+ PUPDR4 -+ PUPDR4 -+ 8 -+ 2 -+ -+ -+ PUPDR5 -+ PUPDR5 -+ 10 -+ 2 -+ -+ -+ PUPDR6 -+ PUPDR6 -+ 12 -+ 2 -+ -+ -+ PUPDR7 -+ PUPDR7 -+ 14 -+ 2 -+ -+ -+ PUPDR8 -+ PUPDR8 -+ 16 -+ 2 -+ -+ -+ PUPDR9 -+ PUPDR9 -+ 18 -+ 2 -+ -+ -+ PUPDR10 -+ PUPDR10 -+ 20 -+ 2 -+ -+ -+ PUPDR11 -+ PUPDR11 -+ 22 -+ 2 -+ -+ -+ PUPDR12 -+ PUPDR12 -+ 24 -+ 2 -+ -+ -+ PUPDR13 -+ PUPDR13 -+ 26 -+ 2 -+ -+ -+ PUPDR14 -+ PUPDR14 -+ 28 -+ 2 -+ -+ -+ PUPDR15 -+ PUPDR15 -+ 30 -+ 2 -+ -+ -+ -+ -+ GPIOZ_IDR -+ GPIOZ_IDR -+ GPIO port input data register -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IDR0 -+ IDR0 -+ 0 -+ 1 -+ -+ -+ IDR1 -+ IDR1 -+ 1 -+ 1 -+ -+ -+ IDR2 -+ IDR2 -+ 2 -+ 1 -+ -+ -+ IDR3 -+ IDR3 -+ 3 -+ 1 -+ -+ -+ IDR4 -+ IDR4 -+ 4 -+ 1 -+ -+ -+ IDR5 -+ IDR5 -+ 5 -+ 1 -+ -+ -+ IDR6 -+ IDR6 -+ 6 -+ 1 -+ -+ -+ IDR7 -+ IDR7 -+ 7 -+ 1 -+ -+ -+ IDR8 -+ IDR8 -+ 8 -+ 1 -+ -+ -+ IDR9 -+ IDR9 -+ 9 -+ 1 -+ -+ -+ IDR10 -+ IDR10 -+ 10 -+ 1 -+ -+ -+ IDR11 -+ IDR11 -+ 11 -+ 1 -+ -+ -+ IDR12 -+ IDR12 -+ 12 -+ 1 -+ -+ -+ IDR13 -+ IDR13 -+ 13 -+ 1 -+ -+ -+ IDR14 -+ IDR14 -+ 14 -+ 1 -+ -+ -+ IDR15 -+ IDR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOZ_ODR -+ GPIOZ_ODR -+ GPIO port output data register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ODR0 -+ ODR0 -+ 0 -+ 1 -+ -+ -+ ODR1 -+ ODR1 -+ 1 -+ 1 -+ -+ -+ ODR2 -+ ODR2 -+ 2 -+ 1 -+ -+ -+ ODR3 -+ ODR3 -+ 3 -+ 1 -+ -+ -+ ODR4 -+ ODR4 -+ 4 -+ 1 -+ -+ -+ ODR5 -+ ODR5 -+ 5 -+ 1 -+ -+ -+ ODR6 -+ ODR6 -+ 6 -+ 1 -+ -+ -+ ODR7 -+ ODR7 -+ 7 -+ 1 -+ -+ -+ ODR8 -+ ODR8 -+ 8 -+ 1 -+ -+ -+ ODR9 -+ ODR9 -+ 9 -+ 1 -+ -+ -+ ODR10 -+ ODR10 -+ 10 -+ 1 -+ -+ -+ ODR11 -+ ODR11 -+ 11 -+ 1 -+ -+ -+ ODR12 -+ ODR12 -+ 12 -+ 1 -+ -+ -+ ODR13 -+ ODR13 -+ 13 -+ 1 -+ -+ -+ ODR14 -+ ODR14 -+ 14 -+ 1 -+ -+ -+ ODR15 -+ ODR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOZ_BSRR -+ GPIOZ_BSRR -+ GPIO port bit set/reset register -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BS0 -+ BS0 -+ 0 -+ 1 -+ -+ -+ BS1 -+ BS1 -+ 1 -+ 1 -+ -+ -+ BS2 -+ BS2 -+ 2 -+ 1 -+ -+ -+ BS3 -+ BS3 -+ 3 -+ 1 -+ -+ -+ BS4 -+ BS4 -+ 4 -+ 1 -+ -+ -+ BS5 -+ BS5 -+ 5 -+ 1 -+ -+ -+ BS6 -+ BS6 -+ 6 -+ 1 -+ -+ -+ BS7 -+ BS7 -+ 7 -+ 1 -+ -+ -+ BS8 -+ BS8 -+ 8 -+ 1 -+ -+ -+ BS9 -+ BS9 -+ 9 -+ 1 -+ -+ -+ BS10 -+ BS10 -+ 10 -+ 1 -+ -+ -+ BS11 -+ BS11 -+ 11 -+ 1 -+ -+ -+ BS12 -+ BS12 -+ 12 -+ 1 -+ -+ -+ BS13 -+ BS13 -+ 13 -+ 1 -+ -+ -+ BS14 -+ BS14 -+ 14 -+ 1 -+ -+ -+ BS15 -+ BS15 -+ 15 -+ 1 -+ -+ -+ BR0 -+ BR0 -+ 16 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 17 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 18 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 19 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 20 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 21 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 22 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 23 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 24 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 25 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 26 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 27 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 28 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 29 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 30 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 31 -+ 1 -+ -+ -+ -+ -+ GPIOZ_LCKR -+ GPIOZ_LCKR -+ This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LCK0 -+ LCK0 -+ 0 -+ 1 -+ -+ -+ LCK1 -+ LCK1 -+ 1 -+ 1 -+ -+ -+ LCK2 -+ LCK2 -+ 2 -+ 1 -+ -+ -+ LCK3 -+ LCK3 -+ 3 -+ 1 -+ -+ -+ LCK4 -+ LCK4 -+ 4 -+ 1 -+ -+ -+ LCK5 -+ LCK5 -+ 5 -+ 1 -+ -+ -+ LCK6 -+ LCK6 -+ 6 -+ 1 -+ -+ -+ LCK7 -+ LCK7 -+ 7 -+ 1 -+ -+ -+ LCK8 -+ LCK8 -+ 8 -+ 1 -+ -+ -+ LCK9 -+ LCK9 -+ 9 -+ 1 -+ -+ -+ LCK10 -+ LCK10 -+ 10 -+ 1 -+ -+ -+ LCK11 -+ LCK11 -+ 11 -+ 1 -+ -+ -+ LCK12 -+ LCK12 -+ 12 -+ 1 -+ -+ -+ LCK13 -+ LCK13 -+ 13 -+ 1 -+ -+ -+ LCK14 -+ LCK14 -+ 14 -+ 1 -+ -+ -+ LCK15 -+ LCK15 -+ 15 -+ 1 -+ -+ -+ LCKK -+ LCKK -+ 16 -+ 1 -+ -+ -+ -+ -+ GPIOZ_AFRL -+ GPIOZ_AFRL -+ GPIO alternate function low register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR0 -+ AFR0 -+ 0 -+ 4 -+ -+ -+ AFR1 -+ AFR1 -+ 4 -+ 4 -+ -+ -+ AFR2 -+ AFR2 -+ 8 -+ 4 -+ -+ -+ AFR3 -+ AFR3 -+ 12 -+ 4 -+ -+ -+ AFR4 -+ AFR4 -+ 16 -+ 4 -+ -+ -+ AFR5 -+ AFR5 -+ 20 -+ 4 -+ -+ -+ AFR6 -+ AFR6 -+ 24 -+ 4 -+ -+ -+ AFR7 -+ AFR7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOZ_AFRH -+ GPIOZ_AFRH -+ GPIO alternate function high register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AFR8 -+ AFR8 -+ 0 -+ 4 -+ -+ -+ AFR9 -+ AFR9 -+ 4 -+ 4 -+ -+ -+ AFR10 -+ AFR10 -+ 8 -+ 4 -+ -+ -+ AFR11 -+ AFR11 -+ 12 -+ 4 -+ -+ -+ AFR12 -+ AFR12 -+ 16 -+ 4 -+ -+ -+ AFR13 -+ AFR13 -+ 20 -+ 4 -+ -+ -+ AFR14 -+ AFR14 -+ 24 -+ 4 -+ -+ -+ AFR15 -+ AFR15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOZ_BRR -+ GPIOZ_BRR -+ GPIO port bit reset register -+ 0x28 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ BR0 -+ BR0 -+ 0 -+ 1 -+ -+ -+ BR1 -+ BR1 -+ 1 -+ 1 -+ -+ -+ BR2 -+ BR2 -+ 2 -+ 1 -+ -+ -+ BR3 -+ BR3 -+ 3 -+ 1 -+ -+ -+ BR4 -+ BR4 -+ 4 -+ 1 -+ -+ -+ BR5 -+ BR5 -+ 5 -+ 1 -+ -+ -+ BR6 -+ BR6 -+ 6 -+ 1 -+ -+ -+ BR7 -+ BR7 -+ 7 -+ 1 -+ -+ -+ BR8 -+ BR8 -+ 8 -+ 1 -+ -+ -+ BR9 -+ BR9 -+ 9 -+ 1 -+ -+ -+ BR10 -+ BR10 -+ 10 -+ 1 -+ -+ -+ BR11 -+ BR11 -+ 11 -+ 1 -+ -+ -+ BR12 -+ BR12 -+ 12 -+ 1 -+ -+ -+ BR13 -+ BR13 -+ 13 -+ 1 -+ -+ -+ BR14 -+ BR14 -+ 14 -+ 1 -+ -+ -+ BR15 -+ BR15 -+ 15 -+ 1 -+ -+ -+ -+ -+ GPIOZ_SECCFGR -+ GPIOZ_SECCFGR -+ This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded. -+ 0x30 -+ 0x20 -+ write-only -+ 0x000000FF -+ -+ -+ SEC0 -+ SEC0 -+ 0 -+ 1 -+ -+ -+ SEC1 -+ SEC1 -+ 1 -+ 1 -+ -+ -+ SEC2 -+ SEC2 -+ 2 -+ 1 -+ -+ -+ SEC3 -+ SEC3 -+ 3 -+ 1 -+ -+ -+ SEC4 -+ SEC4 -+ 4 -+ 1 -+ -+ -+ SEC5 -+ SEC5 -+ 5 -+ 1 -+ -+ -+ SEC6 -+ SEC6 -+ 6 -+ 1 -+ -+ -+ SEC7 -+ SEC7 -+ 7 -+ 1 -+ -+ -+ -+ -+ GPIOZ_HWCFGR10 -+ GPIOZ_HWCFGR10 -+ For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: -+ 0x3C8 -+ 0x20 -+ read-only -+ 0x00011240 -+ -+ -+ AHB_IOP -+ AHB_IOP -+ 0 -+ 4 -+ -+ -+ AF_SIZE -+ AF_SIZE -+ 4 -+ 4 -+ -+ -+ SPEED_CFG -+ SPEED_CFG -+ 8 -+ 4 -+ -+ -+ LOCK_CFG -+ LOCK_CFG -+ 12 -+ 4 -+ -+ -+ SEC_CFG -+ SEC_CFG -+ 16 -+ 4 -+ -+ -+ OR_CFG -+ OR_CFG -+ 20 -+ 4 -+ -+ -+ -+ -+ GPIOZ_HWCFGR9 -+ GPIOZ_HWCFGR9 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3CC -+ 0x20 -+ read-only -+ 0x000000FF -+ -+ -+ EN_IO -+ EN_IO -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOZ_HWCFGR8 -+ GPIOZ_HWCFGR8 -+ For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: -+ 0x3D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AF_PRIO8 -+ AF_PRIO8 -+ 0 -+ 4 -+ -+ -+ AF_PRIO9 -+ AF_PRIO9 -+ 4 -+ 4 -+ -+ -+ AF_PRIO10 -+ AF_PRIO10 -+ 8 -+ 4 -+ -+ -+ AF_PRIO11 -+ AF_PRIO11 -+ 12 -+ 4 -+ -+ -+ AF_PRIO12 -+ AF_PRIO12 -+ 16 -+ 4 -+ -+ -+ AF_PRIO13 -+ AF_PRIO13 -+ 20 -+ 4 -+ -+ -+ AF_PRIO14 -+ AF_PRIO14 -+ 24 -+ 4 -+ -+ -+ AF_PRIO15 -+ AF_PRIO15 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOZ_HWCFGR7 -+ GPIOZ_HWCFGR7 -+ GPIO hardware configuration register 7 -+ 0x3D4 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ AF_PRIO0 -+ AF_PRIO0 -+ 0 -+ 4 -+ -+ -+ AF_PRIO1 -+ AF_PRIO1 -+ 4 -+ 4 -+ -+ -+ AF_PRIO2 -+ AF_PRIO2 -+ 8 -+ 4 -+ -+ -+ AF_PRIO3 -+ AF_PRIO3 -+ 12 -+ 4 -+ -+ -+ AF_PRIO4 -+ AF_PRIO4 -+ 16 -+ 4 -+ -+ -+ AF_PRIO5 -+ AF_PRIO5 -+ 20 -+ 4 -+ -+ -+ AF_PRIO6 -+ AF_PRIO6 -+ 24 -+ 4 -+ -+ -+ AF_PRIO7 -+ AF_PRIO7 -+ 28 -+ 4 -+ -+ -+ -+ -+ GPIOZ_HWCFGR6 -+ GPIOZ_HWCFGR6 -+ GPIO hardware configuration register 6 -+ 0x3D8 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ MODER_RES -+ MODER_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_HWCFGR5 -+ GPIOZ_HWCFGR5 -+ GPIO hardware configuration register 5 -+ 0x3DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PUPDR_RES -+ PUPDR_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_HWCFGR4 -+ GPIOZ_HWCFGR4 -+ GPIO hardware configuration register 4 -+ 0x3E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OSPEED_RES -+ OSPEED_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_HWCFGR3 -+ GPIOZ_HWCFGR3 -+ GPIO hardware configuration register 3 -+ 0x3E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ODR_RES -+ ODR_RES -+ 0 -+ 16 -+ -+ -+ OTYPER_RES -+ OTYPER_RES -+ 16 -+ 16 -+ -+ -+ -+ -+ GPIOZ_HWCFGR2 -+ GPIOZ_HWCFGR2 -+ GPIO hardware configuration register 2 -+ 0x3E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRL_RES -+ AFRL_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_HWCFGR1 -+ GPIOZ_HWCFGR1 -+ GPIO hardware configuration register 1 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ AFRH_RES -+ AFRH_RES -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_HWCFGR0 -+ GPIOZ_HWCFGR0 -+ GPIO hardware configuration register 0 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ OR_RES -+ OR_RES -+ 0 -+ 16 -+ -+ -+ -+ -+ GPIOZ_VERR -+ GPIOZ_VERR -+ GPIO version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000040 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ GPIOZ_IPIDR -+ GPIOZ_IPIDR -+ GPIO identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x000F0002 -+ -+ -+ IPIDR -+ IPIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ GPIOZ_SIDR -+ GPIOZ_SIDR -+ GPIO size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SIDR -+ SIDR -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ RNG1 -+ RNG1 -+ RNG1 -+ 0x54003000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ RNG_CR -+ RNG_CR -+ RNG control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RNGEN -+ RNGEN -+ 2 -+ 1 -+ -+ -+ IE -+ IE -+ 3 -+ 1 -+ -+ -+ CED -+ CED -+ 5 -+ 1 -+ -+ -+ -+ -+ RNG_SR -+ RNG_SR -+ RNG status register -+ 0x4 -+ 0x20 -+ 0x00000000 -+ -+ -+ DRDY -+ DRDY -+ 0 -+ 1 -+ read-only -+ -+ -+ CECS -+ CECS -+ 1 -+ 1 -+ read-only -+ -+ -+ SECS -+ SECS -+ 2 -+ 1 -+ read-only -+ -+ -+ CEIS -+ CEIS -+ 5 -+ 1 -+ read-write -+ -+ -+ SEIS -+ SEIS -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RNG_DR -+ RNG_DR -+ The RNG_DR register is a read-only register. -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RNDATA -+ RNDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ RNG_HWCFGR -+ RNG_HWCFGR -+ RNG hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000006 -+ -+ -+ RNG_VERR -+ RNG_VERR -+ RNG version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ RNG_IPIDR -+ RNG_IPIDR -+ RNG identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00170041 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ RNG_SIDR -+ RNG_SIDR -+ RNG size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ RNG2 -+ RNG2 -+ RNG2 -+ 0x4C003000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ RNG_CR -+ RNG_CR -+ RNG control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RNGEN -+ RNGEN -+ 2 -+ 1 -+ -+ -+ IE -+ IE -+ 3 -+ 1 -+ -+ -+ CED -+ CED -+ 5 -+ 1 -+ -+ -+ -+ -+ RNG_SR -+ RNG_SR -+ RNG status register -+ 0x4 -+ 0x20 -+ 0x00000000 -+ -+ -+ DRDY -+ DRDY -+ 0 -+ 1 -+ read-only -+ -+ -+ CECS -+ CECS -+ 1 -+ 1 -+ read-only -+ -+ -+ SECS -+ SECS -+ 2 -+ 1 -+ read-only -+ -+ -+ CEIS -+ CEIS -+ 5 -+ 1 -+ read-write -+ -+ -+ SEIS -+ SEIS -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RNG_DR -+ RNG_DR -+ The RNG_DR register is a read-only register. -+ 0x8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RNDATA -+ RNDATA -+ 0 -+ 32 -+ -+ -+ -+ -+ RNG_HWCFGR -+ RNG_HWCFGR -+ RNG hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000006 -+ -+ -+ RNG_VERR -+ RNG_VERR -+ RNG version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ RNG_IPIDR -+ RNG_IPIDR -+ RNG identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00170041 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ RNG_SIDR -+ RNG_SIDR -+ RNG size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ HASH1 -+ HASH register block -+ HASH -+ 0x54002000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ HASH_CR -+ HASH_CR -+ HASH control register -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ INIT -+ INIT -+ 2 -+ 1 -+ write-only -+ -+ -+ DMAE -+ DMAE -+ 3 -+ 1 -+ read-write -+ -+ -+ DATATYPE -+ DATATYPE -+ 4 -+ 2 -+ read-write -+ -+ -+ MODE -+ MODE -+ 6 -+ 1 -+ read-write -+ -+ -+ ALGO0 -+ ALGO0 -+ 7 -+ 1 -+ read-write -+ -+ -+ NBW -+ NBW -+ 8 -+ 4 -+ read-only -+ -+ -+ DINNE -+ DINNE -+ 12 -+ 1 -+ read-only -+ -+ -+ MDMAT -+ MDMAT -+ 13 -+ 1 -+ read-write -+ -+ -+ DMAA -+ DMAA -+ 14 -+ 1 -+ write-only -+ -+ -+ LKEY -+ LKEY -+ 16 -+ 1 -+ read-write -+ -+ -+ ALGO1 -+ ALGO1 -+ 18 -+ 1 -+ read-write -+ -+ -+ -+ -+ HASH_DIN -+ HASH_DIN -+ HASH_DIN is the data input register. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATAIN -+ DATAIN -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_STR -+ HASH_STR -+ The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 -+ 0x8 -+ 0x20 -+ 0x00000000 -+ -+ -+ NBLW -+ NBLW -+ 0 -+ 5 -+ read-write -+ -+ -+ DCAL -+ DCAL -+ 8 -+ 1 -+ write-only -+ -+ -+ -+ -+ HASH_HR0 -+ HASH_HR0 -+ HASH digest register 0 -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H0 -+ H0 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR1 -+ HASH_HR1 -+ HASH digest register 1 -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H1 -+ H1 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR2 -+ HASH_HR2 -+ HASH digest register 2 -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H2 -+ H2 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR3 -+ HASH_HR3 -+ HASH digest register 3 -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H3 -+ H3 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR4 -+ HASH_HR4 -+ HASH digest register 4 -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H4 -+ H4 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_IMR -+ HASH_IMR -+ HASH interrupt enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DINIE -+ DINIE -+ 0 -+ 1 -+ -+ -+ DCIE -+ DCIE -+ 1 -+ 1 -+ -+ -+ -+ -+ HASH_SR -+ HASH_SR -+ HASH status register -+ 0x24 -+ 0x20 -+ 0x00000001 -+ -+ -+ DINIS -+ DINIS -+ 0 -+ 1 -+ read-write -+ -+ -+ DCIS -+ DCIS -+ 1 -+ 1 -+ read-write -+ -+ -+ DMAS -+ DMAS -+ 2 -+ 1 -+ read-only -+ -+ -+ BUSY -+ BUSY -+ 3 -+ 1 -+ read-only -+ -+ -+ -+ -+ HASH_CSR0 -+ HASH_CSR0 -+ These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. -+ 0xF8 -+ 0x20 -+ read-write -+ 0x00000002 -+ -+ -+ CS0 -+ CS0 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR1 -+ HASH_CSR1 -+ HASH context swap registers -+ 0xFC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS1 -+ CS1 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR2 -+ HASH_CSR2 -+ HASH context swap registers -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS2 -+ CS2 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR3 -+ HASH_CSR3 -+ HASH context swap registers -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS3 -+ CS3 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR4 -+ HASH_CSR4 -+ HASH context swap registers -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS4 -+ CS4 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR5 -+ HASH_CSR5 -+ HASH context swap registers -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS5 -+ CS5 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR6 -+ HASH_CSR6 -+ HASH context swap registers -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS6 -+ CS6 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR7 -+ HASH_CSR7 -+ HASH context swap registers -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS7 -+ CS7 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR8 -+ HASH_CSR8 -+ HASH context swap registers -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS8 -+ CS8 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR9 -+ HASH_CSR9 -+ HASH context swap registers -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS9 -+ CS9 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR10 -+ HASH_CSR10 -+ HASH context swap registers -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS10 -+ CS10 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR11 -+ HASH_CSR11 -+ HASH context swap registers -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS11 -+ CS11 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR12 -+ HASH_CSR12 -+ HASH context swap registers -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS12 -+ CS12 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR13 -+ HASH_CSR13 -+ HASH context swap registers -+ 0x12C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS13 -+ CS13 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR14 -+ HASH_CSR14 -+ HASH context swap registers -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS14 -+ CS14 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR15 -+ HASH_CSR15 -+ HASH context swap registers -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS15 -+ CS15 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR16 -+ HASH_CSR16 -+ HASH context swap registers -+ 0x138 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS16 -+ CS16 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR17 -+ HASH_CSR17 -+ HASH context swap registers -+ 0x13C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS17 -+ CS17 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR18 -+ HASH_CSR18 -+ HASH context swap registers -+ 0x140 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS18 -+ CS18 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR19 -+ HASH_CSR19 -+ HASH context swap registers -+ 0x144 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS19 -+ CS19 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR20 -+ HASH_CSR20 -+ HASH context swap registers -+ 0x148 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS20 -+ CS20 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR21 -+ HASH_CSR21 -+ HASH context swap registers -+ 0x14C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS21 -+ CS21 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR22 -+ HASH_CSR22 -+ HASH context swap registers -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS22 -+ CS22 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR23 -+ HASH_CSR23 -+ HASH context swap registers -+ 0x154 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS23 -+ CS23 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR24 -+ HASH_CSR24 -+ HASH context swap registers -+ 0x158 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS24 -+ CS24 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR25 -+ HASH_CSR25 -+ HASH context swap registers -+ 0x15C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS25 -+ CS25 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR26 -+ HASH_CSR26 -+ HASH context swap registers -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS26 -+ CS26 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR27 -+ HASH_CSR27 -+ HASH context swap registers -+ 0x164 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS27 -+ CS27 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR28 -+ HASH_CSR28 -+ HASH context swap registers -+ 0x168 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS28 -+ CS28 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR29 -+ HASH_CSR29 -+ HASH context swap registers -+ 0x16C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS29 -+ CS29 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR30 -+ HASH_CSR30 -+ HASH context swap registers -+ 0x170 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS30 -+ CS30 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR31 -+ HASH_CSR31 -+ HASH context swap registers -+ 0x174 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS31 -+ CS31 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR32 -+ HASH_CSR32 -+ HASH context swap registers -+ 0x178 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS32 -+ CS32 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR33 -+ HASH_CSR33 -+ HASH context swap registers -+ 0x17C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS33 -+ CS33 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR34 -+ HASH_CSR34 -+ HASH context swap registers -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS34 -+ CS34 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR35 -+ HASH_CSR35 -+ HASH context swap registers -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS35 -+ CS35 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR36 -+ HASH_CSR36 -+ HASH context swap registers -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS36 -+ CS36 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR37 -+ HASH_CSR37 -+ HASH context swap registers -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS37 -+ CS37 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR38 -+ HASH_CSR38 -+ HASH context swap registers -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS38 -+ CS38 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR39 -+ HASH_CSR39 -+ HASH context swap registers -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS39 -+ CS39 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR40 -+ HASH_CSR40 -+ HASH context swap registers -+ 0x198 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS40 -+ CS40 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR41 -+ HASH_CSR41 -+ HASH context swap registers -+ 0x19C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS41 -+ CS41 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR42 -+ HASH_CSR42 -+ HASH context swap registers -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS42 -+ CS42 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR43 -+ HASH_CSR43 -+ HASH context swap registers -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS43 -+ CS43 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR44 -+ HASH_CSR44 -+ HASH context swap registers -+ 0x1A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS44 -+ CS44 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR45 -+ HASH_CSR45 -+ HASH context swap registers -+ 0x1AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS45 -+ CS45 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR46 -+ HASH_CSR46 -+ HASH context swap registers -+ 0x1B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS46 -+ CS46 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR47 -+ HASH_CSR47 -+ HASH context swap registers -+ 0x1B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS47 -+ CS47 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR48 -+ HASH_CSR48 -+ HASH context swap registers -+ 0x1B8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS48 -+ CS48 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR49 -+ HASH_CSR49 -+ HASH context swap registers -+ 0x1BC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS49 -+ CS49 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR50 -+ HASH_CSR50 -+ HASH context swap registers -+ 0x1C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS50 -+ CS50 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR51 -+ HASH_CSR51 -+ HASH context swap registers -+ 0x1C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS51 -+ CS51 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR52 -+ HASH_CSR52 -+ HASH context swap registers -+ 0x1C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS52 -+ CS52 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR53 -+ HASH_CSR53 -+ HASH context swap registers -+ 0x1CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS53 -+ CS53 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR5 -+ HASH_HR5 -+ HASH digest register 5 -+ 0x324 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H5 -+ H5 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR6 -+ HASH_HR6 -+ HASH digest register 6 -+ 0x328 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H6 -+ H6 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR7 -+ HASH_HR7 -+ HASH digest register 7 -+ 0x32C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H7 -+ H7 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HWCFGR -+ HASH_HWCFGR -+ HASH Hardware Configuration Register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 4 -+ -+ -+ -+ -+ HASH_VERR -+ HASH_VERR -+ HASH Version Register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000023 -+ -+ -+ VER -+ VER -+ 0 -+ 8 -+ -+ -+ -+ -+ HASH_IPIDR -+ HASH_IPIDR -+ HASH Identification -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00170031 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_MID -+ HASH_MID -+ HASH Hardware Magic ID -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ MID -+ MID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ HASH2 -+ HASH register block -+ HASH -+ 0x4C002000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ HASH_CR -+ HASH_CR -+ HASH control register -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ INIT -+ INIT -+ 2 -+ 1 -+ write-only -+ -+ -+ DMAE -+ DMAE -+ 3 -+ 1 -+ read-write -+ -+ -+ DATATYPE -+ DATATYPE -+ 4 -+ 2 -+ read-write -+ -+ -+ MODE -+ MODE -+ 6 -+ 1 -+ read-write -+ -+ -+ ALGO0 -+ ALGO0 -+ 7 -+ 1 -+ read-write -+ -+ -+ NBW -+ NBW -+ 8 -+ 4 -+ read-only -+ -+ -+ DINNE -+ DINNE -+ 12 -+ 1 -+ read-only -+ -+ -+ MDMAT -+ MDMAT -+ 13 -+ 1 -+ read-write -+ -+ -+ DMAA -+ DMAA -+ 14 -+ 1 -+ write-only -+ -+ -+ LKEY -+ LKEY -+ 16 -+ 1 -+ read-write -+ -+ -+ ALGO1 -+ ALGO1 -+ 18 -+ 1 -+ read-write -+ -+ -+ -+ -+ HASH_DIN -+ HASH_DIN -+ HASH_DIN is the data input register. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATAIN -+ DATAIN -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_STR -+ HASH_STR -+ The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 -+ 0x8 -+ 0x20 -+ 0x00000000 -+ -+ -+ NBLW -+ NBLW -+ 0 -+ 5 -+ read-write -+ -+ -+ DCAL -+ DCAL -+ 8 -+ 1 -+ write-only -+ -+ -+ -+ -+ HASH_HR0 -+ HASH_HR0 -+ HASH digest register 0 -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H0 -+ H0 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR1 -+ HASH_HR1 -+ HASH digest register 1 -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H1 -+ H1 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR2 -+ HASH_HR2 -+ HASH digest register 2 -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H2 -+ H2 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR3 -+ HASH_HR3 -+ HASH digest register 3 -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H3 -+ H3 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR4 -+ HASH_HR4 -+ HASH digest register 4 -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H4 -+ H4 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_IMR -+ HASH_IMR -+ HASH interrupt enable register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DINIE -+ DINIE -+ 0 -+ 1 -+ -+ -+ DCIE -+ DCIE -+ 1 -+ 1 -+ -+ -+ -+ -+ HASH_SR -+ HASH_SR -+ HASH status register -+ 0x24 -+ 0x20 -+ 0x00000001 -+ -+ -+ DINIS -+ DINIS -+ 0 -+ 1 -+ read-write -+ -+ -+ DCIS -+ DCIS -+ 1 -+ 1 -+ read-write -+ -+ -+ DMAS -+ DMAS -+ 2 -+ 1 -+ read-only -+ -+ -+ BUSY -+ BUSY -+ 3 -+ 1 -+ read-only -+ -+ -+ -+ -+ HASH_CSR0 -+ HASH_CSR0 -+ These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. -+ 0xF8 -+ 0x20 -+ read-write -+ 0x00000002 -+ -+ -+ CS0 -+ CS0 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR1 -+ HASH_CSR1 -+ HASH context swap registers -+ 0xFC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS1 -+ CS1 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR2 -+ HASH_CSR2 -+ HASH context swap registers -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS2 -+ CS2 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR3 -+ HASH_CSR3 -+ HASH context swap registers -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS3 -+ CS3 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR4 -+ HASH_CSR4 -+ HASH context swap registers -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS4 -+ CS4 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR5 -+ HASH_CSR5 -+ HASH context swap registers -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS5 -+ CS5 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR6 -+ HASH_CSR6 -+ HASH context swap registers -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS6 -+ CS6 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR7 -+ HASH_CSR7 -+ HASH context swap registers -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS7 -+ CS7 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR8 -+ HASH_CSR8 -+ HASH context swap registers -+ 0x118 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS8 -+ CS8 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR9 -+ HASH_CSR9 -+ HASH context swap registers -+ 0x11C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS9 -+ CS9 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR10 -+ HASH_CSR10 -+ HASH context swap registers -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS10 -+ CS10 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR11 -+ HASH_CSR11 -+ HASH context swap registers -+ 0x124 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS11 -+ CS11 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR12 -+ HASH_CSR12 -+ HASH context swap registers -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS12 -+ CS12 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR13 -+ HASH_CSR13 -+ HASH context swap registers -+ 0x12C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS13 -+ CS13 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR14 -+ HASH_CSR14 -+ HASH context swap registers -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS14 -+ CS14 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR15 -+ HASH_CSR15 -+ HASH context swap registers -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS15 -+ CS15 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR16 -+ HASH_CSR16 -+ HASH context swap registers -+ 0x138 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS16 -+ CS16 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR17 -+ HASH_CSR17 -+ HASH context swap registers -+ 0x13C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS17 -+ CS17 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR18 -+ HASH_CSR18 -+ HASH context swap registers -+ 0x140 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS18 -+ CS18 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR19 -+ HASH_CSR19 -+ HASH context swap registers -+ 0x144 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS19 -+ CS19 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR20 -+ HASH_CSR20 -+ HASH context swap registers -+ 0x148 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS20 -+ CS20 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR21 -+ HASH_CSR21 -+ HASH context swap registers -+ 0x14C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS21 -+ CS21 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR22 -+ HASH_CSR22 -+ HASH context swap registers -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS22 -+ CS22 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR23 -+ HASH_CSR23 -+ HASH context swap registers -+ 0x154 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS23 -+ CS23 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR24 -+ HASH_CSR24 -+ HASH context swap registers -+ 0x158 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS24 -+ CS24 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR25 -+ HASH_CSR25 -+ HASH context swap registers -+ 0x15C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS25 -+ CS25 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR26 -+ HASH_CSR26 -+ HASH context swap registers -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS26 -+ CS26 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR27 -+ HASH_CSR27 -+ HASH context swap registers -+ 0x164 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS27 -+ CS27 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR28 -+ HASH_CSR28 -+ HASH context swap registers -+ 0x168 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS28 -+ CS28 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR29 -+ HASH_CSR29 -+ HASH context swap registers -+ 0x16C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS29 -+ CS29 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR30 -+ HASH_CSR30 -+ HASH context swap registers -+ 0x170 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS30 -+ CS30 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR31 -+ HASH_CSR31 -+ HASH context swap registers -+ 0x174 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS31 -+ CS31 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR32 -+ HASH_CSR32 -+ HASH context swap registers -+ 0x178 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS32 -+ CS32 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR33 -+ HASH_CSR33 -+ HASH context swap registers -+ 0x17C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS33 -+ CS33 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR34 -+ HASH_CSR34 -+ HASH context swap registers -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS34 -+ CS34 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR35 -+ HASH_CSR35 -+ HASH context swap registers -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS35 -+ CS35 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR36 -+ HASH_CSR36 -+ HASH context swap registers -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS36 -+ CS36 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR37 -+ HASH_CSR37 -+ HASH context swap registers -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS37 -+ CS37 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR38 -+ HASH_CSR38 -+ HASH context swap registers -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS38 -+ CS38 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR39 -+ HASH_CSR39 -+ HASH context swap registers -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS39 -+ CS39 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR40 -+ HASH_CSR40 -+ HASH context swap registers -+ 0x198 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS40 -+ CS40 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR41 -+ HASH_CSR41 -+ HASH context swap registers -+ 0x19C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS41 -+ CS41 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR42 -+ HASH_CSR42 -+ HASH context swap registers -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS42 -+ CS42 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR43 -+ HASH_CSR43 -+ HASH context swap registers -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS43 -+ CS43 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR44 -+ HASH_CSR44 -+ HASH context swap registers -+ 0x1A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS44 -+ CS44 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR45 -+ HASH_CSR45 -+ HASH context swap registers -+ 0x1AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS45 -+ CS45 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR46 -+ HASH_CSR46 -+ HASH context swap registers -+ 0x1B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS46 -+ CS46 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR47 -+ HASH_CSR47 -+ HASH context swap registers -+ 0x1B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS47 -+ CS47 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR48 -+ HASH_CSR48 -+ HASH context swap registers -+ 0x1B8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS48 -+ CS48 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR49 -+ HASH_CSR49 -+ HASH context swap registers -+ 0x1BC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS49 -+ CS49 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR50 -+ HASH_CSR50 -+ HASH context swap registers -+ 0x1C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS50 -+ CS50 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR51 -+ HASH_CSR51 -+ HASH context swap registers -+ 0x1C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS51 -+ CS51 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR52 -+ HASH_CSR52 -+ HASH context swap registers -+ 0x1C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS52 -+ CS52 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_CSR53 -+ HASH_CSR53 -+ HASH context swap registers -+ 0x1CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CS53 -+ CS53 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR5 -+ HASH_HR5 -+ HASH digest register 5 -+ 0x324 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H5 -+ H5 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR6 -+ HASH_HR6 -+ HASH digest register 6 -+ 0x328 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H6 -+ H6 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HR7 -+ HASH_HR7 -+ HASH digest register 7 -+ 0x32C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ H7 -+ H7 -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_HWCFGR -+ HASH_HWCFGR -+ HASH Hardware Configuration Register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 4 -+ -+ -+ -+ -+ HASH_VERR -+ HASH_VERR -+ HASH Version Register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000023 -+ -+ -+ VER -+ VER -+ 0 -+ 8 -+ -+ -+ -+ -+ HASH_IPIDR -+ HASH_IPIDR -+ HASH Identification -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00170031 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ HASH_MID -+ HASH_MID -+ HASH Hardware Magic ID -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ MID -+ MID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ HSEM -+ HSEM -+ HSEM_IPXACT -+ 0x4C000000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ HSEM_R0 -+ HSEM_R0 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R1 -+ HSEM_R1 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R2 -+ HSEM_R2 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R3 -+ HSEM_R3 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R4 -+ HSEM_R4 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R5 -+ HSEM_R5 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R6 -+ HSEM_R6 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R7 -+ HSEM_R7 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R8 -+ HSEM_R8 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R9 -+ HSEM_R9 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R10 -+ HSEM_R10 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R11 -+ HSEM_R11 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R12 -+ HSEM_R12 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R13 -+ HSEM_R13 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R14 -+ HSEM_R14 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x38 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R15 -+ HSEM_R15 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x3C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R16 -+ HSEM_R16 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R17 -+ HSEM_R17 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R18 -+ HSEM_R18 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R19 -+ HSEM_R19 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x4C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R20 -+ HSEM_R20 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R21 -+ HSEM_R21 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R22 -+ HSEM_R22 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R23 -+ HSEM_R23 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x5C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R24 -+ HSEM_R24 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R25 -+ HSEM_R25 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x64 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R26 -+ HSEM_R26 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R27 -+ HSEM_R27 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x6C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R28 -+ HSEM_R28 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R29 -+ HSEM_R29 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R30 -+ HSEM_R30 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x78 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_R31 -+ HSEM_R31 -+ The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x7C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR0 -+ HSEM_RLR0 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x80 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR1 -+ HSEM_RLR1 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x84 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR2 -+ HSEM_RLR2 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x88 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR3 -+ HSEM_RLR3 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x8C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR4 -+ HSEM_RLR4 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x90 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR5 -+ HSEM_RLR5 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x94 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR6 -+ HSEM_RLR6 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x98 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR7 -+ HSEM_RLR7 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0x9C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR8 -+ HSEM_RLR8 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xA0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR9 -+ HSEM_RLR9 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xA4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR10 -+ HSEM_RLR10 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xA8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR11 -+ HSEM_RLR11 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xAC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR12 -+ HSEM_RLR12 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xB0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR13 -+ HSEM_RLR13 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xB4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR14 -+ HSEM_RLR14 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xB8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR15 -+ HSEM_RLR15 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xBC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR16 -+ HSEM_RLR16 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xC0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR17 -+ HSEM_RLR17 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xC4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR18 -+ HSEM_RLR18 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xC8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR19 -+ HSEM_RLR19 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xCC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR20 -+ HSEM_RLR20 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xD0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR21 -+ HSEM_RLR21 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR22 -+ HSEM_RLR22 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR23 -+ HSEM_RLR23 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR24 -+ HSEM_RLR24 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xE0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR25 -+ HSEM_RLR25 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xE4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR26 -+ HSEM_RLR26 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xE8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR27 -+ HSEM_RLR27 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR28 -+ HSEM_RLR28 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xF0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR29 -+ HSEM_RLR29 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xF4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR30 -+ HSEM_RLR30 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xF8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_RLR31 -+ HSEM_RLR31 -+ Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. -+ 0xFC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PROCID -+ PROCID -+ 0 -+ 8 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ LOCK -+ LOCK -+ 31 -+ 1 -+ -+ -+ -+ -+ HSEM_C1IER -+ HSEM_C1IER -+ HSEM i1terrupt enable register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISE -+ ISE -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C1ICR -+ HSEM_C1ICR -+ HSEM i1terrupt clear register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISC -+ ISC -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C1ISR -+ HSEM_C1ISR -+ HSEM i1terrupt status register -+ 0x108 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ISF -+ ISF -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C1MISR -+ HSEM_C1MISR -+ HSEM i1terrupt status register -+ 0x10C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ MISF -+ MISF -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C2IER -+ HSEM_C2IER -+ HSEM i2terrupt enable register -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISE -+ ISE -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C2ICR -+ HSEM_C2ICR -+ HSEM i2terrupt clear register -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISC -+ ISC -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C2ISR -+ HSEM_C2ISR -+ HSEM i2terrupt status register -+ 0x118 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ISF -+ ISF -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_C2MISR -+ HSEM_C2MISR -+ HSEM i2terrupt status register -+ 0x11C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ MISF -+ MISF -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_CR -+ HSEM_CR -+ Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. -+ 0x140 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ COREID -+ COREID -+ 8 -+ 4 -+ -+ -+ KEY -+ KEY -+ 16 -+ 16 -+ -+ -+ -+ -+ HSEM_KEYR -+ HSEM_KEYR -+ HSEM interrupt clear register -+ 0x144 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ KEY -+ KEY -+ 16 -+ 16 -+ -+ -+ -+ -+ HSEM_HWCFGR2 -+ HSEM_HWCFGR2 -+ HSEM hardware configuration register 2 -+ 0x3EC -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MASTERID1 -+ MASTERID1 -+ 0 -+ 4 -+ -+ -+ MASTERID2 -+ MASTERID2 -+ 4 -+ 4 -+ -+ -+ MASTERID3 -+ MASTERID3 -+ 8 -+ 4 -+ -+ -+ MASTERID4 -+ MASTERID4 -+ 12 -+ 4 -+ -+ -+ -+ -+ HSEM_HWCFGR1 -+ HSEM_HWCFGR1 -+ HSEM hardware configuration register 1 -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000220 -+ -+ -+ NBSEM -+ NBSEM -+ 0 -+ 8 -+ -+ -+ NBINT -+ NBINT -+ 8 -+ 4 -+ -+ -+ -+ -+ HSEM_VERR -+ HSEM_VERR -+ HSEM IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ HSEM_IPIDR -+ HSEM_IPIDR -+ HSEM IP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00100072 -+ -+ -+ IPID -+ IPID -+ 0 -+ 32 -+ -+ -+ -+ -+ HSEM_SIDR -+ HSEM_SIDR -+ HSEM size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ HDP -+ HDP -+ HDP -+ 0x5002A000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ HDP_CTRL -+ HDP_CTRL -+ HDP Control -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ -+ -+ -+ -+ HDP_MUX -+ HDP_MUX -+ HDP multiplexing -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MUX0 -+ MUX0 -+ 0 -+ 4 -+ -+ -+ MUX1 -+ MUX1 -+ 4 -+ 4 -+ -+ -+ MUX2 -+ MUX2 -+ 8 -+ 4 -+ -+ -+ MUX3 -+ MUX3 -+ 12 -+ 4 -+ -+ -+ MUX4 -+ MUX4 -+ 16 -+ 4 -+ -+ -+ MUX5 -+ MUX5 -+ 20 -+ 4 -+ -+ -+ MUX6 -+ MUX6 -+ 24 -+ 4 -+ -+ -+ MUX7 -+ MUX7 -+ 28 -+ 4 -+ -+ -+ -+ -+ HDP_VAL -+ HDP_VAL -+ HDP value -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HDPVAL -+ HDPVAL -+ 0 -+ 8 -+ -+ -+ -+ -+ HDP_GPOSET -+ HDP_GPOSET -+ HDP GPO set -+ 0x14 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ HDPGPOSET -+ HDPGPOSET -+ 0 -+ 8 -+ -+ -+ -+ -+ HDP_GPOCLR -+ HDP_GPOCLR -+ HDP GPO clear -+ 0x18 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ HDPGPOCLR -+ HDPGPOCLR -+ 0 -+ 8 -+ -+ -+ -+ -+ HDP_GPOVAL -+ HDP_GPOVAL -+ HDP GPO value -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HDPGPOVAL -+ HDPGPOVAL -+ 0 -+ 8 -+ -+ -+ -+ -+ HDP_VERR -+ HDP_VERR -+ HDP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ HDP_IPIDR -+ HDP_IPIDR -+ HDP IP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00030002 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ HDP_SIDR -+ HDP_SIDR -+ HDP size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ SAI1 -+ SAI1 register block -+ SAI -+ 0x4400A000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ SAI_GCR -+ SAI_GCR -+ Global configuration register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SYNCIN -+ SYNCIN -+ 0 -+ 2 -+ -+ -+ SYNCOUT -+ SYNCOUT -+ 4 -+ 2 -+ -+ -+ -+ -+ SAI_ACR1 -+ SAI_ACR1 -+ Configuration register 1 -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000040 -+ -+ -+ MODE -+ MODE -+ 0 -+ 2 -+ -+ -+ PRTCFG -+ PRTCFG -+ 2 -+ 2 -+ -+ -+ DS -+ DS -+ 5 -+ 3 -+ -+ -+ LSBFIRST -+ LSBFIRST -+ 8 -+ 1 -+ -+ -+ CKSTR -+ CKSTR -+ 9 -+ 1 -+ -+ -+ SYNCEN -+ SYNCEN -+ 10 -+ 2 -+ -+ -+ MONO -+ MONO -+ 12 -+ 1 -+ -+ -+ OUTDRIV -+ OUTDRIV -+ 13 -+ 1 -+ -+ -+ SAIEN -+ SAIEN -+ 16 -+ 1 -+ -+ -+ DMAEN -+ DMAEN -+ 17 -+ 1 -+ -+ -+ NODIV -+ NODIV -+ 19 -+ 1 -+ -+ -+ MCKDIV -+ MCKDIV -+ 20 -+ 6 -+ -+ -+ OSR -+ OSR -+ 26 -+ 1 -+ -+ -+ MCKEN -+ MCKEN -+ 27 -+ 1 -+ -+ -+ -+ -+ SAI_ACR2 -+ SAI_ACR2 -+ Configuration register 2 -+ 0x8 -+ 0x20 -+ 0x00000000 -+ -+ -+ FTH -+ FTH -+ 0 -+ 3 -+ read-write -+ -+ -+ FFLUSH -+ FFLUSH -+ 3 -+ 1 -+ write-only -+ -+ -+ TRIS -+ TRIS -+ 4 -+ 1 -+ read-write -+ -+ -+ MUTE -+ MUTE -+ 5 -+ 1 -+ read-write -+ -+ -+ MUTEVAL -+ MUTEVAL -+ 6 -+ 1 -+ read-write -+ -+ -+ MUTECNT -+ MUTECNT -+ 7 -+ 6 -+ read-write -+ -+ -+ CPL -+ CPL -+ 13 -+ 1 -+ read-write -+ -+ -+ COMP -+ COMP -+ 14 -+ 2 -+ read-write -+ -+ -+ -+ -+ SAI_AFRCR -+ SAI_AFRCR -+ This register has no meaning in and SPDIF audio protocol -+ 0xC -+ 0x20 -+ 0x00000007 -+ -+ -+ FRL -+ FRL -+ 0 -+ 8 -+ read-write -+ -+ -+ FSALL -+ FSALL -+ 8 -+ 7 -+ read-write -+ -+ -+ FSDEF -+ FSDEF -+ 16 -+ 1 -+ read-only -+ -+ -+ FSPOL -+ FSPOL -+ 17 -+ 1 -+ read-write -+ -+ -+ FSOFF -+ FSOFF -+ 18 -+ 1 -+ read-write -+ -+ -+ -+ -+ SAI_ASLOTR -+ SAI_ASLOTR -+ This register has no meaning in and SPDIF audio protocol -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FBOFF -+ FBOFF -+ 0 -+ 5 -+ -+ -+ SLOTSZ -+ SLOTSZ -+ 6 -+ 2 -+ -+ -+ NBSLOT -+ NBSLOT -+ 8 -+ 4 -+ -+ -+ SLOTEN -+ SLOTEN -+ 16 -+ 16 -+ -+ -+ -+ -+ SAI_AIM -+ SAI_AIM -+ Interrupt mask register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OVRUDRIE -+ OVRUDRIE -+ 0 -+ 1 -+ -+ -+ MUTEDETIE -+ MUTEDETIE -+ 1 -+ 1 -+ -+ -+ WCKCFGIE -+ WCKCFGIE -+ 2 -+ 1 -+ -+ -+ FREQIE -+ FREQIE -+ 3 -+ 1 -+ -+ -+ CNRDYIE -+ CNRDYIE -+ 4 -+ 1 -+ -+ -+ AFSDETIE -+ AFSDETIE -+ 5 -+ 1 -+ -+ -+ LFSDETIE -+ LFSDETIE -+ 6 -+ 1 -+ -+ -+ -+ -+ SAI_ASR -+ SAI_ASR -+ Status register -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000008 -+ -+ -+ OVRUDR -+ OVRUDR -+ 0 -+ 1 -+ -+ -+ MUTEDET -+ MUTEDET -+ 1 -+ 1 -+ -+ -+ WCKCFG -+ WCKCFG -+ 2 -+ 1 -+ -+ -+ FREQ -+ FREQ -+ 3 -+ 1 -+ -+ -+ CNRDY -+ CNRDY -+ 4 -+ 1 -+ -+ -+ AFSDET -+ AFSDET -+ 5 -+ 1 -+ -+ -+ LFSDET -+ LFSDET -+ 6 -+ 1 -+ -+ -+ FLVL -+ FLVL -+ 16 -+ 3 -+ -+ -+ -+ -+ SAI_ACLRFR -+ SAI_ACLRFR -+ Clear flag register -+ 0x1C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ COVRUDR -+ COVRUDR -+ 0 -+ 1 -+ -+ -+ CMUTEDET -+ CMUTEDET -+ 1 -+ 1 -+ -+ -+ CWCKCFG -+ CWCKCFG -+ 2 -+ 1 -+ -+ -+ CCNRDY -+ CCNRDY -+ 4 -+ 1 -+ -+ -+ CAFSDET -+ CAFSDET -+ 5 -+ 1 -+ -+ -+ CLFSDET -+ CLFSDET -+ 6 -+ 1 -+ -+ -+ -+ -+ SAI_ADR -+ SAI_ADR -+ Data register -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SAI_BCR1 -+ SAI_BCR1 -+ Configuration register 1 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000040 -+ -+ -+ MODE -+ MODE -+ 0 -+ 2 -+ -+ -+ PRTCFG -+ PRTCFG -+ 2 -+ 2 -+ -+ -+ DS -+ DS -+ 5 -+ 3 -+ -+ -+ LSBFIRST -+ LSBFIRST -+ 8 -+ 1 -+ -+ -+ CKSTR -+ CKSTR -+ 9 -+ 1 -+ -+ -+ SYNCEN -+ SYNCEN -+ 10 -+ 2 -+ -+ -+ MONO -+ MONO -+ 12 -+ 1 -+ -+ -+ OUTDRIV -+ OUTDRIV -+ 13 -+ 1 -+ -+ -+ SAIEN -+ SAIEN -+ 16 -+ 1 -+ -+ -+ DMAEN -+ DMAEN -+ 17 -+ 1 -+ -+ -+ NODIV -+ NODIV -+ 19 -+ 1 -+ -+ -+ MCKDIV -+ MCKDIV -+ 20 -+ 6 -+ -+ -+ OSR -+ OSR -+ 26 -+ 1 -+ -+ -+ MCKEN -+ MCKEN -+ 27 -+ 1 -+ -+ -+ -+ -+ SAI_BCR2 -+ SAI_BCR2 -+ Configuration register 2 -+ 0x28 -+ 0x20 -+ 0x00000000 -+ -+ -+ FTH -+ FTH -+ 0 -+ 3 -+ read-write -+ -+ -+ FFLUSH -+ FFLUSH -+ 3 -+ 1 -+ write-only -+ -+ -+ TRIS -+ TRIS -+ 4 -+ 1 -+ read-write -+ -+ -+ MUTE -+ MUTE -+ 5 -+ 1 -+ read-write -+ -+ -+ MUTEVAL -+ MUTEVAL -+ 6 -+ 1 -+ read-write -+ -+ -+ MUTECNT -+ MUTECNT -+ 7 -+ 6 -+ read-write -+ -+ -+ CPL -+ CPL -+ 13 -+ 1 -+ read-write -+ -+ -+ COMP -+ COMP -+ 14 -+ 2 -+ read-write -+ -+ -+ -+ -+ SAI_BFRCR -+ SAI_BFRCR -+ This register has no meaning in and SPDIF audio protocol -+ 0x2C -+ 0x20 -+ 0x00000007 -+ -+ -+ FRL -+ FRL -+ 0 -+ 8 -+ read-write -+ -+ -+ FSALL -+ FSALL -+ 8 -+ 7 -+ read-write -+ -+ -+ FSDEF -+ FSDEF -+ 16 -+ 1 -+ read-only -+ -+ -+ FSPOL -+ FSPOL -+ 17 -+ 1 -+ read-write -+ -+ -+ FSOFF -+ FSOFF -+ 18 -+ 1 -+ read-write -+ -+ -+ -+ -+ SAI_BSLOTR -+ SAI_BSLOTR -+ This register has no meaning in and SPDIF audio protocol -+ 0x30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FBOFF -+ FBOFF -+ 0 -+ 5 -+ -+ -+ SLOTSZ -+ SLOTSZ -+ 6 -+ 2 -+ -+ -+ NBSLOT -+ NBSLOT -+ 8 -+ 4 -+ -+ -+ SLOTEN -+ SLOTEN -+ 16 -+ 16 -+ -+ -+ -+ -+ SAI_BIM -+ SAI_BIM -+ Interrupt mask register -+ 0x34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OVRUDRIE -+ OVRUDRIE -+ 0 -+ 1 -+ -+ -+ MUTEDETIE -+ MUTEDETIE -+ 1 -+ 1 -+ -+ -+ WCKCFGIE -+ WCKCFGIE -+ 2 -+ 1 -+ -+ -+ FREQIE -+ FREQIE -+ 3 -+ 1 -+ -+ -+ CNRDYIE -+ CNRDYIE -+ 4 -+ 1 -+ -+ -+ AFSDETIE -+ AFSDETIE -+ 5 -+ 1 -+ -+ -+ LFSDETIE -+ LFSDETIE -+ 6 -+ 1 -+ -+ -+ -+ -+ SAI_BSR -+ SAI_BSR -+ Status register -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000008 -+ -+ -+ OVRUDR -+ OVRUDR -+ 0 -+ 1 -+ -+ -+ MUTEDET -+ MUTEDET -+ 1 -+ 1 -+ -+ -+ WCKCFG -+ WCKCFG -+ 2 -+ 1 -+ -+ -+ FREQ -+ FREQ -+ 3 -+ 1 -+ -+ -+ CNRDY -+ CNRDY -+ 4 -+ 1 -+ -+ -+ AFSDET -+ AFSDET -+ 5 -+ 1 -+ -+ -+ LFSDET -+ LFSDET -+ 6 -+ 1 -+ -+ -+ FLVL -+ FLVL -+ 16 -+ 3 -+ -+ -+ -+ -+ SAI_BCLRFR -+ SAI_BCLRFR -+ Clear flag register -+ 0x3C -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ COVRUDR -+ COVRUDR -+ 0 -+ 1 -+ -+ -+ CMUTEDET -+ CMUTEDET -+ 1 -+ 1 -+ -+ -+ CWCKCFG -+ CWCKCFG -+ 2 -+ 1 -+ -+ -+ CCNRDY -+ CCNRDY -+ 4 -+ 1 -+ -+ -+ CAFSDET -+ CAFSDET -+ 5 -+ 1 -+ -+ -+ CLFSDET -+ CLFSDET -+ 6 -+ 1 -+ -+ -+ -+ -+ SAI_BDR -+ SAI_BDR -+ Data register -+ 0x40 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DATA -+ DATA -+ 0 -+ 32 -+ -+ -+ -+ -+ SAI_PDMCR -+ SAI_PDMCR -+ PDM control register -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PDMEN -+ PDMEN -+ 0 -+ 1 -+ -+ -+ MICNBR -+ MICNBR -+ 4 -+ 2 -+ -+ -+ CKEN1 -+ CKEN1 -+ 8 -+ 1 -+ -+ -+ CKEN2 -+ CKEN2 -+ 9 -+ 1 -+ -+ -+ CKEN3 -+ CKEN3 -+ 10 -+ 1 -+ -+ -+ CKEN4 -+ CKEN4 -+ 11 -+ 1 -+ -+ -+ -+ -+ SAI_PDMDLY -+ SAI_PDMDLY -+ PDM delay register -+ 0x48 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DLYM1L -+ DLYM1L -+ 0 -+ 3 -+ -+ -+ DLYM1R -+ DLYM1R -+ 4 -+ 3 -+ -+ -+ DLYM2L -+ DLYM2L -+ 8 -+ 3 -+ -+ -+ DLYM2R -+ DLYM2R -+ 12 -+ 3 -+ -+ -+ DLYM3L -+ DLYM3L -+ 16 -+ 3 -+ -+ -+ DLYM3R -+ DLYM3R -+ 20 -+ 3 -+ -+ -+ DLYM4L -+ DLYM4L -+ 24 -+ 3 -+ -+ -+ DLYM4R -+ DLYM4R -+ 28 -+ 3 -+ -+ -+ -+ -+ SAI_HWCFGR -+ SAI_HWCFGR -+ SAI hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000108 -+ -+ -+ FIFO_SIZE -+ FIFO_SIZE -+ 0 -+ 8 -+ -+ -+ SPDIF_PDM -+ SPDIF_PDM -+ 8 -+ 4 -+ -+ -+ OPTION_REGOUT -+ OPTION_REGOUT -+ 12 -+ 8 -+ -+ -+ -+ -+ SAI_VERR -+ SAI_VERR -+ SAI version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ SAI_IPIDR -+ SAI_IPIDR -+ SAI identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130031 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ SAI_SIDR -+ SAI_SIDR -+ SAI size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ SAI2 -+ 0x4400B000 -+ -+ -+ SAI3 -+ 0x4400C000 -+ -+ -+ SAI4 -+ 0x50027000 -+ -+ -+ VREFBUF -+ VREFBUF -+ VREFBUF -+ 0x50025000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ VREFBUF_CSR -+ VREFBUF_CSR -+ VREFBUF control and status register -+ 0x0 -+ 0x20 -+ 0x00000002 -+ -+ -+ ENVR -+ ENVR -+ 0 -+ 1 -+ read-write -+ -+ -+ HIZ -+ HIZ -+ 1 -+ 1 -+ read-write -+ -+ -+ VRR -+ VRR -+ 3 -+ 1 -+ read-only -+ -+ -+ VRS -+ VRS -+ 4 -+ 3 -+ read-write -+ -+ -+ -+ -+ VREFBUF_CCR -+ VREFBUF_CCR -+ VREFBUF calibration control register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TRIM -+ TRIM -+ 0 -+ 6 -+ -+ -+ -+ -+ -+ -+ LPTIM1 -+ LPTIM1 -+ LPTIM1 -+ 0x40009000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LPTIM_ISR -+ LPTIM_ISR -+ LPTIM interrupt and status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMPM -+ CMPM -+ 0 -+ 1 -+ -+ -+ ARRM -+ ARRM -+ 1 -+ 1 -+ -+ -+ EXTTRIG -+ EXTTRIG -+ 2 -+ 1 -+ -+ -+ CMPOK -+ CMPOK -+ 3 -+ 1 -+ -+ -+ ARROK -+ ARROK -+ 4 -+ 1 -+ -+ -+ UP -+ UP -+ 5 -+ 1 -+ -+ -+ DOWN -+ DOWN -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_ICR -+ LPTIM_ICR -+ LPTIM interrupt clear register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CMPMCF -+ CMPMCF -+ 0 -+ 1 -+ -+ -+ ARRMCF -+ ARRMCF -+ 1 -+ 1 -+ -+ -+ EXTTRIGCF -+ EXTTRIGCF -+ 2 -+ 1 -+ -+ -+ CMPOKCF -+ CMPOKCF -+ 3 -+ 1 -+ -+ -+ ARROKCF -+ ARROKCF -+ 4 -+ 1 -+ -+ -+ UPCF -+ UPCF -+ 5 -+ 1 -+ -+ -+ DOWNCF -+ DOWNCF -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_IER -+ LPTIM_IER -+ LPTIM interrupt enable register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMPMIE -+ CMPMIE -+ 0 -+ 1 -+ -+ -+ ARRMIE -+ ARRMIE -+ 1 -+ 1 -+ -+ -+ EXTTRIGIE -+ EXTTRIGIE -+ 2 -+ 1 -+ -+ -+ CMPOKIE -+ CMPOKIE -+ 3 -+ 1 -+ -+ -+ ARROKIE -+ ARROKIE -+ 4 -+ 1 -+ -+ -+ UPIE -+ UPIE -+ 5 -+ 1 -+ -+ -+ DOWNIE -+ DOWNIE -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_CFGR -+ LPTIM_CFGR -+ LPTIM configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKSEL -+ CKSEL -+ 0 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 1 -+ 2 -+ -+ -+ CKFLT -+ CKFLT -+ 3 -+ 2 -+ -+ -+ TRGFLT -+ TRGFLT -+ 6 -+ 2 -+ -+ -+ PRESC -+ PRESC -+ 9 -+ 3 -+ -+ -+ TRIGSEL -+ TRIGSEL -+ 13 -+ 3 -+ -+ -+ TRIGEN -+ TRIGEN -+ 17 -+ 2 -+ -+ -+ TIMOUT -+ TIMOUT -+ 19 -+ 1 -+ -+ -+ WAVE -+ WAVE -+ 20 -+ 1 -+ -+ -+ WAVPOL -+ WAVPOL -+ 21 -+ 1 -+ -+ -+ PRELOAD -+ PRELOAD -+ 22 -+ 1 -+ -+ -+ COUNTMODE -+ COUNTMODE -+ 23 -+ 1 -+ -+ -+ ENC -+ ENC -+ 24 -+ 1 -+ -+ -+ -+ -+ LPTIM_CR -+ LPTIM_CR -+ LPTIM control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLE -+ ENABLE -+ 0 -+ 1 -+ -+ -+ SNGSTRT -+ SNGSTRT -+ 1 -+ 1 -+ -+ -+ CNTSTRT -+ CNTSTRT -+ 2 -+ 1 -+ -+ -+ COUNTRST -+ COUNTRST -+ 3 -+ 1 -+ -+ -+ RSTARE -+ RSTARE -+ 4 -+ 1 -+ -+ -+ -+ -+ LPTIM_CMP -+ LPTIM_CMP -+ LPTIM compare register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMP -+ CMP -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_ARR -+ LPTIM_ARR -+ LPTIM autoreload register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CNT -+ LPTIM_CNT -+ LPTIM counter register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CFGR2 -+ LPTIM_CFGR2 -+ LPTIM configuration register 2 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IN1SEL -+ IN1SEL -+ 0 -+ 2 -+ -+ -+ IN2SEL -+ IN2SEL -+ 4 -+ 2 -+ -+ -+ -+ -+ LPTIM1_HWCFGR -+ LPTIM1_HWCFGR -+ LPTIM 1 peripheral hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00010804 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 8 -+ -+ -+ CFG2 -+ CFG2 -+ 8 -+ 8 -+ -+ -+ CFG3 -+ CFG3 -+ 16 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 24 -+ 8 -+ -+ -+ -+ -+ LPTIM_VERR -+ LPTIM_VERR -+ LPTIM peripheral version identification register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ LPTIM_PIDR -+ LPTIM_PIDR -+ LPTIM peripheral type identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120011 -+ -+ -+ P_ID -+ P_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ LPTIM_SIDR -+ LPTIM_SIDR -+ LPTIM registers map size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ S_ID -+ S_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ LPTIM2 -+ LPTIM2 -+ LPTIM2 -+ 0x50021000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LPTIM2_HWCFGR -+ LPTIM2_HWCFGR -+ LPTIM 2 peripheral hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00010804 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 8 -+ -+ -+ CFG2 -+ CFG2 -+ 8 -+ 8 -+ -+ -+ CFG3 -+ CFG3 -+ 16 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 24 -+ 8 -+ -+ -+ -+ -+ LPTIM_ISR -+ LPTIM_ISR -+ LPTIM interrupt and status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMPM -+ CMPM -+ 0 -+ 1 -+ -+ -+ ARRM -+ ARRM -+ 1 -+ 1 -+ -+ -+ EXTTRIG -+ EXTTRIG -+ 2 -+ 1 -+ -+ -+ CMPOK -+ CMPOK -+ 3 -+ 1 -+ -+ -+ ARROK -+ ARROK -+ 4 -+ 1 -+ -+ -+ UP -+ UP -+ 5 -+ 1 -+ -+ -+ DOWN -+ DOWN -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_ICR -+ LPTIM_ICR -+ LPTIM interrupt clear register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CMPMCF -+ CMPMCF -+ 0 -+ 1 -+ -+ -+ ARRMCF -+ ARRMCF -+ 1 -+ 1 -+ -+ -+ EXTTRIGCF -+ EXTTRIGCF -+ 2 -+ 1 -+ -+ -+ CMPOKCF -+ CMPOKCF -+ 3 -+ 1 -+ -+ -+ ARROKCF -+ ARROKCF -+ 4 -+ 1 -+ -+ -+ UPCF -+ UPCF -+ 5 -+ 1 -+ -+ -+ DOWNCF -+ DOWNCF -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_IER -+ LPTIM_IER -+ LPTIM interrupt enable register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMPMIE -+ CMPMIE -+ 0 -+ 1 -+ -+ -+ ARRMIE -+ ARRMIE -+ 1 -+ 1 -+ -+ -+ EXTTRIGIE -+ EXTTRIGIE -+ 2 -+ 1 -+ -+ -+ CMPOKIE -+ CMPOKIE -+ 3 -+ 1 -+ -+ -+ ARROKIE -+ ARROKIE -+ 4 -+ 1 -+ -+ -+ UPIE -+ UPIE -+ 5 -+ 1 -+ -+ -+ DOWNIE -+ DOWNIE -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_CFGR -+ LPTIM_CFGR -+ LPTIM configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKSEL -+ CKSEL -+ 0 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 1 -+ 2 -+ -+ -+ CKFLT -+ CKFLT -+ 3 -+ 2 -+ -+ -+ TRGFLT -+ TRGFLT -+ 6 -+ 2 -+ -+ -+ PRESC -+ PRESC -+ 9 -+ 3 -+ -+ -+ TRIGSEL -+ TRIGSEL -+ 13 -+ 3 -+ -+ -+ TRIGEN -+ TRIGEN -+ 17 -+ 2 -+ -+ -+ TIMOUT -+ TIMOUT -+ 19 -+ 1 -+ -+ -+ WAVE -+ WAVE -+ 20 -+ 1 -+ -+ -+ WAVPOL -+ WAVPOL -+ 21 -+ 1 -+ -+ -+ PRELOAD -+ PRELOAD -+ 22 -+ 1 -+ -+ -+ COUNTMODE -+ COUNTMODE -+ 23 -+ 1 -+ -+ -+ ENC -+ ENC -+ 24 -+ 1 -+ -+ -+ -+ -+ LPTIM_CR -+ LPTIM_CR -+ LPTIM control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLE -+ ENABLE -+ 0 -+ 1 -+ -+ -+ SNGSTRT -+ SNGSTRT -+ 1 -+ 1 -+ -+ -+ CNTSTRT -+ CNTSTRT -+ 2 -+ 1 -+ -+ -+ COUNTRST -+ COUNTRST -+ 3 -+ 1 -+ -+ -+ RSTARE -+ RSTARE -+ 4 -+ 1 -+ -+ -+ -+ -+ LPTIM_CMP -+ LPTIM_CMP -+ LPTIM compare register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMP -+ CMP -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_ARR -+ LPTIM_ARR -+ LPTIM autoreload register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CNT -+ LPTIM_CNT -+ LPTIM counter register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CFGR2 -+ LPTIM_CFGR2 -+ LPTIM configuration register 2 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IN1SEL -+ IN1SEL -+ 0 -+ 2 -+ -+ -+ IN2SEL -+ IN2SEL -+ 4 -+ 2 -+ -+ -+ -+ -+ LPTIM_VERR -+ LPTIM_VERR -+ LPTIM peripheral version identification register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ LPTIM_PIDR -+ LPTIM_PIDR -+ LPTIM peripheral type identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120011 -+ -+ -+ P_ID -+ P_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ LPTIM_SIDR -+ LPTIM_SIDR -+ LPTIM registers map size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ S_ID -+ S_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ -+ LPTIM4 -+ LPTIM4 -+ LPTIM4 -+ 0x50023000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LPTIM4_HWCFGR -+ LPTIM4_HWCFGR -+ LPTIM 4 peripheral hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000804 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 8 -+ -+ -+ CFG2 -+ CFG2 -+ 8 -+ 8 -+ -+ -+ CFG3 -+ CFG3 -+ 16 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 24 -+ 8 -+ -+ -+ -+ -+ LPTIM_ISR -+ LPTIM_ISR -+ LPTIM interrupt and status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMPM -+ CMPM -+ 0 -+ 1 -+ -+ -+ ARRM -+ ARRM -+ 1 -+ 1 -+ -+ -+ EXTTRIG -+ EXTTRIG -+ 2 -+ 1 -+ -+ -+ CMPOK -+ CMPOK -+ 3 -+ 1 -+ -+ -+ ARROK -+ ARROK -+ 4 -+ 1 -+ -+ -+ UP -+ UP -+ 5 -+ 1 -+ -+ -+ DOWN -+ DOWN -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_ICR -+ LPTIM_ICR -+ LPTIM interrupt clear register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CMPMCF -+ CMPMCF -+ 0 -+ 1 -+ -+ -+ ARRMCF -+ ARRMCF -+ 1 -+ 1 -+ -+ -+ EXTTRIGCF -+ EXTTRIGCF -+ 2 -+ 1 -+ -+ -+ CMPOKCF -+ CMPOKCF -+ 3 -+ 1 -+ -+ -+ ARROKCF -+ ARROKCF -+ 4 -+ 1 -+ -+ -+ UPCF -+ UPCF -+ 5 -+ 1 -+ -+ -+ DOWNCF -+ DOWNCF -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_IER -+ LPTIM_IER -+ LPTIM interrupt enable register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMPMIE -+ CMPMIE -+ 0 -+ 1 -+ -+ -+ ARRMIE -+ ARRMIE -+ 1 -+ 1 -+ -+ -+ EXTTRIGIE -+ EXTTRIGIE -+ 2 -+ 1 -+ -+ -+ CMPOKIE -+ CMPOKIE -+ 3 -+ 1 -+ -+ -+ ARROKIE -+ ARROKIE -+ 4 -+ 1 -+ -+ -+ UPIE -+ UPIE -+ 5 -+ 1 -+ -+ -+ DOWNIE -+ DOWNIE -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_CFGR -+ LPTIM_CFGR -+ LPTIM configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKSEL -+ CKSEL -+ 0 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 1 -+ 2 -+ -+ -+ CKFLT -+ CKFLT -+ 3 -+ 2 -+ -+ -+ TRGFLT -+ TRGFLT -+ 6 -+ 2 -+ -+ -+ PRESC -+ PRESC -+ 9 -+ 3 -+ -+ -+ TRIGSEL -+ TRIGSEL -+ 13 -+ 3 -+ -+ -+ TRIGEN -+ TRIGEN -+ 17 -+ 2 -+ -+ -+ TIMOUT -+ TIMOUT -+ 19 -+ 1 -+ -+ -+ WAVE -+ WAVE -+ 20 -+ 1 -+ -+ -+ WAVPOL -+ WAVPOL -+ 21 -+ 1 -+ -+ -+ PRELOAD -+ PRELOAD -+ 22 -+ 1 -+ -+ -+ COUNTMODE -+ COUNTMODE -+ 23 -+ 1 -+ -+ -+ ENC -+ ENC -+ 24 -+ 1 -+ -+ -+ -+ -+ LPTIM_CR -+ LPTIM_CR -+ LPTIM control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLE -+ ENABLE -+ 0 -+ 1 -+ -+ -+ SNGSTRT -+ SNGSTRT -+ 1 -+ 1 -+ -+ -+ CNTSTRT -+ CNTSTRT -+ 2 -+ 1 -+ -+ -+ COUNTRST -+ COUNTRST -+ 3 -+ 1 -+ -+ -+ RSTARE -+ RSTARE -+ 4 -+ 1 -+ -+ -+ -+ -+ LPTIM_CMP -+ LPTIM_CMP -+ LPTIM compare register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMP -+ CMP -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_ARR -+ LPTIM_ARR -+ LPTIM autoreload register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CNT -+ LPTIM_CNT -+ LPTIM counter register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CFGR2 -+ LPTIM_CFGR2 -+ LPTIM configuration register 2 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IN1SEL -+ IN1SEL -+ 0 -+ 2 -+ -+ -+ IN2SEL -+ IN2SEL -+ 4 -+ 2 -+ -+ -+ -+ -+ LPTIM_VERR -+ LPTIM_VERR -+ LPTIM peripheral version identification register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ LPTIM_PIDR -+ LPTIM_PIDR -+ LPTIM peripheral type identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120011 -+ -+ -+ P_ID -+ P_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ LPTIM_SIDR -+ LPTIM_SIDR -+ LPTIM registers map size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ S_ID -+ S_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ -+ LPTIM5 -+ LPTIM5 -+ LPTIM5 -+ 0x50024000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LPTIM5_HWCFGR -+ LPTIM5_HWCFGR -+ LPTIM 5 peripheral hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000804 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 8 -+ -+ -+ CFG2 -+ CFG2 -+ 8 -+ 8 -+ -+ -+ CFG3 -+ CFG3 -+ 16 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 24 -+ 8 -+ -+ -+ -+ -+ LPTIM_ISR -+ LPTIM_ISR -+ LPTIM interrupt and status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMPM -+ CMPM -+ 0 -+ 1 -+ -+ -+ ARRM -+ ARRM -+ 1 -+ 1 -+ -+ -+ EXTTRIG -+ EXTTRIG -+ 2 -+ 1 -+ -+ -+ CMPOK -+ CMPOK -+ 3 -+ 1 -+ -+ -+ ARROK -+ ARROK -+ 4 -+ 1 -+ -+ -+ UP -+ UP -+ 5 -+ 1 -+ -+ -+ DOWN -+ DOWN -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_ICR -+ LPTIM_ICR -+ LPTIM interrupt clear register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CMPMCF -+ CMPMCF -+ 0 -+ 1 -+ -+ -+ ARRMCF -+ ARRMCF -+ 1 -+ 1 -+ -+ -+ EXTTRIGCF -+ EXTTRIGCF -+ 2 -+ 1 -+ -+ -+ CMPOKCF -+ CMPOKCF -+ 3 -+ 1 -+ -+ -+ ARROKCF -+ ARROKCF -+ 4 -+ 1 -+ -+ -+ UPCF -+ UPCF -+ 5 -+ 1 -+ -+ -+ DOWNCF -+ DOWNCF -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_IER -+ LPTIM_IER -+ LPTIM interrupt enable register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMPMIE -+ CMPMIE -+ 0 -+ 1 -+ -+ -+ ARRMIE -+ ARRMIE -+ 1 -+ 1 -+ -+ -+ EXTTRIGIE -+ EXTTRIGIE -+ 2 -+ 1 -+ -+ -+ CMPOKIE -+ CMPOKIE -+ 3 -+ 1 -+ -+ -+ ARROKIE -+ ARROKIE -+ 4 -+ 1 -+ -+ -+ UPIE -+ UPIE -+ 5 -+ 1 -+ -+ -+ DOWNIE -+ DOWNIE -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_CFGR -+ LPTIM_CFGR -+ LPTIM configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKSEL -+ CKSEL -+ 0 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 1 -+ 2 -+ -+ -+ CKFLT -+ CKFLT -+ 3 -+ 2 -+ -+ -+ TRGFLT -+ TRGFLT -+ 6 -+ 2 -+ -+ -+ PRESC -+ PRESC -+ 9 -+ 3 -+ -+ -+ TRIGSEL -+ TRIGSEL -+ 13 -+ 3 -+ -+ -+ TRIGEN -+ TRIGEN -+ 17 -+ 2 -+ -+ -+ TIMOUT -+ TIMOUT -+ 19 -+ 1 -+ -+ -+ WAVE -+ WAVE -+ 20 -+ 1 -+ -+ -+ WAVPOL -+ WAVPOL -+ 21 -+ 1 -+ -+ -+ PRELOAD -+ PRELOAD -+ 22 -+ 1 -+ -+ -+ COUNTMODE -+ COUNTMODE -+ 23 -+ 1 -+ -+ -+ ENC -+ ENC -+ 24 -+ 1 -+ -+ -+ -+ -+ LPTIM_CR -+ LPTIM_CR -+ LPTIM control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLE -+ ENABLE -+ 0 -+ 1 -+ -+ -+ SNGSTRT -+ SNGSTRT -+ 1 -+ 1 -+ -+ -+ CNTSTRT -+ CNTSTRT -+ 2 -+ 1 -+ -+ -+ COUNTRST -+ COUNTRST -+ 3 -+ 1 -+ -+ -+ RSTARE -+ RSTARE -+ 4 -+ 1 -+ -+ -+ -+ -+ LPTIM_CMP -+ LPTIM_CMP -+ LPTIM compare register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMP -+ CMP -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_ARR -+ LPTIM_ARR -+ LPTIM autoreload register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CNT -+ LPTIM_CNT -+ LPTIM counter register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CFGR2 -+ LPTIM_CFGR2 -+ LPTIM configuration register 2 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IN1SEL -+ IN1SEL -+ 0 -+ 2 -+ -+ -+ IN2SEL -+ IN2SEL -+ 4 -+ 2 -+ -+ -+ -+ -+ LPTIM_VERR -+ LPTIM_VERR -+ LPTIM peripheral version identification register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ LPTIM_PIDR -+ LPTIM_PIDR -+ LPTIM peripheral type identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120011 -+ -+ -+ P_ID -+ P_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ LPTIM_SIDR -+ LPTIM_SIDR -+ LPTIM registers map size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ S_ID -+ S_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ -+ SYSCFG -+ SYSCFG -+ SYSCFG -+ 0x50020000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ SYSCFG_BOOTR -+ SYSCFG_BOOTR -+ This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. ) -+ 0x0 -+ 0x20 -+ 0x00000000 -+ -+ -+ BOOT0 -+ BOOT0 -+ 0 -+ 1 -+ read-only -+ -+ -+ BOOT1 -+ BOOT1 -+ 1 -+ 1 -+ read-only -+ -+ -+ BOOT2 -+ BOOT2 -+ 2 -+ 1 -+ read-only -+ -+ -+ BOOT0_PD -+ BOOT0_PD -+ 4 -+ 1 -+ read-write -+ -+ -+ BOOT1_PD -+ BOOT1_PD -+ 5 -+ 1 -+ read-write -+ -+ -+ BOOT2_PD -+ BOOT2_PD -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ SYSCFG_PMCSETR -+ SYSCFG_PMCSETR -+ SYSCFG peripheral mode configuration set register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2C1_FMP -+ I2C1_FMP -+ 0 -+ 1 -+ -+ -+ I2C2_FMP -+ I2C2_FMP -+ 1 -+ 1 -+ -+ -+ I2C3_FMP -+ I2C3_FMP -+ 2 -+ 1 -+ -+ -+ I2C4_FMP -+ I2C4_FMP -+ 3 -+ 1 -+ -+ -+ I2C5_FMP -+ I2C5_FMP -+ 4 -+ 1 -+ -+ -+ I2C6_FMP -+ I2C6_FMP -+ 5 -+ 1 -+ -+ -+ EN_BOOSTER -+ EN_BOOSTER -+ 8 -+ 1 -+ -+ -+ ANASWVDD -+ ANASWVDD -+ 9 -+ 1 -+ -+ -+ ETH_CLK_SEL -+ ETH_CLK_SEL -+ 16 -+ 1 -+ -+ -+ ETH_REF_CLK_SEL -+ ETH_REF_CLK_SEL -+ 17 -+ 1 -+ -+ -+ ETH_SELMII -+ ETH_SELMII -+ 20 -+ 1 -+ -+ -+ ETH_SEL -+ ETH_SEL -+ 21 -+ 3 -+ -+ -+ ANA0_SEL -+ ANA0_SEL -+ 24 -+ 1 -+ -+ -+ ANA1_SEL -+ ANA1_SEL -+ 25 -+ 1 -+ -+ -+ -+ -+ SYSCFG_IOCTRLSETR -+ SYSCFG_IOCTRLSETR -+ SYSCFG IO control register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HSLVEN_TRACE -+ HSLVEN_TRACE -+ 0 -+ 1 -+ -+ -+ HSLVEN_QUADSPI -+ HSLVEN_QUADSPI -+ 1 -+ 1 -+ -+ -+ HSLVEN_ETH -+ HSLVEN_ETH -+ 2 -+ 1 -+ -+ -+ HSLVEN_SDMMC -+ HSLVEN_SDMMC -+ 3 -+ 1 -+ -+ -+ HSLVEN_SPI -+ HSLVEN_SPI -+ 4 -+ 1 -+ -+ -+ -+ -+ SYSCFG_ICNR -+ SYSCFG_ICNR -+ SYSCFG interconnect control register -+ 0x1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ AXI_M0 -+ AXI_M0 -+ 0 -+ 1 -+ -+ -+ AXI_M1 -+ AXI_M1 -+ 1 -+ 1 -+ -+ -+ AXI_M2 -+ AXI_M2 -+ 2 -+ 1 -+ -+ -+ AXI_M3 -+ AXI_M3 -+ 3 -+ 1 -+ -+ -+ AXI_M5 -+ AXI_M5 -+ 5 -+ 1 -+ -+ -+ AXI_M6 -+ AXI_M6 -+ 6 -+ 1 -+ -+ -+ AXI_M7 -+ AXI_M7 -+ 7 -+ 1 -+ -+ -+ AXI_M8 -+ AXI_M8 -+ 8 -+ 1 -+ -+ -+ AXI_M9 -+ AXI_M9 -+ 9 -+ 1 -+ -+ -+ AXI_M10 -+ AXI_M10 -+ 10 -+ 1 -+ -+ -+ -+ -+ SYSCFG_CMPCR -+ SYSCFG_CMPCR -+ SYSCFG compensation cell control register -+ 0x20 -+ 0x20 -+ 0x00870000 -+ -+ -+ SW_CTRL -+ SW_CTRL -+ 1 -+ 1 -+ read-write -+ -+ -+ READY -+ READY -+ 8 -+ 1 -+ read-only -+ -+ -+ RANSRC -+ RANSRC -+ 16 -+ 4 -+ read-write -+ -+ -+ RAPSRC -+ RAPSRC -+ 20 -+ 4 -+ read-write -+ -+ -+ ANSRC -+ ANSRC -+ 24 -+ 4 -+ read-only -+ -+ -+ APSRC -+ APSRC -+ 28 -+ 4 -+ read-only -+ -+ -+ -+ -+ SYSCFG_CMPENSETR -+ SYSCFG_CMPENSETR -+ SYSCFG compensation cell enable set register -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPU_EN -+ MPU_EN -+ 0 -+ 1 -+ -+ -+ MCU_EN -+ MCU_EN -+ 1 -+ 1 -+ -+ -+ -+ -+ SYSCFG_CMPENCLRR -+ SYSCFG_CMPENCLRR -+ SYSCFG compensation cell enable set register -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPU_EN -+ MPU_EN -+ 0 -+ 1 -+ -+ -+ MCU_EN -+ MCU_EN -+ 1 -+ 1 -+ -+ -+ -+ -+ SYSCFG_CBR -+ SYSCFG_CBR -+ SYSCFG control timer break register -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLL -+ CLL -+ 0 -+ 1 -+ -+ -+ PVDL -+ PVDL -+ 2 -+ 1 -+ -+ -+ -+ -+ SYSCFG_PMCCLRR -+ SYSCFG_PMCCLRR -+ SYSCFG peripheral mode configuration clear register -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2C1_FMP -+ I2C1_FMP -+ 0 -+ 1 -+ -+ -+ I2C2_FMP -+ I2C2_FMP -+ 1 -+ 1 -+ -+ -+ I2C3_FMP -+ I2C3_FMP -+ 2 -+ 1 -+ -+ -+ I2C4_FMP -+ I2C4_FMP -+ 3 -+ 1 -+ -+ -+ I2C5_FMP -+ I2C5_FMP -+ 4 -+ 1 -+ -+ -+ I2C6_FMP -+ I2C6_FMP -+ 5 -+ 1 -+ -+ -+ EN_BOOSTER -+ EN_BOOSTER -+ 8 -+ 1 -+ -+ -+ ANASWVDD -+ ANASWVDD -+ 9 -+ 1 -+ -+ -+ ETH_CLK_SEL -+ ETH_CLK_SEL -+ 16 -+ 1 -+ -+ -+ ETH_REF_CLK_SEL -+ ETH_REF_CLK_SEL -+ 17 -+ 1 -+ -+ -+ ETH_SELMII -+ ETH_SELMII -+ 20 -+ 1 -+ -+ -+ ETH_SEL -+ ETH_SEL -+ 21 -+ 3 -+ -+ -+ ANA0_SEL -+ ANA0_SEL -+ 24 -+ 1 -+ -+ -+ ANA1_SEL -+ ANA1_SEL -+ 25 -+ 1 -+ -+ -+ -+ -+ SYSCFG_IOCTRLCLRR -+ SYSCFG_IOCTRLCLRR -+ SYSCFG IO control register -+ 0x58 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HSLVEN_TRACE -+ HSLVEN_TRACE -+ 0 -+ 1 -+ -+ -+ HSLVEN_QUADSPI -+ HSLVEN_QUADSPI -+ 1 -+ 1 -+ -+ -+ HSLVEN_ETH -+ HSLVEN_ETH -+ 2 -+ 1 -+ -+ -+ HSLVEN_SDMMC -+ HSLVEN_SDMMC -+ 3 -+ 1 -+ -+ -+ HSLVEN_SPI -+ HSLVEN_SPI -+ 4 -+ 1 -+ -+ -+ -+ -+ SYSCFG_VERR -+ SYSCFG_VERR -+ SYSCFG version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ SYSCFG_IPIDR -+ SYSCFG_IPIDR -+ SYSCFG identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00030001 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ SYSCFG_SIDR -+ SYSCFG_SIDR -+ SYSCFG size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ LPTIM3 -+ LPTIM3 -+ LPTIM3 -+ 0x50022000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ LPTIM3_CFGR2 -+ LPTIM3_CFGR2 -+ LPTIM3 configuration register 2 -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IN1SEL -+ IN1SEL -+ 0 -+ 2 -+ -+ -+ -+ -+ LPTIM_ISR -+ LPTIM_ISR -+ LPTIM interrupt and status register -+ 0x0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CMPM -+ CMPM -+ 0 -+ 1 -+ -+ -+ ARRM -+ ARRM -+ 1 -+ 1 -+ -+ -+ EXTTRIG -+ EXTTRIG -+ 2 -+ 1 -+ -+ -+ CMPOK -+ CMPOK -+ 3 -+ 1 -+ -+ -+ ARROK -+ ARROK -+ 4 -+ 1 -+ -+ -+ UP -+ UP -+ 5 -+ 1 -+ -+ -+ DOWN -+ DOWN -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_ICR -+ LPTIM_ICR -+ LPTIM interrupt clear register -+ 0x4 -+ 0x20 -+ write-only -+ 0x00000000 -+ -+ -+ CMPMCF -+ CMPMCF -+ 0 -+ 1 -+ -+ -+ ARRMCF -+ ARRMCF -+ 1 -+ 1 -+ -+ -+ EXTTRIGCF -+ EXTTRIGCF -+ 2 -+ 1 -+ -+ -+ CMPOKCF -+ CMPOKCF -+ 3 -+ 1 -+ -+ -+ ARROKCF -+ ARROKCF -+ 4 -+ 1 -+ -+ -+ UPCF -+ UPCF -+ 5 -+ 1 -+ -+ -+ DOWNCF -+ DOWNCF -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_IER -+ LPTIM_IER -+ LPTIM interrupt enable register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMPMIE -+ CMPMIE -+ 0 -+ 1 -+ -+ -+ ARRMIE -+ ARRMIE -+ 1 -+ 1 -+ -+ -+ EXTTRIGIE -+ EXTTRIGIE -+ 2 -+ 1 -+ -+ -+ CMPOKIE -+ CMPOKIE -+ 3 -+ 1 -+ -+ -+ ARROKIE -+ ARROKIE -+ 4 -+ 1 -+ -+ -+ UPIE -+ UPIE -+ 5 -+ 1 -+ -+ -+ DOWNIE -+ DOWNIE -+ 6 -+ 1 -+ -+ -+ -+ -+ LPTIM_CFGR -+ LPTIM_CFGR -+ LPTIM configuration register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKSEL -+ CKSEL -+ 0 -+ 1 -+ -+ -+ CKPOL -+ CKPOL -+ 1 -+ 2 -+ -+ -+ CKFLT -+ CKFLT -+ 3 -+ 2 -+ -+ -+ TRGFLT -+ TRGFLT -+ 6 -+ 2 -+ -+ -+ PRESC -+ PRESC -+ 9 -+ 3 -+ -+ -+ TRIGSEL -+ TRIGSEL -+ 13 -+ 3 -+ -+ -+ TRIGEN -+ TRIGEN -+ 17 -+ 2 -+ -+ -+ TIMOUT -+ TIMOUT -+ 19 -+ 1 -+ -+ -+ WAVE -+ WAVE -+ 20 -+ 1 -+ -+ -+ WAVPOL -+ WAVPOL -+ 21 -+ 1 -+ -+ -+ PRELOAD -+ PRELOAD -+ 22 -+ 1 -+ -+ -+ COUNTMODE -+ COUNTMODE -+ 23 -+ 1 -+ -+ -+ ENC -+ ENC -+ 24 -+ 1 -+ -+ -+ -+ -+ LPTIM_CR -+ LPTIM_CR -+ LPTIM control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ENABLE -+ ENABLE -+ 0 -+ 1 -+ -+ -+ SNGSTRT -+ SNGSTRT -+ 1 -+ 1 -+ -+ -+ CNTSTRT -+ CNTSTRT -+ 2 -+ 1 -+ -+ -+ COUNTRST -+ COUNTRST -+ 3 -+ 1 -+ -+ -+ RSTARE -+ RSTARE -+ 4 -+ 1 -+ -+ -+ -+ -+ LPTIM_CMP -+ LPTIM_CMP -+ LPTIM compare register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CMP -+ CMP -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_ARR -+ LPTIM_ARR -+ LPTIM autoreload register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_CNT -+ LPTIM_CNT -+ LPTIM counter register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ -+ -+ -+ -+ LPTIM_VERR -+ LPTIM_VERR -+ LPTIM peripheral version identification register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000014 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ LPTIM_PIDR -+ LPTIM_PIDR -+ LPTIM peripheral type identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120011 -+ -+ -+ P_ID -+ P_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ LPTIM_SIDR -+ LPTIM_SIDR -+ LPTIM registers map size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ S_ID -+ S_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ LPTIM3_HWCFGR -+ LPTIM3_HWCFGR -+ LPTIM 3 peripheral hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000804 -+ -+ -+ CFG1 -+ CFG1 -+ 0 -+ 8 -+ -+ -+ CFG2 -+ CFG2 -+ 8 -+ 8 -+ -+ -+ CFG3 -+ CFG3 -+ 16 -+ 4 -+ -+ -+ CFG4 -+ CFG4 -+ 24 -+ 8 -+ -+ -+ -+ -+ -+ -+ PWR -+ PWR -+ PWR -+ 0x50001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ PWR_CR1 -+ PWR_CR1 -+ Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPDS -+ LPDS -+ 0 -+ 1 -+ -+ -+ LPCFG -+ LPCFG -+ 1 -+ 1 -+ -+ -+ LVDS -+ LVDS -+ 2 -+ 1 -+ -+ -+ PVDEN -+ PVDEN -+ 4 -+ 1 -+ -+ -+ PLS -+ PLS -+ 5 -+ 3 -+ -+ -+ DBP -+ DBP -+ 8 -+ 1 -+ -+ -+ AVDEN -+ AVDEN -+ 16 -+ 1 -+ -+ -+ ALS -+ ALS -+ 17 -+ 2 -+ -+ -+ -+ -+ PWR_CSR1 -+ PWR_CSR1 -+ Reset on any system reset. -+ 0x4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PVDO -+ PVDO -+ 4 -+ 1 -+ -+ -+ AVDO -+ AVDO -+ 16 -+ 1 -+ -+ -+ -+ -+ PWR_CR2 -+ PWR_CR2 -+ Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x8 -+ 0x20 -+ 0x00000000 -+ -+ -+ BREN -+ BREN -+ 0 -+ 1 -+ read-write -+ -+ -+ RREN -+ RREN -+ 1 -+ 1 -+ read-write -+ -+ -+ MONEN -+ MONEN -+ 4 -+ 1 -+ read-write -+ -+ -+ BRRDY -+ BRRDY -+ 16 -+ 1 -+ read-only -+ -+ -+ RRRDY -+ RRRDY -+ 17 -+ 1 -+ read-only -+ -+ -+ VBATL -+ VBATL -+ 20 -+ 1 -+ read-only -+ -+ -+ VBATH -+ VBATH -+ 21 -+ 1 -+ read-only -+ -+ -+ TEMPL -+ TEMPL -+ 22 -+ 1 -+ read-only -+ -+ -+ TEMPH -+ TEMPH -+ 23 -+ 1 -+ read-only -+ -+ -+ -+ -+ PWR_CR3 -+ PWR_CR3 -+ Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0xC -+ 0x20 -+ 0x50000000 -+ -+ -+ VBE -+ VBE -+ 8 -+ 1 -+ read-write -+ -+ -+ VBRS -+ VBRS -+ 9 -+ 1 -+ read-write -+ -+ -+ DDRSREN -+ DDRSREN -+ 10 -+ 1 -+ read-write -+ -+ -+ DDRSRDIS -+ DDRSRDIS -+ 11 -+ 1 -+ read-write -+ -+ -+ DDRRETEN -+ DDRRETEN -+ 12 -+ 1 -+ read-write -+ -+ -+ POPL -+ POPL -+ 17 -+ 5 -+ read-write -+ -+ -+ USB33DEN -+ USB33DEN -+ 24 -+ 1 -+ read-write -+ -+ -+ USB33RDY -+ USB33RDY -+ 26 -+ 1 -+ read-only -+ -+ -+ REG18EN -+ REG18EN -+ 28 -+ 1 -+ read-write -+ -+ -+ REG18RDY -+ REG18RDY -+ 29 -+ 1 -+ read-only -+ -+ -+ REG11EN -+ REG11EN -+ 30 -+ 1 -+ read-write -+ -+ -+ REG11RDY -+ REG11RDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ PWR_MPUCR -+ PWR_MPUCR -+ See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x10 -+ 0x20 -+ 0x00000000 -+ -+ -+ PDDS -+ PDDS -+ 0 -+ 1 -+ read-write -+ -+ -+ CSTBYDIS -+ CSTBYDIS -+ 3 -+ 1 -+ read-write -+ -+ -+ STOPF -+ STOPF -+ 5 -+ 1 -+ read-only -+ -+ -+ SBF -+ SBF -+ 6 -+ 1 -+ read-only -+ -+ -+ SBFMPU -+ SBFMPU -+ 7 -+ 1 -+ read-only -+ -+ -+ CSSF -+ CSSF -+ 9 -+ 1 -+ read-write -+ -+ -+ STANDBYWFIL2 -+ STANDBYWFIL2 -+ 15 -+ 1 -+ read-only -+ -+ -+ -+ -+ PWR_MCUCR -+ PWR_MCUCR -+ See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x14 -+ 0x20 -+ 0x00000000 -+ -+ -+ PDDS -+ PDDS -+ 0 -+ 1 -+ read-write -+ -+ -+ STOPF -+ STOPF -+ 5 -+ 1 -+ read-only -+ -+ -+ SBF -+ SBF -+ 6 -+ 1 -+ read-only -+ -+ -+ CSSF -+ CSSF -+ 9 -+ 1 -+ read-write -+ -+ -+ DEEPSLEEP -+ DEEPSLEEP -+ 15 -+ 1 -+ read-only -+ -+ -+ -+ -+ PWR_WKUPCR -+ PWR_WKUPCR -+ Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WKUPC1 -+ WKUPC1 -+ 0 -+ 1 -+ -+ -+ WKUPC2 -+ WKUPC2 -+ 1 -+ 1 -+ -+ -+ WKUPC3 -+ WKUPC3 -+ 2 -+ 1 -+ -+ -+ WKUPC4 -+ WKUPC4 -+ 3 -+ 1 -+ -+ -+ WKUPC5 -+ WKUPC5 -+ 4 -+ 1 -+ -+ -+ WKUPC6 -+ WKUPC6 -+ 5 -+ 1 -+ -+ -+ WKUPP1 -+ WKUPP1 -+ 8 -+ 1 -+ -+ -+ WKUPP2 -+ WKUPP2 -+ 9 -+ 1 -+ -+ -+ WKUPP3 -+ WKUPP3 -+ 10 -+ 1 -+ -+ -+ WKUPP4 -+ WKUPP4 -+ 11 -+ 1 -+ -+ -+ WKUPP5 -+ WKUPP5 -+ 12 -+ 1 -+ -+ -+ WKUPP6 -+ WKUPP6 -+ 13 -+ 1 -+ -+ -+ WKUPPUPD1 -+ WKUPPUPD1 -+ 16 -+ 2 -+ -+ -+ WKUPPUPD2 -+ WKUPPUPD2 -+ 18 -+ 2 -+ -+ -+ WKUPPUPD3 -+ WKUPPUPD3 -+ 20 -+ 2 -+ -+ -+ WKUPPUPD4 -+ WKUPPUPD4 -+ 22 -+ 2 -+ -+ -+ WKUPPUPD5 -+ WKUPPUPD5 -+ 24 -+ 2 -+ -+ -+ WKUPPUPD6 -+ WKUPPUPD6 -+ 26 -+ 2 -+ -+ -+ -+ -+ PWR_WKUPFR -+ PWR_WKUPFR -+ Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) -+ 0x24 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WKUPF1 -+ WKUPF1 -+ 0 -+ 1 -+ -+ -+ WKUPF2 -+ WKUPF2 -+ 1 -+ 1 -+ -+ -+ WKUPF3 -+ WKUPF3 -+ 2 -+ 1 -+ -+ -+ WKUPF4 -+ WKUPF4 -+ 3 -+ 1 -+ -+ -+ WKUPF5 -+ WKUPF5 -+ 4 -+ 1 -+ -+ -+ WKUPF6 -+ WKUPF6 -+ 5 -+ 1 -+ -+ -+ -+ -+ PWR_MPUWKUPENR -+ PWR_MPUWKUPENR -+ Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WKUPEN1 -+ WKUPEN1 -+ 0 -+ 1 -+ -+ -+ WKUPEN2 -+ WKUPEN2 -+ 1 -+ 1 -+ -+ -+ WKUPEN3 -+ WKUPEN3 -+ 2 -+ 1 -+ -+ -+ WKUPEN4 -+ WKUPEN4 -+ 3 -+ 1 -+ -+ -+ WKUPEN5 -+ WKUPEN5 -+ 4 -+ 1 -+ -+ -+ WKUPEN6 -+ WKUPEN6 -+ 5 -+ 1 -+ -+ -+ -+ -+ PWR_MCUWKUPENR -+ PWR_MCUWKUPENR -+ Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed. -+ 0x2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ WKUPEN1 -+ WKUPEN1 -+ 0 -+ 1 -+ -+ -+ WKUPEN2 -+ WKUPEN2 -+ 1 -+ 1 -+ -+ -+ WKUPEN3 -+ WKUPEN3 -+ 2 -+ 1 -+ -+ -+ WKUPEN4 -+ WKUPEN4 -+ 3 -+ 1 -+ -+ -+ WKUPEN5 -+ WKUPEN5 -+ 4 -+ 1 -+ -+ -+ WKUPEN6 -+ WKUPEN6 -+ 5 -+ 1 -+ -+ -+ -+ -+ PWR_VER -+ PWR_VER -+ PWR IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ PWR_ID -+ PWR_ID -+ PWR IP identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00010001 -+ -+ -+ IPID -+ IPID -+ 0 -+ 32 -+ -+ -+ -+ -+ PWR_SID -+ PWR_SID -+ PWR size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ RCC -+ RCC -+ RCC -+ 0x50000000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ RCC -+ RCC global interrupt -+ 5 -+ -+ -+ RCC_WAKEUP -+ RCC MPU wakeup interrupt -+ 145 -+ -+ -+ -+ RCC_TZCR -+ RCC_TZCR -+ This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode. -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ TZEN -+ TZEN -+ 0 -+ 1 -+ -+ -+ MCKPROT -+ MCKPROT -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_OCENSETR -+ RCC_OCENSETR -+ This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0xC -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ HSION -+ HSION -+ 0 -+ 1 -+ -+ -+ HSIKERON -+ HSIKERON -+ 1 -+ 1 -+ -+ -+ CSION -+ CSION -+ 4 -+ 1 -+ -+ -+ CSIKERON -+ CSIKERON -+ 5 -+ 1 -+ -+ -+ DIGBYP -+ DIGBYP -+ 7 -+ 1 -+ -+ -+ HSEON -+ HSEON -+ 8 -+ 1 -+ -+ -+ HSEKERON -+ HSEKERON -+ 9 -+ 1 -+ -+ -+ HSEBYP -+ HSEBYP -+ 10 -+ 1 -+ -+ -+ HSECSSON -+ HSECSSON -+ 11 -+ 1 -+ -+ -+ -+ -+ RCC_OCENCLRR -+ RCC_OCENCLRR -+ This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ HSION -+ HSION -+ 0 -+ 1 -+ -+ -+ HSIKERON -+ HSIKERON -+ 1 -+ 1 -+ -+ -+ CSION -+ CSION -+ 4 -+ 1 -+ -+ -+ CSIKERON -+ CSIKERON -+ 5 -+ 1 -+ -+ -+ DIGBYP -+ DIGBYP -+ 7 -+ 1 -+ -+ -+ HSEON -+ HSEON -+ 8 -+ 1 -+ -+ -+ HSEKERON -+ HSEKERON -+ 9 -+ 1 -+ -+ -+ HSEBYP -+ HSEBYP -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_HSICFGR -+ RCC_HSICFGR -+ This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x18 -+ 0x20 -+ 0x00000000 -+ -+ -+ HSIDIV -+ HSIDIV -+ 0 -+ 2 -+ read-write -+ -+ -+ HSITRIM -+ HSITRIM -+ 8 -+ 7 -+ read-write -+ -+ -+ HSICAL -+ HSICAL -+ 16 -+ 12 -+ read-only -+ -+ -+ -+ -+ RCC_CSICFGR -+ RCC_CSICFGR -+ This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details. -+ 0x1C -+ 0x20 -+ 0x00001000 -+ -+ -+ CSITRIM -+ CSITRIM -+ 8 -+ 5 -+ read-write -+ -+ -+ CSICAL -+ CSICAL -+ 16 -+ 8 -+ read-only -+ -+ -+ -+ -+ RCC_MPCKSELR -+ RCC_MPCKSELR -+ This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x20 -+ 0x20 -+ 0x80000000 -+ -+ -+ MPUSRC -+ MPUSRC -+ 0 -+ 2 -+ read-write -+ -+ -+ MPUSRCRDY -+ MPUSRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_ASSCKSELR -+ RCC_ASSCKSELR -+ This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x24 -+ 0x20 -+ 0x80000000 -+ -+ -+ AXISSRC -+ AXISSRC -+ 0 -+ 3 -+ read-write -+ -+ -+ AXISSRCRDY -+ AXISSRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_RCK12SELR -+ RCC_RCK12SELR -+ This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x28 -+ 0x20 -+ 0x80000000 -+ -+ -+ PLL12SRC -+ PLL12SRC -+ 0 -+ 2 -+ read-write -+ -+ -+ PLL12SRCRDY -+ PLL12SRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_MPCKDIVR -+ RCC_MPCKDIVR -+ This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. -+ 0x2C -+ 0x20 -+ 0x80000001 -+ -+ -+ MPUDIV -+ MPUDIV -+ 0 -+ 3 -+ read-write -+ -+ -+ MPUDIVRDY -+ MPUDIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_AXIDIVR -+ RCC_AXIDIVR -+ This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. -+ 0x30 -+ 0x20 -+ 0x80000000 -+ -+ -+ AXIDIV -+ AXIDIV -+ 0 -+ 3 -+ read-write -+ -+ -+ AXIDIVRDY -+ AXIDIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_APB4DIVR -+ RCC_APB4DIVR -+ This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. -+ 0x3C -+ 0x20 -+ 0x80000000 -+ -+ -+ APB4DIV -+ APB4DIV -+ 0 -+ 3 -+ read-write -+ -+ -+ APB4DIVRDY -+ APB4DIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_APB5DIVR -+ RCC_APB5DIVR -+ This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. -+ 0x40 -+ 0x20 -+ 0x80000000 -+ -+ -+ APB5DIV -+ APB5DIV -+ 0 -+ 3 -+ read-write -+ -+ -+ APB5DIVRDY -+ APB5DIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_RTCDIVR -+ RCC_RTCDIVR -+ This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RTCDIV -+ RTCDIV -+ 0 -+ 6 -+ -+ -+ -+ -+ RCC_MSSCKSELR -+ RCC_MSSCKSELR -+ This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x48 -+ 0x20 -+ 0x80000000 -+ -+ -+ MCUSSRC -+ MCUSSRC -+ 0 -+ 2 -+ read-write -+ -+ -+ MCUSSRCRDY -+ MCUSSRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_PLL1CR -+ RCC_PLL1CR -+ This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x80 -+ 0x20 -+ 0x00000000 -+ -+ -+ PLLON -+ PLLON -+ 0 -+ 1 -+ read-write -+ -+ -+ PLL1RDY -+ PLL1RDY -+ 1 -+ 1 -+ read-only -+ -+ -+ SSCG_CTRL -+ SSCG_CTRL -+ 2 -+ 1 -+ read-write -+ -+ -+ DIVPEN -+ DIVPEN -+ 4 -+ 1 -+ read-write -+ -+ -+ DIVQEN -+ DIVQEN -+ 5 -+ 1 -+ read-write -+ -+ -+ DIVREN -+ DIVREN -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RCC_PLL1CFGR1 -+ RCC_PLL1CFGR1 -+ This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x84 -+ 0x20 -+ read-write -+ 0x00010031 -+ -+ -+ DIVN -+ DIVN -+ 0 -+ 9 -+ -+ -+ DIVM1 -+ DIVM1 -+ 16 -+ 6 -+ -+ -+ -+ -+ RCC_PLL1CFGR2 -+ RCC_PLL1CFGR2 -+ This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x88 -+ 0x20 -+ read-write -+ 0x00010100 -+ -+ -+ DIVP -+ DIVP -+ 0 -+ 7 -+ -+ -+ DIVQ -+ DIVQ -+ 8 -+ 7 -+ -+ -+ DIVR -+ DIVR -+ 16 -+ 7 -+ -+ -+ -+ -+ RCC_PLL1FRACR -+ RCC_PLL1FRACR -+ This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FRACV -+ FRACV -+ 3 -+ 13 -+ -+ -+ FRACLE -+ FRACLE -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_PLL1CSGR -+ RCC_PLL1CSGR -+ This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MOD_PER -+ MOD_PER -+ 0 -+ 13 -+ -+ -+ TPDFN_DIS -+ TPDFN_DIS -+ 13 -+ 1 -+ -+ -+ RPDFN_DIS -+ RPDFN_DIS -+ 14 -+ 1 -+ -+ -+ SSCG_MODE -+ SSCG_MODE -+ 15 -+ 1 -+ -+ -+ INC_STEP -+ INC_STEP -+ 16 -+ 15 -+ -+ -+ -+ -+ RCC_PLL2CR -+ RCC_PLL2CR -+ This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x94 -+ 0x20 -+ 0x00000000 -+ -+ -+ PLLON -+ PLLON -+ 0 -+ 1 -+ read-write -+ -+ -+ PLL2RDY -+ PLL2RDY -+ 1 -+ 1 -+ read-only -+ -+ -+ SSCG_CTRL -+ SSCG_CTRL -+ 2 -+ 1 -+ read-write -+ -+ -+ DIVPEN -+ DIVPEN -+ 4 -+ 1 -+ read-write -+ -+ -+ DIVQEN -+ DIVQEN -+ 5 -+ 1 -+ read-write -+ -+ -+ DIVREN -+ DIVREN -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RCC_PLL2CFGR1 -+ RCC_PLL2CFGR1 -+ This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x98 -+ 0x20 -+ read-write -+ 0x00010063 -+ -+ -+ DIVN -+ DIVN -+ 0 -+ 9 -+ -+ -+ DIVM2 -+ DIVM2 -+ 16 -+ 6 -+ -+ -+ -+ -+ RCC_PLL2CFGR2 -+ RCC_PLL2CFGR2 -+ This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0x9C -+ 0x20 -+ read-write -+ 0x00010101 -+ -+ -+ DIVP -+ DIVP -+ 0 -+ 7 -+ -+ -+ DIVQ -+ DIVQ -+ 8 -+ 7 -+ -+ -+ DIVR -+ DIVR -+ 16 -+ 7 -+ -+ -+ -+ -+ RCC_PLL2FRACR -+ RCC_PLL2FRACR -+ This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0xA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FRACV -+ FRACV -+ 3 -+ 13 -+ -+ -+ FRACLE -+ FRACLE -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_PLL2CSGR -+ RCC_PLL2CSGR -+ This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. -+ 0xA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MOD_PER -+ MOD_PER -+ 0 -+ 13 -+ -+ -+ TPDFN_DIS -+ TPDFN_DIS -+ 13 -+ 1 -+ -+ -+ RPDFN_DIS -+ RPDFN_DIS -+ 14 -+ 1 -+ -+ -+ SSCG_MODE -+ SSCG_MODE -+ 15 -+ 1 -+ -+ -+ INC_STEP -+ INC_STEP -+ 16 -+ 15 -+ -+ -+ -+ -+ RCC_I2C46CKSELR -+ RCC_I2C46CKSELR -+ This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. -+ 0xC0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2C46SRC -+ I2C46SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SPI6CKSELR -+ RCC_SPI6CKSELR -+ This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. -+ 0xC4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6SRC -+ SPI6SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_UART1CKSELR -+ RCC_UART1CKSELR -+ This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. -+ 0xC8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UART1SRC -+ UART1SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_RNG1CKSELR -+ RCC_RNG1CKSELR -+ This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. -+ 0xCC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RNG1SRC -+ RNG1SRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_CPERCKSELR -+ RCC_CPERCKSELR -+ This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays. -+ 0xD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CKPERSRC -+ CKPERSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_STGENCKSELR -+ RCC_STGENCKSELR -+ This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. -+ 0xD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ STGENSRC -+ STGENSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_DDRITFCR -+ RCC_DDRITFCR -+ This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode. -+ 0xD8 -+ 0x20 -+ read-write -+ 0x000FD02A -+ -+ -+ DDRC1EN -+ DDRC1EN -+ 0 -+ 1 -+ -+ -+ DDRC1LPEN -+ DDRC1LPEN -+ 1 -+ 1 -+ -+ -+ DDRC2EN -+ DDRC2EN -+ 2 -+ 1 -+ -+ -+ DDRC2LPEN -+ DDRC2LPEN -+ 3 -+ 1 -+ -+ -+ DDRPHYCEN -+ DDRPHYCEN -+ 4 -+ 1 -+ -+ -+ DDRPHYCLPEN -+ DDRPHYCLPEN -+ 5 -+ 1 -+ -+ -+ DDRCAPBEN -+ DDRCAPBEN -+ 6 -+ 1 -+ -+ -+ DDRCAPBLPEN -+ DDRCAPBLPEN -+ 7 -+ 1 -+ -+ -+ AXIDCGEN -+ AXIDCGEN -+ 8 -+ 1 -+ -+ -+ DDRPHYCAPBEN -+ DDRPHYCAPBEN -+ 9 -+ 1 -+ -+ -+ DDRPHYCAPBLPEN -+ DDRPHYCAPBLPEN -+ 10 -+ 1 -+ -+ -+ KERDCG_DLY -+ KERDCG_DLY -+ 11 -+ 3 -+ -+ -+ DDRCAPBRST -+ DDRCAPBRST -+ 14 -+ 1 -+ -+ -+ DDRCAXIRST -+ DDRCAXIRST -+ 15 -+ 1 -+ -+ -+ DDRCORERST -+ DDRCORERST -+ 16 -+ 1 -+ -+ -+ DPHYAPBRST -+ DPHYAPBRST -+ 17 -+ 1 -+ -+ -+ DPHYRST -+ DPHYRST -+ 18 -+ 1 -+ -+ -+ DPHYCTLRST -+ DPHYCTLRST -+ 19 -+ 1 -+ -+ -+ DDRCKMOD -+ DDRCKMOD -+ 20 -+ 3 -+ -+ -+ GSKPMOD -+ GSKPMOD -+ 23 -+ 1 -+ -+ -+ GSKPCTRL -+ GSKPCTRL -+ 24 -+ 1 -+ -+ -+ DFILP_WIDTH -+ DFILP_WIDTH -+ 25 -+ 3 -+ -+ -+ GSKP_DUR -+ GSKP_DUR -+ 28 -+ 4 -+ -+ -+ -+ -+ RCC_MP_BOOTCR -+ RCC_MP_BOOTCR -+ This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU. -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MCU_BEN -+ MCU_BEN -+ 0 -+ 1 -+ -+ -+ MPU_BEN -+ MPU_BEN -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_MP_SREQSETR -+ RCC_MP_SREQSETR -+ Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ STPREQ_P0 -+ STPREQ_P0 -+ 0 -+ 1 -+ -+ -+ STPREQ_P1 -+ STPREQ_P1 -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_MP_SREQCLRR -+ RCC_MP_SREQCLRR -+ Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ STPREQ_P0 -+ STPREQ_P0 -+ 0 -+ 1 -+ -+ -+ STPREQ_P1 -+ STPREQ_P1 -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_MP_GCR -+ RCC_MP_GCR -+ The register contains global control bits. If TZEN = , this register can only be modified in secure mode. -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BOOT_MCU -+ BOOT_MCU -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APRSTCR -+ RCC_MP_APRSTCR -+ This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode. -+ 0x110 -+ 0x20 -+ read-write -+ 0x00007F00 -+ -+ -+ RDCTLEN -+ RDCTLEN -+ 0 -+ 1 -+ -+ -+ RSTTO -+ RSTTO -+ 8 -+ 7 -+ -+ -+ -+ -+ RCC_MP_APRSTSR -+ RCC_MP_APRSTSR -+ This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode. -+ 0x114 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RSTTOV -+ RSTTOV -+ 8 -+ 7 -+ -+ -+ -+ -+ RCC_BDCR -+ RCC_BDCR -+ This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode. -+ 0x140 -+ 0x20 -+ 0x00000020 -+ -+ -+ LSEON -+ LSEON -+ 0 -+ 1 -+ read-write -+ -+ -+ LSEBYP -+ LSEBYP -+ 1 -+ 1 -+ read-write -+ -+ -+ LSERDY -+ LSERDY -+ 2 -+ 1 -+ read-only -+ -+ -+ DIGBYP -+ DIGBYP -+ 3 -+ 1 -+ read-only -+ -+ -+ LSEDRV -+ LSEDRV -+ 4 -+ 2 -+ read-write -+ -+ -+ LSECSSON -+ LSECSSON -+ 8 -+ 1 -+ read-write -+ -+ -+ LSECSSD -+ LSECSSD -+ 9 -+ 1 -+ read-only -+ -+ -+ RTCSRC -+ RTCSRC -+ 16 -+ 2 -+ read-only -+ -+ -+ RTCCKEN -+ RTCCKEN -+ 20 -+ 1 -+ read-write -+ -+ -+ VSWRST -+ VSWRST -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ RCC_RDLSICR -+ RCC_RDLSICR -+ This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode. -+ 0x144 -+ 0x20 -+ 0x00000000 -+ -+ -+ LSION -+ LSION -+ 0 -+ 1 -+ read-write -+ -+ -+ LSIRDY -+ LSIRDY -+ 1 -+ 1 -+ read-only -+ -+ -+ MRD -+ MRD -+ 16 -+ 5 -+ read-write -+ -+ -+ EADLY -+ EADLY -+ 24 -+ 3 -+ read-write -+ -+ -+ SPARE -+ SPARE -+ 27 -+ 5 -+ read-write -+ -+ -+ -+ -+ RCC_APB4RSTSETR -+ RCC_APB4RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCRST -+ LTDCRST -+ 0 -+ 1 -+ -+ -+ DSIRST -+ DSIRST -+ 4 -+ 1 -+ -+ -+ DDRPERFMRST -+ DDRPERFMRST -+ 8 -+ 1 -+ -+ -+ USBPHYRST -+ USBPHYRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_APB4RSTCLRR -+ RCC_APB4RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCRST -+ LTDCRST -+ 0 -+ 1 -+ -+ -+ DSIRST -+ DSIRST -+ 4 -+ 1 -+ -+ -+ DDRPERFMRST -+ DDRPERFMRST -+ 8 -+ 1 -+ -+ -+ USBPHYRST -+ USBPHYRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_APB5RSTSETR -+ RCC_APB5RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6RST -+ SPI6RST -+ 0 -+ 1 -+ -+ -+ I2C4RST -+ I2C4RST -+ 2 -+ 1 -+ -+ -+ I2C6RST -+ I2C6RST -+ 3 -+ 1 -+ -+ -+ USART1RST -+ USART1RST -+ 4 -+ 1 -+ -+ -+ STGENRST -+ STGENRST -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_APB5RSTCLRR -+ RCC_APB5RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6RST -+ SPI6RST -+ 0 -+ 1 -+ -+ -+ I2C4RST -+ I2C4RST -+ 2 -+ 1 -+ -+ -+ I2C6RST -+ I2C6RST -+ 3 -+ 1 -+ -+ -+ USART1RST -+ USART1RST -+ 4 -+ 1 -+ -+ -+ STGENRST -+ STGENRST -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_AHB5RSTSETR -+ RCC_AHB5RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOZRST -+ GPIOZRST -+ 0 -+ 1 -+ -+ -+ CRYP1RST -+ CRYP1RST -+ 4 -+ 1 -+ -+ -+ HASH1RST -+ HASH1RST -+ 5 -+ 1 -+ -+ -+ RNG1RST -+ RNG1RST -+ 6 -+ 1 -+ -+ -+ AXIMCRST -+ AXIMCRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_AHB5RSTCLRR -+ RCC_AHB5RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOZRST -+ GPIOZRST -+ 0 -+ 1 -+ -+ -+ CRYP1RST -+ CRYP1RST -+ 4 -+ 1 -+ -+ -+ HASH1RST -+ HASH1RST -+ 5 -+ 1 -+ -+ -+ RNG1RST -+ RNG1RST -+ 6 -+ 1 -+ -+ -+ AXIMCRST -+ AXIMCRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_AHB6RSTSETR -+ RCC_AHB6RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. -+ 0x198 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPURST -+ GPURST -+ 5 -+ 1 -+ -+ -+ ETHMACRST -+ ETHMACRST -+ 10 -+ 1 -+ -+ -+ FMCRST -+ FMCRST -+ 12 -+ 1 -+ -+ -+ QSPIRST -+ QSPIRST -+ 14 -+ 1 -+ -+ -+ SDMMC1RST -+ SDMMC1RST -+ 16 -+ 1 -+ -+ -+ SDMMC2RST -+ SDMMC2RST -+ 17 -+ 1 -+ -+ -+ CRC1RST -+ CRC1RST -+ 20 -+ 1 -+ -+ -+ USBHRST -+ USBHRST -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_AHB6RSTCLRR -+ RCC_AHB6RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. -+ 0x19C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ETHMACRST -+ ETHMACRST -+ 10 -+ 1 -+ -+ -+ FMCRST -+ FMCRST -+ 12 -+ 1 -+ -+ -+ QSPIRST -+ QSPIRST -+ 14 -+ 1 -+ -+ -+ SDMMC1RST -+ SDMMC1RST -+ 16 -+ 1 -+ -+ -+ SDMMC2RST -+ SDMMC2RST -+ 17 -+ 1 -+ -+ -+ CRC1RST -+ CRC1RST -+ 20 -+ 1 -+ -+ -+ USBHRST -+ USBHRST -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_TZAHB6RSTSETR -+ RCC_TZAHB6RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMARST -+ MDMARST -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_TZAHB6RSTCLRR -+ RCC_TZAHB6RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. -+ 0x1A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMARST -+ MDMARST -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB4ENSETR -+ RCC_MP_APB4ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCEN -+ LTDCEN -+ 0 -+ 1 -+ -+ -+ DSIEN -+ DSIEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMEN -+ DDRPERFMEN -+ 8 -+ 1 -+ -+ -+ IWDG2APBEN -+ IWDG2APBEN -+ 15 -+ 1 -+ -+ -+ USBPHYEN -+ USBPHYEN -+ 16 -+ 1 -+ -+ -+ STGENROEN -+ STGENROEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB4ENCLRR -+ RCC_MP_APB4ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x204 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCEN -+ LTDCEN -+ 0 -+ 1 -+ -+ -+ DSIEN -+ DSIEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMEN -+ DDRPERFMEN -+ 8 -+ 1 -+ -+ -+ IWDG2APBEN -+ IWDG2APBEN -+ 15 -+ 1 -+ -+ -+ USBPHYEN -+ USBPHYEN -+ 16 -+ 1 -+ -+ -+ STGENROEN -+ STGENROEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB5ENSETR -+ RCC_MP_APB5ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x208 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6EN -+ SPI6EN -+ 0 -+ 1 -+ -+ -+ I2C4EN -+ I2C4EN -+ 2 -+ 1 -+ -+ -+ I2C6EN -+ I2C6EN -+ 3 -+ 1 -+ -+ -+ USART1EN -+ USART1EN -+ 4 -+ 1 -+ -+ -+ RTCAPBEN -+ RTCAPBEN -+ 8 -+ 1 -+ -+ -+ TZC1EN -+ TZC1EN -+ 11 -+ 1 -+ -+ -+ TZC2EN -+ TZC2EN -+ 12 -+ 1 -+ -+ -+ TZPCEN -+ TZPCEN -+ 13 -+ 1 -+ -+ -+ IWDG1APBEN -+ IWDG1APBEN -+ 15 -+ 1 -+ -+ -+ BSECEN -+ BSECEN -+ 16 -+ 1 -+ -+ -+ STGENEN -+ STGENEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB5ENCLRR -+ RCC_MP_APB5ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x20C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6EN -+ SPI6EN -+ 0 -+ 1 -+ -+ -+ I2C4EN -+ I2C4EN -+ 2 -+ 1 -+ -+ -+ I2C6EN -+ I2C6EN -+ 3 -+ 1 -+ -+ -+ USART1EN -+ USART1EN -+ 4 -+ 1 -+ -+ -+ RTCAPBEN -+ RTCAPBEN -+ 8 -+ 1 -+ -+ -+ TZC1EN -+ TZC1EN -+ 11 -+ 1 -+ -+ -+ TZC2EN -+ TZC2EN -+ 12 -+ 1 -+ -+ -+ TZPCEN -+ TZPCEN -+ 13 -+ 1 -+ -+ -+ IWDG1APBEN -+ IWDG1APBEN -+ 15 -+ 1 -+ -+ -+ BSECEN -+ BSECEN -+ 16 -+ 1 -+ -+ -+ STGENEN -+ STGENEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB5ENSETR -+ RCC_MP_AHB5ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x210 -+ 0x20 -+ read-write -+ 0x00010000 -+ -+ -+ GPIOZEN -+ GPIOZEN -+ 0 -+ 1 -+ -+ -+ CRYP1EN -+ CRYP1EN -+ 4 -+ 1 -+ -+ -+ HASH1EN -+ HASH1EN -+ 5 -+ 1 -+ -+ -+ RNG1EN -+ RNG1EN -+ 6 -+ 1 -+ -+ -+ BKPSRAMEN -+ BKPSRAMEN -+ 8 -+ 1 -+ -+ -+ AXIMCEN -+ AXIMCEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB5ENCLRR -+ RCC_MP_AHB5ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x214 -+ 0x20 -+ read-write -+ 0x00010000 -+ -+ -+ GPIOZEN -+ GPIOZEN -+ 0 -+ 1 -+ -+ -+ CRYP1EN -+ CRYP1EN -+ 4 -+ 1 -+ -+ -+ HASH1EN -+ HASH1EN -+ 5 -+ 1 -+ -+ -+ RNG1EN -+ RNG1EN -+ 6 -+ 1 -+ -+ -+ BKPSRAMEN -+ BKPSRAMEN -+ 8 -+ 1 -+ -+ -+ AXIMCEN -+ AXIMCEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB6ENSETR -+ RCC_MP_AHB6ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x218 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ GPUEN -+ GPUEN -+ 5 -+ 1 -+ -+ -+ ETHCKEN -+ ETHCKEN -+ 7 -+ 1 -+ -+ -+ ETHTXEN -+ ETHTXEN -+ 8 -+ 1 -+ -+ -+ ETHRXEN -+ ETHRXEN -+ 9 -+ 1 -+ -+ -+ ETHMACEN -+ ETHMACEN -+ 10 -+ 1 -+ -+ -+ FMCEN -+ FMCEN -+ 12 -+ 1 -+ -+ -+ QSPIEN -+ QSPIEN -+ 14 -+ 1 -+ -+ -+ SDMMC1EN -+ SDMMC1EN -+ 16 -+ 1 -+ -+ -+ SDMMC2EN -+ SDMMC2EN -+ 17 -+ 1 -+ -+ -+ CRC1EN -+ CRC1EN -+ 20 -+ 1 -+ -+ -+ USBHEN -+ USBHEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB6ENCLRR -+ RCC_MP_AHB6ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . -+ 0x21C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ GPUEN -+ GPUEN -+ 5 -+ 1 -+ -+ -+ ETHCKEN -+ ETHCKEN -+ 7 -+ 1 -+ -+ -+ ETHTXEN -+ ETHTXEN -+ 8 -+ 1 -+ -+ -+ ETHRXEN -+ ETHRXEN -+ 9 -+ 1 -+ -+ -+ ETHMACEN -+ ETHMACEN -+ 10 -+ 1 -+ -+ -+ FMCEN -+ FMCEN -+ 12 -+ 1 -+ -+ -+ QSPIEN -+ QSPIEN -+ 14 -+ 1 -+ -+ -+ SDMMC1EN -+ SDMMC1EN -+ 16 -+ 1 -+ -+ -+ SDMMC2EN -+ SDMMC2EN -+ 17 -+ 1 -+ -+ -+ CRC1EN -+ CRC1EN -+ 20 -+ 1 -+ -+ -+ USBHEN -+ USBHEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_TZAHB6ENSETR -+ RCC_MP_TZAHB6ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x220 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_TZAHB6ENCLRR -+ RCC_MP_TZAHB6ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x224 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB4ENSETR -+ RCC_MC_APB4ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0x280 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCEN -+ LTDCEN -+ 0 -+ 1 -+ -+ -+ DSIEN -+ DSIEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMEN -+ DDRPERFMEN -+ 8 -+ 1 -+ -+ -+ USBPHYEN -+ USBPHYEN -+ 16 -+ 1 -+ -+ -+ STGENROEN -+ STGENROEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB4ENCLRR -+ RCC_MC_APB4ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0x284 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LTDCEN -+ LTDCEN -+ 0 -+ 1 -+ -+ -+ DSIEN -+ DSIEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMEN -+ DDRPERFMEN -+ 8 -+ 1 -+ -+ -+ USBPHYEN -+ USBPHYEN -+ 16 -+ 1 -+ -+ -+ STGENROEN -+ STGENROEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB5ENSETR -+ RCC_MC_APB5ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0x288 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6EN -+ SPI6EN -+ 0 -+ 1 -+ -+ -+ I2C4EN -+ I2C4EN -+ 2 -+ 1 -+ -+ -+ I2C6EN -+ I2C6EN -+ 3 -+ 1 -+ -+ -+ USART1EN -+ USART1EN -+ 4 -+ 1 -+ -+ -+ RTCAPBEN -+ RTCAPBEN -+ 8 -+ 1 -+ -+ -+ TZC1EN -+ TZC1EN -+ 11 -+ 1 -+ -+ -+ TZC2EN -+ TZC2EN -+ 12 -+ 1 -+ -+ -+ TZPCEN -+ TZPCEN -+ 13 -+ 1 -+ -+ -+ BSECEN -+ BSECEN -+ 16 -+ 1 -+ -+ -+ STGENEN -+ STGENEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB5ENCLRR -+ RCC_MC_APB5ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0x28C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI6EN -+ SPI6EN -+ 0 -+ 1 -+ -+ -+ I2C4EN -+ I2C4EN -+ 2 -+ 1 -+ -+ -+ I2C6EN -+ I2C6EN -+ 3 -+ 1 -+ -+ -+ USART1EN -+ USART1EN -+ 4 -+ 1 -+ -+ -+ RTCAPBEN -+ RTCAPBEN -+ 8 -+ 1 -+ -+ -+ TZC1EN -+ TZC1EN -+ 11 -+ 1 -+ -+ -+ TZC2EN -+ TZC2EN -+ 12 -+ 1 -+ -+ -+ TZPCEN -+ TZPCEN -+ 13 -+ 1 -+ -+ -+ BSECEN -+ BSECEN -+ 16 -+ 1 -+ -+ -+ STGENEN -+ STGENEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB5ENSETR -+ RCC_MC_AHB5ENSETR -+ This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. -+ 0x290 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOZEN -+ GPIOZEN -+ 0 -+ 1 -+ -+ -+ CRYP1EN -+ CRYP1EN -+ 4 -+ 1 -+ -+ -+ HASH1EN -+ HASH1EN -+ 5 -+ 1 -+ -+ -+ RNG1EN -+ RNG1EN -+ 6 -+ 1 -+ -+ -+ BKPSRAMEN -+ BKPSRAMEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB5ENCLRR -+ RCC_MC_AHB5ENCLRR -+ This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. -+ 0x294 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOZEN -+ GPIOZEN -+ 0 -+ 1 -+ -+ -+ CRYP1EN -+ CRYP1EN -+ 4 -+ 1 -+ -+ -+ HASH1EN -+ HASH1EN -+ 5 -+ 1 -+ -+ -+ RNG1EN -+ RNG1EN -+ 6 -+ 1 -+ -+ -+ BKPSRAMEN -+ BKPSRAMEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB6ENSETR -+ RCC_MC_AHB6ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0x298 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ GPUEN -+ GPUEN -+ 5 -+ 1 -+ -+ -+ ETHCKEN -+ ETHCKEN -+ 7 -+ 1 -+ -+ -+ ETHTXEN -+ ETHTXEN -+ 8 -+ 1 -+ -+ -+ ETHRXEN -+ ETHRXEN -+ 9 -+ 1 -+ -+ -+ ETHMACEN -+ ETHMACEN -+ 10 -+ 1 -+ -+ -+ FMCEN -+ FMCEN -+ 12 -+ 1 -+ -+ -+ QSPIEN -+ QSPIEN -+ 14 -+ 1 -+ -+ -+ SDMMC1EN -+ SDMMC1EN -+ 16 -+ 1 -+ -+ -+ SDMMC2EN -+ SDMMC2EN -+ 17 -+ 1 -+ -+ -+ CRC1EN -+ CRC1EN -+ 20 -+ 1 -+ -+ -+ USBHEN -+ USBHEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB6ENCLRR -+ RCC_MC_AHB6ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0x29C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MDMAEN -+ MDMAEN -+ 0 -+ 1 -+ -+ -+ GPUEN -+ GPUEN -+ 5 -+ 1 -+ -+ -+ ETHCKEN -+ ETHCKEN -+ 7 -+ 1 -+ -+ -+ ETHTXEN -+ ETHTXEN -+ 8 -+ 1 -+ -+ -+ ETHRXEN -+ ETHRXEN -+ 9 -+ 1 -+ -+ -+ ETHMACEN -+ ETHMACEN -+ 10 -+ 1 -+ -+ -+ FMCEN -+ FMCEN -+ 12 -+ 1 -+ -+ -+ QSPIEN -+ QSPIEN -+ 14 -+ 1 -+ -+ -+ SDMMC1EN -+ SDMMC1EN -+ 16 -+ 1 -+ -+ -+ SDMMC2EN -+ SDMMC2EN -+ 17 -+ 1 -+ -+ -+ CRC1EN -+ CRC1EN -+ 20 -+ 1 -+ -+ -+ USBHEN -+ USBHEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB4LPENSETR -+ RCC_MP_APB4LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0x300 -+ 0x20 -+ read-write -+ 0x00118111 -+ -+ -+ LTDCLPEN -+ LTDCLPEN -+ 0 -+ 1 -+ -+ -+ DSILPEN -+ DSILPEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMLPEN -+ DDRPERFMLPEN -+ 8 -+ 1 -+ -+ -+ IWDG2APBLPEN -+ IWDG2APBLPEN -+ 15 -+ 1 -+ -+ -+ USBPHYLPEN -+ USBPHYLPEN -+ 16 -+ 1 -+ -+ -+ STGENROLPEN -+ STGENROLPEN -+ 20 -+ 1 -+ -+ -+ STGENROSTPEN -+ STGENROSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB4LPENCLRR -+ RCC_MP_APB4LPENCLRR -+ This register is used by the MCU -+ 0x304 -+ 0x20 -+ read-write -+ 0x00118111 -+ -+ -+ LTDCLPEN -+ LTDCLPEN -+ 0 -+ 1 -+ -+ -+ DSILPEN -+ DSILPEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMLPEN -+ DDRPERFMLPEN -+ 8 -+ 1 -+ -+ -+ IWDG2APBLPEN -+ IWDG2APBLPEN -+ 15 -+ 1 -+ -+ -+ USBPHYLPEN -+ USBPHYLPEN -+ 16 -+ 1 -+ -+ -+ STGENROLPEN -+ STGENROLPEN -+ 20 -+ 1 -+ -+ -+ STGENROSTPEN -+ STGENROSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB5LPENSETR -+ RCC_MP_APB5LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. -+ 0x308 -+ 0x20 -+ read-write -+ 0x0011391D -+ -+ -+ SPI6LPEN -+ SPI6LPEN -+ 0 -+ 1 -+ -+ -+ I2C4LPEN -+ I2C4LPEN -+ 2 -+ 1 -+ -+ -+ I2C6LPEN -+ I2C6LPEN -+ 3 -+ 1 -+ -+ -+ USART1LPEN -+ USART1LPEN -+ 4 -+ 1 -+ -+ -+ RTCAPBLPEN -+ RTCAPBLPEN -+ 8 -+ 1 -+ -+ -+ TZC1LPEN -+ TZC1LPEN -+ 11 -+ 1 -+ -+ -+ TZC2LPEN -+ TZC2LPEN -+ 12 -+ 1 -+ -+ -+ TZPCLPEN -+ TZPCLPEN -+ 13 -+ 1 -+ -+ -+ IWDG1APBLPEN -+ IWDG1APBLPEN -+ 15 -+ 1 -+ -+ -+ BSECLPEN -+ BSECLPEN -+ 16 -+ 1 -+ -+ -+ STGENLPEN -+ STGENLPEN -+ 20 -+ 1 -+ -+ -+ STGENSTPEN -+ STGENSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB5LPENCLRR -+ RCC_MP_APB5LPENCLRR -+ This register is used by the Mpu. -+ 0x30C -+ 0x20 -+ read-write -+ 0x0011391D -+ -+ -+ SPI6LPEN -+ SPI6LPEN -+ 0 -+ 1 -+ -+ -+ I2C4LPEN -+ I2C4LPEN -+ 2 -+ 1 -+ -+ -+ I2C6LPEN -+ I2C6LPEN -+ 3 -+ 1 -+ -+ -+ USART1LPEN -+ USART1LPEN -+ 4 -+ 1 -+ -+ -+ RTCAPBLPEN -+ RTCAPBLPEN -+ 8 -+ 1 -+ -+ -+ TZC1LPEN -+ TZC1LPEN -+ 11 -+ 1 -+ -+ -+ TZC2LPEN -+ TZC2LPEN -+ 12 -+ 1 -+ -+ -+ TZPCLPEN -+ TZPCLPEN -+ 13 -+ 1 -+ -+ -+ IWDG1APBLPEN -+ IWDG1APBLPEN -+ 15 -+ 1 -+ -+ -+ BSECLPEN -+ BSECLPEN -+ 16 -+ 1 -+ -+ -+ STGENLPEN -+ STGENLPEN -+ 20 -+ 1 -+ -+ -+ STGENSTPEN -+ STGENSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB5LPENSETR -+ RCC_MP_AHB5LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000171 -+ -+ -+ GPIOZLPEN -+ GPIOZLPEN -+ 0 -+ 1 -+ -+ -+ CRYP1LPEN -+ CRYP1LPEN -+ 4 -+ 1 -+ -+ -+ HASH1LPEN -+ HASH1LPEN -+ 5 -+ 1 -+ -+ -+ RNG1LPEN -+ RNG1LPEN -+ 6 -+ 1 -+ -+ -+ BKPSRAMLPEN -+ BKPSRAMLPEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB5LPENCLRR -+ RCC_MP_AHB5LPENCLRR -+ This register is used by the MCU -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000171 -+ -+ -+ GPIOZLPEN -+ GPIOZLPEN -+ 0 -+ 1 -+ -+ -+ CRYP1LPEN -+ CRYP1LPEN -+ 4 -+ 1 -+ -+ -+ HASH1LPEN -+ HASH1LPEN -+ 5 -+ 1 -+ -+ -+ RNG1LPEN -+ RNG1LPEN -+ 6 -+ 1 -+ -+ -+ BKPSRAMLPEN -+ BKPSRAMLPEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB6LPENSETR -+ RCC_MP_AHB6LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0x318 -+ 0x20 -+ read-write -+ 0x011357A1 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ GPULPEN -+ GPULPEN -+ 5 -+ 1 -+ -+ -+ ETHCKLPEN -+ ETHCKLPEN -+ 7 -+ 1 -+ -+ -+ ETHTXLPEN -+ ETHTXLPEN -+ 8 -+ 1 -+ -+ -+ ETHRXLPEN -+ ETHRXLPEN -+ 9 -+ 1 -+ -+ -+ ETHMACLPEN -+ ETHMACLPEN -+ 10 -+ 1 -+ -+ -+ ETHSTPEN -+ ETHSTPEN -+ 11 -+ 1 -+ -+ -+ FMCLPEN -+ FMCLPEN -+ 12 -+ 1 -+ -+ -+ QSPILPEN -+ QSPILPEN -+ 14 -+ 1 -+ -+ -+ SDMMC1LPEN -+ SDMMC1LPEN -+ 16 -+ 1 -+ -+ -+ SDMMC2LPEN -+ SDMMC2LPEN -+ 17 -+ 1 -+ -+ -+ CRC1LPEN -+ CRC1LPEN -+ 20 -+ 1 -+ -+ -+ USBHLPEN -+ USBHLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB6LPENCLRR -+ RCC_MP_AHB6LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0x31C -+ 0x20 -+ read-write -+ 0x011357A1 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ GPULPEN -+ GPULPEN -+ 5 -+ 1 -+ -+ -+ ETHCKLPEN -+ ETHCKLPEN -+ 7 -+ 1 -+ -+ -+ ETHTXLPEN -+ ETHTXLPEN -+ 8 -+ 1 -+ -+ -+ ETHRXLPEN -+ ETHRXLPEN -+ 9 -+ 1 -+ -+ -+ ETHMACLPEN -+ ETHMACLPEN -+ 10 -+ 1 -+ -+ -+ ETHSTPEN -+ ETHSTPEN -+ 11 -+ 1 -+ -+ -+ FMCLPEN -+ FMCLPEN -+ 12 -+ 1 -+ -+ -+ QSPILPEN -+ QSPILPEN -+ 14 -+ 1 -+ -+ -+ SDMMC1LPEN -+ SDMMC1LPEN -+ 16 -+ 1 -+ -+ -+ SDMMC2LPEN -+ SDMMC2LPEN -+ 17 -+ 1 -+ -+ -+ CRC1LPEN -+ CRC1LPEN -+ 20 -+ 1 -+ -+ -+ USBHLPEN -+ USBHLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_TZAHB6LPENSETR -+ RCC_MP_TZAHB6LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_TZAHB6LPENCLRR -+ RCC_MP_TZAHB6LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. -+ 0x324 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB4LPENSETR -+ RCC_MC_APB4LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0x380 -+ 0x20 -+ read-write -+ 0x00110111 -+ -+ -+ LTDCLPEN -+ LTDCLPEN -+ 0 -+ 1 -+ -+ -+ DSILPEN -+ DSILPEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMLPEN -+ DDRPERFMLPEN -+ 8 -+ 1 -+ -+ -+ USBPHYLPEN -+ USBPHYLPEN -+ 16 -+ 1 -+ -+ -+ STGENROLPEN -+ STGENROLPEN -+ 20 -+ 1 -+ -+ -+ STGENROSTPEN -+ STGENROSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB4LPENCLRR -+ RCC_MC_APB4LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0x384 -+ 0x20 -+ read-write -+ 0x00110111 -+ -+ -+ LTDCLPEN -+ LTDCLPEN -+ 0 -+ 1 -+ -+ -+ DSILPEN -+ DSILPEN -+ 4 -+ 1 -+ -+ -+ DDRPERFMLPEN -+ DDRPERFMLPEN -+ 8 -+ 1 -+ -+ -+ USBPHYLPEN -+ USBPHYLPEN -+ 16 -+ 1 -+ -+ -+ STGENROLPEN -+ STGENROLPEN -+ 20 -+ 1 -+ -+ -+ STGENROSTPEN -+ STGENROSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB5LPENSETR -+ RCC_MC_APB5LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0x388 -+ 0x20 -+ read-write -+ 0x0011391D -+ -+ -+ SPI6LPEN -+ SPI6LPEN -+ 0 -+ 1 -+ -+ -+ I2C4LPEN -+ I2C4LPEN -+ 2 -+ 1 -+ -+ -+ I2C6LPEN -+ I2C6LPEN -+ 3 -+ 1 -+ -+ -+ USART1LPEN -+ USART1LPEN -+ 4 -+ 1 -+ -+ -+ RTCAPBLPEN -+ RTCAPBLPEN -+ 8 -+ 1 -+ -+ -+ TZC1LPEN -+ TZC1LPEN -+ 11 -+ 1 -+ -+ -+ TZC2LPEN -+ TZC2LPEN -+ 12 -+ 1 -+ -+ -+ TZPCLPEN -+ TZPCLPEN -+ 13 -+ 1 -+ -+ -+ BSECLPEN -+ BSECLPEN -+ 16 -+ 1 -+ -+ -+ STGENLPEN -+ STGENLPEN -+ 20 -+ 1 -+ -+ -+ STGENSTPEN -+ STGENSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB5LPENCLRR -+ RCC_MC_APB5LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0x38C -+ 0x20 -+ read-write -+ 0x0011391D -+ -+ -+ SPI6LPEN -+ SPI6LPEN -+ 0 -+ 1 -+ -+ -+ I2C4LPEN -+ I2C4LPEN -+ 2 -+ 1 -+ -+ -+ I2C6LPEN -+ I2C6LPEN -+ 3 -+ 1 -+ -+ -+ USART1LPEN -+ USART1LPEN -+ 4 -+ 1 -+ -+ -+ RTCAPBLPEN -+ RTCAPBLPEN -+ 8 -+ 1 -+ -+ -+ TZC1LPEN -+ TZC1LPEN -+ 11 -+ 1 -+ -+ -+ TZC2LPEN -+ TZC2LPEN -+ 12 -+ 1 -+ -+ -+ TZPCLPEN -+ TZPCLPEN -+ 13 -+ 1 -+ -+ -+ BSECLPEN -+ BSECLPEN -+ 16 -+ 1 -+ -+ -+ STGENLPEN -+ STGENLPEN -+ 20 -+ 1 -+ -+ -+ STGENSTPEN -+ STGENSTPEN -+ 21 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB5LPENSETR -+ RCC_MC_AHB5LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode. -+ 0x390 -+ 0x20 -+ read-write -+ 0x00000171 -+ -+ -+ GPIOZLPEN -+ GPIOZLPEN -+ 0 -+ 1 -+ -+ -+ CRYP1LPEN -+ CRYP1LPEN -+ 4 -+ 1 -+ -+ -+ HASH1LPEN -+ HASH1LPEN -+ 5 -+ 1 -+ -+ -+ RNG1LPEN -+ RNG1LPEN -+ 6 -+ 1 -+ -+ -+ BKPSRAMLPEN -+ BKPSRAMLPEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB5LPENCLRR -+ RCC_MC_AHB5LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode. -+ 0x394 -+ 0x20 -+ read-write -+ 0x00000171 -+ -+ -+ GPIOZLPEN -+ GPIOZLPEN -+ 0 -+ 1 -+ -+ -+ CRYP1LPEN -+ CRYP1LPEN -+ 4 -+ 1 -+ -+ -+ HASH1LPEN -+ HASH1LPEN -+ 5 -+ 1 -+ -+ -+ RNG1LPEN -+ RNG1LPEN -+ 6 -+ 1 -+ -+ -+ BKPSRAMLPEN -+ BKPSRAMLPEN -+ 8 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB6LPENSETR -+ RCC_MC_AHB6LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0x398 -+ 0x20 -+ read-write -+ 0x011357A1 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ GPULPEN -+ GPULPEN -+ 5 -+ 1 -+ -+ -+ ETHCKLPEN -+ ETHCKLPEN -+ 7 -+ 1 -+ -+ -+ ETHTXLPEN -+ ETHTXLPEN -+ 8 -+ 1 -+ -+ -+ ETHRXLPEN -+ ETHRXLPEN -+ 9 -+ 1 -+ -+ -+ ETHMACLPEN -+ ETHMACLPEN -+ 10 -+ 1 -+ -+ -+ ETHSTPEN -+ ETHSTPEN -+ 11 -+ 1 -+ -+ -+ FMCLPEN -+ FMCLPEN -+ 12 -+ 1 -+ -+ -+ QSPILPEN -+ QSPILPEN -+ 14 -+ 1 -+ -+ -+ SDMMC1LPEN -+ SDMMC1LPEN -+ 16 -+ 1 -+ -+ -+ SDMMC2LPEN -+ SDMMC2LPEN -+ 17 -+ 1 -+ -+ -+ CRC1LPEN -+ CRC1LPEN -+ 20 -+ 1 -+ -+ -+ USBHLPEN -+ USBHLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB6LPENCLRR -+ RCC_MC_AHB6LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0x39C -+ 0x20 -+ read-write -+ 0x011357A1 -+ -+ -+ MDMALPEN -+ MDMALPEN -+ 0 -+ 1 -+ -+ -+ GPULPEN -+ GPULPEN -+ 5 -+ 1 -+ -+ -+ ETHCKLPEN -+ ETHCKLPEN -+ 7 -+ 1 -+ -+ -+ ETHTXLPEN -+ ETHTXLPEN -+ 8 -+ 1 -+ -+ -+ ETHRXLPEN -+ ETHRXLPEN -+ 9 -+ 1 -+ -+ -+ ETHMACLPEN -+ ETHMACLPEN -+ 10 -+ 1 -+ -+ -+ ETHSTPEN -+ ETHSTPEN -+ 11 -+ 1 -+ -+ -+ FMCLPEN -+ FMCLPEN -+ 12 -+ 1 -+ -+ -+ QSPILPEN -+ QSPILPEN -+ 14 -+ 1 -+ -+ -+ SDMMC1LPEN -+ SDMMC1LPEN -+ 16 -+ 1 -+ -+ -+ SDMMC2LPEN -+ SDMMC2LPEN -+ 17 -+ 1 -+ -+ -+ CRC1LPEN -+ CRC1LPEN -+ 20 -+ 1 -+ -+ -+ USBHLPEN -+ USBHLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_BR_RSTSCLRR -+ RCC_BR_RSTSCLRR -+ This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode. -+ 0x400 -+ 0x20 -+ read-write -+ 0x00000015 -+ -+ -+ PORRSTF -+ PORRSTF -+ 0 -+ 1 -+ -+ -+ BORRSTF -+ BORRSTF -+ 1 -+ 1 -+ -+ -+ PADRSTF -+ PADRSTF -+ 2 -+ 1 -+ -+ -+ HCSSRSTF -+ HCSSRSTF -+ 3 -+ 1 -+ -+ -+ VCORERSTF -+ VCORERSTF -+ 4 -+ 1 -+ -+ -+ MPSYSRSTF -+ MPSYSRSTF -+ 6 -+ 1 -+ -+ -+ MCSYSRSTF -+ MCSYSRSTF -+ 7 -+ 1 -+ -+ -+ IWDG1RSTF -+ IWDG1RSTF -+ 8 -+ 1 -+ -+ -+ IWDG2RSTF -+ IWDG2RSTF -+ 9 -+ 1 -+ -+ -+ MPUP0RSTF -+ MPUP0RSTF -+ 13 -+ 1 -+ -+ -+ MPUP1RSTF -+ MPUP1RSTF -+ 14 -+ 1 -+ -+ -+ -+ -+ RCC_MP_GRSTCSETR -+ RCC_MP_GRSTCSETR -+ This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset. -+ 0x404 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSYSRST -+ MPSYSRST -+ 0 -+ 1 -+ -+ -+ MCURST -+ MCURST -+ 1 -+ 1 -+ -+ -+ MPUP0RST -+ MPUP0RST -+ 4 -+ 1 -+ -+ -+ MPUP1RST -+ MPUP1RST -+ 5 -+ 1 -+ -+ -+ -+ -+ RCC_MP_RSTSCLRR -+ RCC_MP_RSTSCLRR -+ This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. -+ 0x408 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PORRSTF -+ PORRSTF -+ 0 -+ 1 -+ -+ -+ BORRSTF -+ BORRSTF -+ 1 -+ 1 -+ -+ -+ PADRSTF -+ PADRSTF -+ 2 -+ 1 -+ -+ -+ HCSSRSTF -+ HCSSRSTF -+ 3 -+ 1 -+ -+ -+ VCORERSTF -+ VCORERSTF -+ 4 -+ 1 -+ -+ -+ MPSYSRSTF -+ MPSYSRSTF -+ 6 -+ 1 -+ -+ -+ MCSYSRSTF -+ MCSYSRSTF -+ 7 -+ 1 -+ -+ -+ IWDG1RSTF -+ IWDG1RSTF -+ 8 -+ 1 -+ -+ -+ IWDG2RSTF -+ IWDG2RSTF -+ 9 -+ 1 -+ -+ -+ STDBYRSTF -+ STDBYRSTF -+ 11 -+ 1 -+ -+ -+ CSTDBYRSTF -+ CSTDBYRSTF -+ 12 -+ 1 -+ -+ -+ MPUP0RSTF -+ MPUP0RSTF -+ 13 -+ 1 -+ -+ -+ MPUP1RSTF -+ MPUP1RSTF -+ 14 -+ 1 -+ -+ -+ SPARE -+ SPARE -+ 15 -+ 1 -+ -+ -+ -+ -+ RCC_MP_IWDGFZSETR -+ RCC_MP_IWDGFZSETR -+ This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x40C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FZ_IWDG1 -+ FZ_IWDG1 -+ 0 -+ 1 -+ -+ -+ FZ_IWDG2 -+ FZ_IWDG2 -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_MP_IWDGFZCLRR -+ RCC_MP_IWDGFZCLRR -+ This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode. -+ 0x410 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FZ_IWDG1 -+ FZ_IWDG1 -+ 0 -+ 1 -+ -+ -+ FZ_IWDG2 -+ FZ_IWDG2 -+ 1 -+ 1 -+ -+ -+ -+ -+ RCC_MP_CIER -+ RCC_MP_CIER -+ This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. -+ 0x414 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LSIRDYIE -+ LSIRDYIE -+ 0 -+ 1 -+ -+ -+ LSERDYIE -+ LSERDYIE -+ 1 -+ 1 -+ -+ -+ HSIRDYIE -+ HSIRDYIE -+ 2 -+ 1 -+ -+ -+ HSERDYIE -+ HSERDYIE -+ 3 -+ 1 -+ -+ -+ CSIRDYIE -+ CSIRDYIE -+ 4 -+ 1 -+ -+ -+ PLL1DYIE -+ PLL1DYIE -+ 8 -+ 1 -+ -+ -+ PLL2DYIE -+ PLL2DYIE -+ 9 -+ 1 -+ -+ -+ PLL3DYIE -+ PLL3DYIE -+ 10 -+ 1 -+ -+ -+ PLL4DYIE -+ PLL4DYIE -+ 11 -+ 1 -+ -+ -+ LSECSSIE -+ LSECSSIE -+ 16 -+ 1 -+ -+ -+ WKUPIE -+ WKUPIE -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_CIFR -+ RCC_MP_CIFR -+ This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. -+ 0x418 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LSIRDYF -+ LSIRDYF -+ 0 -+ 1 -+ -+ -+ LSERDYF -+ LSERDYF -+ 1 -+ 1 -+ -+ -+ HSIRDYF -+ HSIRDYF -+ 2 -+ 1 -+ -+ -+ HSERDYF -+ HSERDYF -+ 3 -+ 1 -+ -+ -+ CSIRDYF -+ CSIRDYF -+ 4 -+ 1 -+ -+ -+ PLL1DYF -+ PLL1DYF -+ 8 -+ 1 -+ -+ -+ PLL2DYF -+ PLL2DYF -+ 9 -+ 1 -+ -+ -+ PLL3DYF -+ PLL3DYF -+ 10 -+ 1 -+ -+ -+ PLL4DYF -+ PLL4DYF -+ 11 -+ 1 -+ -+ -+ LSECSSF -+ LSECSSF -+ 16 -+ 1 -+ -+ -+ WKUPF -+ WKUPF -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_PWRLPDLYCR -+ RCC_PWRLPDLYCR -+ This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode. -+ 0x41C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PWRLP_DLY -+ PWRLP_DLY -+ 0 -+ 22 -+ -+ -+ MCTMPSKP -+ MCTMPSKP -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_RSTSSETR -+ RCC_MP_RSTSSETR -+ This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. -+ 0x420 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PORRSTF -+ PORRSTF -+ 0 -+ 1 -+ -+ -+ BORRSTF -+ BORRSTF -+ 1 -+ 1 -+ -+ -+ PADRSTF -+ PADRSTF -+ 2 -+ 1 -+ -+ -+ HCSSRSTF -+ HCSSRSTF -+ 3 -+ 1 -+ -+ -+ VCORERSTF -+ VCORERSTF -+ 4 -+ 1 -+ -+ -+ MPSYSRSTF -+ MPSYSRSTF -+ 6 -+ 1 -+ -+ -+ MCSYSRSTF -+ MCSYSRSTF -+ 7 -+ 1 -+ -+ -+ IWDG1RSTF -+ IWDG1RSTF -+ 8 -+ 1 -+ -+ -+ IWDG2RSTF -+ IWDG2RSTF -+ 9 -+ 1 -+ -+ -+ STDBYRSTF -+ STDBYRSTF -+ 11 -+ 1 -+ -+ -+ CSTDBYRSTF -+ CSTDBYRSTF -+ 12 -+ 1 -+ -+ -+ MPUP0RSTF -+ MPUP0RSTF -+ 13 -+ 1 -+ -+ -+ MPUP1RSTF -+ MPUP1RSTF -+ 14 -+ 1 -+ -+ -+ SPARE -+ SPARE -+ 15 -+ 1 -+ -+ -+ -+ -+ RCC_MCO1CFGR -+ RCC_MCO1CFGR -+ This register is used to select the clock generated on MCO1 output. -+ 0x800 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MCO1SEL -+ MCO1SEL -+ 0 -+ 3 -+ -+ -+ MCO1DIV -+ MCO1DIV -+ 4 -+ 4 -+ -+ -+ MCO1ON -+ MCO1ON -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MCO2CFGR -+ RCC_MCO2CFGR -+ This register is used to select the clock generated on MCO2 output. -+ 0x804 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MCO2SEL -+ MCO2SEL -+ 0 -+ 3 -+ -+ -+ MCO2DIV -+ MCO2DIV -+ 4 -+ 4 -+ -+ -+ MCO2ON -+ MCO2ON -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_OCRDYR -+ RCC_OCRDYR -+ This is a read-only access register, It contains the status flags of oscillators. Writing has no effect. -+ 0x808 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HSIRDY -+ HSIRDY -+ 0 -+ 1 -+ -+ -+ HSIDIVRDY -+ HSIDIVRDY -+ 2 -+ 1 -+ -+ -+ CSIRDY -+ CSIRDY -+ 4 -+ 1 -+ -+ -+ HSERDY -+ HSERDY -+ 8 -+ 1 -+ -+ -+ MPUCKRDY -+ MPUCKRDY -+ 23 -+ 1 -+ -+ -+ AXICKRDY -+ AXICKRDY -+ 24 -+ 1 -+ -+ -+ CKREST -+ CKREST -+ 25 -+ 1 -+ -+ -+ -+ -+ RCC_DBGCFGR -+ RCC_DBGCFGR -+ This is register contains the enable control of the debug and trace function, and the clock divider for the trace function. -+ 0x80C -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ TRACEDIV -+ TRACEDIV -+ 0 -+ 3 -+ -+ -+ DBGCKEN -+ DBGCKEN -+ 8 -+ 1 -+ -+ -+ TRACECKEN -+ TRACECKEN -+ 9 -+ 1 -+ -+ -+ DBGRST -+ DBGRST -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_RCK3SELR -+ RCC_RCK3SELR -+ This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x820 -+ 0x20 -+ 0x80000000 -+ -+ -+ PLL3SRC -+ PLL3SRC -+ 0 -+ 2 -+ read-write -+ -+ -+ PLL3SRCRDY -+ PLL3SRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_RCK4SELR -+ RCC_RCK4SELR -+ This register is used to select the reference clock for PLL4. -+ 0x824 -+ 0x20 -+ 0x80000000 -+ -+ -+ PLL4SRC -+ PLL4SRC -+ 0 -+ 2 -+ read-write -+ -+ -+ PLL4SRCRDY -+ PLL4SRCRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_TIMG1PRER -+ RCC_TIMG1PRER -+ This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information. -+ 0x828 -+ 0x20 -+ 0x80000000 -+ -+ -+ TIMG1PRE -+ TIMG1PRE -+ 0 -+ 1 -+ read-write -+ -+ -+ TIMG1PRERDY -+ TIMG1PRERDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_TIMG2PRER -+ RCC_TIMG2PRER -+ This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information. -+ 0x82C -+ 0x20 -+ 0x80000000 -+ -+ -+ TIMG2PRE -+ TIMG2PRE -+ 0 -+ 1 -+ read-write -+ -+ -+ TIMG2PRERDY -+ TIMG2PRERDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_MCUDIVR -+ RCC_MCUDIVR -+ This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. -+ 0x830 -+ 0x20 -+ 0x80000000 -+ -+ -+ MCUDIV -+ MCUDIV -+ 0 -+ 4 -+ read-write -+ -+ -+ MCUDIVRDY -+ MCUDIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_APB1DIVR -+ RCC_APB1DIVR -+ This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information. -+ 0x834 -+ 0x20 -+ 0x80000000 -+ -+ -+ APB1DIV -+ APB1DIV -+ 0 -+ 3 -+ read-write -+ -+ -+ APB1DIVRDY -+ APB1DIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_APB2DIVR -+ RCC_APB2DIVR -+ This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information. -+ 0x838 -+ 0x20 -+ 0x80000000 -+ -+ -+ APB2DIV -+ APB2DIV -+ 0 -+ 3 -+ read-write -+ -+ -+ APB2DIVRDY -+ APB2DIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_APB3DIVR -+ RCC_APB3DIVR -+ This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information. -+ 0x83C -+ 0x20 -+ 0x80000000 -+ -+ -+ APB3DIV -+ APB3DIV -+ 0 -+ 3 -+ read-write -+ -+ -+ APB3DIVRDY -+ APB3DIVRDY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ RCC_PLL3CR -+ RCC_PLL3CR -+ This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x880 -+ 0x20 -+ 0x00000000 -+ -+ -+ PLLON -+ PLLON -+ 0 -+ 1 -+ read-write -+ -+ -+ PLL3RDY -+ PLL3RDY -+ 1 -+ 1 -+ read-only -+ -+ -+ SSCG_CTRL -+ SSCG_CTRL -+ 2 -+ 1 -+ read-write -+ -+ -+ DIVPEN -+ DIVPEN -+ 4 -+ 1 -+ read-write -+ -+ -+ DIVQEN -+ DIVQEN -+ 5 -+ 1 -+ read-write -+ -+ -+ DIVREN -+ DIVREN -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RCC_PLL3CFGR1 -+ RCC_PLL3CFGR1 -+ This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x884 -+ 0x20 -+ read-write -+ 0x00010031 -+ -+ -+ DIVN -+ DIVN -+ 0 -+ 9 -+ -+ -+ DIVM3 -+ DIVM3 -+ 16 -+ 6 -+ -+ -+ IFRGE -+ IFRGE -+ 24 -+ 2 -+ -+ -+ -+ -+ RCC_PLL3CFGR2 -+ RCC_PLL3CFGR2 -+ This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x888 -+ 0x20 -+ read-write -+ 0x00010101 -+ -+ -+ DIVP -+ DIVP -+ 0 -+ 7 -+ -+ -+ DIVQ -+ DIVQ -+ 8 -+ 7 -+ -+ -+ DIVR -+ DIVR -+ 16 -+ 7 -+ -+ -+ -+ -+ RCC_PLL3FRACR -+ RCC_PLL3FRACR -+ This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x88C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FRACV -+ FRACV -+ 3 -+ 13 -+ -+ -+ FRACLE -+ FRACLE -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_PLL3CSGR -+ RCC_PLL3CSGR -+ This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x890 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MOD_PER -+ MOD_PER -+ 0 -+ 13 -+ -+ -+ TPDFN_DIS -+ TPDFN_DIS -+ 13 -+ 1 -+ -+ -+ RPDFN_DIS -+ RPDFN_DIS -+ 14 -+ 1 -+ -+ -+ SSCG_MODE -+ SSCG_MODE -+ 15 -+ 1 -+ -+ -+ INC_STEP -+ INC_STEP -+ 16 -+ 15 -+ -+ -+ -+ -+ RCC_PLL4CR -+ RCC_PLL4CR -+ This register is used to control the PLL4. -+ 0x894 -+ 0x20 -+ 0x00000000 -+ -+ -+ PLLON -+ PLLON -+ 0 -+ 1 -+ read-write -+ -+ -+ PLL4RDY -+ PLL4RDY -+ 1 -+ 1 -+ read-only -+ -+ -+ SSCG_CTRL -+ SSCG_CTRL -+ 2 -+ 1 -+ read-write -+ -+ -+ DIVPEN -+ DIVPEN -+ 4 -+ 1 -+ read-write -+ -+ -+ DIVQEN -+ DIVQEN -+ 5 -+ 1 -+ read-write -+ -+ -+ DIVREN -+ DIVREN -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ RCC_PLL4CFGR1 -+ RCC_PLL4CFGR1 -+ This register is used to configure the PLL4. -+ 0x898 -+ 0x20 -+ read-write -+ 0x00010031 -+ -+ -+ DIVN -+ DIVN -+ 0 -+ 9 -+ -+ -+ DIVM4 -+ DIVM4 -+ 16 -+ 6 -+ -+ -+ IFRGE -+ IFRGE -+ 24 -+ 2 -+ -+ -+ -+ -+ RCC_PLL4CFGR2 -+ RCC_PLL4CFGR2 -+ This register is used to configure the PLL4. -+ 0x89C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DIVP -+ DIVP -+ 0 -+ 7 -+ -+ -+ DIVQ -+ DIVQ -+ 8 -+ 7 -+ -+ -+ DIVR -+ DIVR -+ 16 -+ 7 -+ -+ -+ -+ -+ RCC_PLL4FRACR -+ RCC_PLL4FRACR -+ This register is used to fine-tune the frequency of the PLL4 VCO. -+ 0x8A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FRACV -+ FRACV -+ 3 -+ 13 -+ -+ -+ FRACLE -+ FRACLE -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_PLL4CSGR -+ RCC_PLL4CSGR -+ This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. -+ 0x8A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MOD_PER -+ MOD_PER -+ 0 -+ 13 -+ -+ -+ TPDFN_DIS -+ TPDFN_DIS -+ 13 -+ 1 -+ -+ -+ RPDFN_DIS -+ RPDFN_DIS -+ 14 -+ 1 -+ -+ -+ SSCG_MODE -+ SSCG_MODE -+ 15 -+ 1 -+ -+ -+ INC_STEP -+ INC_STEP -+ 16 -+ 15 -+ -+ -+ -+ -+ RCC_I2C12CKSELR -+ RCC_I2C12CKSELR -+ This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2C12SRC -+ I2C12SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_I2C35CKSELR -+ RCC_I2C35CKSELR -+ This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ I2C35SRC -+ I2C35SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SAI1CKSELR -+ RCC_SAI1CKSELR -+ This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAI1SRC -+ SAI1SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SAI2CKSELR -+ RCC_SAI2CKSELR -+ This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAI2SRC -+ SAI2SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SAI3CKSELR -+ RCC_SAI3CKSELR -+ This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAI3SRC -+ SAI3SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SAI4CKSELR -+ RCC_SAI4CKSELR -+ This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SAI4SRC -+ SAI4SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SPI2S1CKSELR -+ RCC_SPI2S1CKSELR -+ This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8D8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI1SRC -+ SPI1SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SPI2S23CKSELR -+ RCC_SPI2S23CKSELR -+ This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8DC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI23SRC -+ SPI23SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SPI45CKSELR -+ RCC_SPI45CKSELR -+ This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPI45SRC -+ SPI45SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_UART6CKSELR -+ RCC_UART6CKSELR -+ This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UART6SRC -+ UART6SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_UART24CKSELR -+ RCC_UART24CKSELR -+ This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UART24SRC -+ UART24SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_UART35CKSELR -+ RCC_UART35CKSELR -+ This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UART35SRC -+ UART35SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_UART78CKSELR -+ RCC_UART78CKSELR -+ This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ UART78SRC -+ UART78SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SDMMC12CKSELR -+ RCC_SDMMC12CKSELR -+ This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8F4 -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ SDMMC12SRC -+ SDMMC12SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_SDMMC3CKSELR -+ RCC_SDMMC3CKSELR -+ This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8F8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SDMMC3SRC -+ SDMMC3SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_ETHCKSELR -+ RCC_ETHCKSELR -+ This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x8FC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ETHSRC -+ ETHSRC -+ 0 -+ 2 -+ -+ -+ ETHPTPDIV -+ ETHPTPDIV -+ 4 -+ 4 -+ -+ -+ -+ -+ RCC_QSPICKSELR -+ RCC_QSPICKSELR -+ This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x900 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ QSPISRC -+ QSPISRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_FMCCKSELR -+ RCC_FMCCKSELR -+ This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x904 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FMCSRC -+ FMCSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_FDCANCKSELR -+ RCC_FDCANCKSELR -+ This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x90C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FDCANSRC -+ FDCANSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_SPDIFCKSELR -+ RCC_SPDIFCKSELR -+ This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. -+ 0x914 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPDIFSRC -+ SPDIFSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_CECCKSELR -+ RCC_CECCKSELR -+ This register is used to control the selection of the kernel clock for the CEC-HDMI. -+ 0x918 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CECSRC -+ CECSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_USBCKSELR -+ RCC_USBCKSELR -+ This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG -+ 0x91C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ USBPHYSRC -+ USBPHYSRC -+ 0 -+ 2 -+ -+ -+ USBOSRC -+ USBOSRC -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_RNG2CKSELR -+ RCC_RNG2CKSELR -+ This register is used to control the selection of the kernel clock for the RNG2. -+ 0x920 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RNG2SRC -+ RNG2SRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_DSICKSELR -+ RCC_DSICKSELR -+ This register is used to control the selection of the kernel clock for the DSI block. -+ 0x924 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DSISRC -+ DSISRC -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_ADCCKSELR -+ RCC_ADCCKSELR -+ This register is used to control the selection of the kernel clock for the ADC block. -+ 0x928 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ADCSRC -+ ADCSRC -+ 0 -+ 2 -+ -+ -+ -+ -+ RCC_LPTIM45CKSELR -+ RCC_LPTIM45CKSELR -+ This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. -+ 0x92C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM45SRC -+ LPTIM45SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_LPTIM23CKSELR -+ RCC_LPTIM23CKSELR -+ This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. -+ 0x930 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM23SRC -+ LPTIM23SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_LPTIM1CKSELR -+ RCC_LPTIM1CKSELR -+ This register is used to control the selection of the kernel clock for the LPTIM1 block. -+ 0x934 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM1SRC -+ LPTIM1SRC -+ 0 -+ 3 -+ -+ -+ -+ -+ RCC_APB1RSTSETR -+ RCC_APB1RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. -+ 0x980 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2RST -+ TIM2RST -+ 0 -+ 1 -+ -+ -+ TIM3RST -+ TIM3RST -+ 1 -+ 1 -+ -+ -+ TIM4RST -+ TIM4RST -+ 2 -+ 1 -+ -+ -+ TIM5RST -+ TIM5RST -+ 3 -+ 1 -+ -+ -+ TIM6RST -+ TIM6RST -+ 4 -+ 1 -+ -+ -+ TIM7RST -+ TIM7RST -+ 5 -+ 1 -+ -+ -+ TIM12RST -+ TIM12RST -+ 6 -+ 1 -+ -+ -+ TIM13RST -+ TIM13RST -+ 7 -+ 1 -+ -+ -+ TIM14RST -+ TIM14RST -+ 8 -+ 1 -+ -+ -+ LPTIM1RST -+ LPTIM1RST -+ 9 -+ 1 -+ -+ -+ SPI2RST -+ SPI2RST -+ 11 -+ 1 -+ -+ -+ SPI3RST -+ SPI3RST -+ 12 -+ 1 -+ -+ -+ USART2RST -+ USART2RST -+ 14 -+ 1 -+ -+ -+ USART3RST -+ USART3RST -+ 15 -+ 1 -+ -+ -+ UART4RST -+ UART4RST -+ 16 -+ 1 -+ -+ -+ UART5RST -+ UART5RST -+ 17 -+ 1 -+ -+ -+ UART7RST -+ UART7RST -+ 18 -+ 1 -+ -+ -+ UART8RST -+ UART8RST -+ 19 -+ 1 -+ -+ -+ I2C1RST -+ I2C1RST -+ 21 -+ 1 -+ -+ -+ I2C2RST -+ I2C2RST -+ 22 -+ 1 -+ -+ -+ I2C3RST -+ I2C3RST -+ 23 -+ 1 -+ -+ -+ I2C5RST -+ I2C5RST -+ 24 -+ 1 -+ -+ -+ SPDIFRST -+ SPDIFRST -+ 26 -+ 1 -+ -+ -+ CECRST -+ CECRST -+ 27 -+ 1 -+ -+ -+ DAC12RST -+ DAC12RST -+ 29 -+ 1 -+ -+ -+ MDIOSRST -+ MDIOSRST -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_APB1RSTCLRR -+ RCC_APB1RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x984 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2RST -+ TIM2RST -+ 0 -+ 1 -+ -+ -+ TIM3RST -+ TIM3RST -+ 1 -+ 1 -+ -+ -+ TIM4RST -+ TIM4RST -+ 2 -+ 1 -+ -+ -+ TIM5RST -+ TIM5RST -+ 3 -+ 1 -+ -+ -+ TIM6RST -+ TIM6RST -+ 4 -+ 1 -+ -+ -+ TIM7RST -+ TIM7RST -+ 5 -+ 1 -+ -+ -+ TIM12RST -+ TIM12RST -+ 6 -+ 1 -+ -+ -+ TIM13RST -+ TIM13RST -+ 7 -+ 1 -+ -+ -+ TIM14RST -+ TIM14RST -+ 8 -+ 1 -+ -+ -+ LPTIM1RST -+ LPTIM1RST -+ 9 -+ 1 -+ -+ -+ SPI2RST -+ SPI2RST -+ 11 -+ 1 -+ -+ -+ SPI3RST -+ SPI3RST -+ 12 -+ 1 -+ -+ -+ USART2RST -+ USART2RST -+ 14 -+ 1 -+ -+ -+ USART3RST -+ USART3RST -+ 15 -+ 1 -+ -+ -+ UART4RST -+ UART4RST -+ 16 -+ 1 -+ -+ -+ UART5RST -+ UART5RST -+ 17 -+ 1 -+ -+ -+ UART7RST -+ UART7RST -+ 18 -+ 1 -+ -+ -+ UART8RST -+ UART8RST -+ 19 -+ 1 -+ -+ -+ I2C1RST -+ I2C1RST -+ 21 -+ 1 -+ -+ -+ I2C2RST -+ I2C2RST -+ 22 -+ 1 -+ -+ -+ I2C3RST -+ I2C3RST -+ 23 -+ 1 -+ -+ -+ I2C5RST -+ I2C5RST -+ 24 -+ 1 -+ -+ -+ SPDIFRST -+ SPDIFRST -+ 26 -+ 1 -+ -+ -+ CECRST -+ CECRST -+ 27 -+ 1 -+ -+ -+ DAC12RST -+ DAC12RST -+ 29 -+ 1 -+ -+ -+ MDIOSRST -+ MDIOSRST -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_APB2RSTSETR -+ RCC_APB2RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. -+ 0x988 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1RST -+ TIM1RST -+ 0 -+ 1 -+ -+ -+ TIM8RST -+ TIM8RST -+ 1 -+ 1 -+ -+ -+ TIM15RST -+ TIM15RST -+ 2 -+ 1 -+ -+ -+ TIM16RST -+ TIM16RST -+ 3 -+ 1 -+ -+ -+ TIM17RST -+ TIM17RST -+ 4 -+ 1 -+ -+ -+ SPI1RST -+ SPI1RST -+ 8 -+ 1 -+ -+ -+ SPI4RST -+ SPI4RST -+ 9 -+ 1 -+ -+ -+ SPI5RST -+ SPI5RST -+ 10 -+ 1 -+ -+ -+ USART6RST -+ USART6RST -+ 13 -+ 1 -+ -+ -+ SAI1RST -+ SAI1RST -+ 16 -+ 1 -+ -+ -+ SAI2RST -+ SAI2RST -+ 17 -+ 1 -+ -+ -+ SAI3RST -+ SAI3RST -+ 18 -+ 1 -+ -+ -+ DFSDMRST -+ DFSDMRST -+ 20 -+ 1 -+ -+ -+ FDCANRST -+ FDCANRST -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_APB2RSTCLRR -+ RCC_APB2RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x98C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1RST -+ TIM1RST -+ 0 -+ 1 -+ -+ -+ TIM8RST -+ TIM8RST -+ 1 -+ 1 -+ -+ -+ TIM15RST -+ TIM15RST -+ 2 -+ 1 -+ -+ -+ TIM16RST -+ TIM16RST -+ 3 -+ 1 -+ -+ -+ TIM17RST -+ TIM17RST -+ 4 -+ 1 -+ -+ -+ SPI1RST -+ SPI1RST -+ 8 -+ 1 -+ -+ -+ SPI4RST -+ SPI4RST -+ 9 -+ 1 -+ -+ -+ SPI5RST -+ SPI5RST -+ 10 -+ 1 -+ -+ -+ USART6RST -+ USART6RST -+ 13 -+ 1 -+ -+ -+ SAI1RST -+ SAI1RST -+ 16 -+ 1 -+ -+ -+ SAI2RST -+ SAI2RST -+ 17 -+ 1 -+ -+ -+ SAI3RST -+ SAI3RST -+ 18 -+ 1 -+ -+ -+ DFSDMRST -+ DFSDMRST -+ 20 -+ 1 -+ -+ -+ FDCANRST -+ FDCANRST -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_APB3RSTSETR -+ RCC_APB3RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. -+ 0x990 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2RST -+ LPTIM2RST -+ 0 -+ 1 -+ -+ -+ LPTIM3RST -+ LPTIM3RST -+ 1 -+ 1 -+ -+ -+ LPTIM4RST -+ LPTIM4RST -+ 2 -+ 1 -+ -+ -+ LPTIM5RST -+ LPTIM5RST -+ 3 -+ 1 -+ -+ -+ SAI4RST -+ SAI4RST -+ 8 -+ 1 -+ -+ -+ SYSCFGRST -+ SYSCFGRST -+ 11 -+ 1 -+ -+ -+ VREFRST -+ VREFRST -+ 13 -+ 1 -+ -+ -+ DTSRST -+ DTSRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_APB3RSTCLRR -+ RCC_APB3RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x994 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2RST -+ LPTIM2RST -+ 0 -+ 1 -+ -+ -+ LPTIM3RST -+ LPTIM3RST -+ 1 -+ 1 -+ -+ -+ LPTIM4RST -+ LPTIM4RST -+ 2 -+ 1 -+ -+ -+ LPTIM5RST -+ LPTIM5RST -+ 3 -+ 1 -+ -+ -+ SAI4RST -+ SAI4RST -+ 8 -+ 1 -+ -+ -+ SYSCFGRST -+ SYSCFGRST -+ 11 -+ 1 -+ -+ -+ VREFRST -+ VREFRST -+ 13 -+ 1 -+ -+ -+ DTSRST -+ DTSRST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_AHB2RSTSETR -+ RCC_AHB2RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. -+ 0x998 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1RST -+ DMA1RST -+ 0 -+ 1 -+ -+ -+ DMA2RST -+ DMA2RST -+ 1 -+ 1 -+ -+ -+ DMAMUXRST -+ DMAMUXRST -+ 2 -+ 1 -+ -+ -+ ADC12RST -+ ADC12RST -+ 5 -+ 1 -+ -+ -+ USBORST -+ USBORST -+ 8 -+ 1 -+ -+ -+ SDMMC3RST -+ SDMMC3RST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_AHB2RSTCLRR -+ RCC_AHB2RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x99C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1RST -+ DMA1RST -+ 0 -+ 1 -+ -+ -+ DMA2RST -+ DMA2RST -+ 1 -+ 1 -+ -+ -+ DMAMUXRST -+ DMAMUXRST -+ 2 -+ 1 -+ -+ -+ ADC12RST -+ ADC12RST -+ 5 -+ 1 -+ -+ -+ USBORST -+ USBORST -+ 8 -+ 1 -+ -+ -+ SDMMC3RST -+ SDMMC3RST -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_AHB3RSTSETR -+ RCC_AHB3RSTSETR -+ This register is used to activate the reset of the corresponding peripheral. -+ 0x9A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIRST -+ DCMIRST -+ 0 -+ 1 -+ -+ -+ CRYP2RST -+ CRYP2RST -+ 4 -+ 1 -+ -+ -+ HASH2RST -+ HASH2RST -+ 5 -+ 1 -+ -+ -+ RNG2RST -+ RNG2RST -+ 6 -+ 1 -+ -+ -+ CRC2RST -+ CRC2RST -+ 7 -+ 1 -+ -+ -+ HSEMRST -+ HSEMRST -+ 11 -+ 1 -+ -+ -+ IPCCRST -+ IPCCRST -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_AHB3RSTCLRR -+ RCC_AHB3RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x9A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIRST -+ DCMIRST -+ 0 -+ 1 -+ -+ -+ CRYP2RST -+ CRYP2RST -+ 4 -+ 1 -+ -+ -+ HASH2RST -+ HASH2RST -+ 5 -+ 1 -+ -+ -+ RNG2RST -+ RNG2RST -+ 6 -+ 1 -+ -+ -+ CRC2RST -+ CRC2RST -+ 7 -+ 1 -+ -+ -+ HSEMRST -+ HSEMRST -+ 11 -+ 1 -+ -+ -+ IPCCRST -+ IPCCRST -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_AHB4RSTSETR -+ RCC_AHB4RSTSETR -+ This register is used to activate the reset of the corresponding peripheral -+ 0x9A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOARST -+ GPIOARST -+ 0 -+ 1 -+ -+ -+ GPIOBRST -+ GPIOBRST -+ 1 -+ 1 -+ -+ -+ GPIOCRST -+ GPIOCRST -+ 2 -+ 1 -+ -+ -+ GPIODRST -+ GPIODRST -+ 3 -+ 1 -+ -+ -+ GPIOERST -+ GPIOERST -+ 4 -+ 1 -+ -+ -+ GPIOFRST -+ GPIOFRST -+ 5 -+ 1 -+ -+ -+ GPIOGRST -+ GPIOGRST -+ 6 -+ 1 -+ -+ -+ GPIOHRST -+ GPIOHRST -+ 7 -+ 1 -+ -+ -+ GPIOIRST -+ GPIOIRST -+ 8 -+ 1 -+ -+ -+ GPIOJRST -+ GPIOJRST -+ 9 -+ 1 -+ -+ -+ GPIOKRST -+ GPIOKRST -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_AHB4RSTCLRR -+ RCC_AHB4RSTCLRR -+ This register is used to release the reset of the corresponding peripheral. -+ 0x9AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOARST -+ GPIOARST -+ 0 -+ 1 -+ -+ -+ GPIOBRST -+ GPIOBRST -+ 1 -+ 1 -+ -+ -+ GPIOCRST -+ GPIOCRST -+ 2 -+ 1 -+ -+ -+ GPIODRST -+ GPIODRST -+ 3 -+ 1 -+ -+ -+ GPIOERST -+ GPIOERST -+ 4 -+ 1 -+ -+ -+ GPIOFRST -+ GPIOFRST -+ 5 -+ 1 -+ -+ -+ GPIOGRST -+ GPIOGRST -+ 6 -+ 1 -+ -+ -+ GPIOHRST -+ GPIOHRST -+ 7 -+ 1 -+ -+ -+ GPIOIRST -+ GPIOIRST -+ 8 -+ 1 -+ -+ -+ GPIOJRST -+ GPIOJRST -+ 9 -+ 1 -+ -+ -+ GPIOKRST -+ GPIOKRST -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB1ENSETR -+ RCC_MP_APB1ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA00 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2EN -+ TIM2EN -+ 0 -+ 1 -+ -+ -+ TIM3EN -+ TIM3EN -+ 1 -+ 1 -+ -+ -+ TIM4EN -+ TIM4EN -+ 2 -+ 1 -+ -+ -+ TIM5EN -+ TIM5EN -+ 3 -+ 1 -+ -+ -+ TIM6EN -+ TIM6EN -+ 4 -+ 1 -+ -+ -+ TIM7EN -+ TIM7EN -+ 5 -+ 1 -+ -+ -+ TIM12EN -+ TIM12EN -+ 6 -+ 1 -+ -+ -+ TIM13EN -+ TIM13EN -+ 7 -+ 1 -+ -+ -+ TIM14EN -+ TIM14EN -+ 8 -+ 1 -+ -+ -+ LPTIM1EN -+ LPTIM1EN -+ 9 -+ 1 -+ -+ -+ SPI2EN -+ SPI2EN -+ 11 -+ 1 -+ -+ -+ SPI3EN -+ SPI3EN -+ 12 -+ 1 -+ -+ -+ USART2EN -+ USART2EN -+ 14 -+ 1 -+ -+ -+ USART3EN -+ USART3EN -+ 15 -+ 1 -+ -+ -+ UART4EN -+ UART4EN -+ 16 -+ 1 -+ -+ -+ UART5EN -+ UART5EN -+ 17 -+ 1 -+ -+ -+ UART7EN -+ UART7EN -+ 18 -+ 1 -+ -+ -+ UART8EN -+ UART8EN -+ 19 -+ 1 -+ -+ -+ I2C1EN -+ I2C1EN -+ 21 -+ 1 -+ -+ -+ I2C2EN -+ I2C2EN -+ 22 -+ 1 -+ -+ -+ I2C3EN -+ I2C3EN -+ 23 -+ 1 -+ -+ -+ I2C5EN -+ I2C5EN -+ 24 -+ 1 -+ -+ -+ SPDIFEN -+ SPDIFEN -+ 26 -+ 1 -+ -+ -+ CECEN -+ CECEN -+ 27 -+ 1 -+ -+ -+ DAC12EN -+ DAC12EN -+ 29 -+ 1 -+ -+ -+ MDIOSEN -+ MDIOSEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB1ENCLRR -+ RCC_MP_APB1ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xA04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2EN -+ TIM2EN -+ 0 -+ 1 -+ -+ -+ TIM3EN -+ TIM3EN -+ 1 -+ 1 -+ -+ -+ TIM4EN -+ TIM4EN -+ 2 -+ 1 -+ -+ -+ TIM5EN -+ TIM5EN -+ 3 -+ 1 -+ -+ -+ TIM6EN -+ TIM6EN -+ 4 -+ 1 -+ -+ -+ TIM7EN -+ TIM7EN -+ 5 -+ 1 -+ -+ -+ TIM12EN -+ TIM12EN -+ 6 -+ 1 -+ -+ -+ TIM13EN -+ TIM13EN -+ 7 -+ 1 -+ -+ -+ TIM14EN -+ TIM14EN -+ 8 -+ 1 -+ -+ -+ LPTIM1EN -+ LPTIM1EN -+ 9 -+ 1 -+ -+ -+ SPI2EN -+ SPI2EN -+ 11 -+ 1 -+ -+ -+ SPI3EN -+ SPI3EN -+ 12 -+ 1 -+ -+ -+ USART2EN -+ USART2EN -+ 14 -+ 1 -+ -+ -+ USART3EN -+ USART3EN -+ 15 -+ 1 -+ -+ -+ UART4EN -+ UART4EN -+ 16 -+ 1 -+ -+ -+ UART5EN -+ UART5EN -+ 17 -+ 1 -+ -+ -+ UART7EN -+ UART7EN -+ 18 -+ 1 -+ -+ -+ UART8EN -+ UART8EN -+ 19 -+ 1 -+ -+ -+ I2C1EN -+ I2C1EN -+ 21 -+ 1 -+ -+ -+ I2C2EN -+ I2C2EN -+ 22 -+ 1 -+ -+ -+ I2C3EN -+ I2C3EN -+ 23 -+ 1 -+ -+ -+ I2C5EN -+ I2C5EN -+ 24 -+ 1 -+ -+ -+ SPDIFEN -+ SPDIFEN -+ 26 -+ 1 -+ -+ -+ CECEN -+ CECEN -+ 27 -+ 1 -+ -+ -+ DAC12EN -+ DAC12EN -+ 29 -+ 1 -+ -+ -+ MDIOSEN -+ MDIOSEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB2ENSETR -+ RCC_MP_APB2ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1EN -+ TIM1EN -+ 0 -+ 1 -+ -+ -+ TIM8EN -+ TIM8EN -+ 1 -+ 1 -+ -+ -+ TIM15EN -+ TIM15EN -+ 2 -+ 1 -+ -+ -+ TIM16EN -+ TIM16EN -+ 3 -+ 1 -+ -+ -+ TIM17EN -+ TIM17EN -+ 4 -+ 1 -+ -+ -+ SPI1EN -+ SPI1EN -+ 8 -+ 1 -+ -+ -+ SPI4EN -+ SPI4EN -+ 9 -+ 1 -+ -+ -+ SPI5EN -+ SPI5EN -+ 10 -+ 1 -+ -+ -+ USART6EN -+ USART6EN -+ 13 -+ 1 -+ -+ -+ SAI1EN -+ SAI1EN -+ 16 -+ 1 -+ -+ -+ SAI2EN -+ SAI2EN -+ 17 -+ 1 -+ -+ -+ SAI3EN -+ SAI3EN -+ 18 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 20 -+ 1 -+ -+ -+ ADFSDMEN -+ ADFSDMEN -+ 21 -+ 1 -+ -+ -+ FDCANEN -+ FDCANEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB2ENCLRR -+ RCC_MP_APB2ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. -+ 0xA0C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1EN -+ TIM1EN -+ 0 -+ 1 -+ -+ -+ TIM8EN -+ TIM8EN -+ 1 -+ 1 -+ -+ -+ TIM15EN -+ TIM15EN -+ 2 -+ 1 -+ -+ -+ TIM16EN -+ TIM16EN -+ 3 -+ 1 -+ -+ -+ TIM17EN -+ TIM17EN -+ 4 -+ 1 -+ -+ -+ SPI1EN -+ SPI1EN -+ 8 -+ 1 -+ -+ -+ SPI4EN -+ SPI4EN -+ 9 -+ 1 -+ -+ -+ SPI5EN -+ SPI5EN -+ 10 -+ 1 -+ -+ -+ USART6EN -+ USART6EN -+ 13 -+ 1 -+ -+ -+ SAI1EN -+ SAI1EN -+ 16 -+ 1 -+ -+ -+ SAI2EN -+ SAI2EN -+ 17 -+ 1 -+ -+ -+ SAI3EN -+ SAI3EN -+ 18 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 20 -+ 1 -+ -+ -+ ADFSDMEN -+ ADFSDMEN -+ 21 -+ 1 -+ -+ -+ FDCANEN -+ FDCANEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB3ENSETR -+ RCC_MP_APB3ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2EN -+ LPTIM2EN -+ 0 -+ 1 -+ -+ -+ LPTIM3EN -+ LPTIM3EN -+ 1 -+ 1 -+ -+ -+ LPTIM4EN -+ LPTIM4EN -+ 2 -+ 1 -+ -+ -+ LPTIM5EN -+ LPTIM5EN -+ 3 -+ 1 -+ -+ -+ SAI4EN -+ SAI4EN -+ 8 -+ 1 -+ -+ -+ SYSCFGEN -+ SYSCFGEN -+ 11 -+ 1 -+ -+ -+ VREFEN -+ VREFEN -+ 13 -+ 1 -+ -+ -+ DTSEN -+ DTSEN -+ 16 -+ 1 -+ -+ -+ HDPEN -+ HDPEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB3ENCLRR -+ RCC_MP_APB3ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. -+ 0xA14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2EN -+ LPTIM2EN -+ 0 -+ 1 -+ -+ -+ LPTIM3EN -+ LPTIM3EN -+ 1 -+ 1 -+ -+ -+ LPTIM4EN -+ LPTIM4EN -+ 2 -+ 1 -+ -+ -+ LPTIM5EN -+ LPTIM5EN -+ 3 -+ 1 -+ -+ -+ SAI4EN -+ SAI4EN -+ 8 -+ 1 -+ -+ -+ SYSCFGEN -+ SYSCFGEN -+ 11 -+ 1 -+ -+ -+ VREFEN -+ VREFEN -+ 13 -+ 1 -+ -+ -+ DTSEN -+ DTSEN -+ 16 -+ 1 -+ -+ -+ HDPEN -+ HDPEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB2ENSETR -+ RCC_MP_AHB2ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral -+ 0xA18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1EN -+ DMA1EN -+ 0 -+ 1 -+ -+ -+ DMA2EN -+ DMA2EN -+ 1 -+ 1 -+ -+ -+ DMAMUXEN -+ DMAMUXEN -+ 2 -+ 1 -+ -+ -+ ADC12EN -+ ADC12EN -+ 5 -+ 1 -+ -+ -+ USBOEN -+ USBOEN -+ 8 -+ 1 -+ -+ -+ SDMMC3EN -+ SDMMC3EN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB2ENCLRR -+ RCC_MP_AHB2ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. -+ 0xA1C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1EN -+ DMA1EN -+ 0 -+ 1 -+ -+ -+ DMA2EN -+ DMA2EN -+ 1 -+ 1 -+ -+ -+ DMAMUXEN -+ DMAMUXEN -+ 2 -+ 1 -+ -+ -+ ADC12EN -+ ADC12EN -+ 5 -+ 1 -+ -+ -+ USBOEN -+ USBOEN -+ 8 -+ 1 -+ -+ -+ SDMMC3EN -+ SDMMC3EN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB3ENSETR -+ RCC_MP_AHB3ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral -+ 0xA20 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIEN -+ DCMIEN -+ 0 -+ 1 -+ -+ -+ CRYP2EN -+ CRYP2EN -+ 4 -+ 1 -+ -+ -+ HASH2EN -+ HASH2EN -+ 5 -+ 1 -+ -+ -+ RNG2EN -+ RNG2EN -+ 6 -+ 1 -+ -+ -+ CRC2EN -+ CRC2EN -+ 7 -+ 1 -+ -+ -+ HSEMEN -+ HSEMEN -+ 11 -+ 1 -+ -+ -+ IPCCEN -+ IPCCEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB3ENCLRR -+ RCC_MP_AHB3ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. -+ 0xA24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIEN -+ DCMIEN -+ 0 -+ 1 -+ -+ -+ CRYP2EN -+ CRYP2EN -+ 4 -+ 1 -+ -+ -+ HASH2EN -+ HASH2EN -+ 5 -+ 1 -+ -+ -+ RNG2EN -+ RNG2EN -+ 6 -+ 1 -+ -+ -+ CRC2EN -+ CRC2EN -+ 7 -+ 1 -+ -+ -+ HSEMEN -+ HSEMEN -+ 11 -+ 1 -+ -+ -+ IPCCEN -+ IPCCEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB4ENSETR -+ RCC_MP_AHB4ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. -+ 0xA28 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOAEN -+ GPIOAEN -+ 0 -+ 1 -+ -+ -+ GPIOBEN -+ GPIOBEN -+ 1 -+ 1 -+ -+ -+ GPIOCEN -+ GPIOCEN -+ 2 -+ 1 -+ -+ -+ GPIODEN -+ GPIODEN -+ 3 -+ 1 -+ -+ -+ GPIOEEN -+ GPIOEEN -+ 4 -+ 1 -+ -+ -+ GPIOFEN -+ GPIOFEN -+ 5 -+ 1 -+ -+ -+ GPIOGEN -+ GPIOGEN -+ 6 -+ 1 -+ -+ -+ GPIOHEN -+ GPIOHEN -+ 7 -+ 1 -+ -+ -+ GPIOIEN -+ GPIOIEN -+ 8 -+ 1 -+ -+ -+ GPIOJEN -+ GPIOJEN -+ 9 -+ 1 -+ -+ -+ GPIOKEN -+ GPIOKEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB4ENCLRR -+ RCC_MP_AHB4ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xA2C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOAEN -+ GPIOAEN -+ 0 -+ 1 -+ -+ -+ GPIOBEN -+ GPIOBEN -+ 1 -+ 1 -+ -+ -+ GPIOCEN -+ GPIOCEN -+ 2 -+ 1 -+ -+ -+ GPIODEN -+ GPIODEN -+ 3 -+ 1 -+ -+ -+ GPIOEEN -+ GPIOEEN -+ 4 -+ 1 -+ -+ -+ GPIOFEN -+ GPIOFEN -+ 5 -+ 1 -+ -+ -+ GPIOGEN -+ GPIOGEN -+ 6 -+ 1 -+ -+ -+ GPIOHEN -+ GPIOHEN -+ 7 -+ 1 -+ -+ -+ GPIOIEN -+ GPIOIEN -+ 8 -+ 1 -+ -+ -+ GPIOJEN -+ GPIOJEN -+ 9 -+ 1 -+ -+ -+ GPIOKEN -+ GPIOKEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MP_MLAHBENSETR -+ RCC_MP_MLAHBENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA38 -+ 0x20 -+ read-write -+ 0x00000010 -+ -+ -+ RETRAMEN -+ RETRAMEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MP_MLAHBENCLRR -+ RCC_MP_MLAHBENCLRR -+ This register is used to clear the peripheral clock enable bit. -+ 0xA3C -+ 0x20 -+ read-write -+ 0x00000010 -+ -+ -+ RETRAMEN -+ RETRAMEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB1ENSETR -+ RCC_MC_APB1ENSETR -+ This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . -+ 0xA80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2EN -+ TIM2EN -+ 0 -+ 1 -+ -+ -+ TIM3EN -+ TIM3EN -+ 1 -+ 1 -+ -+ -+ TIM4EN -+ TIM4EN -+ 2 -+ 1 -+ -+ -+ TIM5EN -+ TIM5EN -+ 3 -+ 1 -+ -+ -+ TIM6EN -+ TIM6EN -+ 4 -+ 1 -+ -+ -+ TIM7EN -+ TIM7EN -+ 5 -+ 1 -+ -+ -+ TIM12EN -+ TIM12EN -+ 6 -+ 1 -+ -+ -+ TIM13EN -+ TIM13EN -+ 7 -+ 1 -+ -+ -+ TIM14EN -+ TIM14EN -+ 8 -+ 1 -+ -+ -+ LPTIM1EN -+ LPTIM1EN -+ 9 -+ 1 -+ -+ -+ SPI2EN -+ SPI2EN -+ 11 -+ 1 -+ -+ -+ SPI3EN -+ SPI3EN -+ 12 -+ 1 -+ -+ -+ USART2EN -+ USART2EN -+ 14 -+ 1 -+ -+ -+ USART3EN -+ USART3EN -+ 15 -+ 1 -+ -+ -+ UART4EN -+ UART4EN -+ 16 -+ 1 -+ -+ -+ UART5EN -+ UART5EN -+ 17 -+ 1 -+ -+ -+ UART7EN -+ UART7EN -+ 18 -+ 1 -+ -+ -+ UART8EN -+ UART8EN -+ 19 -+ 1 -+ -+ -+ I2C1EN -+ I2C1EN -+ 21 -+ 1 -+ -+ -+ I2C2EN -+ I2C2EN -+ 22 -+ 1 -+ -+ -+ I2C3EN -+ I2C3EN -+ 23 -+ 1 -+ -+ -+ I2C5EN -+ I2C5EN -+ 24 -+ 1 -+ -+ -+ SPDIFEN -+ SPDIFEN -+ 26 -+ 1 -+ -+ -+ CECEN -+ CECEN -+ 27 -+ 1 -+ -+ -+ WWDG1EN -+ WWDG1EN -+ 28 -+ 1 -+ -+ -+ DAC12EN -+ DAC12EN -+ 29 -+ 1 -+ -+ -+ MDIOSEN -+ MDIOSEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB1ENCLRR -+ RCC_MC_APB1ENCLRR -+ This register is used to clear the peripheral clock enable bit of the corresponding peripheral. -+ 0xA84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM2EN -+ TIM2EN -+ 0 -+ 1 -+ -+ -+ TIM3EN -+ TIM3EN -+ 1 -+ 1 -+ -+ -+ TIM4EN -+ TIM4EN -+ 2 -+ 1 -+ -+ -+ TIM5EN -+ TIM5EN -+ 3 -+ 1 -+ -+ -+ TIM6EN -+ TIM6EN -+ 4 -+ 1 -+ -+ -+ TIM7EN -+ TIM7EN -+ 5 -+ 1 -+ -+ -+ TIM12EN -+ TIM12EN -+ 6 -+ 1 -+ -+ -+ TIM13EN -+ TIM13EN -+ 7 -+ 1 -+ -+ -+ TIM14EN -+ TIM14EN -+ 8 -+ 1 -+ -+ -+ LPTIM1EN -+ LPTIM1EN -+ 9 -+ 1 -+ -+ -+ SPI2EN -+ SPI2EN -+ 11 -+ 1 -+ -+ -+ SPI3EN -+ SPI3EN -+ 12 -+ 1 -+ -+ -+ USART2EN -+ USART2EN -+ 14 -+ 1 -+ -+ -+ USART3EN -+ USART3EN -+ 15 -+ 1 -+ -+ -+ UART4EN -+ UART4EN -+ 16 -+ 1 -+ -+ -+ UART5EN -+ UART5EN -+ 17 -+ 1 -+ -+ -+ UART7EN -+ UART7EN -+ 18 -+ 1 -+ -+ -+ UART8EN -+ UART8EN -+ 19 -+ 1 -+ -+ -+ I2C1EN -+ I2C1EN -+ 21 -+ 1 -+ -+ -+ I2C2EN -+ I2C2EN -+ 22 -+ 1 -+ -+ -+ I2C3EN -+ I2C3EN -+ 23 -+ 1 -+ -+ -+ I2C5EN -+ I2C5EN -+ 24 -+ 1 -+ -+ -+ SPDIFEN -+ SPDIFEN -+ 26 -+ 1 -+ -+ -+ CECEN -+ CECEN -+ 27 -+ 1 -+ -+ -+ DAC12EN -+ DAC12EN -+ 29 -+ 1 -+ -+ -+ MDIOSEN -+ MDIOSEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB2ENSETR -+ RCC_MC_APB2ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1EN -+ TIM1EN -+ 0 -+ 1 -+ -+ -+ TIM8EN -+ TIM8EN -+ 1 -+ 1 -+ -+ -+ TIM15EN -+ TIM15EN -+ 2 -+ 1 -+ -+ -+ TIM16EN -+ TIM16EN -+ 3 -+ 1 -+ -+ -+ TIM17EN -+ TIM17EN -+ 4 -+ 1 -+ -+ -+ SPI1EN -+ SPI1EN -+ 8 -+ 1 -+ -+ -+ SPI4EN -+ SPI4EN -+ 9 -+ 1 -+ -+ -+ SPI5EN -+ SPI5EN -+ 10 -+ 1 -+ -+ -+ USART6EN -+ USART6EN -+ 13 -+ 1 -+ -+ -+ SAI1EN -+ SAI1EN -+ 16 -+ 1 -+ -+ -+ SAI2EN -+ SAI2EN -+ 17 -+ 1 -+ -+ -+ SAI3EN -+ SAI3EN -+ 18 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 20 -+ 1 -+ -+ -+ ADFSDMEN -+ ADFSDMEN -+ 21 -+ 1 -+ -+ -+ FDCANEN -+ FDCANEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB2ENCLRR -+ RCC_MC_APB2ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xA8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TIM1EN -+ TIM1EN -+ 0 -+ 1 -+ -+ -+ TIM8EN -+ TIM8EN -+ 1 -+ 1 -+ -+ -+ TIM15EN -+ TIM15EN -+ 2 -+ 1 -+ -+ -+ TIM16EN -+ TIM16EN -+ 3 -+ 1 -+ -+ -+ TIM17EN -+ TIM17EN -+ 4 -+ 1 -+ -+ -+ SPI1EN -+ SPI1EN -+ 8 -+ 1 -+ -+ -+ SPI4EN -+ SPI4EN -+ 9 -+ 1 -+ -+ -+ SPI5EN -+ SPI5EN -+ 10 -+ 1 -+ -+ -+ USART6EN -+ USART6EN -+ 13 -+ 1 -+ -+ -+ SAI1EN -+ SAI1EN -+ 16 -+ 1 -+ -+ -+ SAI2EN -+ SAI2EN -+ 17 -+ 1 -+ -+ -+ SAI3EN -+ SAI3EN -+ 18 -+ 1 -+ -+ -+ DFSDMEN -+ DFSDMEN -+ 20 -+ 1 -+ -+ -+ ADFSDMEN -+ ADFSDMEN -+ 21 -+ 1 -+ -+ -+ FDCANEN -+ FDCANEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB3ENSETR -+ RCC_MC_APB3ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2EN -+ LPTIM2EN -+ 0 -+ 1 -+ -+ -+ LPTIM3EN -+ LPTIM3EN -+ 1 -+ 1 -+ -+ -+ LPTIM4EN -+ LPTIM4EN -+ 2 -+ 1 -+ -+ -+ LPTIM5EN -+ LPTIM5EN -+ 3 -+ 1 -+ -+ -+ SAI4EN -+ SAI4EN -+ 8 -+ 1 -+ -+ -+ SYSCFGEN -+ SYSCFGEN -+ 11 -+ 1 -+ -+ -+ VREFEN -+ VREFEN -+ 13 -+ 1 -+ -+ -+ DTSEN -+ DTSEN -+ 16 -+ 1 -+ -+ -+ HDPEN -+ HDPEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB3ENCLRR -+ RCC_MC_APB3ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xA94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LPTIM2EN -+ LPTIM2EN -+ 0 -+ 1 -+ -+ -+ LPTIM3EN -+ LPTIM3EN -+ 1 -+ 1 -+ -+ -+ LPTIM4EN -+ LPTIM4EN -+ 2 -+ 1 -+ -+ -+ LPTIM5EN -+ LPTIM5EN -+ 3 -+ 1 -+ -+ -+ SAI4EN -+ SAI4EN -+ 8 -+ 1 -+ -+ -+ SYSCFGEN -+ SYSCFGEN -+ 11 -+ 1 -+ -+ -+ VREFEN -+ VREFEN -+ 13 -+ 1 -+ -+ -+ DTSEN -+ DTSEN -+ 16 -+ 1 -+ -+ -+ HDPEN -+ HDPEN -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB2ENSETR -+ RCC_MC_AHB2ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xA98 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1EN -+ DMA1EN -+ 0 -+ 1 -+ -+ -+ DMA2EN -+ DMA2EN -+ 1 -+ 1 -+ -+ -+ DMAMUXEN -+ DMAMUXEN -+ 2 -+ 1 -+ -+ -+ ADC12EN -+ ADC12EN -+ 5 -+ 1 -+ -+ -+ USBOEN -+ USBOEN -+ 8 -+ 1 -+ -+ -+ SDMMC3EN -+ SDMMC3EN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB2ENCLRR -+ RCC_MC_AHB2ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xA9C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMA1EN -+ DMA1EN -+ 0 -+ 1 -+ -+ -+ DMA2EN -+ DMA2EN -+ 1 -+ 1 -+ -+ -+ DMAMUXEN -+ DMAMUXEN -+ 2 -+ 1 -+ -+ -+ ADC12EN -+ ADC12EN -+ 5 -+ 1 -+ -+ -+ USBOEN -+ USBOEN -+ 8 -+ 1 -+ -+ -+ SDMMC3EN -+ SDMMC3EN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB3ENSETR -+ RCC_MC_AHB3ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xAA0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIEN -+ DCMIEN -+ 0 -+ 1 -+ -+ -+ CRYP2EN -+ CRYP2EN -+ 4 -+ 1 -+ -+ -+ HASH2EN -+ HASH2EN -+ 5 -+ 1 -+ -+ -+ RNG2EN -+ RNG2EN -+ 6 -+ 1 -+ -+ -+ CRC2EN -+ CRC2EN -+ 7 -+ 1 -+ -+ -+ HSEMEN -+ HSEMEN -+ 11 -+ 1 -+ -+ -+ IPCCEN -+ IPCCEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB3ENCLRR -+ RCC_MC_AHB3ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xAA4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DCMIEN -+ DCMIEN -+ 0 -+ 1 -+ -+ -+ CRYP2EN -+ CRYP2EN -+ 4 -+ 1 -+ -+ -+ HASH2EN -+ HASH2EN -+ 5 -+ 1 -+ -+ -+ RNG2EN -+ RNG2EN -+ 6 -+ 1 -+ -+ -+ CRC2EN -+ CRC2EN -+ 7 -+ 1 -+ -+ -+ HSEMEN -+ HSEMEN -+ 11 -+ 1 -+ -+ -+ IPCCEN -+ IPCCEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB4ENSETR -+ RCC_MC_AHB4ENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xAA8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOAEN -+ GPIOAEN -+ 0 -+ 1 -+ -+ -+ GPIOBEN -+ GPIOBEN -+ 1 -+ 1 -+ -+ -+ GPIOCEN -+ GPIOCEN -+ 2 -+ 1 -+ -+ -+ GPIODEN -+ GPIODEN -+ 3 -+ 1 -+ -+ -+ GPIOEEN -+ GPIOEEN -+ 4 -+ 1 -+ -+ -+ GPIOFEN -+ GPIOFEN -+ 5 -+ 1 -+ -+ -+ GPIOGEN -+ GPIOGEN -+ 6 -+ 1 -+ -+ -+ GPIOHEN -+ GPIOHEN -+ 7 -+ 1 -+ -+ -+ GPIOIEN -+ GPIOIEN -+ 8 -+ 1 -+ -+ -+ GPIOJEN -+ GPIOJEN -+ 9 -+ 1 -+ -+ -+ GPIOKEN -+ GPIOKEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB4ENCLRR -+ RCC_MC_AHB4ENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xAAC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GPIOAEN -+ GPIOAEN -+ 0 -+ 1 -+ -+ -+ GPIOBEN -+ GPIOBEN -+ 1 -+ 1 -+ -+ -+ GPIOCEN -+ GPIOCEN -+ 2 -+ 1 -+ -+ -+ GPIODEN -+ GPIODEN -+ 3 -+ 1 -+ -+ -+ GPIOEEN -+ GPIOEEN -+ 4 -+ 1 -+ -+ -+ GPIOFEN -+ GPIOFEN -+ 5 -+ 1 -+ -+ -+ GPIOGEN -+ GPIOGEN -+ 6 -+ 1 -+ -+ -+ GPIOHEN -+ GPIOHEN -+ 7 -+ 1 -+ -+ -+ GPIOIEN -+ GPIOIEN -+ 8 -+ 1 -+ -+ -+ GPIOJEN -+ GPIOJEN -+ 9 -+ 1 -+ -+ -+ GPIOKEN -+ GPIOKEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AXIMENSETR -+ RCC_MC_AXIMENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xAB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SYSRAMEN -+ SYSRAMEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AXIMENCLRR -+ RCC_MC_AXIMENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xAB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SYSRAMEN -+ SYSRAMEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_MLAHBENSETR -+ RCC_MC_MLAHBENSETR -+ This register is used to set the peripheral clock enable bit -+ 0xAB8 -+ 0x20 -+ read-write -+ 0x00000010 -+ -+ -+ RETRAMEN -+ RETRAMEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MC_MLAHBENCLRR -+ RCC_MC_MLAHBENCLRR -+ This register is used to clear the peripheral clock enable bit -+ 0xABC -+ 0x20 -+ read-write -+ 0x00000010 -+ -+ -+ RETRAMEN -+ RETRAMEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB1LPENSETR -+ RCC_MP_APB1LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB00 -+ 0x20 -+ read-write -+ 0xADEFDBFF -+ -+ -+ TIM2LPEN -+ TIM2LPEN -+ 0 -+ 1 -+ -+ -+ TIM3LPEN -+ TIM3LPEN -+ 1 -+ 1 -+ -+ -+ TIM4LPEN -+ TIM4LPEN -+ 2 -+ 1 -+ -+ -+ TIM5LPEN -+ TIM5LPEN -+ 3 -+ 1 -+ -+ -+ TIM6LPEN -+ TIM6LPEN -+ 4 -+ 1 -+ -+ -+ TIM7LPEN -+ TIM7LPEN -+ 5 -+ 1 -+ -+ -+ TIM12LPEN -+ TIM12LPEN -+ 6 -+ 1 -+ -+ -+ TIM13LPEN -+ TIM13LPEN -+ 7 -+ 1 -+ -+ -+ TIM14LPEN -+ TIM14LPEN -+ 8 -+ 1 -+ -+ -+ LPTIM1LPEN -+ LPTIM1LPEN -+ 9 -+ 1 -+ -+ -+ SPI2LPEN -+ SPI2LPEN -+ 11 -+ 1 -+ -+ -+ SPI3LPEN -+ SPI3LPEN -+ 12 -+ 1 -+ -+ -+ USART2LPEN -+ USART2LPEN -+ 14 -+ 1 -+ -+ -+ USART3LPEN -+ USART3LPEN -+ 15 -+ 1 -+ -+ -+ UART4LPEN -+ UART4LPEN -+ 16 -+ 1 -+ -+ -+ UART5LPEN -+ UART5LPEN -+ 17 -+ 1 -+ -+ -+ UART7LPEN -+ UART7LPEN -+ 18 -+ 1 -+ -+ -+ UART8LPEN -+ UART8LPEN -+ 19 -+ 1 -+ -+ -+ I2C1LPEN -+ I2C1LPEN -+ 21 -+ 1 -+ -+ -+ I2C2LPEN -+ I2C2LPEN -+ 22 -+ 1 -+ -+ -+ I2C3LPEN -+ I2C3LPEN -+ 23 -+ 1 -+ -+ -+ I2C5LPEN -+ I2C5LPEN -+ 24 -+ 1 -+ -+ -+ SPDIFLPEN -+ SPDIFLPEN -+ 26 -+ 1 -+ -+ -+ CECLPEN -+ CECLPEN -+ 27 -+ 1 -+ -+ -+ DAC12LPEN -+ DAC12LPEN -+ 29 -+ 1 -+ -+ -+ MDIOSLPEN -+ MDIOSLPEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB1LPENCLRR -+ RCC_MP_APB1LPENCLRR -+ This register is used by the MPU in order to clear the PERxLPEN bits . -+ 0xB04 -+ 0x20 -+ read-write -+ 0xADEFDBFF -+ -+ -+ TIM2LPEN -+ TIM2LPEN -+ 0 -+ 1 -+ -+ -+ TIM3LPEN -+ TIM3LPEN -+ 1 -+ 1 -+ -+ -+ TIM4LPEN -+ TIM4LPEN -+ 2 -+ 1 -+ -+ -+ TIM5LPEN -+ TIM5LPEN -+ 3 -+ 1 -+ -+ -+ TIM6LPEN -+ TIM6LPEN -+ 4 -+ 1 -+ -+ -+ TIM7LPEN -+ TIM7LPEN -+ 5 -+ 1 -+ -+ -+ TIM12LPEN -+ TIM12LPEN -+ 6 -+ 1 -+ -+ -+ TIM13LPEN -+ TIM13LPEN -+ 7 -+ 1 -+ -+ -+ TIM14LPEN -+ TIM14LPEN -+ 8 -+ 1 -+ -+ -+ LPTIM1LPEN -+ LPTIM1LPEN -+ 9 -+ 1 -+ -+ -+ SPI2LPEN -+ SPI2LPEN -+ 11 -+ 1 -+ -+ -+ SPI3LPEN -+ SPI3LPEN -+ 12 -+ 1 -+ -+ -+ USART2LPEN -+ USART2LPEN -+ 14 -+ 1 -+ -+ -+ USART3LPEN -+ USART3LPEN -+ 15 -+ 1 -+ -+ -+ UART4LPEN -+ UART4LPEN -+ 16 -+ 1 -+ -+ -+ UART5LPEN -+ UART5LPEN -+ 17 -+ 1 -+ -+ -+ UART7LPEN -+ UART7LPEN -+ 18 -+ 1 -+ -+ -+ UART8LPEN -+ UART8LPEN -+ 19 -+ 1 -+ -+ -+ I2C1LPEN -+ I2C1LPEN -+ 21 -+ 1 -+ -+ -+ I2C2LPEN -+ I2C2LPEN -+ 22 -+ 1 -+ -+ -+ I2C3LPEN -+ I2C3LPEN -+ 23 -+ 1 -+ -+ -+ I2C5LPEN -+ I2C5LPEN -+ 24 -+ 1 -+ -+ -+ SPDIFLPEN -+ SPDIFLPEN -+ 26 -+ 1 -+ -+ -+ CECLPEN -+ CECLPEN -+ 27 -+ 1 -+ -+ -+ DAC12LPEN -+ DAC12LPEN -+ 29 -+ 1 -+ -+ -+ MDIOSLPEN -+ MDIOSLPEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB2LPENSETR -+ RCC_MP_APB2LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB08 -+ 0x20 -+ read-write -+ 0x0137271F -+ -+ -+ TIM1LPEN -+ TIM1LPEN -+ 0 -+ 1 -+ -+ -+ TIM8LPEN -+ TIM8LPEN -+ 1 -+ 1 -+ -+ -+ TIM15LPEN -+ TIM15LPEN -+ 2 -+ 1 -+ -+ -+ TIM16LPEN -+ TIM16LPEN -+ 3 -+ 1 -+ -+ -+ TIM17LPEN -+ TIM17LPEN -+ 4 -+ 1 -+ -+ -+ SPI1LPEN -+ SPI1LPEN -+ 8 -+ 1 -+ -+ -+ SPI4LPEN -+ SPI4LPEN -+ 9 -+ 1 -+ -+ -+ SPI5LPEN -+ SPI5LPEN -+ 10 -+ 1 -+ -+ -+ USART6LPEN -+ USART6LPEN -+ 13 -+ 1 -+ -+ -+ SAI1LPEN -+ SAI1LPEN -+ 16 -+ 1 -+ -+ -+ SAI2LPEN -+ SAI2LPEN -+ 17 -+ 1 -+ -+ -+ SAI3LPEN -+ SAI3LPEN -+ 18 -+ 1 -+ -+ -+ DFSDMLPEN -+ DFSDMLPEN -+ 20 -+ 1 -+ -+ -+ ADFSDMLPEN -+ ADFSDMLPEN -+ 21 -+ 1 -+ -+ -+ FDCANLPEN -+ FDCANLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB2LPENCLRR -+ RCC_MP_APB2LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB0C -+ 0x20 -+ read-write -+ 0x0137271F -+ -+ -+ TIM1LPEN -+ TIM1LPEN -+ 0 -+ 1 -+ -+ -+ TIM8LPEN -+ TIM8LPEN -+ 1 -+ 1 -+ -+ -+ TIM15LPEN -+ TIM15LPEN -+ 2 -+ 1 -+ -+ -+ TIM16LPEN -+ TIM16LPEN -+ 3 -+ 1 -+ -+ -+ TIM17LPEN -+ TIM17LPEN -+ 4 -+ 1 -+ -+ -+ SPI1LPEN -+ SPI1LPEN -+ 8 -+ 1 -+ -+ -+ SPI4LPEN -+ SPI4LPEN -+ 9 -+ 1 -+ -+ -+ SPI5LPEN -+ SPI5LPEN -+ 10 -+ 1 -+ -+ -+ USART6LPEN -+ USART6LPEN -+ 13 -+ 1 -+ -+ -+ SAI1LPEN -+ SAI1LPEN -+ 16 -+ 1 -+ -+ -+ SAI2LPEN -+ SAI2LPEN -+ 17 -+ 1 -+ -+ -+ SAI3LPEN -+ SAI3LPEN -+ 18 -+ 1 -+ -+ -+ DFSDMLPEN -+ DFSDMLPEN -+ 20 -+ 1 -+ -+ -+ ADFSDMLPEN -+ ADFSDMLPEN -+ 21 -+ 1 -+ -+ -+ FDCANLPEN -+ FDCANLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB3LPENSETR -+ RCC_MP_APB3LPENSETR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB10 -+ 0x20 -+ read-write -+ 0x0003290F -+ -+ -+ LPTIM2LPEN -+ LPTIM2LPEN -+ 0 -+ 1 -+ -+ -+ LPTIM3LPEN -+ LPTIM3LPEN -+ 1 -+ 1 -+ -+ -+ LPTIM4LPEN -+ LPTIM4LPEN -+ 2 -+ 1 -+ -+ -+ LPTIM5LPEN -+ LPTIM5LPEN -+ 3 -+ 1 -+ -+ -+ SAI4LPEN -+ SAI4LPEN -+ 8 -+ 1 -+ -+ -+ SYSCFGLPEN -+ SYSCFGLPEN -+ 11 -+ 1 -+ -+ -+ VREFLPEN -+ VREFLPEN -+ 13 -+ 1 -+ -+ -+ DTSLPEN -+ DTSLPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_APB3LPENCLRR -+ RCC_MP_APB3LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB14 -+ 0x20 -+ read-write -+ 0x0003290F -+ -+ -+ LPTIM2LPEN -+ LPTIM2LPEN -+ 0 -+ 1 -+ -+ -+ LPTIM3LPEN -+ LPTIM3LPEN -+ 1 -+ 1 -+ -+ -+ LPTIM4LPEN -+ LPTIM4LPEN -+ 2 -+ 1 -+ -+ -+ LPTIM5LPEN -+ LPTIM5LPEN -+ 3 -+ 1 -+ -+ -+ SAI4LPEN -+ SAI4LPEN -+ 8 -+ 1 -+ -+ -+ SYSCFGLPEN -+ SYSCFGLPEN -+ 11 -+ 1 -+ -+ -+ VREFLPEN -+ VREFLPEN -+ 13 -+ 1 -+ -+ -+ DTSLPEN -+ DTSLPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB2LPENSETR -+ RCC_MP_AHB2LPENSETR -+ This register is used by the MPU in order to set the PERxLPEN bit. -+ 0xB18 -+ 0x20 -+ read-write -+ 0x00010127 -+ -+ -+ DMA1LPEN -+ DMA1LPEN -+ 0 -+ 1 -+ -+ -+ DMA2LPEN -+ DMA2LPEN -+ 1 -+ 1 -+ -+ -+ DMAMUXLPEN -+ DMAMUXLPEN -+ 2 -+ 1 -+ -+ -+ ADC12LPEN -+ ADC12LPEN -+ 5 -+ 1 -+ -+ -+ USBOLPEN -+ USBOLPEN -+ 8 -+ 1 -+ -+ -+ SDMMC3LPEN -+ SDMMC3LPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB2LPENCLRR -+ RCC_MP_AHB2LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB1C -+ 0x20 -+ read-write -+ 0x00010127 -+ -+ -+ DMA1LPEN -+ DMA1LPEN -+ 0 -+ 1 -+ -+ -+ DMA2LPEN -+ DMA2LPEN -+ 1 -+ 1 -+ -+ -+ DMAMUXLPEN -+ DMAMUXLPEN -+ 2 -+ 1 -+ -+ -+ ADC12LPEN -+ ADC12LPEN -+ 5 -+ 1 -+ -+ -+ USBOLPEN -+ USBOLPEN -+ 8 -+ 1 -+ -+ -+ SDMMC3LPEN -+ SDMMC3LPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB3LPENSETR -+ RCC_MP_AHB3LPENSETR -+ This register is used by the MPU -+ 0xB20 -+ 0x20 -+ read-write -+ 0x000018F1 -+ -+ -+ DCMILPEN -+ DCMILPEN -+ 0 -+ 1 -+ -+ -+ CRYP2LPEN -+ CRYP2LPEN -+ 4 -+ 1 -+ -+ -+ HASH2LPEN -+ HASH2LPEN -+ 5 -+ 1 -+ -+ -+ RNG2LPEN -+ RNG2LPEN -+ 6 -+ 1 -+ -+ -+ CRC2LPEN -+ CRC2LPEN -+ 7 -+ 1 -+ -+ -+ HSEMLPEN -+ HSEMLPEN -+ 11 -+ 1 -+ -+ -+ IPCCLPEN -+ IPCCLPEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB3LPENCLRR -+ RCC_MP_AHB3LPENCLRR -+ This register is used by the MPU in order to clear the PERxLPEN bit -+ 0xB24 -+ 0x20 -+ read-write -+ 0x000018F1 -+ -+ -+ DCMILPEN -+ DCMILPEN -+ 0 -+ 1 -+ -+ -+ CRYP2LPEN -+ CRYP2LPEN -+ 4 -+ 1 -+ -+ -+ HASH2LPEN -+ HASH2LPEN -+ 5 -+ 1 -+ -+ -+ RNG2LPEN -+ RNG2LPEN -+ 6 -+ 1 -+ -+ -+ CRC2LPEN -+ CRC2LPEN -+ 7 -+ 1 -+ -+ -+ HSEMLPEN -+ HSEMLPEN -+ 11 -+ 1 -+ -+ -+ IPCCLPEN -+ IPCCLPEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB4LPENSETR -+ RCC_MP_AHB4LPENSETR -+ This register is used by the MPU -+ 0xB28 -+ 0x20 -+ read-write -+ 0x000007FF -+ -+ -+ GPIOALPEN -+ GPIOALPEN -+ 0 -+ 1 -+ -+ -+ GPIOBLPEN -+ GPIOBLPEN -+ 1 -+ 1 -+ -+ -+ GPIOCLPEN -+ GPIOCLPEN -+ 2 -+ 1 -+ -+ -+ GPIODLPEN -+ GPIODLPEN -+ 3 -+ 1 -+ -+ -+ GPIOELPEN -+ GPIOELPEN -+ 4 -+ 1 -+ -+ -+ GPIOFLPEN -+ GPIOFLPEN -+ 5 -+ 1 -+ -+ -+ GPIOGLPEN -+ GPIOGLPEN -+ 6 -+ 1 -+ -+ -+ GPIOHLPEN -+ GPIOHLPEN -+ 7 -+ 1 -+ -+ -+ GPIOILPEN -+ GPIOILPEN -+ 8 -+ 1 -+ -+ -+ GPIOJLPEN -+ GPIOJLPEN -+ 9 -+ 1 -+ -+ -+ GPIOKLPEN -+ GPIOKLPEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AHB4LPENCLRR -+ RCC_MP_AHB4LPENCLRR -+ This register is used by the MPU -+ 0xB2C -+ 0x20 -+ read-write -+ 0x000007FF -+ -+ -+ GPIOALPEN -+ GPIOALPEN -+ 0 -+ 1 -+ -+ -+ GPIOBLPEN -+ GPIOBLPEN -+ 1 -+ 1 -+ -+ -+ GPIOCLPEN -+ GPIOCLPEN -+ 2 -+ 1 -+ -+ -+ GPIODLPEN -+ GPIODLPEN -+ 3 -+ 1 -+ -+ -+ GPIOELPEN -+ GPIOELPEN -+ 4 -+ 1 -+ -+ -+ GPIOFLPEN -+ GPIOFLPEN -+ 5 -+ 1 -+ -+ -+ GPIOGLPEN -+ GPIOGLPEN -+ 6 -+ 1 -+ -+ -+ GPIOHLPEN -+ GPIOHLPEN -+ 7 -+ 1 -+ -+ -+ GPIOILPEN -+ GPIOILPEN -+ 8 -+ 1 -+ -+ -+ GPIOJLPEN -+ GPIOJLPEN -+ 9 -+ 1 -+ -+ -+ GPIOKLPEN -+ GPIOKLPEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AXIMLPENSETR -+ RCC_MP_AXIMLPENSETR -+ This register is used by the MPU -+ 0xB30 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SYSRAMLPEN -+ SYSRAMLPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_AXIMLPENCLRR -+ RCC_MP_AXIMLPENCLRR -+ This register is used by the MPU -+ 0xB34 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SYSRAMLPEN -+ SYSRAMLPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MP_MLAHBLPENSETR -+ RCC_MP_MLAHBLPENSETR -+ This register is used by the MPU in order to set the PERxLPEN bit -+ 0xB38 -+ 0x20 -+ read-write -+ 0x00000017 -+ -+ -+ SRAM1LPEN -+ SRAM1LPEN -+ 0 -+ 1 -+ -+ -+ SRAM2LPEN -+ SRAM2LPEN -+ 1 -+ 1 -+ -+ -+ SRAM34LPEN -+ SRAM34LPEN -+ 2 -+ 1 -+ -+ -+ RETRAMLPEN -+ RETRAMLPEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MP_MLAHBLPENCLRR -+ RCC_MP_MLAHBLPENCLRR -+ This register is used by the MPU in order to clear the PERxLPEN bit -+ 0xB3C -+ 0x20 -+ read-write -+ 0x00000017 -+ -+ -+ SRAM1LPEN -+ SRAM1LPEN -+ 0 -+ 1 -+ -+ -+ SRAM2LPEN -+ SRAM2LPEN -+ 1 -+ 1 -+ -+ -+ SRAM34LPEN -+ SRAM34LPEN -+ 2 -+ 1 -+ -+ -+ RETRAMLPEN -+ RETRAMLPEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB1LPENSETR -+ RCC_MC_APB1LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xB80 -+ 0x20 -+ read-write -+ 0xBDEFDBFF -+ -+ -+ TIM2LPEN -+ TIM2LPEN -+ 0 -+ 1 -+ -+ -+ TIM3LPEN -+ TIM3LPEN -+ 1 -+ 1 -+ -+ -+ TIM4LPEN -+ TIM4LPEN -+ 2 -+ 1 -+ -+ -+ TIM5LPEN -+ TIM5LPEN -+ 3 -+ 1 -+ -+ -+ TIM6LPEN -+ TIM6LPEN -+ 4 -+ 1 -+ -+ -+ TIM7LPEN -+ TIM7LPEN -+ 5 -+ 1 -+ -+ -+ TIM12LPEN -+ TIM12LPEN -+ 6 -+ 1 -+ -+ -+ TIM13LPEN -+ TIM13LPEN -+ 7 -+ 1 -+ -+ -+ TIM14LPEN -+ TIM14LPEN -+ 8 -+ 1 -+ -+ -+ LPTIM1LPEN -+ LPTIM1LPEN -+ 9 -+ 1 -+ -+ -+ SPI2LPEN -+ SPI2LPEN -+ 11 -+ 1 -+ -+ -+ SPI3LPEN -+ SPI3LPEN -+ 12 -+ 1 -+ -+ -+ USART2LPEN -+ USART2LPEN -+ 14 -+ 1 -+ -+ -+ USART3LPEN -+ USART3LPEN -+ 15 -+ 1 -+ -+ -+ UART4LPEN -+ UART4LPEN -+ 16 -+ 1 -+ -+ -+ UART5LPEN -+ UART5LPEN -+ 17 -+ 1 -+ -+ -+ UART7LPEN -+ UART7LPEN -+ 18 -+ 1 -+ -+ -+ UART8LPEN -+ UART8LPEN -+ 19 -+ 1 -+ -+ -+ I2C1LPEN -+ I2C1LPEN -+ 21 -+ 1 -+ -+ -+ I2C2LPEN -+ I2C2LPEN -+ 22 -+ 1 -+ -+ -+ I2C3LPEN -+ I2C3LPEN -+ 23 -+ 1 -+ -+ -+ I2C5LPEN -+ I2C5LPEN -+ 24 -+ 1 -+ -+ -+ SPDIFLPEN -+ SPDIFLPEN -+ 26 -+ 1 -+ -+ -+ CECLPEN -+ CECLPEN -+ 27 -+ 1 -+ -+ -+ WWDG1LPEN -+ WWDG1LPEN -+ 28 -+ 1 -+ -+ -+ DAC12LPEN -+ DAC12LPEN -+ 29 -+ 1 -+ -+ -+ MDIOSLPEN -+ MDIOSLPEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB1LPENCLRR -+ RCC_MC_APB1LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bits -+ 0xB84 -+ 0x20 -+ read-write -+ 0xBDEFDBFF -+ -+ -+ TIM2LPEN -+ TIM2LPEN -+ 0 -+ 1 -+ -+ -+ TIM3LPEN -+ TIM3LPEN -+ 1 -+ 1 -+ -+ -+ TIM4LPEN -+ TIM4LPEN -+ 2 -+ 1 -+ -+ -+ TIM5LPEN -+ TIM5LPEN -+ 3 -+ 1 -+ -+ -+ TIM6LPEN -+ TIM6LPEN -+ 4 -+ 1 -+ -+ -+ TIM7LPEN -+ TIM7LPEN -+ 5 -+ 1 -+ -+ -+ TIM12LPEN -+ TIM12LPEN -+ 6 -+ 1 -+ -+ -+ TIM13LPEN -+ TIM13LPEN -+ 7 -+ 1 -+ -+ -+ TIM14LPEN -+ TIM14LPEN -+ 8 -+ 1 -+ -+ -+ LPTIM1LPEN -+ LPTIM1LPEN -+ 9 -+ 1 -+ -+ -+ SPI2LPEN -+ SPI2LPEN -+ 11 -+ 1 -+ -+ -+ SPI3LPEN -+ SPI3LPEN -+ 12 -+ 1 -+ -+ -+ USART2LPEN -+ USART2LPEN -+ 14 -+ 1 -+ -+ -+ USART3LPEN -+ USART3LPEN -+ 15 -+ 1 -+ -+ -+ UART4LPEN -+ UART4LPEN -+ 16 -+ 1 -+ -+ -+ UART5LPEN -+ UART5LPEN -+ 17 -+ 1 -+ -+ -+ UART7LPEN -+ UART7LPEN -+ 18 -+ 1 -+ -+ -+ UART8LPEN -+ UART8LPEN -+ 19 -+ 1 -+ -+ -+ I2C1LPEN -+ I2C1LPEN -+ 21 -+ 1 -+ -+ -+ I2C2LPEN -+ I2C2LPEN -+ 22 -+ 1 -+ -+ -+ I2C3LPEN -+ I2C3LPEN -+ 23 -+ 1 -+ -+ -+ I2C5LPEN -+ I2C5LPEN -+ 24 -+ 1 -+ -+ -+ SPDIFLPEN -+ SPDIFLPEN -+ 26 -+ 1 -+ -+ -+ CECLPEN -+ CECLPEN -+ 27 -+ 1 -+ -+ -+ WWDG1LPEN -+ WWDG1LPEN -+ 28 -+ 1 -+ -+ -+ DAC12LPEN -+ DAC12LPEN -+ 29 -+ 1 -+ -+ -+ MDIOSLPEN -+ MDIOSLPEN -+ 31 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB2LPENSETR -+ RCC_MC_APB2LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xB88 -+ 0x20 -+ read-write -+ 0x0137271F -+ -+ -+ TIM1LPEN -+ TIM1LPEN -+ 0 -+ 1 -+ -+ -+ TIM8LPEN -+ TIM8LPEN -+ 1 -+ 1 -+ -+ -+ TIM15LPEN -+ TIM15LPEN -+ 2 -+ 1 -+ -+ -+ TIM16LPEN -+ TIM16LPEN -+ 3 -+ 1 -+ -+ -+ TIM17LPEN -+ TIM17LPEN -+ 4 -+ 1 -+ -+ -+ SPI1LPEN -+ SPI1LPEN -+ 8 -+ 1 -+ -+ -+ SPI4LPEN -+ SPI4LPEN -+ 9 -+ 1 -+ -+ -+ SPI5LPEN -+ SPI5LPEN -+ 10 -+ 1 -+ -+ -+ USART6LPEN -+ USART6LPEN -+ 13 -+ 1 -+ -+ -+ SAI1LPEN -+ SAI1LPEN -+ 16 -+ 1 -+ -+ -+ SAI2LPEN -+ SAI2LPEN -+ 17 -+ 1 -+ -+ -+ SAI3LPEN -+ SAI3LPEN -+ 18 -+ 1 -+ -+ -+ DFSDMLPEN -+ DFSDMLPEN -+ 20 -+ 1 -+ -+ -+ ADFSDMLPEN -+ ADFSDMLPEN -+ 21 -+ 1 -+ -+ -+ FDCANLPEN -+ FDCANLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB2LPENCLRR -+ RCC_MC_APB2LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0xB8C -+ 0x20 -+ read-write -+ 0x0137271F -+ -+ -+ TIM1LPEN -+ TIM1LPEN -+ 0 -+ 1 -+ -+ -+ TIM8LPEN -+ TIM8LPEN -+ 1 -+ 1 -+ -+ -+ TIM15LPEN -+ TIM15LPEN -+ 2 -+ 1 -+ -+ -+ TIM16LPEN -+ TIM16LPEN -+ 3 -+ 1 -+ -+ -+ TIM17LPEN -+ TIM17LPEN -+ 4 -+ 1 -+ -+ -+ SPI1LPEN -+ SPI1LPEN -+ 8 -+ 1 -+ -+ -+ SPI4LPEN -+ SPI4LPEN -+ 9 -+ 1 -+ -+ -+ SPI5LPEN -+ SPI5LPEN -+ 10 -+ 1 -+ -+ -+ USART6LPEN -+ USART6LPEN -+ 13 -+ 1 -+ -+ -+ SAI1LPEN -+ SAI1LPEN -+ 16 -+ 1 -+ -+ -+ SAI2LPEN -+ SAI2LPEN -+ 17 -+ 1 -+ -+ -+ SAI3LPEN -+ SAI3LPEN -+ 18 -+ 1 -+ -+ -+ DFSDMLPEN -+ DFSDMLPEN -+ 20 -+ 1 -+ -+ -+ ADFSDMLPEN -+ ADFSDMLPEN -+ 21 -+ 1 -+ -+ -+ FDCANLPEN -+ FDCANLPEN -+ 24 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB3LPENSETR -+ RCC_MC_APB3LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xB90 -+ 0x20 -+ read-write -+ 0x0003290F -+ -+ -+ LPTIM2LPEN -+ LPTIM2LPEN -+ 0 -+ 1 -+ -+ -+ LPTIM3LPEN -+ LPTIM3LPEN -+ 1 -+ 1 -+ -+ -+ LPTIM4LPEN -+ LPTIM4LPEN -+ 2 -+ 1 -+ -+ -+ LPTIM5LPEN -+ LPTIM5LPEN -+ 3 -+ 1 -+ -+ -+ SAI4LPEN -+ SAI4LPEN -+ 8 -+ 1 -+ -+ -+ SYSCFGLPEN -+ SYSCFGLPEN -+ 11 -+ 1 -+ -+ -+ VREFLPEN -+ VREFLPEN -+ 13 -+ 1 -+ -+ -+ DTSLPEN -+ DTSLPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_APB3LPENCLRR -+ RCC_MC_APB3LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0xB94 -+ 0x20 -+ read-write -+ 0x0003290F -+ -+ -+ LPTIM2LPEN -+ LPTIM2LPEN -+ 0 -+ 1 -+ -+ -+ LPTIM3LPEN -+ LPTIM3LPEN -+ 1 -+ 1 -+ -+ -+ LPTIM4LPEN -+ LPTIM4LPEN -+ 2 -+ 1 -+ -+ -+ LPTIM5LPEN -+ LPTIM5LPEN -+ 3 -+ 1 -+ -+ -+ SAI4LPEN -+ SAI4LPEN -+ 8 -+ 1 -+ -+ -+ SYSCFGLPEN -+ SYSCFGLPEN -+ 11 -+ 1 -+ -+ -+ VREFLPEN -+ VREFLPEN -+ 13 -+ 1 -+ -+ -+ DTSLPEN -+ DTSLPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB2LPENSETR -+ RCC_MC_AHB2LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xB98 -+ 0x20 -+ read-write -+ 0x00010127 -+ -+ -+ DMA1LPEN -+ DMA1LPEN -+ 0 -+ 1 -+ -+ -+ DMA2LPEN -+ DMA2LPEN -+ 1 -+ 1 -+ -+ -+ DMAMUXLPEN -+ DMAMUXLPEN -+ 2 -+ 1 -+ -+ -+ ADC12LPEN -+ ADC12LPEN -+ 5 -+ 1 -+ -+ -+ USBOLPEN -+ USBOLPEN -+ 8 -+ 1 -+ -+ -+ SDMMC3LPEN -+ SDMMC3LPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB2LPENCLRR -+ RCC_MC_AHB2LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0xB9C -+ 0x20 -+ read-write -+ 0x00010127 -+ -+ -+ DMA1LPEN -+ DMA1LPEN -+ 0 -+ 1 -+ -+ -+ DMA2LPEN -+ DMA2LPEN -+ 1 -+ 1 -+ -+ -+ DMAMUXLPEN -+ DMAMUXLPEN -+ 2 -+ 1 -+ -+ -+ ADC12LPEN -+ ADC12LPEN -+ 5 -+ 1 -+ -+ -+ USBOLPEN -+ USBOLPEN -+ 8 -+ 1 -+ -+ -+ SDMMC3LPEN -+ SDMMC3LPEN -+ 16 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB3LPENSETR -+ RCC_MC_AHB3LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xBA0 -+ 0x20 -+ read-write -+ 0x000018F1 -+ -+ -+ DCMILPEN -+ DCMILPEN -+ 0 -+ 1 -+ -+ -+ CRYP2LPEN -+ CRYP2LPEN -+ 4 -+ 1 -+ -+ -+ HASH2LPEN -+ HASH2LPEN -+ 5 -+ 1 -+ -+ -+ RNG2LPEN -+ RNG2LPEN -+ 6 -+ 1 -+ -+ -+ CRC2LPEN -+ CRC2LPEN -+ 7 -+ 1 -+ -+ -+ HSEMLPEN -+ HSEMLPEN -+ 11 -+ 1 -+ -+ -+ IPCCLPEN -+ IPCCLPEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB3LPENCLRR -+ RCC_MC_AHB3LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit -+ 0xBA4 -+ 0x20 -+ read-write -+ 0x000018F1 -+ -+ -+ DCMILPEN -+ DCMILPEN -+ 0 -+ 1 -+ -+ -+ CRYP2LPEN -+ CRYP2LPEN -+ 4 -+ 1 -+ -+ -+ HASH2LPEN -+ HASH2LPEN -+ 5 -+ 1 -+ -+ -+ RNG2LPEN -+ RNG2LPEN -+ 6 -+ 1 -+ -+ -+ CRC2LPEN -+ CRC2LPEN -+ 7 -+ 1 -+ -+ -+ HSEMLPEN -+ HSEMLPEN -+ 11 -+ 1 -+ -+ -+ IPCCLPEN -+ IPCCLPEN -+ 12 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB4LPENSETR -+ RCC_MC_AHB4LPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit. -+ 0xBA8 -+ 0x20 -+ read-write -+ 0x000007FF -+ -+ -+ GPIOALPEN -+ GPIOALPEN -+ 0 -+ 1 -+ -+ -+ GPIOBLPEN -+ GPIOBLPEN -+ 1 -+ 1 -+ -+ -+ GPIOCLPEN -+ GPIOCLPEN -+ 2 -+ 1 -+ -+ -+ GPIODLPEN -+ GPIODLPEN -+ 3 -+ 1 -+ -+ -+ GPIOELPEN -+ GPIOELPEN -+ 4 -+ 1 -+ -+ -+ GPIOFLPEN -+ GPIOFLPEN -+ 5 -+ 1 -+ -+ -+ GPIOGLPEN -+ GPIOGLPEN -+ 6 -+ 1 -+ -+ -+ GPIOHLPEN -+ GPIOHLPEN -+ 7 -+ 1 -+ -+ -+ GPIOILPEN -+ GPIOILPEN -+ 8 -+ 1 -+ -+ -+ GPIOJLPEN -+ GPIOJLPEN -+ 9 -+ 1 -+ -+ -+ GPIOKLPEN -+ GPIOKLPEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AHB4LPENCLRR -+ RCC_MC_AHB4LPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. -+ 0xBAC -+ 0x20 -+ read-write -+ 0x000007FF -+ -+ -+ GPIOALPEN -+ GPIOALPEN -+ 0 -+ 1 -+ -+ -+ GPIOBLPEN -+ GPIOBLPEN -+ 1 -+ 1 -+ -+ -+ GPIOCLPEN -+ GPIOCLPEN -+ 2 -+ 1 -+ -+ -+ GPIODLPEN -+ GPIODLPEN -+ 3 -+ 1 -+ -+ -+ GPIOELPEN -+ GPIOELPEN -+ 4 -+ 1 -+ -+ -+ GPIOFLPEN -+ GPIOFLPEN -+ 5 -+ 1 -+ -+ -+ GPIOGLPEN -+ GPIOGLPEN -+ 6 -+ 1 -+ -+ -+ GPIOHLPEN -+ GPIOHLPEN -+ 7 -+ 1 -+ -+ -+ GPIOILPEN -+ GPIOILPEN -+ 8 -+ 1 -+ -+ -+ GPIOJLPEN -+ GPIOJLPEN -+ 9 -+ 1 -+ -+ -+ GPIOKLPEN -+ GPIOKLPEN -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AXIMLPENSETR -+ RCC_MC_AXIMLPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. -+ 0xBB0 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SYSRAMLPEN -+ SYSRAMLPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_AXIMLPENCLRR -+ RCC_MC_AXIMLPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. -+ 0xBB4 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ SYSRAMLPEN -+ SYSRAMLPEN -+ 0 -+ 1 -+ -+ -+ -+ -+ RCC_MC_MLAHBLPENSETR -+ RCC_MC_MLAHBLPENSETR -+ This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. -+ 0xBB8 -+ 0x20 -+ read-write -+ 0x00000017 -+ -+ -+ SRAM1LPEN -+ SRAM1LPEN -+ 0 -+ 1 -+ -+ -+ SRAM2LPEN -+ SRAM2LPEN -+ 1 -+ 1 -+ -+ -+ SRAM34LPEN -+ SRAM34LPEN -+ 2 -+ 1 -+ -+ -+ RETRAMLPEN -+ RETRAMLPEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MC_MLAHBLPENCLRR -+ RCC_MC_MLAHBLPENCLRR -+ This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. -+ 0xBBC -+ 0x20 -+ read-write -+ 0x00000017 -+ -+ -+ SRAM1LPEN -+ SRAM1LPEN -+ 0 -+ 1 -+ -+ -+ SRAM2LPEN -+ SRAM2LPEN -+ 1 -+ 1 -+ -+ -+ SRAM34LPEN -+ SRAM34LPEN -+ 2 -+ 1 -+ -+ -+ RETRAMLPEN -+ RETRAMLPEN -+ 4 -+ 1 -+ -+ -+ -+ -+ RCC_MC_RSTSCLRR -+ RCC_MC_RSTSCLRR -+ This register is used by the MCU to check the reset source. -+ 0xC00 -+ 0x20 -+ read-write -+ 0x00000015 -+ -+ -+ PORRSTF -+ PORRSTF -+ 0 -+ 1 -+ -+ -+ BORRSTF -+ BORRSTF -+ 1 -+ 1 -+ -+ -+ PADRSTF -+ PADRSTF -+ 2 -+ 1 -+ -+ -+ HCSSRSTF -+ HCSSRSTF -+ 3 -+ 1 -+ -+ -+ VCORERSTF -+ VCORERSTF -+ 4 -+ 1 -+ -+ -+ MCURSTF -+ MCURSTF -+ 5 -+ 1 -+ -+ -+ MPSYSRSTF -+ MPSYSRSTF -+ 6 -+ 1 -+ -+ -+ MCSYSRSTF -+ MCSYSRSTF -+ 7 -+ 1 -+ -+ -+ IWDG1RSTF -+ IWDG1RSTF -+ 8 -+ 1 -+ -+ -+ IWDG2RSTF -+ IWDG2RSTF -+ 9 -+ 1 -+ -+ -+ WWDG1RSTF -+ WWDG1RSTF -+ 10 -+ 1 -+ -+ -+ -+ -+ RCC_MC_CIER -+ RCC_MC_CIER -+ This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. -+ 0xC14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LSIRDYIE -+ LSIRDYIE -+ 0 -+ 1 -+ -+ -+ LSERDYIE -+ LSERDYIE -+ 1 -+ 1 -+ -+ -+ HSIRDYIE -+ HSIRDYIE -+ 2 -+ 1 -+ -+ -+ HSERDYIE -+ HSERDYIE -+ 3 -+ 1 -+ -+ -+ CSIRDYIE -+ CSIRDYIE -+ 4 -+ 1 -+ -+ -+ PLL1DYIE -+ PLL1DYIE -+ 8 -+ 1 -+ -+ -+ PLL2DYIE -+ PLL2DYIE -+ 9 -+ 1 -+ -+ -+ PLL3DYIE -+ PLL3DYIE -+ 10 -+ 1 -+ -+ -+ PLL4DYIE -+ PLL4DYIE -+ 11 -+ 1 -+ -+ -+ LSECSSIE -+ LSECSSIE -+ 16 -+ 1 -+ -+ -+ WKUPIE -+ WKUPIE -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_MC_CIFR -+ RCC_MC_CIFR -+ This register shall be used by the MCU in order to read and clear the interrupt flags. -+ 0xC18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ LSIRDYF -+ LSIRDYF -+ 0 -+ 1 -+ -+ -+ LSERDYF -+ LSERDYF -+ 1 -+ 1 -+ -+ -+ HSIRDYF -+ HSIRDYF -+ 2 -+ 1 -+ -+ -+ HSERDYF -+ HSERDYF -+ 3 -+ 1 -+ -+ -+ CSIRDYF -+ CSIRDYF -+ 4 -+ 1 -+ -+ -+ PLL1DYF -+ PLL1DYF -+ 8 -+ 1 -+ -+ -+ PLL2DYF -+ PLL2DYF -+ 9 -+ 1 -+ -+ -+ PLL3DYF -+ PLL3DYF -+ 10 -+ 1 -+ -+ -+ PLL4DYF -+ PLL4DYF -+ 11 -+ 1 -+ -+ -+ LSECSSF -+ LSECSSF -+ 16 -+ 1 -+ -+ -+ WKUPF -+ WKUPF -+ 20 -+ 1 -+ -+ -+ -+ -+ RCC_VERR -+ RCC_VERR -+ This register gives the IP version -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ RCC_IDR -+ RCC_IDR -+ This register gives the unique identifier of the RCC -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00000001 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ -+ -+ -+ -+ RCC_SIDR -+ RCC_SIDR -+ This register gives the decoding space, which is for the RCC of 4 kB. -+ 0xFFC -+ 0x20 -+ read-only -+ 0xA3C5DD04 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ IPCC -+ IPCC -+ IPCC -+ 0x4C001000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ IPCC_C1CR -+ IPCC_C1CR -+ IPCC Processor 1 control register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXOIE -+ RXOIE -+ 0 -+ 1 -+ -+ -+ TXFIE -+ TXFIE -+ 16 -+ 1 -+ -+ -+ -+ -+ IPCC_C1MR -+ IPCC_C1MR -+ IPCC Processor 1 mask register -+ 0x4 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ CHxOM -+ CHxOM -+ 0 -+ 6 -+ -+ -+ CHxFM -+ CHxFM -+ 16 -+ 6 -+ -+ -+ -+ -+ IPCC_C1SCR -+ IPCC_C1SCR -+ Reading this register will always return 0x0000 0000. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CHxC -+ CHxC -+ 0 -+ 6 -+ -+ -+ CHxS -+ CHxS -+ 16 -+ 6 -+ -+ -+ -+ -+ IPCC_C1TOC2SR -+ IPCC_C1TOC2SR -+ IPCC processor 1 to processor 2 status register -+ 0xC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CHxF -+ CHxF -+ 0 -+ 6 -+ -+ -+ -+ -+ IPCC_C2CR -+ IPCC_C2CR -+ IPCC Processor 2 control register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXOIE -+ RXOIE -+ 0 -+ 1 -+ -+ -+ TXFIE -+ TXFIE -+ 16 -+ 1 -+ -+ -+ -+ -+ IPCC_C2MR -+ IPCC_C2MR -+ IPCC Processor 2 mask register -+ 0x14 -+ 0x20 -+ read-write -+ 0xFFFFFFFF -+ -+ -+ CHxOM -+ CHxOM -+ 0 -+ 6 -+ -+ -+ CHxFM -+ CHxFM -+ 16 -+ 6 -+ -+ -+ -+ -+ IPCC_C2SCR -+ IPCC_C2SCR -+ Reading this register will always return 0x0000 0000. -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CHxC -+ CHxC -+ 0 -+ 6 -+ -+ -+ CHxS -+ CHxS -+ 16 -+ 6 -+ -+ -+ -+ -+ IPCC_C2TOC1SR -+ IPCC_C2TOC1SR -+ IPCC processor 2 to processor 1 status register -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CHxF -+ CHxF -+ 0 -+ 6 -+ -+ -+ -+ -+ IPCC_HWCFGR -+ IPCC_HWCFGR -+ IPCC Hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000002 -+ -+ -+ CHANNELS -+ CHANNELS -+ 0 -+ 8 -+ -+ -+ -+ -+ IPCC_VER -+ IPCC_VER -+ IPCC IP Version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ -+ -+ -+ -+ IPCC_ID -+ IPCC_ID -+ IPCC IP Identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00100071 -+ -+ -+ IPID -+ IPID -+ 0 -+ 32 -+ -+ -+ -+ -+ IPCC_SID -+ IPCC_SID -+ IPCC Size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ -+ -+ -+ -+ -+ -+ OTGHSFS1 -+ OTGHSFS1 -+ OTGHSFS1 -+ 0x49000000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ OTG_GOTGCTL -+ OTG_GOTGCTL -+ The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. -+ 0x0 -+ 0x20 -+ 0x00010000 -+ -+ -+ SRQSCS -+ SRQSCS -+ 0 -+ 1 -+ read-only -+ -+ -+ SRQ -+ SRQ -+ 1 -+ 1 -+ read-write -+ -+ -+ VBVALOEN -+ VBVALOEN -+ 2 -+ 1 -+ read-write -+ -+ -+ VBVALOVAL -+ VBVALOVAL -+ 3 -+ 1 -+ read-write -+ -+ -+ AVALOEN -+ AVALOEN -+ 4 -+ 1 -+ read-write -+ -+ -+ AVALOVAL -+ AVALOVAL -+ 5 -+ 1 -+ read-write -+ -+ -+ BVALOEN -+ BVALOEN -+ 6 -+ 1 -+ read-write -+ -+ -+ BVALOVAL -+ BVALOVAL -+ 7 -+ 1 -+ read-write -+ -+ -+ HNGSCS -+ HNGSCS -+ 8 -+ 1 -+ read-only -+ -+ -+ HNPRQ -+ HNPRQ -+ 9 -+ 1 -+ read-write -+ -+ -+ HSHNPEN -+ HSHNPEN -+ 10 -+ 1 -+ read-write -+ -+ -+ DHNPEN -+ DHNPEN -+ 11 -+ 1 -+ read-write -+ -+ -+ EHEN -+ EHEN -+ 12 -+ 1 -+ read-write -+ -+ -+ CIDSTS -+ CIDSTS -+ 16 -+ 1 -+ read-only -+ -+ -+ DBCT -+ DBCT -+ 17 -+ 1 -+ read-only -+ -+ -+ ASVLD -+ ASVLD -+ 18 -+ 1 -+ read-only -+ -+ -+ BSVLD -+ BSVLD -+ 19 -+ 1 -+ read-only -+ -+ -+ OTGVER -+ OTGVER -+ 20 -+ 1 -+ read-write -+ -+ -+ CURMOD -+ CURMOD -+ 21 -+ 1 -+ read-only -+ -+ -+ -+ -+ OTG_GOTGINT -+ OTG_GOTGINT -+ The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SEDET -+ SEDET -+ 2 -+ 1 -+ -+ -+ SRSSCHG -+ SRSSCHG -+ 8 -+ 1 -+ -+ -+ HNSSCHG -+ HNSSCHG -+ 9 -+ 1 -+ -+ -+ HNGDET -+ HNGDET -+ 17 -+ 1 -+ -+ -+ ADTOCHG -+ ADTOCHG -+ 18 -+ 1 -+ -+ -+ DBCDNE -+ DBCDNE -+ 19 -+ 1 -+ -+ -+ IDCHNG -+ IDCHNG -+ 20 -+ 1 -+ -+ -+ -+ -+ OTG_GAHBCFG -+ OTG_GAHBCFG -+ This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ GINTMSK -+ GINTMSK -+ 0 -+ 1 -+ -+ -+ HBSTLEN -+ HBSTLEN -+ 1 -+ 4 -+ -+ -+ DMAEN -+ DMAEN -+ 5 -+ 1 -+ -+ -+ TXFELVL -+ TXFELVL -+ 7 -+ 1 -+ -+ -+ PTXFELVL -+ PTXFELVL -+ 8 -+ 1 -+ -+ -+ -+ -+ OTG_GUSBCFG -+ OTG_GUSBCFG -+ This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. -+ 0xC -+ 0x20 -+ read-write -+ 0x00001400 -+ -+ -+ TOCAL -+ TOCAL -+ 0 -+ 3 -+ -+ -+ PHYSEL -+ PHYSEL -+ 6 -+ 1 -+ -+ -+ SRPCAP -+ SRPCAP -+ 8 -+ 1 -+ -+ -+ HNPCAP -+ HNPCAP -+ 9 -+ 1 -+ -+ -+ TRDT -+ TRDT -+ 10 -+ 4 -+ -+ -+ PHYLPC -+ PHYLPC -+ 15 -+ 1 -+ -+ -+ TSDPS -+ TSDPS -+ 22 -+ 1 -+ -+ -+ FHMOD -+ FHMOD -+ 29 -+ 1 -+ -+ -+ FDMOD -+ FDMOD -+ 30 -+ 1 -+ -+ -+ -+ -+ OTG_GRSTCTL -+ OTG_GRSTCTL -+ The application uses this register to reset various hardware features inside the core. -+ 0x10 -+ 0x20 -+ 0x80000000 -+ -+ -+ CSRST -+ CSRST -+ 0 -+ 1 -+ read-write -+ -+ -+ PSRST -+ PSRST -+ 1 -+ 1 -+ read-write -+ -+ -+ RXFFLSH -+ RXFFLSH -+ 4 -+ 1 -+ read-write -+ -+ -+ TXFFLSH -+ TXFFLSH -+ 5 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 6 -+ 5 -+ read-write -+ -+ -+ DMAREQ -+ DMAREQ -+ 30 -+ 1 -+ read-only -+ -+ -+ AHBIDL -+ AHBIDL -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ OTG_GINTSTS -+ OTG_GINTSTS -+ This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. -+ 0x14 -+ 0x20 -+ 0x14000020 -+ -+ -+ CMOD -+ CMOD -+ 0 -+ 1 -+ read-only -+ -+ -+ MMIS -+ MMIS -+ 1 -+ 1 -+ read-write -+ -+ -+ OTGINT -+ OTGINT -+ 2 -+ 1 -+ read-only -+ -+ -+ SOF -+ SOF -+ 3 -+ 1 -+ read-write -+ -+ -+ RXFLVL -+ RXFLVL -+ 4 -+ 1 -+ read-only -+ -+ -+ NPTXFE -+ NPTXFE -+ 5 -+ 1 -+ read-only -+ -+ -+ GINAKEFF -+ GINAKEFF -+ 6 -+ 1 -+ read-only -+ -+ -+ GONAKEFF -+ GONAKEFF -+ 7 -+ 1 -+ read-only -+ -+ -+ ESUSP -+ ESUSP -+ 10 -+ 1 -+ read-write -+ -+ -+ USBSUSP -+ USBSUSP -+ 11 -+ 1 -+ read-write -+ -+ -+ USBRST -+ USBRST -+ 12 -+ 1 -+ read-write -+ -+ -+ ENUMDNE -+ ENUMDNE -+ 13 -+ 1 -+ read-write -+ -+ -+ ISOODRP -+ ISOODRP -+ 14 -+ 1 -+ read-write -+ -+ -+ EOPF -+ EOPF -+ 15 -+ 1 -+ read-write -+ -+ -+ IEPINT -+ IEPINT -+ 18 -+ 1 -+ read-only -+ -+ -+ OEPINT -+ OEPINT -+ 19 -+ 1 -+ read-only -+ -+ -+ IISOIXFR -+ IISOIXFR -+ 20 -+ 1 -+ read-write -+ -+ -+ IPXFR -+ IPXFR -+ 21 -+ 1 -+ read-write -+ -+ -+ DATAFSUSP -+ DATAFSUSP -+ 22 -+ 1 -+ read-write -+ -+ -+ HPRTINT -+ HPRTINT -+ 24 -+ 1 -+ read-only -+ -+ -+ HCINT -+ HCINT -+ 25 -+ 1 -+ read-only -+ -+ -+ PTXFE -+ PTXFE -+ 26 -+ 1 -+ read-only -+ -+ -+ CIDSCHG -+ CIDSCHG -+ 28 -+ 1 -+ read-write -+ -+ -+ DISCINT -+ DISCINT -+ 29 -+ 1 -+ read-write -+ -+ -+ SRQINT -+ SRQINT -+ 30 -+ 1 -+ read-write -+ -+ -+ WKUPINT -+ WKUPINT -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_GINTMSK -+ OTG_GINTMSK -+ This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. -+ 0x18 -+ 0x20 -+ 0x00000000 -+ -+ -+ MMISM -+ MMISM -+ 1 -+ 1 -+ read-write -+ -+ -+ OTGINT -+ OTGINT -+ 2 -+ 1 -+ read-write -+ -+ -+ SOFM -+ SOFM -+ 3 -+ 1 -+ read-write -+ -+ -+ RXFLVLM -+ RXFLVLM -+ 4 -+ 1 -+ read-write -+ -+ -+ NPTXFEM -+ NPTXFEM -+ 5 -+ 1 -+ read-write -+ -+ -+ GINAKEFFM -+ GINAKEFFM -+ 6 -+ 1 -+ read-write -+ -+ -+ GONAKEFFM -+ GONAKEFFM -+ 7 -+ 1 -+ read-write -+ -+ -+ ESUSPM -+ ESUSPM -+ 10 -+ 1 -+ read-write -+ -+ -+ USBSUSPM -+ USBSUSPM -+ 11 -+ 1 -+ read-write -+ -+ -+ USBRST -+ USBRST -+ 12 -+ 1 -+ read-write -+ -+ -+ ENUMDNEM -+ ENUMDNEM -+ 13 -+ 1 -+ read-write -+ -+ -+ ISOODRPM -+ ISOODRPM -+ 14 -+ 1 -+ read-write -+ -+ -+ EOPFM -+ EOPFM -+ 15 -+ 1 -+ read-write -+ -+ -+ IEPINT -+ IEPINT -+ 18 -+ 1 -+ read-write -+ -+ -+ OEPINT -+ OEPINT -+ 19 -+ 1 -+ read-write -+ -+ -+ IISOIXFRM -+ IISOIXFRM -+ 20 -+ 1 -+ read-write -+ -+ -+ IPXFRM -+ IPXFRM -+ 21 -+ 1 -+ read-write -+ -+ -+ FSUSPM -+ FSUSPM -+ 22 -+ 1 -+ read-write -+ -+ -+ RSTDETM -+ RSTDETM -+ 23 -+ 1 -+ read-write -+ -+ -+ PRTIM -+ PRTIM -+ 24 -+ 1 -+ read-only -+ -+ -+ HCIM -+ HCIM -+ 25 -+ 1 -+ read-write -+ -+ -+ PTXFEM -+ PTXFEM -+ 26 -+ 1 -+ read-write -+ -+ -+ LPMINTM -+ LPMINTM -+ 27 -+ 1 -+ read-write -+ -+ -+ CIDSCHGM -+ CIDSCHGM -+ 28 -+ 1 -+ read-write -+ -+ -+ DISCINT -+ DISCINT -+ 29 -+ 1 -+ read-write -+ -+ -+ SRQIM -+ SRQIM -+ 30 -+ 1 -+ read-write -+ -+ -+ WUIM -+ WUIM -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_GRXSTSR -+ OTG_GRXSTSR -+ This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. -+ 0x1C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EPNUM -+ EPNUM -+ 0 -+ 4 -+ -+ -+ BCNT -+ BCNT -+ 4 -+ 11 -+ -+ -+ DPID -+ DPID -+ 15 -+ 2 -+ -+ -+ PKTSTS -+ PKTSTS -+ 17 -+ 4 -+ -+ -+ FRMNUM -+ FRMNUM -+ 21 -+ 4 -+ -+ -+ STSPHST -+ STSPHST -+ 27 -+ 1 -+ -+ -+ -+ -+ OTG_GRXSTSP -+ OTG_GRXSTSP -+ This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ EPNUM -+ EPNUM -+ 0 -+ 4 -+ -+ -+ BCNT -+ BCNT -+ 4 -+ 11 -+ -+ -+ DPID -+ DPID -+ 15 -+ 2 -+ -+ -+ PKTSTS -+ PKTSTS -+ 17 -+ 4 -+ -+ -+ FRMNUM -+ FRMNUM -+ 21 -+ 4 -+ -+ -+ STSPHST -+ STSPHST -+ 27 -+ 1 -+ -+ -+ -+ -+ OTG_GRXFSIZ -+ OTG_GRXFSIZ -+ The application can program the RAM size that must be allocated to the Rx FIFO. -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000400 -+ -+ -+ RXFD -+ RXFD -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_HNPTXFSIZ -+ OTG_HNPTXFSIZ -+ Host mode -+ 0x28 -+ 0x20 -+ read-write -+ 0x02000200 -+ -+ -+ NPTXFSA -+ NPTXFSA -+ 0 -+ 16 -+ -+ -+ NPTXFD -+ NPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_HNPTXSTS -+ OTG_HNPTXSTS -+ In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. -+ 0x2C -+ 0x20 -+ read-only -+ 0x00080400 -+ -+ -+ NPTXFSAV -+ NPTXFSAV -+ 0 -+ 16 -+ -+ -+ NPTQXSAV -+ NPTQXSAV -+ 16 -+ 8 -+ -+ -+ NPTXQTOP -+ NPTXQTOP -+ 24 -+ 7 -+ -+ -+ -+ -+ OTG_GCCFG -+ OTG_GCCFG -+ OTG general core configuration register -+ 0x38 -+ 0x20 -+ 0x00000000 -+ -+ -+ PDET -+ PDET -+ 1 -+ 1 -+ read-only -+ -+ -+ SDET -+ SDET -+ 2 -+ 1 -+ read-only -+ -+ -+ PS2DET -+ PS2DET -+ 3 -+ 1 -+ read-only -+ -+ -+ PWRDWN -+ PWRDWN -+ 16 -+ 1 -+ read-write -+ -+ -+ BCDEN -+ BCDEN -+ 17 -+ 1 -+ read-write -+ -+ -+ PDEN -+ PDEN -+ 19 -+ 1 -+ read-write -+ -+ -+ SDEN -+ SDEN -+ 20 -+ 1 -+ read-write -+ -+ -+ VBDEN -+ VBDEN -+ 21 -+ 1 -+ read-write -+ -+ -+ IDEN -+ IDEN -+ 22 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_CID -+ OTG_CID -+ This is a register containing the Product ID as reset value. -+ 0x3C -+ 0x20 -+ read-write -+ 0x00004000 -+ -+ -+ PRODUCT_ID -+ PRODUCT_ID -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_GLPMCFG -+ OTG_GLPMCFG -+ OTG core LPM configuration register -+ 0x54 -+ 0x20 -+ 0x00000000 -+ -+ -+ LPMEN -+ LPMEN -+ 0 -+ 1 -+ read-write -+ -+ -+ LPMACK -+ LPMACK -+ 1 -+ 1 -+ read-write -+ -+ -+ BESL -+ BESL -+ 2 -+ 4 -+ read-write -+ -+ -+ REMWAKE -+ REMWAKE -+ 6 -+ 1 -+ read-write -+ -+ -+ L1SSEN -+ L1SSEN -+ 7 -+ 1 -+ read-write -+ -+ -+ BESLTHRS -+ BESLTHRS -+ 8 -+ 4 -+ read-write -+ -+ -+ L1DSEN -+ L1DSEN -+ 12 -+ 1 -+ read-write -+ -+ -+ LPMRSP -+ LPMRSP -+ 13 -+ 2 -+ read-only -+ -+ -+ SLPSTS -+ SLPSTS -+ 15 -+ 1 -+ read-only -+ -+ -+ L1RSMOK -+ L1RSMOK -+ 16 -+ 1 -+ read-only -+ -+ -+ LPMCHIDX -+ LPMCHIDX -+ 17 -+ 4 -+ read-write -+ -+ -+ LPMRCNT -+ LPMRCNT -+ 21 -+ 3 -+ read-write -+ -+ -+ SNDLPM -+ SNDLPM -+ 24 -+ 1 -+ read-write -+ -+ -+ LPMRCNTSTS -+ LPMRCNTSTS -+ 25 -+ 3 -+ read-only -+ -+ -+ ENBESL -+ ENBESL -+ 28 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_HPTXFSIZ -+ OTG_HPTXFSIZ -+ OTG host periodic transmit FIFO size register -+ 0x100 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ PTXSA -+ PTXSA -+ 0 -+ 16 -+ -+ -+ PTXFSIZ -+ PTXFSIZ -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF1 -+ OTG_DIEPTXF1 -+ OTG device IN endpoint transmit FIFO 1 size register -+ 0x104 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF2 -+ OTG_DIEPTXF2 -+ OTG device IN endpoint transmit FIFO 2 size register -+ 0x108 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF3 -+ OTG_DIEPTXF3 -+ OTG device IN endpoint transmit FIFO 3 size register -+ 0x10C -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF4 -+ OTG_DIEPTXF4 -+ OTG device IN endpoint transmit FIFO 4 size register -+ 0x110 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF5 -+ OTG_DIEPTXF5 -+ OTG device IN endpoint transmit FIFO 5 size register -+ 0x114 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF6 -+ OTG_DIEPTXF6 -+ OTG device IN endpoint transmit FIFO 6 size register -+ 0x118 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF7 -+ OTG_DIEPTXF7 -+ OTG device IN endpoint transmit FIFO 7 size register -+ 0x11C -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPTXF8 -+ OTG_DIEPTXF8 -+ OTG device IN endpoint transmit FIFO 8 size register -+ 0x120 -+ 0x20 -+ read-write -+ 0x02000400 -+ -+ -+ INEPTXSA -+ INEPTXSA -+ 0 -+ 16 -+ -+ -+ INEPTXFD -+ INEPTXFD -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_HCFG -+ OTG_HCFG -+ This register configures the core after power-on. Do not make changes to this register after initializing the host. -+ 0x400 -+ 0x20 -+ 0x00000000 -+ -+ -+ FSLSPCS -+ FSLSPCS -+ 0 -+ 2 -+ read-write -+ -+ -+ FSLSS -+ FSLSS -+ 2 -+ 1 -+ read-only -+ -+ -+ DESCDMA -+ DESCDMA -+ 23 -+ 1 -+ read-write -+ -+ -+ FRLSTEN -+ FRLSTEN -+ 24 -+ 2 -+ read-write -+ -+ -+ PERSSCHEDENA -+ PERSSCHEDENA -+ 26 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_HFIR -+ OTG_HFIR -+ This register stores the frame interval information for the current speed to which the OTG controller has enumerated. -+ 0x404 -+ 0x20 -+ read-write -+ 0x0000EA60 -+ -+ -+ FRIVL -+ FRIVL -+ 0 -+ 16 -+ -+ -+ RLDCTRL -+ RLDCTRL -+ 16 -+ 1 -+ -+ -+ -+ -+ OTG_HFNUM -+ OTG_HFNUM -+ This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. -+ 0x408 -+ 0x20 -+ read-only -+ 0x00003FFF -+ -+ -+ FRNUM -+ FRNUM -+ 0 -+ 16 -+ -+ -+ FTREM -+ FTREM -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_HPTXSTS -+ OTG_HPTXSTS -+ This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. -+ 0x410 -+ 0x20 -+ read-only -+ 0x00080100 -+ -+ -+ PTXFSAVL -+ PTXFSAVL -+ 0 -+ 16 -+ -+ -+ PTXQSAV -+ PTXQSAV -+ 16 -+ 8 -+ -+ -+ PTXQTOP -+ PTXQTOP -+ 24 -+ 8 -+ -+ -+ -+ -+ OTG_HAINT -+ OTG_HAINT -+ When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. -+ 0x414 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HAINT -+ HAINT -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_HAINTMSK -+ OTG_HAINTMSK -+ The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. -+ 0x418 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HAINTM -+ HAINTM -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_HFLBADDR -+ OTG_HFLBADDR -+ This register holds the starting address of the frame list information (scatter/gather mode). -+ 0x41C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ HFLBADDR -+ HFLBADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HPRT -+ OTG_HPRT -+ This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. -+ 0x440 -+ 0x20 -+ 0x00000000 -+ -+ -+ PCSTS -+ PCSTS -+ 0 -+ 1 -+ read-only -+ -+ -+ PCDET -+ PCDET -+ 1 -+ 1 -+ read-write -+ -+ -+ PENA -+ PENA -+ 2 -+ 1 -+ read-write -+ -+ -+ PENCHNG -+ PENCHNG -+ 3 -+ 1 -+ read-write -+ -+ -+ POCA -+ POCA -+ 4 -+ 1 -+ read-only -+ -+ -+ POCCHNG -+ POCCHNG -+ 5 -+ 1 -+ read-write -+ -+ -+ PRES -+ PRES -+ 6 -+ 1 -+ read-write -+ -+ -+ PSUSP -+ PSUSP -+ 7 -+ 1 -+ read-write -+ -+ -+ PRST -+ PRST -+ 8 -+ 1 -+ read-write -+ -+ -+ PLSTS -+ PLSTS -+ 10 -+ 2 -+ read-only -+ -+ -+ PPWR -+ PPWR -+ 12 -+ 1 -+ read-write -+ -+ -+ PTCTL -+ PTCTL -+ 13 -+ 4 -+ read-write -+ -+ -+ PSPD -+ PSPD -+ 17 -+ 2 -+ read-only -+ -+ -+ -+ -+ OTG_HCCHAR0 -+ OTG_HCCHAR0 -+ OTG host channel 0 characteristics register -+ 0x500 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT0 -+ OTG_HCSPLT0 -+ OTG host channel 0 split control register -+ 0x504 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT0 -+ OTG_HCINT0 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x508 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK0 -+ OTG_HCINTMSK0 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x50C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ0 -+ OTG_HCTSIZ0 -+ OTG host channel 0 transfer size register -+ 0x510 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA0 -+ OTG_HCDMA0 -+ OTG host channel 0 DMA address register in buffer DMA [alternate] -+ 0x514 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB0 -+ OTG_HCDMAB0 -+ OTG host channel-n DMA address buffer register -+ 0x51C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR1 -+ OTG_HCCHAR1 -+ OTG host channel 1 characteristics register -+ 0x520 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT1 -+ OTG_HCSPLT1 -+ OTG host channel 1 split control register -+ 0x524 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT1 -+ OTG_HCINT1 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x528 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK1 -+ OTG_HCINTMSK1 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x52C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ1 -+ OTG_HCTSIZ1 -+ OTG host channel 1 transfer size register -+ 0x530 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA1 -+ OTG_HCDMA1 -+ OTG host channel 1 DMA address register in buffer DMA [alternate] -+ 0x534 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB1 -+ OTG_HCDMAB1 -+ OTG host channel-n DMA address buffer register -+ 0x53C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR2 -+ OTG_HCCHAR2 -+ OTG host channel 2 characteristics register -+ 0x540 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT2 -+ OTG_HCSPLT2 -+ OTG host channel 2 split control register -+ 0x544 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT2 -+ OTG_HCINT2 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x548 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK2 -+ OTG_HCINTMSK2 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x54C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ2 -+ OTG_HCTSIZ2 -+ OTG host channel 2 transfer size register -+ 0x550 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA2 -+ OTG_HCDMA2 -+ OTG host channel 2 DMA address register in buffer DMA [alternate] -+ 0x554 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB2 -+ OTG_HCDMAB2 -+ OTG host channel-n DMA address buffer register -+ 0x55C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR3 -+ OTG_HCCHAR3 -+ OTG host channel 3 characteristics register -+ 0x560 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT3 -+ OTG_HCSPLT3 -+ OTG host channel 3 split control register -+ 0x564 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT3 -+ OTG_HCINT3 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x568 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK3 -+ OTG_HCINTMSK3 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x56C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ3 -+ OTG_HCTSIZ3 -+ OTG host channel 3 transfer size register -+ 0x570 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA3 -+ OTG_HCDMA3 -+ OTG host channel 3 DMA address register in buffer DMA [alternate] -+ 0x574 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB3 -+ OTG_HCDMAB3 -+ OTG host channel-n DMA address buffer register -+ 0x57C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR4 -+ OTG_HCCHAR4 -+ OTG host channel 4 characteristics register -+ 0x580 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT4 -+ OTG_HCSPLT4 -+ OTG host channel 4 split control register -+ 0x584 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT4 -+ OTG_HCINT4 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x588 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK4 -+ OTG_HCINTMSK4 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x58C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ4 -+ OTG_HCTSIZ4 -+ OTG host channel 4 transfer size register -+ 0x590 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA4 -+ OTG_HCDMA4 -+ OTG host channel 4 DMA address register in buffer DMA [alternate] -+ 0x594 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB4 -+ OTG_HCDMAB4 -+ OTG host channel-n DMA address buffer register -+ 0x59C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR5 -+ OTG_HCCHAR5 -+ OTG host channel 5 characteristics register -+ 0x5A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT5 -+ OTG_HCSPLT5 -+ OTG host channel 5 split control register -+ 0x5A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT5 -+ OTG_HCINT5 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x5A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK5 -+ OTG_HCINTMSK5 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x5AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ5 -+ OTG_HCTSIZ5 -+ OTG host channel 5 transfer size register -+ 0x5B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA5 -+ OTG_HCDMA5 -+ OTG host channel 5 DMA address register in buffer DMA [alternate] -+ 0x5B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB5 -+ OTG_HCDMAB5 -+ OTG host channel-n DMA address buffer register -+ 0x5BC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR6 -+ OTG_HCCHAR6 -+ OTG host channel 6 characteristics register -+ 0x5C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT6 -+ OTG_HCSPLT6 -+ OTG host channel 6 split control register -+ 0x5C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT6 -+ OTG_HCINT6 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x5C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK6 -+ OTG_HCINTMSK6 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x5CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ6 -+ OTG_HCTSIZ6 -+ OTG host channel 6 transfer size register -+ 0x5D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA6 -+ OTG_HCDMA6 -+ OTG host channel 6 DMA address register in buffer DMA [alternate] -+ 0x5D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB6 -+ OTG_HCDMAB6 -+ OTG host channel-n DMA address buffer register -+ 0x5DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR7 -+ OTG_HCCHAR7 -+ OTG host channel 7 characteristics register -+ 0x5E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT7 -+ OTG_HCSPLT7 -+ OTG host channel 7 split control register -+ 0x5E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT7 -+ OTG_HCINT7 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x5E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK7 -+ OTG_HCINTMSK7 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x5EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ7 -+ OTG_HCTSIZ7 -+ OTG host channel 7 transfer size register -+ 0x5F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA7 -+ OTG_HCDMA7 -+ OTG host channel 7 DMA address register in buffer DMA [alternate] -+ 0x5F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB7 -+ OTG_HCDMAB7 -+ OTG host channel-n DMA address buffer register -+ 0x5FC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR8 -+ OTG_HCCHAR8 -+ OTG host channel 8 characteristics register -+ 0x600 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT8 -+ OTG_HCSPLT8 -+ OTG host channel 8 split control register -+ 0x604 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT8 -+ OTG_HCINT8 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x608 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK8 -+ OTG_HCINTMSK8 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x60C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ8 -+ OTG_HCTSIZ8 -+ OTG host channel 8 transfer size register -+ 0x610 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA8 -+ OTG_HCDMA8 -+ OTG host channel 8 DMA address register in buffer DMA [alternate] -+ 0x614 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB8 -+ OTG_HCDMAB8 -+ OTG host channel-n DMA address buffer register -+ 0x61C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR9 -+ OTG_HCCHAR9 -+ OTG host channel 9 characteristics register -+ 0x620 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT9 -+ OTG_HCSPLT9 -+ OTG host channel 9 split control register -+ 0x624 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT9 -+ OTG_HCINT9 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x628 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK9 -+ OTG_HCINTMSK9 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x62C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ9 -+ OTG_HCTSIZ9 -+ OTG host channel 9 transfer size register -+ 0x630 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA9 -+ OTG_HCDMA9 -+ OTG host channel 9 DMA address register in buffer DMA [alternate] -+ 0x634 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB9 -+ OTG_HCDMAB9 -+ OTG host channel-n DMA address buffer register -+ 0x63C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR10 -+ OTG_HCCHAR10 -+ OTG host channel 10 characteristics register -+ 0x640 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT10 -+ OTG_HCSPLT10 -+ OTG host channel 10 split control register -+ 0x644 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT10 -+ OTG_HCINT10 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x648 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK10 -+ OTG_HCINTMSK10 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x64C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ10 -+ OTG_HCTSIZ10 -+ OTG host channel 10 transfer size register -+ 0x650 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA10 -+ OTG_HCDMA10 -+ OTG host channel 10 DMA address register in buffer DMA [alternate] -+ 0x654 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB10 -+ OTG_HCDMAB10 -+ OTG host channel-n DMA address buffer register -+ 0x65C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR11 -+ OTG_HCCHAR11 -+ OTG host channel 11 characteristics register -+ 0x660 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT11 -+ OTG_HCSPLT11 -+ OTG host channel 11 split control register -+ 0x664 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT11 -+ OTG_HCINT11 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x668 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK11 -+ OTG_HCINTMSK11 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x66C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ11 -+ OTG_HCTSIZ11 -+ OTG host channel 11 transfer size register -+ 0x670 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA11 -+ OTG_HCDMA11 -+ OTG host channel 11 DMA address register in buffer DMA [alternate] -+ 0x674 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB11 -+ OTG_HCDMAB11 -+ OTG host channel-n DMA address buffer register -+ 0x67C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR12 -+ OTG_HCCHAR12 -+ OTG host channel 12 characteristics register -+ 0x680 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT12 -+ OTG_HCSPLT12 -+ OTG host channel 12 split control register -+ 0x684 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT12 -+ OTG_HCINT12 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x688 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK12 -+ OTG_HCINTMSK12 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x68C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ12 -+ OTG_HCTSIZ12 -+ OTG host channel 12 transfer size register -+ 0x690 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA12 -+ OTG_HCDMA12 -+ OTG host channel 12 DMA address register in buffer DMA [alternate] -+ 0x694 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB12 -+ OTG_HCDMAB12 -+ OTG host channel-n DMA address buffer register -+ 0x69C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR13 -+ OTG_HCCHAR13 -+ OTG host channel 13 characteristics register -+ 0x6A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT13 -+ OTG_HCSPLT13 -+ OTG host channel 13 split control register -+ 0x6A4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT13 -+ OTG_HCINT13 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x6A8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK13 -+ OTG_HCINTMSK13 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x6AC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ13 -+ OTG_HCTSIZ13 -+ OTG host channel 13 transfer size register -+ 0x6B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA13 -+ OTG_HCDMA13 -+ OTG host channel 13 DMA address register in buffer DMA [alternate] -+ 0x6B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB13 -+ OTG_HCDMAB13 -+ OTG host channel-n DMA address buffer register -+ 0x6BC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR14 -+ OTG_HCCHAR14 -+ OTG host channel 14 characteristics register -+ 0x6C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT14 -+ OTG_HCSPLT14 -+ OTG host channel 14 split control register -+ 0x6C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT14 -+ OTG_HCINT14 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x6C8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK14 -+ OTG_HCINTMSK14 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x6CC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ14 -+ OTG_HCTSIZ14 -+ OTG host channel 14 transfer size register -+ 0x6D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA14 -+ OTG_HCDMA14 -+ OTG host channel 14 DMA address register in buffer DMA [alternate] -+ 0x6D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB14 -+ OTG_HCDMAB14 -+ OTG host channel-n DMA address buffer register -+ 0x6DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCCHAR15 -+ OTG_HCCHAR15 -+ OTG host channel 15 characteristics register -+ 0x6E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ -+ -+ EPNUM -+ EPNUM -+ 11 -+ 4 -+ -+ -+ EPDIR -+ EPDIR -+ 15 -+ 1 -+ -+ -+ LSDEV -+ LSDEV -+ 17 -+ 1 -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ -+ -+ MCNT -+ MCNT -+ 20 -+ 2 -+ -+ -+ DAD -+ DAD -+ 22 -+ 7 -+ -+ -+ CHDIS -+ CHDIS -+ 30 -+ 1 -+ -+ -+ CHENA -+ CHENA -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCSPLT15 -+ OTG_HCSPLT15 -+ OTG host channel 15 split control register -+ 0x6E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PRTADDR -+ PRTADDR -+ 0 -+ 7 -+ -+ -+ HUBADDR -+ HUBADDR -+ 7 -+ 7 -+ -+ -+ XACTPOS -+ XACTPOS -+ 14 -+ 2 -+ -+ -+ COMPLSPLT -+ COMPLSPLT -+ 16 -+ 1 -+ -+ -+ SPLITEN -+ SPLITEN -+ 31 -+ 1 -+ -+ -+ -+ -+ OTG_HCINT15 -+ OTG_HCINT15 -+ This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. -+ 0x6E8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ CHH -+ CHH -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STALL -+ STALL -+ 3 -+ 1 -+ -+ -+ NAK -+ NAK -+ 4 -+ 1 -+ -+ -+ ACK -+ ACK -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERR -+ TXERR -+ 7 -+ 1 -+ -+ -+ BBERR -+ BBERR -+ 8 -+ 1 -+ -+ -+ FRMOR -+ FRMOR -+ 9 -+ 1 -+ -+ -+ DTERR -+ DTERR -+ 10 -+ 1 -+ -+ -+ BNA -+ BNA -+ 11 -+ 1 -+ -+ -+ XCSXACTERR -+ XCSXACTERR -+ 12 -+ 1 -+ -+ -+ DESCLSTROLL -+ DESCLSTROLL -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCINTMSK15 -+ OTG_HCINTMSK15 -+ This register reflects the mask for each channel status described in the previous section. -+ 0x6EC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ CHHM -+ CHHM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STALLM -+ STALLM -+ 3 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 4 -+ 1 -+ -+ -+ ACKM -+ ACKM -+ 5 -+ 1 -+ -+ -+ NYET -+ NYET -+ 6 -+ 1 -+ -+ -+ TXERRM -+ TXERRM -+ 7 -+ 1 -+ -+ -+ BBERRM -+ BBERRM -+ 8 -+ 1 -+ -+ -+ FRMORM -+ FRMORM -+ 9 -+ 1 -+ -+ -+ DTERRM -+ DTERRM -+ 10 -+ 1 -+ -+ -+ BNAMSK -+ BNAMSK -+ 11 -+ 1 -+ -+ -+ DESCLSTROLLMSK -+ DESCLSTROLLMSK -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HCTSIZ15 -+ OTG_HCTSIZ15 -+ OTG host channel 15 transfer size register -+ 0x6F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ DPID -+ DPID -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_HCDMA15 -+ OTG_HCDMA15 -+ OTG host channel 15 DMA address register in buffer DMA [alternate] -+ 0x6F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_HCDMAB15 -+ OTG_HCDMAB15 -+ OTG host channel-n DMA address buffer register -+ 0x6FC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ HCDMAB -+ HCDMAB -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DCFG -+ OTG_DCFG -+ This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. -+ 0x800 -+ 0x20 -+ read-write -+ 0x02200000 -+ -+ -+ DSPD -+ DSPD -+ 0 -+ 2 -+ -+ -+ NZLSOHSK -+ NZLSOHSK -+ 2 -+ 1 -+ -+ -+ DAD -+ DAD -+ 4 -+ 7 -+ -+ -+ PFIVL -+ PFIVL -+ 11 -+ 2 -+ -+ -+ XCVRDLY -+ XCVRDLY -+ 14 -+ 1 -+ -+ -+ ERRATIM -+ ERRATIM -+ 15 -+ 1 -+ -+ -+ PERSCHIVL -+ PERSCHIVL -+ 24 -+ 2 -+ -+ -+ -+ -+ OTG_DCTL -+ OTG_DCTL -+ OTG device control register -+ 0x804 -+ 0x20 -+ 0x00000002 -+ -+ -+ RWUSIG -+ RWUSIG -+ 0 -+ 1 -+ read-write -+ -+ -+ SDIS -+ SDIS -+ 1 -+ 1 -+ read-write -+ -+ -+ GINSTS -+ GINSTS -+ 2 -+ 1 -+ read-only -+ -+ -+ GONSTS -+ GONSTS -+ 3 -+ 1 -+ read-only -+ -+ -+ TCTL -+ TCTL -+ 4 -+ 3 -+ read-write -+ -+ -+ SGINAK -+ SGINAK -+ 7 -+ 1 -+ write-only -+ -+ -+ CGINAK -+ CGINAK -+ 8 -+ 1 -+ write-only -+ -+ -+ SGONAK -+ SGONAK -+ 9 -+ 1 -+ write-only -+ -+ -+ CGONAK -+ CGONAK -+ 10 -+ 1 -+ write-only -+ -+ -+ POPRGDNE -+ POPRGDNE -+ 11 -+ 1 -+ read-write -+ -+ -+ DSBESLRJCT -+ DSBESLRJCT -+ 18 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DSTS -+ OTG_DSTS -+ This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. -+ 0x808 -+ 0x20 -+ read-only -+ 0x00000010 -+ -+ -+ SUSPSTS -+ SUSPSTS -+ 0 -+ 1 -+ -+ -+ ENUMSPD -+ ENUMSPD -+ 1 -+ 2 -+ -+ -+ EERR -+ EERR -+ 3 -+ 1 -+ -+ -+ FNSOF -+ FNSOF -+ 8 -+ 14 -+ -+ -+ DEVLNSTS -+ DEVLNSTS -+ 22 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPMSK -+ OTG_DIEPMSK -+ This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. -+ 0x810 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ EPDM -+ EPDM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ TOM -+ TOM -+ 3 -+ 1 -+ -+ -+ ITTXFEMSK -+ ITTXFEMSK -+ 4 -+ 1 -+ -+ -+ INEPNMM -+ INEPNMM -+ 5 -+ 1 -+ -+ -+ INEPNEM -+ INEPNEM -+ 6 -+ 1 -+ -+ -+ TXFURM -+ TXFURM -+ 8 -+ 1 -+ -+ -+ BNAM -+ BNAM -+ 9 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPMSK -+ OTG_DOEPMSK -+ This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. -+ 0x814 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ EPDM -+ EPDM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STUPM -+ STUPM -+ 3 -+ 1 -+ -+ -+ OTEPDM -+ OTEPDM -+ 4 -+ 1 -+ -+ -+ STSPHSRXM -+ STSPHSRXM -+ 5 -+ 1 -+ -+ -+ B2BSTUPM -+ B2BSTUPM -+ 6 -+ 1 -+ -+ -+ OUTPKTERRM -+ OUTPKTERRM -+ 8 -+ 1 -+ -+ -+ BNAM -+ BNAM -+ 9 -+ 1 -+ -+ -+ BERRM -+ BERRM -+ 12 -+ 1 -+ -+ -+ NAKMSK -+ NAKMSK -+ 13 -+ 1 -+ -+ -+ NYETMSK -+ NYETMSK -+ 14 -+ 1 -+ -+ -+ -+ -+ OTG_DAINT -+ OTG_DAINT -+ When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). -+ 0x818 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IEPINT -+ IEPINT -+ 0 -+ 16 -+ -+ -+ OEPINT -+ OEPINT -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DAINTMSK -+ OTG_DAINTMSK -+ The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. -+ 0x81C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IEPM -+ IEPM -+ 0 -+ 16 -+ -+ -+ OEPM -+ OEPM -+ 16 -+ 16 -+ -+ -+ -+ -+ OTG_DVBUSDIS -+ OTG_DVBUSDIS -+ This register specifies the VBUS discharge time after VBUS pulsing during SRP. -+ 0x828 -+ 0x20 -+ read-write -+ 0x000017D7 -+ -+ -+ VBUSDT -+ VBUSDT -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DVBUSPULSE -+ OTG_DVBUSPULSE -+ This register specifies the VBUS pulsing time during SRP. -+ 0x82C -+ 0x20 -+ read-write -+ 0x000005B8 -+ -+ -+ DVBUSP -+ DVBUSP -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DTHRCTL -+ OTG_DTHRCTL -+ OTG device threshold control register -+ 0x830 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NONISOTHREN -+ NONISOTHREN -+ 0 -+ 1 -+ -+ -+ ISOTHREN -+ ISOTHREN -+ 1 -+ 1 -+ -+ -+ TXTHRLEN -+ TXTHRLEN -+ 2 -+ 9 -+ -+ -+ RXTHREN -+ RXTHREN -+ 16 -+ 1 -+ -+ -+ RXTHRLEN -+ RXTHRLEN -+ 17 -+ 9 -+ -+ -+ ARPEN -+ ARPEN -+ 27 -+ 1 -+ -+ -+ -+ -+ OTG_DIEPEMPMSK -+ OTG_DIEPEMPMSK -+ This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). -+ 0x834 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ INEPTXFEM -+ INEPTXFEM -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DEACHINT -+ OTG_DEACHINT -+ OTG device each endpoint interrupt register -+ 0x838 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ IEP1INT -+ IEP1INT -+ 1 -+ 1 -+ -+ -+ OEP1INT -+ OEP1INT -+ 17 -+ 1 -+ -+ -+ -+ -+ OTG_DEACHINTMSK -+ OTG_DEACHINTMSK -+ There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT. -+ 0x83C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IEP1INTM -+ IEP1INTM -+ 1 -+ 1 -+ -+ -+ OEP1INTM -+ OEP1INTM -+ 17 -+ 1 -+ -+ -+ -+ -+ OTG_HS_DIEPEACHMSK1 -+ OTG_HS_DIEPEACHMSK1 -+ This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. -+ 0x844 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ EPDM -+ EPDM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ TOM -+ TOM -+ 3 -+ 1 -+ -+ -+ ITTXFEMSK -+ ITTXFEMSK -+ 4 -+ 1 -+ -+ -+ INEPNEM -+ INEPNEM -+ 6 -+ 1 -+ -+ -+ TXFURM -+ TXFURM -+ 8 -+ 1 -+ -+ -+ BNAM -+ BNAM -+ 9 -+ 1 -+ -+ -+ NAKM -+ NAKM -+ 13 -+ 1 -+ -+ -+ -+ -+ OTG_HS_DOEPEACHMSK1 -+ OTG_HS_DOEPEACHMSK1 -+ This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. -+ 0x884 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRCM -+ XFRCM -+ 0 -+ 1 -+ -+ -+ EPDM -+ EPDM -+ 1 -+ 1 -+ -+ -+ AHBERRM -+ AHBERRM -+ 2 -+ 1 -+ -+ -+ STUPM -+ STUPM -+ 3 -+ 1 -+ -+ -+ OTEPDM -+ OTEPDM -+ 4 -+ 1 -+ -+ -+ B2BSTUPM -+ B2BSTUPM -+ 6 -+ 1 -+ -+ -+ OUTPKTERRM -+ OUTPKTERRM -+ 8 -+ 1 -+ -+ -+ BNAM -+ BNAM -+ 9 -+ 1 -+ -+ -+ BERRM -+ BERRM -+ 12 -+ 1 -+ -+ -+ NAKMSK -+ NAKMSK -+ 13 -+ 1 -+ -+ -+ NYETMSK -+ NYETMSK -+ 14 -+ 1 -+ -+ -+ -+ -+ OTG_DIEPCTL0 -+ OTG_DIEPCTL0 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x900 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT0 -+ OTG_DIEPINT0 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x908 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ0 -+ OTG_DIEPTSIZ0 -+ The application must modify this register before enabling endpoint 0. -+ 0x910 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 7 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA0 -+ OTG_DIEPDMA0 -+ OTG device IN endpoint 0 DMA address register -+ 0x914 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS0 -+ OTG_DTXFSTS0 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x918 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL1 -+ OTG_DIEPCTL1 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x920 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT1 -+ OTG_DIEPINT1 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x928 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ1 -+ OTG_DIEPTSIZ1 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x930 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA1 -+ OTG_DIEPDMA1 -+ OTG device IN endpoint 1 DMA address register -+ 0x934 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS1 -+ OTG_DTXFSTS1 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x938 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL2 -+ OTG_DIEPCTL2 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x940 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT2 -+ OTG_DIEPINT2 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x948 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ2 -+ OTG_DIEPTSIZ2 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x950 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA2 -+ OTG_DIEPDMA2 -+ OTG device IN endpoint 2 DMA address register -+ 0x954 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS2 -+ OTG_DTXFSTS2 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x958 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL3 -+ OTG_DIEPCTL3 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x960 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT3 -+ OTG_DIEPINT3 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x968 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ3 -+ OTG_DIEPTSIZ3 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x970 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA3 -+ OTG_DIEPDMA3 -+ OTG device IN endpoint 3 DMA address register -+ 0x974 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS3 -+ OTG_DTXFSTS3 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x978 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL4 -+ OTG_DIEPCTL4 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x980 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT4 -+ OTG_DIEPINT4 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x988 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ4 -+ OTG_DIEPTSIZ4 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x990 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA4 -+ OTG_DIEPDMA4 -+ OTG device IN endpoint 4 DMA address register -+ 0x994 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS4 -+ OTG_DTXFSTS4 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x998 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL5 -+ OTG_DIEPCTL5 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x9A0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT5 -+ OTG_DIEPINT5 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x9A8 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ5 -+ OTG_DIEPTSIZ5 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x9B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA5 -+ OTG_DIEPDMA5 -+ OTG device IN endpoint 5 DMA address register -+ 0x9B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS5 -+ OTG_DTXFSTS5 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x9B8 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL6 -+ OTG_DIEPCTL6 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x9C0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT6 -+ OTG_DIEPINT6 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x9C8 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ6 -+ OTG_DIEPTSIZ6 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x9D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA6 -+ OTG_DIEPDMA6 -+ OTG device IN endpoint 6 DMA address register -+ 0x9D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS6 -+ OTG_DTXFSTS6 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x9D8 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL7 -+ OTG_DIEPCTL7 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0x9E0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT7 -+ OTG_DIEPINT7 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0x9E8 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ7 -+ OTG_DIEPTSIZ7 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0x9F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA7 -+ OTG_DIEPDMA7 -+ OTG device IN endpoint 7 DMA address register -+ 0x9F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS7 -+ OTG_DTXFSTS7 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0x9F8 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DIEPCTL8 -+ OTG_DIEPCTL8 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xA00 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ TXFNUM -+ TXFNUM -+ 22 -+ 4 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SODDFRM -+ SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPINT8 -+ OTG_DIEPINT8 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xA08 -+ 0x20 -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ read-write -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ read-write -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ read-write -+ -+ -+ TOC -+ TOC -+ 3 -+ 1 -+ read-write -+ -+ -+ ITTXFE -+ ITTXFE -+ 4 -+ 1 -+ read-write -+ -+ -+ INEPNM -+ INEPNM -+ 5 -+ 1 -+ read-write -+ -+ -+ INEPNE -+ INEPNE -+ 6 -+ 1 -+ read-only -+ -+ -+ TXFE -+ TXFE -+ 7 -+ 1 -+ read-only -+ -+ -+ TXFIFOUDRN -+ TXFIFOUDRN -+ 8 -+ 1 -+ read-write -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ read-write -+ -+ -+ PKTDRPSTS -+ PKTDRPSTS -+ 11 -+ 1 -+ read-write -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DIEPTSIZ8 -+ OTG_DIEPTSIZ8 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xA10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ MCNT -+ MCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DIEPDMA8 -+ OTG_DIEPDMA8 -+ OTG device IN endpoint 8 DMA address register -+ 0xA14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DTXFSTS8 -+ OTG_DTXFSTS8 -+ This read-only register contains the free space information for the device IN endpoint Tx FIFO. -+ 0xA18 -+ 0x20 -+ read-only -+ 0x00000200 -+ -+ -+ INEPTFSAV -+ INEPTFSAV -+ 0 -+ 16 -+ -+ -+ -+ -+ OTG_DOEPCTL0 -+ OTG_DOEPCTL0 -+ This section describes the OTG_DOEPCTL0 register. -+ 0xB00 -+ 0x20 -+ 0x00008000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 2 -+ read-only -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-only -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-only -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ write-only -+ -+ -+ -+ -+ OTG_DOEPINT0 -+ OTG_DOEPINT0 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xB08 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ0 -+ OTG_DOEPTSIZ0 -+ The application must modify this register before enabling endpoint 0. -+ 0xB10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 7 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 1 -+ -+ -+ STUPCNT -+ STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA0 -+ OTG_DOEPDMA0 -+ OTG device OUT endpoint 0 DMA address register -+ 0xB14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL1 -+ OTG_DOEPCTL1 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xB20 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT1 -+ OTG_DOEPINT1 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xB28 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ1 -+ OTG_DOEPTSIZ1 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xB30 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA1 -+ OTG_DOEPDMA1 -+ OTG device OUT endpoint 1 DMA address register -+ 0xB34 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL2 -+ OTG_DOEPCTL2 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xB40 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT2 -+ OTG_DOEPINT2 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xB48 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ2 -+ OTG_DOEPTSIZ2 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xB50 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA2 -+ OTG_DOEPDMA2 -+ OTG device OUT endpoint 2 DMA address register -+ 0xB54 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL3 -+ OTG_DOEPCTL3 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xB60 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT3 -+ OTG_DOEPINT3 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xB68 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ3 -+ OTG_DOEPTSIZ3 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xB70 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA3 -+ OTG_DOEPDMA3 -+ OTG device OUT endpoint 3 DMA address register -+ 0xB74 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL4 -+ OTG_DOEPCTL4 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xB80 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT4 -+ OTG_DOEPINT4 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xB88 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ4 -+ OTG_DOEPTSIZ4 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xB90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA4 -+ OTG_DOEPDMA4 -+ OTG device OUT endpoint 4 DMA address register -+ 0xB94 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL5 -+ OTG_DOEPCTL5 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xBA0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT5 -+ OTG_DOEPINT5 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xBA8 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ5 -+ OTG_DOEPTSIZ5 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xBB0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA5 -+ OTG_DOEPDMA5 -+ OTG device OUT endpoint 5 DMA address register -+ 0xBB4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL6 -+ OTG_DOEPCTL6 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xBC0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT6 -+ OTG_DOEPINT6 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xBC8 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ6 -+ OTG_DOEPTSIZ6 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xBD0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA6 -+ OTG_DOEPDMA6 -+ OTG device OUT endpoint 6 DMA address register -+ 0xBD4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL7 -+ OTG_DOEPCTL7 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xBE0 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT7 -+ OTG_DOEPINT7 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xBE8 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ7 -+ OTG_DOEPTSIZ7 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xBF0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA7 -+ OTG_DOEPDMA7 -+ OTG device OUT endpoint 7 DMA address register -+ 0xBF4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_DOEPCTL8 -+ OTG_DOEPCTL8 -+ The application uses this register to control the behavior of each logical endpoint other than endpoint 0. -+ 0xC00 -+ 0x20 -+ 0x00000000 -+ -+ -+ MPSIZ -+ MPSIZ -+ 0 -+ 11 -+ read-write -+ -+ -+ USBAEP -+ USBAEP -+ 15 -+ 1 -+ read-write -+ -+ -+ EONUM_DPIP -+ EONUM_DPIP -+ 16 -+ 1 -+ read-only -+ -+ -+ NAKSTS -+ NAKSTS -+ 17 -+ 1 -+ read-only -+ -+ -+ EPTYP -+ EPTYP -+ 18 -+ 2 -+ read-write -+ -+ -+ SNPM -+ SNPM -+ 20 -+ 1 -+ read-write -+ -+ -+ STALL -+ STALL -+ 21 -+ 1 -+ read-write -+ -+ -+ CNAK -+ CNAK -+ 26 -+ 1 -+ write-only -+ -+ -+ SNAK -+ SNAK -+ 27 -+ 1 -+ write-only -+ -+ -+ SD0PID_SEVNFRM -+ SD0PID_SEVNFRM -+ 28 -+ 1 -+ write-only -+ -+ -+ SD1PID_SODDFRM -+ SD1PID_SODDFRM -+ 29 -+ 1 -+ write-only -+ -+ -+ EPDIS -+ EPDIS -+ 30 -+ 1 -+ read-write -+ -+ -+ EPENA -+ EPENA -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ OTG_DOEPINT8 -+ OTG_DOEPINT8 -+ This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. -+ 0xC08 -+ 0x20 -+ read-write -+ 0x00000080 -+ -+ -+ XFRC -+ XFRC -+ 0 -+ 1 -+ -+ -+ EPDISD -+ EPDISD -+ 1 -+ 1 -+ -+ -+ AHBERR -+ AHBERR -+ 2 -+ 1 -+ -+ -+ STUP -+ STUP -+ 3 -+ 1 -+ -+ -+ OTEPDIS -+ OTEPDIS -+ 4 -+ 1 -+ -+ -+ STSPHSRX -+ STSPHSRX -+ 5 -+ 1 -+ -+ -+ B2BSTUP -+ B2BSTUP -+ 6 -+ 1 -+ -+ -+ OUTPKTERR -+ OUTPKTERR -+ 8 -+ 1 -+ -+ -+ BNA -+ BNA -+ 9 -+ 1 -+ -+ -+ BERR -+ BERR -+ 12 -+ 1 -+ -+ -+ NAK -+ NAK -+ 13 -+ 1 -+ -+ -+ NYET -+ NYET -+ 14 -+ 1 -+ -+ -+ STPKTRX -+ STPKTRX -+ 15 -+ 1 -+ -+ -+ -+ -+ OTG_DOEPTSIZ8 -+ OTG_DOEPTSIZ8 -+ The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. -+ 0xC10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ XFRSIZ -+ XFRSIZ -+ 0 -+ 19 -+ -+ -+ PKTCNT -+ PKTCNT -+ 19 -+ 10 -+ -+ -+ RXDPID_STUPCNT -+ RXDPID_STUPCNT -+ 29 -+ 2 -+ -+ -+ -+ -+ OTG_DOEPDMA8 -+ OTG_DOEPDMA8 -+ OTG device OUT endpoint 8 DMA address register -+ 0xC14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DMAADDR -+ DMAADDR -+ 0 -+ 32 -+ -+ -+ -+ -+ OTG_PCGCCTL -+ OTG_PCGCCTL -+ This register is available in host and device modes. -+ 0xE00 -+ 0x20 -+ 0x200B8000 -+ -+ -+ STPPCLK -+ STPPCLK -+ 0 -+ 1 -+ read-write -+ -+ -+ GATEHCLK -+ GATEHCLK -+ 1 -+ 1 -+ read-write -+ -+ -+ PHYSUSP -+ PHYSUSP -+ 4 -+ 1 -+ read-only -+ -+ -+ ENL1GTG -+ ENL1GTG -+ 5 -+ 1 -+ read-write -+ -+ -+ PHYSLEEP -+ PHYSLEEP -+ 6 -+ 1 -+ read-only -+ -+ -+ SUSP -+ SUSP -+ 7 -+ 1 -+ read-only -+ -+ -+ -+ -+ -+ -+ MDIOS -+ MDIOS -+ MDIOS -+ 0x4001C000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ MDIOS_CR -+ MDIOS_CR -+ MDIOS configuration register -+ 0x00 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EN -+ EN -+ 0 -+ 1 -+ read-write -+ -+ -+ WRIE -+ WRIE -+ 1 -+ 1 -+ read-write -+ -+ -+ RDIE -+ RDIE -+ 2 -+ 1 -+ read-write -+ -+ -+ EIE -+ EIE -+ 3 -+ 1 -+ read-write -+ -+ -+ DPC -+ DPC -+ 7 -+ 1 -+ read-write -+ -+ -+ PORT_ADDRESS -+ PORT_ADDRESS -+ 8 -+ 5 -+ read-write -+ -+ -+ -+ -+ MDIOS_WRFR -+ MDIOS_WRFR -+ MDIOS write flag register -+ 0x04 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ WRF -+ WRF -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ MDIOS_CWRFR -+ MDIOS_CWRFR -+ MDIOS clear write flag -+ register -+ 0x08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CWRF -+ CWRF -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ MDIOS_RDFR -+ MDIOS_RDFR -+ MDIOS read flag register -+ 0x0C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RDF -+ RDF -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ MDIOS_CRDFR -+ MDIOS_CRDFR -+ MDIOS clear read flag register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CRDF -+ CRDF -+ 0 -+ 32 -+ read-write -+ -+ -+ -+ -+ MDIOS_SR -+ MDIOS_SR -+ MDIOS status register -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PERF -+ PERF -+ 0 -+ 1 -+ read-only -+ -+ -+ SERF -+ SERF -+ 1 -+ 1 -+ read-only -+ -+ -+ TERF -+ TERF -+ 2 -+ 1 -+ read-only -+ -+ -+ -+ -+ MDIOS_CLRFR -+ MDIOS_CLRFR -+ MDIOS clear flag register -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CPERF -+ CPERF -+ 0 -+ 1 -+ read-write -+ -+ -+ CSERF -+ CSERF -+ 1 -+ 1 -+ read-write -+ -+ -+ CTERF -+ CTERF -+ 2 -+ 1 -+ read-write -+ -+ -+ -+ -+ MDIOS_DINR0 -+ MDIOS_DINR0 -+ MDIOS input data register -+ 0x100 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR1 -+ MDIOS_DINR1 -+ MDIOS input data register -+ 0x104 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR2 -+ MDIOS_DINR2 -+ MDIOS input data register -+ 0x108 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR3 -+ MDIOS_DINR3 -+ MDIOS input data register -+ 0x10C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR4 -+ MDIOS_DINR4 -+ MDIOS input data register -+ 0x110 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR5 -+ MDIOS_DINR5 -+ MDIOS input data register -+ 0x114 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR6 -+ MDIOS_DINR6 -+ MDIOS input data register -+ 0x118 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR7 -+ MDIOS_DINR7 -+ MDIOS input data register -+ 0x11C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR8 -+ MDIOS_DINR8 -+ MDIOS input data register -+ 0x120 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR9 -+ MDIOS_DINR9 -+ MDIOS input data register -+ 0x124 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR10 -+ MDIOS_DINR10 -+ MDIOS input data register -+ 0x128 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR11 -+ MDIOS_DINR11 -+ MDIOS input data register -+ 0x12C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR12 -+ MDIOS_DINR12 -+ MDIOS input data register -+ 0x130 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR13 -+ MDIOS_DINR13 -+ MDIOS input data register -+ 0x134 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR14 -+ MDIOS_DINR14 -+ MDIOS input data register -+ 0x138 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR15 -+ MDIOS_DINR15 -+ MDIOS input data register -+ 0x13C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR16 -+ MDIOS_DINR16 -+ MDIOS input data register -+ 0x140 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR17 -+ MDIOS_DINR17 -+ MDIOS input data register -+ 0x144 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR18 -+ MDIOS_DINR18 -+ MDIOS input data register -+ 0x148 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR19 -+ MDIOS_DINR19 -+ MDIOS input data register -+ 0x14C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR20 -+ MDIOS_DINR20 -+ MDIOS input data register -+ 0x150 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR21 -+ MDIOS_DINR21 -+ MDIOS input data register -+ 0x154 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR22 -+ MDIOS_DINR22 -+ MDIOS input data register -+ 0x158 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR23 -+ MDIOS_DINR23 -+ MDIOS input data register -+ 0x15C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR24 -+ MDIOS_DINR24 -+ MDIOS input data register -+ 0x160 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR25 -+ MDIOS_DINR25 -+ MDIOS input data register -+ 0x164 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR26 -+ MDIOS_DINR26 -+ MDIOS input data register -+ 0x168 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR27 -+ MDIOS_DINR27 -+ MDIOS input data register -+ 0x16C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR28 -+ MDIOS_DINR28 -+ MDIOS input data register -+ 0x170 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR29 -+ MDIOS_DINR29 -+ MDIOS input data register -+ 0x174 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR30 -+ MDIOS_DINR30 -+ MDIOS input data register -+ 0x178 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DINR31 -+ MDIOS_DINR31 -+ MDIOS input data register -+ 0x17C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DIN -+ DIN -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR0 -+ MDIOS_DOUTR0 -+ MDIOS input data register -+ 0x180 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR1 -+ MDIOS_DOUTR1 -+ MDIOS input data register -+ 0x184 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR2 -+ MDIOS_DOUTR2 -+ MDIOS output data register -+ 0x188 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR3 -+ MDIOS_DOUTR3 -+ MDIOS output data register -+ 0x18C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR4 -+ MDIOS_DOUTR4 -+ MDIOS output data register -+ 0x190 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR5 -+ MDIOS_DOUTR5 -+ MDIOS output data register -+ 0x194 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR6 -+ MDIOS_DOUTR6 -+ MDIOS output data register -+ 0x198 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR7 -+ MDIOS_DOUTR7 -+ MDIOS output data register -+ 0x19C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR8 -+ MDIOS_DOUTR8 -+ MDIOS output data register -+ 0x1A0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR9 -+ MDIOS_DOUTR9 -+ MDIOS output data register -+ 0x1A4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR10 -+ MDIOS_DOUTR10 -+ MDIOS output data register -+ 0x1A8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR11 -+ MDIOS_DOUTR11 -+ MDIOS output data register -+ 0x1AC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR12 -+ MDIOS_DOUTR12 -+ MDIOS output data register -+ 0x1B0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR13 -+ MDIOS_DOUTR13 -+ MDIOS output data register -+ 0x1B4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR14 -+ MDIOS_DOUTR14 -+ MDIOS output data register -+ 0x1B8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR15 -+ MDIOS_DOUTR15 -+ MDIOS output data register -+ 0x1BC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR16 -+ MDIOS_DOUTR16 -+ MDIOS output data register -+ 0x1C0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR17 -+ MDIOS_DOUTR17 -+ MDIOS output data register -+ 0x1C4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR18 -+ MDIOS_DOUTR18 -+ MDIOS output data register -+ 0x1C8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR19 -+ MDIOS_DOUTR19 -+ MDIOS output data register -+ 0x1CC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR20 -+ MDIOS_DOUTR20 -+ MDIOS output data register -+ 0x1D0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR21 -+ MDIOS_DOUTR21 -+ MDIOS output data register -+ 0x1D4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR22 -+ MDIOS_DOUTR22 -+ MDIOS output data register -+ 0x1D8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR23 -+ MDIOS_DOUTR23 -+ MDIOS output data register -+ 0x1DC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR24 -+ MDIOS_DOUTR24 -+ MDIOS output data register -+ 0x1E0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR25 -+ MDIOS_DOUTR25 -+ MDIOS output data register -+ 0x1E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR26 -+ MDIOS_DOUTR26 -+ MDIOS output data register -+ 0x1E8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR27 -+ MDIOS_DOUTR27 -+ MDIOS output data register -+ 0x1EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR28 -+ MDIOS_DOUTR28 -+ MDIOS output data register -+ 0x1F0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR29 -+ MDIOS_DOUTR29 -+ MDIOS output data register -+ 0x1F4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR30 -+ MDIOS_DOUTR30 -+ MDIOS output data register -+ 0x1F8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_DOUTR31 -+ MDIOS_DOUTR31 -+ MDIOS output data register -+ 0x1FC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DOUT -+ DOUT -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ MDIOS_HWCFGR -+ MDIOS_HWCFGR -+ MDIOS HW configuration -+ register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000020 -+ -+ -+ NBREG -+ NBREG -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ MDIOS_VERR -+ MDIOS_VERR -+ MDIOS version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ read-only -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ MDIOS_IPIDR -+ MDIOS_IPIDR -+ MDIOS identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00180001 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ MDIOS_SIDR -+ MDIOS_SIDR -+ MDIOS size identification -+ register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ -+ -+ HDMI_CEC -+ HDMI_CEC -+ HDMI_CEC -+ 0x40016000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ CEC_CR -+ CEC_CR -+ CEC control register -+ 0x00 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CECEN -+ CECEN -+ 0 -+ 1 -+ read-write -+ -+ -+ TXSOM -+ TXSOM -+ 1 -+ 1 -+ read-write -+ -+ -+ TXEOM -+ TXEOM -+ 2 -+ 1 -+ read-write -+ -+ -+ -+ -+ CEC_CFGR -+ CEC_CFGR -+ This register is used to configure the HDMI-CEC controller. -+It is mandatory to write CEC_CFGR only when CECEN=0. -+ 0x04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SFT -+ SFT -+ 0 -+ 3 -+ read-write -+ -+ -+ RXTOL -+ RXTOL -+ 3 -+ 1 -+ read-write -+ -+ -+ BRESTP -+ BRESTP -+ 4 -+ 1 -+ read-write -+ -+ -+ BREGEN -+ BREGEN -+ 5 -+ 1 -+ read-write -+ -+ -+ LBPEGEN -+ LBPEGEN -+ 6 -+ 1 -+ read-write -+ -+ -+ BRDNOGEN -+ BRDNOGEN -+ 7 -+ 1 -+ read-write -+ -+ -+ SFTOP -+ SFTOP -+ 8 -+ 1 -+ read-write -+ -+ -+ OAR -+ OAR -+ 16 -+ 15 -+ read-write -+ -+ -+ LSTN -+ LSTN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ CEC_TXDR -+ CEC_TXDR -+ CEC Tx data register -+ 0x08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TXD -+ TXD -+ 0 -+ 8 -+ write-only -+ -+ -+ -+ -+ CEC_RXDR -+ CEC_RXDR -+ CEC Rx data register -+ 0x0C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXD -+ RXD -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ CEC_ISR -+ CEC_ISR -+ CEC Interrupt and Status Register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXBR -+ RXBR -+ 0 -+ 1 -+ read-write -+ -+ -+ RXEND -+ RXEND -+ 1 -+ 1 -+ read-write -+ -+ -+ RXOVR -+ RXOVR -+ 2 -+ 1 -+ read-write -+ -+ -+ BRE -+ BRE -+ 3 -+ 1 -+ read-write -+ -+ -+ SBPE -+ SBPE -+ 4 -+ 1 -+ read-write -+ -+ -+ LBPE -+ LBPE -+ 5 -+ 1 -+ read-write -+ -+ -+ RXACKE -+ RXACKE -+ 6 -+ 1 -+ read-write -+ -+ -+ ARBLST -+ ARBLST -+ 7 -+ 1 -+ read-write -+ -+ -+ TXBR -+ TXBR -+ 8 -+ 1 -+ read-write -+ -+ -+ TXEND -+ TXEND -+ 9 -+ 1 -+ read-write -+ -+ -+ TXUDR -+ TXUDR -+ 10 -+ 1 -+ read-write -+ -+ -+ TXERR -+ TXERR -+ 11 -+ 1 -+ read-write -+ -+ -+ TXACKE -+ TXACKE -+ 12 -+ 1 -+ read-write -+ -+ -+ -+ -+ CEC_IER -+ CEC_IER -+ CEC interrupt enable register -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXBRIE -+ RXBRIE -+ 0 -+ 1 -+ read-write -+ -+ -+ RXENDIE -+ RXENDIE -+ 1 -+ 1 -+ read-write -+ -+ -+ RXOVRIE -+ RXOVRIE -+ 2 -+ 1 -+ read-write -+ -+ -+ BREIE -+ BREIE -+ 3 -+ 1 -+ read-write -+ -+ -+ SBPEIE -+ SBPEIE -+ 4 -+ 1 -+ read-write -+ -+ -+ LBPEIE -+ LBPEIE -+ 5 -+ 1 -+ read-write -+ -+ -+ RXACKIE -+ RXACKIE -+ 6 -+ 1 -+ read-write -+ -+ -+ ARBLSTIE -+ ARBLSTIE -+ 7 -+ 1 -+ read-write -+ -+ -+ TXBRIE -+ TXBRIE -+ 8 -+ 1 -+ read-write -+ -+ -+ TXENDIE -+ TXENDIE -+ 9 -+ 1 -+ read-write -+ -+ -+ TXUDRIE -+ TXUDRIE -+ 10 -+ 1 -+ read-write -+ -+ -+ TXERRIE -+ TXERRIE -+ 11 -+ 1 -+ read-write -+ -+ -+ TXACKIE -+ TXACKIE -+ 12 -+ 1 -+ read-write -+ -+ -+ -+ -+ -+ -+ SPDIFRX -+ SPDIFRX -+ SPDIFRX -+ 0x4000D000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ SPDIFRX_CR -+ SPDIFRX_CR -+ Control register -+ 0x00 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SPDIFRXEN -+ SPDIFRXEN -+ 0 -+ 2 -+ read-write -+ -+ -+ RXDMAEN -+ RXDMAEN -+ 2 -+ 1 -+ read-write -+ -+ -+ RXSTEO -+ RXSTEO -+ 3 -+ 1 -+ read-write -+ -+ -+ DRFMT -+ DRFMT -+ 4 -+ 2 -+ read-write -+ -+ -+ PMSK -+ PMSK -+ 6 -+ 1 -+ read-write -+ -+ -+ VMSK -+ VMSK -+ 7 -+ 1 -+ read-write -+ -+ -+ CUMSK -+ CUMSK -+ 8 -+ 1 -+ read-write -+ -+ -+ PTMSK -+ PTMSK -+ 9 -+ 1 -+ read-write -+ -+ -+ CBDMAEN -+ CBDMAEN -+ 10 -+ 1 -+ read-write -+ -+ -+ CHSEL -+ CHSEL -+ 11 -+ 1 -+ read-write -+ -+ -+ NBTR -+ NBTR -+ 12 -+ 2 -+ read-write -+ -+ -+ WFA -+ WFA -+ 14 -+ 1 -+ read-write -+ -+ -+ INSEL -+ INSEL -+ 16 -+ 3 -+ read-write -+ -+ -+ CKSEN -+ CKSEN -+ 20 -+ 1 -+ read-write -+ -+ -+ CKSBKPEN -+ CKSBKPEN -+ 21 -+ 1 -+ read-write -+ -+ -+ -+ -+ SPDIFRX_IMR -+ SPDIFRX_IMR -+ Interrupt mask register -+ 0x04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RXNEIE -+ RXNEIE -+ 0 -+ 1 -+ read-write -+ -+ -+ CSRNEIE -+ CSRNEIE -+ 1 -+ 1 -+ read-write -+ -+ -+ PERRIE -+ PERRIE -+ 2 -+ 1 -+ read-write -+ -+ -+ OVRIE -+ OVRIE -+ 3 -+ 1 -+ read-write -+ -+ -+ SBLKIE -+ SBLKIE -+ 4 -+ 1 -+ read-write -+ -+ -+ SYNCDIE -+ SYNCDIE -+ 5 -+ 1 -+ read-write -+ -+ -+ IFEIE -+ IFEIE -+ 6 -+ 1 -+ read-write -+ -+ -+ -+ -+ SPDIFRX_SR -+ SPDIFRX_SR -+ Status register -+ 0x08 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ RXNE -+ RXNE -+ 0 -+ 1 -+ read-only -+ -+ -+ CSRNE -+ CSRNE -+ 1 -+ 1 -+ read-only -+ -+ -+ PERR -+ PERR -+ 2 -+ 1 -+ read-only -+ -+ -+ OVR -+ OVR -+ 3 -+ 1 -+ read-only -+ -+ -+ SBD -+ SBD -+ 4 -+ 1 -+ read-only -+ -+ -+ SYNCD -+ SYNCD -+ 5 -+ 1 -+ read-only -+ -+ -+ FERR -+ FERR -+ 6 -+ 1 -+ read-only -+ -+ -+ SERR -+ SERR -+ 7 -+ 1 -+ read-only -+ -+ -+ TERR -+ TERR -+ 8 -+ 1 -+ read-only -+ -+ -+ WIDTH5 -+ WIDTH5 -+ 16 -+ 15 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_IFCR -+ SPDIFRX_IFCR -+ Interrupt flag clear register -+ 0x0C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ PERRCF -+ PERRCF -+ 2 -+ 1 -+ write-only -+ -+ -+ OVRCF -+ OVRCF -+ 3 -+ 1 -+ write-only -+ -+ -+ SBDCF -+ SBDCF -+ 4 -+ 1 -+ write-only -+ -+ -+ SYNCDCF -+ SYNCDCF -+ 5 -+ 1 -+ write-only -+ -+ -+ -+ -+ SPDIFRX_FMT0_DR -+ SPDIFRX_FMT0_DR -+ This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00: -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ DR -+ DR -+ 0 -+ 24 -+ read-only -+ -+ -+ PE -+ PE -+ 24 -+ 1 -+ read-only -+ -+ -+ V -+ V -+ 25 -+ 1 -+ read-only -+ -+ -+ U -+ U -+ 26 -+ 1 -+ read-only -+ -+ -+ C -+ C -+ 27 -+ 1 -+ read-only -+ -+ -+ PT -+ PT -+ 28 -+ 2 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_CSR -+ SPDIFRX_CSR -+ Channel status register -+ 0x14 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ USR -+ USR -+ 0 -+ 16 -+ read-only -+ -+ -+ CS -+ CS -+ 16 -+ 8 -+ read-only -+ -+ -+ SOB -+ SOB -+ 24 -+ 1 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_DIR -+ SPDIFRX_DIR -+ Debug information register -+ 0x18 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ THI -+ THI -+ 0 -+ 13 -+ read-only -+ -+ -+ TLO -+ TLO -+ 16 -+ 13 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_VERR -+ SPDIFRX_VERR -+ SPDIFRX version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000012 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ read-only -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_IPIDR -+ SPDIFRX_IPIDR -+ SPDIFRX identification register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00130041 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ SPDIFRX_SIDR -+ SPDIFRX_SIDR -+ SPDIFRX size identification register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ -+ -+ WWDG1 -+ WWDG1 -+ WWDG1 -+ 0x4000A000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ WWDG1_IT -+ Window Watchdog interrupt -+ 0 -+ -+ -+ -+ WWDG_CR -+ WWDG_CR -+ Control register -+ 0x00 -+ 0x20 -+ read-write -+ 0x0000007F -+ -+ -+ T -+ T -+ 0 -+ 7 -+ read-write -+ -+ -+ WDGA -+ WDGA -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ WWDG_CFR -+ WWDG_CFR -+ Configuration register -+ 0x04 -+ 0x20 -+ read-write -+ 0x0000007F -+ -+ -+ W -+ W -+ 0 -+ 7 -+ read-write -+ -+ -+ EWI -+ EWI -+ 9 -+ 1 -+ read-write -+ -+ -+ WDGTB -+ WDGTB -+ 11 -+ 3 -+ read-write -+ -+ -+ -+ -+ WWDG_SR -+ WWDG_SR -+ Status register -+ 0x08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ EWIF -+ EWIF -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ WWDG_HWCFGR -+ WWDG_HWCFGR -+ WWDG hardware configuration register -+ 0x3F0 -+ 0x20 -+ read-only -+ 0x00000FFF -+ -+ -+ PREDIV -+ PREDIV -+ 0 -+ 16 -+ read-only -+ -+ -+ -+ -+ WWDG_VERR -+ WWDG_VERR -+ WWDG version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000021 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ read-only -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ WWDG_IPIDR -+ WWDG_IPIDR -+ WWDG ID register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00120051 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ WWDG_SIDR -+ WWDG_SIDR -+ WWDG size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ -+ -+ AXIMC_Mx -+ AXIMC_Mx -+ AXIMC_Mx -+ 0x57042024 -+ -+ 0x0 -+ 0x100000 -+ registers -+ -+ -+ -+ AXIMC_M0_FN_MOD2 -+ AXIMC_M0_FN_MOD2 -+ AXIMC master 0 packing functionality register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M0_READ_QOS -+ AXIMC_M0_READ_QOS -+ AXIMC master 0 read priority register -+ 0xDC -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M0_WRITE_QOS -+ AXIMC_M0_WRITE_QOS -+ AXIMC master 0 write priority register -+ 0xE4 -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M0_FN_MOD -+ AXIMC_M0_FN_MOD -+ AXIMC master 0 issuing capability override functionality register -+ 0xE0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M1_FN_MOD2 -+ AXIMC_M1_FN_MOD2 -+ AXIMC master 1 packing functionality register -+ 0x1000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M1_READ_QOS -+ AXIMC_M1_READ_QOS -+ AXIMC master 1 read priority register -+ 0x10DC -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M1_WRITE_QOS -+ AXIMC_M1_WRITE_QOS -+ AXIMC master 1 write priority register -+ 0x10E0 -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M1_FN_MOD -+ AXIMC_M1_FN_MOD -+ AXIMC master 1 issuing capability override functionality register -+ 0x10E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M2_FN_MOD2 -+ AXIMC_M2_FN_MOD2 -+ AXIMC master 2 packing functionality register -+ 0x2000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M2_READ_QOS -+ AXIMC_M2_READ_QOS -+ AXIMC master 2 read priority register -+ 0x20DC -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M2_WRITE_QOS -+ AXIMC_M2_WRITE_QOS -+ AXIMC master 2 write priority register -+ 0x20E0 -+ 0x20 -+ read-write -+ 0x00000006 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M2_FN_MOD -+ AXIMC_M2_FN_MOD -+ AXIMC master 2 issuing capability override functionality register -+ 0x20E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M5_FN_MOD2 -+ AXIMC_M5_FN_MOD2 -+ AXIMC master 5 packing functionality register -+ 0x3000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M5_READ_QOS -+ AXIMC_M5_READ_QOS -+ AXIMC master 5 read priority register -+ 0x30DC -+ 0x20 -+ read-write -+ 0x00000004 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M5_WRITE_QOS -+ AXIMC_M5_WRITE_QOS -+ AXIMC master 5 write priority register -+ 0x30E0 -+ 0x20 -+ read-write -+ 0x00000004 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M5_FN_MOD -+ AXIMC_M5_FN_MOD -+ AXIMC master 5 issuing capability override functionality register -+ 0x30E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M3_READ_QOS -+ AXIMC_M3_READ_QOS -+ AXIMC master 3 read priority register -+ 0x40DC -+ 0x20 -+ read-write -+ 0x00000007 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M3_WRITE_QOS -+ AXIMC_M3_WRITE_QOS -+ AXIMC master 3 write priority register -+ 0x40E0 -+ 0x20 -+ read-write -+ 0x00000007 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M3_FN_MOD -+ AXIMC_M3_FN_MOD -+ AXIMC master 3 packing functionality register -+ 0x40E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M7_READ_QOS -+ AXIMC_M7_READ_QOS -+ AXIMC master 7 read priority register -+ 0x50DC -+ 0x20 -+ read-write -+ 0x00000008 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M7_WRITE_QOS -+ AXIMC_M7_WRITE_QOS -+ AXIMC master 7 write priority register -+ 0x50E0 -+ 0x20 -+ read-write -+ 0x00000008 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M7_FN_MOD -+ AXIMC_M7_FN_MOD -+ AXIMC master 7 issuing capability override functionality register -+ 0x50E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M8_READ_QOS -+ AXIMC_M8_READ_QOS -+ AXIMC master 8 read priority register -+ 0x60DC -+ 0x20 -+ read-write -+ 0x00000008 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M8_WRITE_QOS -+ AXIMC_M8_WRITE_QOS -+ AXIMC master 8 write priority register -+ 0x60E0 -+ 0x20 -+ read-write -+ 0x00000008 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M8_FN_MOD -+ AXIMC_M8_FN_MOD -+ AXIMC master 8 issuing capability override functionality register -+ 0x60E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M4_FN_MOD2 -+ AXIMC_M4_FN_MOD2 -+ AXIMC master 4 packing functionality register -+ 0x8000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M4_READ_QOS -+ AXIMC_M4_READ_QOS -+ AXIMC master 4 read priority register -+ 0x80DC -+ 0x20 -+ read-write -+ 0x00000007 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M4_WRITE_QOS -+ AXIMC_M4_WRITE_QOS -+ AXIMC master 4 write priority register -+ 0x80E0 -+ 0x20 -+ read-write -+ 0x00000007 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M4_FN_MOD -+ AXIMC_M4_FN_MOD -+ AXIMC master 4 packing functionality register -+ 0x80E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M9_READ_QOS -+ AXIMC_M9_READ_QOS -+ AXIMC master 9 read priority register -+ 0x90DC -+ 0x20 -+ read-write -+ 0x0000000B -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M9_WRITE_QOS -+ AXIMC_M9_WRITE_QOS -+ AXIMC master 9 write priority register -+ 0x90E0 -+ 0x20 -+ read-write -+ 0x0000000B -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M9_FN_MOD -+ AXIMC_M9_FN_MOD -+ AXIMC master 9 issuing capability override functionality register -+ 0x90E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M10_READ_QOS -+ AXIMC_M10_READ_QOS -+ AXIMC master 10 read priority register -+ 0xA0DC -+ 0x20 -+ read-write -+ 0x0000000B -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M10_WRITE_QOS -+ AXIMC_M10_WRITE_QOS -+ AXIMC master 10 write priority register -+ 0xA0E0 -+ 0x20 -+ read-write -+ 0x0000000B -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M10_FN_MOD -+ AXIMC_M10_FN_MOD -+ AXIMC master 10 issuing capability override functionality register -+ 0xA0E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M6_FN_MOD2 -+ AXIMC_M6_FN_MOD2 -+ AXIMC master 6 packing functionality register -+ 0xB000 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BYPASS_MERGE -+ BYPASS_MERGE -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M6_READ_QOS -+ AXIMC_M6_READ_QOS -+ AXIMC master 6 read priority register -+ 0xB0DC -+ 0x20 -+ read-write -+ 0x00000004 -+ -+ -+ AR_QOS -+ AR_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M6_WRITE_QOS -+ AXIMC_M6_WRITE_QOS -+ AXIMC master 6 write priority register -+ 0xB0E0 -+ 0x20 -+ read-write -+ 0x00000004 -+ -+ -+ AW_QOS -+ AW_QOS -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ AXIMC_M6_FN_MOD -+ AXIMC_M6_FN_MOD -+ AXIMC master 6 issuing capability override functionality register -+ 0xB0E4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READ_ISS_OVERRIDE -+ READ_ISS_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITE_ISS_OVERRIDE -+ WRITE_ISS_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_4 -+ AXIMC_PERIPH_ID_4 -+ AXIMC peripheral ID4 register -+ 0x1FD0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ JEP106CON -+ JEP106CON -+ 0 -+ 4 -+ read-only -+ -+ -+ K4COUNT -+ K4COUNT -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_5 -+ AXIMC_PERIPH_ID_5 -+ AXIMC peripheral ID5 register -+ 0x1FD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PERIPH_ID_5 -+ PERIPH_ID_5 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_6 -+ AXIMC_PERIPH_ID_6 -+ AXIMC peripheral ID6 register -+ 0x1FD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PERIPH_ID_6 -+ PERIPH_ID_6 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_7 -+ AXIMC_PERIPH_ID_7 -+ AXIMC peripheral ID7 register -+ 0x1FDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PERIPH_ID_7 -+ PERIPH_ID_7 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_0 -+ AXIMC_PERIPH_ID_0 -+ AXIMC peripheral ID0 register -+ 0x1FE0 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PERIPH_ID_0 -+ PERIPH_ID_0 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_1 -+ AXIMC_PERIPH_ID_1 -+ AXIMC peripheral ID1 register -+ 0x1FE4 -+ 0x20 -+ read-only -+ 0x000000B4 -+ -+ -+ PERIPH_ID_1 -+ PERIPH_ID_1 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_2 -+ AXIMC_PERIPH_ID_2 -+ AXIMC peripheral ID2 register -+ 0x1FE8 -+ 0x20 -+ read-only -+ 0x0000003B -+ -+ -+ PERIPH_ID_2 -+ PERIPH_ID_2 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_PERIPH_ID_3 -+ AXIMC_PERIPH_ID_3 -+ AXIMC peripheral ID3 register -+ 0x1FEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ CUST_MOD_NUM -+ CUST_MOD_NUM -+ 0 -+ 4 -+ read-only -+ -+ -+ REV_AND -+ REV_AND -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ AXIMC_COMP_ID_0 -+ AXIMC_COMP_ID_0 -+ AXIMC component ID0 register -+ 0x1FF0 -+ 0x20 -+ read-only -+ 0x0000000D -+ -+ -+ PREAMBLE -+ PREAMBLE -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_COMP_ID_1 -+ AXIMC_COMP_ID_1 -+ AXIMC component ID1 register -+ 0x1FF4 -+ 0x20 -+ read-only -+ 0x000000F0 -+ -+ -+ PREAMBLE -+ PREAMBLE -+ 0 -+ 4 -+ read-only -+ -+ -+ CLASS -+ CLASS -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ AXIMC_COMP_ID_2 -+ AXIMC_COMP_ID_2 -+ AXIMC component ID2 register -+ 0x1FF8 -+ 0x20 -+ read-only -+ 0x00000005 -+ -+ -+ PREAMBLE -+ PREAMBLE -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_COMP_ID_3 -+ AXIMC_COMP_ID_3 -+ AXIMC component ID3 register -+ 0x1FFC -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ PREAMBLE -+ PREAMBLE -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ AXIMC_M0_FN_MOD_AHB -+ AXIMC_M0_FN_MOD_AHB -+ AXIMC master 0 AHB conversion override functionality register -+ 0x42028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RD_INC_OVERRIDE -+ RD_INC_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WR_INC_OVERRIDE -+ WR_INC_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M1_FN_MOD_AHB -+ AXIMC_M1_FN_MOD_AHB -+ AXIMC master 1 AHB conversion override functionality register -+ 0x43028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RD_INC_OVERRIDE -+ RD_INC_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WR_INC_OVERRIDE -+ WR_INC_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M2_FN_MOD_AHB -+ AXIMC_M2_FN_MOD_AHB -+ AXIMC master 2 AHB conversion override functionality register -+ 0x44028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RD_INC_OVERRIDE -+ RD_INC_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WR_INC_OVERRIDE -+ WR_INC_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M5_FN_MOD_AHB -+ AXIMC_M5_FN_MOD_AHB -+ AXIMC master 5 AHB conversion override functionality register -+ 0x45028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RD_INC_OVERRIDE -+ RD_INC_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WR_INC_OVERRIDE -+ WR_INC_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_M6_FN_MOD_AHB -+ AXIMC_M6_FN_MOD_AHB -+ AXIMC master 6 AHB conversion override functionality register -+ 0x4D028 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ RD_INC_OVERRIDE -+ RD_INC_OVERRIDE -+ 0 -+ 1 -+ read-write -+ -+ -+ WR_INC_OVERRIDE -+ WR_INC_OVERRIDE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ AXIMC_FN_MOD_LB -+ AXIMC_FN_MOD_LB -+ AXIMC long burst capability inhibition register -+ 0x4A02C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FN_MOD_LB -+ FN_MOD_LB -+ 0 -+ 1 -+ read-write -+ -+ -+ -+ -+ -+ -+ TZC -+ TZC -+ TZC -+ 0x5C006000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ TZC_IT -+ TrustZone DDR address space controller -+ 4 -+ -+ -+ -+ TZC_BUILD_CONFIG -+ TZC_BUILD_CONFIG -+ Provides information about TZC configuration. -+ 0x00 -+ 0x20 -+ read-only -+ 0x01001F08 -+ -+ -+ NO_OF_REGIONS -+ NO_OF_REGIONS -+ 0 -+ 5 -+ read-only -+ -+ -+ ADDRESS_WIDTH -+ ADDRESS_WIDTH -+ 8 -+ 6 -+ read-only -+ -+ -+ NO_OF_FILTERS -+ NO_OF_FILTERS -+ 24 -+ 2 -+ read-only -+ -+ -+ -+ -+ TZC_ACTION -+ TZC_ACTION -+ Controls interrupt and bus error response behavior when regions permission failures occur. -+ 0x04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ REACTION_VALUE -+ REACTION_VALUE -+ 0 -+ 2 -+ read-write -+ -+ -+ -+ -+ TZC_GATE_KEEPER -+ TZC_GATE_KEEPER -+ Provides control and status for the gate keeper in each filter unit implemented. -+ 0x08 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OPENREQ -+ OPENREQ -+ 0 -+ 2 -+ read-write -+ -+ -+ OPENSTAT -+ OPENSTAT -+ 16 -+ 2 -+ read-only -+ -+ -+ -+ -+ TZC_SPECULATION_CTRL -+ TZC_SPECULATION_CTRL -+ Controls read and write access speculation. -+ 0x0C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ READSPEC_DISABLE -+ READSPEC_DISABLE -+ 0 -+ 1 -+ read-write -+ -+ -+ WRITESPEC_DISABLE -+ WRITESPEC_DISABLE -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_INT_STATUS -+ TZC_INT_STATUS -+ Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. -+ 0x10 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ STATUS -+ STATUS -+ 0 -+ 2 -+ read-only -+ -+ -+ OVERRUN -+ OVERRUN -+ 8 -+ 2 -+ read-only -+ -+ -+ OVERLAP -+ OVERLAP -+ 16 -+ 2 -+ read-only -+ -+ -+ -+ -+ TZC_INT_CLEAR -+ TZC_INT_CLEAR -+ Interrupt clear for each filter. -+ 0x14 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLEAR -+ CLEAR -+ 0 -+ 2 -+ write-only -+ -+ -+ -+ -+ TZC_FAIL_CONTROL0 -+ TZC_FAIL_CONTROL0 -+ Status information about the first access that failed a region permission check in the associated filter (0 to 1). -+ 0x28 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PRIVILEGE -+ PRIVILEGE -+ 20 -+ 1 -+ read-only -+ -+ -+ NON_SECURE -+ NON_SECURE -+ 21 -+ 1 -+ read-only -+ -+ -+ DIRECTION -+ DIRECTION -+ 24 -+ 1 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_ID0 -+ TZC_FAIL_ID0 -+ Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. -+AXI ID mapping is described in Table4: NSAID definition table (TBD). -+ 0x2C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ID -+ ID -+ 0 -+ 11 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_CONTROL1 -+ TZC_FAIL_CONTROL1 -+ Status information about the first access that failed a region permission check in the associated filter (0 to 1). -+ 0x38 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PRIVILEGE -+ PRIVILEGE -+ 20 -+ 1 -+ read-only -+ -+ -+ NON_SECURE -+ NON_SECURE -+ 21 -+ 1 -+ read-only -+ -+ -+ DIRECTION -+ DIRECTION -+ 24 -+ 1 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_ID1 -+ TZC_FAIL_ID1 -+ Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. -+AXI ID mapping is described in Table4: NSAID definition table (TBD). -+ 0x3C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ID -+ ID -+ 0 -+ 11 -+ read-only -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE0 -+ TZC_REGION_ATTRIBUTE0 -+ Region 0 attributes. -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000003 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-only -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE1 -+ TZC_REGION_ATTRIBUTE1 -+ Region x attributes. -+ 0x130 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE2 -+ TZC_REGION_ATTRIBUTE2 -+ Region x attributes. -+ 0x150 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE3 -+ TZC_REGION_ATTRIBUTE3 -+ Region x attributes. -+ 0x170 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE4 -+ TZC_REGION_ATTRIBUTE4 -+ Region x attributes. -+ 0x190 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE5 -+ TZC_REGION_ATTRIBUTE5 -+ Region x attributes. -+ 0x1B0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE6 -+ TZC_REGION_ATTRIBUTE6 -+ Region x attributes. -+ 0x1D0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE7 -+ TZC_REGION_ATTRIBUTE7 -+ Region x attributes. -+ 0x1F0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_ATTRIBUTE8 -+ TZC_REGION_ATTRIBUTE8 -+ Region x attributes. -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ FILTER_EN -+ FILTER_EN -+ 0 -+ 2 -+ read-write -+ -+ -+ S_RD_EN -+ S_RD_EN -+ 30 -+ 1 -+ read-write -+ -+ -+ S_WR_EN -+ S_WR_EN -+ 31 -+ 1 -+ read-write -+ -+ -+ -+ -+ TZC_PID4 -+ TZC_PID4 -+ Peripheral ID 4. -+ 0xFD0 -+ 0x20 -+ read-only -+ 0x00000004 -+ -+ -+ PER_ID_4 -+ PER_ID_4 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID5 -+ TZC_PID5 -+ Peripheral ID 5. -+ 0xFD4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PER_ID_5 -+ PER_ID_5 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID6 -+ TZC_PID6 -+ Peripheral ID 6. -+ 0xFD8 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PER_ID_6 -+ PER_ID_6 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID7 -+ TZC_PID7 -+ Peripheral ID 7. -+ 0xFDC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PER_ID_7 -+ PER_ID_7 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID0 -+ TZC_PID0 -+ Peripheral ID 0. -+ 0xFE0 -+ 0x20 -+ read-only -+ 0x00000060 -+ -+ -+ PER_ID_0 -+ PER_ID_0 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID1 -+ TZC_PID1 -+ Peripheral ID 1. -+ 0xFE4 -+ 0x20 -+ read-only -+ 0x000000B4 -+ -+ -+ PER_ID_1 -+ PER_ID_1 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID2 -+ TZC_PID2 -+ Peripheral ID 2. -+ 0xFE8 -+ 0x20 -+ read-only -+ 0x0000002B -+ -+ -+ PER_ID_2 -+ PER_ID_2 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_PID3 -+ TZC_PID3 -+ Peripheral ID 3. -+ 0xFEC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ PER_ID_3 -+ PER_ID_3 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_CID0 -+ TZC_CID0 -+ Component ID 0. -+ 0xFF0 -+ 0x20 -+ read-only -+ 0x0000000D -+ -+ -+ COMP_ID_0 -+ COMP_ID_0 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_CID1 -+ TZC_CID1 -+ Component ID 1. -+ 0xFF4 -+ 0x20 -+ read-only -+ 0x000000F0 -+ -+ -+ COMP_ID_1 -+ COMP_ID_1 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_CID2 -+ TZC_CID2 -+ Component ID 2. -+ 0xFF8 -+ 0x20 -+ read-only -+ 0x00000005 -+ -+ -+ COMP_ID_2 -+ COMP_ID_2 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_CID3 -+ TZC_CID3 -+ Component ID 3. -+ 0xFFC -+ 0x20 -+ read-only -+ 0x000000B1 -+ -+ -+ COMP_ID_3 -+ COMP_ID_3 -+ 0 -+ 8 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_ADDRESS_LOW0 -+ TZC_FAIL_ADDRESS_LOW0 -+ Address low bits of the first failed access in the associated filter (0 to 1). -+ 0x20 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ADDR_STATUS_LOW -+ ADDR_STATUS_LOW -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_ADDRESS_HIGH0 -+ TZC_FAIL_ADDRESS_HIGH0 -+ Address high bit of the first failed access in the associated filter (0 to 1). -+Not used with 32bit address. -+ 0x24 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_FAIL_ADDRESS_LOW1 -+ TZC_FAIL_ADDRESS_LOW1 -+ Address low bits of the first failed access in the associated filter (0 to 1). -+ 0x30 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ADDR_STATUS_LOW -+ ADDR_STATUS_LOW -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ TZC_FAIL_ADDRESS_HIGH1 -+ TZC_FAIL_ADDRESS_HIGH1 -+ Address high bit of the first failed access in the associated filter (0 to 1). -+Not used with 32bit address. -+ 0x34 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_BASE_HIGH0 -+ TZC_REGION_BASE_HIGH0 -+ Base address high are not used with 32-bit address. -+ 0x104 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW0 -+ TZC_REGION_TOP_LOW0 -+ Top address bits [31:12] for region 0. -+ 0x108 -+ 0x20 -+ read-only -+ 0xFFFFFFFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-only -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH0 -+ TZC_REGION_TOP_HIGH0 -+ Top address high of region are not used with 32-bit address. -+ 0x10C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS0 -+ TZC_REGION_ID_ACCESS0 -+ Region non-secure access based on NSAID. -+ 0x114 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW1 -+ TZC_REGION_BASE_LOW1 -+ Base address low for regions 1 to 8. -+ 0x120 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH1 -+ TZC_REGION_BASE_HIGH1 -+ Base address high are not used with 32-bit address. -+ 0x124 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW1 -+ TZC_REGION_TOP_LOW1 -+ Top address bits [31:12] for region x. -+ 0x128 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH1 -+ TZC_REGION_TOP_HIGH1 -+ Top address high of region are not used with 32-bit address. -+ 0x12C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS1 -+ TZC_REGION_ID_ACCESS1 -+ Region non-secure access based on NSAID. -+ 0x134 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW2 -+ TZC_REGION_BASE_LOW2 -+ Base address low for regions 1 to 8. -+ 0x140 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH2 -+ TZC_REGION_BASE_HIGH2 -+ Base address high are not used with 32-bit address. -+ 0x144 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW2 -+ TZC_REGION_TOP_LOW2 -+ Top address bits [31:12] for region x. -+ 0x148 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH2 -+ TZC_REGION_TOP_HIGH2 -+ Top address high of region are not used with 32-bit address. -+ 0x14C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS2 -+ TZC_REGION_ID_ACCESS2 -+ Region non-secure access based on NSAID. -+ 0x154 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW3 -+ TZC_REGION_BASE_LOW3 -+ Base address low for regions 1 to 8. -+ 0x160 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH3 -+ TZC_REGION_BASE_HIGH3 -+ Base address high are not used with 32-bit address. -+ 0x164 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW3 -+ TZC_REGION_TOP_LOW3 -+ Top address bits [31:12] for region x. -+ 0x168 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH3 -+ TZC_REGION_TOP_HIGH3 -+ Top address high of region are not used with 32-bit address. -+ 0x16C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS3 -+ TZC_REGION_ID_ACCESS3 -+ Region non-secure access based on NSAID. -+ 0x174 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW4 -+ TZC_REGION_BASE_LOW4 -+ Base address low for regions 1 to 8. -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH4 -+ TZC_REGION_BASE_HIGH4 -+ Base address high are not used with 32-bit address. -+ 0x184 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW4 -+ TZC_REGION_TOP_LOW4 -+ Top address bits [31:12] for region x. -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH4 -+ TZC_REGION_TOP_HIGH4 -+ Top address high of region are not used with 32-bit address. -+ 0x18C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS4 -+ TZC_REGION_ID_ACCESS4 -+ Region non-secure access based on NSAID. -+ 0x194 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW5 -+ TZC_REGION_BASE_LOW5 -+ Base address low for regions 1 to 8. -+ 0x1A0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH5 -+ TZC_REGION_BASE_HIGH5 -+ Base address high are not used with 32-bit address. -+ 0x1A4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW5 -+ TZC_REGION_TOP_LOW5 -+ Top address bits [31:12] for region x. -+ 0x1A8 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH5 -+ TZC_REGION_TOP_HIGH5 -+ Top address high of region are not used with 32-bit address. -+ 0x1AC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS5 -+ TZC_REGION_ID_ACCESS5 -+ Region non-secure access based on NSAID. -+ 0x1B4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW6 -+ TZC_REGION_BASE_LOW6 -+ Base address low for regions 1 to 8. -+ 0x1C0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH6 -+ TZC_REGION_BASE_HIGH6 -+ Base address high are not used with 32-bit address. -+ 0x1C4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW6 -+ TZC_REGION_TOP_LOW6 -+ Top address bits [31:12] for region x. -+ 0x1C8 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH6 -+ TZC_REGION_TOP_HIGH6 -+ Top address high of region are not used with 32-bit address. -+ 0x1CC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS6 -+ TZC_REGION_ID_ACCESS6 -+ Region non-secure access based on NSAID. -+ 0x1D4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW7 -+ TZC_REGION_BASE_LOW7 -+ Base address low for regions 1 to 8. -+ 0x2E0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH7 -+ TZC_REGION_BASE_HIGH7 -+ Base address high are not used with 32-bit address. -+ 0x2E4 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW7 -+ TZC_REGION_TOP_LOW7 -+ Top address bits [31:12] for region x. -+ 0x1E8 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH7 -+ TZC_REGION_TOP_HIGH7 -+ Top address high of region are not used with 32-bit address. -+ 0x2EC -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS7 -+ TZC_REGION_ID_ACCESS7 -+ Region non-secure access based on NSAID. -+ 0x2F4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_LOW8 -+ TZC_REGION_BASE_LOW8 -+ Base address low for regions 1 to 8. -+ 0x200 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ BASE_ADDRESS_LOW -+ BASE_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_BASE_HIGH8 -+ TZC_REGION_BASE_HIGH8 -+ Base address high are not used with 32-bit address. -+ 0x204 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_TOP_LOW8 -+ TZC_REGION_TOP_LOW8 -+ Top address bits [31:12] for region x. -+ 0x308 -+ 0x20 -+ read-write -+ 0x00000FFF -+ -+ -+ TOP_ADDRESS_LOW -+ TOP_ADDRESS_LOW -+ 12 -+ 20 -+ read-write -+ -+ -+ -+ -+ TZC_REGION_TOP_HIGH8 -+ TZC_REGION_TOP_HIGH8 -+ Top address high of region are not used with 32-bit address. -+ 0x30C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ -+ TZC_REGION_ID_ACCESS8 -+ TZC_REGION_ID_ACCESS8 -+ Region non-secure access based on NSAID. -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ NSAID_RD_EN -+ NSAID_RD_EN -+ 0 -+ 16 -+ read-write -+ -+ -+ NSAID_WR_EN -+ NSAID_WR_EN -+ 16 -+ 16 -+ read-write -+ -+ -+ -+ -+ -+ -+ -+ TIM15 -+ TIM15 -+ TIMER -+ 0x44006000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIM15_CR1 -+ TIM15_CR1 -+ TIM15 control register 1 -+ 0x00 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ read-write -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ read-write -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ read-write -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ read-write -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ read-write -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ read-write -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIM15_CR2 -+ TIM15_CR2 -+ TIM15 control register 2 -+ 0x04 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ read-write -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ read-write -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ read-write -+ -+ -+ MMS -+ MMS -+ 4 -+ 3 -+ read-write -+ -+ -+ TI1S -+ TI1S -+ 7 -+ 1 -+ read-write -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ read-write -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ read-write -+ -+ -+ OIS2 -+ OIS2 -+ 10 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_SMCR -+ TIMx_SMCR -+ slave mode control register -+ 0x8 -+ 0x20 -+ read-write -+ 0x0000 -+ -+ -+ TS_4_3 -+ Trigger selection -+ 20 -+ 2 -+ -+ -+ SMS_3 -+ Slave mode selection - bit -+ 3 -+ 16 -+ 1 -+ -+ -+ MSM -+ Master/Slave mode -+ 7 -+ 1 -+ -+ -+ TS -+ Trigger selection -+ 4 -+ 3 -+ -+ -+ SMS -+ Slave mode selection -+ 0 -+ 3 -+ -+ -+ -+ -+ TIM15_DIER -+ TIM15_DIER -+ TIM15 DMA/interrupt enable -+ register -+ 0x0C -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ read-write -+ -+ -+ CC2IE -+ CC2IE -+ 2 -+ 1 -+ read-write -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ read-write -+ -+ -+ TIE -+ TIE -+ 6 -+ 1 -+ read-write -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ read-write -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ read-write -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ read-write -+ -+ -+ CC2DE -+ CC2DE -+ 10 -+ 1 -+ read-write -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ read-write -+ -+ -+ TDE -+ TDE -+ 14 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIM15_SR -+ TIM15_SR -+ TIM15 status register -+ 0x10 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ read-write -+ -+ -+ CC2IF -+ CC2IF -+ 2 -+ 1 -+ read-write -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ read-write -+ -+ -+ TIF -+ TIF -+ 6 -+ 1 -+ read-write -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ read-write -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ read-write -+ -+ -+ CC2OF -+ CC2OF -+ 10 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_EGR -+ TIMx_EGR -+ event generation register -+ 0x14 -+ 0x20 -+ write-only -+ 0x0000 -+ -+ -+ BG -+ BG -+ 7 -+ 1 -+ -+ -+ TG -+ Trigger generation -+ 6 -+ 1 -+ -+ -+ COMG -+ COMG -+ 5 -+ 1 -+ -+ -+ CC2G -+ Capture/compare 2 -+ generation -+ 2 -+ 1 -+ -+ -+ CC1G -+ Capture/compare 1 -+ generation -+ 1 -+ 1 -+ -+ -+ UG -+ Update generation -+ 0 -+ 1 -+ -+ -+ -+ -+ TIMx_CCMR1_Output -+ TIMx_CCMR1_Output -+ capture/compare mode register 1 (output -+ mode) -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ OC2M_3 -+ Output Compare 2 mode - bit -+ 3 -+ 24 -+ 1 -+ -+ -+ OC1M_3 -+ Output Compare 1 mode - bit -+ 3 -+ 16 -+ 1 -+ -+ -+ OC2CE -+ Output compare 2 clear -+ enable -+ 15 -+ 1 -+ -+ -+ OC2M -+ Output compare 2 mode -+ 12 -+ 3 -+ -+ -+ OC2PE -+ Output compare 2 preload -+ enable -+ 11 -+ 1 -+ -+ -+ OC2FE -+ Output compare 2 fast -+ enable -+ 10 -+ 1 -+ -+ -+ CC2S -+ Capture/Compare 2 -+ selection -+ 8 -+ 2 -+ -+ -+ OC1CE -+ Output compare 1 clear -+ enable -+ 7 -+ 1 -+ -+ -+ OC1M -+ Output compare 1 mode -+ 4 -+ 3 -+ -+ -+ OC1PE -+ Output compare 1 preload -+ enable -+ 3 -+ 1 -+ -+ -+ OC1FE -+ Output compare 1 fast -+ enable -+ 2 -+ 1 -+ -+ -+ CC1S -+ Capture/Compare 1 -+ selection -+ 0 -+ 2 -+ -+ -+ -+ -+ TIMx_CCMR1_Input -+ TIMx_CCMR1_Input -+ capture/compare mode register 1 (input -+ mode) -+ TIMx_CCMR1_Output -+ 0x18 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IC2F -+ Input capture 2 filter -+ 12 -+ 4 -+ -+ -+ IC2PSC -+ Input capture 2 prescaler -+ 10 -+ 2 -+ -+ -+ CC2S -+ Capture/compare 2 -+ selection -+ 8 -+ 2 -+ -+ -+ IC1F -+ Input capture 1 filter -+ 4 -+ 4 -+ -+ -+ IC1PSC -+ Input capture 1 prescaler -+ 2 -+ 2 -+ -+ -+ CC1S -+ Capture/Compare 1 -+ selection -+ 0 -+ 2 -+ -+ -+ -+ -+ TIM15_CCER -+ TIM15_CCER -+ TIM15 capture/compare enable -+ register -+ 0x20 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ read-write -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ read-write -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ read-write -+ -+ -+ CC2E -+ CC2E -+ 4 -+ 1 -+ read-write -+ -+ -+ CC2P -+ CC2P -+ 5 -+ 1 -+ read-write -+ -+ -+ CC2NP -+ CC2NP -+ 7 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIM15_CNT -+ TIM15_CNT -+ TIM15 counter -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIM15_PSC -+ TIM15_PSC -+ TIM15 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIM15_ARR -+ TIM15_ARR -+ TIM15 auto-reload register -+ 0x2C -+ 0x10 -+ read-write -+ 0xFFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIM15_RCR -+ TIM15_RCR -+ TIM15 repetition counter -+ register -+ 0x30 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ REP -+ REP -+ 0 -+ 8 -+ read-write -+ -+ -+ -+ -+ TIM15_CCR1 -+ TIM15_CCR1 -+ TIM15 capture/compare register -+ 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIM15_CCR2 -+ TIM15_CCR2 -+ TIM15 capture/compare register -+ 2 -+ 0x38 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CCR2 -+ CCR2 -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIMx_BDTR -+ TIMx_BDTR -+ As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, -+ BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, -+ OSSR and DTG[7:0] can be write-locked depending on the -+ LOCK configuration, it can be necessary to configure all -+ of them during the first write access to the TIMx_BDTR -+ register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ read-write -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ read-write -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ read-write -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ read-write -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ read-write -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ read-write -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ read-write -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ read-write -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ read-write -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ read-write -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIM15_DCR -+ TIM15_DCR -+ TIM15 DMA control register -+ 0x48 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ read-write -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ read-write -+ -+ -+ -+ -+ TIM15_DMAR -+ TIM15_DMAR -+ TIM15 DMA address for full -+ transfer -+ 0x4C -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIM15_AF1 -+ TIM15_AF1 -+ TIM15 alternate register 1 -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BKINE -+ BKINE -+ 0 -+ 1 -+ read-write -+ -+ -+ BKDF1BK0E -+ BKDF1BK0E -+ 8 -+ 1 -+ read-write -+ -+ -+ BKINP -+ BKINP -+ 9 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIM15_TISEL -+ TIM15_TISEL -+ TIM15 input selection register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ read-write -+ -+ -+ TI2SEL -+ TI2SEL -+ 8 -+ 4 -+ read-write -+ -+ -+ -+ -+ -+ -+ TIM16 -+ TIM16 -+ TIMER -+ 0x44007000 -+ -+ 0x0 -+ 0x400 -+ registers -+ -+ -+ -+ TIMx_CR1 -+ TIMx_CR1 -+ TIM16/TIM17 control register 1 -+ 0x00 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CEN -+ CEN -+ 0 -+ 1 -+ read-write -+ -+ -+ UDIS -+ UDIS -+ 1 -+ 1 -+ read-write -+ -+ -+ URS -+ URS -+ 2 -+ 1 -+ read-write -+ -+ -+ OPM -+ OPM -+ 3 -+ 1 -+ read-write -+ -+ -+ ARPE -+ ARPE -+ 7 -+ 1 -+ read-write -+ -+ -+ CKD -+ CKD -+ 8 -+ 2 -+ read-write -+ -+ -+ UIFREMAP -+ UIFREMAP -+ 11 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_CR2 -+ TIMx_CR2 -+ TIM16/TIM17 control register 2 -+ 0x04 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CCPC -+ CCPC -+ 0 -+ 1 -+ read-write -+ -+ -+ CCUS -+ CCUS -+ 2 -+ 1 -+ read-write -+ -+ -+ CCDS -+ CCDS -+ 3 -+ 1 -+ read-write -+ -+ -+ OIS1 -+ OIS1 -+ 8 -+ 1 -+ read-write -+ -+ -+ OIS1N -+ OIS1N -+ 9 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_DIER -+ TIMx_DIER -+ TIM16/TIM17 DMA/interrupt enable -+ register -+ 0x0C -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ UIE -+ UIE -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1IE -+ CC1IE -+ 1 -+ 1 -+ read-write -+ -+ -+ COMIE -+ COMIE -+ 5 -+ 1 -+ read-write -+ -+ -+ BIE -+ BIE -+ 7 -+ 1 -+ read-write -+ -+ -+ UDE -+ UDE -+ 8 -+ 1 -+ read-write -+ -+ -+ CC1DE -+ CC1DE -+ 9 -+ 1 -+ read-write -+ -+ -+ COMDE -+ COMDE -+ 13 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_SR -+ TIMx_SR -+ TIM16/TIM17 status register -+ 0x10 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ UIF -+ UIF -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1IF -+ CC1IF -+ 1 -+ 1 -+ read-write -+ -+ -+ COMIF -+ COMIF -+ 5 -+ 1 -+ read-write -+ -+ -+ BIF -+ BIF -+ 7 -+ 1 -+ read-write -+ -+ -+ CC1OF -+ CC1OF -+ 9 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_EGR -+ TIMx_EGR -+ event generation register -+ 0x14 -+ 0x20 -+ write-only -+ 0x0000 -+ -+ -+ UG -+ Update generation -+ 0 -+ 1 -+ -+ -+ -+ -+ TIMx_CCER -+ TIMx_CCER -+ TIM16/TIM17 capture/compare enable -+ register -+ 0x20 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CC1E -+ CC1E -+ 0 -+ 1 -+ read-write -+ -+ -+ CC1P -+ CC1P -+ 1 -+ 1 -+ read-write -+ -+ -+ CC1NE -+ CC1NE -+ 2 -+ 1 -+ read-write -+ -+ -+ CC1NP -+ CC1NP -+ 3 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_CNT -+ TIMx_CNT -+ TIM16/TIM17 counter -+ 0x24 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CNT -+ CNT -+ 0 -+ 16 -+ read-write -+ -+ -+ UIFCPY -+ UIFCPY -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ TIMx_PSC -+ TIMx_PSC -+ TIM16/TIM17 prescaler -+ 0x28 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ PSC -+ PSC -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIMx_ARR -+ TIMx_ARR -+ TIM16/TIM17 auto-reload -+ register -+ 0x2C -+ 0x10 -+ read-write -+ 0xFFFF -+ -+ -+ ARR -+ ARR -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIMx_RCR -+ TIMx_RCR -+ TIM16/TIM17 repetition counter -+ register -+ 0x30 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ REP -+ REP -+ 0 -+ 8 -+ read-write -+ -+ -+ -+ -+ TIMx_CCR1 -+ TIMx_CCR1 -+ TIM16/TIM17 capture/compare register -+ 1 -+ 0x34 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ CCR1 -+ CCR1 -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIMx_BDTR -+ TIMx_BDTR -+ As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, -+ BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked -+ depending on the LOCK configuration, it may be necessary -+ to configure all of them during the first write access to -+ the TIMx_BDTR register. -+ 0x44 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DTG -+ DTG -+ 0 -+ 8 -+ read-write -+ -+ -+ LOCK -+ LOCK -+ 8 -+ 2 -+ read-write -+ -+ -+ OSSI -+ OSSI -+ 10 -+ 1 -+ read-write -+ -+ -+ OSSR -+ OSSR -+ 11 -+ 1 -+ read-write -+ -+ -+ BKE -+ BKE -+ 12 -+ 1 -+ read-write -+ -+ -+ BKP -+ BKP -+ 13 -+ 1 -+ read-write -+ -+ -+ AOE -+ AOE -+ 14 -+ 1 -+ read-write -+ -+ -+ MOE -+ MOE -+ 15 -+ 1 -+ read-write -+ -+ -+ BKF -+ BKF -+ 16 -+ 4 -+ read-write -+ -+ -+ BKDSRM -+ BKDSRM -+ 26 -+ 1 -+ read-write -+ -+ -+ BKBID -+ BKBID -+ 28 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_DCR -+ TIMx_DCR -+ TIM16/TIM17 DMA control -+ register -+ 0x48 -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ DBA -+ DBA -+ 0 -+ 5 -+ read-write -+ -+ -+ DBL -+ DBL -+ 8 -+ 5 -+ read-write -+ -+ -+ -+ -+ TIMx_DMAR -+ TIMx_DMAR -+ TIM16/TIM17 DMA address for full -+ transfer -+ 0x4C -+ 0x10 -+ read-write -+ 0x0000 -+ -+ -+ DMAB -+ DMAB -+ 0 -+ 16 -+ read-write -+ -+ -+ -+ -+ TIMx_AF1 -+ TIM17_AF1 -+ TIM17 alternate function register -+ 1 -+ 0x60 -+ 0x20 -+ read-write -+ 0x00000001 -+ -+ -+ BKINE -+ BKINE -+ 0 -+ 1 -+ read-write -+ -+ -+ BKDF1BK2E -+ BKDF1BK2E -+ 8 -+ 1 -+ read-write -+ -+ -+ BKINP -+ BKINP -+ 9 -+ 1 -+ read-write -+ -+ -+ -+ -+ TIMx_TISEL -+ TIM17_TISEL -+ TIM17 input selection register -+ 0x68 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ TI1SEL -+ TI1SEL -+ 0 -+ 4 -+ read-write -+ -+ -+ -+ -+ -+ -+ TIM17 -+ 0x44008000 -+ -+ -+ DLYBQS -+ DLYBQS -+ DLYB -+ 0x58004000 -+ -+ 0x0 -+ 0x1000 -+ registers -+ -+ -+ -+ DLYB_CR -+ DLYB_CR -+ DLYB control register -+ 0x00 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ DEN -+ DEN -+ 0 -+ 1 -+ read-write -+ -+ -+ SEN -+ SEN -+ 1 -+ 1 -+ read-write -+ -+ -+ -+ -+ DLYB_CFGR -+ DLYB_CFGR -+ DLYB configuration register -+ 0x04 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SEL -+ SEL -+ 0 -+ 4 -+ read-write -+ -+ -+ UNIT -+ UNIT -+ 8 -+ 7 -+ read-write -+ -+ -+ LNG -+ LNG -+ 16 -+ 12 -+ read-only -+ -+ -+ LNGF -+ LNGF -+ 31 -+ 1 -+ read-only -+ -+ -+ -+ -+ DLYB_VERR -+ DLYB_VERR -+ DLYB IP version register -+ 0x3F4 -+ 0x20 -+ read-only -+ 0x00000011 -+ -+ -+ MINREV -+ MINREV -+ 0 -+ 4 -+ read-only -+ -+ -+ MAJREV -+ MAJREV -+ 4 -+ 4 -+ read-only -+ -+ -+ -+ -+ DLYB_IPIDR -+ DLYB_IPIDR -+ DLYB IP identification -+ register -+ 0x3F8 -+ 0x20 -+ read-only -+ 0x00140051 -+ -+ -+ ID -+ ID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ DLYB_SIDR -+ DLYB_SIDR -+ DLYB size ID register -+ 0x3FC -+ 0x20 -+ read-only -+ 0xA3C5DD01 -+ -+ -+ SID -+ SID -+ 0 -+ 32 -+ read-only -+ -+ -+ -+ -+ -+ -+ NVIC -+ Nested Vectored Interrupt -+ Controller -+ NVIC -+ 0xE000E100 -+ -+ 0x0 -+ 0x401 -+ registers -+ -+ -+ -+ ISER0 -+ ISER0 -+ Interrupt Set-Enable Register -+ 0x0 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETENA -+ SETENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ISER1 -+ ISER1 -+ Interrupt Set-Enable Register -+ 0x4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETENA -+ SETENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ISER2 -+ ISER2 -+ Interrupt Set-Enable Register -+ 0x8 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETENA -+ SETENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ISER3 -+ ISER3 -+ Interrupt Set-Enable Register -+ 0xC -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETENA -+ SETENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ICER0 -+ ICER0 -+ Interrupt Clear-Enable -+ Register -+ 0x80 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRENA -+ CLRENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ICER1 -+ ICER1 -+ Interrupt Clear-Enable -+ Register -+ 0x84 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRENA -+ CLRENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ICER2 -+ ICER2 -+ Interrupt Clear-Enable -+ Register -+ 0x88 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRENA -+ CLRENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ICER3 -+ ICER3 -+ Interrupt Clear-Enable -+ Register -+ 0x8C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRENA -+ CLRENA -+ 0 -+ 32 -+ -+ -+ -+ -+ ISPR0 -+ ISPR0 -+ Interrupt Set-Pending Register -+ 0x100 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETPEND -+ SETPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ISPR1 -+ ISPR1 -+ Interrupt Set-Pending Register -+ 0x104 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETPEND -+ SETPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ISPR2 -+ ISPR2 -+ Interrupt Set-Pending Register -+ 0x108 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETPEND -+ SETPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ISPR3 -+ ISPR3 -+ Interrupt Set-Pending Register -+ 0x10C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ SETPEND -+ SETPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ICPR0 -+ ICPR0 -+ Interrupt Clear-Pending -+ Register -+ 0x180 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRPEND -+ CLRPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ICPR1 -+ ICPR1 -+ Interrupt Clear-Pending -+ Register -+ 0x184 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRPEND -+ CLRPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ICPR2 -+ ICPR2 -+ Interrupt Clear-Pending -+ Register -+ 0x188 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRPEND -+ CLRPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ ICPR3 -+ ICPR3 -+ Interrupt Clear-Pending -+ Register -+ 0x18C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ CLRPEND -+ CLRPEND -+ 0 -+ 32 -+ -+ -+ -+ -+ IABR0 -+ IABR0 -+ Interrupt Active Bit Register -+ 0x200 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ACTIVE -+ ACTIVE -+ 0 -+ 32 -+ -+ -+ -+ -+ IABR1 -+ IABR1 -+ Interrupt Active Bit Register -+ 0x204 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ACTIVE -+ ACTIVE -+ 0 -+ 32 -+ -+ -+ -+ -+ IABR2 -+ IABR2 -+ Interrupt Active Bit Register -+ 0x208 -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ACTIVE -+ ACTIVE -+ 0 -+ 32 -+ -+ -+ -+ -+ IABR3 -+ IABR3 -+ Interrupt Active Bit Register -+ 0x20C -+ 0x20 -+ read-only -+ 0x00000000 -+ -+ -+ ACTIVE -+ ACTIVE -+ 0 -+ 32 -+ -+ -+ -+ -+ IPR0 -+ IPR0 -+ Interrupt Priority Register -+ 0x300 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR1 -+ IPR1 -+ Interrupt Priority Register -+ 0x304 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR2 -+ IPR2 -+ Interrupt Priority Register -+ 0x308 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR3 -+ IPR3 -+ Interrupt Priority Register -+ 0x30C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR4 -+ IPR4 -+ Interrupt Priority Register -+ 0x310 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR5 -+ IPR5 -+ Interrupt Priority Register -+ 0x314 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR6 -+ IPR6 -+ Interrupt Priority Register -+ 0x318 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR7 -+ IPR7 -+ Interrupt Priority Register -+ 0x31C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR8 -+ IPR8 -+ Interrupt Priority Register -+ 0x320 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR9 -+ IPR9 -+ Interrupt Priority Register -+ 0x324 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR10 -+ IPR10 -+ Interrupt Priority Register -+ 0x328 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR11 -+ IPR11 -+ Interrupt Priority Register -+ 0x32C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR12 -+ IPR12 -+ Interrupt Priority Register -+ 0x330 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR13 -+ IPR13 -+ Interrupt Priority Register -+ 0x334 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR14 -+ IPR14 -+ Interrupt Priority Register -+ 0x338 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR15 -+ IPR15 -+ Interrupt Priority Register -+ 0x33C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR16 -+ IPR16 -+ Interrupt Priority Register -+ 0x340 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR17 -+ IPR17 -+ Interrupt Priority Register -+ 0x344 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR18 -+ IPR18 -+ Interrupt Priority Register -+ 0x348 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR19 -+ IPR19 -+ Interrupt Priority Register -+ 0x34C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR20 -+ IPR20 -+ Interrupt Priority Register -+ 0x350 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR21 -+ IPR21 -+ Interrupt Priority Register -+ 0x354 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR22 -+ IPR22 -+ Interrupt Priority Register -+ 0x358 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR23 -+ IPR23 -+ Interrupt Priority Register -+ 0x35C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR24 -+ IPR24 -+ Interrupt Priority Register -+ 0x360 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR25 -+ IPR25 -+ Interrupt Priority Register -+ 0x364 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR26 -+ IPR26 -+ Interrupt Priority Register -+ 0x368 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR27 -+ IPR27 -+ Interrupt Priority Register -+ 0x36C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR28 -+ IPR28 -+ Interrupt Priority Register -+ 0x370 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR29 -+ IPR29 -+ Interrupt Priority Register -+ 0x374 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR30 -+ IPR30 -+ Interrupt Priority Register -+ 0x378 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR31 -+ IPR31 -+ Interrupt Priority Register -+ 0x37C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR32 -+ IPR32 -+ Interrupt Priority Register -+ 0x380 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR33 -+ IPR33 -+ Interrupt Priority Register -+ 0x384 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR34 -+ IPR34 -+ Interrupt Priority Register -+ 0x388 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR35 -+ IPR35 -+ Interrupt Priority Register -+ 0x38C -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR36 -+ IPR36 -+ Interrupt Priority Register -+ 0x390 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR37 -+ IPR37 -+ Interrupt Priority Register -+ 0x394 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ IPR38 -+ IPR38 -+ Interrupt Priority Register -+ 0x398 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IPR_N0 -+ IPR_N0 -+ 0 -+ 8 -+ -+ -+ IPR_N1 -+ IPR_N1 -+ 8 -+ 8 -+ -+ -+ IPR_N2 -+ IPR_N2 -+ 16 -+ 8 -+ -+ -+ IPR_N3 -+ IPR_N3 -+ 24 -+ 8 -+ -+ -+ -+ -+ ISER4 -+ ISER4 -+ Interrupt Set-Enable Register -+ 0x10 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICER4 -+ ICER4 -+ Interrupt Clear-Enable -+ Register -+ 0x90 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ISPR4 -+ ISPR4 -+ Interrupt Set-Pending Register -+ 0x110 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ ICPR4 -+ ICPR4 -+ Interrupt Clear-Pending -+ Register -+ 0x1C4 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ IABR4 -+ IABR4 -+ Interrupt Active Bit Register -+ 0x210 -+ 0x20 -+ read-write -+ 0x00000000 -+ -+ -+ -+ -+ --- -2.7.4 - diff --git a/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP13xx.svd b/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP13xx.svd new file mode 100644 index 0000000..dd23d91 --- /dev/null +++ b/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP13xx.svd @@ -0,0 +1,184041 @@ + + + + STM32MP13xx + 1.4 + STM32MP13xx + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC1 + ADC + ADC + 0x48003000 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 18 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready +This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. +It is cleared by software writing 1 to it. + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag +This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. + 1 + 1 + read-write + + + B_0x0 + not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag +This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register + 2 + 1 + read-write + + + B_0x0 + Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular channel conversion complete + 0x1 + + + + + EOS + End of regular sequence flag +This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. + 3 + 1 + read-write + + + B_0x0 + Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular Conversions sequence complete + 0x1 + + + + + OVR + ADC overrun +This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + JEOC + Injected channel end of conversion flag +This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register + 5 + 1 + read-write + + + B_0x0 + Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected channel conversion complete + 0x1 + + + + + JEOS + Injected channel end of sequence flag +This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. + 6 + 1 + read-write + + + B_0x0 + Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected conversions complete + 0x1 + + + + + AWD1 + Analog watchdog 1 flag +This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it. + 7 + 1 + read-write + + + B_0x0 + No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 1 event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag +This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it. + 8 + 1 + read-write + + + B_0x0 + No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 2 event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag +This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it. + 9 + 1 + read-write + + + B_0x0 + No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 3 event occurred + 0x1 + + + + + JQOVF + Injected context queue overflow +This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information. + 10 + 1 + read-write + + + B_0x0 + No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected context queue overflow has occurred + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable +This bit is set and cleared by software to enable/disable the ADC Ready interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled + 0x0 + + + B_0x1 + ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable for regular conversions +This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. + 0x1 + + + + + EOCIE + End of regular conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled. + 0x0 + + + B_0x1 + EOC interrupt enabled. An interrupt is generated when the EOC bit is set. + 0x1 + + + + + EOSIE + End of regular sequence of conversions interrupt enable +This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. An interrupt is generated when the EOS bit is set. + 0x1 + + + + + OVRIE + Overrun interrupt enable +This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. + 0x1 + + + + + JEOCIE + End of injected conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + JEOC interrupt disabled. + 0x0 + + + B_0x1 + JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. + 0x1 + + + + + JEOSIE + End of injected sequence of conversions interrupt enable +This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + JEOS interrupt disabled + 0x0 + + + B_0x1 + JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + Analog watchdog 1 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 1 interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Analog watchdog 2 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 2 interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Analog watchdog 3 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 3 interrupt enabled + 0x1 + + + + + JQOVFIE + Injected context queue overflow interrupt enable +This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + Injected Context Queue Overflow interrupt disabled + 0x0 + + + B_0x1 + Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set. + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x8 + 0x20 + 0x20000000 + 0xFFFFFFFF + + + ADEN + ADC enable control +This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. +It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. +Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command +This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). +It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). +Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) + 1 + 1 + read-write + + + B_0x0 + no ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. + 0x1 + + + + + ADSTART + ADC start of regular conversion +This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). +It is cleared by hardware: +in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. +in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. +Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) +In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) + 2 + 1 + read-write + + + B_0x0 + No ADC regular conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel. + 0x1 + + + + + JADSTART + ADC start of injected conversion +This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). +It is cleared by hardware: +in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. +in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. +Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). +In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) + 3 + 1 + read-write + + + B_0x0 + No ADC injected conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel. + 0x1 + + + + + ADSTP + ADC stop of regular conversion command +This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). +It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). +Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). +In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). + 4 + 1 + read-write + + + B_0x0 + No ADC stop regular conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + JADSTP + ADC stop of injected conversion command +This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). +It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). +Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) +In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) + 5 + 1 + read-write + + + B_0x0 + No ADC stop injected conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + ADVREGEN + ADC voltage regulator enable +This bits is set by software to enable the ADC voltage regulator. +Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. +For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). +The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 28 + 1 + read-write + + + B_0x0 + ADC Voltage regulator disabled + 0x0 + + + B_0x1 + ADC Voltage regulator enabled. + 0x1 + + + + + DEEPPWD + Deep-power-down enable +This bit is set and cleared by software to put the ADC in Deep-power-down mode. +Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 29 + 1 + read-write + + + B_0x0 + ADC not in Deep-power down + 0x0 + + + B_0x1 + ADC in Deep-power-down (default reset state) + 0x1 + + + + + ADCALDIF + Differential mode for calibration +This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. +Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 30 + 1 + read-write + + + B_0x0 + Writing ADCAL launches a calibration in Single-ended inputs mode. + 0x0 + + + B_0x1 + Writing ADCAL launches a calibration in Differential inputs mode. + 0x1 + + + + + ADCAL + ADC calibration +This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. +It is cleared by hardware after calibration is complete. +Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. +The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing) + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress. + 0x1 + + + + + + + ADC_CFGR + ADC_CFGR + ADC configuration register + 0xc + 0x20 + 0x80000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable +This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration +This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. +For more details, refer to +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + DMA One Shot mode selected + 0x0 + + + B_0x1 + DMA Circular mode selected + 0x1 + + + + + DFSDMCFG + DFSDM mode configuration +This bit is set and cleared by software to enable the DFSDM mode. It is effective only when +DMAEN = 0. +Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART =  0 and JADSTART =  0. + 2 + 1 + read-write + + + B_0x0 + DFSDM mode disabled + 0x0 + + + B_0x1 + DFSDM mode enabled + 0x1 + + + + + RES + Data resolution +These bits are written by software to select the resolution of the conversion. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 3 + 2 + read-write + + + B_0x0 + 12-bit + 0x0 + + + B_0x1 + 10-bit + 0x1 + + + B_0x2 + 8-bit + 0x2 + + + B_0x3 + 6-bit + 0x3 + + + + + EXTSEL0 + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 5 + 1 + read-write + + + EXTSEL1 + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 6 + 1 + read-write + + + EXTSEL2 + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 7 + 1 + read-write + + + EXTSEL3 + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 8 + 1 + read-write + + + EXTSEL4 + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 9 + 1 + read-write + + + EXTEN + External trigger enable and polarity selection for regular channels +These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 10 + 2 + read-write + + + OVRMOD + Overrun mode +This bit is set and cleared by software and configure the way data overrun is managed. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / Continuous conversion mode for regular conversions +This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. +Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. +The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + AUTDLY + Delayed conversion mode +This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + Auto-delayed conversion mode off + 0x0 + + + B_0x1 + Auto-delayed conversion mode on + 0x1 + + + + + ALIGN + Data alignment +This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + DISCEN + Discontinuous mode for regular channels +This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. +Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. +It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. +The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode for regular channels disabled + 0x0 + + + B_0x1 + Discontinuous mode for regular channels enabled + 0x1 + + + + + DISCNUM + Discontinuous mode channel count +These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 17 + 3 + read-write + + + B_0x0 + 1 channel + 0x0 + + + B_0x1 + 2 channels + 0x1 + + + B_0x7 + 8 channels + 0x7 + + + + + JDISCEN + Discontinuous mode on injected channels +This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). +It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. + 20 + 1 + read-write + + + B_0x0 + Discontinuous mode on injected channels disabled + 0x0 + + + B_0x1 + Discontinuous mode on injected channels enabled + 0x1 + + + + + JQM + JSQR queue mode +This bit is set and cleared by software. +It defines how an empty Queue is managed. +Refer to for more information. +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR. + 0x0 + + + B_0x1 + JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. + 0x1 + + + + + AWD1SGL + Enable the watchdog 1 on a single channel or on all channels +This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog 1 enable on regular channels +This bit is set and cleared by software +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on regular channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on regular channels + 0x1 + + + + + JAWD1EN + Analog watchdog 1 enable on injected channels +This bit is set and cleared by software +Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on injected channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on injected channels + 0x1 + + + + + JAUTO + Automatic injected group conversion +This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + Automatic injected group conversion disabled + 0x0 + + + B_0x1 + Automatic injected group conversion enabled + 0x1 + + + + + AWD1CH + Analog watchdog 1 channel selection +These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. +..... +others: reserved, must not be used +Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. +The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. +The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 26 + 5 + read-write + + + B_0x0 + ADC analog input channel 0 monitored by AWD1 + 0x0 + + + B_0x1 + ADC analog input channel 1 monitored by AWD1 + 0x1 + + + B_0x12 + ADC analog input channel 18 monitored by AWD1 + 0x12 + + + + + JQDIS + Injected Queue disable +These bits are set and cleared by software to disable the Injected Queue mechanism : +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). +A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. + 31 + 1 + read-write + + + B_0x0 + Injected Queue enabled + 0x0 + + + B_0x1 + Injected Queue disabled + 0x1 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ROVSE + Regular Oversampling Enable +This bit is set and cleared by software to enable regular oversampling. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) + 0 + 1 + read-write + + + B_0x0 + Regular Oversampling disabled + 0x0 + + + B_0x1 + Regular Oversampling enabled + 0x1 + + + + + JOVSE + Injected Oversampling Enable +This bit is set and cleared by software to enable injected oversampling. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) + 1 + 1 + read-write + + + B_0x0 + Injected Oversampling disabled + 0x0 + + + B_0x1 + Injected Oversampling enabled + 0x1 + + + + + OVSR + Oversampling ratio +This bitfield is set and cleared by software to define the oversampling ratio. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift +This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. +Other codes reserved +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TROVS + Triggered Regular Oversampling +This bit is set and cleared by software to enable triggered oversampling +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively following a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a new trigger + 0x1 + + + + + ROVSM + Regular Oversampling mode +This bit is set and cleared by software to select the regular oversampling mode. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) + 0x0 + + + B_0x1 + Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) + 0x1 + + + + + SWTRIG + Software trigger bit for sampling time control trigger mode +This bit is set and cleared by software to enable the bulb sampling mode. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + Software trigger starts the conversion for sampling time control trigger mode + 0x0 + + + B_0x1 + Software trigger starts the sampling for sampling time control trigger mode + 0x1 + + + + + BULB + Bulb sampling mode +This bit is set and cleared by software to enable the bulb sampling mode. +SAMPTRIG bit must not be set when the BULB bit is set. +The very first ADC conversion is performed with the sampling time specified in SMPx bits. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 26 + 1 + read-write + + + B_0x0 + Bulb sampling mode disabled + 0x0 + + + B_0x1 + Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion. + 0x1 + + + + + SMPTRIG + Sampling time control trigger mode +This bit is set and cleared by software to enable the sampling time control trigger mode. +The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. +EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. +When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 27 + 1 + read-write + + + B_0x0 + Sampling time control trigger mode disabled + 0x0 + + + B_0x1 + Sampling time control trigger mode enabled + 0x1 + + + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMP0 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 0 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP1 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 3 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP2 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 6 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP3 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 9 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP4 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 12 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP5 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 15 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP6 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 18 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP7 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 21 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP8 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 24 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP9 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 27 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMPPLUS + Addition of one clock cycle to the sampling time. +To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0. + 31 + 1 + read-write + + + B_0x1 + 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. + 0x1 + + + B_0x0 + The sampling time remains set to 2.5 ADC clock cycles remains + 0x0 + + + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMP10 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 0 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP11 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 3 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP12 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 6 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP13 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 9 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP14 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 12 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP15 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 15 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP16 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 18 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP17 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 21 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + SMP18 + Channel x sampling time selection +These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. + 24 + 3 + read-write + + + B_0x0 + 2.5 ADC clock cycles + 0x0 + + + B_0x1 + 6.5 ADC clock cycles + 0x1 + + + B_0x2 + 12.5 ADC clock cycles + 0x2 + + + B_0x3 + 24.5 ADC clock cycles + 0x3 + + + B_0x4 + 47.5 ADC clock cycles + 0x4 + + + B_0x5 + 92.5 ADC clock cycles + 0x5 + + + B_0x6 + 247.5 ADC clock cycles + 0x6 + + + B_0x7 + 640.5 ADC clock cycles + 0x7 + + + + + + + ADC_TR1 + ADC_TR1 + ADC watchdog threshold register 1 + 0x20 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog 1. +Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 12 + read-write + + + AWDFILT + Analog watchdog filtering parameter +This bit is set and cleared by software. +... +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 12 + 3 + read-write + + + B_0x0 + No filtering + 0x0 + + + B_0x1 + two consecutive detection generates an AWDx flag or an interrupt + 0x1 + + + B_0x7 + Eight consecutive detection generates an AWDx flag or an interrupt + 0x7 + + + + + HT1 + Analog watchdog 1 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog 1. +Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 16 + 12 + read-write + + + + + ADC_TR2 + ADC_TR2 + ADC watchdog threshold register 2 + 0x24 + 0x20 + 0x00FF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog 2. +Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 8 + read-write + + + HT2 + Analog watchdog 2 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog 2. +Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 16 + 8 + read-write + + + + + ADC_TR3 + ADC_TR3 + ADC watchdog threshold register 3 + 0x28 + 0x20 + 0x00FF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog 3. +This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 8 + read-write + + + HT3 + Analog watchdog 3 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog 3. +Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 16 + 8 + read-write + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L + Regular channel sequence length +These bits are written by software to define the total number of conversions in the regular channel conversion sequence. +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 0 + 4 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0xF + 16 conversions + 0xF + + + + + SQ1 + 1st conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 6 + 5 + read-write + + + SQ2 + 2nd conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 12 + 5 + read-write + + + SQ3 + 3rd conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 18 + 5 + read-write + + + SQ4 + 4th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 24 + 5 + read-write + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ5 + 5th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 0 + 5 + read-write + + + SQ6 + 6th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 6 + 5 + read-write + + + SQ7 + 7th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 12 + 5 + read-write + + + SQ8 + 8th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 18 + 5 + read-write + + + SQ9 + 9th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 24 + 5 + read-write + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ10 + 10th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 0 + 5 + read-write + + + SQ11 + 11th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 6 + 5 + read-write + + + SQ12 + 12th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 12 + 5 + read-write + + + SQ13 + 13th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 18 + 5 + read-write + + + SQ14 + 14th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 24 + 5 + read-write + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ15 + 15th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 0 + 5 + read-write + + + SQ16 + 16th conversion in regular sequence +These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence. +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 6 + 5 + read-write + + + + + ADC_DR + ADC_DR + ADC regular data register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDATA + Regular data converted +These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in . + 0 + 16 + read-only + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JL + Injected channel sequence length +These bits are written by software to define the total number of conversions in the injected channel conversion sequence. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 0 + 2 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0x2 + 3 conversions + 0x2 + + + B_0x3 + 4 conversions + 0x3 + + + + + JEXTSEL + External Trigger Selection for injected group +These bits select the external event used to trigger the start of conversion of an injected group: +... +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 2 + 5 + read-write + + + B_0x0 + adc_jext_trg0 + 0x0 + + + B_0x1 + adc_jext_trg1 + 0x1 + + + B_0x2 + adc_jext_trg2 + 0x2 + + + B_0x3 + adc_jext_trg3 + 0x3 + + + B_0x4 + adc_jext_trg4 + 0x4 + + + B_0x5 + adc_jext_trg5 + 0x5 + + + B_0x6 + adc_jext_trg6 + 0x6 + + + B_0x7 + adc_jext_trg7 + 0x7 + + + B_0x1F + adc_jext_trg31 + 0x1F + + + + + JEXTEN + External trigger enable and polarity selection for injected channels +These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). +If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions) + 7 + 2 + read-write + + + B_0x0 + If JQDIS = 0 (queue enabled), hardware and software trigger detection disabled. Otherwise, the queue is disabled as well as hardware trigger detection (conversions can be launched by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + JSQ1 + 1st conversion in the injected sequence +These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 9 + 5 + read-write + + + JSQ2 + 2nd conversion in the injected sequence +These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 15 + 5 + read-write + + + JSQ3 + 3rd conversion in the injected sequence +These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 21 + 5 + read-write + + + JSQ4 + 4th conversion in the injected sequence +These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence. +Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). + 27 + 5 + read-write + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset 1 register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] +These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. +Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. + 0 + 12 + read-write + + + OFFSETPOS + Positive offset +This bit is set and cleared by software to enable the positive offset. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable +This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y +These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the data offset y. +If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable +This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 31 + 1 + read-write + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset 2 register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] +These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. +Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. + 0 + 12 + read-write + + + OFFSETPOS + Positive offset +This bit is set and cleared by software to enable the positive offset. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable +This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y +These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the data offset y. +If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable +This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 31 + 1 + read-write + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset 3 register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] +These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. +Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. + 0 + 12 + read-write + + + OFFSETPOS + Positive offset +This bit is set and cleared by software to enable the positive offset. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable +This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y +These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the data offset y. +If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable +This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 31 + 1 + read-write + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset 4 register + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] +These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. +Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4. + 0 + 12 + read-write + + + OFFSETPOS + Positive offset +This bit is set and cleared by software to enable the positive offset. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable +This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y +These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. +Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the data offset y. +If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers. + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable +This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. +Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). + 31 + 1 + read-write + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected channel 1 data register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data +These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . + 0 + 16 + read-only + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected channel 2 data register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data +These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . + 0 + 16 + read-only + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected channel 3 data register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data +These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . + 0 + 16 + read-only + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected channel 4 data register + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data +These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in . + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC Analog Watchdog 2 Configuration Register + 0xa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD2CH + Analog watchdog 2 channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. +AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 +AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 +When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled +Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. +The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the analog watchdog. + 0 + 19 + read-write + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration Register + 0xa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD3CH + Analog watchdog 3 channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. +AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 +AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 +When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled +Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. +The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). +Some channels are not connected physically and must not be selected for the analog watchdog. + 0 + 19 + read-write + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC Differential mode Selection Register + 0xb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIFSEL + Differential mode for channels 18 to 0. +These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. +DIFSEL[i] = 0: ADC analog input channel is configured in Single-ended mode +DIFSEL[i] = 1: ADC analog input channel i is configured in Differential mode +Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). +The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 0 + 19 + read-write + + + + + ADC_CALFACT + ADC_CALFACT + ADC Calibration Factors + 0xb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALFACT_S + Calibration Factors In Single-ended mode +These bits are written by hardware or by software. +Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. +Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 0 + 7 + read-write + + + CALFACT_D + Calibration Factors in differential mode +These bits are written by hardware or by software. +Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. +Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 16 + 7 + read-write + + + + + ADC_OR + ADC_OR + ADC option register + 0xc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OP0 + VDDCORE channel enable + 0 + 1 + read-write + + + B_0x0 + VDDCORE channel disabled + 0x0 + + + B_0x1 + VDDCORE channel enabled + 0x1 + + + + + OP1 + VDDCPU channel enable + 1 + 1 + read-write + + + B_0x0 + VDDCPU channel disabled + 0x0 + + + B_0x1 + VDDCPU channel enabled + 0x1 + + + + + OP2 + VDDQ_DDR channel enable + 2 + 1 + read-write + + + B_0x0 + VDDQ_DDR channel disabled + 0x0 + + + B_0x1 + VDDQ_DDR channel enabled + 0x1 + + + + + + + ADC_CSR + ADC_CSR + ADC common status register + 0x300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDY_MST + Master ADC ready +This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. + 0 + 1 + read-only + + + EOSMP_MST + End of Sampling phase flag of the master ADC +This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. + 1 + 1 + read-only + + + EOC_MST + End of regular conversion of the master ADC +This bit is a copy of the EOC bit in the corresponding ADC_ISR register. + 2 + 1 + read-only + + + EOS_MST + End of regular sequence flag of the master ADC +This bit is a copy of the EOS bit in the corresponding ADC_ISR register. + 3 + 1 + read-only + + + OVR_MST + Overrun flag of the master ADC +This bit is a copy of the OVR bit in the corresponding ADC_ISR register. + 4 + 1 + read-only + + + JEOC_MST + End of injected conversion flag of the master ADC +This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. + 5 + 1 + read-only + + + JEOS_MST + End of injected sequence flag of the master ADC +This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. + 6 + 1 + read-only + + + AWD1_MST + Analog watchdog 1 flag of the master ADC +This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. + 7 + 1 + read-only + + + AWD2_MST + Analog watchdog 2 flag of the master ADC +This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. + 8 + 1 + read-only + + + AWD3_MST + Analog watchdog 3 flag of the master ADC +This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. + 9 + 1 + read-only + + + JQOVF_MST + Injected Context Queue Overflow flag of the master ADC +This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. + 10 + 1 + read-only + + + + + ADC_CCR + ADC_CCR + ADC common control register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKMODE + ADC clock mode +These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): +In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. +Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 16 + 2 + read-write + + + B_0x0 + adc_ker_ck (x = 1/2) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC)) + 0x0 + + + B_0x1 + adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register) and if the system clock has a 50% duty cycle. + 0x1 + + + B_0x2 + adc_hclk/2 (Synchronous clock mode) + 0x2 + + + B_0x3 + adc_hclk/4 (Synchronous clock mode) + 0x3 + + + + + PRESC + ADC prescaler +These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. +other: reserved +Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + VREFINT enable +This bit is set and cleared by software to enable/disable the VREFINT channel. + 22 + 1 + read-write + + + B_0x0 + VREFINT channel disabled + 0x0 + + + B_0x1 + VREFINT channel enabled + 0x1 + + + + + TSEN + VSENSE enable +This bit is set and cleared by software to control VSENSE. + 23 + 1 + read-write + + + B_0x0 + Temperature sensor channel disabled + 0x0 + + + B_0x1 + Temperature sensor channel enabled + 0x1 + + + + + VBATEN + VBAT enable +This bit is set and cleared by software to control. + 24 + 1 + read-write + + + B_0x0 + VBAT channel disabled + 0x0 + + + B_0x1 + VBAT channel enabled + 0x1 + + + + + + + ADC_HWCFGR0 + ADC_HWCFGR0 + ADC hardware configuration register + 0x3f0 + 0x20 + 0x00001411 + 0xFFFFFFFF + + + ADCNUM + Number of ADCs implemented + 0 + 4 + read-only + + + B_0x1 + One ADC instance implemented + 0x1 + + + B_0x2 + Two ADC instances implemented + 0x2 + + + B_0x3 + Three ADCs instances implemented + 0x3 + + + + + MULPIPE + Number of pipeline stages + 4 + 4 + read-only + + + B_0x1 + One-stage pipeline + 0x1 + + + + + OPBITS + Number of option bits + 8 + 4 + read-only + + + B_0x0 + No option register implemented + 0x0 + + + B_0x4 + 4 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8 + 0x4 + + + + + IDLEVALUE + Idle value for non-selected channels + 12 + 4 + read-only + + + B_0x0 + Dummy channel selection is 0x13 + 0x0 + + + B_0x1 + Dummy channel selection is 0x1F + 0x1 + + + + + + + ADC_VERR + ADC_VERR + ADC version register + 0x3f4 + 0x20 + 0x00000011 + 0xFFFFFFFF + + + MINREV + Minor revision +These bits returns the ADC IP minor revision + 0 + 4 + read-only + + + B_0x1 + Major revision = X.1 + 0x1 + + + + + MAJREV + Major revision +These bits returns the ADC IP major revision + 4 + 4 + read-only + + + B_0x1 + Major revision = 1.X + 0x1 + + + + + + + ADC_IPDR + ADC_IPDR + ADC identification register + 0x3f8 + 0x20 + 0x00110006 + 0xFFFFFFFF + + + ID + Peripheral identifier +These bits returns the ADC identifier. +ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1 + 0 + 32 + read-only + + + + + ADC_SIDR + ADC_SIDR + ADC size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size Identification +SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. +SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address: + 0 + 32 + read-only + + + B_0x1 + 1 Kbytes address offset + 0x1 + + + B_0x2 + 2 Kbytes address offset + 0x2 + + + B_0x4 + 4 Kbytes address offset + 0x4 + + + B_0x8 + 8 Kbytes address offset + 0x8 + + + + + + + + + ADC2 + 0x48004000 + + ADC2 + ADC2 global interrupt + 19 + + + + AXIMC + AXIMC + AXIMC + 0x57000000 + + 0x0 + 0x100000 + registers + + + + AXIMC_PERIPH_ID_4 + AXIMC_PERIPH_ID_4 + AXIMC peripheral ID4 register + 0x1fd0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + K4COUNT + register file size + 4 + 4 + read-only + + + + + AXIMC_PERIPH_ID_5 + AXIMC_PERIPH_ID_5 + AXIMC peripheral ID5 register + 0x1fd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PERIPH_ID_5 + reserved, not used. + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_6 + AXIMC_PERIPH_ID_6 + AXIMC peripheral ID6 register + 0x1fd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PERIPH_ID_6 + reserved, not used. + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_7 + AXIMC_PERIPH_ID_7 + AXIMC peripheral ID7 register + 0x1fdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PERIPH_ID_7 + reserved, not used. + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_0 + AXIMC_PERIPH_ID_0 + AXIMC peripheral ID0 register + 0x1fe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PERIPH_ID_0 + part number [7:0] + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_1 + AXIMC_PERIPH_ID_1 + AXIMC peripheral ID1 register + 0x1fe4 + 0x20 + 0x000000B4 + 0xFFFFFFFF + + + PERIPH_ID_1 + JEP106 identity [3:0], part number [11:8] + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_2 + AXIMC_PERIPH_ID_2 + AXIMC peripheral ID2 register + 0x1fe8 + 0x20 + 0x0000003B + 0xFFFFFFFF + + + PERIPH_ID_2 + part revision, JEP106 code flag, JEP106 identity [6:4] + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_3 + AXIMC_PERIPH_ID_3 + AXIMC peripheral ID3 register + 0x1fec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CUST_MOD_NUM + customer modification + 0 + 4 + read-only + + + B_0x0 + none + 0x0 + + + + + REV_AND + customer version + 4 + 4 + read-only + + + B_0x0 + none + 0x0 + + + + + + + AXIMC_COMP_ID_0 + AXIMC_COMP_ID_0 + AXIMC component ID0 register + 0x1ff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + preamble bits [7:0] + 0 + 8 + read-only + + + + + AXIMC_COMP_ID_1 + AXIMC_COMP_ID_1 + AXIMC component ID1 register + 0x1ff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + preamble bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common ID value + 0x0 + + + + + CLASS + Component class + 4 + 4 + read-only + + + B_0xF + generic IP component class + 0xF + + + + + + + AXIMC_COMP_ID_2 + AXIMC_COMP_ID_2 + AXIMC component ID2 register + 0x1ff8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + preamble bits [19:12] + 0 + 8 + read-only + + + + + AXIMC_COMP_ID_3 + AXIMC_COMP_ID_3 + AXIMC component ID3 register + 0x1ffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + preamble bits [27:20] + 0 + 8 + read-only + + + + + AXIMC_M0_FN_MOD2 + AXIMC_M0_FN_MOD2 + AXIMC master 0 packing functionality register + 0x42024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BYPASS_MERGE + Disable packing of beats to match the output data width +Unaligned transactions are not realigned to the input data word boundary. + 0 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + disable packing + 0x1 + + + + + + + AXIMC_M0_FN_MOD_AHB + AXIMC_M0_FN_MOD_AHB + AXIMC master 0 AHB conversion override functionality register + 0x42028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. + 0 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions to a series of single beat AXI transactions + 1 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + + + AXIMC_M0_READ_QOS + AXIMC_M0_READ_QOS + AXIMC master 0 read priority register + 0x42100 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M0_WRITE_QOS + AXIMC_M0_WRITE_QOS + AXIMC master 0 write priority register + 0x42104 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M0_FN_MOD + AXIMC_M0_FN_MOD + AXIMC master 0 issuing capability override functionality register + 0x42108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M1_FN_MOD2 + AXIMC_M1_FN_MOD2 + AXIMC master 1 packing functionality register + 0x43024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BYPASS_MERGE + Disable packing of beats to match the output data width +Unaligned transactions are not realigned to the input data word boundary. + 0 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + disable packing + 0x1 + + + + + + + AXIMC_M1_FN_MOD_AHB + AXIMC_M1_FN_MOD_AHB + AXIMC master 1 AHB conversion override functionality register + 0x43028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. + 0 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions to a series of single beat AXI transactions + 1 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + + + AXIMC_M1_READ_QOS + AXIMC_M1_READ_QOS + AXIMC master 1 read priority register + 0x43100 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M1_WRITE_QOS + AXIMC_M1_WRITE_QOS + AXIMC master 1 write priority register + 0x43104 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M1_FN_MOD + AXIMC_M1_FN_MOD + AXIMC master 1 issuing capability override functionality register + 0x43108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M2_FN_MOD2 + AXIMC_M2_FN_MOD2 + AXIMC master 2 packing functionality register + 0x44024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BYPASS_MERGE + Disable packing of beats to match the output data width +Unaligned transactions are not realigned to the input data word boundary. + 0 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + disable packing + 0x1 + + + + + + + AXIMC_M2_FN_MOD_AHB + AXIMC_M2_FN_MOD_AHB + AXIMC master 2 AHB conversion override functionality register + 0x44028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_INC_OVERRIDE + Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. + 0 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + WR_INC_OVERRIDE + Converts all AHB-Lite read transactions to a series of single beat AXI transactions + 1 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + + + AXIMC_M2_READ_QOS + AXIMC_M2_READ_QOS + AXIMC master 2 read priority register + 0x44100 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M2_WRITE_QOS + AXIMC_M2_WRITE_QOS + AXIMC master 2 write priority register + 0x44104 + 0x20 + 0x00000006 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M2_FN_MOD + AXIMC_M2_FN_MOD + AXIMC master 2 issuing capability override functionality register + 0x44108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M3_READ_QOS + AXIMC_M3_READ_QOS + AXIMC master 3 read priority register + 0x45100 + 0x20 + 0x00000007 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M3_WRITE_QOS + AXIMC_M3_WRITE_QOS + AXIMC master 3 write priority register + 0x45104 + 0x20 + 0x00000007 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M3_FN_MOD + AXIMC_M3_FN_MOD + AXIMC master 3 packing functionality register + 0x45108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M4_FN_MOD_LB + AXIMC_M4_FN_MOD_LB + AXIMC long burst capability inhibition register + 0x4602c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FN_MOD_LB + controls burst breaking of long bursts + 0 + 1 + read-write + + + B_0x0 + long bursts can not be generated at the output of the ASIB + 0x0 + + + B_0x1 + long bursts can be generated at the output of the ASIB + 0x1 + + + + + + + AXIMC_M4_READ_QOS + AXIMC_M4_READ_QOS + AXIMC master 4 read priority register + 0x46100 + 0x20 + 0x00000007 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M4_WRITE_QOS + AXIMC_M4_WRITE_QOS + AXIMC master 4 write priority register + 0x46104 + 0x20 + 0x00000007 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M4_FN_MOD + AXIMC_M4_FN_MOD + AXIMC master 4 packing functionality register + 0x46108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M5_FN_MOD2 + AXIMC_M5_FN_MOD2 + AXIMC master 5 packing functionality register + 0x47024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BYPASS_MERGE + Disable packing of beats to match the output data width +Unaligned transactions are not realigned to the input data word boundary. + 0 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + disable packing + 0x1 + + + + + + + AXIMC_M5_FN_MOD_AHB + AXIMC_M5_FN_MOD_AHB + AXIMC master 5 AHB conversion override functionality register + 0x47028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_INC_OVERRIDE + converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. + 0 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + WR_INC_OVERRIDE + converts all AHB-Lite read transactions to a series of single beat AXI transactions + 1 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + + + AXIMC_M5_READ_QOS + AXIMC_M5_READ_QOS + AXIMC master 5 read priority register + 0x47100 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M5_WRITE_QOS + AXIMC_M5_WRITE_QOS + AXIMC master 5 write priority register + 0x47104 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M5_FN_MOD + AXIMC_M5_FN_MOD + AXIMC master 5 issuing capability override functionality register + 0x47108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M6_FN_MOD2 + AXIMC_M6_FN_MOD2 + AXIMC master 6 packing functionality register + 0x48024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BYPASS_MERGE + Disable packing of beats to match the output data width +Unaligned transactions are not realigned to the input data word boundary. + 0 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + disable packing + 0x1 + + + + + + + AXIMC_M6_FN_MOD_AHB + AXIMC_M6_FN_MOD_AHB + AXIMC master 6 AHB conversion override functionality register + 0x48028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_INC_OVERRIDE + converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. + 0 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + WR_INC_OVERRIDE + converts all AHB-Lite read transactions to a series of single beat AXI transactions + 1 + 1 + read-write + + + B_0x0 + override disabled + 0x0 + + + B_0x1 + override enabled + 0x1 + + + + + + + AXIMC_M6_READ_QOS + AXIMC_M6_READ_QOS + AXIMC master 6 read priority register + 0x48100 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M6_WRITE_QOS + AXIMC_M6_WRITE_QOS + AXIMC master 6 write priority register + 0x48104 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M6_FN_MOD + AXIMC_M6_FN_MOD + AXIMC master 6 issuing capability override functionality register + 0x48108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M7_READ_QOS + AXIMC_M7_READ_QOS + AXIMC master 7 read priority register + 0x49100 + 0x20 + 0x00000008 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M7_WRITE_QOS + AXIMC_M7_WRITE_QOS + AXIMC master 7 write priority register + 0x49104 + 0x20 + 0x00000008 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M7_FN_MOD + AXIMC_M7_FN_MOD + AXIMC master 7 issuing capability override functionality register + 0x49108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M8_READ_QOS + AXIMC_M8_READ_QOS + AXIMC master 8 read priority register + 0x4a100 + 0x20 + 0x00000008 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M8_WRITE_QOS + AXIMC_M8_WRITE_QOS + AXIMC master 8 write priority register + 0x4a104 + 0x20 + 0x00000008 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M8_FN_MOD + AXIMC_M8_FN_MOD + AXIMC master 8 issuing capability override functionality register + 0x4a108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M9_READ_QOS + AXIMC_M9_READ_QOS + AXIMC master 9 read priority register + 0x4b100 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M9_WRITE_QOS + AXIMC_M9_WRITE_QOS + AXIMC master 9 write priority register + 0x4b104 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M9_FN_MOD + AXIMC_M9_FN_MOD + AXIMC master 9 issuing capability override functionality register + 0x4b108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M10_READ_QOS + AXIMC_M10_READ_QOS + AXIMC master 10 read priority register + 0x4c100 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M10_WRITE_QOS + AXIMC_M10_WRITE_QOS + AXIMC master 10 write priority register + 0x4c104 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M10_FN_MOD + AXIMC_M10_FN_MOD + AXIMC master 10 issuing capability override functionality register + 0x4c108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + AXIMC_M11_READ_QOS + AXIMC_M11_READ_QOS + AXIMC master 11 read priority register + 0x4d100 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AR_QOS + read channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M11_WRITE_QOS + AXIMC_M11_WRITE_QOS + AXIMC master 11 write priority register + 0x4d104 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + AW_QOS + write channel QoS setting + 0 + 4 + read-write + + + B_0x0 + lowest priority + 0x0 + + + B_0xF + highest priority + 0xF + + + + + + + AXIMC_M11_FN_MOD + AXIMC_M11_FN_MOD + AXIMC master 11 issuing capability override functionality register + 0x4d108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READ_ISS_OVERRIDE + override AMIB read issuing capability + 0 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + WRITE_ISS_OVERRIDE + override AMIB write issuing capability + 1 + 1 + read-write + + + B_0x0 + normal issuing capability + 0x0 + + + B_0x1 + force issuing capability to 1 + 0x1 + + + + + + + + + BSEC + BSEC + BSEC + 0x5C005000 + + 0x0 + 0x1000 + registers + + + + BSEC_OTP_CONFIG + BSEC_OTP_CONFIG + BSEC OTP configuration register + 0x0 + 0x20 + 0x0000000E + 0xFFFFFFFF + + + PWRUP + OTP power-up control +Note: After the power-on initial read of OTP, BSEC powers down OTP. PWRUP bit is then cleared. +Prior to any read or programming operation, OTP must be powered up again by setting PWRUP bit. +OTP read is qualified by pwrok input signal, which indicates that VDD and VDD1 supplies are in valid range. + 0 + 1 + read-write + + + B_0x0 + OTP powered down + 0x0 + + + B_0x1 + OTP powered up + 0x1 + + + + + FRC + OTP clock frequency range selection +Note: 0b11 is used by default. OTP initial read is always using an internal OSC with 64 MHz max frequency. Reading OTP at a lower frequency than the range programmed by FRC[1:0] is possible. + 1 + 2 + read-write + + + B_0x0 + 10 MHz ≤ frequency ≤ 20 MHz + 0x0 + + + B_0x1 + 20 MHz ≤ frequency ≤ 30 MHz + 0x1 + + + B_0x2 + 30 MHz ≤ frequency ≤ 45 MHz + 0x2 + + + B_0x3 + 45 MHz ≤ frequency ≤ 67 MHz + 0x3 + + + + + PRGWIDTH + OTP programming pulse width (default = 0b0001) + 3 + 4 + read-write + + + TREAD + set OTP reading current level (default = 0b00) + 7 + 2 + read-write + + + + + BSEC_OTP_CONTROL + BSEC_OTP_CONTROL + BSEC OTP control register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR + OTP word address +Actual OTP word address. +Words address are from 0 to 95 for BSEC +Note: the actual OTP word address is adjusted according to the redundancy or ECC scheme. + 0 + 7 + read-write + + + PROG + OTP operation control + 8 + 1 + read-write + + + B_0x0 + OTP read operation + 0x0 + + + B_0x1 + OTP program operation + 0x1 + + + + + LOCK + OTP permanent word lock control + 9 + 1 + read-write + + + B_0x0 + OTP normal word programing + 0x0 + + + B_0x1 + OTP permanent write lock word programming + 0x1 + + + + + + + BSEC_OTP_WRDATA + BSEC_OTP_WRDATA + BSEC OTP write data register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WRDATA + OTP write data + 0 + 32 + read-write + + + + + BSEC_OTP_STATUS + BSEC_OTP_STATUS + BSEC OTP status register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SECURE + OTP secured mode + 0 + 1 + read-only + + + B_0x0 + OTP mode is not OTP-SECURED + 0x0 + + + B_0x1 + OTP mode is OTP-SECURED + 0x1 + + + + + INVALID + OTP invalid mode + 2 + 1 + read-only + + + B_0x0 + OTP mode is not OTP-INVALID + 0x0 + + + B_0x1 + OTP mode is OTP-INVALID + 0x1 + + + + + BUSY + OTP operation status +Note: bit polling is used to determine operation completion. + 3 + 1 + read-only + + + B_0x0 + OTP idle + 0x0 + + + B_0x1 + OTP operation on going + 0x1 + + + + + PROGFAIL + last programming status + 4 + 1 + read-only + + + B_0x0 + OTP successful last programming + 0x0 + + + B_0x1 + OTP failed last programming + 0x1 + + + + + PWRON + OTP power status +Note: used to poll pwrok signal value + 5 + 1 + read-only + + + B_0x0 + OTP in power off + 0x0 + + + B_0x1 + OTP in power on + 0x1 + + + + + CLOSED + OTP_SECURED mode + 8 + 1 + read-only + + + B_0x0 + OTP-SECURED open device + 0x0 + + + B_0x1 + OTP-SECURED closed device + 0x1 + + + + + BSCANDIS + Boundary Scan status + 9 + 1 + read-only + + + B_0x0 + Boundary Scan is not disabled + 0x0 + + + B_0x1 + Boundary Scan is disabled + 0x1 + + + + + JTAGDIS + JTAG port status + 10 + 1 + read-only + + + B_0x0 + JTAG Port is not disabled + 0x0 + + + B_0x1 + JTAG Port is disabled except for accessing REV_ID information (see “Device electronic signature” section) and BSEC_JTAGIN register. + 0x1 + + + + + + + BSEC_OTP_LOCK + BSEC_OTP_LOCK + BSEC OTP lock configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OTP + upper OTP read lock + 0 + 1 + read-write + + + B_0x0 + upper OTP not locked + 0x0 + + + B_0x1 + upper OTP cannot be reloaded until next system reset + 0x1 + + + + + ROMLOCK + Upper ROM region read lock +The upper ROM region is accessible only in OTP-SECURED open and OTP-SECURED closed modes and ROMLOCK bit is relevant only in these modes. + 1 + 1 + read-write + + + B_0x0 + Upper ROM region is accessible + 0x0 + + + B_0x1 + Upper ROM region is no more accessible until next system reset + 0x1 + + + + + DENREG + debug enable register sticky lock + 2 + 1 + read-write + + + B_0x0 + BSEC_DENABLE register not locked + 0x0 + + + B_0x1 + BSEC_DENABLE register locked until next system reset + 0x1 + + + + + GPLOCK + programming sticky lock + 4 + 1 + read-write + + + B_0x0 + programming allowed + 0x0 + + + B_0x1 + programming disabled until next system reset + 0x1 + + + + + + + BSEC_DENABLE + BSEC_DENABLE + BSEC debug configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBGEN + debug enable with signal dbgen + 1 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + NIDEN + non-invasive debug enable with signal niden + 2 + 1 + read-write + + + B_0x0 + non-invasive debug disabled + 0x0 + + + B_0x1 + non-invasive debug enabled + 0x1 + + + + + DEVICEEN + controls access to debug component via external debug port by signal deviceen + 3 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + HDPEN + hardware debug port enable with signal hdpen + 4 + 1 + read-write + + + B_0x0 + hardware debug port disabled + 0x0 + + + B_0x1 + hardware debug port enabled + 0x1 + + + + + SPIDEN + secure privilege invasive debug enable with signal spniden + 5 + 1 + read-write + + + B_0x0 + secure privilege invasive debug disabled + 0x0 + + + B_0x1 + secure privilege invasive debug enabled + 0x1 + + + + + SPNIDEN + secure privilege non-invasive debug enable with signal spiden + 6 + 1 + read-write + + + B_0x0 + secure privilege non-invasive debug disabled + 0x0 + + + B_0x1 + secure privilege non-invasive debug enabled + 0x1 + + + + + CP15SDISABLE + write access to some secure Cortex®-A7 CP15 registers disable + 7 + 1 + read-write + + + B_0x0 + All CP15 registers are accessible + 0x0 + + + B_0x1 + Disable write access to some secure CP15 registers into Cortex®-A7 corresponding CPU + 0x1 + + + + + CFGSDISABLE + write access to secure GIC registers disable with signal cfgsdisable + 9 + 1 + read-write + + + B_0x0 + no effect, all GIC registers are accessible + 0x0 + + + B_0x1 + Disable write access to some secure GIC registers + 0x1 + + + + + DBGSWENABLE + control self hosted debug enable with signal dbgswenable + 10 + 1 + read-write + + + B_0x0 + Software access to all debug components is disabled + 0x0 + + + B_0x1 + Software access to all debug components is enabled + 0x1 + + + + + + + BSEC_OTP_DISTURBED0 + BSEC_OTP_DISTURBED0 + BSEC OTP disturbed status register 0 + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS + disturbed status of the corresponding OTP word +Note: ECC bits resilience against hardware attacks is applied only to lower OTP region. + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is disturbed, either because of a read with disturbcheck failed or because the spare ECC bits [37:32] for words 0 to 31 do not match expected value. It may result from a possible hardware attack. + 0x1 + + + + + + + BSEC_OTP_DISTURBED1 + BSEC_OTP_DISTURBED1 + BSEC OTP disturbed status register 1 + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS + disturbed status of the corresponding OTP word +Note: ECC bits resilience against hardware attacks is applied only to lower OTP region. + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is disturbed, either because of a read with disturbcheck failed or because the spare ECC bits [37:32] for words 0 to 31 do not match expected value. It may result from a possible hardware attack. + 0x1 + + + + + + + BSEC_OTP_DISTURBED2 + BSEC_OTP_DISTURBED2 + BSEC OTP disturbed status register 2 + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS + disturbed status of the corresponding OTP word +Note: ECC bits resilience against hardware attacks is applied only to lower OTP region. + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is disturbed, either because of a read with disturbcheck failed or because the spare ECC bits [37:32] for words 0 to 31 do not match expected value. It may result from a possible hardware attack. + 0x1 + + + + + + + BSEC_OTP_ERROR0 + BSEC_OTP_ERROR0 + BSEC OTP error status register 0 + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ERR + error status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is erroneous, either because 2:1 redundancy has failed for words 0 to 31 or because ECC check has failed for words 32 to 95. + 0x1 + + + + + + + BSEC_OTP_ERROR1 + BSEC_OTP_ERROR1 + BSEC OTP error status register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ERR + error status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is erroneous, either because 2:1 redundancy has failed for words 0 to 31 or because ECC check has failed for words 32 to 95. + 0x1 + + + + + + + BSEC_OTP_ERROR2 + BSEC_OTP_ERROR2 + BSEC OTP error status register 2 + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ERR + error status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word has been read correctly + 0x0 + + + B_0x1 + OTP word is erroneous, either because 2:1 redundancy has failed for words 0 to 31 or because ECC check has failed for words 32 to 95. + 0x1 + + + + + + + BSEC_OTP_WRLOCK0 + BSEC_OTP_WRLOCK0 + BSEC OTP lock status register 0 + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WRLOCK + permanent word lock status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word permanently locked + 0x1 + + + + + + + BSEC_OTP_WRLOCK1 + BSEC_OTP_WRLOCK1 + BSEC OTP lock status register 1 + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WRLOCK + permanent word lock status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word permanently locked + 0x1 + + + + + + + BSEC_OTP_WRLOCK2 + BSEC_OTP_WRLOCK2 + BSEC OTP lock status register 2 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WRLOCK + permanent word lock status of the correspond OTP word + 0 + 32 + read-only + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word permanently locked + 0x1 + + + + + + + BSEC_OTP_SPLOCK0 + BSEC_OTP_SPLOCK0 + BSEC OTP sticky programming lock register 0 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPLOCK + lock programming for the OTP word until next power-on reset + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked for programming + 0x1 + + + + + + + BSEC_OTP_SPLOCK1 + BSEC_OTP_SPLOCK1 + BSEC OTP sticky programming lock register 1 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPLOCK + lock programming for the OTP word until next power-on reset + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked for programming + 0x1 + + + + + + + BSEC_OTP_SPLOCK2 + BSEC_OTP_SPLOCK2 + BSEC OTP sticky programming lock register 2 + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPLOCK + lock programming for the OTP word until next power-on reset + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked for programming + 0x1 + + + + + + + BSEC_OTP_SWLOCK0 + BSEC_OTP_SWLOCK0 + BSEC OTP shadow write sticky lock register 0 + 0x7c + 0x20 + 0x00000001 + 0xFFFFFFFF + + + SWLOCK + lock the writing for the OTP shadow word until next power-on reset. +Note: BSEC_OTP_SWLOCK0 bit 0 is forced to 1 by hardware, writing to this bit has no effect. + 0 + 32 + read-write + + + B_0x0 + shadow word not locked + 0x0 + + + B_0x1 + shadow word locked and cannot be written by software + 0x1 + + + + + + + BSEC_OTP_SWLOCK1 + BSEC_OTP_SWLOCK1 + BSEC OTP shadow write sticky lock register 1 + 0x80 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + SWLOCK + lock the writing for the OTP shadow word until next power-on reset. +Note: BSEC_OTP_SWLOCK0 bit 0 is forced to 1 by hardware, writing to this bit has no effect. + 0 + 32 + read-write + + + B_0x0 + shadow word not locked + 0x0 + + + B_0x1 + shadow word locked and cannot be written by software + 0x1 + + + + + + + BSEC_OTP_SWLOCK2 + BSEC_OTP_SWLOCK2 + BSEC OTP shadow write sticky lock register 2 + 0x84 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + SWLOCK + lock the writing for the OTP shadow word until next power-on reset. +Note: BSEC_OTP_SWLOCK0 bit 0 is forced to 1 by hardware, writing to this bit has no effect. + 0 + 32 + read-write + + + B_0x0 + shadow word not locked + 0x0 + + + B_0x1 + shadow word locked and cannot be written by software + 0x1 + + + + + + + BSEC_OTP_SRLOCK0 + BSEC_OTP_SRLOCK0 + BSEC OTP shadow read sticky lock register 0 + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + SRLOCK + prevent reloading of the shadow word from OTP until next power-on reset. +Note: Reloading of OTP word 0 is prevented after its initial read on a system reset. + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked and cannot be reloaded + 0x1 + + + + + + + BSEC_OTP_SRLOCK1 + BSEC_OTP_SRLOCK1 + BSEC OTP shadow read sticky lock register 1 + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + SRLOCK + prevent reloading of the shadow word from OTP until next power-on reset. +Note: Reloading of OTP word 0 is prevented after its initial read on a system reset. + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked and cannot be reloaded + 0x1 + + + + + + + BSEC_OTP_SRLOCK2 + BSEC_OTP_SRLOCK2 + BSEC OTP shadow read sticky lock register 2 + 0x9c + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + SRLOCK + prevent reloading of the shadow word from OTP until next power-on reset. +Note: Reloading of OTP word 0 is prevented after its initial read on a system reset. + 0 + 32 + read-write + + + B_0x0 + OTP word not locked + 0x0 + + + B_0x1 + OTP word locked and cannot be reloaded + 0x1 + + + + + + + BSEC_JTAGIN + BSEC_JTAGIN + BSEC JTAG input register + 0xac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + JTAG input data +32-bit copy from JTAG SoC register + 0 + 32 + read-only + + + + + BSEC_JTAGOUT + BSEC_JTAGOUT + BSEC JTAG output register + 0xb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + JTAG output data +32-bit copy to JTAG SoC register + 0 + 32 + read-only + + + + + BSEC_SCRATCH + BSEC_SCRATCH + BSEC scratch register + 0xb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + scratch data +This register is a general purpose register. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA0 + BSEC_OTP_DATA0 + BSEC shadow register 0 + 0x200 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA1 + BSEC_OTP_DATA1 + BSEC shadow register 1 + 0x204 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA2 + BSEC_OTP_DATA2 + BSEC shadow register 2 + 0x208 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA3 + BSEC_OTP_DATA3 + BSEC shadow register 3 + 0x20c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA4 + BSEC_OTP_DATA4 + BSEC shadow register 4 + 0x210 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA5 + BSEC_OTP_DATA5 + BSEC shadow register 5 + 0x214 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA6 + BSEC_OTP_DATA6 + BSEC shadow register 6 + 0x218 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA7 + BSEC_OTP_DATA7 + BSEC shadow register 7 + 0x21c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA8 + BSEC_OTP_DATA8 + BSEC shadow register 8 + 0x220 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA9 + BSEC_OTP_DATA9 + BSEC shadow register 9 + 0x224 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA10 + BSEC_OTP_DATA10 + BSEC shadow register 10 + 0x228 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA11 + BSEC_OTP_DATA11 + BSEC shadow register 11 + 0x22c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA12 + BSEC_OTP_DATA12 + BSEC shadow register 12 + 0x230 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA13 + BSEC_OTP_DATA13 + BSEC shadow register 13 + 0x234 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA14 + BSEC_OTP_DATA14 + BSEC shadow register 14 + 0x238 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA15 + BSEC_OTP_DATA15 + BSEC shadow register 15 + 0x23c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA16 + BSEC_OTP_DATA16 + BSEC shadow register 16 + 0x240 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA17 + BSEC_OTP_DATA17 + BSEC shadow register 17 + 0x244 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA18 + BSEC_OTP_DATA18 + BSEC shadow register 18 + 0x248 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA19 + BSEC_OTP_DATA19 + BSEC shadow register 19 + 0x24c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA20 + BSEC_OTP_DATA20 + BSEC shadow register 20 + 0x250 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA21 + BSEC_OTP_DATA21 + BSEC shadow register 21 + 0x254 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA22 + BSEC_OTP_DATA22 + BSEC shadow register 22 + 0x258 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA23 + BSEC_OTP_DATA23 + BSEC shadow register 23 + 0x25c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA24 + BSEC_OTP_DATA24 + BSEC shadow register 24 + 0x260 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA25 + BSEC_OTP_DATA25 + BSEC shadow register 25 + 0x264 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA26 + BSEC_OTP_DATA26 + BSEC shadow register 26 + 0x268 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA27 + BSEC_OTP_DATA27 + BSEC shadow register 27 + 0x26c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA28 + BSEC_OTP_DATA28 + BSEC shadow register 28 + 0x270 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA29 + BSEC_OTP_DATA29 + BSEC shadow register 29 + 0x274 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA30 + BSEC_OTP_DATA30 + BSEC shadow register 30 + 0x278 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA31 + BSEC_OTP_DATA31 + BSEC shadow register 31 + 0x27c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA32 + BSEC_OTP_DATA32 + BSEC shadow register 32 + 0x280 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA33 + BSEC_OTP_DATA33 + BSEC shadow register 33 + 0x284 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA34 + BSEC_OTP_DATA34 + BSEC shadow register 34 + 0x288 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA35 + BSEC_OTP_DATA35 + BSEC shadow register 35 + 0x28c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA36 + BSEC_OTP_DATA36 + BSEC shadow register 36 + 0x290 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA37 + BSEC_OTP_DATA37 + BSEC shadow register 37 + 0x294 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA38 + BSEC_OTP_DATA38 + BSEC shadow register 38 + 0x298 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA39 + BSEC_OTP_DATA39 + BSEC shadow register 39 + 0x29c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA40 + BSEC_OTP_DATA40 + BSEC shadow register 40 + 0x2a0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA41 + BSEC_OTP_DATA41 + BSEC shadow register 41 + 0x2a4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA42 + BSEC_OTP_DATA42 + BSEC shadow register 42 + 0x2a8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA43 + BSEC_OTP_DATA43 + BSEC shadow register 43 + 0x2ac + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA44 + BSEC_OTP_DATA44 + BSEC shadow register 44 + 0x2b0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA45 + BSEC_OTP_DATA45 + BSEC shadow register 45 + 0x2b4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA46 + BSEC_OTP_DATA46 + BSEC shadow register 46 + 0x2b8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA47 + BSEC_OTP_DATA47 + BSEC shadow register 47 + 0x2bc + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA48 + BSEC_OTP_DATA48 + BSEC shadow register 48 + 0x2c0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA49 + BSEC_OTP_DATA49 + BSEC shadow register 49 + 0x2c4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA50 + BSEC_OTP_DATA50 + BSEC shadow register 50 + 0x2c8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA51 + BSEC_OTP_DATA51 + BSEC shadow register 51 + 0x2cc + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA52 + BSEC_OTP_DATA52 + BSEC shadow register 52 + 0x2d0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA53 + BSEC_OTP_DATA53 + BSEC shadow register 53 + 0x2d4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA54 + BSEC_OTP_DATA54 + BSEC shadow register 54 + 0x2d8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA55 + BSEC_OTP_DATA55 + BSEC shadow register 55 + 0x2dc + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA56 + BSEC_OTP_DATA56 + BSEC shadow register 56 + 0x2e0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA57 + BSEC_OTP_DATA57 + BSEC shadow register 57 + 0x2e4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA58 + BSEC_OTP_DATA58 + BSEC shadow register 58 + 0x2e8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA59 + BSEC_OTP_DATA59 + BSEC shadow register 59 + 0x2ec + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA60 + BSEC_OTP_DATA60 + BSEC shadow register 60 + 0x2f0 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA61 + BSEC_OTP_DATA61 + BSEC shadow register 61 + 0x2f4 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA62 + BSEC_OTP_DATA62 + BSEC shadow register 62 + 0x2f8 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA63 + BSEC_OTP_DATA63 + BSEC shadow register 63 + 0x2fc + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA64 + BSEC_OTP_DATA64 + BSEC shadow register 64 + 0x300 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA65 + BSEC_OTP_DATA65 + BSEC shadow register 65 + 0x304 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA66 + BSEC_OTP_DATA66 + BSEC shadow register 66 + 0x308 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA67 + BSEC_OTP_DATA67 + BSEC shadow register 67 + 0x30c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA68 + BSEC_OTP_DATA68 + BSEC shadow register 68 + 0x310 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA69 + BSEC_OTP_DATA69 + BSEC shadow register 69 + 0x314 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA70 + BSEC_OTP_DATA70 + BSEC shadow register 70 + 0x318 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA71 + BSEC_OTP_DATA71 + BSEC shadow register 71 + 0x31c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA72 + BSEC_OTP_DATA72 + BSEC shadow register 72 + 0x320 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA73 + BSEC_OTP_DATA73 + BSEC shadow register 73 + 0x324 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA74 + BSEC_OTP_DATA74 + BSEC shadow register 74 + 0x328 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA75 + BSEC_OTP_DATA75 + BSEC shadow register 75 + 0x32c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA76 + BSEC_OTP_DATA76 + BSEC shadow register 76 + 0x330 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA77 + BSEC_OTP_DATA77 + BSEC shadow register 77 + 0x334 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA78 + BSEC_OTP_DATA78 + BSEC shadow register 78 + 0x338 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA79 + BSEC_OTP_DATA79 + BSEC shadow register 79 + 0x33c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA80 + BSEC_OTP_DATA80 + BSEC shadow register 80 + 0x340 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA81 + BSEC_OTP_DATA81 + BSEC shadow register 81 + 0x344 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA82 + BSEC_OTP_DATA82 + BSEC shadow register 82 + 0x348 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA83 + BSEC_OTP_DATA83 + BSEC shadow register 83 + 0x34c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA84 + BSEC_OTP_DATA84 + BSEC shadow register 84 + 0x350 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA85 + BSEC_OTP_DATA85 + BSEC shadow register 85 + 0x354 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA86 + BSEC_OTP_DATA86 + BSEC shadow register 86 + 0x358 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA87 + BSEC_OTP_DATA87 + BSEC shadow register 87 + 0x35c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA88 + BSEC_OTP_DATA88 + BSEC shadow register 88 + 0x360 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA89 + BSEC_OTP_DATA89 + BSEC shadow register 89 + 0x364 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA90 + BSEC_OTP_DATA90 + BSEC shadow register 90 + 0x368 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA91 + BSEC_OTP_DATA91 + BSEC shadow register 91 + 0x36c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA92 + BSEC_OTP_DATA92 + BSEC shadow register 92 + 0x370 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA93 + BSEC_OTP_DATA93 + BSEC shadow register 93 + 0x374 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA94 + BSEC_OTP_DATA94 + BSEC shadow register 94 + 0x378 + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_OTP_DATA95 + BSEC_OTP_DATA95 + BSEC shadow register 95 + 0x37c + 0x20 + 0x00000000 + 0x00000000 + + + DATA + shadow register read from OTP or written by software (OTP emulation mode) +The update of shadow registers is controlled by other registers and by OTP security mode. + 0 + 32 + read-write + + + + + BSEC_HWCFGR + BSEC_HWCFGR + BSEC hardware configuration register + 0xff0 + 0x20 + 0x00000014 + 0xFFFFFFFF + + + SIZE + OTP block size +Others: reserved + 0 + 4 + read-only + + + B_0x2 + 2 Kbits + 0x2 + + + B_0x4 + 4 Kbits + 0x4 + + + B_0x8 + 8 Kbits + 0x8 + + + + + ECC_USE + protection / redundancy scheme used +Others: reserved + 4 + 4 + read-only + + + B_0x0 + No + 0x0 + + + B_0x1 + ECC for upper OTP bits used + 0x1 + + + + + + + BSEC_VERR + BSEC_VERR + BSEC version register + 0xff4 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + MINREV + minor revision information + 0 + 4 + read-only + + + MAJREV + major revision information + 4 + 4 + read-only + + + + + BSEC_IPIDR + BSEC_IPIDR + BSEC identification register + 0xff8 + 0x20 + 0x00100032 + 0xFFFFFFFF + + + ID + BSEC identification + 0 + 32 + read-only + + + + + BSEC_SIDR + BSEC_SIDR + BSEC size identification register + 0xffc + 0x20 + 0xA3C5DD04 + 0xFFFFFFFF + + + SID + BSEC size identification + 0 + 32 + read-only + + + + + + + CCU + CCU + CCU + 0x44010000 + + 0x0 + 0x400 + registers + + + FDCAN_CAL + FDCAN CCU interrupt + 64 + + + + CCU_CREL + CCU_CREL + Clock calibration unit core release register + 0x0 + 0x20 + 0x11141218 + 0xFFFFFFFF + + + DAY + Timestamp day = 18 + 0 + 8 + read-only + + + MON + Timestamp month = 12 + 8 + 8 + read-only + + + YEAR + Timestamp year = + 16 + 4 + read-only + + + SUBSTEP + Sub-step of core release = 1 + 20 + 4 + read-only + + + STEP + Step of core release = 1 + 24 + 4 + read-only + + + REL + Core release = 1 + 28 + 4 + read-only + + + + + CCU_CCFG + CCU_CCFG + Calibration configuration register + 0x4 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + TQBT + Time quanta per bit time +Configures the number of time quanta per bit time. Same value as configured in FDCAN modules. The range of the resulting time quanta clock fdcan_tq_ck is from 0.5 MHz (bitrate of 125 kbit/s with 4 tq per bit time) to 25 MHz (bitrate of 1 Mbit/s with 25 tq per bit time). Valid values are 4 to 25. Configured values below 4 are interpreted as 4, values above 25 are interpreted as 25. +Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 0 + 5 + read-write + + + BCC + Bypass clock calibration +If this bit is set, the clock input fdcan_ker_ck is routed to the time quanta clock through a clock divider configurable via CDIV, cu_cok is always 1. In this case the baudrate prescaler of the connected FDCANs has to be configured to generate the FDCAN internal time quanta clock. + 6 + 1 + read-write + + + B_0x0 + Clock calibration unit generates time quanta clock + 0x0 + + + B_0x1 + Clock calibration unit bypassed (default configuration) + 0x1 + + + + + CFL + Calibration field length +Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 7 + 1 + read-write + + + B_0x0 + Calibration field length is 32 bits + 0x0 + + + B_0x1 + Calibration field length is 64 bits + 0x1 + + + + + OCPM + Oscillator clock periods minimum +Configures the minimum number of periods in two CAN bit times. OCPM is used in basic calibration to avoid false measurements in case of glitches on the bus line. The configured number of periods is OCPM × 32. The configuration depends on the frequency and the bitrate configured in FDCAN modules (from 125 kbit/s up to 1 Mbit/s). It is recommended to configure a value slightly below two CAN bit times. The reset value is 1.6 bit times at 80 MHz fdcan_ker_ck and 1 Mbit/s CAN bitrate. +Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 8 + 8 + read-write + + + CDIV + Clock divider +The clock divider has to be configured when the clock calibration is bypassed (BCC = 1) to ensure that the FDCAN requirement is fulfilled. +Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 16 + 4 + read-write + + + B_0x0 + Divide by 1 + 0x0 + + + B_0x1 + Divide by 2 + 0x1 + + + B_0x2 + Divide by 4 + 0x2 + + + B_0x3 + Divide by 6 + 0x3 + + + B_0x4 + Divide by 8 + 0x4 + + + B_0x5 + Divide by 10 + 0x5 + + + B_0x6 + Divide by 12 + 0x6 + + + B_0x7 + Divide by 14 + 0x7 + + + B_0x8 + Divide by 16 + 0x8 + + + B_0x9 + Divide by 18 + 0x9 + + + B_0xA + Divide by 20 + 0xA + + + B_0xB + Divide by 22 + 0xB + + + B_0xC + Divide by 24 + 0xC + + + B_0xD + Divide by 26 + 0xD + + + B_0xE + Divide by 28 + 0xE + + + B_0xF + Divide by 30 + 0xF + + + + + SWR + Software reset +Writing a 1 to this bit resets the calibration FSM to state Not_Calibrated +(FDCAN_CCU_CSTAT.CALS = 00). The calibration watchdog value CWD.WDV is also reset. Registers FDCAN_CCFG, FDCAN_CCU_CSTAT and the calibration watchdog configuration CWD.WDC are unchanged. The bit remains set until reset is completed. +Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 31 + 1 + read-write + + + + + CCU_CSTAT + CCU_CSTAT + Calibration status register + 0x8 + 0x20 + 0x0203FFFF + 0xFFFFFFFF + + + OCPC + Oscillator clock period counter +Captured number of oscillator clock periods in calibration field (32 or 64 bits). Only valid when the clock calibration unit is in state Precision_Calibrated. + 0 + 18 + read-only + + + TQC + Time quanta counter +Captured number of time quanta in calibration field (32 or 64 bits). Only valid when the clock calibration unit is in state Precision_Calibrated. + 18 + 11 + read-only + + + CALS + Calibration state + 30 + 2 + read-only + + + B_0x0 + Not_Calibrated + 0x0 + + + B_0x1 + Basic_Calibrated + 0x1 + + + B_0x2 + Precision_Calibrated + 0x2 + + + + + + + CCU_CWD + CCU_CWD + Calibration watchdog register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDC + WDC +Watchdog configuration +Start value of the calibration watchdog counter. With the reset value of 00 the counter is disabled. +Write access by the Host CPU to registers/bits marked with “P = Protected Write” is possible only when the FDCAN control bits FDCAN_CCCR.CCE = 1 AND FDCAN_CCCR.INIT = 1. + 0 + 16 + read-write + + + WDV + Watchdog value +Actual calibration watchdog counter value. + 16 + 16 + read-only + + + + + CCU_IR + CCU_IR + Clock calibration unit interrupt register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWE + Calibration watchdog event + 0 + 1 + read-write + + + B_0x0 + No calibration watchdog event + 0x0 + + + B_0x1 + Calibration watchdog event occurred + 0x1 + + + + + CSC + Calibration state changed + 1 + 1 + read-write + + + B_0x0 + Calibration state unchanged + 0x0 + + + B_0x1 + Calibration state has changed + 0x1 + + + + + + + CCU_IE + CCU_IE + Clock calibration unit interrupt enable register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWEE + Calibration watchdog event enable + 0 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + CSCE + Calibration state changed enable + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + + + + + CRC + CRC + CRC + 0x58009000 + + 0x0 + 0x1000 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x0 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +These bits control the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + CRYP + CRYP + CRYP + 0x54002000 + + 0x0 + 0x400 + registers + + + CRYP + CRYP global interrupt + 80 + + + + CRYP_CR + CRYP_CR + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALGODIR + Algorithm Direction +Writing ALGODIR bit while BUSY = 1 has no effect. + 2 + 1 + read-write + + + B_0x0 + Encrypt + 0x0 + + + B_0x1 + Decrypt + 0x1 + + + + + ALGOMODE + Algorithm mode +Below definition includes the bit 19: +Writing ALGOMODE bits while BUSY = 1 has no effect. +Others: Reserved, must no be used +Changing ALGOMODE from AES algorithm to DES or TDES (or the reverse) clears KEYVALID. KEYVALID is not cleared when the algorithm type is kept between two ALGOMODE, that is between TDES-ECB and TDES-CBC or between AES-ECB and AES_CTR. + 3 + 3 + read-write + + + DATATYPE + Data Type selection +This bitfield defines the format of data written in CRYP_DIN or read from CRYP_DOUT registers. For more details refer to registers and data swapping). +Writing DATATYPE bits while BUSY = 1 has no effect. + 6 + 2 + read-write + + + B_0x0 + 32-bit data. No swapping for each word. First word pushed into the IN FIFO (or popped off the OUT FIFO) forms bits 1...32 of the data block, the second word forms bits 33...64 etc. + 0x0 + + + B_0x1 + 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 2 half-words, which are swapped with each other. + 0x1 + + + B_0x2 + 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 4 bytes, which are swapped with each other. + 0x2 + + + B_0x3 + bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are swapped with each other. + 0x3 + + + + + KEYSIZE + Key size selection (AES mode only) +This bitfield defines the bit-length of the key used for the AES cryptographic core. This bitfield is 'don’t care’ in the DES or TDES modes. +Writing KEYSIZE bits while BUSY = 1 has no effect. +When KEYSIZE is changed KEYVALID is cleared. + 8 + 2 + read-write + + + B_0x0 + 128-bit key length + 0x0 + + + B_0x1 + 192-bit key length + 0x1 + + + B_0x2 + 256-bit key length + 0x2 + + + B_0x3 + Reserved, do not use this value + 0x3 + + + + + FFLUSH + CRYP FIFO Flush +When CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset). Writing this bit to 0 has no effect. When CRYPEN = 1, writing this bit to 0 or 1 has no effect. +Reading this bit always returns 0. +FFLUSH bit has to be set only when BUSY = 0. If not, the FIFO is flushed, but the block being processed may be pushed into the output FIFO just after the flush operation, resulting in a non-empty FIFO condition. + 14 + 1 + read-write + + + B_0x0 + No FIFO flush + 0x0 + + + B_0x1 + FIFO flush enabled + 0x1 + + + + + CRYPEN + CRYP processor Enable +This bit is automatically cleared by hardware when the key preparation process ends (ALGOMODE = 0111) or after GCM/GMAC or CCM Initialization phase. + 15 + 1 + read-write + + + B_0x0 + Cryptographic processor peripheral is disabled + 0x0 + + + B_0x1 + Cryptographic processor peripheral is enabled + 0x1 + + + + + GCM_CCMPH + GCM or CCM Phase selection +This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected in ALGOMODE field. +Writing to GCM_CCMPH bits while BUSY = 1 has no effect. + 16 + 2 + read-write + + + B_0x0 + Initialization phase + 0x0 + + + B_0x1 + Header phase + 0x1 + + + B_0x2 + Payload phase + 0x2 + + + B_0x3 + Final phase + 0x3 + + + + + ALGOMODE3 + Algorithm mode +Below definition includes the bit 19: +Writing ALGOMODE bits while BUSY = 1 has no effect. +Others: Reserved, must no be used +Changing ALGOMODE from AES algorithm to DES or TDES (or the reverse) clears KEYVALID. KEYVALID is not cleared when the algorithm type is kept between two ALGOMODE, that is between TDES-ECB and TDES-CBC or between AES-ECB and AES_CTR. + 19 + 1 + read-write + + + NPBLB + Number of Padding Bytes in Last Block of payload. +This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. +... +Writing NPBLB bits while BUSY = 1 has no effect. + 20 + 4 + read-write + + + B_0x0 + All bytes are valid (no padding) + 0x0 + + + B_0x1 + Padding for the last LSB byte + 0x1 + + + B_0xF + Padding for the 15 LSB bytes of last block. + 0xF + + + + + KMOD0 + Key mode selection +This bitfield defines how the CRYP key is used by the application: +Others: Reserved, must not be used. +When KMOD[1:0] = 10 the selected key value is available in the key registers when KEYVALID is set in SAES_SR register. Otherwise the key error flag KERF is set in CRYP_SR register. +KMOD[1:0] must be set to 10 only when KEYSIZE is correct and a shared key decryption sequence has been successfully completed by the SAES co-processor. Otherwise the key error flag KERF is set in CRYP_SR. +Writing to KMOD bits while BUSY = 1 has no effect. + 24 + 1 + read-write + + + KMOD1 + Key mode selection +This bitfield defines how the CRYP key is used by the application: +Others: Reserved, must not be used. +When KMOD[1:0] = 10 the selected key value is available in the key registers when KEYVALID is set in SAES_SR register. Otherwise the key error flag KERF is set in CRYP_SR register. +KMOD[1:0] must be set to 10 only when KEYSIZE is correct and a shared key decryption sequence has been successfully completed by the SAES co-processor. Otherwise the key error flag KERF is set in CRYP_SR. +Writing to KMOD bits while BUSY = 1 has no effect. + 25 + 1 + read-write + + + IPRST + CRYP software reset +Setting the bit resets the CRYP processor, resetting all registers to their default values except the IPRST bit itself. +This bit must be kept cleared while writing any configuration registers. + 31 + 1 + read-write + + + + + CRYP_SR + CRYP_SR + 0x4 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + IFEM + Input FIFO empty flag + 0 + 1 + read-only + + + B_0x0 + Input FIFO is not empty + 0x0 + + + B_0x1 + Input FIFO is empty + 0x1 + + + + + IFNF + Input FIFO not full flag + 1 + 1 + read-only + + + B_0x0 + Input FIFO is full + 0x0 + + + B_0x1 + Input FIFO is not full + 0x1 + + + + + OFNE + Output FIFO not empty flag + 2 + 1 + read-only + + + B_0x0 + Output FIFO is empty + 0x0 + + + B_0x1 + Output FIFO is not empty + 0x1 + + + + + OFFU + Output FIFO full flag + 3 + 1 + read-only + + + B_0x0 + Output FIFO is not full + 0x0 + + + B_0x1 + Output FIFO is full + 0x1 + + + + + BUSY + Busy bit +either that the CRYP core is disabled (CRYPEN = 0 in the CRYP_CR register) and the last processing has completed, +or the CRYP core is waiting for enough data in the input FIFO or enough free space in the output FIFO (that is in each case at least 2 words in the DES, 4 words in the AES). + 4 + 1 + read-only + + + B_0x0 + The CRYP core is not processing any data. The reason is: + 0x0 + + + B_0x1 + The CRYP core is currently processing a block of data or a key preparation is ongoing (AES ECB or CBC decryption only). BUSY is also set when an AES key is being transfered from SAES to CRYP. + 0x1 + + + + + KERF + Key error flag +KERF is a read-only bit. It is set by hardware when key information failed to load into key registers. +KERF is set if one of the below errors occurred: +The user application did not write the key registers in the correct sequence (refer to for details). +The CRYP failed to load the AES key shared by SAES peripheral (KMOD = 10). +KMOD = 10 with ALGOMODE selecting either DES or TDES algorithm. +KERF must be cleared by the application, for example through IPRST bit of CRYP_CR, otherwise KEYVALID cannot be set. + 6 + 1 + read-only + + + B_0x0 + No key error detected + 0x0 + + + B_0x1 + Key information failed to load into key registers + 0x1 + + + + + KEYVALID + Key valid +KEYVALID is a read-only bit. It is set by hardware when the expected amount of key information has been loaded in CRYP_KEYx key registers. It is valid for both AES and DES/TDES algorithms. +When KMOD = 00, the use application must write the key registers in the correct sequence, otherwise KERF flag is set and KEYVALID remains at zero. +When KMOD = 10 (AES Shared key mode), the shared key is loaded successfully from SAES to CRYP when KEYVALID is set. When an error occurs KERF flag is set in CRYP_SR and KEYVALID remains at zero. + 7 + 1 + read-only + + + B_0x0 + No valid key information is available in key registers. CRYPEN bit in CRYP_CR cannot be set. + 0x0 + + + B_0x1 + Valid key information, defined by KEYSIZE in CRYP_CR, is loaded in key registers. + 0x1 + + + + + + + CRYP_DIN + CRYP_DIN + CRYP data input register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATAIN + Data Input +On read FIFO is popped (last written value is returned), and its value is returned if CRYPEN = 0. If CRYPEN = 1 DATAIN register returns an undefined value. +On write current register content is pushed inside the FIFO. + 0 + 32 + read-write + + + + + CRYP_DOUT + CRYP_DOUT + CRYP data output register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATAOUT + Data Output +On read returns output FIFO content (pointed to by read pointer), else returns an undefined value. +On write, no effect. + 0 + 32 + read-only + + + + + CRYP_DMACR + CRYP_DMACR + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIEN + DMA Input Enable +When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. + 0 + 1 + read-write + + + B_0x0 + DMA for incoming data transfer is disabled + 0x0 + + + B_0x1 + DMA for incoming data transfer is enabled + 0x1 + + + + + DOEN + DMA Output Enable +When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. + 1 + 1 + read-write + + + B_0x0 + DMA for outgoing data transfer is disabled + 0x0 + + + B_0x1 + DMA for outgoing data transfer is enabled + 0x1 + + + + + + + CRYP_IMSCR + CRYP_IMSCR + CRYP interrupt mask set/clear register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INIM + Input FIFO service interrupt mask + 0 + 1 + read-write + + + B_0x0 + Input FIFO service interrupt is masked + 0x0 + + + B_0x1 + Input FIFO service interrupt is not masked + 0x1 + + + + + OUTIM + Output FIFO service interrupt mask + 1 + 1 + read-write + + + B_0x0 + Output FIFO service interrupt is masked + 0x0 + + + B_0x1 + Output FIFO service interrupt is not masked + 0x1 + + + + + + + CRYP_RISR + CRYP_RISR + CRYP raw interrupt status register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + INRIS + Input FIFO service raw interrupt status +This bit gives the input FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. + 0 + 1 + read-only + + + B_0x0 + Raw interrupt not pending + 0x0 + + + B_0x1 + Raw interrupt pending + 0x1 + + + + + OUTRIS + Output FIFO service raw interrupt status +This bit gives the output FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. + 1 + 1 + read-only + + + B_0x0 + Raw interrupt not pending + 0x0 + + + B_0x1 + Raw interrupt pending + 0x1 + + + + + + + CRYP_MISR + CRYP_MISR + CRYP masked interrupt status register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INMIS + Input FIFO service masked interrupt status +This bit gives the input FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. + 0 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending when CRYPEN = 1 + 0x1 + + + + + OUTMIS + Output FIFO service masked interrupt status +This bit gives the output FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. + 1 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + + + CRYP_K0LR + CRYP_K0LR + CRYP key register 0L + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  255 to 224) +This write-only bitfield contains the bits [255:224] of the AES encryption or decryption key, depending on the operating mode. This register is not used in DES/TDES mode. + 0 + 32 + write-only + + + + + CRYP_K0RR + CRYP_K0RR + CRYP key register 0R + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  223 to 192) +This write-only bitfield contains the bits [223:192] of the AES encryption or decryption key, depending on the operating mode. This register is not used in DES/TDES mode. + 0 + 32 + write-only + + + + + CRYP_K1LR + CRYP_K1LR + CRYP key register 1L + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  191 to 160) +This write-only bitfield contains the bits [191:160] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [64:33] of the key K1, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_K1RR + CRYP_K1RR + CRYP key register 1R + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  159 to 128) +This write-only bitfield contains the bits [159:128] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [32:1] of the key K1, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_K2LR + CRYP_K2LR + CRYP key register 2L + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  127 to 96) +This write-only bitfield contains the bits [127:96] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [64:33] of the key K2, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_K2RR + CRYP_K2RR + CRYP key register 2R + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  95 to 64) +This write-only bitfield contains the bits [95:64] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [32:1] of the key K2, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_K3LR + CRYP_K3LR + CRYP key register 3L + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  63 to 32) +This write-only bitfield contains the bits [63:32] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [64:33] of the key K3, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_K3RR + CRYP_K3RR + CRYP key register 3R + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + K + Key bit x (x =  31 to 0) +This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode. In DES/TDES mode this bitfield contains the bits [32:1] of the key K3, with parity bits unused. + 0 + 32 + write-only + + + + + CRYP_IV0LR + CRYP_IV0LR + CRYP initialization vector register 0L + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IV + Initialization vector bit x (x =  127 to 96) +This bitfield stores the initialization vector bits [127:96] for AES chaining modes other than ECB. In DES/TDES mode it corresponds to IV bits [63:32]. +IV registers are updated by the core after each computation round of the DES/TDES or AES core. + 0 + 32 + read-write + + + + + CRYP_IV0RR + CRYP_IV0RR + CRYP initialization vector register 0R + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IV + Initialization vector bit x (x =  95 to 64) +This bitfield stores the initialization vector bits [95:64] for AES chaining modes other than ECB. In DES/TDES mode it corresponds to IV bits [31:0]. +IV registers are updated by the core after each computation round of the DES/TDES or AES core. + 0 + 32 + read-write + + + + + CRYP_IV1LR + CRYP_IV1LR + CRYP initialization vector register 1L + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IV + Initialization vector bit x (x =  63 to 32) +This bitfield stores the initialization vector bits [63:32] for AES chaining modes other than ECB. This register is not used in DES mode. +IV registers are updated by the core after each computation round of the AES core. + 0 + 32 + read-write + + + + + CRYP_IV1RR + CRYP_IV1RR + CRYP initialization vector register 1R + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IV + Initialization vector bit x (x =  31 to 16) +This bitfield stores the initialization vector bits [31:0] for AES chaining modes other than ECB. This register is not used in DES mode. +IV registers are updated by the core after each computation round of the AES core. + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM0R + CRYP_CSGCMCCM0R + CRYP context swap GCM-CCM registers + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM0 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM1R + CRYP_CSGCMCCM1R + CRYP context swap GCM-CCM registers + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM1 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM2R + CRYP_CSGCMCCM2R + CRYP context swap GCM-CCM registers + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM2 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM3R + CRYP_CSGCMCCM3R + CRYP context swap GCM-CCM registers + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM3 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM4R + CRYP_CSGCMCCM4R + CRYP context swap GCM-CCM registers + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM4 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM5R + CRYP_CSGCMCCM5R + CRYP context swap GCM-CCM registers + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM5 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM6R + CRYP_CSGCMCCM6R + CRYP context swap GCM-CCM registers + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM6 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCMCCM7R + CRYP_CSGCMCCM7R + CRYP context swap GCM-CCM registers + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCMCCM7 + CRYP processor internal register states for GCM, GMAC and CCM modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM0R + CRYP_CSGCM0R + CRYP context swap GCM registers + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM0 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM1R + CRYP_CSGCM1R + CRYP context swap GCM registers + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM1 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM2R + CRYP_CSGCM2R + CRYP context swap GCM registers + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM2 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM3R + CRYP_CSGCM3R + CRYP context swap GCM registers + 0x7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM3 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM4R + CRYP_CSGCM4R + CRYP context swap GCM registers + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM4 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM5R + CRYP_CSGCM5R + CRYP context swap GCM registers + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM5 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM6R + CRYP_CSGCM6R + CRYP context swap GCM registers + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM6 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_CSGCM7R + CRYP_CSGCM7R + CRYP context swap GCM registers + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSGCM7 + CRYP processor internal register states for GCM and GMAC modes. +Note: This register is not used in DES/TDES or other AES modes than the ones indicated + 0 + 32 + read-write + + + + + CRYP_HWCFGR + CRYP_HWCFGR + 0x3f0 + 0x20 + 0x00000131 + 0xFFFFFFFF + + + CFG1 + HW Generic 1 +This field returns the tdes_impl generic value (0x1). + 0 + 4 + read-only + + + CFG2 + HW Generic 2 +This field returns the aes_impl generic value (0x3). + 4 + 4 + read-only + + + CFG3 + HW Generic 3 +This field returns the dma_version generic value (0x1). + 8 + 4 + read-only + + + CFG4 + HW Generic 4 +Reserved, must be kept at reset value. + 12 + 4 + read-only + + + + + CRYP_VERR + CRYP_VERR + 0x3f4 + 0x20 + 0x00000023 + 0xFFFFFFFF + + + MINVER + CRYP processor minor version +This field returns the CRYP processor minor version. + 0 + 4 + read-only + + + MAJVER + CRYP processor major version +This field returns the CRYP processor major version. + 4 + 4 + read-only + + + + + CRYP_IPIDR + CRYP_IPIDR + 0x3f8 + 0x20 + 0x00170011 + 0xFFFFFFFF + + + ID + Identification Code +This field returns the identification code of the CRYP processor. + 0 + 32 + read-only + + + + + CRYP_SIDR + CRYP_SIDR + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification code +This field returns the size identification code of the CRYP processor as defined below: +SID[31:8] = 0xA3C5DD (fixed code) +SID[7:0] = 0x01 (1-Kbyte address decoding) + 0 + 32 + read-only + + + + + + + DBGMCU + Microcontroller Debug Unit + DBGMCU + 0x50081000 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDC + DBGMCU_IDC + DBGMCU identity code register + 0x0 + 0x20 + 0x10006501 + 0xFFFFFFFF + + + DEV_ID + device ID + 0 + 12 + read-only + + + B_0x501 + STM32MP13xx + 0x501 + + + + + REV_ID + revision +0x1000 = Rev. 1 + 16 + 16 + read-only + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBGLP + Low power mode debug enable + 2 + 1 + read-write + + + B_0x0 + normal operation. In Stop, LP-Stop, LPLV-Stop, LPLV-Stop2 and Standby mode, debug access is lost. + 0x0 + + + B_0x1 + automatic clock stop/power down disabled. All active clocks and oscillators continue to run during low power mode, and the VDDCORE and VDDCPU supplies are maintained, allowing full debug capability. On exit from Standby or LPLV-Stop2 modes, the Cortex®-A7 is reset. + 0x1 + + + + + + + DBGMCU_APB4FZ + DBGMCU_APB4FZ + DBGMCU APB4 peripheral freeze register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IWDG2 + IWDG2 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. IWDG2 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. IWDG2 is frozen while Cortex®-A7 core is in debug mode. No accesses are allowed on its APB interface. + 0x1 + + + + + + + DBGMCU_APB1FZ + DBGMCU_APB1FZ + DBGMCU APB1 peripheral freeze register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2 + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + Normal operation. TIM2 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + Stop in debug. TIM2 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM3 + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. TIM3 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM3 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM4 + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. TIM4 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM4 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM5 + TIM5 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. TIM5 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM5 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM6 + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. TIM6 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM6 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM7 + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. TIM7 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM7 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + LPTIM1 + LPTIM1 stop in debug + 9 + 1 + read-write + + + B_0x0 + normal operation. LPTIM1 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM1 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + I2C1 + I2C1 SMBUS timeout stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. I2C1 SMBUS timeout continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C1 SMBUS timeout is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + I2C2 + I2C2 SMBUS timeout stop in debug + 19 + 1 + read-write + + + B_0x0 + normal operation. I2C2 SMBUS timeout continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C2 SMBUS timeout is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + + + DBGMCU_APB2FZ + DBGMCU_APB2FZ + DBGMCU APB2 peripheral freeze register + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1 + TIM1 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. TIM1 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM1 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + TIM8 + TIM8 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. TIM8 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM8 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + FDCAN + FDCAN stop in debug + 15 + 1 + read-write + + + B_0x0 + normal operation. FDCAN continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. FDCAN is frozen while Cortex®-A7 core is in debug mode. + 0x1 + + + + + + + DBGMCU_APB3FZ + DBGMCU_APB3FZ + DBGMCU APB3 peripheral freeze register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPTIM2 + LPTIM2 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. LPTIM2 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM2 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + LPTIM3 + LPTIM3 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. LPTIM3 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM3 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + LPTIM4 + LPTIM4 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. LPTIM4 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM4 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + LPTIM5 + LPTIM5 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. LPTIM5 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM5 is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + + + DBGMCU_APB5FZ + DBGMCU_APB5FZ + DBGMCU APB5 peripheral freeze register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IWDG1 + independent watchdog 1 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. Watchdog continues to count while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. IWGD1 is frozen while the Cortex®-A7 core is in debug mode. No accesses are allowed on its APB interface. + 0x1 + + + + + RTC + RTC stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. RTC continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. RTC is frozen while the Cortex®-A7 core is in debug mode. + 0x1 + + + + + + + DBGMCU_APB6FZ + DBGMCU_APB6FZ + DBGMCU APB6 peripheral freeze register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C3 + I2C3 SMBUS stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. I2C3 SMBUS timeout continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C3 SMBUS timeout is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + I2C4 + I2C4 SMBUS stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. I2C4 SMBUS timeout continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C4 SMBUS timeout is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + I2C5 + I2C5 SMBUS stop in debug + 6 + 1 + read-write + + + B_0x0 + normal operation. I2C5 SMBUS timeout continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C5 SMBUS timeout is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM12 + TIM12 stop in debug + 7 + 1 + read-write + + + B_0x0 + normal operation. TIM12 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM12 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM13 + TIM13 stop in debug + 8 + 1 + read-write + + + B_0x0 + normal operation. TIM13 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM13 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM14 + TIM14 stop in debug + 9 + 1 + read-write + + + B_0x0 + normal operation. TIM14 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM14 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM15 + TIM15 stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. TIM15 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM15 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM16 + TIM16 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. TIM16 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM16 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + TIM17 + TIM17 stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. TIM17 continues to operate while Cortex®-A7 is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM17 is frozen while Cortex®-A7 is in debug mode. + 0x1 + + + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU peripheral ID4 register + 0xfd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DES_2 + JEDEC continuation code +Indicates the designer of the component, together with the identity code. + 0 + 4 + read-only + + + B_0x0 + indicates that STMicroelectronics JEDEC identity code is on the 1st bank + 0x0 + + + + + SIZE + component memory size indicator +Indicates the total contiguous size of the memory window used by the component in powers of two from the standard 4 Kbytes. If a component only requires the standard 4 Kbytes, this bit field must read as 0x0. For 8 Kbytes it is set to 0x1. For 16 Kbytes it set to 0x2. For 32 Kbytes it is set to 0x3, and similarly for larger memory windows. + 4 + 4 + read-only + + + B_0x0 + the device only occupies 4 Kbytes of memory + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU peripheral ID0 register + 0xfe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PART_0 + bits [7:0] of the component part number +This field is specified by the designer of the component. + 0 + 8 + read-only + + + B_0x0 + CoreSight™ DBGMCU Part Number[7:0]. Eight least significant bits of the part number (0x000). + 0x0 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU peripheral ID1 register + 0xfe4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PART_1 + bits [11:8] of the component part number +Specified by the designer of the component. + 0 + 4 + read-only + + + B_0x0 + CoreSight™ DBGMCU part number[11:8]. Most significant four bits of the part number (0x000). + 0x0 + + + + + DES_0 + bits [3:0] of the JEDEC identity code +Indicates the designer of the component, together with the continuation code. + 4 + 4 + read-only + + + B_0x0 + least significant four bits of the JEP106 identity code (0x20 = STMicroelectronics) + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU peripheral ID2 register + 0xfe8 + 0x20 + 0x0000000A + 0xFFFFFFFF + + + DES_1 + bits [6:4] of the JEDEC identity code +Indicates the designer of the component, together with the continuation code. + 0 + 3 + read-only + + + B_0x2 + most significant three bits of the JEP106 identity code (0x20 = STMicroelectronics) + 0x2 + + + + + JEDEC + JEDEC assigned value usage +Indicates the use of a JEDEC assigned value. This bit is always set. + 3 + 1 + read-only + + + B_0x1 + the designer ID is specified by JEDEC (refer to http://www.jedec.org) + 0x1 + + + + + REVISION + incremental component design version +An incremental value starting from 0x0 for the first design of this component. The value increases by one at both major and minor revisions and is used as a look-up to establish the exact major and minor revisions. + 4 + 4 + read-only + + + B_0x0 + this component is at rev0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU peripheral ID3 register + 0xfec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modification indicator +When the component is a reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is 0x0. + 0 + 4 + read-only + + + B_0x0 + no modification made + 0x0 + + + + + REVAND + minor fix indicator +Indicates minor errata fixes specific to the design, for example metal fixes after implementation. In most cases this field is 0x0. Arm® recommends that the component designers ensure that the bit field can be changed by a metal fix if required, for example by driving the bit field from registers that reset to zero. + 4 + 4 + read-only + + + B_0x0 + no metal fix in the component + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU component ID0 register + 0xff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PRMBL_0 + bits [31:24] of component identification +Component identification register, that indicates that the identification registers are present. + 0 + 8 + read-only + + + B_0xD + identification value + 0xD + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU component ID1 register + 0xff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PRMBL_1 + bits [19:16] of component identification. +Component identification register, that indicates that the identification registers are present. + 0 + 4 + read-only + + + B_0x0 + identification value + 0x0 + + + + + CLASS + component class +Indicates the class of the component, for example, ROM table or CoreSight™ component. + 4 + 4 + read-only + + + B_0xF + indicates that the component is a non-CoreSight™ component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU component ID2 register + 0xff8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + PRMBL_2 + bits [15:8] of component identification +Component identification register, that indicates that the identification registers are present. + 0 + 8 + read-only + + + B_0x5 + identification value + 0x5 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU component ID3 register + 0xffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PRMBL_3 + bits [7:0] of component identification +Component identification register, that indicates that the identification registers are present. + 0 + 8 + read-only + + + B_0xB1 + identification value + 0xB1 + + + + + + + + + DDRCTRL + DDRCTRL + DDRCTRL + 0x5A003000 + + 0x0 + 0x1000 + registers + + + + DDRCTRL_MSTR + DDRCTRL_MSTR + DDRCTRL master register 0 + 0x0 + 0x20 + 0x00040001 + 0xFFFFFFFF + + + DDR3 + Selects DDR3 SDRAM +- 1 - DDR3 SDRAM device in use +- 0 - non-DDR3 SDRAM device in use +Only present in designs that support DDR3. +Programming mode: Static + 0 + 1 + read-write + + + LPDDR2 + Selects LPDDR2 SDRAM +- 1 - LPDDR2 SDRAM device in use. +- 0 - non-LPDDR2 device in use +Present only in designs configured to support LPDDR2. +Programming mode: Static + 2 + 1 + read-write + + + LPDDR3 + Selects LPDDR3 SDRAM +- 1 - LPDDR3 SDRAM device in use. +- 0 - non-LPDDR3 device in use +Present only in designs configured to support LPDDR3. +Programming mode: Static + 3 + 1 + read-write + + + BURSTCHOP + When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. The burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). +The BC4 (fixed) mode is not supported. +Programming mode: Static + 9 + 1 + read-write + + + EN_2T_TIMING_MODE + If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command +Note: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode +Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set +Note: 2T timing is not supported in DDR4 geardown mode. +Note: 2T timing is not supported in Shared-AC dual channel mode and the register value is don't care. +Programming mode: Static + 10 + 1 + read-write + + + DATA_BUS_WIDTH + Selects proportion of DQ bus width that is used by the SDRAM +- 00 - Full DQ bus width to SDRAM +- 01 - Half DQ bus width to SDRAM +- 10 - Quarter DQ bus width to SDRAM +- 11 - Reserved. +Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. the bus width refers to DQ bus width (excluding any ECC width). +Programming mode: Static + 12 + 2 + read-write + + + DLL_OFF_MODE + Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. +Set to 0 to put DDRCTRL and DRAM in DLL-on mode for normal frequency operation. +If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and this bit must be set to '0'. +Programming mode: Quasi-dynamic Group 2 + 15 + 1 + read-write + + + BURST_RDWR + SDRAM burst length used: +- 0001 - Burst length of 2 (only supported for mDDR) +- 0010 - Burst length of 4 +- 0100 - Burst length of 8 +- 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) +All other values are reserved. +This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) The burst length of 2 is not supported with the AXI port when MEMC_BURST_LENGTH is 8. +The burst length of 2 is only supported when the controller is operating in 1:1 frequency mode. +For DDR3, DDR4 and LPDDR3, this must be set to 0x0100 (BL8). +For LPDDR4, this must be set to 0x1000 (BL16). +Programming mode: Static + 16 + 4 + read-write + + + + + DDRCTRL_STAT + DDRCTRL_STAT + DDRCTRL operating mode status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPERATING_MODE + Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. +Condition non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: +- 000 - Init +- 001 - Normal +- 010 - Power-down +- 011 - Self refresh +Condition mDDR/LPDDR2/LPDDR3 or DDR4 designs: +- 000 - Init +- 001 - Normal +- 010 - Power-down +- 011 - Self refresh +- 1XX - Deep power-down / Maximum Power Saving Mode +- 000 - Init +- 001 - Normal +- 010 - Power-down +- 011 - Self refresh / Self refresh power-down +Programming mode: Dynamic + 0 + 3 + read-only + + + SELFREF_TYPE + Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. +- 00 - SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress. +- 11 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. +- 10 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low-power Interface and/or Software (PWRCTL.selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity error. +- 01 - SDRAM is in Self Refresh, which was caused by PHY Master Request. +Programming mode: Dynamic + 4 + 2 + read-only + + + SELFREF_CAM_NOT_EMPTY + Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. +Programming mode: Dynamic + 12 + 1 + read-only + + + + + DDRCTRL_MRCTRL0 + DDRCTRL_MRCTRL0 + DDRCTRL mode register read/write control register 0 + 0x10 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MR_TYPE + Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. +- 0 - Write +- 1 - Read +Programming mode: Dynamic + 0 + 1 + read-write + + + MR_ADDR + Address of the mode register that is to be written to. +- 0000 - MR0 +- 0001 - MR1 +- 0010 - MR2 +- 0011 - MR3 +- 0100 - MR4 +- 0101 - MR5 +- 0110 - MR6 +- 0111 - MR7 +Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3/LPDDR4) +This signal is also used for writing to control words of the register chip on RDIMMs/LRDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM/LRDIMM +In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs/LRDIMMs and the Output Inversion of RDIMMs/LRDIMMs. +Programming mode: Dynamic + 12 + 4 + read-write + + + MR_WR + Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. +Programming mode: Dynamic + 31 + 1 + read-write + + + + + DDRCTRL_MRCTRL1 + DDRCTRL_MRCTRL1 + DDRCTRL mode register read/write control register 1 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MR_DATA + Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. +For LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as +[15:8] MR Address +[7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. +Programming mode: Dynamic + 0 + 16 + read-write + + + + + DDRCTRL_MRSTAT + DDRCTRL_MRSTAT + DDRCTRL mode register read/write status register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MR_WR_BUSY + The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. +- 0 - Indicates that the SoC core can initiate a mode register write operation +- 1 - Indicates that mode register write operation is in progress +Programming mode: Dynamic + 0 + 1 + read-only + + + + + DDRCTRL_DERATEEN + DDRCTRL_DERATEEN + DDRCTRL temperature derate enable register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DERATE_ENABLE + Enables derating +- 0 - Timing parameter derating is disabled +- 1 - Timing parameter derating is enabled using MR4 read value. +Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +Programming mode: Dynamic + 0 + 1 + read-write + + + DERATE_VALUE + Derate value +- 0 - Derating uses +1. +- 1 - Derating uses +2. +Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. +For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 1 + 2 + read-write + + + DERATE_BYTE + Derate byte +Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +Indicates which byte of the MRR data is used for derating. The maximum valid value depends +on MEMC_DRAM_TOTAL_DATA_WIDTH. +Programming mode: Static + 4 + 4 + read-write + + + + + DDRCTRL_DERATEINT + DDRCTRL_DERATEINT + DDRCTRL temperature derate interval register + 0x24 + 0x20 + 0x00800000 + 0xFFFFFFFF + + + MR4_READ_INTERVAL + Interval between two MR4 reads, used to derate the timing parameters. +Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. +Unit: DFI clock cycle. +Programming mode: Static + 0 + 32 + read-write + + + + + DDRCTRL_PWRCTL + DDRCTRL_PWRCTL + DDRCTRL low power control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SELFREF_EN + If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. +Programming mode: Dynamic + 0 + 1 + read-write + + + POWERDOWN_EN + If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). +This register bit may be re-programmed during the course of normal operation. +Programming mode: Dynamic + 1 + 1 + read-write + + + DEEPPOWERDOWN_EN + When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. +This register must be reset to '0' to bring DDRCTRL out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit. +Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. +For performance only +Programming mode: Dynamic + 2 + 1 + read-write + + + EN_DFI_DRAM_CLK_DISABLE + Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. +If set to 0, dfi_dram_clk_disable is never asserted. +Assertion of dfi_dram_clk_disable is as follows: +In DDR2/DDR3, can only be asserted in Self Refresh. +In DDR4, can be asserted in following: +- in Self Refresh. +- in Maximum Power Saving Mode +In mDDR/LPDDR2/LPDDR3, can be asserted in following: +- in Self Refresh +- in Power Down +- in Deep Power Down +- during Normal operation (Clock Stop) +In LPDDR4, can be asserted in following: +- in Self Refresh Power Down +- in Power Down +- during Normal operation (Clock Stop) +Programming mode: Dynamic + 3 + 1 + read-write + + + SELFREF_SW + A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. +- 1 - Software Entry to Self Refresh +- 0 - Software Exit from Self Refresh +Programming mode: Dynamic + 5 + 1 + read-write + + + DIS_CAM_DRAIN_SELFREF + Indicates whether skipping CAM draining is allowed when entering Self-Refresh. +This register field cannot be modified while PWRCTL.selfref_sw==1. +- 0 - CAMs must be empty before entering SR +- 1 - CAMs are not emptied before entering SR (unsupported) +Note, PWRCTL.dis_cam_drain_selfref=1 is unsupported in this release. PWRCTL.dis_cam_drain_selfref=0 is required. +Programming mode: Dynamic + 7 + 1 + read-write + + + + + DDRCTRL_PWRTMG + DDRCTRL_PWRTMG + DDRCTRL low power timing register + 0x34 + 0x20 + 0x00402010 + 0xFFFFFFFF + + + POWERDOWN_TO_X32 + After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. +Unit: Multiples of 32 DFI clocks +For performance only. +Programming mode: Quasi-dynamic Group 4 + 0 + 5 + read-write + + + T_DPD_X4096 + Minimum deep power-down time. +For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. +For LPDDR2/LPDDR3, value from the JEDEC specification is 500 us. +Unit: Multiples of 4096 DFI clocks. +Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. +For performance only. +Programming mode: Quasi-dynamic Group 4 + 8 + 8 + read-write + + + SELFREF_TO_X32 + After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. +Unit: Multiples of 32 DFI clocks. +For performance only. +Programming mode: Quasi-dynamic Group 4 + 16 + 8 + read-write + + + + + DDRCTRL_HWLPCTL + DDRCTRL_HWLPCTL + DDRCTRL hardware low power control register + 0x38 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + HW_LP_EN + Enable for hardware low power interface. +Programming mode: Quasi-dynamic Group 3 + 0 + 1 + read-write + + + HW_LP_EXIT_IDLE_EN + When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). +Programming mode: Static + 1 + 1 + read-write + + + HW_LP_IDLE_X32 + Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. +Unit: Multiples of 32 DFI clocks. +For performance only. +Programming mode: Static + 16 + 12 + read-write + + + + + DDRCTRL_RFSHCTL0 + DDRCTRL_RFSHCTL0 + DDRCTRL refresh control register 0 + 0x50 + 0x20 + 0x00210000 + 0xFFFFFFFF + + + PER_BANK_REFRESH + - 1 - Per bank refresh; +- 0 - All bank refresh. +Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +Programming mode: Static + 2 + 1 + read-write + + + REFRESH_BURST + The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. +- 0 - single refresh +- 1 - burst-of-2 refresh +- 7 - burst-of-8 refresh +For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. +For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. +In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst is delayed until the PHY-initiated update is complete. +Programming mode: dynamic - refresh related + 4 + 5 + read-write + + + REFRESH_TO_X32 + If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. +For performance only. +Unit: Multiples of 32 DFI clocks. +Programming mode: Dynamic - Refresh Related + 12 + 5 + read-write + + + REFRESH_MARGIN + Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). +Unit: Multiples of 32 DFI clocks. +Programming mode: Dynamic - Refresh Related + 20 + 4 + read-write + + + + + DDRCTRL_RFSHCTL3 + DDRCTRL_RFSHCTL3 + DDRCTRL refresh control register 3 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS_AUTO_REFRESH + When '1', disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. +When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRCTRL. +If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. +(DDR4 only) If FGR mode is enabled (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. +This register field is changeable on the fly. +Programming mode: Dynamic - Refresh Related + 0 + 1 + read-write + + + REFRESH_UPDATE_LEVEL + Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. +refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). +The refresh register(s) are automatically updated when exiting reset. +Programming mode: Dynamic + 1 + 1 + read-write + + + + + DDRCTRL_RFSHTMG + DDRCTRL_RFSHTMG + DDRCTRL refresh timing register + 0x64 + 0x20 + 0x0062008C + 0xFFFFFFFF + + + T_RFC_MIN + tRFC (min): Minimum time from refresh to refresh or activate. +When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). +When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). +In LPDDR2/LPDDR3/LPDDR4 mode: +- If using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab +- If using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb +In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. +Unit: Clocks. +Programming mode: Dynamic - Refresh Related + 0 + 10 + read-write + + + LPDDR3_TREFBW_EN + Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: +- 0 - tREFBW parameter not used +- 1 - tREFBW parameter used +Programming mode: Static + 15 + 1 + read-write + + + T_RFC_NOM_X1_X32 + tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). +For LPDDR2/LPDDR3/LPDDR4: +- If using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab +- If using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb +When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. +In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. +Note that if RFSHTMG.t_rfc_nom_x1_sel == 1, RFSHTMG.t_rfc_nom_x1_x32 must be greater than RFSHTMG.t_rfc_min; if RFSHTMG.t_rfc_nom_x1_sel == 0, RFSHTMG.t_rfc_nom_x1_x32 * 32 must be greater than RFSHTMG.t_rfc_min; RFSHTMG.t_rfc_nom_x1_x32 must be greater than 0x1. +- Non-DDR4 or DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0xFFE. +- DDR4 Fixed 2x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0x7FF. +- DDR4 Fixed 4x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0x3FF. +Unit: Clocks or multiples of 32 clocks, depending on RFSHTMG.t_rfc_nom_x1_sel. +Programming mode: Dynamic - Refresh Related + 16 + 12 + read-write + + + T_RFC_NOM_X1_SEL + Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. +Programming mode: Dynamic - Refresh Related + 31 + 1 + read-write + + + + + DDRCTRL_CRCPARCTL0 + DDRCTRL_CRCPARCTL0 + DDRCTRL CRC parity control register 0 + 0xc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFI_ALERT_ERR_INT_EN + Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. +Programming mode: Dynamic + 0 + 1 + read-write + + + DFI_ALERT_ERR_INT_CLR + Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. +Programming mode: Dynamic + 1 + 1 + read-write + + + DFI_ALERT_ERR_CNT_CLR + DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. +Programming mode: Dynamic + 2 + 1 + read-write + + + + + DDRCTRL_CRCPARSTAT + DDRCTRL_CRCPARSTAT + DDRCTRL CRC parity status register + 0xcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFI_ALERT_ERR_CNT + DFI alert error count. +If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. +Programming mode: Static + 0 + 16 + read-only + + + DFI_ALERT_ERR_INT + DFI alert error interrupt. +If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr +Programming mode: Static + 16 + 1 + read-only + + + + + DDRCTRL_INIT0 + DDRCTRL_INIT0 + DDRCTRL SDRAM initialization register 0 + 0xd0 + 0x20 + 0x0002004E + 0xFFFFFFFF + + + PRE_CKE_X1024 + Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. +Unit: 1024 DFI clock cycles. +DDR2 specifications typically require this to be programmed for a delay of >= 200 us. +LPDDR2/LPDDR3: tINIT1 of 100 ns (min) +LPDDR4: tINIT3 of 2 ms (min) +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +For DDR3/DDR4 RDIMMs, this should include the time needed to satisfy tSTAB +Programming mode: Static + 0 + 12 + read-write + + + POST_CKE_X1024 + Cycles to wait after driving CKE high to start the SDRAM initialization sequence. +Unit: 1024 DFI clock cycles. +DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. +LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. +LPDDR4 typically requires this to be programmed for a delay of 2 us. +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +Programming mode: Static + 16 + 10 + read-write + + + SKIP_DRAM_INIT + If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed +- 00 - SDRAM Initialization routine is run after power-up +- 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode +- 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode +- 10 - Reserved. +Programming mode: Quasi-dynamic Group 2 + 30 + 2 + read-write + + + + + DDRCTRL_INIT1 + DDRCTRL_INIT1 + DDRCTRL SDRAM initialization register 1 + 0xd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRE_OCD_X32 + Wait period before driving the OCD complete command to SDRAM. +Unit: Counts of a global timer that pulses every 32 DFI clock cycles. +There is no known specific requirement for this; it may be set to zero. +Programming mode: Static + 0 + 4 + read-write + + + DRAM_RSTN_X1024 + Number of cycles to assert SDRAM reset signal during init sequence. +This is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1. +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +Unit: 1024 DFI clock cycles. +Programming mode: Static + 16 + 9 + read-write + + + + + DDRCTRL_INIT2 + DDRCTRL_INIT2 + DDRCTRL SDRAM initialization register 2 + 0xd8 + 0x20 + 0x00000D05 + 0xFFFFFFFF + + + MIN_STABLE_CLOCK_X1 + Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. +LPDDR2/LPDDR3 typically requires 5 x tCK delay. +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +Unit: DFI clock cycles. +Programming mode: Static + 0 + 4 + read-write + + + IDLE_AFTER_RESET_X32 + Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +Unit: 32 DFI clock cycles. +Programming mode: Static + 8 + 8 + read-write + + + + + DDRCTRL_INIT3 + DDRCTRL_INIT3 + DDRCTRL SDRAM initialization register 3 + 0xdc + 0x20 + 0x00000510 + 0xFFFFFFFF + + + EMR + DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. +DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the DDRCTRL during write leveling. +mDDR: Value to write to EMR register. +LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register +Programming mode: Quasi-dynamic Group 4 + 0 + 16 + read-write + + + MR + DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. +DDR3/DDR4: Value loaded into MR0 register. +mDDR: Value to write to MR register. +LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register +Programming mode: Quasi-dynamic Group 1 and Group 4 + 16 + 16 + read-write + + + + + DDRCTRL_INIT4 + DDRCTRL_INIT4 + DDRCTRL SDRAM initialization register 4 + 0xe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EMR3 + DDR2: Value to write to EMR3 register. +DDR3/DDR4: Value to write to MR3 register +mDDR/LPDDR2/LPDDR3: Unused +LPDDR4: Value to write to MR13 register +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 16 + read-write + + + EMR2 + DDR2: Value to write to EMR2 register. +DDR3/DDR4: Value to write to MR2 register +LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register +mDDR: Unused +Programming mode: Quasi-dynamic Group 4 + 16 + 16 + read-write + + + + + DDRCTRL_INIT5 + DDRCTRL_INIT5 + DDRCTRL SDRAM initialization register 5 + 0xe4 + 0x20 + 0x00100004 + 0xFFFFFFFF + + + MAX_AUTO_INIT_X1024 + Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. +LPDDR2/LPDDR3 typically requires 10 us. +Unit: 1024 DFI clock cycles. +Programming mode: Static + 0 + 10 + read-write + + + DEV_ZQINIT_X32 + ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. +DDR3 typically requires 512 SDRAM clock cycles. +DDR4 requires 1024 SDRAM clock cycles. +LPDDR2/LPDDR3 requires 1 us. +When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. +Unit: 32 DFI clock cycles. +Programming mode: Static + 16 + 8 + read-write + + + + + DDRCTRL_DIMMCTL + DDRCTRL_DIMMCTL + DDRCTRL DIMM control register + 0xf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIMM_STAGGER_CS_EN + Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. +Note: Even if this bit is set it does not take care of software driven MR commands (via MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. +- 1 - (DDR4) Send MRS commands to each ranks separately +- 1 - (non-DDR4) Send all commands to even and odd ranks separately +- 0 - Do not stagger accesses +Programming mode: Static. + 0 + 1 + read-write + + + DIMM_ADDR_MIRR_EN + Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). +Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the DDRCTRL to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. +Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. +This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. +Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. +- 1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) +- 0 - Do not implement address mirroring +Programming mode: Static + 1 + 1 + read-write + + + + + DDRCTRL_DRAMTMG0 + DDRCTRL_DRAMTMG0 + DDRCTRL SDRAM timing register 0 + 0x100 + 0x20 + 0x0F101B0F + 0xFFFFFFFF + + + T_RAS_MIN + tRAS(min): Minimum time between activate and precharge to the same bank. +When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. +When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 0 + 6 + read-write + + + T_RAS_MAX + tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open +Minimum value of this register is 1. Zero is invalid. +When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. +Unit: Multiples of 1024 clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 8 + 7 + read-write + + + T_FAW + tFAW Valid only when 8 or more banks(or banks x bank groups) are present. +In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. +When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. +In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. +Unit: Clocks +Programming mode: Quasi-dynamic Group 2 and Group 4. + 16 + 6 + read-write + + + WR2PRE + Minimum time between write and precharge to same bank. +Unit: Clocks +Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies +where: +- WL = write latency +- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. +- tWR = Write recovery time. This comes directly from the SDRAM specification. +Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. +When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. +When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. +Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4. + 24 + 7 + read-write + + + + + DDRCTRL_DRAMTMG1 + DDRCTRL_DRAMTMG1 + DDRCTRL SDRAM timing register 1 + 0x104 + 0x20 + 0x00080414 + 0xFFFFFFFF + + + T_RC + tRC: Minimum time between activates to same bank. +When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 0 + 7 + read-write + + + RD2PRE + tRTP: Minimum time from read to precharge of same bank. +- DDR2: tAL + BL/2 + max(tRTP, 2) - 2 +- DDR3: tAL + max (tRTP, 4) +- DDR4: Max of following two equations: +tAL + max (tRTP, 4) or, +RL + BL/2 - tRP (*). +- mDDR: BL/2 +- LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: +LPDDR2-S2: BL/2 + tRTP - 1. +LPDDR2-S4: BL/2 + max(tRTP,2) - 2. +- LPDDR3: BL/2 + max(tRTP,4) - 4 +- LPDDR4: BL/2 + max(tRTP,8) - 8 +(*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. +When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. +When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4 + 8 + 6 + read-write + + + T_XP + tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. +If C/A parity for DDR4 is used, set to (tXP+PL) instead. +If LPDDR4 is selected and its spec has tCKELPD parameter, set to the larger of tXP and tCKELPD instead. +When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. +Units: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 16 + 5 + read-write + + + + + DDRCTRL_DRAMTMG2 + DDRCTRL_DRAMTMG2 + DDRCTRL SDRAM timing register 2 + 0x108 + 0x20 + 0x0305060D + 0xFFFFFFFF + + + WR2RD + DDR4: CWL + PL + BL/2 + tWTR_L +LPDDR2/3/4: WL + BL/2 + tWTR + 1 +Others: CWL + BL/2 + tWTR +In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. +Unit: Clocks. +Where: +- CWL = CAS write latency +- WL = Write latency +- PL = Parity latency +- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM +- tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. +- tWTR = internal write to read command delay. This comes directly from the SDRAM specification. +Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. +When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4 + 0 + 6 + read-write + + + RD2WR + DDR2/3/mDDR: RL + BL/2 + 2 - WL +DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL +LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL +LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL +LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see the relevant PHY databook for details of what should be included here. +Unit: Clocks. +Where: +- WL = write latency +- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM +- RL = read latency = CAS latency +- WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. +- RD_POSTAMBLE = read postamble. This is unique to LPDDR4. +For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. +When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. +Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4 + 8 + 6 + read-write + + + READ_LATENCY + Set to RL +The time from read command to read data on SDRAM interface. This must be set to RL. +Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. +When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. +This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols. +Unit: clocks. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4. + 16 + 6 + read-write + + + WRITE_LATENCY + Set to WL +The time from write command to write data on SDRAM interface. This must be set to WL. +For mDDR, it should normally be set to 1. +Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. +When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. +This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols. +Unit: clocks. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4. + 24 + 6 + read-write + + + + + DDRCTRL_DRAMTMG3 + DDRCTRL_DRAMTMG3 + DDRCTRL SDRAM timing register 3 + 0x10c + 0x20 + 0x0050400C + 0xFFFFFFFF + + + T_MOD + tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. +If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. +If MPR writes for DDR4 are used, set to tMOD + AL (or tMPD_PAR + AL if C/A parity is also used). +Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. +Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 10 + read-write + + + T_MRD + tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: +DDR2/mDDR: Time from MRS to any command +DDR3/4: Time from MRS to MRS command +LPDDR2: not used +LPDDR3/4: Time from MRS to non-MRS command. +When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. +If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 12 + 6 + read-write + + + T_MRW + Time to wait after a mode register write or read (MRW or MRR). +Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. +LPDDR2 typically requires value of 5. +LPDDR3 typically requires value of 10. +LPDDR4: Set this to the larger of tMRW and tMRWCKEL. +For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. +When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. +For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 20 + 10 + read-write + + + + + DDRCTRL_DRAMTMG4 + DDRCTRL_DRAMTMG4 + DDRCTRL SDRAM timing register 4 + 0x110 + 0x20 + 0x05040405 + 0xFFFFFFFF + + + T_RP + tRP: Minimum time from precharge to activate of same bank. +When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). +When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. +When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). +Unit: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 0 + 5 + read-write + + + T_RRD + DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. +Others: tRRD: Minimum time between activates from bank "a" to bank "b" +When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 8 + 4 + read-write + + + T_CCD + DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. +Others: tCCD: This is the minimum time between two reads or two writes. +When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. +Unit: clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 16 + 4 + read-write + + + T_RCD + tRCD - tAL: Minimum time from activate to read or write command to same bank. +When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. +Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4 + 24 + 5 + read-write + + + + + DDRCTRL_DRAMTMG5 + DDRCTRL_DRAMTMG5 + DDRCTRL SDRAM timing register 5 + 0x114 + 0x20 + 0x05050403 + 0xFFFFFFFF + + + T_CKE + Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. +- LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR +- LPDDR4 mode: Set this to the larger of tCKE or tSR. +- Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. +When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. +Unit: Clocks. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 5 + read-write + + + T_CKESR + Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. +Recommended settings: +- mDDR: tRFC +- LPDDR2: tCKESR +- LPDDR3: tCKESR +- LPDDR4: max(tCKE, tSR) +- DDR2: tCKE +- DDR3: tCKE + 1 +- DDR4: tCKE + 1 (+ PL(parity latency)(*)) +(*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 8 + 6 + read-write + + + T_CKSRE + This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. +Recommended settings: +- mDDR: 0 +- LPDDR2: 2 +- LPDDR3: 2 +- LPDDR4: tCKELCK +- DDR2: 1 +- DDR3: max (10 ns, 5 tCK) +- DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) +(*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 16 + 4 + read-write + + + T_CKSRX + This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. +Recommended settings: +- mDDR: 1 +- LPDDR2: 2 +- LPDDR3: 2 +- LPDDR4: tCKCKEH +- DDR2: 1 +- DDR3: tCKSRX +- DDR4: tCKSRX +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 24 + 4 + read-write + + + + + DDRCTRL_DRAMTMG6 + DDRCTRL_DRAMTMG6 + DDRCTRL SDRAM timing register 6 + 0x118 + 0x20 + 0x02020005 + 0xFFFFFFFF + + + T_CKCSX + This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. +Recommended settings: +- mDDR: 1 +- LPDDR2: tXP + 2 +- LPDDR3: tXP + 2 +- LPDDR4: tXP + 2 +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 4 + read-write + + + T_CKDPDX + This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. +Recommended settings: +- mDDR: 1 +- LPDDR2: 2 +- LPDDR3: 2 +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +This is only present for designs supporting mDDR or LPDDR2 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 16 + 4 + read-write + + + T_CKDPDE + This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. +Recommended settings: +- mDDR: 0 +- LPDDR2: 2 +- LPDDR3: 2 +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 24 + 4 + read-write + + + + + DDRCTRL_DRAMTMG7 + DDRCTRL_DRAMTMG7 + DDRCTRL SDRAM timing register 7 + 0x11c + 0x20 + 0x00000202 + 0xFFFFFFFF + + + T_CKPDX + This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. +Recommended settings: +- mDDR: 0 +- LPDDR2: 2 +- LPDDR3: 2 +- LPDDR4: 2 +When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksrx. +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 4 + read-write + + + T_CKPDE + This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. +Recommended settings: +- mDDR: 0 +- LPDDR2: 2 +- LPDDR3: 2 +- LPDDR4: tCKELCK +When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksre. +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 8 + 4 + read-write + + + + + DDRCTRL_DRAMTMG8 + DDRCTRL_DRAMTMG8 + DDRCTRL SDRAM timing register 8 + 0x120 + 0x20 + 0x00004405 + 0xFFFFFFFF + + + T_XS_X32 + tXS: Exit Self Refresh to commands not requiring a locked DLL. +When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. +Unit: Multiples of 32 clocks. +Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 7 + read-write + + + T_XS_DLL_X32 + tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. +When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. +Unit: Multiples of 32 clocks. +Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 8 + 7 + read-write + + + + + DDRCTRL_DRAMTMG14 + DDRCTRL_DRAMTMG14 + DDRCTRL SDRAM timing register 14 + 0x138 + 0x20 + 0x000000A0 + 0xFFFFFFFF + + + T_XSR + tXSR: Exit Self Refresh to any command. +When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. +Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. +Programming mode: Quasi-dynamic Group 2 and Group 4 + 0 + 12 + read-write + + + + + DDRCTRL_DRAMTMG15 + DDRCTRL_DRAMTMG15 + DDRCTRL SDRAM timing register 15 + 0x13c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + T_STAB_X32 + tSTAB: Stabilization time. +It is required in the following two cases for DDR3/DDR4 RDIMM: +- When exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB +- In the case of input clock frequency change (DDR4) +- After issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4). +When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. +Unit: Multiples of 32 clock cycles. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 0 + 8 + read-write + + + EN_DFI_LP_T_STAB + - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. +- 0 - Disable using tSTAB when exiting DFI LP +Programming mode: Quasi-dynamic Group 2 and Group 4. + 31 + 1 + read-write + + + + + DDRCTRL_ZQCTL0 + DDRCTRL_ZQCTL0 + DDRCTRL ZQ control register 0 + 0x180 + 0x20 + 0x02000040 + 0xFFFFFFFF + + + T_ZQ_SHORT_NOP + tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. +When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Static. + 0 + 10 + read-write + + + T_ZQ_LONG_NOP + tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. +When the controller is operating in 1:2 frequency ratio mode: +DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. +LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. +LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Static. + 16 + 11 + read-write + + + ZQ_RESISTOR_SHARED + - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. +- 0 - ZQ resistor is not shared. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Static. + 29 + 1 + read-write + + + DIS_SRX_ZQCL + - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. +- 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Quasi-dynamic Group 2 and Group 4. + 30 + 1 + read-write + + + DIS_AUTO_ZQ + - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. +- 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Dynamic + 31 + 1 + read-write + + + + + DDRCTRL_ZQCTL1 + DDRCTRL_ZQCTL1 + DDRCTRL ZQ control register 1 + 0x184 + 0x20 + 0x02000100 + 0xFFFFFFFF + + + T_ZQ_SHORT_INTERVAL_X1024 + Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. +Meaningless, if ZQCTL0.dis_auto_zq=1. +Unit: 1024 DFI clock cycles. +This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Static. + 0 + 20 + read-write + + + T_ZQ_RESET_NOP + tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. +When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and round it up to the next integer value. +This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Static. + 20 + 10 + read-write + + + + + DDRCTRL_ZQCTL2 + DDRCTRL_ZQCTL2 + DDRCTRL ZQ control register 2 + 0x188 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ZQ_RESET + Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. +For Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) it is scheduled after SR(except LPDDR4) or SPRD(LPDDR4) has been exited. +For Deep power down, it is not scheduled, although ZQSTAT.zq_reset_busy is de-asserted. +This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. +Programming mode: Dynamic + 0 + 1 + read-write + + + + + DDRCTRL_ZQSTAT + DDRCTRL_ZQSTAT + DDRCTRL ZQ status register + 0x18c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ZQ_RESET_BUSY + SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. +- 0 - Indicates that the SoC core can initiate a ZQ Reset operation +- 1 - Indicates that ZQ Reset operation is in progress +Programming mode: Dynamic + 0 + 1 + read-only + + + + + DDRCTRL_DFITMG0 + DDRCTRL_DFITMG0 + DDRCTRL DFI timing register 0 + 0x190 + 0x20 + 0x07020002 + 0xFFFFFFFF + + + DFI_TPHY_WRLAT + Write latency +Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. +Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. +For LPDDR4, dfi_tphy_wrlat>60 is not supported. +Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk. +Programming mode: Quasi-dynamic Group 1 and Group 4 + 0 + 6 + read-write + + + DFI_TPHY_WRDATA + Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. +Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk. +Programming mode: Quasi-dynamic Group 4 + 8 + 6 + read-write + + + DFI_T_RDDATA_EN + Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. +Refer to PHY specification for correct value. +This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. +Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_dfi_phy_clk. +Programming mode: Quasi-dynamic Group 1 and Group 4 + 16 + 7 + read-write + + + DFI_T_CTRL_DELAY + Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock. +Programming mode: Quasi-dynamic Group 4 + 24 + 5 + read-write + + + + + DDRCTRL_DFITMG1 + DDRCTRL_DFITMG1 + DDRCTRL DFI timing register 1 + 0x194 + 0x20 + 0x00000404 + 0xFFFFFFFF + + + DFI_T_DRAM_CLK_ENABLE + Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +Programming mode: Quasi-dynamic Group 4 + 0 + 5 + read-write + + + DFI_T_DRAM_CLK_DISABLE + Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +Programming mode: Quasi-dynamic Group 4 + 8 + 5 + read-write + + + DFI_T_WRDATA_DELAY + Specifies the number of DFI clock cycles between when the dfi_wrdata_en +signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. +This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. +For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. +For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). +Value to be programmed is in terms of DFI clocks, not PHY clocks. +In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. +If using DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value. +Unit: Clocks +Programming mode: Quasi-dynamic Group 4 + 16 + 5 + read-write + + + + + DDRCTRL_DFILPCFG0 + DDRCTRL_DFILPCFG0 + DDRCTRL low power configuration register 0 + 0x198 + 0x20 + 0x07000000 + 0xFFFFFFFF + + + DFI_LP_EN_PD + Enables DFI Low Power interface handshaking during Power Down Entry/Exit. +- 0 - Disabled +- 1 - Enabled +Programming mode: Static + 0 + 1 + read-write + + + DFI_LP_WAKEUP_PD + Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. +Determines the DFI's tlp_wakeup time: +- 0x0 - 16 cycles +- 0x1 - 32 cycles +- 0x2 - 64 cycles +- 0x3 - 128 cycles +- 0x4 - 256 cycles +- 0x5 - 512 cycles +- 0x6 - 1024 cycles +- 0x7 - 2048 cycles +- 0x8 - 4096 cycles +- 0x9 - 8192 cycles +- 0xA - 16384 cycles +- 0xB - 32768 cycles +- 0xC - 65536 cycles +- 0xD - 131072 cycles +- 0xE - 262144 cycles +- 0xF - Unlimited +Programming mode: Static + 4 + 4 + read-write + + + DFI_LP_EN_SR + Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. +- 0 - Disabled +- 1 - Enabled +Programming mode: Static + 8 + 1 + read-write + + + DFI_LP_WAKEUP_SR + Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. +Determines the DFI's tlp_wakeup time: +- 0x0 - 16 cycles +- 0x1 - 32 cycles +- 0x2 - 64 cycles +- 0x3 - 128 cycles +- 0x4 - 256 cycles +- 0x5 - 512 cycles +- 0x6 - 1024 cycles +- 0x7 - 2048 cycles +- 0x8 - 4096 cycles +- 0x9 - 8192 cycles +- 0xA - 16384 cycles +- 0xB - 32768 cycles +- 0xC - 65536 cycles +- 0xD - 131072 cycles +- 0xE - 262144 cycles +- 0xF - Unlimited +Programming mode: Static + 12 + 4 + read-write + + + DFI_LP_EN_DPD + Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. +- 0 - Disabled +- 1 - Enabled +This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. +Programming mode: Static. + 16 + 1 + read-write + + + DFI_LP_WAKEUP_DPD + Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. +Determines the DFI's tlp_wakeup time: +- 0x0 - 16 cycles +- 0x1 - 32 cycles +- 0x2 - 64 cycles +- 0x3 - 128 cycles +- 0x4 - 256 cycles +- 0x5 - 512 cycles +- 0x6 - 1024 cycles +- 0x7 - 2048 cycles +- 0x8 - 4096 cycles +- 0x9 - 8192 cycles +- 0xA - 16384 cycles +- 0xB - 32768 cycles +- 0xC - 65536 cycles +- 0xD - 131072 cycles +- 0xE - 262144 cycles +- 0xF - Unlimited +This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. +Programming mode: Static. + 20 + 4 + read-write + + + DFI_TLP_RESP + Setting in DFI clock cycles for DFI's tlp_resp time. +Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. +DFI 2.1 specification onwards, recommends using a fixed value of 7 always. +Programming mode: Static + 24 + 5 + read-write + + + + + DDRCTRL_DFIUPD0 + DDRCTRL_DFIUPD0 + DDRCTRL DFI update register 0 + 0x1a0 + 0x20 + 0x00400003 + 0xFFFFFFFF + + + DFI_T_CTRLUP_MIN + Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. +Programming mode: Static + 0 + 10 + read-write + + + DFI_T_CTRLUP_MAX + Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. +Programming mode: Static + 16 + 10 + read-write + + + CTRLUPD_PRE_SRX + Selects dfi_ctrlupd_req requirements at SRX: +-0: send ctrlupd after SRX +-1: send ctrlupd before SRX +If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req is issued when SRX. +Programming mode: Static + 29 + 1 + read-write + + + DIS_AUTO_CTRLUPD_SRX + When '1', disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. +When '0', DDRCTRL issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. +Programming mode: Static + 30 + 1 + read-write + + + DIS_AUTO_CTRLUPD + When '1', disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. +When '0', DDRCTRL issues dfi_ctrlupd_req periodically. +Programming mode: Quasi-dynamic Group 3 + 31 + 1 + read-write + + + + + DDRCTRL_DFIUPD1 + DDRCTRL_DFIUPD1 + DDRCTRL DFI update register 1 + 0x1a4 + 0x20 + 0x00010001 + 0xFFFFFFFF + + + DFI_T_CTRLUPD_INTERVAL_MAX_X1024 + This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. +Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. +Unit: 1024 DFI clock cycles. +Programming mode: Static. + 0 + 8 + read-write + + + DFI_T_CTRLUPD_INTERVAL_MIN_X1024 + This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. +Unit: 1024 DFI clock cycles. +Programming mode: Static. + 16 + 8 + read-write + + + + + DDRCTRL_DFIUPD2 + DDRCTRL_DFIUPD2 + DDRCTRL DFI update register 2 + 0x1a8 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + DFI_PHYUPD_EN + Enables the support for acknowledging PHY-initiated updates: +- 0 - Disabled +- 1 - Enabled +Programming mode: Static + 31 + 1 + read-write + + + + + DDRCTRL_DFIMISC + DDRCTRL_DFIMISC + DDRCTRL DFI miscellaneous control register + 0x1b0 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + DFI_INIT_COMPLETE_EN + PHY initialization complete enable signal. +When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation +Programming mode: Quasi-dynamic Group 3 + 0 + 1 + read-write + + + CTL_IDLE_EN + Enables support of ctl_idle signal +Programming mode: Static + 4 + 1 + read-write + + + DFI_INIT_START + PHY init start request signal.When asserted it triggers the PHY init start request +Programming mode: Quasi-dynamic Group 3 + 5 + 1 + read-write + + + DFI_FREQUENCY + Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. +Programming mode: Quasi-dynamic Group 1 + 8 + 5 + read-write + + + + + DDRCTRL_DFISTAT + DDRCTRL_DFISTAT + DDRCTRL DFI status register + 0x1bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFI_INIT_COMPLETE + The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. +Programming mode: Dynamic + 0 + 1 + read-only + + + DFI_LP_ACK + Stores the value of the dfi_lp_ack input to the controller. +Programming mode: Dynamic + 1 + 1 + read-only + + + + + DDRCTRL_DFIPHYMSTR + DDRCTRL_DFIPHYMSTR + DDRCTRL DFI PHY master register + 0x1c4 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + DFI_PHYMSTR_EN + Enables the PHY Master Interface: +- 0 - Disabled +- 1 - Enabled +Programming mode: Dynamic + 0 + 1 + read-write + + + + + DDRCTRL_ADDRMAP1 + DDRCTRL_ADDRMAP1 + DDRCTRL address map register 1 + 0x204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_BANK_B0 + Selects the HIF address bits used as bank address bit 0. +Valid Range: 0 to 32, and 63 +Internal Base: 2 +The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. +If unused, set to 63 and then bank address bit 0 is set to 0. +Programming mode: Static. + 0 + 6 + read-write + + + ADDRMAP_BANK_B1 + Selects the HIF address bits used as bank address bit 1. +Valid Range: 0 to 32, and 63 +Internal Base: 3 +The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. +If unused, set to 63 and then bank address bit 1 is set to 0. +Programming mode: Static. + 8 + 6 + read-write + + + ADDRMAP_BANK_B2 + Selects the HIF address bit used as bank address bit 2. +Valid Range: 0 to 31, and 63 +Internal Base: 4 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 63 and then bank address bit 2 is set to 0. +Programming mode: Static. + 16 + 6 + read-write + + + + + DDRCTRL_ADDRMAP2 + DDRCTRL_ADDRMAP2 + DDRCTRL address map register 2 + 0x208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_COL_B2 + - Full bus width mode: Selects the HIF address bit used as column address bit 2. +- Half bus width mode: Selects the HIF address bit used as column address bit 3. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 4. +Valid Range: 0 to 7 +Internal Base: 2 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to program this to 0 unless: +- in Half or Quarter bus width (MSTR.data_bus_width!=00) and +- PCCFG.bl_exp_mode==1 and either +- In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or +- In LPDDR4 and ADDRMAP1.addrmap_bank_b0==0 +If UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0 unless: +- in Half or Quarter bus width (MSTR.data_bus_width!=00) and +- PCCFG.bl_exp_mode==1 and +- In DDR4 and ADDRMAP8.addrmap_bg_b0==0 +Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. +If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. +If MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0 so that HIF[2] maps to column address bit 3. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_COL_B3 + - Full bus width mode: Selects the HIF address bit used as column address bit 3. +- Half bus width mode: Selects the HIF address bit used as column address bit 4. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 5. +Valid Range: 0 to 7 +Internal Base: 3 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note, if UMCTL2_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0. +Programming mode: Static + 8 + 4 + read-write + + + ADDRMAP_COL_B4 + - Full bus width mode: Selects the HIF address bit used as column address bit 4. +- Half bus width mode: Selects the HIF address bit used as column address bit 5. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 6. +Valid Range: 0 to 7, and 15 +Internal Base: 4 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then this column address bit is set to 0. +Programming mode: Static + 16 + 4 + read-write + + + ADDRMAP_COL_B5 + - Full bus width mode: Selects the HIF address bit used as column address bit 5. +- Half bus width mode: Selects the HIF address bit used as column address bit 6. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . +Valid Range: 0 to 7, and 15 +Internal Base: 5 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then this column address bit is set to 0. +Programming mode: Static + 24 + 4 + read-write + + + + + DDRCTRL_ADDRMAP3 + DDRCTRL_ADDRMAP3 + DDRCTRL address map register 3 + 0x20c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_COL_B6 + - Full bus width mode: Selects the HIF address bit used as column address bit 6. +- Half bus width mode: Selects the HIF address bit used as column address bit 7. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 8. +Valid Range: 0 to 7, and 15 +Internal Base: 6 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then this column address bit is set to 0. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_COL_B7 + - Full bus width mode: Selects the HIF address bit used as column address bit 7. +- Half bus width mode: Selects the HIF address bit used as column address bit 8. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 9. +Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. +Internal Base: 7 +The selected HIF address bit is determined by adding the internal base to the value of this field. +In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. +If column bit 7 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base). +If unused, set to 31 and then this column address bit is set to 0. +Programming mode: Static. + 8 + 5 + read-write + + + ADDRMAP_COL_B8 + - Full bus width mode: Selects the HIF address bit used as column address bit 8. +- Half bus width mode: Selects the HIF address bit used as column address bit 9. +- Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). +Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. +Internal Base: 8 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. +In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. +If column bit 8 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base). +If column bit 8 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base). +If unused, set to 31 and then this column address bit is set to 0. +Programming mode: Static. + 16 + 5 + read-write + + + ADDRMAP_COL_B9 + - Full bus width mode: Selects the HIF address bit used as column address bit 9. +- Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). +- Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). +Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. +Internal Base: 9 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. +In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. +If column bit 9 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) +If column bit 9 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) +If column bit 9 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) +If unused, set to 31 and then this column address bit is set to 0. +Programming mode: Static. + 24 + 5 + read-write + + + + + DDRCTRL_ADDRMAP4 + DDRCTRL_ADDRMAP4 + DDRCTRL address map register 4 + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_COL_B10 + - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). +- Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). +- Quarter bus width mode: UNUSED. See later in this description for value you need to set to make it unused. +Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. +Internal Base: 10 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. +In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. +If column bit 10 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) +If column bit 10 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) +If column bit 10 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) +If unused, set to 31 and then this column address bit is set to 0. +Programming mode: Static + 0 + 5 + read-write + + + ADDRMAP_COL_B11 + - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). +- Half bus width mode: UNUSED. See later in this description for value you need to set to make it unused. +- Quarter bus width mode: UNUSED. See later in this description for value you need to set to make it unused. +Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. +Internal Base: 11 +The selected HIF address bit is determined by adding the internal base to the value of this field. +Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. +In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. +In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. +If column bit 11 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) +If column bit 11 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) +If column bit 11 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) +If unused, set to 31 and then this column address bit is set to 0. +Programming mode: Static + 8 + 5 + read-write + + + + + DDRCTRL_ADDRMAP5 + DDRCTRL_ADDRMAP5 + DDRCTRL address map register 5 + 0x214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_ROW_B0 + Selects the HIF address bits used as row address bit 0. +Valid Range: 0 to 11 +Internal Base: 6 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_ROW_B1 + Selects the HIF address bits used as row address bit 1. +Valid Range: 0 to 11 +Internal Base: 7 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +Programming mode: Static + 8 + 4 + read-write + + + ADDRMAP_ROW_B2_10 + Selects the HIF address bits used as row address bits 2 to 10. +Valid Range: 0 to 11, and 15 +Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. +When set to 15, the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +Programming mode: Static + 16 + 4 + read-write + + + ADDRMAP_ROW_B11 + Selects the HIF address bit used as row address bit 11. +Valid Range: 0 to 11, and 15 +Internal Base: 17 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then row address bit 11 is set to 0. +Programming mode: Static + 24 + 4 + read-write + + + + + DDRCTRL_ADDRMAP6 + DDRCTRL_ADDRMAP6 + DDRCTRL address register 6 + 0x218 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_ROW_B12 + Selects the HIF address bit used as row address bit 12. +Valid Range: 0 to 11, and 15 +Internal Base: 18 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then row address bit 12 is set to 0. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_ROW_B13 + Selects the HIF address bit used as row address bit 13. +Valid Range: 0 to 11, and 15 +Internal Base: 19 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then row address bit 13 is set to 0. +Programming mode: Static + 8 + 4 + read-write + + + ADDRMAP_ROW_B14 + Selects the HIF address bit used as row address bit 14. +Valid Range: 0 to 11, and 15 +Internal Base: 20 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then row address bit 14 is set to 0. +Programming mode: Static + 16 + 4 + read-write + + + ADDRMAP_ROW_B15 + Selects the HIF address bit used as row address bit 15. +Valid Range: 0 to 11, and 15 +Internal Base: 21 +The selected HIF address bit is determined by adding the internal base to the value of this field. +If unused, set to 15 and then row address bit 15 is set to 0. +Programming mode: Static + 24 + 4 + read-write + + + LPDDR3_6GB_12GB + Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. +- 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid +- 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid +Present only in designs configured to support LPDDR3. +Programming mode: Static + 31 + 1 + read-write + + + + + DDRCTRL_ADDRMAP9 + DDRCTRL_ADDRMAP9 + DDRCTRL address map register 9 + 0x224 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_ROW_B2 + Selects the HIF address bits used as row address bit 2. +Valid Range: 0 to 11 +Internal Base: 8 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_ROW_B3 + Selects the HIF address bits used as row address bit 3. +Valid Range: 0 to 11 +Internal Base: 9 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 8 + 4 + read-write + + + ADDRMAP_ROW_B4 + Selects the HIF address bits used as row address bit 4. +Valid Range: 0 to 11 +Internal Base: 10 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 16 + 4 + read-write + + + ADDRMAP_ROW_B5 + Selects the HIF address bits used as row address bit 5. +Valid Range: 0 to 11 +Internal Base: 11 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 24 + 4 + read-write + + + + + DDRCTRL_ADDRMAP10 + DDRCTRL_ADDRMAP10 + DDRCTRL address map register 10 + 0x228 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_ROW_B6 + Selects the HIF address bits used as row address bit 6. +Valid Range: 0 to 11 +Internal Base: 12 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 0 + 4 + read-write + + + ADDRMAP_ROW_B7 + Selects the HIF address bits used as row address bit 7. +Valid Range: 0 to 11 +Internal Base: 13 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 8 + 4 + read-write + + + ADDRMAP_ROW_B8 + Selects the HIF address bits used as row address bit 8. +Valid Range: 0 to 11 +Internal Base: 14 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 16 + 4 + read-write + + + ADDRMAP_ROW_B9 + Selects the HIF address bits used as row address bit 9. +Valid Range: 0 to 11 +Internal Base: 15 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 24 + 4 + read-write + + + + + DDRCTRL_ADDRMAP11 + DDRCTRL_ADDRMAP11 + DDRCTRL address map register 11 + 0x22c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRMAP_ROW_B10 + Selects the HIF address bits used as row address bit 10. +Valid Range: 0 to 11 +Internal Base: 16 +The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. +Programming mode: Static + 0 + 4 + read-write + + + + + DDRCTRL_ODTCFG + DDRCTRL_ODTCFG + DDRCTRL ODT configuration register + 0x240 + 0x20 + 0x04000400 + 0xFFFFFFFF + + + RD_ODT_DELAY + The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. +Recommended values: +DDR2: +- CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) +If (CL + AL - 4 < 0), DDRCTRL does not support ODT for read operation. +DDR3: +- CL - CWL +DDR4: +- CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) +WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) +RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) +If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRCTRL does not support ODT for read operation. +LPDDR3: +- RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) +Programming mode: Quasi-dynamic Group 1 and Group 4. + 2 + 5 + read-write + + + RD_ODT_HOLD + DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. +Recommended values: +DDR2: +- BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) +- BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) +DDR3: +- BL8 - 0x6 +DDR4: +- BL8: 5 + RD_PREAMBLE +RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) +LPDDR3: +- BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) +Programming mode: Quasi-dynamic Group 1 and Group 4 + 8 + 4 + read-write + + + WR_ODT_DELAY + The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. +Recommended values: +DDR2: +- CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) +If (CWL + AL - 3 < 0), DDRCTRL does not support ODT for write operation. +DDR3: +- 0x0 +DDR4: +- DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) +LPDDR3: +- WL - 1 - RU(tODTon(max)/tCK)) +Programming mode: Quasi-dynamic Group 1 and Group 4 + 16 + 5 + read-write + + + WR_ODT_HOLD + DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. +Recommended values: +DDR2: +- BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) +- BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) +DDR3: +- BL8: 0x6 +DDR4: +- BL8: 5 + WR_PREAMBLE + CRC_MODE +WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) +CRC_MODE = 0 (not CRC mode), 1 (CRC mode) +LPDDR3: +- BL8: 7 + RU(tODTon(max)/tCK) +Programming mode: Quasi-dynamic Group 1 and Group 4 + 24 + 4 + read-write + + + + + DDRCTRL_ODTMAP + DDRCTRL_ODTMAP + DDRCTRL ODT/Rank map register + 0x244 + 0x20 + 0x00000011 + 0xFFFFFFFF + + + RANK0_WR_ODT + Indicates which remote ODTs must be turned on during a write to rank 0. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Programming mode: Static + 0 + 1 + read-write + + + RANK0_RD_ODT + Indicates which remote ODTs must be turned on during a read from rank 0. +Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. +Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. +For each rank, set its bit to 1 to enable its ODT. +Programming mode: Static + 4 + 1 + read-write + + + + + DDRCTRL_SCHED + DDRCTRL_SCHED + DDRCTRL scheduler control register + 0x250 + 0x20 + 0x00000805 + 0xFFFFFFFF + + + FORCE_LOW_PRI_N + Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. +For performance only. +Programming mode: Static + 0 + 1 + read-write + + + PREFER_WRITE + If set then the bank selector prefers writes over reads. +FOR DEBUG ONLY. +Programming mode: Static + 1 + 1 + read-write + + + PAGECLOSE + If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. +If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). +The pageclose feature provids a midway between Open and Close page policies. +For performance only. +Programming mode: Quasi-dynamic Group 3 + 2 + 1 + read-write + + + LPR_NUM_ENTRIES + Number of entries in the low priority transaction store is this value + 1. +(MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. +Setting this to maximum value allocates all entries to low priority transaction store. +Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. +Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. +Programming mode: Static + 8 + 4 + read-write + + + GO2CRITICAL_HYSTERESIS + UNUSED +Programming mode: Static + 16 + 8 + read-write + + + RDWR_IDLE_GAP + When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. +The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. +When prefer write over read is set this is reversed. +0x0 is a legal value for this register. When set to 0x0, the transaction store switching happens immediately when the switching conditions become true. +FOR PERFORMANCE ONLY +Programming mode: Static + 24 + 7 + read-write + + + + + DDRCTRL_SCHED1 + DDRCTRL_SCHED1 + DDRCTRL scheduler control register 1 + 0x254 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAGECLOSE_TIMER + This field works in conjunction with SCHED.pageclose. +It only has meaning if SCHED.pageclose==1. +If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read +or write command in the CAM with a bank and page hit. +Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. +If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read +or write command in the CAM with a bank and page hit. +Instead, a timer is started, with pageclose_timer as the initial value. +There is a timer on a per bank basis. +The timer decrements unless the next read or write in the CAM to a bank is a page hit. +It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. +Once the timer has reached zero, an explicit precharge is attempted to be scheduled. +Programming mode: Static. + 0 + 8 + read-write + + + + + DDRCTRL_PERFHPR1 + DDRCTRL_PERFHPR1 + DDRCTRL high priority read CAM register 1 + 0x25c + 0x20 + 0x0F000001 + 0xFFFFFFFF + + + HPR_MAX_STARVE + Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. +For performance only. +Programming mode: Quasi-dynamic Group 3 + 0 + 16 + read-write + + + HPR_XACT_RUN_LENGTH + Number of transactions that are serviced once the HPR queue goes critical is the smaller of: +- (a) This number +- (b) Number of transactions available. +Unit: Transaction. +For performance only. +Programming mode: Quasi-dynamic Group 3 + 24 + 8 + read-write + + + + + DDRCTRL_PERFLPR1 + DDRCTRL_PERFLPR1 + DDRCTRL low priority read CAM register 1 + 0x264 + 0x20 + 0x0F00007F + 0xFFFFFFFF + + + LPR_MAX_STARVE + Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. +For performance only +Programming mode: Quasi-dynamic Group 3 + 0 + 16 + read-write + + + LPR_XACT_RUN_LENGTH + Number of transactions that are serviced once the LPR queue goes critical is the smaller of: +- (a) This number +- (b) Number of transactions available. +Unit: Transaction. +For performance only +Programming mode: Quasi-dynamic group 3 + 24 + 8 + read-write + + + + + DDRCTRL_PERFWR1 + DDRCTRL_PERFWR1 + DDRCTRL write CAM register 1 + 0x26c + 0x20 + 0x0F00007F + 0xFFFFFFFF + + + W_MAX_STARVE + Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. +For performance only. +Programming mode: Quasi-dynamic Group 3. + 0 + 16 + read-write + + + W_XACT_RUN_LENGTH + Number of transactions that are serviced once the WR queue goes critical is the smaller of: +- (a) This number +- (b) Number of transactions available. +Unit: Transaction. +For performance only. +Programming mode: Quasi-dynamic Group 3. + 24 + 8 + read-write + + + + + DDRCTRL_DBG0 + DDRCTRL_DBG0 + DDRCTRL debug register 0 + 0x300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS_WC + When 1, disable write combine. +FOR DEBUG ONLY +Programming mode: Static + 0 + 1 + read-write + + + DIS_COLLISION_PAGE_OPT + When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). +FOR DEBUG ONLY. +Programming mode: Static + 4 + 1 + read-write + + + + + DDRCTRL_DBG1 + DDRCTRL_DBG1 + DDRCTRL debug register 1 + 0x304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIS_DQ + When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. +This bit may be used to prevent reads or writes being issued by the DDRCTRL, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This ensures that the relevant logic in the DDRC is idle. +This bit is intended to be switched on-the-fly. +Programming mode: Dynamic + 0 + 1 + read-write + + + DIS_HIF + When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. +This bit is intended to be switched on-the-fly. +Programming mode: Dynamic + 1 + 1 + read-write + + + + + DDRCTRL_DBGCAM + DDRCTRL_DBGCAM + DDRCTRL CAM debug register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_HPR_Q_DEPTH + High priority read queue depth +For debug only. +Programming mode: Dynamic + 0 + 5 + read-only + + + DBG_LPR_Q_DEPTH + Low priority read queue depth +The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. +For debug only. +Programming mode: Dynamic + 8 + 5 + read-only + + + DBG_W_Q_DEPTH + Write queue depth +The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. +For debug only. +Programming mode: Dynamic + 16 + 5 + read-only + + + DBG_STALL + Stall +For debug only. +Programming mode: Dynamic + 24 + 1 + read-only + + + DBG_RD_Q_EMPTY + When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. +An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. +For debug only. +Programming mode: Dynamic + 25 + 1 + read-only + + + DBG_WR_Q_EMPTY + When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. +An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. +For debug only. +Programming mode: Dynamic. + 26 + 1 + read-only + + + RD_DATA_PIPELINE_EMPTY + This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. +Programming mode: Dynamic. + 28 + 1 + read-only + + + WR_DATA_PIPELINE_EMPTY + This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. +Programming mode: Dynamic. + 29 + 1 + read-only + + + + + DDRCTRL_DBGCMD + DDRCTRL_DBGCMD + DDRCTRL command debug register + 0x30c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RANK0_REFRESH + Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. +For 3DS configuration, refresh is sent to rank index 0. +This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. +Programming mode: Dynamic. + 0 + 1 + read-write + + + ZQ_CALIB_SHORT + Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. +For self-refresh(except LPDDR4) or SR-powerdown(LPDDR4) it is scheduled after SR(except LPDDR4) or SPRD(LPDDR4) has been exited. +For Deep power down and maximum power saving mode, it is not scheduled, although DBGSTAT.zq_calib_short_busy is de-asserted. +Programming mode: Dynamic. + 4 + 1 + read-write + + + CTRLUPD + Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. +Programming mode: Dynamic. + 5 + 1 + read-write + + + + + DDRCTRL_DBGSTAT + DDRCTRL_DBGSTAT + DDRCTRL status debug register + 0x310 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RANK0_REFRESH_BUSY + SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. +- 0 - Indicates that the SoC core can initiate a rank0_refresh operation +- 1 - Indicates that rank0_refresh operation has not been stored yet in the DDRCTRL +Programming mode: Dynamic + 0 + 1 + read-only + + + ZQ_CALIB_SHORT_BUSY + SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. +- 0 - Indicates that the SoC core can initiate a ZQCS operation +- 1 - Indicates that ZQCS operation has not been initiated yet in the DDRCTRL +Programming mode: Dynamic + 4 + 1 + read-only + + + CTRLUPD_BUSY + SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. +- 0 - Indicates that the SoC core can initiate a ctrlupd operation +- 1 - Indicates that ctrlupd operation has not been initiated yet in the DDRCTRL +Programming mode: Dynamic + 5 + 1 + read-only + + + + + DDRCTRL_SWCTL + DDRCTRL_SWCTL + DDRCTRL software register programming control enable + 0x320 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + SW_DONE + Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. +Programming mode: Dynamic + 0 + 1 + read-write + + + + + DDRCTRL_SWSTAT + DDRCTRL_SWSTAT + DDRCTRL software register programming control status + 0x324 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + SW_DONE_ACK + Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. +Programming mode: Static + 0 + 1 + read-only + + + + + DDRCTRL_POISONCFG + DDRCTRL_POISONCFG + DDRCTRL AXI Poison configuration register + 0x36c + 0x20 + 0x00110011 + 0xFFFFFFFF + + + WR_POISON_SLVERR_EN + If set to 1, enables SLVERR response for write transaction poisoning +Programming mode: Dynamic + 0 + 1 + read-write + + + WR_POISON_INTR_EN + If set to 1, enables interrupts for write transaction poisoning +Programming mode: Dynamic + 4 + 1 + read-write + + + WR_POISON_INTR_CLR + Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. +Programming mode: Dynamic + 8 + 1 + read-write + + + RD_POISON_SLVERR_EN + If set to 1, enables SLVERR response for read transaction poisoning +Programming mode: Dynamic + 16 + 1 + read-write + + + RD_POISON_INTR_EN + If set to 1, enables interrupts for read transaction poisoning +Programming mode: Dynamic + 20 + 1 + read-write + + + RD_POISON_INTR_CLR + Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. +Programming mode: Dynamic + 24 + 1 + read-write + + + + + DDRCTRL_POISONSTAT + DDRCTRL_POISONSTAT + DDRCTRL AXI Poison status register + 0x370 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WR_POISON_INTR_0 + Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. +Programming mode: Dynamic + 0 + 1 + read-only + + + RD_POISON_INTR_0 + Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. +Programming mode: Dynamic + 16 + 1 + read-only + + + + + DDRCTRL_PSTAT + DDRCTRL_PSTAT + DDRCTRL port status register + 0x3fc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RD_PORT_BUSY_0 + Indicates if there are outstanding reads for AXI port 0. +Programming mode: Dynamic + 0 + 1 + read-only + + + WR_PORT_BUSY_0 + Indicates if there are outstanding writes for AXI port 0. +Programming mode: Dynamic + 16 + 1 + read-only + + + + + DDRCTRL_PCCFG + DDRCTRL_PCCFG + DDRCTRL port common configuration register + 0x400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GO2CRITICAL_EN + If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. +Programming mode: Static. + 0 + 1 + read-write + + + PAGEMATCH_LIMIT + Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. +Programming mode: Static. + 4 + 1 + read-write + + + BL_EXP_MODE + Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. +This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. +This can be used in cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if DDR4 or LPDDR4. +Note that if DBICTL.dm_en=0, functionality is not supported in the following cases: +- UMCTL2_PARTIAL_WR=0 +- UMCTL2_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) +- UMCTL2_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.burstchop=0 or CRCPARCTL1.crc_enable=1 +Functionality is also not supported if Data Channel Interleave is enabled. +Programming mode: Static. + 8 + 1 + read-write + + + + + DDRCTRL_PCFGR_0 + DDRCTRL_PCFGR_0 + DDRCTRL port x configuration read register + 0x404 + 0x20 + 0x00004000 + 0xFFFFFFFF + + + RD_PORT_PRIORITY + Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. +Note: The two LSBs of this register field are tied internally to 2'b00. +Programming mode: Static + 0 + 10 + read-write + + + RD_PORT_AGING_EN + If set to 1, enables aging function for the read channel of the port. +Programming mode: Static + 12 + 1 + read-write + + + RD_PORT_URGENT_EN + If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). +Programming mode: Static + 13 + 1 + read-write + + + RD_PORT_PAGEMATCH_EN + If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. +Programming mode: Static + 14 + 1 + read-write + + + RDWR_ORDERED_EN + Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. +Programming mode: Static. + 16 + 1 + read-write + + + + + DDRCTRL_PCFGW_0 + DDRCTRL_PCFGW_0 + DDRCTRL port x configuration write register + 0x408 + 0x20 + 0x00004000 + 0xFFFFFFFF + + + WR_PORT_PRIORITY + Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port's priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. +For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). +For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. +Note: The two LSBs of this register field are tied internally to 2'b00. +Programming mode: Static + 0 + 10 + read-write + + + WR_PORT_AGING_EN + If set to 1, enables aging function for the write channel of the port. +Programming mode: Static + 12 + 1 + read-write + + + WR_PORT_URGENT_EN + If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. +Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). +Programming mode: Static + 13 + 1 + read-write + + + WR_PORT_PAGEMATCH_EN + If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. +Programming mode: Static + 14 + 1 + read-write + + + + + DDRCTRL_PCTRL_0 + DDRCTRL_PCTRL_0 + DDRCTRL port x control register + 0x490 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PORT_EN + Enables AXI port n. +Programming mode: Dynamic + 0 + 1 + read-write + + + + + DDRCTRL_PCFGQOS0_0 + DDRCTRL_PCFGQOS0_0 + DDRCTRL port x read Q0S configuration register 0 + 0x494 + 0x20 + 0x02000E00 + 0xFFFFFFFF + + + RQOS_MAP_LEVEL1 + Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. +Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. +All of the map_level* registers must be set to distinct values. +Programming mode: Quasi-dynamic Group 3 + 0 + 4 + read-write + + + RQOS_MAP_REGION0 + This bitfield indicates the traffic class of region 0. +Valid values are: +-0: LPR, 1: VPR, 2: HPR. +For dual address queue configurations, region 0 maps to the blue address queue. +In this case, valid values are: +-0: LPR and 1: VPR only. +When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. +Programming mode: Quasi-dynamic Group 3 + 16 + 2 + read-write + + + RQOS_MAP_REGION1 + This bitfield indicates the traffic class of region 1. +Valid values are: +-0: LPR, +-1: VPR, +- 2: HPR. +For dual address queue configurations, region1 maps to the blue address queue. +In this case, valid values are +-0: LPR and +-1: VPR only. +When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. +Programming mode: Quasi-dynamic Group 3 + 20 + 2 + read-write + + + + + DDRCTRL_PCFGQOS1_0 + DDRCTRL_PCFGQOS1_0 + DDRCTRL port x read Q0S configuration register 1 + 0x498 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RQOS_MAP_TIMEOUTB + Specifies the timeout value for transactions mapped to the blue address queue. +Programming mode: Quasi-dynamic Group 3. + 0 + 11 + read-write + + + RQOS_MAP_TIMEOUTR + Specifies the timeout value for transactions mapped to the red address queue. With single read address queue, there is no red queue and this value has no effect. +Programming mode: Quasi-dynamic Group 3 + 16 + 11 + read-write + + + + + DDRCTRL_PCFGWQOS0_0 + DDRCTRL_PCFGWQOS0_0 + DDRCTRL port x write Q0S configuration register 0 + 0x49c + 0x20 + 0x00000E00 + 0xFFFFFFFF + + + WQOS_MAP_LEVEL1 + Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. +Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. +All of the map_level* registers must be set to distinct values. +Programming mode: Quasi-dynamic Group 3 + 0 + 4 + read-write + + + WQOS_MAP_LEVEL2 + Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. +Region2 starts from (level2 + 1) up to 15. +Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. +All of the map_level* registers must be set to distinct values. +Programming mode: Quasi-dynamic Group 3 + 8 + 4 + read-write + + + WQOS_MAP_REGION0 + This bitfield indicates the traffic class of region 0. +Valid values are: +When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. +Programming mode: Quasi-dynamic Group 3 + 16 + 2 + read-write + + + B_0x0 + NPW, 1: VPW. + 0x0 + + + + + WQOS_MAP_REGION1 + This bitfield indicates the traffic class of region 1. +Valid values are: +When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. +Programming mode: Quasi-dynamic Group 3 + 20 + 2 + read-write + + + B_0x0 + NPW, 1: VPW. + 0x0 + + + + + WQOS_MAP_REGION2 + This bitfield indicates the traffic class of region 2. +Valid values are: +When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. +Programming mode: Quasi-dynamic Group 3 + 24 + 2 + read-write + + + B_0x0 + NPW, 1: VPW. + 0x0 + + + + + + + DDRCTRL_PCFGWQOS1_0 + DDRCTRL_PCFGWQOS1_0 + DDRCTRL port x write Q0S configuration register 1 + 0x4a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WQOS_MAP_TIMEOUT1 + Specifies the timeout value for write transactions in region 0 and 1. +Programming mode: Quasi-dynamic Group 3. + 0 + 11 + read-write + + + WQOS_MAP_TIMEOUT2 + Specifies the timeout value for write transactions in region 2. +Programming mode: Quasi-dynamic Group 3. + 16 + 11 + read-write + + + + + + + DDRPERFM + DDRPERFM + DDRPERFM + 0x5A007000 + + 0x0 + 0x400 + registers + + + DDRPERFM + DDR performance monitor interrupt + 137 + + + + DDRPERFM_CTL + DDRPERFM_CTL + DDRPERFM control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + START + Start counters which are enabled, the time counter (TCNT) is always enabled. +writing a '1’ when the counters are running (DDRPERFM_STATUS.BUSY = 1) is ignored + 0 + 1 + write-only + + + B_0x0 + writing a '0’ has no effect. + 0x0 + + + B_0x1 + writing a '1’ Starts counters which are enabledW + 0x1 + + + + + STOP + stop all the counters. +Writing a '1’ when the counters are stopped (DDRPERFM_STATUS.BUSY = 0) is ignored + 1 + 1 + write-only + + + B_0x0 + writing a '0’ has no effect. + 0x0 + + + B_0x1 + writing a '1’ stops all the counters + 0x1 + + + + + + + DDRPERFM_CFG + DDRPERFM_CFG + DDRPERFM configurationl register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + enable counter x (from 0 to 3) + 0 + 4 + read-write + + + B_0x0 + the corresponding counter is disabled and does not increment + 0x0 + + + B_0x1 + the corresponding counter is enabled and incremented on event at each clock + 0x1 + + + + + SEL + select set of signals to be monitored (from 0 to 3) (see signal set description in ) and counters to be enabled + 16 + 2 + read-write + + + + + DDRPERFM_STATUS + DDRPERFM_STATUS + DDRPERFM status register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COVF + Counter x Overflow (with x from 0 to 3) + 0 + 4 + read-only + + + B_0x0 + no overflow + 0x0 + + + B_0x1 + counter overflow + 0x1 + + + + + BUSY + Busy Status + 16 + 1 + read-only + + + B_0x0 + DDRPERFM is stopped or a counter is in overflow + 0x0 + + + B_0x1 + DDRPERFM is counting (at least TCNT is counting) + 0x1 + + + + + TOVF + total counter overflow + 31 + 1 + read-only + + + B_0x0 + no overflow + 0x0 + + + B_0x1 + counter overflow + 0x1 + + + + + + + DDRPERFM_CCR + DDRPERFM_CCR + DDRPERFM counter clear register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCLR + counter x Clear (with x from 0 to 3) + 0 + 4 + write-only + + + B_0x0 + writing a '0’ has no effect + 0x0 + + + B_0x1 + writing a '1’ clears the corresponding event counter x (with x from 0 to 3) + 0x1 + + + + + TCLR + time counter clear + 31 + 1 + write-only + + + B_0x0 + writing a '0’ has no effect + 0x0 + + + B_0x1 + writing a '1’ clears the time counter + 0x1 + + + + + + + DDRPERFM_IER + DDRPERFM_IER + DDRPERFM interrupt enable register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVFIE + overflow interrupt enable + 0 + 1 + read-write + + + B_0x0 + overflow interrupt disabled + 0x0 + + + B_0x1 + overflow interrupt enabled + 0x1 + + + + + + + DDRPERFM_ISR + DDRPERFM_ISR + DDRPERFM interrupt status register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVFF + overflow flag +This flag is set when one counter is in overflow + 0 + 1 + read-only + + + + + DDRPERFM_ICR + DDRPERFM_ICR + DDRPERFM interrupt clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVF + overflow flag + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + clears the overflow flag + 0x1 + + + + + + + DDRPERFM_TCNT + DDRPERFM_TCNT + DDRPERFM time counter register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. + 0 + 32 + read-only + + + + + DDRPERFM_CNT0 + DDRPERFM_CNT0 + DDRPERFM event counter 0 register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + event counter value. + 0 + 32 + read-only + + + + + DDRPERFM_CNT1 + DDRPERFM_CNT1 + DDRPERFM event counter 1 register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + event counter value. + 0 + 32 + read-only + + + + + DDRPERFM_CNT2 + DDRPERFM_CNT2 + DDRPERFM event counter 2 register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + event counter value. + 0 + 32 + read-only + + + + + DDRPERFM_CNT3 + DDRPERFM_CNT3 + DDRPERFM event counter 3 register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + event counter value. + 0 + 32 + read-only + + + + + DDRPERFM_HWCFG + DDRPERFM_HWCFG + DDRPERFM hardware configuration register + 0x3f0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + NCNT + number of counters for this configuration (4) + 0 + 4 + read-only + + + + + DDRPERFM_VER + DDRPERFM_VER + DDRPERFM version register + 0x3f4 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MINREV + Minor revision number. + 0 + 4 + read-only + + + MAJREV + Major revision number. + 4 + 4 + read-only + + + + + DDRPERFM_ID + DDRPERFM_ID + DDRPERFM ID register + 0x3f8 + 0x20 + 0x00140061 + 0xFFFFFFFF + + + ID + DDRPERFM unique identification. + 0 + 32 + read-only + + + + + DDRPERFM_SID + DDRPERFM_SID + DDRPERFM magic ID register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + magic ID for automatic IP discovery. + 0 + 32 + read-only + + + + + + + DDRPHYC + DDRPHYC + DDRPHYC + 0x5A004000 + + 0x0 + 0x1000 + registers + + + + DDRPHYC_RIDR + DDRPHYC_RIDR + DDRPHYC revision ID register + 0x0 + 0x20 + 0x00200200 + 0xFFFFFFFF + + + PUBMNR + PUB minor rev + 0 + 4 + read-only + + + PUBMDR + PUB moderate rev + 4 + 4 + read-only + + + PUBMJR + PUB maj rev + 8 + 4 + read-only + + + PHYMNR + PHY minor rev + 12 + 4 + read-only + + + PHYMDR + PHY moderate rev + 16 + 4 + read-only + + + PHYMJR + PHY maj rev + 20 + 4 + read-only + + + UDRID + User-defined rev ID + 24 + 8 + read-only + + + + + DDRPHYC_PIR + DDRPHYC_PIR + DDRPHYC PHY initialization register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INIT + Initialization trigger +A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. +The exact initialization steps to be executes are specified in bits 1 to 6 of this register. A bit +setting of 1 means the step is executed as part of the initialization sequence, while a setting of '0’ means the step is bypassed. +The initialization trigger bit is self-clearing. + 0 + 1 + write-only + + + DLLSRST + DLL soft reset +Soft resets all PHY DLLs by driving the DLL soft reset pin. +Note: - Requires that ctl_clk be toggling for the DLL soft reset signal to be output from the DLL. If ctl_clk (AC DLL's cclk_0) is not guaranteed to be toggling, it is recommended to use the manual DLL soft reset bit DLLSRST of DDRPHYC_ACDLLCR, and not bit DLLSRST of DDRPHYC_PIR. +- Ensure that the minimum requirements for DLL bypass and DLL reset are observed while asserting this bit. + 1 + 1 + write-only + + + DLLLOCK + DLL lock +Waits for the PHY DLLs to lock. + 2 + 1 + write-only + + + ZCAL + Impedance calibration (Driver and ODT) +Performs PHY impedance calibration. + 3 + 1 + write-only + + + ITMSRST + ITM reset +Soft resets the interface timing modules for the data and data strobes, i.e., it asserts the ITM soft reset (srstb) signal. + 4 + 1 + write-only + + + DRAMRST + DRAM reset (DDR3 only) +Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. +This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the latter case, the reset is issued and 200us is waited before starting the full initialization sequence. + 5 + 1 + write-only + + + DRAMINIT + DRAM initialization +Executes the DRAM initialization sequence + 6 + 1 + write-only + + + QSTRN + Read DQS training +Executes a PUBL training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. + 7 + 1 + write-only + + + RVTRN + Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run +together. +It is expected RVTRN is normally set whenever bit QSTRN is set. +If RVTRN=1 and bit QSTRN=0, when bit INIT=1 (triggering the init process) the read DQS gate training algorithm still runs (as if bit QSTRN in DDRPHYC_PIR register was actually set to 1). +If it is necessary to run only RV training stand-alone, with no read DQS gate training, you can prevent the read DQS gate training from running by setting bit LBGDQS=1 in DDRPHYC_PGCR register. +Note: RV training cannot use multi-purpose register (MPR) and must use the user data programmed in DTDR0-1. +Note: RVTRN is not applicable to this version of PUBL. + 8 + 1 + write-only + + + ICPC + Initialization complete pin configuration +Specifies how the DFI 2.1 initialization complete output pin should be used to indicate the status of initialization. + 16 + 1 + write-only + + + B_0x0 + Asserted after PHY initialization (DLL locking and impedance calibration) is complete. + 0x0 + + + B_0x1 + Asserted after PHY initialization is complete and the triggered PUBL initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. + 0x1 + + + + + DLLBYP + DLL bypass +A setting of 1 on this bit puts all PHY DLLs in bypass mode. A bypassed DLL is also powered down (disabled). + 17 + 1 + write-only + + + CTLDINIT + Controller DRAM initialization +Indicates if set that DRAM initialization is performed by the controller. Otherwise if not set it indicates that DRAM initialization is performed using the built-in initialization sequence or using software through the configuration port. + 18 + 1 + write-only + + + CLRSR + clear status register +Writing 1 to this bits does the following: +Auto-clears itself. This means a following read to bit CLRSR returns 0 +Clears the DXnGSR0 bits for DTDONE, DTERR, DTIERR +Clears bit DFTERR in DDRPHYC_PGSR register and bit DFTERR in DDRPHYC_DXnGSR1 register +This bit is primarily for debug purposes and is typically not needed during normal functional operation. +It can be used when bit IDONE=1 in PGSR register, to manually clear the PGSR status bits, however, the PGSR status bits (except for the DFTRR and TQ bits) are automatically cleared by starting a new init process. +The bit can also be used to manually clear the DXnGSR status bits, however, starting a new data training process automatically clears the DXnGSR status bits. + 28 + 1 + write-only + + + LOCKBYP + DLL lock bypass +Bypasses or stops, if set, the waiting of DLLs to lock. DLL lock wait is automatically triggers after reset. +DLL lock wait may be triggered manually using INIT and DLLLOCK bits of the DDRPHYC_PIR register. This bit is self-clearing. + 29 + 1 + write-only + + + ZCALBYP + zcal bypass +Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. +Impedance calibration may be triggered manually using INIT and ZCAL bits of the DDRPHYC_PIR register. This bit is self-clearing. + 30 + 1 + write-only + + + INITBYP + Initialization bypass +Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. +Initialization may be triggered manually using INIT and the other relevant bits of the DDRPHYC_PIR register. This bit is self-clearing. + 31 + 1 + write-only + + + + + DDRPHYC_PGCR + DDRPHYC_PGCR + DDRPHYC PHY global control register + 0x8 + 0x20 + 0x01842E04 + 0xFFFFFFFF + + + ITMDMD + ITM DDR mode +Selects whether ITMS uses DQS and DQS# or it only uses DQS. +Valid values are: +Note: The correct setting is always DQS and DQS#. + 0 + 1 + read-write + + + B_0x0 + ITMS uses DQS and DQS# + 0x0 + + + B_0x1 + ITMS uses DQS only + 0x1 + + + + + DQSCFG + DQS gating configuration +Selects one of the two DQS gating schemes: +Note: Passive windowing must be used for LPDDR2/3. + 1 + 1 + read-write + + + B_0x0 + DQS gating is shut off using the rising edge of DQS_b (active windowing mode) + 0x0 + + + B_0x1 + DQS gating blankets the whole burst (passive windowing mode). + 0x1 + + + + + DFTCMP + DQS drift compensation +Enables or disables DQS drift compensation. Valid values are: +By default, drift compensation is enabled. +Note: Drift compensation is not supported under any of the following situations: +- LPDDR2/3 (bit DDRMD set to LPDDR2 in DDRPHYC_DCR register) +- Burst length 2 (bit BL in DDRPHYC_MR0 register set to burst length of 2) +- Read DQS gating using passive windowing (bit DQSCFG in DDRPHYC_PGCR register set to passive windowing) +Drift compensation must be set to disabled if any of the above are set. + 2 + 1 + read-write + + + B_0x0 + Disables data strobe drift compensation + 0x0 + + + B_0x1 + Enables data strobe drift compensation + 0x1 + + + + + DFTLMT + DQS drift limit +Specifies the expected limit of drift on read data strobes. A drift of this value or greater is reported as a drift error through the host port error flag. Valid values are: +Note: Although reported through the error flag, this is not an error requiring any action. It is simply an indicator that the drift is greater than expected. + 3 + 2 + read-write + + + B_0x0 + No limit (no error reported) + 0x0 + + + B_0x1 + 90° drift + 0x1 + + + B_0x2 + 180° drift + 0x2 + + + B_0x3 + 270° or more drift + 0x3 + + + + + DTOSEL + Digital test output select +Digital Test Output Select: Selects the PHY digital test output that should be driven +onto PHY digital test output (phy_dto) pin: Valid values are: +Other: Reserved + 5 + 4 + read-write + + + B_0x0 + DATX8 0 DLL digital test output + 0x0 + + + B_0x1 + DATX8 1 DLL digital test output + 0x1 + + + B_0x2 + DATX8 2 DLL digital test output + 0x2 + + + B_0x3 + DATX8 3 DLL digital test output + 0x3 + + + B_0x4 + DATX8 4 DLL digital test output + 0x4 + + + B_0x5 + DATX8 5 DLL digital test output + 0x5 + + + B_0x6 + DATX8 6 DLL digital test output + 0x6 + + + B_0x7 + DATX8 7 DLL digital test output + 0x7 + + + B_0x8 + DATX8 8 DLL digital test output + 0x8 + + + B_0x9 + AC DLL digital test output + 0x9 + + + + + CKEN + CK enable +Controls whether the CK going to the SDRAM is enabled (toggling) or +disabled (static value defined by CKDV). One bit for each of the three CK pairs. + 9 + 3 + read-write + + + CKDV + CK disable value +Specifies the static value that should be driven on CK/CK# pair(s) when the pair(s) is disabled. CKDV[0] specifies the value for CK and CKDV[1] specifies the value for CK#. + 12 + 2 + read-write + + + CKINV + CK invert +Specifies if set that CK/CK# should be inverted. Otherwise CK/CK# toggles with normal polarity. + 14 + 1 + read-write + + + IOLB + I/O loop back select +Selects where inside the I/O the loop-back of signals happens. Not applicable to D3A I/Os. +Valid values are: + 15 + 1 + read-write + + + B_0x0 + Loopback is after output buffer; output enable must be asserted + 0x0 + + + B_0x1 + Loopback is before output buffer; output enable is don’t care + 0x1 + + + + + IODDRM + I/O DDR mode +Selects the DDR mode for the I/Os. + 16 + 2 + read-write + + + RANKEN + Rank enable +Specifies the ranks that are enabled for data-training. +only Bit 0 is used and controls rank 0. +Setting the bit to '1’ enables the rank, and setting it to '0’ disables the rank. + 18 + 4 + read-write + + + ZKSEL + Impedance clock divider selection +Selects the divide ratio for the clock used by the impedance control logic. The source clock for +the divider is the configuration port clock signal (pclk), depending on which configuration port type used (see “Impedance Calibration” on page tbc). +Valid values are: + 22 + 2 + read-write + + + B_0x0 + Divide by 2 + 0x0 + + + B_0x1 + Divide by 8 + 0x1 + + + B_0x2 + Divide by 32 + 0x2 + + + B_0x3 + Divide by 64 + 0x3 + + + + + PDDISDX + Power down disabled byte +Indicates if set that the DLL and I/Os of a disabled byte should be powered down. + 24 + 1 + read-write + + + RFSHDT + Refresh during training +A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. + 25 + 4 + read-write + + + LBDQSS + Loop back DQS shift +Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: + 29 + 1 + read-write + + + B_0x0 + PUB sets the read DQS delay to 0; DQS is already shifted 90 degrees by write path + 0x0 + + + B_0x1 + The read DQS shift is set manually through software. + 0x1 + + + + + LBGDQS + Loop back DQS gating +Selects the DQS gating mode that should be used when the PHY is in loopback mode. Valid values are: + 30 + 1 + read-write + + + B_0x0 + DQS gate training is triggered on the PUB + 0x0 + + + B_0x1 + DQS gate is set manually using software + 0x1 + + + + + LBMODE + Loop back mode +Indicates if set that the PHY/PUB is in loopback mode + 31 + 1 + read-write + + + + + DDRPHYC_PGSR + DDRPHYC_PGSR + DDRPHYC PHY global status register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDONE + Initialization done +Indicates if set that the DDR system initialization has completed. +This bit is set after all the selected initialization routines in DDRPHYC_PIR register have completed. + 0 + 1 + read-only + + + DLDONE + DLL lock done +Indicates if set that DLL locking has completed. + 1 + 1 + read-only + + + ZCDDONE + zcal done +Indicates if set that impedance calibration has completed. + 2 + 1 + read-only + + + DIDONE + DRAM initialization done +Indicates if set that DRAM initialization has completed. + 3 + 1 + read-only + + + DTDONE + Data training done +Indicates, if set, that the PHY has finished doing data training. + 4 + 1 + read-only + + + DTERR + DQS gate training error +If set, indicates that a valid DQS gating window could not be found during DQS gate training. + 5 + 1 + read-only + + + DTIERR + DQS gate training intermittent error +If set, indicates that there was an intermittent error during DQS gate training, such as a pass was followed by a fail then followed by another pass. + 6 + 1 + read-only + + + DFTERR + DQS drift error +If set, indicates that at least one of the read data strobes has drifted by more than or equal to the drift limit set in the PHY General Configuration Register (PGCR). + 7 + 1 + read-only + + + RVERR + Read valid training error +If set, indicates that a valid read valid placement could not be found during read valid training. +Note: RVTRN is not applicable to this version of PUBL + 8 + 1 + read-only + + + RVEIRR + Read valid training intermittent error +If set, indicates that there was an intermittent error during read valid training, such as a pass was followed by a fail then followed by another pass. +Note: RVTRN is not applicable to this version of PUBL + 9 + 1 + read-only + + + TQ + Temperature output (LPDDR only) N/A + 31 + 1 + read-only + + + + + DDRPHYC_DLLGCR + DDRPHYC_DLLGCR + DDRPHYC DDR DLL global control register + 0x10 + 0x20 + 0x03737000 + 0xFFFFFFFF + + + DRES + Trim reference current versus resistor value variation +1x: Rnom + 20% +Note: For a few processes this field is reserved and is not used by the DLL. + 0 + 2 + read-write + + + B_0x0 + Rnom + 0x0 + + + B_0x1 + Rnom - 20% + 0x1 + + + + + IPUMP + Charge pump current trim +Note: If DWC_DDR3PHY_DLL_TYPEA Verilog macro is defined then the default value for this field is 011. + 2 + 3 + read-write + + + B_0x0 + maximum current + 0x0 + + + B_0x7 + minimum current + 0x7 + + + + + TESTEN + Test enable +Enables digital and analog test outputs selected by DTC and ATC respectively. + 5 + 1 + read-write + + + DTC + Digital test control +Selects the digital signal to be output on the DLL digital test output (test_out_d[1]) when TESTEN is high (Output is '0' when TESTEN is low). +Valid settings for master DLL (such as, when TESTSW = '0'): +-000: 0 output clock (clk_0) +-001: 90 output clock (clk_90) +-010: 180 output clock (clk_180) +-011: 270 output clock (clk_270) +-100: 360 internal clock (clk_360_int) +-101: Speed-up pulse (spdup) +-110: Slow-down pulse (slwdn) +-111: 0 MCTL logic clock (cclk_0) +Valid settings for slave DLL (such as when TESTSW = '1'): +-000: Input DQS strobe (dqs) +-001: Input clock reference (clk_90_in) +-010: Internal feedback clock (clk_0_out) +-011: 90 output DQS# strobe (dqsb_90) +-100: 90 output DQS strobe (dqs_90) +-101: Speed-up pulse (spdup) +-110: Slow-down pulse (slwdn) +-111: Auto-lock enable signal + 6 + 3 + read-write + + + ATC + Analog test control +Selects the analog signal to be output on the DLL analog test output (test_out_a) when TESTEN is high (Output is Vss when TESTEN is low). +The test output either comes from the master DLL or the slave DLL, depending on the setting of the test switch (TESTSW). +Both master DLL and slave DLL output similar analog test signals. Valid settings for analog test control are: + 9 + 2 + read-write + + + B_0x0 + Replica bias output for PMOS (Vbp) + 0x0 + + + B_0x1 + Replica bias output for NMOS (Vbn) + 0x1 + + + B_0x2 + Filter output (Vc) + 0x2 + + + B_0x3 + VDDCORE + 0x3 + + + + + TESTSW + Test switch +Selects the test signals of either the master DLL, set to 0, or the slave DLL, set to 1. + 11 + 1 + read-write + + + MBIAS + Master bias trim +Used to trim the bias for the master DLL. +Note: If DWC_DDR3PHY_DLL_TYPEA Verilog macro is defined then the default value for this field is 0x00. + 12 + 8 + read-write + + + SBIAS2_0 + Slave bias trim +Used to trim the bias for the slave DLL. +Note: If DWC_DDR3PHY_DLL_TYPEA Verilog macro is defined then the default value for this field is 0x00. + 20 + 3 + read-write + + + BPS200 + Bypass mode frequency range + 23 + 1 + read-write + + + B_0x0 + 0 to 100 MHz + 0x0 + + + B_0x1 + 0 to 200 MHz + 0x1 + + + + + SBIAS5_3 + Slave bias trim +Used to trim the bias for the slave DLL. +Note: If DWC_DDR3PHY_DLL_TYPEA Verilog macro is defined then the default value for this field is 0x00. + 24 + 3 + read-write + + + FDTRMSL + Slave bypass fixed delay trim + 27 + 2 + read-write + + + B_0x0 + Nominal delay + 0x0 + + + B_0x1 + Nominal delay – 10% + 0x1 + + + B_0x2 + Nominal delay + 10% + 0x2 + + + B_0x3 + Nominal delay + 20% + 0x3 + + + + + LOCKDET + Master lock detect enable +Note: This field is only valid for a few processes. For all other processes this field is reserved. + 29 + 1 + read-write + + + DLLRSVD2 + These bit are connected to the DLL control bus and reserved for future use. + 30 + 2 + read-write + + + + + DDRPHYC_ACDLLCR + DDRPHYC_ACDLLCR + DDRPHYC AC DLL control register + 0x14 + 0x20 + 0x40000000 + 0xFFFFFFFF + + + MFBDLY + Master DLL feed-back delay trim +Used to trim the delay in the master DLL feed-back path: + 6 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + MFWDLY + Master DLL feed-forward delay trim +Used to trim the delay in the master DLL feed-forward path: + 9 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + ATESTEN + Analog test enable +Enables the analog test signal to be output on the DLL analog test output (ATO pin). The DLL analog test output is tri-stated when this bit is '0'. + 18 + 1 + read-write + + + DLLSRST + DLL soft reset +Soft resets the AC DLL by driving the DLL soft reset pin. + 30 + 1 + read-write + + + DLLDIS + DLL disable +A disabled DLL is bypassed. By default DLL is enabled. + 31 + 1 + read-write + + + + + DDRPHYC_PTR0 + DDRPHYC_PTR0 + DDRPHYC PT register 0 + 0x18 + 0x20 + 0x0022AF9B + 0xFFFFFFFF + + + TDLLSRST + DLL soft reset +Number of configuration clock cycles that the DLL soft reset pin must remain asserted when the soft reset is triggered through the PHY initialization register (DDRPHYC_PIR). +This must correspond to a value that is equal to or more than 50ns or 8 controller clock cycles, whichever is bigger. +Default value corresponds to 50 ns at 533 MHz. + 0 + 6 + read-write + + + TDLLLOCK + DLL lock time +Number of configuration clock cycles for the DLL to stabilize and lock, i.e. number of clock cycles from when the DLL reset pin is de-asserted to when the DLL has locked and is ready for use. +Default value corresponds to 5.12us at 533MHz. + 6 + 12 + read-write + + + TITMSRST + ITM soft reset +Number of configuration clock cycles that the ITM soft reset pin must remain asserted when the soft reset is applied to the ITMs. +This must correspond to a value that is equal to or more than 8 controller clock cycles. +Default value corresponds to 8 controller clock cycles. + 18 + 4 + read-write + + + + + DDRPHYC_PTR1 + DDRPHYC_PTR1 + DDRPHYC PT register 1 + 0x1c + 0x20 + 0x0604111D + 0xFFFFFFFF + + + TDINIT0 + tDINIT0 +DRAM initialization time corresponding to the following: +DDR3 = CKE low time with power and clock stable (500 us) +LPDDR2 = CKE high time to first command (200 us) +LPDDR3 = CKE high time to first command (200us) +Default value corresponds to DDR3 500 us at 533MHz. + 0 + 19 + read-write + + + TDINIT1 + tDINIT1 +DRAM initialization time corresponding to the following: +DDR3 = CKE high time to first command (tRFC +10 ns or 5 tCK, whichever value is larger) +LPDDR2 = CKE low time with power and clock stable (100 ns) +LPDDR3 = CKE low time with power and clock stable (100 ns) +Default value corresponds to DDR3 360ns at 533MHz. + 19 + 8 + read-write + + + + + DDRPHYC_PTR2 + DDRPHYC_PTR2 + DDRPHYC PT register 2 + 0x20 + 0x20 + 0x042DA072 + 0xFFFFFFFF + + + TDINIT2 + tDINIT2 +DRAM initialization time corresponding to the following: +DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) +LPDDR2 = Time from reset command to end of auto initialization (1 us + 10 us = 11us) +LPDDR3 = Time from reset command to end of auto initialization (11us) +Default value corresponds to DDR3 200 us at 533MHz + 0 + 17 + read-write + + + TDINIT3 + tDINIT3 +DRAM initialization time corresponding to the following: +LPDDR2 = Time from ZQ initialization command to first command (1 us) +LPDDR3 = Time from ZQ initialization command to first command (1us) +Default value corresponds to the LPDDR2/3 1 us at 533MHz. + 17 + 10 + read-write + + + + + DDRPHYC_ACIOCR + DDRPHYC_ACIOCR + DDRPHYC ACIOC register + 0x24 + 0x20 + 0x30400812 + 0xFFFFFFFF + + + ACIOM + AC pins I/O mode +Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins, + 0 + 1 + read-write + + + ACOE + AC pins output enable +Enables, when set, the output driver on the I/O for all address and command pins + 1 + 1 + read-write + + + ACODT + AC pins ODT +Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins + 2 + 1 + read-write + + + ACPDD + AC pins power down drivers +Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins + 3 + 1 + read-write + + + ACPDR + AC pins power down receivers +Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + 4 + 1 + read-write + + + CKODT + CK pin ODT +Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + 5 + 3 + read-write + + + CKPDD + CK pin power down driver +Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + 8 + 3 + read-write + + + CKPDR + CK pin power down receiver +Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively + 11 + 3 + read-write + + + RANKODT + Rank ODT +Enables, when set, the on-die termination on the I/O for CKE, ODT, and CS# pins. + 14 + 1 + read-write + + + CSPDD + CS power down driver +Powers down, when set, the output driver on the I/O for CS# pins. +Only PDD[0] is used for single rank. +CKE and ODT driver power down is controlled by DSGCR register. + 18 + 1 + read-write + + + RANKPDR + Rank power down receiver +Powers down, when set, the input receiver on the I/O CKE, ODT, and CS# pins. +Only RANKPDR[0] is used for single rank + 22 + 1 + read-write + + + RSTODT + RST pin ODT +Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. + 26 + 1 + read-write + + + RSTPDD + RST pin power down driver +Powers down, when set, the output driver on the I/O for SDRAM RST# pin. + 27 + 1 + read-write + + + RSTPDR + RST pin power down receiver +Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. + 28 + 1 + read-write + + + RSTIOM + Reset I/O mode +Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. + 29 + 1 + read-write + + + ACSR + AC slew rate +Selects slew rate of the I/O for all address and command pins. + 30 + 2 + read-write + + + + + DDRPHYC_DXCCR + DDRPHYC_DXCCR + DDRPHYC DXCC register + 0x28 + 0x20 + 0x00000800 + 0xFFFFFFFF + + + DXODT + Data on die termination +Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8. + 0 + 1 + read-write + + + DXIOM + Data I/O mode +Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. + 1 + 1 + read-write + + + DXPDD + Data power down driver +Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. + 2 + 1 + read-write + + + DXPDR + Data power down receiver +Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. It also powers down the PDQSR cell of all DAXT8 macros. This bit is ORed with the PDR and DQSRPD configuration bits of the individual DATX8 + 3 + 1 + read-write + + + DQSRES + DQS resistor +Selects the on-die pull-down/pull-up resistor for DQS pins. +DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). +DQSRES[2:0] selects the resistor value as follows: +Note: DQS resistor must be connected for LPDDR2 + 4 + 4 + read-write + + + B_0x0 + Open: On-die resistor disconnected + 0x0 + + + B_0x1 + 688 Ω + 0x1 + + + B_0x2 + 611 Ω + 0x2 + + + B_0x3 + 550 Ω + 0x3 + + + B_0x4 + 500 Ω + 0x4 + + + B_0x5 + 458 Ω + 0x5 + + + B_0x6 + 393 Ω + 0x6 + + + B_0x7 + 344 Ω + 0x7 + + + + + DQSNRES + DQS# resistor +Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. +Note: DQS# resistor must be connected for LPDDR2. + 8 + 4 + read-write + + + DQSNRST + DQS reset +Indicates, if set, that the ITMS of DQS# should always be put in reset such that its output enable is always '1' and its data output is always '0'. +This is done by driving the oe_set_b and do_rst_b pins of this ITMS to '0' in order to force the +unused DQS# PAD to a known state of '0' in applications that don't use DQS#. + 14 + 1 + read-write + + + RVSEL + ITMD read valid select +Selects the scheme used for ITMD read valid. Valid values are: + 15 + 1 + read-write + + + B_0x0 + ITMD read valid signal is generated by delayed DFI read enable signal. + 0x0 + + + B_0x1 + ITMD read valid is generated by the ITMD itself using asynchronous crossing. + 0x1 + + + + + AWDT + Active window data train +Indicates if set that data training (DQS gate training and read valid training) should be performed with active DQS gate window. +This is just for debug purposes. +The default is to perform training with passive windowing. + 16 + 1 + read-write + + + + + DDRPHYC_DSGCR + DDRPHYC_DSGCR + DDRPHYC DSGC register + 0x2c + 0x20 + 0xFA00001F + 0xFFFFFFFF + + + PUREN + PHY update request enable +Specifies if set, that the PHY should issue PHY initiated DFI update request when there is DQS drift of more than ¾ of a clock cycle within one continuous (back-to-back) read burst. +By default the PHY issues PHY initiated update requests and the controller should respond otherwise the PHY may return erroneous values. +The option to disable it is provided only for silicon evaluation and testing. + 0 + 1 + read-write + + + BDISEN + Byte disable enable +Specifies if set that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register + 1 + 1 + read-write + + + ZUEN + zcal on DFI update request +Specifies if set that the PHY should perform impedance calibration (update) whenever there is a controller initiated DFI update request. Otherwise the PHY ignores an update request from the controller. + 2 + 1 + read-write + + + LPIOPD + Low power I/O power down +Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the PHY. + 3 + 1 + read-write + + + LPDLLPD + Low power DLL power down +Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the DLL of the PHY if the wakeup time request satisfies the DLL lock time. +For more information on requirements when enabling and disabling the DLL, refer to “bypass mode register control” + 4 + 1 + read-write + + + DQSGX + DQS gate extension +Specifies the number of clock cycles for which the DQS gating must be extended beyond the normal burst length width. Only applicable when using PDQSR I/O cell, passive DQS gating and no drift compensation. +This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3. +For LPDDR2/LPDDR3 it should be set to (tDQSCKmax- tDQSCKmin) divide by clock period and rounded up. tDQSCKmax and tDQSCKmin can be found in the LPDDR2 vendor datasheet. + 5 + 3 + read-write + + + DQSGE + DQS gate early +Specifies the number of clock cycles for which the DQS gating must be enable dearlier than its normal position. Only applicable when using PDQSR I/O cell, passive DQS gating and no drift compensation. +This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3. +For LPDDR2/LPDDR3 it should be set to (tDQSCKmax - tDQSCKmin) divide by clock period and rounded up. tDQSCKmax and tDQSCKmin can be found in the LPDDR/LPDDR2 vendor datasheet. + 8 + 3 + read-write + + + NOBUB + No bubble +Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: + 11 + 1 + read-write + + + B_0x0 + Bubbles are allowed during reads + 0x0 + + + B_0x1 + Bubbles are not allowed during reads + 0x1 + + + + + FXDLAT + Fixed latency +Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: + 12 + 1 + read-write + + + B_0x0 + Disable fixed read latency + 0x0 + + + B_0x1 + Enable fixed read latency + 0x1 + + + + + CKEPDD + CKE power down driver +Powers down, when set, the output driver on the I/O for CKE pin. + 16 + 1 + read-write + + + ODTPDD + ODT power down driver +Powers down, when set, the output driver on the I/O for ODT pin. + 20 + 1 + read-write + + + NL2PD + Non LPDDR2 power down +Powers down, when set, the output driver and the input receiver on the I/O for non-LPDDR2/LPDDR3 (ODT, RAS#, CAS#, WE#, and BA) pins. +This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR modes is being used in LPDDR2/LPDDR3 mode. +For these pins, the I/O power down signal (PDD or PDR) is an OR of this bit and the respective power-down bit in ACIOCR register. + 24 + 1 + read-write + + + NL2OE + Non LPDDR2 output enable +Enables, when set, the output driver on the I/O for non-LPDDR2/LPDDR3 (ODT, RAS#, CAS#, WE#, and BA) pins. +This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR modes is being used in LPDDR2/LPDDR3 mode. +For these pins, the I/O output enable signal (OE) is an AND of this bit and the respective output enable bit in ACIOCR or DSGCR registers. + 25 + 1 + read-write + + + TPDPD + TPD power down driver (N/A LPDDR only) + 26 + 1 + read-write + + + TPDOE + TPD output enable (N/A LPDDR only) + 27 + 1 + read-write + + + CKOE + CK output enable +Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. + 28 + 1 + read-write + + + ODTOE + ODT output enable +Enables, when set, the output driver on the I/O for SDRAM ODT pins. + 29 + 1 + read-write + + + RSTOE + RST output enable +Enables, when set, the output driver on the I/O for SDRAM RST# pin + 30 + 1 + read-write + + + CKEOE + CKE output enable +Sets the output driver on the I/O for SDRAM CKE pins. + 31 + 1 + read-write + + + + + DDRPHYC_DCR + DDRPHYC_DCR + DDRPHYC DC register + 0x30 + 0x20 + 0x0000000B + 0xFFFFFFFF + + + DDRMD + SDRAM DDR mode +Others: Reserved + 0 + 3 + read-write + + + B_0x3 + DDR3 + 0x3 + + + B_0x4 + LPDDR2 (Mobile DDR2) + 0x4 + + + B_0x5 + LPDDR3 (Mobile DDR3) + 0x5 + + + + + DDR8BNK + DDR 8 banks +Indicates if set that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, other tRPA = tRP and no tFAW is used. +Note: A setting of 1 for DRAMs that have fewer than 8 banks still results in correct functionality but less tighter DRAM command spacing for the parameters described here. + 3 + 1 + read-write + + + PDQ + Primary DQ(DDR3 Only) +Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively + 4 + 3 + read-write + + + MPRDQ + MPR DQ +Specifies the value that is driven on non-primary DQ pins during MPR reads. +Valid values are: + 7 + 1 + read-write + + + B_0x0 + Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive '0’ + 0x0 + + + B_0x1 + Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) + 0x1 + + + + + DDRTYPE + DDR type (LPDDR2 S4) +Selects the DDR type for the specified LPDDR mode. +Valid values for LPDDR2 are: +Others: Reserved + 8 + 2 + read-write + + + B_0x0 + LPDDR2-S4 + 0x0 + + + B_0x1 + LPDDR2-S2 + 0x1 + + + + + NOSRA + No simultaneous rank access +Specifies if set that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. + 27 + 1 + read-write + + + DDR2T + 2T timing +Indicates if set that 2T timing should be used by PUB internally generated SDRAM transactions. + 28 + 1 + read-write + + + UDIMM + Unbuffered DIMM +Indicates if set that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). +In this case, the PUBL re-scrambles the bank and address when sending mode register commands to the second rank. +This only applies to PUBL internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. + 29 + 1 + read-write + + + RDIMM + Registered DIMM +Indicates if set that a registered DIMM is used. In this case, the PUBL increases the SDRAM write and read latencies (WL/RL) by 1. +This only applies to PUBL internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM + 30 + 1 + read-write + + + TPD + Test power down (N/A LPDDR only) +If set it places the DRAM in deep power down mode. + 31 + 1 + read-write + + + + + DDRPHYC_DTPR0 + DDRPHYC_DTPR0 + DDRPHYC DTP register 0 + 0x34 + 0x20 + 0x3092666E + 0xFFFFFFFF + + + TMRD + tMRD +Load mode cycle time: The minimum time between a load mode register command and any other command. +For DDR3 this is the minimum time between two load mode register commands. +For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. +For LPDDR3, the value used for tMRD is 8 plus the value programmed in these bits. + 0 + 2 + read-write + + + TRTP + tRTP +Internal read to precharge command delay. Valid values are 2 to 6. Note that even though RTP does not apply to JEDEC DDR devices, this parameter must still be set to a minimum value of 2 for DDR because the Controller always uses the DDR2 equation, AL + BL/2 + max(RTP,2) – 2, to compute the read to precharge timing (which is BL/2 for JEDEC DDR). + 2 + 3 + read-write + + + TWTR + tWTR +Internal write to read command delay. Valid values are 1 to 6. + 5 + 3 + read-write + + + TRP + tRP +Precharge command period: The minimum time between a precharge command and any other command. +Note: Note that the controller automatically derives tRPA for 8-bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 11. + 8 + 4 + read-write + + + TRCD + tRCD +Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 11. + 12 + 4 + read-write + + + TRAS + tRAS +Activate to precharge command delay. Valid values are 2 to 31. + 16 + 5 + read-write + + + TRRD + tRRD +Activate to activate command delay (different banks). Valid values are 1 to 8. + 21 + 4 + read-write + + + TRC + tRC +Activate to activate command delay (same bank). Valid values are 2 to 42. + 25 + 6 + read-write + + + TCCD + tCCDRead to read and write to write command delay + 31 + 1 + read-write + + + B_0x0 + BL/2 for DDR2 and 4 for DDR3 + 0x0 + + + B_0x1 + BL/2 + 1 for DDR2 and 5 for DDR3 + 0x1 + + + + + + + DDRPHYC_DTPR1 + DDRPHYC_DTPR1 + DDRPHYC DTP register 1 + 0x38 + 0x20 + 0x09830090 + 0xFFFFFFFF + + + TAOND + tAOND/tAOFD +ODT turn-on/turn-off delays (DDR2 only). The delays are in clock cycles. +Valid values are: +Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the +user must ensure that the operational Write Latency is always greater than or equal +to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 +and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, +but not 3/3.5 or higher. + 0 + 2 + read-write + + + B_0x0 + 2/2.5 + 0x0 + + + B_0x1 + 3/3.5 + 0x1 + + + B_0x2 + 4/4.5 + 0x2 + + + B_0x3 + 5/5.5 + 0x3 + + + + + TRTW + tRTW +Read to Write command delay. +Valid values are: +This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. + 2 + 1 + read-write + + + B_0x0 + standard bus turn around delay + 0x0 + + + B_0x1 + add 1 clock to standard bus turn around delay + 0x1 + + + + + TFAW + tFAW +4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. +Valid values are 2 to 31. + 3 + 6 + read-write + + + TMOD + tMOD +Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. +Valid values are: + 9 + 2 + read-write + + + B_0x0 + 12 + 0x0 + + + B_0x1 + 13 + 0x1 + + + B_0x2 + 14 + 0x2 + + + B_0x3 + 15 + 0x3 + + + + + TRTODT + tRTODT +Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. +Valid values are: +If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. + 11 + 1 + read-write + + + B_0x0 + ODT may be turned on immediately after read post-amble + 0x0 + + + B_0x1 + ODT may not be turned on until one clock after the read post-amble + 0x1 + + + + + TRFC + tRFC +Refresh-to-Refresh: Indicates the minimum time, in clock cycles, between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. +The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. + 16 + 8 + read-write + + + TDQSCKMIN + tDQSCKmin +DQS output access time from CK/CK# (LPDDR2/3 only). +This value is used for computing the read latency. Valid values are 0 to 7. +This value is derived from the corresponding parameter in the SDRAM datasheet divided by the clock cycle time without rounding up. +The fractional remainder is automatically adjusted for by data training in quarter clock cycle units. +If data training is not performed then this fractional remainder must be converted to quarter clock cycle units and the gating registers (DXnDQSTR) adjusted accordingly. + 24 + 3 + read-write + + + TDQSCKMAX + tDQSCKmax +Maximum DQS output access time from CK/CK# (LPDDR2 only). +This value is used for implementing read-to-write spacing. Valid values are 1 to 7. + 27 + 3 + read-write + + + + + DDRPHYC_DTPR2 + DDRPHYC_DTPR2 + DDRPHYC DTP register 2 + 0x3c + 0x20 + 0x1001A0C8 + 0xFFFFFFFF + + + TXS + tXS +Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. + 0 + 10 + read-write + + + TXP + tXP +Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. + 10 + 5 + read-write + + + TCKE + tCKE +CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. + 15 + 4 + read-write + + + TDLLK + tDLLK +DLL locking time. Valid values are 2 to 1023. + 19 + 10 + read-write + + + + + DDRPHYC_DDR3_MR0 + DDRPHYC_DDR3_MR0 + DDRPHYC MR0 register for DDR3 + 0x40 + 16 + 0x00000A52 + 0x0000FFFF + + + BL + Burst length +Determines the maximum number of column locations that can be accessed during a given read or write command. +Valid values for DDR3 are: + 0 + 2 + read-write + + + B_0x0 + 8 (Fixed) + 0x0 + + + B_0x1 + 4 or 8 (On the fly) + 0x1 + + + B_0x2 + 4 (Fixed) + 0x2 + + + + + CL0 + CAS latency +The delay, in clock cycles, between when the SDRAM registers a read command to when data is available. +Valid values for CL[3:0] are: +Others: Reserved + 2 + 1 + read-write + + + BT + Burst type +Indicates whether a burst is sequential (0) or interleaved (1). + 3 + 1 + read-write + + + CL + CAS latency +The delay, in clock cycles, between when the SDRAM registers a read command to when data is available. +Valid values for CL[3:0] are: +Others: Reserved + 4 + 3 + read-write + + + TM + Operating mode +Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. + 7 + 1 + read-write + + + DR + DLL reset (autoclear) +Writing a '1’ to this bit resets the SDRAM DLL. This bit is self clearing, +i.e. it returns back to '0’ after the DLL reset has been issued. + 8 + 1 + read-write + + + WR + Write recovery +This is the value of the write recovery in clock cycles. It is calculated by dividing the data sheet write recovery time, tWR (ns) by the data sheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. +Valid values are: +All other settings are reserved and should not be used. +Note: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + 9 + 3 + read-write + + + B_0x1 + 5 + 0x1 + + + B_0x2 + 6 + 0x2 + + + B_0x3 + 7 + 0x3 + + + B_0x4 + 8 + 0x4 + + + B_0x5 + 10 + 0x5 + + + B_0x6 + 12 + 0x6 + + + + + PD + Power-down control +Controls the exit time for power-down modes. Refer to SDRAM datasheet for details on power-down modes. Valid values are: + 12 + 1 + read-write + + + B_0x0 + Slow exit (DLL off) + 0x0 + + + B_0x1 + Fast exit (DLL on) + 0x1 + + + + + RSVD + JEDEC reserved. + 13 + 3 + read-write + + + + + DDRPHYC_DDR3_MR1 + DDRPHYC_DDR3_MR1 + DDRPHYC MR1 register for DDR3 + 0x44 + 16 + 0x00000000 + 0x0000FFFF + + + DE + DLL enable/disable +Enable (0) or disable (1) the DLL. +DLL must be enabled for normal operation. + 0 + 1 + read-write + + + DIC0 + Output driver impedance control +Controls the output drive strength. +Valid values for {DIC1,DIC0} are: + 1 + 1 + read-write + + + B_0x0 + RZQ/6 + 0x0 + + + B_0x1 + RZQ/7 + 0x1 + + + + + RTT0 + On die termination +Selects the effective resistance for SDRAM on die termination. +Valid values for {RTT2,RTT1,RTT0} are: +Others: Reserved + 2 + 1 + read-write + + + AL + Posted CAS Additive Latency: +Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to SDRAM datasheet for details). Valid values are: + 3 + 2 + read-write + + + B_0x0 + 0 (AL disabled) + 0x0 + + + B_0x1 + CL - 1 + 0x1 + + + B_0x2 + CL - 2 + 0x2 + + + + + DIC1 + Output driver impedance control +Controls the output drive strength. +Valid values for {DIC1,DIC0} are: + 5 + 1 + read-write + + + B_0x0 + RZQ/6 + 0x0 + + + B_0x1 + RZQ/7 + 0x1 + + + + + RTT1 + On die termination +Selects the effective resistance for SDRAM on die termination. +Valid values for {RTT2,RTT1,RTT0} are: +Others: Reserved + 6 + 1 + read-write + + + LEVEL + Write leveling enable (N/A) + 7 + 1 + read-write + + + RTT2 + On die termination +Selects the effective resistance for SDRAM on die termination. +Valid values for {RTT2,RTT1,RTT0} are: +Others: Reserved + 9 + 1 + read-write + + + TDQS + Termination data strobe +When enabled ('1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. (N/A) + 11 + 1 + read-write + + + QOFF + Output enable/disable +This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. + 12 + 1 + read-write + + + B_0x0 + all outputs function as normal + 0x0 + + + B_0x1 + all SDRAM outputs are disabled removing output buffer current. + 0x1 + + + + + + + DDRPHYC_LPDDR2_MR1 + DDRPHYC_LPDDR2_MR1 + DDRPHYC_LPDDR2_MR1 + DDRPHYC_DDR3_MR1 + 0x44 + 0x20 + read-write + 0x00000000 + 0x0000FFFF + + + BL + Burst length + Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: + Others: Reserved + 0 + 3 + read-write + + + B_0x2 + 4 + 0x2 + + + B_0x3 + 8 + 0x3 + + + B_0x4 + 16 + 0x4 + + + + + BT + Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , + 3 + 1 + read-write + + + WC + Wrap control + 4 + 1 + read-write + + + B_0x0 + wrap + 0x0 + + + B_0x1 + no wrap + 0x1 + + + + + NWR + Write recovery +Others: Reserved + 5 + 3 + read-write + + + B_0x1 + nWR=3 + 0x1 + + + B_0x4 + nWR=6 + 0x4 + + + B_0x6 + nWR=8 + 0x6 + + + B_0x7 + nWR=9 + 0x7 + + + + + + + DDRPHYC_LPDDR3_MR1 + DDRPHYC_LPDDR3_MR1 + DDRPHYC_LPDDR3_MR1 + DDRPHYC_DDR3_MR1 + 0x44 + 0x20 + read-write + 0x00000000 + 0x0000FFFF + + + BL + Burst length +Determines the maximum number of column locations that can be accessed during a given read or write command. +Others: Reserved + 0 + 3 + read-write + + + B_0x3 + 8 + 0x3 + + + + + NWR + Write recovery +If nWRE (MR2 [4]) = 0: +-001: nWR=3 +-100: nWR=6 +-110: nWR=8 +-111: nWR=9 +If nWRE (MR2[4]) = 1: +-000: nWR=10 +-001: nWR=11 +-010: nWR=12 +Others: Reserved + 5 + 3 + read-write + + + + + DDRPHYC_DDR3_MR2 + DDRPHYC_DDR3_MR2 + DDRPHYC MR2 register for DDR3 + 0x48 + 16 + 0x00000000 + 0x0000FFFF + + + PASR + Partial array self-refresh +Specifies that data located in areas of the array beyond the specified location are lost if self refresh is entered. +Valid settings for 8 banks are: + 0 + 3 + read-write + + + B_0x0 + Full Array + 0x0 + + + B_0x1 + Half Array (BA[2:0] = 000, 001, 010 & 011) + 0x1 + + + B_0x2 + Quarter Array (BA[2:0] = 000, 001) + 0x2 + + + B_0x3 + 1/8 Array (BA[2:0] = 000) + 0x3 + + + B_0x4 + 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) + 0x4 + + + B_0x5 + Half Array (BA[2:0] = 100, 101, 110 & 111) + 0x5 + + + B_0x6 + Quarter Array (BA[2:0] = 110 & 111) + 0x6 + + + B_0x7 + 1/8 Array (BA[2:0] 111) + 0x7 + + + + + CWL + CAS write latency +The delay, in clock cycles, between when the SDRAM registers a write command to when write data is available. +Others: Reserved + 3 + 3 + read-write + + + B_0x0 + 5 (tCK = 2.5ns) + 0x0 + + + B_0x1 + 6 (2.5ns > tCK = 1.875ns) + 0x1 + + + B_0x2 + 7 (1.875ns > tCK = 1.5ns) + 0x2 + + + B_0x3 + 8 (1.5ns > tCK = 1.25ns) + 0x3 + + + + + ASR + Auto self-refresh +When enabled ('1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. +Otherwise the SRT bit must be programmed to indicate the temperature range. + 6 + 1 + read-write + + + SRT + Self-refresh temperature range +Selects either normal ('0’) or extended ('1’) operating temperature range during self-refresh. + 7 + 1 + read-write + + + RTTWR + Dynamic ODT +Selects RTT for dynamic ODT. + 9 + 2 + read-write + + + B_0x0 + Dynamic ODT off + 0x0 + + + B_0x1 + RZQ/4 + 0x1 + + + B_0x2 + RZQ/2 + 0x2 + + + + + + + DDRPHYC_LPDDR2_MR2 + DDRPHYC_LPDDR2_MR2 + DDRPHYC MR2 register for LPDDR2 + DDRPHYC_DDR3_MR2 + 0x48 + 0x20 + read-write + 0x00000000 + 0x0000FFFF + + + RLWL + Read and write latency +Others: Reserved + 0 + 3 + read-write + + + B_0x1 + RL = 3 /WL = 1 + 0x1 + + + B_0x2 + RL = 4 / WL = 2 + 0x2 + + + B_0x3 + RL = 5 / WL = 2 + 0x3 + + + B_0x4 + RL = 6 / WL = 3 + 0x4 + + + B_0x5 + RL = 7 / WL = 4 + 0x5 + + + B_0x6 + RL = 8 / WL = 4 + 0x6 + + + + + + + DDRPHYC_LPDDR3_MR2 + DDRPHYC_LPDDR3_MR2 + DDRPHYC MR2 register for LPDDR3 + DDRPHYC_DDR3_MR2 + 0x48 + 0x20 + read-write + 0x00000000 + 0x0000FFFF + + + RLWL + Read and write latency +Others: Reserved + 0 + 3 + read-write + + + B_0x1 + RL = 3 /WL = 1 + 0x1 + + + B_0x2 + RL = 4 / WL = 2 + 0x2 + + + B_0x3 + RL = 5 / WL = 2 + 0x3 + + + B_0x4 + RL = 6 / WL = 3 + 0x4 + + + B_0x5 + RL = 7 / WL = 4 + 0x5 + + + B_0x6 + RL = 8 / WL = 4 + 0x6 + + + + + NWRE + New for LPDDR3 (not used by this PHY, leave at zero) + 4 + 1 + read-write + + + WL + New for LPDDR3 (not used by this PHY, leave at zero) + 6 + 1 + read-write + + + WR + New for LPDDR3 (not used by this PHY, leave at zero) + 7 + 1 + read-write + + + + + DDRPHYC_DDR3_MR3 + DDRPHYC_DDR3_MR3 + DDRPHYC MR3 register for DDR3 + 0x4c + 8 + 0x00000000 + 0x000000FF + + + MPRLOC + Multi-purpose register (MPR) location +Selects MPR data location. +Others: Reserved + 0 + 2 + read-write + + + B_0x0 + Predefined pattern for system calibration + 0x0 + + + + + MPR + Multi-purpose register enable +Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. + 2 + 1 + read-write + + + + + DDRPHYC_ODTCR + DDRPHYC_ODTCR + DDRPHYC ODTC register + 0x50 + 0x20 + 0x00010000 + 0xFFFFFFFF + + + RDODT + Specifies whether ODT should be enabled ('1’) or disabled ('0’) on read + 0 + 1 + read-write + + + WRODT + Specifies whether ODT should be enabled ('1’) or disabled ('0’) on write + 16 + 1 + read-write + + + + + DDRPHYC_DTAR + DDRPHYC_DTAR + DDRPHYC DTA register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTCOL + Data training column address: +Selects the SDRAM column address to be used during data training. +The lower four bits of this address must always be “0000”. + 0 + 12 + read-write + + + DTROW + Data training row address: +Selects the SDRAM row address to be used during data training. + 12 + 16 + read-write + + + DTBANK + Data training bank address: +Selects the SDRAM bank address to be used during data training. + 28 + 3 + read-write + + + DTMPR + Data training using MPR (DDR3 Only): +Specifies, if set, that data-training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading the back. + 31 + 1 + read-write + + + + + DDRPHYC_DTDR0 + DDRPHYC_DTDR0 + DDRPHYC DTD register 0 + 0x58 + 0x20 + 0xDD22EE11 + 0xFFFFFFFF + + + DTBYTE0 + Data Training Data + 0 + 8 + read-write + + + DTBYTE1 + Data Training Data + 8 + 8 + read-write + + + DTBYTE2 + Data Training Data + 16 + 8 + read-write + + + DTBYTE3 + Data training data +The first 4 bytes (e.g. shifted as Byte 0,1,2,3) of data used during data training. This same data byte is used for each Byte Lane. +Default sequence is a walking 1 while toggling data every data cycle. + 24 + 8 + read-write + + + + + DDRPHYC_DTDR1 + DDRPHYC_DTDR1 + DDRPHYC DTD register 1 + 0x5c + 0x20 + 0x7788BB44 + 0xFFFFFFFF + + + DTBYTE4 + Data Training Data + 0 + 8 + read-write + + + DTBYTE5 + Data Training Data + 8 + 8 + read-write + + + DTBYTE6 + Data Training Data + 16 + 8 + read-write + + + DTBYTE7 + Data training data: +The second 4 bytes (e.g. shifted as Byte 4,5,6,7) of data used during data training. This same data byte is used for each Byte Lane. +Default sequence is a walking 1 while toggling data every data cycle. + 24 + 8 + read-write + + + + + DDRPHYC_GPR0 + DDRPHYC_GPR0 + DDRPHYC general purpose register 0 + 0x178 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPR0 + General purpose register 0 bits + 0 + 32 + read-write + + + + + DDRPHYC_GPR1 + DDRPHYC_GPR1 + DDRPHYC general purpose register 1 + 0x17c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPR1 + General purpose register 1 bits + 0 + 32 + read-write + + + + + DDRPHYC_ZQ0CR0 + DDRPHYC_ZQ0CR0 + DDRPHYC ZQ0C register 0 + 0x180 + 0x20 + 0x0000014A + 0xFFFFFFFF + + + ZDATA + Impedance override +Impedance Over-Ride Data: Data used to directly drive the impedance control. +ZDATA field mapping for D3R I/Os is as follows: +ZDATA[27:20] is reserved and returns zeros on reads +ZDATA[19:15] is used to select the pull-up on-die termination impedance +ZDATA[14:10] is used to select the pull-down on-die termination impedance +ZDATA[9:5] is used to select the pull-up output impedance +ZDATA[4:0] is used to select the pull-down output impedance +Note: See mPHY ST40c25 Datasheet for ZDATA encoding, default value is: ODT pulp-up/down set to hi-impedance and pull-up/down set to ~44.5 Ω for DDR3, 48.8 Ω for DDR3L, 55.5 Ω for LPDDR2 typical corner 25C + 0 + 20 + read-write + + + ZDEN + Impedance override enable +Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZQDATA field. Otherwise, the control is generated automatically by the impedance control logic. +Note: If ZDEN is set, then the ZCAL bit should be set to 0. + 28 + 1 + read-write + + + ZCALBYP + Impedance calibration bypass +Impedance Calibration Bypass: Disables, if set, impedance calibration of this ZQ control block when impedance calibration is triggered globally using the ZCAL bit of DDRPHYC_PIR. +Impedance calibration of this ZQ block may be triggered manually using ZCAL. + 29 + 1 + read-write + + + ZCAL + ZCAL trigger +Impedance Calibration Trigger: A write of '1' to this bit triggers impedance calibration to be performed by the impedance control logic. +The impedance calibration trigger bit is self-clearing and returns back to '0' when the calibration is complete. +Note: If ZDEN is set, then the ZCAL bit should be set to 0. + 30 + 1 + read-write + + + ZQPD + ZCAL power down +Powers down, if set, the PZQ cell. + 31 + 1 + read-write + + + + + DDRPHYC_ZQ0CR1 + DDRPHYC_ZQ0CR1 + DDRPHYC ZQ0CR1 register + 0x184 + 8 + 0x0000007B + 0x000000FF + + + ZPROG + Impedance divide ratio to ext R +Impedance divide ratio: selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: +null Ω ±1%) +- 0x0: Reserved +- 0x1: 120 Ω +- 0x2: 96 Ω +- 0x3: 80 Ω +- 0x4: 69 Ω +- 0x5: 60 Ω +- 0x6: 52Ω +- 0x7: 46 Ω +- 0x8: 40 Ω +- 0x9: 37 Ω +- 0xA: 34 Ω +- 0xB: 32 Ω +- 0xC: 30 Ω +- 0xD: 28 Ω +- 0xE: 26.5 Ω +- 0xF: 25 Ω +nullImpedance divide ratio to ext R +Impedance divide ratio: selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: +null Ω ±1%) +- 0x0 to 0x4: Reserved +- 0x5: 80 Ω +- 0x6: 69 Ω +- 0x7: 60 Ω +- 0x8: 53 Ω +- 0x9: 48 Ω +- 0xA: 44 Ω +- 0xB: 40 Ω +- 0xC: 37 Ω +- 0xD: 34 Ω +- 0xE: 32 Ω +- 0xF: 30 Ω + 0 + 8 + read-write + + + + + DDRPHYC_ZQ0SR0 + DDRPHYC_ZQ0SR0 + DDRPHYC ZQ0S register 0 + 0x188 + 0x20 + 0x0000014A + 0xFFFFFFFF + + + ZCTRL + Impedance control +Impedance Control: Current value of impedance control. +ZZCTRL field mapping for D3R I/Os is as follows: +ZCTRL[27:20] is reserved and returns zeros on reads +ZCTRL[19:15] is used to select the pull-up on-die termination impedance +ZCTRL[14:10] is used to select the pull-down on-die termination impedance +ZCTRL[9:5] is used to select the pull-up output impedance +ZCTRL[4:0] is used to select the pull-down output impedance + 0 + 20 + read-only + + + ZERR + Impedance calibration error +If set, indicates that there was an error during impedance calibration. + 30 + 1 + read-only + + + ZDONE + Impedance calibration done +Indicates that impedance calibration has completed. + 31 + 1 + read-only + + + + + DDRPHYC_ZQ0SR1 + DDRPHYC_ZQ0SR1 + DDRPHYC ZQ0S register 1 + 0x18c + 8 + 0x00000000 + 0x000000FF + + + ZPD + zpd calibration status +Output impedance pull-down calibration status. Valid status encodings are: + 0 + 2 + read-only + + + B_0x0 + Completed with no errors + 0x0 + + + B_0x1 + Overflow error + 0x1 + + + B_0x2 + Underflow error + 0x2 + + + B_0x3 + Calibration in progress + 0x3 + + + + + ZPU + zpu calibration status +Output impedance pull-up calibration status. Valid status encodings are: + 2 + 2 + read-only + + + B_0x0 + Completed with no errors + 0x0 + + + B_0x1 + Overflow error + 0x1 + + + B_0x2 + Underflow error + 0x2 + + + B_0x3 + Calibration in progress + 0x3 + + + + + OPD + opd calibration status +On-Die termination (ODT) pull-down calibration status. + 4 + 2 + read-only + + + B_0x0 + Completed with no errors + 0x0 + + + B_0x1 + Overflow error + 0x1 + + + B_0x2 + Underflow error + 0x2 + + + B_0x3 + Calibration in progress + 0x3 + + + + + OPU + opu calibration status +On-Die termination (ODT) pull-up calibration status. + 6 + 2 + read-only + + + B_0x0 + Completed with no errors + 0x0 + + + B_0x1 + Overflow error + 0x1 + + + B_0x2 + Underflow error + 0x2 + + + B_0x3 + Calibration in progress + 0x3 + + + + + + + DDRPHYC_DX0GCR + DDRPHYC_DX0GCR + DDRPHYC byte lane 0 GC register + 0x1c0 + 0x20 + 0x00010E81 + 0xFFFFFFFF + + + DXEN + DATA byte enable +Enables, if set, the DATX8 and SSTL I/Os used on the data byte. +Setting this bit to '0’ disables the byte, i.e. the byte SSTL I/Os are put in power-down mode and the DLL in the DATX8 is put in bypass mode. +After changing a Byte Lane from disabled to enabled, the DLL for that Byte Lane must be reset and re-locked. +Software can use bits DLLSRST and DLLLOCK of DDRPHYC_PIR register to accomplish this (reset and re-locks all DLLs in the DDR PHY). + 0 + 1 + read-write + + + DQSODT + DQS ODT enable +Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. +This bit is ORed with the common DATX8 ODT configuration bit + 1 + 1 + read-write + + + DQODT + DQ ODT enable +Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. +This bit is ORed with the common DATX8 ODT configuration bit + 2 + 1 + read-write + + + DXIOM + Data I/O mode +Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) for the I/O for DQ, DM, and DQS/DQS# pins of the byte. +This bit is ORed with the IOM configuration bit of the individual DATX8 + 3 + 1 + read-write + + + DXPDD + Data power-down driver +Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit + 4 + 1 + read-write + + + DXPDR + Data power-down receiver +Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit + 5 + 1 + read-write + + + DQSRPD + DQSR power-down +Powers down, if set, the PDQSR cell. +This bit is ORed with the common PDR configuration bit + 6 + 1 + read-write + + + DSEN + Write DQS enable +Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. +DQS# is always the inversion of DQS. +These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. +Valid settings are: + 7 + 2 + read-write + + + B_0x0 + DQS disabled (Driven to constant 0) + 0x0 + + + B_0x1 + DQS toggling with normal polarity (This should be the default setting) + 0x1 + + + B_0x2 + DQS toggling with inverted polarity + 0x2 + + + B_0x3 + DQS disabled (Driven to constant 1) + 0x3 + + + + + DQSRTT + DQS dynamic RTT control +Indicates, if set, that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0’) during any other cycle. +If this bit is not set, then the ODT control of DQS SSTL I/Os is always set to the value in DQSODT field. +Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 since LPDDR2/LPDDR3 does not require ODT to be on. + 9 + 1 + read-write + + + DQRTT + DQ dynamic RTT control +Indicates, if set, that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0’) during any other cycle. +If this bit is not set, then the ODT control of DQ SSTL I/Os is always set to the value in DQODT. +Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 +since LPDDR2/LPDDR3 does not require ODT to be on.` + 10 + 1 + read-write + + + RTTOH + RTT output hold +Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0’) when using dynamic ODT control. +ODT is disabled almost RTTOH clock cycles after the read postamble + 11 + 2 + read-write + + + RTTOAL + RTT ON additive latency +Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. +Valid values are: + 13 + 1 + read-write + + + B_0x0 + ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + 0x0 + + + B_0x1 + ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + 0x1 + + + + + R0RVSL + Read valid system latency in steps +Used to specify the read valid system latency relative to the ideal placement of the ITMD read valid signal when bit RVSEL in DDRPHYC_DXCCR register is set to 0. +Power-up default is 011 (i.e. ideal placement of the read valid signal). +The RVSL fields are initially set by the PUB during automatic read valid training but these values can be overwritten by a direct write to this register. +Valid values are: +Others: Reserved + 14 + 3 + read-write + + + B_0x0 + read valid system latency = ideal placement - 3 + 0x0 + + + B_0x1 + read valid system latency = ideal placement - 2 + 0x1 + + + B_0x2 + read valid system latency = ideal placement - 1 + 0x2 + + + B_0x3 + read valid system latency = ideal placement + 0x3 + + + B_0x4 + read valid system latency = ideal placement + 1 + 0x4 + + + B_0x5 + read valid system latency = ideal placement + 2 + 0x5 + + + B_0x6 + read valid system latency = ideal placement + 3 + 0x6 + + + + + + + DDRPHYC_DX0GSR0 + DDRPHYC_DX0GSR0 + DDRPHYC byte lane 0 GS register 0 + 0x1c4 + 16 + 0x00000000 + 0x0000FFFF + + + DTDONE + Data training done +Indicates, if set, that the byte has finished doing data training. + 0 + 1 + read-only + + + DTERR + DQS gate training error +If set, indicates that a valid DQS gating window could not be found during DQS gate training of the byte. + 4 + 1 + read-only + + + DTIERR + DQS gate training intermittent error +If set, indicates that there was an intermittent error during DQS gate training of the byte, such as a pass was followed by a fail then followed by another pass. + 8 + 1 + read-only + + + DTPASS + DQS training pass count +The number of passing configurations during DQS gate training. + 13 + 3 + read-only + + + + + DDRPHYC_DX0GSR1 + DDRPHYC_DX0GSR1 + DDRPHYC byte lane 0 GS register 1 + 0x1c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFTERR + DQS drift error +If set, indicates that the byte read data strobe has drifted by more than or equal to the drift limit set in the PHY General Configuration Register (PGCR). + 0 + 1 + read-only + + + DQSDFT + DQS drift value +Used to report the drift on the read data strobe of the data byte. +Valid settings are: + 4 + 2 + read-only + + + B_0x0 + No drift + 0x0 + + + B_0x1 + 90° drift + 0x1 + + + B_0x2 + 180° drift + 0x2 + + + B_0x3 + 270° drift or more + 0x3 + + + + + RVERR + RV training error +If set, indicates that a valid read valid placement could not be found during read valid training of the byte + 12 + 1 + read-only + + + RVIERR + RV intermittent error for rank +If set, indicates that there was an intermittent error during read valid training of the byte, such as a pass was followed by a fail then followed by another pass. + 16 + 1 + read-only + + + RVPASS + Read valid training pass count +The number of passing configurations during read valid training. + 20 + 3 + read-only + + + + + DDRPHYC_DX0DLLCR + DDRPHYC_DX0DLLCR + DDRPHYC byte lane 0 DLLC register + 0x1cc + 0x20 + 0x40000000 + 0xFFFFFFFF + + + SFBDLY + Slave DLL feed-back trim +Slave Feed-Back Delay Trim: Used to trim the delay in the slave DLL feedback path: +... + 0 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + SFWDLY + Slave DLL feed-forward trim +Slave Feed-Forward Delay Trim: Used to trim the delay in the slave DLL feedforward path: +... + 3 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + MFBDLY + Master DLL feed-back trim +Used to trim the delay in the master DLL feedback path: +... + 6 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + MFWDLY + Master DLL feed-forward trim +Used to trim the delay in the master DLL feedforward path: +... + 9 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + SSTART + Slave DLL autostart +Used to control how the slave DLL starts up relative to the +master DLL locking: +0X: Slave DLL automatically starts up once the master DLL has achieved lock. +disabled. +enabled. + 12 + 2 + read-write + + + B_0x2 + The automatic startup of the slave DLL is disabled; the phase detector is + 0x2 + + + B_0x3 + The automatic startup of the slave DLL is disabled; the phase detector is + 0x3 + + + + + SDPHASE + Slave DLL phase +Selects the phase difference between the input clock and +the corresponding output clock of the slave DLL. Valid settings: + 14 + 4 + read-write + + + B_0x0 + 90 + 0x0 + + + B_0x1 + 72 + 0x1 + + + B_0x2 + 54 + 0x2 + + + B_0x3 + 36 + 0x3 + + + B_0x4 + 108 + 0x4 + + + B_0x5 + 90 + 0x5 + + + B_0x6 + 72 + 0x6 + + + B_0x7 + 54 + 0x7 + + + B_0x8 + 126 + 0x8 + + + B_0x9 + 108 + 0x9 + + + B_0xA + 90 + 0xA + + + B_0xB + 72 + 0xB + + + B_0xC + 144 + 0xC + + + B_0xD + 126 + 0xD + + + B_0xE + 108 + 0xE + + + B_0xF + 90 + 0xF + + + + + ATESTEN + Enable path to pin 'ATO' +Enables the analog test signal to be output on the DLL analog test output (test_out_a). +The DLL analog test output is tri-stated when this bit is '0'. + 18 + 1 + read-write + + + SDLBMODE + Bypass slave DLL during loopback +If this bit is set, the slave DLL is put in loopback mode in which there is no 90 degrees phase shift on read DQS/DQS#. This bit must be set when operating the byte PHYs in loopback mode. + 19 + 1 + read-write + + + DLLSRST + DLL reset +Soft resets the byte DLL by driving the DLL soft reset pin + 30 + 1 + read-write + + + DLLDIS + DLL bypass +A disabled DLL is bypassed. Default ('0') is DLL enabled + 31 + 1 + read-write + + + + + DDRPHYC_DX0DQTR + DDRPHYC_DX0DQTR + DDRPHYC byte lane 0 DQT register + 0x1d0 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DQDLY0 + DQ delay for bit 0 +Idem + 0 + 4 + read-write + + + DQDLY1 + DQ delay for bit 1 +Idem + 4 + 4 + read-write + + + DQDLY2 + DQ delay for bit 2 +Idem + 8 + 4 + read-write + + + DQDLY3 + DQ delay for bit 3 +Idem + 12 + 4 + read-write + + + DQDLY4 + DQ delay for bit 4 +Idem + 16 + 4 + read-write + + + DQDLY5 + DQ delay for bit 5 +Idem + 20 + 4 + read-write + + + DQDLY6 + DQ delay for bit 6 +idem + 24 + 4 + read-write + + + DQDLY7 + DQ delay for bit 7 +Used to adjust the delay of the data relative to the nominal delay that is matched to the delay of the data strobes through the slave DLL and clock tree. +The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by DQS, while the higher two bits control the delay for the data clocked by DQS_b. +Valid settings for each 2-bit control field are: + 28 + 4 + read-write + + + B_0x0 + nominal delay + 0x0 + + + B_0x1 + nominal delay + 1 step + 0x1 + + + B_0x2 + nominal delay + 2 steps + 0x2 + + + B_0x3 + nominal delay + 3 steps + 0x3 + + + + + + + DDRPHYC_DX0DQSTR + DDRPHYC_DX0DQSTR + DDRPHYC byte lane 0 DQST register + 0x1d4 + 0x20 + 0x3DB02000 + 0xFFFFFFFF + + + R0DGSL + Rank 0 DQS gating system latency +Used to increase the number of clock cycles needed to expect valid DDR read data by up to five extra clock cycles. +This is used to compensate for board delays and other system delays. +Power-up default is 000 (i.e. no extra clock cycles required). +The SL fields are initially set by the PUBL during automatic DQS data training but these values can be overwritten by a direct write to this register. +Valid values are: +Others: Reserved + 0 + 3 + read-write + + + B_0x0 + No extra clock cycles + 0x0 + + + B_0x1 + 1 extra clock cycle + 0x1 + + + B_0x2 + 2 extra clock cycles + 0x2 + + + B_0x3 + 3 extra clock cycles + 0x3 + + + B_0x4 + 4 extra clock cycles + 0x4 + + + B_0x5 + 5 extra clock cycles + 0x5 + + + + + R0DGPS + Rank 0 DQS gating phase select +Selects the clock used to enable the data strobes during read so that the value of the data strobes before and after the preamble/postamble are filtered out. +R0DGPS is initially set by the PUBL during automatic DQS data training and subsequently updated during data strobe drift compensation. However, these values can be overwritten by a direct write to this register, and the automatic update during DQS drift compensation can be disabled using the PHY General Configuration Register (PGCR). +Valid values are: + 12 + 2 + read-write + + + B_0x0 + 180 clock (clk180) + 0x0 + + + B_0x1 + 270 clock (clk270) + 0x1 + + + B_0x2 + 360 clock (clk0) + 0x2 + + + B_0x3 + 450 clock (next clk90) + 0x3 + + + + + DQSDLY + DQS delay +Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the slave DLL and clock tree. +Valid values are: +Note: - After changing this value, an ITM soft reset (bit ITMSRST=1 and bit INIT=1 in DDRPHYC_PIR register) must be issued. + 20 + 3 + read-write + + + B_0x0 + nominal delay - 3 steps + 0x0 + + + B_0x1 + nominal delay - 2 steps + 0x1 + + + B_0x2 + nominal delay - 1 step + 0x2 + + + B_0x3 + nominal delay + 0x3 + + + B_0x4 + nominal delay + 1 step + 0x4 + + + B_0x5 + nominal delay + 2 steps + 0x5 + + + B_0x6 + nominal delay + 3 steps + 0x6 + + + B_0x7 + nominal delay + 4 steps + 0x7 + + + + + DQSNDLY + DQS# delay +Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the slave DLL and clock tree. +Valid values are: +Note: - After changing this value, an ITM soft reset must be issued: bit ITMSRST=1 and bit INIT=1 in DDRPHYC_PIR register. + 23 + 3 + read-write + + + B_0x0 + nominal delay - 3 steps + 0x0 + + + B_0x1 + nominal delay - 2 steps + 0x1 + + + B_0x2 + nominal delay - 1 step + 0x2 + + + B_0x3 + nominal delay + 0x3 + + + B_0x4 + nominal delay + 1 step + 0x4 + + + B_0x5 + nominal delay + 2 steps + 0x5 + + + B_0x6 + nominal delay + 3 steps + 0x6 + + + B_0x7 + nominal delay + 4 steps + 0x7 + + + + + DMDLY + DM delay +Used to adjust the delay of the data relative to the nominal delay that is matched to the delay of the data strobes through the slave DLL and clock tree. +The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by DQS, while the higher two bits control the delay for the data clocked by DQS_b. +Valid settings for each 2-bit control field are: + 26 + 4 + read-write + + + B_0x0 + nominal delay + 0x0 + + + B_0x1 + nominal delay + 1 step + 0x1 + + + B_0x2 + nominal delay + 2 steps + 0x2 + + + B_0x3 + nominal delay + 3 steps + 0x3 + + + + + + + DDRPHYC_DX1GCR + DDRPHYC_DX1GCR + DDRPHYC byte lane 1 GC register + 0x200 + 0x20 + 0x00010E81 + 0xFFFFFFFF + + + DXEN + DATA byte enable +Enables, if set, the DATX8 and SSTL I/Os used on the data byte. +Setting this bit to '0’ disables the byte, i.e. the byte SSTL I/Os are put in power-down mode and the DLL in the DATX8 is put in bypass mode. +After changing a Byte Lane from disabled to enabled, the DLL for that Byte Lane must be reset and re-locked. +Software can use bits DLLSRST and DLLLOCK of DDRPHYC_PIR register to accomplish this (reset and re-locks all DLLs in the DDR PHY). + 0 + 1 + read-write + + + DQSODT + DQS ODT enable +Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. +This bit is ORed with the common DATX8 ODT configuration bit + 1 + 1 + read-write + + + DQODT + DQ ODT enable +Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. +This bit is ORed with the common DATX8 ODT configuration bit + 2 + 1 + read-write + + + DXIOM + Data I/O mode +Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) for the I/O for DQ, DM, and DQS/DQS# pins of the byte. +This bit is ORed with the IOM configuration bit of the individual DATX8 + 3 + 1 + read-write + + + DXPDD + Data power-down driver +Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit + 4 + 1 + read-write + + + DXPDR + Data power-down receiver +Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit + 5 + 1 + read-write + + + DQSRPD + DQSR power-down +Powers down, if set, the PDQSR cell. +This bit is ORed with the common PDR configuration bit + 6 + 1 + read-write + + + DSEN + Write DQS enable +Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. +DQS# is always the inversion of DQS. +These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. +Valid settings are: + 7 + 2 + read-write + + + B_0x0 + DQS disabled (Driven to constant 0) + 0x0 + + + B_0x1 + DQS toggling with normal polarity (This should be the default setting) + 0x1 + + + B_0x2 + DQS toggling with inverted polarity + 0x2 + + + B_0x3 + DQS disabled (Driven to constant 1) + 0x3 + + + + + DQSRTT + DQS dynamic RTT control +Indicates, if set, that the ODT control of DQS SSTL I/Os be dynamically controlled by setting it to the value in DQSODT during reads and disabling it (setting it to '0’) during any other cycle. +If this bit is not set, then the ODT control of DQS SSTL I/Os is always set to the value in DQSODT field. +Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 since LPDDR2/LPDDR3 does not require ODT to be on. + 9 + 1 + read-write + + + DQRTT + DQ dynamic RTT control +Indicates, if set, that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by setting it to the value in DQODT during reads and disabling it (setting it to '0’) during any other cycle. +If this bit is not set, then the ODT control of DQ SSTL I/Os is always set to the value in DQODT. +Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0 +since LPDDR2/LPDDR3 does not require ODT to be on.` + 10 + 1 + read-write + + + RTTOH + RTT output hold +Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0’) when using dynamic ODT control. +ODT is disabled almost RTTOH clock cycles after the read postamble + 11 + 2 + read-write + + + RTTOAL + RTT ON additive latency +Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. +Valid values are: + 13 + 1 + read-write + + + B_0x0 + ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + 0x0 + + + B_0x1 + ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + 0x1 + + + + + R0RVSL + Read valid system latency in steps +Used to specify the read valid system latency relative to the ideal placement of the ITMD read valid signal when bit RVSEL in DDRPHYC_DXCCR register is set to 0. +Power-up default is 011 (i.e. ideal placement of the read valid signal). +The RVSL fields are initially set by the PUB during automatic read valid training but these values can be overwritten by a direct write to this register. +Valid values are: +Others: Reserved + 14 + 3 + read-write + + + B_0x0 + read valid system latency = ideal placement - 3 + 0x0 + + + B_0x1 + read valid system latency = ideal placement - 2 + 0x1 + + + B_0x2 + read valid system latency = ideal placement - 1 + 0x2 + + + B_0x3 + read valid system latency = ideal placement + 0x3 + + + B_0x4 + read valid system latency = ideal placement + 1 + 0x4 + + + B_0x5 + read valid system latency = ideal placement + 2 + 0x5 + + + B_0x6 + read valid system latency = ideal placement + 3 + 0x6 + + + + + + + DDRPHYC_DX1GSR0 + DDRPHYC_DX1GSR0 + DDRPHYC byte lane 1 GS register 0 + 0x204 + 16 + 0x00000000 + 0x0000FFFF + + + DTDONE + Data training done +Indicates, if set, that the byte has finished doing data training. + 0 + 1 + read-only + + + DTERR + DQS gate training error +If set, indicates that a valid DQS gating window could not be found during DQS gate training of the byte. + 4 + 1 + read-only + + + DTIERR + DQS gate training intermittent error +If set, indicates that there was an intermittent error during DQS gate training of the byte, such as a pass was followed by a fail then followed by another pass. + 8 + 1 + read-only + + + DTPASS + DQS training pass count +The number of passing configurations during DQS gate training. + 13 + 3 + read-only + + + + + DDRPHYC_DX1GSR1 + DDRPHYC_DX1GSR1 + DDRPHYC byte lane 1 GS register 1 + 0x208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFTERR + DQS drift error +If set, indicates that the byte read data strobe has drifted by more than or equal to the drift limit set in the PHY General Configuration Register (PGCR). + 0 + 1 + read-only + + + DQSDFT + DQS drift value +Used to report the drift on the read data strobe of the data byte. +Valid settings are: + 4 + 2 + read-only + + + B_0x0 + No drift + 0x0 + + + B_0x1 + 90° drift + 0x1 + + + B_0x2 + 180° drift + 0x2 + + + B_0x3 + 270° drift or more + 0x3 + + + + + RVERR + RV training error +If set, indicates that a valid read valid placement could not be found during read valid training of the byte + 12 + 1 + read-only + + + RVIERR + RV intermittent error for rank +If set, indicates that there was an intermittent error during read valid training of the byte, such as a pass was followed by a fail then followed by another pass. + 16 + 1 + read-only + + + RVPASS + Read valid training pass count +The number of passing configurations during read valid training. + 20 + 3 + read-only + + + + + DDRPHYC_DX1DLLCR + DDRPHYC_DX1DLLCR + DDRPHYC byte lane 1 DLLC register + 0x20c + 0x20 + 0x40000000 + 0xFFFFFFFF + + + SFBDLY + Slave DLL feed-back trim +Slave Feed-Back Delay Trim: Used to trim the delay in the slave DLL feedback path: +... + 0 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + SFWDLY + Slave DLL feed-forward trim +Slave Feed-Forward Delay Trim: Used to trim the delay in the slave DLL feedforward path: +... + 3 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + MFBDLY + Master DLL feed-back trim +Used to trim the delay in the master DLL feedback path: +... + 6 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + MFWDLY + Master DLL feed-forward trim +Used to trim the delay in the master DLL feedforward path: +... + 9 + 3 + read-write + + + B_0x0 + minimum delay + 0x0 + + + B_0x7 + maximum delay + 0x7 + + + + + SSTART + Slave DLL autostart +Used to control how the slave DLL starts up relative to the +master DLL locking: +0X: Slave DLL automatically starts up once the master DLL has achieved lock. +disabled. +enabled. + 12 + 2 + read-write + + + B_0x2 + The automatic startup of the slave DLL is disabled; the phase detector is + 0x2 + + + B_0x3 + The automatic startup of the slave DLL is disabled; the phase detector is + 0x3 + + + + + SDPHASE + Slave DLL phase +Selects the phase difference between the input clock and +the corresponding output clock of the slave DLL. Valid settings: + 14 + 4 + read-write + + + B_0x0 + 90 + 0x0 + + + B_0x1 + 72 + 0x1 + + + B_0x2 + 54 + 0x2 + + + B_0x3 + 36 + 0x3 + + + B_0x4 + 108 + 0x4 + + + B_0x5 + 90 + 0x5 + + + B_0x6 + 72 + 0x6 + + + B_0x7 + 54 + 0x7 + + + B_0x8 + 126 + 0x8 + + + B_0x9 + 108 + 0x9 + + + B_0xA + 90 + 0xA + + + B_0xB + 72 + 0xB + + + B_0xC + 144 + 0xC + + + B_0xD + 126 + 0xD + + + B_0xE + 108 + 0xE + + + B_0xF + 90 + 0xF + + + + + ATESTEN + Enable path to pin 'ATO' +Enables the analog test signal to be output on the DLL analog test output (test_out_a). +The DLL analog test output is tri-stated when this bit is '0'. + 18 + 1 + read-write + + + SDLBMODE + Bypass slave DLL during loopback +If this bit is set, the slave DLL is put in loopback mode in which there is no 90 degrees phase shift on read DQS/DQS#. This bit must be set when operating the byte PHYs in loopback mode. + 19 + 1 + read-write + + + DLLSRST + DLL reset +Soft resets the byte DLL by driving the DLL soft reset pin + 30 + 1 + read-write + + + DLLDIS + DLL bypass +A disabled DLL is bypassed. Default ('0') is DLL enabled + 31 + 1 + read-write + + + + + DDRPHYC_DX1DQTR + DDRPHYC_DX1DQTR + DDRPHYC byte lane 1 DQT register + 0x210 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DQDLY0 + DQ delay for bit 0 +Idem + 0 + 4 + read-write + + + DQDLY1 + DQ delay for bit 1 +Idem + 4 + 4 + read-write + + + DQDLY2 + DQ delay for bit 2 +Idem + 8 + 4 + read-write + + + DQDLY3 + DQ delay for bit 3 +Idem + 12 + 4 + read-write + + + DQDLY4 + DQ delay for bit 4 +Idem + 16 + 4 + read-write + + + DQDLY5 + DQ delay for bit 5 +Idem + 20 + 4 + read-write + + + DQDLY6 + DQ delay for bit 6 +idem + 24 + 4 + read-write + + + DQDLY7 + DQ delay for bit 7 +Used to adjust the delay of the data relative to the nominal delay that is matched to the delay of the data strobes through the slave DLL and clock tree. +The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by DQS, while the higher two bits control the delay for the data clocked by DQS_b. +Valid settings for each 2-bit control field are: + 28 + 4 + read-write + + + B_0x0 + nominal delay + 0x0 + + + B_0x1 + nominal delay + 1 step + 0x1 + + + B_0x2 + nominal delay + 2 steps + 0x2 + + + B_0x3 + nominal delay + 3 steps + 0x3 + + + + + + + DDRPHYC_DX1DQSTR + DDRPHYC_DX1DQSTR + DDRPHYC byte lane 1 DQST register + 0x214 + 0x20 + 0x3DB02000 + 0xFFFFFFFF + + + R0DGSL + Rank 0 DQS gating system latency +Used to increase the number of clock cycles needed to expect valid DDR read data by up to five extra clock cycles. +This is used to compensate for board delays and other system delays. +Power-up default is 000 (i.e. no extra clock cycles required). +The SL fields are initially set by the PUBL during automatic DQS data training but these values can be overwritten by a direct write to this register. +Valid values are: +Others: Reserved + 0 + 3 + read-write + + + B_0x0 + No extra clock cycles + 0x0 + + + B_0x1 + 1 extra clock cycle + 0x1 + + + B_0x2 + 2 extra clock cycles + 0x2 + + + B_0x3 + 3 extra clock cycles + 0x3 + + + B_0x4 + 4 extra clock cycles + 0x4 + + + B_0x5 + 5 extra clock cycles + 0x5 + + + + + R0DGPS + Rank 0 DQS gating phase select +Selects the clock used to enable the data strobes during read so that the value of the data strobes before and after the preamble/postamble are filtered out. +R0DGPS is initially set by the PUBL during automatic DQS data training and subsequently updated during data strobe drift compensation. However, these values can be overwritten by a direct write to this register, and the automatic update during DQS drift compensation can be disabled using the PHY General Configuration Register (PGCR). +Valid values are: + 12 + 2 + read-write + + + B_0x0 + 180 clock (clk180) + 0x0 + + + B_0x1 + 270 clock (clk270) + 0x1 + + + B_0x2 + 360 clock (clk0) + 0x2 + + + B_0x3 + 450 clock (next clk90) + 0x3 + + + + + DQSDLY + DQS delay +Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the slave DLL and clock tree. +Valid values are: +Note: - After changing this value, an ITM soft reset (bit ITMSRST=1 and bit INIT=1 in DDRPHYC_PIR register) must be issued. + 20 + 3 + read-write + + + B_0x0 + nominal delay - 3 steps + 0x0 + + + B_0x1 + nominal delay - 2 steps + 0x1 + + + B_0x2 + nominal delay - 1 step + 0x2 + + + B_0x3 + nominal delay + 0x3 + + + B_0x4 + nominal delay + 1 step + 0x4 + + + B_0x5 + nominal delay + 2 steps + 0x5 + + + B_0x6 + nominal delay + 3 steps + 0x6 + + + B_0x7 + nominal delay + 4 steps + 0x7 + + + + + DQSNDLY + DQS# delay +Used to adjust the delay of the data strobes relative to the nominal delay that is matched to the delay of the data bit through the slave DLL and clock tree. +Valid values are: +Note: - After changing this value, an ITM soft reset must be issued: bit ITMSRST=1 and bit INIT=1 in DDRPHYC_PIR register. + 23 + 3 + read-write + + + B_0x0 + nominal delay - 3 steps + 0x0 + + + B_0x1 + nominal delay - 2 steps + 0x1 + + + B_0x2 + nominal delay - 1 step + 0x2 + + + B_0x3 + nominal delay + 0x3 + + + B_0x4 + nominal delay + 1 step + 0x4 + + + B_0x5 + nominal delay + 2 steps + 0x5 + + + B_0x6 + nominal delay + 3 steps + 0x6 + + + B_0x7 + nominal delay + 4 steps + 0x7 + + + + + DMDLY + DM delay +Used to adjust the delay of the data relative to the nominal delay that is matched to the delay of the data strobes through the slave DLL and clock tree. +The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by DQS, while the higher two bits control the delay for the data clocked by DQS_b. +Valid settings for each 2-bit control field are: + 26 + 4 + read-write + + + B_0x0 + nominal delay + 0x0 + + + B_0x1 + nominal delay + 1 step + 0x1 + + + B_0x2 + nominal delay + 2 steps + 0x2 + + + B_0x3 + nominal delay + 3 steps + 0x3 + + + + + + + + + DFSDM + DFSDM + DFSDM + 0x4400D000 + + 0x0 + 0x800 + registers + + + + DFSDM_CH0CFGR1 + DFSDM_CH0CFGR1 + DFSDM channel 0 configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SITP + Serial interface type for channel y +This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register). + 0 + 2 + read-write + + + B_0x0 + SPI with rising edge to strobe data + 0x0 + + + B_0x1 + SPI with falling edge to strobe data + 0x1 + + + B_0x2 + Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 + 0x2 + + + B_0x3 + Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 + 0x3 + + + + + SPICKSEL + SPI clock select for channel y +2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). +3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 2 + 2 + read-write + + + B_0x0 + clock coming from external CKINy input - sampling point according SITP[1:0] + 0x0 + + + B_0x1 + clock coming from internal CKOUT output - sampling point according SITP[1:0] + 0x1 + + + + + SCDEN + Short-circuit detector enable on channel y + 5 + 1 + read-write + + + B_0x0 + Input channel y will not be guarded by the short-circuit detector + 0x0 + + + B_0x1 + Input channel y will be continuously guarded by the short-circuit detector + 0x1 + + + + + CKABEN + Clock absence detector enable on channel y + 6 + 1 + read-write + + + B_0x0 + Clock absence detector disabled on channel y + 0x0 + + + B_0x1 + Clock absence detector enabled on channel y + 0x1 + + + + + CHEN + Channel y enable +If channel y is enabled, then serial data receiving is started according to the given channel setting. + 7 + 1 + read-write + + + B_0x0 + Channel y disabled + 0x0 + + + B_0x1 + Channel y enabled + 0x1 + + + + + CHINSEL + Channel inputs selection +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 8 + 1 + read-write + + + B_0x0 + Channel inputs are taken from pins of the same channel y. + 0x0 + + + B_0x1 + Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). + 0x1 + + + + + DATMPX + Input data multiplexer for channel y +2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 12 + 2 + read-write + + + B_0x0 + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. + 0x0 + + + B_0x1 + Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. + 0x1 + + + + + DATPACK + Data packing mode in DFSDM_CHyDATINR register. +first sample in INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y) +To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). +2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: +first sample INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y+1) +To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2), for odd channel numbers (y = 1, 3) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 14 + 2 + read-write + + + B_0x0 + Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. + 0x0 + + + B_0x1 + Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: + 0x1 + + + + + CKOUTDIV + Output serial clock divider + 256 (Divider = CKOUTDIV+1). +CKOUTDIV also defines the threshold for a clock absence detection. +This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). +Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) +1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - + 16 + 8 + read-write + + + B_0x0 + Output clock generation is disabled (CKOUT signal is set to low state) + 0x0 + + + + + CKOUTSRC + Output serial clock source selection +This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0) + 30 + 1 + read-write + + + B_0x0 + Source for output clock is from system clock + 0x0 + + + B_0x1 + Source for output clock is from audio clock + 0x1 + + + + + DFSDMEN + Global enable for DFSDM interface +If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: +all registers DFSDM_FLTxISR are set to reset state (x = 0..1) +all registers DFSDM_FLTxAWSR are set to reset state (x = 0..1) +Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0) + 31 + 1 + read-write + + + B_0x0 + DFSDM interface disabled + 0x0 + + + B_0x1 + DFSDM interface enabled + 0x1 + + + + + + + DFSDM_CH0CFGR2 + DFSDM_CH0CFGR2 + DFSDM channel 0 configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTRBS + Data right bit-shift for channel y +will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right + 3 + 5 + read-write + + + OFFSET + 24-bit calibration offset for channel y +For channel y, OFFSET is applied to the results of each conversion from this channel. +This value is set by software. + 8 + 24 + read-write + + + + + DFSDM_CH0AWSCDR + DFSDM_CH0AWSCDR + DFSDM channel 0 analog watchdog and short-circuit detector register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCDT + short-circuit detector threshold for channel y +These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. + 0 + 8 + read-write + + + BKSCD + Break signal assignment for short-circuit detector on channel y +BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y +BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y + 12 + 4 + read-write + + + AWFOSR + Analog watchdog filter oversampling ratio (decimation rate) on channel y +also the decimation ratio of the analog data rate. +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +Note: If AWFOSR = 0 then the filter has no effect (filter bypass). +0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is + 16 + 5 + read-write + + + AWFORD + Analog watchdog Sinc filter order on channel y +2: Sinc2 filter type +3: Sinc3 filter type +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 22 + 2 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_CH0WDATR + DFSDM_CH0WDATR + DFSDM channel 0 watchdog filter data register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDATA + Input channel y watchdog data +Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). + 0 + 16 + read-only + + + + + DFSDM_CH0DATINR + DFSDM_CH0DATINR + DFSDM channel 0 data input register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INDAT0 + Input data for channel y +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +Channel y data sample is stored into INDAT0[15:0]. +If DATPACK[1:0]=1 (interleaved mode) +First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: Channel y data sample is stored into INDAT0[15:0]. +For odd y channels: INDAT0[15:0] is write protected. +See for more details. +INDAT0[15:0] is in the16-bit signed format. + 0 + 16 + read-write + + + INDAT1 + Input data for channel y or channel y+1 +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +INDAT0[15:0] is write protected (not used for input sample). +If DATPACK[1:0]=1 (interleaved mode) +Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). +For odd y channels: INDAT1[15:0] is write protected. +See for more details. +INDAT0[15:1] is in the16-bit signed format. + 16 + 16 + read-write + + + + + DFSDM_CH0DLYR + DFSDM_CH0DLYR + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH1CFGR1 + DFSDM_CH1CFGR1 + DFSDM channel 1 configuration register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SITP + Serial interface type for channel y +This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register). + 0 + 2 + read-write + + + B_0x0 + SPI with rising edge to strobe data + 0x0 + + + B_0x1 + SPI with falling edge to strobe data + 0x1 + + + B_0x2 + Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 + 0x2 + + + B_0x3 + Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 + 0x3 + + + + + SPICKSEL + SPI clock select for channel y +2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). +3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 2 + 2 + read-write + + + B_0x0 + clock coming from external CKINy input - sampling point according SITP[1:0] + 0x0 + + + B_0x1 + clock coming from internal CKOUT output - sampling point according SITP[1:0] + 0x1 + + + + + SCDEN + Short-circuit detector enable on channel y + 5 + 1 + read-write + + + B_0x0 + Input channel y will not be guarded by the short-circuit detector + 0x0 + + + B_0x1 + Input channel y will be continuously guarded by the short-circuit detector + 0x1 + + + + + CKABEN + Clock absence detector enable on channel y + 6 + 1 + read-write + + + B_0x0 + Clock absence detector disabled on channel y + 0x0 + + + B_0x1 + Clock absence detector enabled on channel y + 0x1 + + + + + CHEN + Channel y enable +If channel y is enabled, then serial data receiving is started according to the given channel setting. + 7 + 1 + read-write + + + B_0x0 + Channel y disabled + 0x0 + + + B_0x1 + Channel y enabled + 0x1 + + + + + CHINSEL + Channel inputs selection +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 8 + 1 + read-write + + + B_0x0 + Channel inputs are taken from pins of the same channel y. + 0x0 + + + B_0x1 + Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). + 0x1 + + + + + DATMPX + Input data multiplexer for channel y +2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 12 + 2 + read-write + + + B_0x0 + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. + 0x0 + + + B_0x1 + Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. + 0x1 + + + + + DATPACK + Data packing mode in DFSDM_CHyDATINR register. +first sample in INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y) +To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). +2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: +first sample INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y+1) +To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2), for odd channel numbers (y = 1, 3) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 14 + 2 + read-write + + + B_0x0 + Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. + 0x0 + + + B_0x1 + Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: + 0x1 + + + + + CKOUTDIV + Output serial clock divider + 256 (Divider = CKOUTDIV+1). +CKOUTDIV also defines the threshold for a clock absence detection. +This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). +Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) +1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - + 16 + 8 + read-write + + + B_0x0 + Output clock generation is disabled (CKOUT signal is set to low state) + 0x0 + + + + + CKOUTSRC + Output serial clock source selection +This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0) + 30 + 1 + read-write + + + B_0x0 + Source for output clock is from system clock + 0x0 + + + B_0x1 + Source for output clock is from audio clock + 0x1 + + + + + DFSDMEN + Global enable for DFSDM interface +If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: +all registers DFSDM_FLTxISR are set to reset state (x = 0..1) +all registers DFSDM_FLTxAWSR are set to reset state (x = 0..1) +Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0) + 31 + 1 + read-write + + + B_0x0 + DFSDM interface disabled + 0x0 + + + B_0x1 + DFSDM interface enabled + 0x1 + + + + + + + DFSDM_CH1CFGR2 + DFSDM_CH1CFGR2 + DFSDM channel 1 configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTRBS + Data right bit-shift for channel y +will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right + 3 + 5 + read-write + + + OFFSET + 24-bit calibration offset for channel y +For channel y, OFFSET is applied to the results of each conversion from this channel. +This value is set by software. + 8 + 24 + read-write + + + + + DFSDM_CH1AWSCDR + DFSDM_CH1AWSCDR + DFSDM channel 1 analog watchdog and short-circuit detector register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCDT + short-circuit detector threshold for channel y +These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. + 0 + 8 + read-write + + + BKSCD + Break signal assignment for short-circuit detector on channel y +BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y +BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y + 12 + 4 + read-write + + + AWFOSR + Analog watchdog filter oversampling ratio (decimation rate) on channel y +also the decimation ratio of the analog data rate. +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +Note: If AWFOSR = 0 then the filter has no effect (filter bypass). +0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is + 16 + 5 + read-write + + + AWFORD + Analog watchdog Sinc filter order on channel y +2: Sinc2 filter type +3: Sinc3 filter type +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 22 + 2 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_CH1WDATR + DFSDM_CH1WDATR + DFSDM channel 1 watchdog filter data register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDATA + Input channel y watchdog data +Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). + 0 + 16 + read-only + + + + + DFSDM_CH1DATINR + DFSDM_CH1DATINR + DFSDM channel 1 data input register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INDAT0 + Input data for channel y +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +Channel y data sample is stored into INDAT0[15:0]. +If DATPACK[1:0]=1 (interleaved mode) +First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: Channel y data sample is stored into INDAT0[15:0]. +For odd y channels: INDAT0[15:0] is write protected. +See for more details. +INDAT0[15:0] is in the16-bit signed format. + 0 + 16 + read-write + + + INDAT1 + Input data for channel y or channel y+1 +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +INDAT0[15:0] is write protected (not used for input sample). +If DATPACK[1:0]=1 (interleaved mode) +Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). +For odd y channels: INDAT1[15:0] is write protected. +See for more details. +INDAT0[15:1] is in the16-bit signed format. + 16 + 16 + read-write + + + + + DFSDM_CH1DLYR + DFSDM_CH1DLYR + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH2CFGR1 + DFSDM_CH2CFGR1 + DFSDM channel 2 configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SITP + Serial interface type for channel y +This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register). + 0 + 2 + read-write + + + B_0x0 + SPI with rising edge to strobe data + 0x0 + + + B_0x1 + SPI with falling edge to strobe data + 0x1 + + + B_0x2 + Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 + 0x2 + + + B_0x3 + Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 + 0x3 + + + + + SPICKSEL + SPI clock select for channel y +2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). +3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 2 + 2 + read-write + + + B_0x0 + clock coming from external CKINy input - sampling point according SITP[1:0] + 0x0 + + + B_0x1 + clock coming from internal CKOUT output - sampling point according SITP[1:0] + 0x1 + + + + + SCDEN + Short-circuit detector enable on channel y + 5 + 1 + read-write + + + B_0x0 + Input channel y will not be guarded by the short-circuit detector + 0x0 + + + B_0x1 + Input channel y will be continuously guarded by the short-circuit detector + 0x1 + + + + + CKABEN + Clock absence detector enable on channel y + 6 + 1 + read-write + + + B_0x0 + Clock absence detector disabled on channel y + 0x0 + + + B_0x1 + Clock absence detector enabled on channel y + 0x1 + + + + + CHEN + Channel y enable +If channel y is enabled, then serial data receiving is started according to the given channel setting. + 7 + 1 + read-write + + + B_0x0 + Channel y disabled + 0x0 + + + B_0x1 + Channel y enabled + 0x1 + + + + + CHINSEL + Channel inputs selection +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 8 + 1 + read-write + + + B_0x0 + Channel inputs are taken from pins of the same channel y. + 0x0 + + + B_0x1 + Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). + 0x1 + + + + + DATMPX + Input data multiplexer for channel y +2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 12 + 2 + read-write + + + B_0x0 + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. + 0x0 + + + B_0x1 + Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. + 0x1 + + + + + DATPACK + Data packing mode in DFSDM_CHyDATINR register. +first sample in INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y) +To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). +2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: +first sample INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y+1) +To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2), for odd channel numbers (y = 1, 3) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 14 + 2 + read-write + + + B_0x0 + Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. + 0x0 + + + B_0x1 + Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: + 0x1 + + + + + CKOUTDIV + Output serial clock divider + 256 (Divider = CKOUTDIV+1). +CKOUTDIV also defines the threshold for a clock absence detection. +This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). +Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) +1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - + 16 + 8 + read-write + + + B_0x0 + Output clock generation is disabled (CKOUT signal is set to low state) + 0x0 + + + + + CKOUTSRC + Output serial clock source selection +This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0) + 30 + 1 + read-write + + + B_0x0 + Source for output clock is from system clock + 0x0 + + + B_0x1 + Source for output clock is from audio clock + 0x1 + + + + + DFSDMEN + Global enable for DFSDM interface +If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: +all registers DFSDM_FLTxISR are set to reset state (x = 0..1) +all registers DFSDM_FLTxAWSR are set to reset state (x = 0..1) +Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0) + 31 + 1 + read-write + + + B_0x0 + DFSDM interface disabled + 0x0 + + + B_0x1 + DFSDM interface enabled + 0x1 + + + + + + + DFSDM_CH2CFGR2 + DFSDM_CH2CFGR2 + DFSDM channel 2 configuration register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTRBS + Data right bit-shift for channel y +will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right + 3 + 5 + read-write + + + OFFSET + 24-bit calibration offset for channel y +For channel y, OFFSET is applied to the results of each conversion from this channel. +This value is set by software. + 8 + 24 + read-write + + + + + DFSDM_CH2AWSCDR + DFSDM_CH2AWSCDR + DFSDM channel 2 analog watchdog and short-circuit detector register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCDT + short-circuit detector threshold for channel y +These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. + 0 + 8 + read-write + + + BKSCD + Break signal assignment for short-circuit detector on channel y +BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y +BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y + 12 + 4 + read-write + + + AWFOSR + Analog watchdog filter oversampling ratio (decimation rate) on channel y +also the decimation ratio of the analog data rate. +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +Note: If AWFOSR = 0 then the filter has no effect (filter bypass). +0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is + 16 + 5 + read-write + + + AWFORD + Analog watchdog Sinc filter order on channel y +2: Sinc2 filter type +3: Sinc3 filter type +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 22 + 2 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_CH2WDATR + DFSDM_CH2WDATR + DFSDM channel 2 watchdog filter data register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDATA + Input channel y watchdog data +Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). + 0 + 16 + read-only + + + + + DFSDM_CH2DATINR + DFSDM_CH2DATINR + DFSDM channel 2 data input register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INDAT0 + Input data for channel y +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +Channel y data sample is stored into INDAT0[15:0]. +If DATPACK[1:0]=1 (interleaved mode) +First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: Channel y data sample is stored into INDAT0[15:0]. +For odd y channels: INDAT0[15:0] is write protected. +See for more details. +INDAT0[15:0] is in the16-bit signed format. + 0 + 16 + read-write + + + INDAT1 + Input data for channel y or channel y+1 +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +INDAT0[15:0] is write protected (not used for input sample). +If DATPACK[1:0]=1 (interleaved mode) +Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). +For odd y channels: INDAT1[15:0] is write protected. +See for more details. +INDAT0[15:1] is in the16-bit signed format. + 16 + 16 + read-write + + + + + DFSDM_CH2DLYR + DFSDM_CH2DLYR + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH3CFGR1 + DFSDM_CH3CFGR1 + DFSDM channel 3 configuration register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SITP + Serial interface type for channel y +This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register). + 0 + 2 + read-write + + + B_0x0 + SPI with rising edge to strobe data + 0x0 + + + B_0x1 + SPI with falling edge to strobe data + 0x1 + + + B_0x2 + Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 + 0x2 + + + B_0x3 + Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 + 0x3 + + + + + SPICKSEL + SPI clock select for channel y +2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). +3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. +For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 2 + 2 + read-write + + + B_0x0 + clock coming from external CKINy input - sampling point according SITP[1:0] + 0x0 + + + B_0x1 + clock coming from internal CKOUT output - sampling point according SITP[1:0] + 0x1 + + + + + SCDEN + Short-circuit detector enable on channel y + 5 + 1 + read-write + + + B_0x0 + Input channel y will not be guarded by the short-circuit detector + 0x0 + + + B_0x1 + Input channel y will be continuously guarded by the short-circuit detector + 0x1 + + + + + CKABEN + Clock absence detector enable on channel y + 6 + 1 + read-write + + + B_0x0 + Clock absence detector disabled on channel y + 0x0 + + + B_0x1 + Clock absence detector enabled on channel y + 0x1 + + + + + CHEN + Channel y enable +If channel y is enabled, then serial data receiving is started according to the given channel setting. + 7 + 1 + read-write + + + B_0x0 + Channel y disabled + 0x0 + + + B_0x1 + Channel y enabled + 0x1 + + + + + CHINSEL + Channel inputs selection +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 8 + 1 + read-write + + + B_0x0 + Channel inputs are taken from pins of the same channel y. + 0x0 + + + B_0x1 + Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). + 0x1 + + + + + DATMPX + Input data multiplexer for channel y +2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 12 + 2 + read-write + + + B_0x0 + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. + 0x0 + + + B_0x1 + Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. + 0x1 + + + + + DATPACK + Data packing mode in DFSDM_CHyDATINR register. +first sample in INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y) +To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). +2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: +first sample INDAT0[15:0] (assigned to channel y) +second sample INDAT1[15:0] (assigned to channel y+1) +To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2), for odd channel numbers (y = 1, 3) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. +3: Reserved +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 14 + 2 + read-write + + + B_0x0 + Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. + 0x0 + + + B_0x1 + Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: + 0x1 + + + + + CKOUTDIV + Output serial clock divider + 256 (Divider = CKOUTDIV+1). +CKOUTDIV also defines the threshold for a clock absence detection. +This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). +Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) +1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - + 16 + 8 + read-write + + + B_0x0 + Output clock generation is disabled (CKOUT signal is set to low state) + 0x0 + + + + + CKOUTSRC + Output serial clock source selection +This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). +Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0) + 30 + 1 + read-write + + + B_0x0 + Source for output clock is from system clock + 0x0 + + + B_0x1 + Source for output clock is from audio clock + 0x1 + + + + + DFSDMEN + Global enable for DFSDM interface +If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: +all registers DFSDM_FLTxISR are set to reset state (x = 0..1) +all registers DFSDM_FLTxAWSR are set to reset state (x = 0..1) +Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0) + 31 + 1 + read-write + + + B_0x0 + DFSDM interface disabled + 0x0 + + + B_0x1 + DFSDM interface enabled + 0x1 + + + + + + + DFSDM_CH3CFGR2 + DFSDM_CH3CFGR2 + DFSDM channel 3 configuration register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTRBS + Data right bit-shift for channel y +will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). +This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right + 3 + 5 + read-write + + + OFFSET + 24-bit calibration offset for channel y +For channel y, OFFSET is applied to the results of each conversion from this channel. +This value is set by software. + 8 + 24 + read-write + + + + + DFSDM_CH3AWSCDR + DFSDM_CH3AWSCDR + DFSDM channel 3 analog watchdog and short-circuit detector register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCDT + short-circuit detector threshold for channel y +These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. + 0 + 8 + read-write + + + BKSCD + Break signal assignment for short-circuit detector on channel y +BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y +BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y + 12 + 4 + read-write + + + AWFOSR + Analog watchdog filter oversampling ratio (decimation rate) on channel y +also the decimation ratio of the analog data rate. +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). +Note: If AWFOSR = 0 then the filter has no effect (filter bypass). +0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is + 16 + 5 + read-write + + + AWFORD + Analog watchdog Sinc filter order on channel y +2: Sinc2 filter type +3: Sinc3 filter type +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). + 22 + 2 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_CH3WDATR + DFSDM_CH3WDATR + DFSDM channel 3 watchdog filter data register + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WDATA + Input channel y watchdog data +Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). + 0 + 16 + read-only + + + + + DFSDM_CH3DATINR + DFSDM_CH3DATINR + DFSDM channel 3 data input register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INDAT0 + Input data for channel y +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +Channel y data sample is stored into INDAT0[15:0]. +If DATPACK[1:0]=1 (interleaved mode) +First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: Channel y data sample is stored into INDAT0[15:0]. +For odd y channels: INDAT0[15:0] is write protected. +See for more details. +INDAT0[15:0] is in the16-bit signed format. + 0 + 16 + read-write + + + INDAT1 + Input data for channel y or channel y+1 +Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. +Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). +If DATPACK[1:0]=0 (standard mode) +INDAT0[15:0] is write protected (not used for input sample). +If DATPACK[1:0]=1 (interleaved mode) +Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. +If DATPACK[1:0]=2 (dual mode). +For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). +For odd y channels: INDAT1[15:0] is write protected. +See for more details. +INDAT0[15:1] is in the16-bit signed format. + 16 + 16 + read-write + + + + + DFSDM_CH3DLYR + DFSDM_CH3DLYR + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH4DLYR + DFSDM_CH4DLYR + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH5DLYR + DFSDM_CH5DLYR + 0xb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH6DLYR + DFSDM_CH6DLYR + 0xd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_CH7DLYR + DFSDM_CH7DLYR + 0xf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PLSSKP + Pulses to skip for input data skipping function +immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. +Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. +0-63: Defines the number of serial input samples that will be skipped. Skipping is applied + 0 + 6 + read-write + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFEN + DFSDM_FLTx enable +Data which are cleared by setting DFEN=0: +register DFSDM_FLTxISR is set to the reset state +register DFSDM_FLTxAWSR is set to the reset state + 0 + 1 + read-write + + + B_0x0 + DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. + 0x0 + + + B_0x1 + DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. + 0x1 + + + + + JSWSTART + Start a conversion of the injected group of channels +This bit is always read as '0’. + 1 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect. + 0x0 + + + B_0x1 + Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1. + 0x1 + + + + + JSYNC + Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 3 + 1 + read-write + + + B_0x0 + Do not launch an injected conversion synchronously with DFSDM_FLT0 + 0x0 + + + B_0x1 + Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger + 0x1 + + + + + JSCAN + Scanning conversion mode for injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel. + 4 + 1 + read-write + + + B_0x0 + One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. + 0x0 + + + B_0x1 + The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. + 0x1 + + + + + JDMAEN + DMA channel enabled to read data for the injected channel group +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 5 + 1 + read-write + + + B_0x0 + The DMA channel is not enabled to read injected data + 0x0 + + + B_0x1 + The DMA channel is enabled to read injected data + 0x1 + + + + + JEXTSEL + Trigger signal selection for launching injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). +DFSDM_FLTx +0x00 dfsdm_jtrg0 +0x01 dfsdm_jtrg1 +... +0x1E dfsdm_jtrg30 +0x1F dfsdm_jtrg31 +Refer to . +0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). + 8 + 5 + read-write + + + JEXTEN + Trigger enable and trigger edge selection for injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 13 + 2 + read-write + + + B_0x0 + Trigger detection is disabled + 0x0 + + + B_0x1 + Each rising edge on the selected trigger makes a request to launch an injected conversion + 0x1 + + + B_0x2 + Each falling edge on the selected trigger makes a request to launch an injected conversion + 0x2 + + + B_0x3 + Both rising edges and falling edges on the selected trigger make requests to launch injected conversions + 0x3 + + + + + RSWSTART + Software start of a conversion on the regular channel +This bit is always read as '0’. + 17 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1. + 0x1 + + + + + RCONT + Continuous mode selection for regular conversions +Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately. + 18 + 1 + read-write + + + B_0x0 + The regular channel is converted just once for each conversion request + 0x0 + + + B_0x1 + The regular channel is converted repeatedly after each conversion request + 0x1 + + + + + RSYNC + Launch regular conversion synchronously with DFSDM_FLT0 +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 19 + 1 + read-write + + + B_0x0 + Do not launch a regular conversion synchronously with DFSDM_FLT0 + 0x0 + + + B_0x1 + Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 + 0x1 + + + + + RDMAEN + DMA channel enabled to read data for the regular conversion +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 21 + 1 + read-write + + + B_0x0 + The DMA channel is not enabled to read regular data + 0x0 + + + B_0x1 + The DMA channel is enabled to read regular data + 0x1 + + + + + RCH + Regular channel selection +... +3: Chanel 3 is selected as the regular channel +Writing this bit when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion). + 24 + 2 + read-write + + + B_0x0 + Channel 0 is selected as the regular channel + 0x0 + + + B_0x1 + Channel 1 is selected as the regular channel + 0x1 + + + + + FAST + Fast conversion mode selection for regular conversions +When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +if FAST=0 (or first conversion in continuous mode if FAST=1): +t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters +t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter +if FAST=1 in continuous mode (except first conversion): +t = [FOSR * IOSR] / fCKIN +in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): +t = IOSR / fCKIN (... but CNVCNT=0) +where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input. + 29 + 1 + read-write + + + B_0x0 + Fast conversion mode disabled + 0x0 + + + B_0x1 + Fast conversion mode enabled + 0x1 + + + + + AWFSEL + Analog watchdog fast mode select + 30 + 1 + read-write + + + B_0x0 + Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift + 0x0 + + + B_0x1 + Analog watchdog on channel transceivers value (after watchdog filter) + 0x1 + + + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JEOCIE + Injected end of conversion interrupt enable +Please see the explanation of JEOCF in DFSDM_FLTxISR. + 0 + 1 + read-write + + + B_0x0 + Injected end of conversion interrupt is disabled + 0x0 + + + B_0x1 + Injected end of conversion interrupt is enabled + 0x1 + + + + + REOCIE + Regular end of conversion interrupt enable +Please see the explanation of REOCF in DFSDM_FLTxISR. + 1 + 1 + read-write + + + B_0x0 + Regular end of conversion interrupt is disabled + 0x0 + + + B_0x1 + Regular end of conversion interrupt is enabled + 0x1 + + + + + JOVRIE + Injected data overrun interrupt enable +Please see the explanation of JOVRF in DFSDM_FLTxISR. + 2 + 1 + read-write + + + B_0x0 + Injected data overrun interrupt is disabled + 0x0 + + + B_0x1 + Injected data overrun interrupt is enabled + 0x1 + + + + + ROVRIE + Regular data overrun interrupt enable +Please see the explanation of ROVRF in DFSDM_FLTxISR. + 3 + 1 + read-write + + + B_0x0 + Regular data overrun interrupt is disabled + 0x0 + + + B_0x1 + Regular data overrun interrupt is enabled + 0x1 + + + + + AWDIE + Analog watchdog interrupt enable +Please see the explanation of AWDF in DFSDM_FLTxISR. + 4 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt is disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt is enabled + 0x1 + + + + + SCDIE + Short-circuit detector interrupt enable +Please see the explanation of SCDF[3:0] in DFSDM_FLTxISR. +Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0) + 5 + 1 + read-write + + + B_0x0 + short-circuit detector interrupt is disabled + 0x0 + + + B_0x1 + short-circuit detector interrupt is enabled + 0x1 + + + + + CKABIE + Clock absence interrupt enable +Please see the explanation of CKABF[3:0] in DFSDM_FLTxISR. +Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0) + 6 + 1 + read-write + + + B_0x0 + Detection of channel input clock absence interrupt is disabled + 0x0 + + + B_0x1 + Detection of channel input clock absence interrupt is enabled + 0x1 + + + + + EXCH + Extremes detector channel selection +These bits select the input channels to be taken by the Extremes detector. +EXCH[y] = 0: Extremes detector does not accept data from channel y +EXCH[y] = 1: Extremes detector accepts data from channel y + 8 + 4 + read-write + + + AWDCH + Analog watchdog channel selection +These bits select the input channel to be guarded continuously by the analog watchdog. +AWDCH[y] = 0: Analog watchdog is disabled on channel y +AWDCH[y] = 1: Analog watchdog is enabled on channel y + 16 + 4 + read-write + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + 0x108 + 0x20 + 0x00FF0000 + 0xFFFFFFFF + + + JEOCF + End of injected conversion flag +This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR. + 0 + 1 + read-only + + + B_0x0 + No injected conversion has completed + 0x0 + + + B_0x1 + An injected conversion has completed and its data may be read + 0x1 + + + + + REOCF + End of regular conversion flag +This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR. + 1 + 1 + read-only + + + B_0x0 + No regular conversion has completed + 0x0 + + + B_0x1 + A regular conversion has completed and its data may be read + 0x1 + + + + + JOVRF + Injected conversion overrun flag +This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register. + 2 + 1 + read-only + + + B_0x0 + No injected conversion overrun has occurred + 0x0 + + + B_0x1 + An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns + 0x1 + + + + + ROVRF + Regular conversion overrun flag +This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register. + 3 + 1 + read-only + + + B_0x0 + No regular conversion overrun has occurred + 0x0 + + + B_0x1 + A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns + 0x1 + + + + + AWDF + Analog watchdog +This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[3:0] and AWLTF[3:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register). + 4 + 1 + read-only + + + B_0x0 + No Analog watchdog event occurred + 0x0 + + + B_0x1 + The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. + 0x1 + + + + + JCIP + Injected conversion in progress status +A request to start an injected conversion is ignored when JCIP=1. + 13 + 1 + read-only + + + B_0x0 + No request to convert the injected channel group (neither by software nor by trigger) has been issued + 0x0 + + + B_0x1 + The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection + 0x1 + + + + + RCIP + Regular conversion in progress status +A request to start a regular conversion is ignored when RCIP=1. + 14 + 1 + read-only + + + B_0x0 + No request to convert the regular channel has been issued + 0x0 + + + B_0x1 + The conversion of the regular channel is in progress or a request for a regular conversion is pending + 0x1 + + + + + CKABF + Clock absence flag +CKABF[y]=0: Clock signal on channel y is present. +CKABF[y]=1: Clock signal on channel y is not present. +Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. +Note: CKABF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0) + 16 + 4 + read-only + + + SCDF + short-circuit detector flag +SDCF[y]=0: No short-circuit detector event occurred on channel y +SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers +This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). +Note: SCDF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0) + 24 + 4 + read-only + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLRJOVRF + Clear the injected conversion overrun flag + 2 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register + 0x1 + + + + + CLRROVRF + Clear the regular conversion overrun flag + 3 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register + 0x1 + + + + + CLRCKABF + Clear the clock absence flag +CLRCKABF[y]=0: Writing '0’ has no effect +CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. +Note: CLRCKABF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0) + 16 + 4 + read-write + + + CLRSCDF + Clear the short-circuit detector flag +CLRSCDF[y]=0: Writing '0’ has no effect +CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register +Note: CLRSCDF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0) + 24 + 4 + read-write + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + 0x110 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + JCHG + Injected channel group selection +JCHG[y]=0: channel y is not part of the injected group +JCHG[y]=1: channel y is part of the injected group +If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. +If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. +At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored. + 0 + 4 + read-write + + + + + DFSDM_FLT0FCR + DFSDM_FLT0FCR + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IOSR + Integrator oversampling ratio (averaging length) +from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) +Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). +0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples + 0 + 8 + read-write + + + FOSR + Sinc filter oversampling ratio (decimation rate) +number is also the decimation ratio of the output data rate from filter. +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) +Note: If FOSR = 0, then the filter has no effect (filter bypass). +0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This + 16 + 10 + read-write + + + FORD + Sinc filter order +2: Sinc2 filter type +3: Sinc3 filter type +4: Sinc4 filter type +5: Sinc5 filter type +6-7: Reserved +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1). + 29 + 3 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATACH + Injected channel most recently converted +When each conversion of a channel in the injected group finishes, JDATACH[1:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[1:0]. + 0 + 2 + read-only + + + JDATA + Injected group conversion data +When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. + 8 + 24 + read-only + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + 0x11c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDATACH + Regular channel most recently converted +When each regular conversion finishes, RDATACH[1:0] is updated to indicate which channel was converted (because regular channel selection RCH[1:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[1:0]. + 0 + 2 + read-only + + + RPEND + Regular channel pending data +Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion + 4 + 1 + read-only + + + RDATA + Regular channel conversion data +When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF. + 8 + 24 + read-only + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKAWH + Break signal assignment to analog watchdog high threshold event +BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event +BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event + 0 + 4 + read-write + + + AWHT + Analog watchdog high threshold +These bits are written by software to define the high threshold for the analog watchdog. +Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case. + 8 + 24 + read-write + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + 0x124 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKAWL + Break signal assignment to analog watchdog low threshold event +BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event +BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event + 0 + 4 + read-write + + + AWLT + Analog watchdog low threshold +These bits are written by software to define the low threshold for the analog watchdog. +Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case. + 8 + 24 + read-write + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + 0x128 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWLTF + Analog watchdog low threshold flag +AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register. + 0 + 4 + read-only + + + AWHTF + Analog watchdog high threshold flag +AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register. + 8 + 4 + read-only + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + 0x12c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLRAWLTF + Clear the analog watchdog low threshold flag +CLRAWLTF[y]=0: Writing '0’ has no effect +CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register + 0 + 4 + read-write + + + CLRAWHTF + Clear the analog watchdog high threshold flag +CLRAWHTF[y]=0: Writing '0’ has no effect +CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register + 8 + 4 + read-write + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + 0x130 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + EXMAXCH + Extremes detector maximum data channel. +These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register. + 0 + 2 + read-only + + + EXMAX + Extremes detector maximum value +These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register. + 8 + 24 + read-only + set + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + 0x134 + 0x20 + 0x7FFFFF00 + 0xFFFFFFFF + + + EXMINCH + Extremes detector minimum data channel +These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register. + 0 + 2 + read-only + + + EXMIN + Extremes detector minimum value +These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. + 8 + 24 + read-write + clear + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + 0x138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNVCNT + 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK +The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: +if FAST=0 (or first conversion in continuous mode if FAST=1): +t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters +t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter +if FAST=1 in continuous mode (except first conversion): +t = [FOSR * IOSR] / fCKIN +in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): +CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) +where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) +Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time. + 4 + 28 + read-only + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + 0x180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DFEN + DFSDM_FLTx enable +Data which are cleared by setting DFEN=0: +register DFSDM_FLTxISR is set to the reset state +register DFSDM_FLTxAWSR is set to the reset state + 0 + 1 + read-write + + + B_0x0 + DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. + 0x0 + + + B_0x1 + DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. + 0x1 + + + + + JSWSTART + Start a conversion of the injected group of channels +This bit is always read as '0’. + 1 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect. + 0x0 + + + B_0x1 + Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1. + 0x1 + + + + + JSYNC + Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 3 + 1 + read-write + + + B_0x0 + Do not launch an injected conversion synchronously with DFSDM_FLT0 + 0x0 + + + B_0x1 + Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger + 0x1 + + + + + JSCAN + Scanning conversion mode for injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel. + 4 + 1 + read-write + + + B_0x0 + One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. + 0x0 + + + B_0x1 + The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. + 0x1 + + + + + JDMAEN + DMA channel enabled to read data for the injected channel group +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 5 + 1 + read-write + + + B_0x0 + The DMA channel is not enabled to read injected data + 0x0 + + + B_0x1 + The DMA channel is enabled to read injected data + 0x1 + + + + + JEXTSEL + Trigger signal selection for launching injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). +DFSDM_FLTx +0x00 dfsdm_jtrg0 +0x01 dfsdm_jtrg1 +... +0x1E dfsdm_jtrg30 +0x1F dfsdm_jtrg31 +Refer to . +0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). + 8 + 5 + read-write + + + JEXTEN + Trigger enable and trigger edge selection for injected conversions +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 13 + 2 + read-write + + + B_0x0 + Trigger detection is disabled + 0x0 + + + B_0x1 + Each rising edge on the selected trigger makes a request to launch an injected conversion + 0x1 + + + B_0x2 + Each falling edge on the selected trigger makes a request to launch an injected conversion + 0x2 + + + B_0x3 + Both rising edges and falling edges on the selected trigger make requests to launch injected conversions + 0x3 + + + + + RSWSTART + Software start of a conversion on the regular channel +This bit is always read as '0’. + 17 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1. + 0x1 + + + + + RCONT + Continuous mode selection for regular conversions +Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately. + 18 + 1 + read-write + + + B_0x0 + The regular channel is converted just once for each conversion request + 0x0 + + + B_0x1 + The regular channel is converted repeatedly after each conversion request + 0x1 + + + + + RSYNC + Launch regular conversion synchronously with DFSDM_FLT0 +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 19 + 1 + read-write + + + B_0x0 + Do not launch a regular conversion synchronously with DFSDM_FLT0 + 0x0 + + + B_0x1 + Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 + 0x1 + + + + + RDMAEN + DMA channel enabled to read data for the regular conversion +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). + 21 + 1 + read-write + + + B_0x0 + The DMA channel is not enabled to read regular data + 0x0 + + + B_0x1 + The DMA channel is enabled to read regular data + 0x1 + + + + + RCH + Regular channel selection +... +3: Chanel 3 is selected as the regular channel +Writing this bit when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion). + 24 + 2 + read-write + + + B_0x0 + Channel 0 is selected as the regular channel + 0x0 + + + B_0x1 + Channel 1 is selected as the regular channel + 0x1 + + + + + FAST + Fast conversion mode selection for regular conversions +When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. +This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). +if FAST=0 (or first conversion in continuous mode if FAST=1): +t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters +t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter +if FAST=1 in continuous mode (except first conversion): +t = [FOSR * IOSR] / fCKIN +in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): +t = IOSR / fCKIN (... but CNVCNT=0) +where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input. + 29 + 1 + read-write + + + B_0x0 + Fast conversion mode disabled + 0x0 + + + B_0x1 + Fast conversion mode enabled + 0x1 + + + + + AWFSEL + Analog watchdog fast mode select + 30 + 1 + read-write + + + B_0x0 + Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift + 0x0 + + + B_0x1 + Analog watchdog on channel transceivers value (after watchdog filter) + 0x1 + + + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + 0x184 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JEOCIE + Injected end of conversion interrupt enable +Please see the explanation of JEOCF in DFSDM_FLTxISR. + 0 + 1 + read-write + + + B_0x0 + Injected end of conversion interrupt is disabled + 0x0 + + + B_0x1 + Injected end of conversion interrupt is enabled + 0x1 + + + + + REOCIE + Regular end of conversion interrupt enable +Please see the explanation of REOCF in DFSDM_FLTxISR. + 1 + 1 + read-write + + + B_0x0 + Regular end of conversion interrupt is disabled + 0x0 + + + B_0x1 + Regular end of conversion interrupt is enabled + 0x1 + + + + + JOVRIE + Injected data overrun interrupt enable +Please see the explanation of JOVRF in DFSDM_FLTxISR. + 2 + 1 + read-write + + + B_0x0 + Injected data overrun interrupt is disabled + 0x0 + + + B_0x1 + Injected data overrun interrupt is enabled + 0x1 + + + + + ROVRIE + Regular data overrun interrupt enable +Please see the explanation of ROVRF in DFSDM_FLTxISR. + 3 + 1 + read-write + + + B_0x0 + Regular data overrun interrupt is disabled + 0x0 + + + B_0x1 + Regular data overrun interrupt is enabled + 0x1 + + + + + AWDIE + Analog watchdog interrupt enable +Please see the explanation of AWDF in DFSDM_FLTxISR. + 4 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt is disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt is enabled + 0x1 + + + + + SCDIE + Short-circuit detector interrupt enable +Please see the explanation of SCDF[3:0] in DFSDM_FLTxISR. +Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0) + 5 + 1 + read-write + + + B_0x0 + short-circuit detector interrupt is disabled + 0x0 + + + B_0x1 + short-circuit detector interrupt is enabled + 0x1 + + + + + CKABIE + Clock absence interrupt enable +Please see the explanation of CKABF[3:0] in DFSDM_FLTxISR. +Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0) + 6 + 1 + read-write + + + B_0x0 + Detection of channel input clock absence interrupt is disabled + 0x0 + + + B_0x1 + Detection of channel input clock absence interrupt is enabled + 0x1 + + + + + EXCH + Extremes detector channel selection +These bits select the input channels to be taken by the Extremes detector. +EXCH[y] = 0: Extremes detector does not accept data from channel y +EXCH[y] = 1: Extremes detector accepts data from channel y + 8 + 4 + read-write + + + AWDCH + Analog watchdog channel selection +These bits select the input channel to be guarded continuously by the analog watchdog. +AWDCH[y] = 0: Analog watchdog is disabled on channel y +AWDCH[y] = 1: Analog watchdog is enabled on channel y + 16 + 4 + read-write + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + 0x188 + 0x20 + 0x00FF0000 + 0xFFFFFFFF + + + JEOCF + End of injected conversion flag +This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR. + 0 + 1 + read-only + + + B_0x0 + No injected conversion has completed + 0x0 + + + B_0x1 + An injected conversion has completed and its data may be read + 0x1 + + + + + REOCF + End of regular conversion flag +This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR. + 1 + 1 + read-only + + + B_0x0 + No regular conversion has completed + 0x0 + + + B_0x1 + A regular conversion has completed and its data may be read + 0x1 + + + + + JOVRF + Injected conversion overrun flag +This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register. + 2 + 1 + read-only + + + B_0x0 + No injected conversion overrun has occurred + 0x0 + + + B_0x1 + An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns + 0x1 + + + + + ROVRF + Regular conversion overrun flag +This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register. + 3 + 1 + read-only + + + B_0x0 + No regular conversion overrun has occurred + 0x0 + + + B_0x1 + A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns + 0x1 + + + + + AWDF + Analog watchdog +This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[3:0] and AWLTF[3:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register). + 4 + 1 + read-only + + + B_0x0 + No Analog watchdog event occurred + 0x0 + + + B_0x1 + The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. + 0x1 + + + + + JCIP + Injected conversion in progress status +A request to start an injected conversion is ignored when JCIP=1. + 13 + 1 + read-only + + + B_0x0 + No request to convert the injected channel group (neither by software nor by trigger) has been issued + 0x0 + + + B_0x1 + The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection + 0x1 + + + + + RCIP + Regular conversion in progress status +A request to start a regular conversion is ignored when RCIP=1. + 14 + 1 + read-only + + + B_0x0 + No request to convert the regular channel has been issued + 0x0 + + + B_0x1 + The conversion of the regular channel is in progress or a request for a regular conversion is pending + 0x1 + + + + + CKABF + Clock absence flag +CKABF[y]=0: Clock signal on channel y is present. +CKABF[y]=1: Clock signal on channel y is not present. +Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. +Note: CKABF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0) + 16 + 4 + read-only + + + SCDF + short-circuit detector flag +SDCF[y]=0: No short-circuit detector event occurred on channel y +SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers +This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). +Note: SCDF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0) + 24 + 4 + read-only + + + + + DFSDM_FLT1ICR + DFSDM_FLT1ICR + 0x18c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLRJOVRF + Clear the injected conversion overrun flag + 2 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register + 0x1 + + + + + CLRROVRF + Clear the regular conversion overrun flag + 3 + 1 + read-write + + + B_0x0 + Writing '0’ has no effect + 0x0 + + + B_0x1 + Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register + 0x1 + + + + + CLRCKABF + Clear the clock absence flag +CLRCKABF[y]=0: Writing '0’ has no effect +CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. +Note: CLRCKABF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0) + 16 + 4 + read-write + + + CLRSCDF + Clear the short-circuit detector flag +CLRSCDF[y]=0: Writing '0’ has no effect +CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register +Note: CLRSCDF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0) + 24 + 4 + read-write + + + + + DFSDM_FLT1JCHGR + DFSDM_FLT1JCHGR + 0x190 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + JCHG + Injected channel group selection +JCHG[y]=0: channel y is not part of the injected group +JCHG[y]=1: channel y is part of the injected group +If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. +If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. +At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored. + 0 + 4 + read-write + + + + + DFSDM_FLT1FCR + DFSDM_FLT1FCR + 0x194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IOSR + Integrator oversampling ratio (averaging length) +from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) +Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). +0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples + 0 + 8 + read-write + + + FOSR + Sinc filter oversampling ratio (decimation rate) +number is also the decimation ratio of the output data rate from filter. +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) +Note: If FOSR = 0, then the filter has no effect (filter bypass). +0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This + 16 + 10 + read-write + + + FORD + Sinc filter order +2: Sinc2 filter type +3: Sinc3 filter type +4: Sinc4 filter type +5: Sinc5 filter type +6-7: Reserved +Sincx filter type transfer function: +FastSinc filter type transfer function: +This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1). + 29 + 3 + read-write + + + B_0x0 + FastSinc filter type + 0x0 + + + B_0x1 + Sinc1 filter type + 0x1 + + + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + 0x198 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JDATACH + Injected channel most recently converted +When each conversion of a channel in the injected group finishes, JDATACH[1:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[1:0]. + 0 + 2 + read-only + + + JDATA + Injected group conversion data +When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. + 8 + 24 + read-only + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + 0x19c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDATACH + Regular channel most recently converted +When each regular conversion finishes, RDATACH[1:0] is updated to indicate which channel was converted (because regular channel selection RCH[1:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[1:0]. + 0 + 2 + read-only + + + RPEND + Regular channel pending data +Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion + 4 + 1 + read-only + + + RDATA + Regular channel conversion data +When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF. + 8 + 24 + read-only + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + 0x1a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKAWH + Break signal assignment to analog watchdog high threshold event +BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event +BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event + 0 + 4 + read-write + + + AWHT + Analog watchdog high threshold +These bits are written by software to define the high threshold for the analog watchdog. +Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case. + 8 + 24 + read-write + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + 0x1a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKAWL + Break signal assignment to analog watchdog low threshold event +BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event +BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event + 0 + 4 + read-write + + + AWLT + Analog watchdog low threshold +These bits are written by software to define the low threshold for the analog watchdog. +Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case. + 8 + 24 + read-write + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + 0x1a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWLTF + Analog watchdog low threshold flag +AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register. + 0 + 4 + read-only + + + AWHTF + Analog watchdog high threshold flag +AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register. + 8 + 4 + read-only + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + 0x1ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLRAWLTF + Clear the analog watchdog low threshold flag +CLRAWLTF[y]=0: Writing '0’ has no effect +CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register + 0 + 4 + read-write + + + CLRAWHTF + Clear the analog watchdog high threshold flag +CLRAWHTF[y]=0: Writing '0’ has no effect +CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register + 8 + 4 + read-write + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + 0x1b0 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + EXMAXCH + Extremes detector maximum data channel. +These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register. + 0 + 2 + read-only + + + EXMAX + Extremes detector maximum value +These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register. + 8 + 24 + read-only + set + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + 0x1b4 + 0x20 + 0x7FFFFF00 + 0xFFFFFFFF + + + EXMINCH + Extremes detector minimum data channel +These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register. + 0 + 2 + read-only + + + EXMIN + Extremes detector minimum value +These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. + 8 + 24 + read-write + clear + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + 0x1b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNVCNT + 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK +The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: +if FAST=0 (or first conversion in continuous mode if FAST=1): +t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters +t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter +if FAST=1 in continuous mode (except first conversion): +t = [FOSR * IOSR] / fCKIN +in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): +CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) +where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) +Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time. + 4 + 28 + read-only + + + + + DFSDM_HWCFGR + DFSDM_HWCFGR + DFSDM hardware configuration register + 0x7f0 + 0x20 + 0x00000204 + 0xFFFFFFFF + + + NBT + Number of implemented transceivers +Defines how many transceivers (input channels) are implemented in DFSDM peripheral. + 0 + 8 + read-only + + + NBF + Number of implemented filters +Defines how many filters are implemented in DFSDM peripheral. + 8 + 8 + read-only + + + + + DFSDM_VERR + DFSDM_VERR + DFSDM version register + 0x7f4 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + MINREV + Minor revision of the DFSDM peripheral +These bits return the DFSDM minor revision (in range 0..15). + 0 + 4 + read-only + + + MAJREV + Major revision of the DFSDM peripheral +These bits return the DFSDM major revision (in range 0..15). + 4 + 4 + read-only + + + + + DFSDM_IPIDR + DFSDM_IPIDR + DFSDM identification register + 0x7f8 + 0x20 + 0x00110031 + 0xFFFFFFFF + + + ID + Peripheral identifier +Bits [31:0]: these bits returns the DFSDM identifier ID[31:0] = 0x0011 0031 + 0 + 32 + read-only + + + + + DFSDM_SIDR + DFSDM_SIDR + DFSDM size identification register + 0x7fc + 0x20 + 0xA3C5DD02 + 0xFFFFFFFF + + + SID + Size identification of DFSDM peripheral +Bits [31:8]: fixed code = 0xA3C5DD +Bits [7:0]: these bits returns the size of the memory region allocated to DFSDM registers. + 0 + 32 + read-only + + + B_0x2 + 2KB allocated by DFSDM peripheral (fixed value). + 0x2 + + + + + + + + + DLYBSD1 + DLYB + DLYB + 0x58006000 + + 0x0 + 0x1000 + registers + + + + DLYB_CR + DLYB_CR + DLYB control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DEN + Delay block enable bit + 0 + 1 + read-write + + + B_0x0 + DLYB disabled. + 0x0 + + + B_0x1 + DLYB enabled. + 0x1 + + + + + SEN + Sampler length enable bit + 1 + 1 + read-write + + + B_0x0 + Sampler length and register access to UNIT[6:0] and SEL[3:0] disabled, output clock enabled. + 0x0 + + + B_0x1 + Sampler length and register access to UNIT[6:0] and SEL[3:0] enabled, output clock disabled. + 0x1 + + + + + + + DLYB_CFGR + DLYB_CFGR + DLYB configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEL + Phase for the output clock. +These bits can only be written when SEN = 1. +Output clock phase = input clock + SEL[3:0] x unit delay + 0 + 4 + read-write + + + UNIT + Delay of a unit delay cell. +These bits can only be written when SEN = 1. +Unit delay = initial delay + UNIT[6:0] x delay step + 8 + 7 + read-write + + + LNG + Delay line length value +These bits reflect the 12 unit delay values sampled at the rising edge of the input clock. +The value is only valid when LNGF = 1. + 16 + 12 + read-only + + + LNGF + Length valid flag +This flag indicates when the delay line length value contained in LNG[11:0] is valid after UNIT[6:0] bits changed. + 31 + 1 + read-only + + + B_0x0 + Length value in LNG is not valid. + 0x0 + + + B_0x1 + Length value in LNG is valid. + 0x1 + + + + + + + + + DLYBSD2 + 0x58008000 + + + DLYBQS + 0x58004000 + + + DMAMUX1 + DMAMUX1 + DMAMUX + 0x48002000 + + 0x0 + 0x400 + registers + + + DMAMUX1_OVR_REQ + DMAMUX1 overrun interrupt + 99 + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C8CR + DMAMUX_C8CR + DMAMUX request line multiplexer channel 8 configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C9CR + DMAMUX_C9CR + DMAMUX request line multiplexer channel 9 configuration register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C10CR + DMAMUX_C10CR + DMAMUX request line multiplexer channel 10 configuration register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C11CR + DMAMUX_C11CR + DMAMUX request line multiplexer channel 11 configuration register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C12CR + DMAMUX_C12CR + DMAMUX request line multiplexer channel 12 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C13CR + DMAMUX_C13CR + DMAMUX request line multiplexer channel 13 configuration register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C14CR + DMAMUX_C14CR + DMAMUX request line multiplexer channel 14 configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C15CR + DMAMUX_C15CR + DMAMUX request line multiplexer channel 15 configuration register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF0 + SOF0 + 0 + 1 + + + SOF1 + SOF1 + 1 + 1 + + + SOF2 + SOF2 + 2 + 1 + + + SOF3 + SOF3 + 3 + 1 + + + SOF4 + SOF4 + 4 + 1 + + + SOF5 + SOF5 + 5 + 1 + + + SOF6 + SOF6 + 6 + 1 + + + SOF7 + SOF7 + 7 + 1 + + + SOF8 + SOF8 + 8 + 1 + + + SOF9 + SOF9 + 9 + 1 + + + SOF10 + SOF10 + 10 + 1 + + + SOF11 + SOF11 + 11 + 1 + + + SOF12 + SOF12 + 12 + 1 + + + SOF13 + SOF13 + 13 + 1 + + + SOF14 + SOF14 + 14 + 1 + + + SOF15 + SOF15 + 15 + 1 + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF0 + CSOF0 + 0 + 1 + + + CSOF1 + CSOF1 + 1 + 1 + + + CSOF2 + CSOF2 + 2 + 1 + + + CSOF3 + CSOF3 + 3 + 1 + + + CSOF4 + CSOF4 + 4 + 1 + + + CSOF5 + CSOF5 + 5 + 1 + + + CSOF6 + CSOF6 + 6 + 1 + + + CSOF7 + CSOF7 + 7 + 1 + + + CSOF8 + CSOF8 + 8 + 1 + + + CSOF9 + CSOF9 + 9 + 1 + + + CSOF10 + CSOF10 + 10 + 1 + + + CSOF11 + CSOF11 + 11 + 1 + + + CSOF12 + CSOF12 + 12 + 1 + + + CSOF13 + CSOF13 + 13 + 1 + + + CSOF14 + CSOF14 + 14 + 1 + + + CSOF15 + CSOF15 + 15 + 1 + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG4CR + DMAMUX_RG4CR + DMAMUX request generator channel 4 configuration register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG5CR + DMAMUX_RG5CR + DMAMUX request generator channel 5 configuration register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG6CR + DMAMUX_RG6CR + DMAMUX request generator channel 6 configuration register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG7CR + DMAMUX_RG7CR + DMAMUX request generator channel 7 configuration register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF0 + OF0 + 0 + 1 + + + OF1 + OF1 + 1 + 1 + + + OF2 + OF2 + 2 + 1 + + + OF3 + OF3 + 3 + 1 + + + OF4 + OF4 + 4 + 1 + + + OF5 + OF5 + 5 + 1 + + + OF6 + OF6 + 6 + 1 + + + OF7 + OF7 + 7 + 1 + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF0 + COF0 + 0 + 1 + + + COF1 + COF1 + 1 + 1 + + + COF2 + COF2 + 2 + 1 + + + COF3 + COF3 + 3 + 1 + + + COF4 + COF4 + 4 + 1 + + + COF5 + COF5 + 5 + 1 + + + COF6 + COF6 + 6 + 1 + + + COF7 + COF7 + 7 + 1 + + + + + DMAMUX_HWCFGR2 + DMAMUX_HWCFGR2 + DMAMUX hardware configuration 2 register + 0x3EC + 0x20 + read-only + 0x00000008 + + + NUM_DMA_EXT_REQ + NUM_DMA_EXT_REQ + 0 + 8 + + + + + DMAMUX_HWCFGR1 + DMAMUX_HWCFGR1 + DMAMUX hardware configuration 1 register + 0x3F0 + 0x20 + read-only + 0x08086C10 + + + NUM_DMA_STREAMS + NUM_DMA_STREAMS + 0 + 8 + + + NUM_DMA_PERIPH_REQ + NUM_DMA_PERIPH_REQ + 8 + 8 + + + NUM_DMA_TRIG + NUM_DMA_TRIG + 16 + 8 + + + NUM_DMA_REQGEN + NUM_DMA_REQGEN + 24 + 8 + + + + + DMAMUX_VERR + DMAMUX_VERR + This register identifies the IP version. + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DMAMUX_IPIDR + DMAMUX_IPIDR + This register identifies the IP. + 0x3F8 + 0x20 + read-only + 0x00100011 + + + ID + ID + 0 + 32 + + + + + DMAMUX_SIDR + DMAMUX_SIDR + DMAMUX size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DMAMUX2 + DMAMUX2 + DMAMUX + 0x48006000 + + 0x0 + 0x400 + registers + + + DMAMUX2_OVR_REQ + DMAMUX2 overrun interrupt + 100 + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF0 + SOF0 + 0 + 1 + + + SOF1 + SOF1 + 1 + 1 + + + SOF2 + SOF2 + 2 + 1 + + + SOF3 + SOF3 + 3 + 1 + + + SOF4 + SOF4 + 4 + 1 + + + SOF5 + SOF5 + 5 + 1 + + + SOF6 + SOF6 + 6 + 1 + + + SOF7 + SOF7 + 7 + 1 + + + SOF8 + SOF8 + 8 + 1 + + + SOF9 + SOF9 + 9 + 1 + + + SOF10 + SOF10 + 10 + 1 + + + SOF11 + SOF11 + 11 + 1 + + + SOF12 + SOF12 + 12 + 1 + + + SOF13 + SOF13 + 13 + 1 + + + SOF14 + SOF14 + 14 + 1 + + + SOF15 + SOF15 + 15 + 1 + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF0 + CSOF0 + 0 + 1 + + + CSOF1 + CSOF1 + 1 + 1 + + + CSOF2 + CSOF2 + 2 + 1 + + + CSOF3 + CSOF3 + 3 + 1 + + + CSOF4 + CSOF4 + 4 + 1 + + + CSOF5 + CSOF5 + 5 + 1 + + + CSOF6 + CSOF6 + 6 + 1 + + + CSOF7 + CSOF7 + 7 + 1 + + + CSOF8 + CSOF8 + 8 + 1 + + + CSOF9 + CSOF9 + 9 + 1 + + + CSOF10 + CSOF10 + 10 + 1 + + + CSOF11 + CSOF11 + 11 + 1 + + + CSOF12 + CSOF12 + 12 + 1 + + + CSOF13 + CSOF13 + 13 + 1 + + + CSOF14 + CSOF14 + 14 + 1 + + + CSOF15 + CSOF15 + 15 + 1 + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG4CR + DMAMUX_RG4CR + DMAMUX request generator channel 4 configuration register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG5CR + DMAMUX_RG5CR + DMAMUX request generator channel 5 configuration register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG6CR + DMAMUX_RG6CR + DMAMUX request generator channel 6 configuration register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG7CR + DMAMUX_RG7CR + DMAMUX request generator channel 7 configuration register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF0 + OF0 + 0 + 1 + + + OF1 + OF1 + 1 + 1 + + + OF2 + OF2 + 2 + 1 + + + OF3 + OF3 + 3 + 1 + + + OF4 + OF4 + 4 + 1 + + + OF5 + OF5 + 5 + 1 + + + OF6 + OF6 + 6 + 1 + + + OF7 + OF7 + 7 + 1 + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF0 + COF0 + 0 + 1 + + + COF1 + COF1 + 1 + 1 + + + COF2 + COF2 + 2 + 1 + + + COF3 + COF3 + 3 + 1 + + + COF4 + COF4 + 4 + 1 + + + COF5 + COF5 + 5 + 1 + + + COF6 + COF6 + 6 + 1 + + + COF7 + COF7 + 7 + 1 + + + + + DMAMUX_HWCFGR2 + DMAMUX_HWCFGR2 + DMAMUX hardware configuration 2 register + 0x3EC + 0x20 + read-only + 0x00000008 + + + NUM_DMA_EXT_REQ + NUM_DMA_EXT_REQ + 0 + 8 + + + + + DMAMUX_HWCFGR1 + DMAMUX_HWCFGR1 + DMAMUX hardware configuration 1 register + 0x3F0 + 0x20 + read-only + 0x08086C10 + + + NUM_DMA_STREAMS + NUM_DMA_STREAMS + 0 + 8 + + + NUM_DMA_PERIPH_REQ + NUM_DMA_PERIPH_REQ + 8 + 8 + + + NUM_DMA_TRIG + NUM_DMA_TRIG + 16 + 8 + + + NUM_DMA_REQGEN + NUM_DMA_REQGEN + 24 + 8 + + + + + DMAMUX_VERR + DMAMUX_VERR + This register identifies the IP version. + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DMAMUX_IPIDR + DMAMUX_IPIDR + This register identifies the IP. + 0x3F8 + 0x20 + read-only + 0x00100011 + + + ID + ID + 0 + 32 + + + + + DMAMUX_SIDR + DMAMUX_SIDR + DMAMUX size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DMA1 + DMA1 + DMA + 0x48000000 + + 0x0 + 0x400 + registers + + + DMA1_STR0 + DMA1 stream0 global interrupt + 11 + + + DMA1_STR1 + DMA1 stream1 global interrupt + 12 + + + DMA1_STR2 + DMA1 stream2 global interrupt + 13 + + + DMA1_STR3 + DMA1 stream3 global interrupt + 14 + + + DMA1_STR4 + DMA1 stream4 global interrupt + 15 + + + DMA1_STR5 + DMA1 stream5 global interrupt + 16 + + + DMA1_STR6 + DMA1 stream6 global interrupt + 17 + + + DMA1_STR7 + DMA1 stream7 global interrupt + 48 + + + + DMA_LISR + DMA_LISR + DMA low interrupt status register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FEIF0 + stream x FIFO error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 0 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF0 + stream x direct mode error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 2 + 1 + read-only + + + B_0x0 + No direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF0 + stream x transfer error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 3 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF0 + stream x half transfer interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 4 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF0 + stream x transfer complete interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 5 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF1 + stream x FIFO error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 6 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF1 + stream x direct mode error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 8 + 1 + read-only + + + B_0x0 + No direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF1 + stream x transfer error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 9 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF1 + stream x half transfer interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 10 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF1 + stream x transfer complete interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 11 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF2 + stream x FIFO error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 16 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF2 + stream x direct mode error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 18 + 1 + read-only + + + B_0x0 + No direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF2 + stream x transfer error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 19 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF2 + stream x half transfer interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 20 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF2 + stream x transfer complete interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 21 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF3 + stream x FIFO error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 22 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF3 + stream x direct mode error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 24 + 1 + read-only + + + B_0x0 + No direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF3 + stream x transfer error interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 25 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF3 + stream x half transfer interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 26 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF3 + stream x transfer complete interrupt flag (x = 3 to 0) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. + 27 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + + + DMA_HISR + DMA_HISR + DMA high interrupt status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FEIF4 + stream x FIFO error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 0 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF4 + stream x direct mode error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 2 + 1 + read-only + + + B_0x0 + no direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF4 + stream x transfer error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 3 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF4 + stream x half transfer interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 4 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF4 + stream x transfer complete interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 5 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF5 + stream x FIFO error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 6 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF5 + stream x direct mode error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 8 + 1 + read-only + + + B_0x0 + no direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF5 + stream x transfer error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 9 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF5 + stream x half transfer interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 10 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF5 + stream x transfer complete interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 11 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF6 + stream x FIFO error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 16 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF6 + stream x direct mode error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 18 + 1 + read-only + + + B_0x0 + no direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF6 + stream x transfer error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 19 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF6 + stream x half transfer interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 20 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF6 + stream x transfer complete interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 21 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + FEIF7 + stream x FIFO error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 22 + 1 + read-only + + + B_0x0 + no FIFO error event on stream x + 0x0 + + + B_0x1 + a FIFO error event occurred on stream x + 0x1 + + + + + DMEIF7 + stream x direct mode error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 24 + 1 + read-only + + + B_0x0 + no direct mode error on stream x + 0x0 + + + B_0x1 + a direct mode error occurred on stream x + 0x1 + + + + + TEIF7 + stream x transfer error interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 25 + 1 + read-only + + + B_0x0 + no transfer error on stream x + 0x0 + + + B_0x1 + a transfer error occurred on stream x + 0x1 + + + + + HTIF7 + stream x half transfer interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 26 + 1 + read-only + + + B_0x0 + no half transfer event on stream x + 0x0 + + + B_0x1 + a half transfer event occurred on stream x + 0x1 + + + + + TCIF7 + stream x transfer complete interrupt flag (x = 7 to 4) +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. + 27 + 1 + read-only + + + B_0x0 + no transfer complete event on stream x + 0x0 + + + B_0x1 + a transfer complete event occurred on stream x + 0x1 + + + + + + + DMA_LIFCR + DMA_LIFCR + DMA low interrupt flag clear register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFEIF0 + stream x clear FIFO error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register. + 0 + 1 + write-only + + + CDMEIF0 + stream x clear direct mode error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register. + 2 + 1 + write-only + + + CTEIF0 + Stream x clear transfer error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register. + 3 + 1 + write-only + + + CHTIF0 + stream x clear half transfer interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register + 4 + 1 + write-only + + + CTCIF0 + stream x clear transfer complete interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register. + 5 + 1 + write-only + + + CFEIF1 + stream x clear FIFO error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register. + 6 + 1 + write-only + + + CDMEIF1 + stream x clear direct mode error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register. + 8 + 1 + write-only + + + CTEIF1 + Stream x clear transfer error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register. + 9 + 1 + write-only + + + CHTIF1 + stream x clear half transfer interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register + 10 + 1 + write-only + + + CTCIF1 + stream x clear transfer complete interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register. + 11 + 1 + write-only + + + CFEIF2 + stream x clear FIFO error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register. + 16 + 1 + write-only + + + CDMEIF2 + stream x clear direct mode error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register. + 18 + 1 + write-only + + + CTEIF2 + Stream x clear transfer error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register. + 19 + 1 + write-only + + + CHTIF2 + stream x clear half transfer interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register + 20 + 1 + write-only + + + CTCIF2 + stream x clear transfer complete interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register. + 21 + 1 + write-only + + + CFEIF3 + stream x clear FIFO error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register. + 22 + 1 + write-only + + + CDMEIF3 + stream x clear direct mode error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register. + 24 + 1 + write-only + + + CTEIF3 + Stream x clear transfer error interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register. + 25 + 1 + write-only + + + CHTIF3 + stream x clear half transfer interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register + 26 + 1 + write-only + + + CTCIF3 + stream x clear transfer complete interrupt flag (x = 3 to 0) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register. + 27 + 1 + write-only + + + + + DMA_HIFCR + DMA_HIFCR + DMA high interrupt flag clear register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFEIF4 + stream x clear FIFO error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register. + 0 + 1 + write-only + + + CDMEIF4 + stream x clear direct mode error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. + 2 + 1 + write-only + + + CTEIF4 + stream x clear transfer error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register. + 3 + 1 + write-only + + + CHTIF4 + stream x clear half transfer interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register. + 4 + 1 + write-only + + + CTCIF4 + stream x clear transfer complete interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register. + 5 + 1 + write-only + + + CFEIF5 + stream x clear FIFO error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register. + 6 + 1 + write-only + + + CDMEIF5 + stream x clear direct mode error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. + 8 + 1 + write-only + + + CTEIF5 + stream x clear transfer error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register. + 9 + 1 + write-only + + + CHTIF5 + stream x clear half transfer interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register. + 10 + 1 + write-only + + + CTCIF5 + stream x clear transfer complete interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register. + 11 + 1 + write-only + + + CFEIF6 + stream x clear FIFO error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register. + 16 + 1 + write-only + + + CDMEIF6 + stream x clear direct mode error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. + 18 + 1 + write-only + + + CTEIF6 + stream x clear transfer error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register. + 19 + 1 + write-only + + + CHTIF6 + stream x clear half transfer interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register. + 20 + 1 + write-only + + + CTCIF6 + stream x clear transfer complete interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register. + 21 + 1 + write-only + + + CFEIF7 + stream x clear FIFO error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register. + 22 + 1 + write-only + + + CDMEIF7 + stream x clear direct mode error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. + 24 + 1 + write-only + + + CTEIF7 + stream x clear transfer error interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register. + 25 + 1 + write-only + + + CHTIF7 + stream x clear half transfer interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register. + 26 + 1 + write-only + + + CTCIF7 + stream x clear transfer complete interrupt flag (x = 7 to 4) +Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register. + 27 + 1 + write-only + + + + + DMA_S0CR + DMA_S0CR + DMA stream 0 configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S0NDTR + DMA_S0NDTR + DMA stream 0 number of data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S0PAR + DMA_S0PAR + DMA stream 0 peripheral address register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S0M0AR + DMA_S0M0AR + DMA stream 0 memory 0 address register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S0M1AR + DMA_S0M1AR + DMA stream 0 memory 1 address register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S0FCR + DMA_S0FCR + DMA stream 0 FIFO control register + 0x24 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S1CR + DMA_S1CR + DMA stream 1 configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S1NDTR + DMA_S1NDTR + DMA stream 1 number of data register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S1PAR + DMA_S1PAR + DMA stream 1 peripheral address register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S1M0AR + DMA_S1M0AR + DMA stream 1 memory 0 address register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S1M1AR + DMA_S1M1AR + DMA stream 1 memory 1 address register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S1FCR + DMA_S1FCR + DMA stream 1 FIFO control register + 0x3c + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S2CR + DMA_S2CR + DMA stream 2 configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S2NDTR + DMA_S2NDTR + DMA stream 2 number of data register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S2PAR + DMA_S2PAR + DMA stream 2 peripheral address register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S2M0AR + DMA_S2M0AR + DMA stream 2 memory 0 address register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S2M1AR + DMA_S2M1AR + DMA stream 2 memory 1 address register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S2FCR + DMA_S2FCR + DMA stream 2 FIFO control register + 0x54 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S3CR + DMA_S3CR + DMA stream 3 configuration register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S3NDTR + DMA_S3NDTR + DMA stream 3 number of data register + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S3PAR + DMA_S3PAR + DMA stream 3 peripheral address register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S3M0AR + DMA_S3M0AR + DMA stream 3 memory 0 address register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S3M1AR + DMA_S3M1AR + DMA stream 3 memory 1 address register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S3FCR + DMA_S3FCR + DMA stream 3 FIFO control register + 0x6c + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S4CR + DMA_S4CR + DMA stream 4 configuration register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S4NDTR + DMA_S4NDTR + DMA stream 4 number of data register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S4PAR + DMA_S4PAR + DMA stream 4 peripheral address register + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S4M0AR + DMA_S4M0AR + DMA stream 4 memory 0 address register + 0x7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S4M1AR + DMA_S4M1AR + DMA stream 4 memory 1 address register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S4FCR + DMA_S4FCR + DMA stream 4 FIFO control register + 0x84 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S5CR + DMA_S5CR + DMA stream 5 configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S5NDTR + DMA_S5NDTR + DMA stream 5 number of data register + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S5PAR + DMA_S5PAR + DMA stream 5 peripheral address register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S5M0AR + DMA_S5M0AR + DMA stream 5 memory 0 address register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S5M1AR + DMA_S5M1AR + DMA stream 5 memory 1 address register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S5FCR + DMA_S5FCR + DMA stream 5 FIFO control register + 0x9c + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S6CR + DMA_S6CR + DMA stream 6 configuration register + 0xa0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S6NDTR + DMA_S6NDTR + DMA stream 6 number of data register + 0xa4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S6PAR + DMA_S6PAR + DMA stream 6 peripheral address register + 0xa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S6M0AR + DMA_S6M0AR + DMA stream 6 memory 0 address register + 0xac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S6M1AR + DMA_S6M1AR + DMA stream 6 memory 1 address register + 0xb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S6FCR + DMA_S6FCR + DMA stream 6 FIFO control register + 0xb4 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_S7CR + DMA_S7CR + DMA stream 7 configuration register + 0xb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + stream enable / flag stream ready when read low +This bit is set and cleared by software. +This bit may be cleared by hardware: +on a DMA end of transfer (stream ready to be configured) +if a transfer error occurs on the AHB master buses +when the FIFO threshold on memory AHB port is not compatible with the size of the burst +When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. +Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. + 0 + 1 + read-write + + + B_0x0 + stream disabled + 0x0 + + + B_0x1 + stream enabled + 0x1 + + + + + DMEIE + direct mode error interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DME interrupt disabled + 0x0 + + + B_0x1 + DME interrupt enabled + 0x1 + + + + + TEIE + transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TE interrupt disabled + 0x0 + + + B_0x1 + TE interrupt enabled + 0x1 + + + + + HTIE + half transfer interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + HT interrupt disabled + 0x0 + + + B_0x1 + HT interrupt enabled + 0x1 + + + + + TCIE + transfer complete interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TC interrupt disabled + 0x0 + + + B_0x1 + TC interrupt enabled + 0x1 + + + + + PFCTRL + peripheral flow controller +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. +When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. + 5 + 1 + read-write + + + B_0x0 + DMA is the flow controller. + 0x0 + + + B_0x1 + The peripheral is the flow controller. + 0x1 + + + + + DIR + data transfer direction +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 6 + 2 + read-write + + + B_0x0 + peripheral-to-memory + 0x0 + + + B_0x1 + memory-to-peripheral + 0x1 + + + B_0x2 + memory-to-memory + 0x2 + + + + + CIRC + circular mode +This bit is set and cleared by software and can be cleared by hardware. +When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled (EN = 1), then this bit is automatically forced by hardware to 0. +It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1). + 8 + 1 + read-write + + + B_0x0 + circular mode disabled + 0x0 + + + B_0x1 + circular mode enabled + 0x1 + + + + + PINC + peripheral increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 9 + 1 + read-write + + + B_0x0 + peripheral address pointer fixed + 0x0 + + + B_0x1 + peripheral address pointer incremented after each data transfer (increment done according to PSIZE) + 0x1 + + + + + MINC + memory increment mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 10 + 1 + read-write + + + B_0x0 + memory address pointer is fixed + 0x0 + + + B_0x1 + memory address pointer is incremented after each data transfer (increment is done according to MSIZE) + 0x1 + + + + + PSIZE + peripheral data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 11 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + MSIZE + memory data size +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as EN = 1. + 13 + 2 + read-write + + + B_0x0 + byte (8-bit) + 0x0 + + + B_0x1 + half-word (16-bit) + 0x1 + + + B_0x2 + word (32-bit) + 0x2 + + + + + PINCOS + peripheral increment offset size +This bit is set and cleared by software +This bit has no meaning if bit PINC = 0. +This bit is protected and can be written only if EN = 0. +This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00. + 15 + 1 + read-write + + + B_0x0 + The offset size for the peripheral address calculation is linked to the PSIZE + 0x0 + + + B_0x1 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). + 0x1 + + + + + PL + priority level +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. + 16 + 2 + read-write + + + B_0x0 + low + 0x0 + + + B_0x1 + medium + 0x1 + + + B_0x2 + high + 0x2 + + + B_0x3 + very high + 0x3 + + + + + DBM + double-buffer mode +This bit is set and cleared by software. +This bit is protected and can be written only if EN = 0. + 18 + 1 + read-write + + + B_0x0 + no buffer switching at the end of transfer + 0x0 + + + B_0x1 + memory target switched at the end of the DMA transfer + 0x1 + + + + + CT + current target (only in double-buffer mode) +This bit is set and cleared by hardware. It can also be written by software. +This bit can be written only if EN = 0 to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. + 19 + 1 + read-write + + + B_0x0 + current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) + 0x0 + + + B_0x1 + current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) + 0x1 + + + + + TRBUFF + Enable the DMA to handle bufferable transfers. +Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers. + 20 + 1 + read-write + + + B_0x0 + bufferable transfers not enabled + 0x0 + + + B_0x1 + bufferable transfers enabled + 0x1 + + + + + PBURST + peripheral burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware. + 21 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + MBURST + memory burst transfer configuration +These bits are set and cleared by software. +These bits are protected and can be written only if EN = 0. +In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1. + 23 + 2 + read-write + + + B_0x0 + single transfer + 0x0 + + + B_0x1 + INCR4 (incremental burst of 4 beats) + 0x1 + + + B_0x2 + INCR8 (incremental burst of 8 beats) + 0x2 + + + B_0x3 + INCR16 (incremental burst of 16 beats) + 0x3 + + + + + + + DMA_S7NDTR + DMA_S7NDTR + DMA stream 7 number of data register + 0xbc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + number of data items to transfer (0 up to 65535) +This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: +when the stream is configured in circular mode. +when the stream is enabled again by setting EN bit to 1. +If the value of this register is zero, no transaction can be served even if the stream is enabled. + 0 + 16 + read-write + + + + + DMA_S7PAR + DMA_S7PAR + DMA stream 7 peripheral address register + 0xc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PAR + peripheral address +Base address of the peripheral data register from/to which the data is read/written. +These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR. + 0 + 32 + read-write + + + + + DMA_S7M0AR + DMA_S7M0AR + DMA stream 7 memory 0 address register + 0xc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M0A + memory 0 address +Base address of memory area 0 from/to which the data is read/written. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode). + 0 + 32 + read-write + + + + + DMA_S7M1AR + DMA_S7M1AR + DMA stream 7 memory 1 address register + 0xc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + M1A + memory 1 address (used in case of double-buffer mode) +Base address of memory area 1 from/to which the data is read/written. +This register is used only for the double-buffer mode. +These bits are write-protected. They can be written only if: +the stream is disabled (EN = 0 in DMA_SxCR) or +the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR . + 0 + 32 + read-write + + + + + DMA_S7FCR + DMA_S7FCR + DMA stream 7 FIFO control register + 0xcc + 0x20 + 0x00000021 + 0xFFFFFFFF + + + FTH + FIFO threshold selection +These bits are set and cleared by software. +These bits are not used in the direct mode when the DMIS = 0. +These bits are protected and can be written only if EN = 0. + 0 + 2 + read-write + + + B_0x0 + 1/4 full FIFO + 0x0 + + + B_0x1 + 1/2 full FIFO + 0x1 + + + B_0x2 + 3/4 full FIFO + 0x2 + + + B_0x3 + full FIFO + 0x3 + + + + + DMDIS + direct mode disable +This bit is set and cleared by software. It can be set by hardware. +This bit is protected and can be written only if EN = 0. +This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration. + 2 + 1 + read-write + + + B_0x0 + direct mode enabled + 0x0 + + + B_0x1 + direct mode disabled + 0x1 + + + + + FS + FIFO status +These bits are read-only. +others: no meaning +These bits are not relevant in the direct mode (DMDIS = 0). + 3 + 3 + read-only + + + B_0x0 + 0 < fifo_level < 1/4 + 0x0 + + + B_0x1 + 1/4 ≤ fifo_level < 1/2 + 0x1 + + + B_0x2 + 1/2 ≤ fifo_level < 3/4 + 0x2 + + + B_0x3 + 3/4 ≤ fifo_level < full + 0x3 + + + B_0x4 + FIFO is empty + 0x4 + + + B_0x5 + FIFO is full + 0x5 + + + + + FEIE + FIFO error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + FE interrupt disabled + 0x0 + + + B_0x1 + FE interrupt enabled + 0x1 + + + + + + + DMA_HWCFGR2 + DMA_HWCFGR2 + DMA hardware configuration 2 register + 0x3ec + 0x20 + 0x00000001 + 0xFFFFFFFF + + + FIFO_SIZE + FIFO size, common to all streams +In [0..3] range: +2: 8-word FIFO +3: 16-word FIFO + 0 + 2 + read-only + + + B_0x0 + 2-word FIFO + 0x0 + + + B_0x1 + 4-word FIFO + 0x1 + + + + + WRITE_BUFFERABLE + In any case, DMA acknowledge signal is asserted one cycle after the address phase of the bus access on its AHB peripheral master port. + 4 + 1 + read-only + + + B_0x0 + DMA acknowledge signal is de-asserted one cycle after occurred both 1) the last cycle of the data phase of the bus access on its AHB peripheral master port and 2) the de-assertion of the peripheral request + 0x0 + + + B_0x1 + DMA acknowledge signal is de-asserted exactly one cycle after the last cycle of the data phase of the bus access on its AHB peripheral master port + 0x1 + + + + + CHSEL_WIDTH + bit width of the CHSEL field of any DMA_SxCR register common to all streams +In [0..6] range: +2: up to 8 channels programmable selection +3: up to 16 channels programmable selection +4: up to 32 channels programmable selection +5: up to 64 channels programmable selection +6: up to 128 channels programmable selection + 8 + 3 + read-only + + + B_0x0 + no programmable selection + 0x0 + + + B_0x1 + 2 channels programmable selection + 0x1 + + + + + + + DMA_HWCFGR1 + DMA_HWCFGR1 + DMA hardware configuration 1 register + 0x3f0 + 0x20 + 0x22222222 + 0xFFFFFFFF + + + DMA_DEF0 + type of the stream 0 +2: double-buffer +3: Reserved + 0 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF1 + type of the stream 1 +2: double-buffer +3: Reserved + 4 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF2 + type of the stream 2 +2: double-buffer +3: Reserved + 8 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF3 + type of the stream 3 +2: double-buffer +3: Reserved + 12 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF4 + type of the stream 4 +2: double-buffer +3: Reserved + 16 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF5 + type of the stream 5 +2: double-buffer +3: Reserved + 20 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF6 + type of the stream 6 +2: double-buffer +3: Reserved + 24 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + DMA_DEF7 + type of the stream 7 +2: double-buffer +3: Reserved + 28 + 2 + read-only + + + B_0x0 + none + 0x0 + + + B_0x1 + regular + 0x1 + + + + + + + DMA_VERR + DMA_VERR + DMA version register + 0x3f4 + 0x20 + 0x00000014 + 0xFFFFFFFF + + + MINREV + minor IP revision + 0 + 4 + read-only + + + MAJREV + major IP revision + 4 + 4 + read-only + + + + + DMA_IPDR + DMA_IPDR + DMA identification register + 0x3f8 + 0x20 + 0x00100002 + 0xFFFFFFFF + + + ID + size identification +This register identifies the peripheral. + 0 + 32 + read-only + + + + + DMA_SIDR + DMA_SIDR + DMA size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + size identification +This register identifies the DMA as a peripheal with a size of 1 Kbyte address space. + 0 + 32 + read-only + + + + + + + DMA2 + 0x48001000 + + DMA2_STR0 + DMA2 stream0 global interrupt + 57 + + + DMA2_STR1 + DMA2 stream1 global interrupt + 58 + + + DMA2_STR2 + DMA2 stream2 global interrupt + 59 + + + DMA2_STR3 + DMA2 stream3 global interrupt + 60 + + + DMA2_STR4 + DMA2 stream4 global interrupt + 61 + + + DMA2_STR5 + DMA2 stream5 global interrupt + 69 + + + DMA2_STR6 + DMA2 stream6 global interrupt + 70 + + + DMA2_STR7 + DMA2 stream7 global interrupt + 71 + + + + DMA3 + 0x48005000 + + DMA3_STR0 + DMA3 stream0 global interrupt + 142 + + + DMA3_STR1 + DMA3 stream1 global interrupt + 143 + + + DMA3_STR2 + DMA3 stream2 global interrupt + 144 + + + DMA3_STR3 + DMA3 stream3 global interrupt + 145 + + + DMA3_STR4 + DMA3 stream4 global interrupt + 146 + + + DMA3_STR5 + DMA3 stream5 global interrupt + 147 + + + DMA3_STR6 + DMA3 stream6 global interrupt + 148 + + + DMA3_STR7 + DMA3 stream7 global interrupt + 149 + + + + DTS + DTS register block + DTS + 0x50028000 + + 0x0 + 0x400 + registers + + + DTS + Digital temperature sensor interrupt + 124 + + + + DTS_CFGR1 + DTS_CFGR1 + DTS_CFGR1 is the configuration register for temperature sensor 1. + 0x0 + 0x20 + read-write + 0x00000000 + + + TS1_EN + TS1_EN + 0 + 1 + + + TS1_START + TS1_START + 4 + 1 + + + TS1_INTRIG_SEL + TS1_INTRIG_SEL + 8 + 4 + + + TS1_SMP_TIME + TS1_SMP_TIME + 16 + 4 + + + REFCLK_SEL + REFCLK_SEL + 20 + 1 + + + Q_MEAS_opt + Q_MEAS_opt + 21 + 1 + + + HSREF_CLK_DIV + HSREF_CLK_DIV + 24 + 7 + + + + + DTS_T0VALR1 + DTS_T0VALR1 + DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. + 0x8 + 0x20 + read-only + 0x00000000 + + + TS1_FMT0 + TS1_FMT0 + 0 + 16 + + + TS1_T0 + TS1_T0 + 16 + 2 + + + + + DTS_RAMPVALR + DTS_RAMPVALR + The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. + 0x10 + 0x20 + read-only + 0x00000000 + + + TS1_RAMP_COEFF + TS1_RAMP_COEFF + 0 + 16 + + + + + DTS_ITR1 + DTS_ITR1 + DTS_ITR1 contains the threshold values for sensor 1. + 0x14 + 0x20 + read-write + 0x00000000 + + + TS1_LITTHD + TS1_LITTHD + 0 + 16 + + + TS1_HITTHD + TS1_HITTHD + 16 + 16 + + + + + DTS_DR + DTS_DR + The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. + 0x1C + 0x20 + read-write + 0x00000000 + + + TS1_MFREQ + TS1_MFREQ + 0 + 16 + + + + + DTS_SR + DTS_SR + Temperature sensor status register + 0x20 + 0x20 + read-only + 0x00000000 + + + TS1_ITEF + TS1_ITEF + 0 + 1 + + + TS1_ITLF + TS1_ITLF + 1 + 1 + + + TS1_ITHF + TS1_ITHF + 2 + 1 + + + TS1_AITEF + TS1_AITEF + 4 + 1 + + + TS1_AITLF + TS1_AITLF + 5 + 1 + + + TS1_AITHF + TS1_AITHF + 6 + 1 + + + TS1_RDY + TS1_RDY + 15 + 1 + + + + + DTS_ITENR + DTS_ITENR + Temperature sensor interrupt enable register + 0x24 + 0x20 + read-write + 0x00000000 + + + TS1_ITEEN + TS1_ITEEN + 0 + 1 + + + TS1_ITLEN + TS1_ITLEN + 1 + 1 + + + TS1_ITHEN + TS1_ITHEN + 2 + 1 + + + TS1_AITEEN + TS1_AITEEN + 4 + 1 + + + TS1_AITLEN + TS1_AITLEN + 5 + 1 + + + TS1_AITHEN + TS1_AITHEN + 6 + 1 + + + + + DTS_ICIFR + DTS_ICIFR + DTS_ICIFR is the control register for the interrupt flags. + 0x28 + 0x20 + read-write + 0x00000000 + + + TS1_CITEF + TS1_CITEF + 0 + 1 + + + TS1_CITLF + TS1_CITLF + 1 + 1 + + + TS1_CITHF + TS1_CITHF + 2 + 1 + + + TS1_CAITEF + TS1_CAITEF + 4 + 1 + + + TS1_CAITLF + TS1_CAITLF + 5 + 1 + + + TS1_CAITHF + TS1_CAITHF + 6 + 1 + + + + + DTS_OR + DTS_OR + The DTS_OR contains general-purpose option bits. + 0x2C + 0x20 + read-write + 0x00000000 + + + TS_Op0 + TS_Op0 + 0 + 1 + + + TS_Op1 + TS_Op1 + 1 + 1 + + + TS_Op2 + TS_Op2 + 2 + 1 + + + TS_Op3 + TS_Op3 + 3 + 1 + + + TS_Op4 + TS_Op4 + 4 + 1 + + + TS_Op5 + TS_Op5 + 5 + 1 + + + TS_Op6 + TS_Op6 + 6 + 1 + + + TS_Op7 + TS_Op7 + 7 + 1 + + + TS_Op8 + TS_Op8 + 8 + 1 + + + TS_Op9 + TS_Op9 + 9 + 1 + + + TS_Op10 + TS_Op10 + 10 + 1 + + + TS_Op11 + TS_Op11 + 11 + 1 + + + TS_Op12 + TS_Op12 + 12 + 1 + + + TS_Op13 + TS_Op13 + 13 + 1 + + + TS_Op14 + TS_Op14 + 14 + 1 + + + TS_Op15 + TS_Op15 + 15 + 1 + + + TS_Op16 + TS_Op16 + 16 + 1 + + + TS_Op17 + TS_Op17 + 17 + 1 + + + TS_Op18 + TS_Op18 + 18 + 1 + + + TS_Op19 + TS_Op19 + 19 + 1 + + + TS_Op20 + TS_Op20 + 20 + 1 + + + TS_Op21 + TS_Op21 + 21 + 1 + + + TS_Op22 + TS_Op22 + 22 + 1 + + + TS_Op23 + TS_Op23 + 23 + 1 + + + TS_Op24 + TS_Op24 + 24 + 1 + + + TS_Op25 + TS_Op25 + 25 + 1 + + + TS_Op26 + TS_Op26 + 26 + 1 + + + TS_Op27 + TS_Op27 + 27 + 1 + + + TS_Op28 + TS_Op28 + 28 + 1 + + + TS_Op29 + TS_Op29 + 29 + 1 + + + TS_Op30 + TS_Op30 + 30 + 1 + + + TS_Op31 + TS_Op31 + 31 + 1 + + + + + + + ETH1 + ETH + ETH + 0x5800A000 + + 0x0 + 0x2000 + registers + + + ETH1 + Ethernet 1 global interrupt + 62 + + + ETH1_WKUP + Ethernet 1 wakeup interrupt (PMT) + 63 + + + + ETH_MACCR + ETH_MACCR + Operating mode configuration register + 0x0 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + RE + Receiver Enable +When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the GMII or MII interface. + 0 + 1 + read-write + + + TE + Transmitter Enable +When this bit is set, the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets. + 1 + 1 + read-write + + + PRELEN + Preamble Length for Transmit packets +These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. + 2 + 2 + read-write + + + B_0x0 + 7 bytes of preamble + 0x0 + + + B_0x1 + 5 bytes of preamble + 0x1 + + + B_0x2 + 3 bytes of preamble + 0x2 + + + B_0x3 + Reserved, must not be used + 0x3 + + + + + DC + Deferral Check +When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode. +If the MAC is configured for 1000 Mbps operation, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. +The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted. +When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. +This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the full-duplex-only configurations. + 4 + 1 + read-write + + + BL + Back-Off Limit +The back-off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. +where - = retransmission attempt +The random integer r takes the value in the range 0 <= r < 2^k +This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the full-duplex-only configurations. + 5 + 2 + read-write + + + B_0x0 + k= min (n, 10) + 0x0 + + + B_0x1 + k = min (n, 8) + 0x1 + + + B_0x2 + k = min (n, 4) + 0x2 + + + B_0x3 + k = min (n, 1) + 0x3 + + + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status. +When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the full-duplex-only configurations. + 8 + 1 + read-write + + + DCRS + Disable Carrier Sense During Transmission +When this bit is set, the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission. +When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission. +This bit is reserved and read-only (RO) in the full-duplex-only configurations. + 9 + 1 + read-write + + + DO + Disable Receive Own +When this bit is set, the MAC disables the reception of packets when the ETH_TX_EN is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY. +This bit is not applicable in the full-duplex mode. This bit is reserved and read-only (RO) with default value in the full-duplex-only configurations. + 10 + 1 + read-write + + + ECRSFD + Enable Carrier Sense Before Transmission in Full-Duplex Mode +When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. +When this bit is reset, the MAC transmitter ignores the status of the CRS signal. + 11 + 1 + read-write + + + LM + Loopback Mode +When this bit is set, the MAC operates in the loopback mode at GMII or MII. The GMII Rx clock input (eth_mii_rx_clk) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. + 12 + 1 + read-write + + + DM + Duplex Mode +When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations. + 13 + 1 + read-write + + + FES + MAC Speed +This bit selects the speed in the 10/100 Mbps mode: +In the 1000 Mbps-only configurations, this bit is read-only with the reset value. In the 10 or 100 Mbps-only or default 10/100/1000 Mbps configurations, this bit is read-write. The mac_speed_o[0] signal reflects the value of this bit. + 14 + 1 + read-write + + + B_0x0 + 10 Mbps + 0x0 + + + B_0x1 + 100 Mbps + 0x1 + + + + + PS + Port Select +This bit selects the Ethernet line speed. +In 10 or 100 Mbps operations, this bit, along with Bit 14, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only (RO) with appropriate value. In default 10/100/1000 Mbps configurations, this bit is read-write (rw). The mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + B_0x0 + For 1000 Mbps operations + 0x0 + + + B_0x1 + For 10 or 100 Mbps operations + 0x1 + + + + + JE + Jumbo Packet Enable +When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. + 16 + 1 + read-write + + + JD + Jabber Disable +When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes. +When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet. + 17 + 1 + read-write + + + BE + Packet Burst Enable +When this bit is set, the MAC allows packet bursting during transmission in the GMII half-duplex mode. This bit is reserved and read-only (RO) in the 10/100 Mbps-only or full-duplex-only configurations. + 18 + 1 + read-write + + + WD + Watchdog Disable +When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes. +When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes. + 19 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping +When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. +When this bit is reset, the MAC passes all incoming packets to the application, without any modification. +Note: For information about how the settings of CST bit and this bit impact the packet length, see the Table, Packet Length based on the CST and ACS Bit. + 20 + 1 + read-write + + + CST + CRC stripping for Type packets +When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. +Note: For information about how the settings of the ACS bit and this bit impact the packet length, see Packet Length based on the CST and ACS Bits. + 21 + 1 + read-write + + + S2KP + IEEE 802.3as Support for 2K Packets +When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets. +When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see Gaint Packet Status based on S2KP and JE Bits. +Note: When the JE bit is set, setting this bit has no effect on the giant packet status. + 22 + 1 + read-write + + + GPSLCE + Giant Packet Size Limit Control Enable +When this bit is set, the MAC considers the value in GPSL field in ETH_MACECR register to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit. +When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet). +The watchdog timeout limit, Jumbo Packet Enable and 2K Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2K Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status. + 23 + 1 + read-write + + + IPG + Inter-Packet Gap +These bits control the minimum IPG between packets during transmission. +... +This range of minimum IPG is valid in full-duplex mode. +In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. +When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG. +The above function (IPG less than 96 bit times) is valid only when EIPGEN bit in ETH_MACECR register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in ETH_MACECR register. + 24 + 3 + read-write + + + B_0x0 + 96 bit times + 0x0 + + + B_0x1 + 88 bit times + 0x1 + + + B_0x2 + 80 bit times + 0x2 + + + B_0x7 + 40 bit times + 0x7 + + + + + IPC + Checksum Offload +When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled. +The Layer 3 and Layer 4 Packet Filter and Enable Split Header features automatically selects the IPC Full Checksum Offload Engine on the Receive side. When any of these features are enabled, you must set the IPC bit. + 27 + 1 + read-write + + + SARC + Source Address Insertion or Replacement Control +This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28] +Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. + 28 + 3 + read-write + + + B_0x0 + Reserved, must not be used + 0x0 + + + B_0x1 + Reserved, must not be used. + 0x1 + + + B_0x2 + the MAC inserts the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets. + 0x2 + + + B_0x3 + the MAC replaces the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets. + 0x3 + + + B_0x4 + Reserved, must not be used + 0x4 + + + B_0x5 + Reserved, must not be used. + 0x5 + + + B_0x6 + the MAC inserts the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets. + 0x6 + + + B_0x7 + the MAC replaces the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets. + 0x7 + + + + + ARPEN + ARP Offload Enable +When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It will forward the ARP packet to the application and also indicate the events in the RxStatus. +When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus. + 31 + 1 + read-write + + + + + ETH_MACECR + ETH_MACECR + Extended operating mode configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPSL + Giant Packet Size Limit +If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes. +For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. For double VLAN tagged packets, the MAC adds 8 bytes to the programmed value. The value in this field is applicable when the GPSLCE bit is set in ETH_MACCR register. + 0 + 14 + read-write + + + DCRCC + Disable CRC Checking for Received Packets +When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets. + 16 + 1 + read-write + + + SPEN + Slow Protocol Detection Enable +When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. +When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets. + 17 + 1 + read-write + + + USP + Unicast Slow Protocol Packet Detect +When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the ETH_MACA0HR and ETH_MACA0LR registers. The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02). +When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2008, Section 5. + 18 + 1 + read-write + + + EIPGEN + Extended Inter-Packet Gap Enable +When this bit is set, the MAC interprets EIPG field and IPG field in ETH_MACCR together as minimum IPG greater than 96 bit times in steps of 8 bit times. +When this bit is reset, the MAC ignores EIPG field and interprets IPG field in ETH_MACCR as minimum IPG less than or equal to 96 bit times in steps of 8 bit times. +Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-Duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-Duplex mode. + 24 + 1 + read-write + + + EIPG + Extended Inter-Packet Gap +The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits) along with IPG field in ETH_MACCR, gives the minimum IPG greater than 96 bit times in steps of 8 bit times. /* FIXME : enum values removed for the moment */ + 25 + 5 + read-write + + + + + ETH_MACPFR + ETH_MACPFR + Packet filtering control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PR + Promiscuous Mode +When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + HUC + Hash Unicast +When this bit is set, the MAC performs the destination address filtering of unicast packets according to the Hash table. +When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + HMC + Hash Multicast +When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the Hash table. +When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + DAIF + DA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed. + 3 + 1 + read-write + + + PM + Pass All Multicast +When this bit is set, it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset, filtering of multicast packet depends on HMC bit. + 4 + 1 + read-write + + + DBF + Disable Broadcast Packets +When this bit is set, the AFM module blocks all incoming broadcast packets. In addition, it overrides all other filter settings. +When this bit is reset, the AFM module passes all received broadcast packets. + 5 + 1 + read-write + + + PCF + Pass Control Packets +These bits control the forwarding of all control packets (including unicast and multicast Pause packets). + 6 + 2 + read-write + + + B_0x0 + The MAC filters all control packets from reaching the application. + 0x0 + + + B_0x1 + The MAC forwards all control packets except Pause packets to the application even if they fail the Address filter. + 0x1 + + + B_0x2 + The MAC forwards all control packets to the application even if they fail the Address filter. + 0x2 + + + B_0x3 + The MAC forwards the control packets that pass the Address filter. + 0x3 + + + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter. +When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter. + 8 + 1 + read-write + + + SAF + Source Address Filter Enable +When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet. +When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison. +Note: According to the IEEE specification, Bit 47 of the SA is reserved. However, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA. + 9 + 1 + read-write + + + HPF + Hash or Perfect Filter +When this bit is set, the address filter passes a packet if it matches either the perfect filtering or Hash filtering as set by the HMC or HUC bit. +When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable +When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag. + 16 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable +When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. +When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + DNTU + Drop Non-TCP/UDP over IP Packets +When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets. + 21 + 1 + read-write + + + RA + Receive All +When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word. +When this bit is reset, the Receiver module passes only those packets to the application that pass the SA or DA address filter. + 31 + 1 + read-write + + + + + ETH_MACWTR + ETH_MACWTR + Watchdog timeout register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WTO + Watchdog Timeout +When the PWE bit is set and the WD bit of the ETH_MACCR register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet. +Encoding is as follows: +.. +Note: When the PWE bit is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE 802.3-specified valid tagged packets are declared as error packets and then dropped. + 0 + 4 + read-write + + + B_0x0 + 2 Kbytes + 0x0 + + + B_0x1 + 3 Kbytes + 0x1 + + + B_0x2 + 4 Kbytes + 0x2 + + + B_0x3 + 5 Kbytes + 0x3 + + + B_0xC + 14 Kbytes + 0xC + + + B_0xD + 15 Kbytes + 0xD + + + B_0xE + 16383 Bytes + 0xE + + + B_0xF + Reserved, must not be used + 0xF + + + + + PWE + Programmable Watchdog Enable +When this bit is set and the WD bit of the ETH_MACCR register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in ETH_MACCR register. + 8 + 1 + read-write + + + + + ETH_MACHT0R + ETH_MACHT0R + Hash Table 0 register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + MAC Hash Table First 32 Bits +This field contains the first 32 Bits [31:0] of the Hash table. + 0 + 32 + read-write + + + + + ETH_MACHT1R + ETH_MACHT1R + Hash Table 1 register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HT63T32 + MAC Hash Table Second 32 Bits +This field contains the second 32 Bits [63:32] of the Hash table. + 0 + 32 + read-write + + + + + ETH_MACVTR + ETH_MACVTR + VLAN tag register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VL + VLAN Tag Identifier for Receive Packets +This field contains the 802.1Q VLAN tag to identify the VLAN packets. This VLAN tag identifier is compared to the 15th and 16th bytes of the packets being received for VLAN packets. The following list describes the bits of this field: +Bits[15:13]: User Priority +Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) +Bits[11:0]: VLAN Identifier (VID) field of VLAN tag +When the ETV bit is set, only the VID is used for comparison. +If this field ([11:0] if ETV is set) is all zeros, the MAC does not check the 15th and 16th bytes for VLAN tag comparison and declares all packets with Type field value of 0x8100 or 0x88a8 as VLAN packets. + 0 + 16 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison +When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits[11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet. Similarly, when enabled, only 12 bits of the VLAN tag in the received packet are used for Hash-based VLAN filtering. +When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for comparison and VLAN Hash filtering. + 16 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ESVL + Enable S-VLAN +When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. + 18 + 1 + read-write + + + ERSVLM + Enable Receive S-VLAN Match +When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets. +The ERIVLT bit determines the VLAN tag position considered for filtering or matching. + 19 + 1 + read-write + + + DOVLTC + Disable VLAN Type Check +When this bit is set, the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN. +When this bit is reset, the MAC filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit. + 20 + 1 + read-write + + + EVLS + Enable VLAN Tag Stripping on Receive +This field indicates the stripping operation on the outer VLAN Tag in received packet: + 21 + 2 + read-write + + + B_0x0 + Do not strip + 0x0 + + + B_0x1 + Strip if VLAN filter passes + 0x1 + + + B_0x2 + Strip if VLAN filter fails + 0x2 + + + B_0x3 + Always strip + 0x3 + + + + + EVLRXS + Enable VLAN Tag in Rx status +When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status. + 24 + 1 + read-write + + + VTHM + VLAN Tag Hash Table Match Enable +When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the ETH_MACVLANHTR register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN Hash table. +When the ETV bit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison. +When this bit is reset, the VLAN Hash Match operation is not performed. If the VLAN Hash feature is not enabled, this bit is reserved (RO with default value). + 25 + 1 + read-write + + + EDVLP + Enable Double VLAN Processing +When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). + 26 + 1 + read-write + + + ERIVLT + Enable Inner VLAN Tag +When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present). The ERSVLM bit determines which VLAN type is enabled for filtering or matching. + 27 + 1 + read-write + + + EIVLS + Enable Inner VLAN Tag Stripping on Receive +This field indicates the stripping operation on inner VLAN Tag in received packet: + 28 + 2 + read-write + + + B_0x0 + Do not strip + 0x0 + + + B_0x1 + Strip if VLAN filter passes + 0x1 + + + B_0x2 + Strip if VLAN filter fails + 0x2 + + + B_0x3 + Always strip + 0x3 + + + + + EIVLRXS + Enable Inner VLAN Tag in Rx Status +When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status. + 31 + 1 + read-write + + + + + ETH_MACVHTR + ETH_MACVHTR + VLAN Hash table register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VLHT + VLAN Hash Table +This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + ETH_MACVIR + ETH_MACVIR + VLAN inclusion register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VLT + VLAN Tag for Transmit Packets +This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. +Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag. +The following list describes the bits of this field: +Bits[15:13]: User Priority +Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) +Bits[11:0]: VLAN Identifier (VID) field of VLAN tag + 0 + 16 + read-write + + + VLC + VLAN Tag Control in Transmit Packets +Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. + 16 + 2 + read-write + + + B_0x0 + No VLAN tag deletion, insertion, or replacement + 0x0 + + + B_0x1 + VLAN tag deletion. The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags. + 0x1 + + + B_0x2 + VLAN tag insertion. The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and 14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. + 0x2 + + + B_0x3 + VLAN tag replacement. The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8). + 0x3 + + + + + VLP + VLAN Priority Control +When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, bits[17:16] are ignored. + 18 + 1 + read-write + + + CSVL + C-VLAN or S-VLAN +When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. + 19 + 1 + read-write + + + VLTI + VLAN Tag Input +When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor. + 20 + 1 + read-write + + + + + ETH_MACIVIR + ETH_MACIVIR + Inner VLAN inclusion register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VLT + VLAN Tag for Transmit Packets +This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. +Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag. +The following list describes the bits of this field: +Bits[15:13]: User Priority +Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) +Bits[11:0]: VLAN Identifier (VID) field of VLAN tag + 0 + 16 + read-write + + + VLC + VLAN Tag Control in Transmit Packets +The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. +The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. +The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8). +Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. + 16 + 2 + read-write + + + B_0x0 + No VLAN tag deletion, insertion, or replacement + 0x0 + + + B_0x1 + VLAN tag deletion + 0x1 + + + B_0x2 + VLAN tag insertion + 0x2 + + + B_0x3 + VLAN tag replacement + 0x3 + + + + + VLP + VLAN Priority Control +When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the VLC field is ignored. + 18 + 1 + read-write + + + CSVL + C-VLAN or S-VLAN +When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. + 19 + 1 + read-write + + + VLTI + VLAN Tag Input +When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor + 20 + 1 + read-write + + + + + ETH_MACQ0TXFCR + ETH_MACQ0TXFCR + Tx Queue 0 flow control register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FCB_BPA + Flow Control Busy or Backpressure Activate +This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. +Full-Duplex Mode: this bit should be read as 0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 0. You should not write to this register until this bit is cleared. +Half-Duplex Mode: When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + TFE + Transmit Flow Control Enable +Full-Duplex Mode: when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets. +Half-Duplex Mode: when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + PLT + Pause Low Threshold +This field configures the threshold of the Pause timer at which the input flow is checked for automatic retransmission of the Pause packet. +The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted at 228 (256-28) slot times after the first Pause packet is transmitted. +The following list provides the threshold values for different values: +The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. +This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times. + 4 + 3 + read-write + + + B_0x0 + Pause Time minus 4 Slot Times (PT -4 slot times) + 0x0 + + + B_0x1 + Pause Time minus 28 Slot Times (PT -28 slot times) + 0x1 + + + B_0x2 + Pause Time minus 36 Slot Times (PT -36 slot times) + 0x2 + + + B_0x3 + Pause Time minus 144 Slot Times (PT -144 slot times) + 0x3 + + + B_0x4 + Pause Time minus 256 Slot Times (PT -256 slot times) + 0x4 + + + B_0x5 + Pause Time minus 512 Slot Times (PT -512 slot times) + 0x5 + + + B_0x6 + Reserved, must not be used + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + + + DZPQ + Disable Zero-Quanta Pause +When this bit is set, it disables the automatic generation of the zero-quanta Pause packets. +When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled. + 7 + 1 + read-write + + + PT + Pause Time +This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain, consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + + + ETH_MACRXFCR + ETH_MACRXFCR + Rx flow control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RFE + Receive Flow Control Enable +When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in half-duplex mode, the decode function of the Pause packet is disabled. +When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time. + 0 + 1 + read-write + + + UP + Unicast Pause Packet Detect +A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in ETH_MACA0HR and ETH_MACA0LR. +When this bit is reset, the MAC only detects Pause packets with unique multicast address. +Note: The MAC does not process a Pause packet if the multicast address is different from the unique multicast address. This is also applicable to the received PFC packet when the Priority Flow Control (PFC) is enabled. The unique multicast address (0x01_80_C2_00_00_01) is as specified in IEEE 802.1 Qbb-2011. + 1 + 1 + read-write + + + + + ETH_MACTXQPMR + ETH_MACTXQPMR + Tx queue priority mapping 0 register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PSTQ0 + Priorities Selected in Transmit Queue 0 +This bit is similar to the PSTQ1 bit. + 0 + 8 + read-only + + + PSTQ1 + Priorities Selected in Transmit Queue 1 +This field holds the priorities assigned to Tx queue 1 by software. It determines if Tx queue 1 is blocked from transmitting during a specific pause time when a PFC packet is received with a priority that matches the priority programmed in this field. +If the content of this field is the same as Queue 0, the MAC blocks the two queues for a specific period of time. + 8 + 8 + read-only + + + + + ETH_MACRXQC2R + ETH_MACRXQC2R + Rx queue control 2 register + 0xa8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PSRQ0 + Priorities Selected in the Receive Queue 0 +This field defines the priorities assigned to Rx queue 0. All packets with priorities that match the values set in this field are routed to Rx queue 0. +For example, if PSRQ0[5] is set, packets with USP field equal to 5 are routed to Rx queue 0. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. + 0 + 8 + read-write + + + PSRQ1 + Priorities Selected in the Receive Queue 1 +This field defines the priorities assigned to Rx queue 1. All packets with priorities that match the values set in this field are routed to Rx queue 1. +For example, if PSRQ1[4] is set, packets with USP field equal to 4 are routed to Rx queue 1. The software must ensure that the content of this +field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. + 8 + 8 + read-write + + + + + ETH_MACISR + ETH_MACISR + Interrupt status register + 0xb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set by any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in ETH_MACPHYCSR register). This bit is cleared when the ETH_MACPHYCSR register is read. + 0 + 1 + read-only + + + PHYIS + PHY Interrupt +This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read. + 3 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in ETH_MACPCSR register). This bit is cleared when Bits[6:5] are cleared because of a Read operation to the ETH_MACPCSR register. +This bit is valid only when you select the Enable power management option. + 4 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the TLPIEN bit of ETH_MACLCSR register is read. In all other modes, this bit is reserved. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when Bit 11, Bit 10, or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC management counters (MMC) option. + 8 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. +This bit is valid only when you select the Enable MAC Management Counters (MMC) option. + 9 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. +This bit is valid only when you select the Enable MAC management counters (MMC) option. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +If the Timestamp feature is enabled, this bit is set when any of the following conditions is true: +The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. +There is an overflow in the Seconds register. +The Target Time Error occurred, that is, programmed target time already elapsed. +If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted. +When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MACTXTSSNR and ETH_MACTXTSSSR registers. +When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the ETH_MACTXTSSNR and ETH_MACTXTSSSR registers, for PTO generated Delay Request and Pdelay request packets. +This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACTSSR register. + 12 + 1 + read-only + + + TXSTSIS + Transmit Status Interrupt +This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the ETH_MACISR register: +Excessive Collision (EXCOL) +Late Collision (LCOL) +Excessive Deferral (EXDEF) +Loss of Carrier (LCARR) +No Carrier (NCARR) +Jabber Timeout (TJT) +This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACISR register. + 13 + 1 + read-only + + + RXSTSIS + Receive Status Interrupt +This bit indicates the status of received packets. This bit is set when the RWT bit is set in the ETH_MACISR register. This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACISR register. + 14 + 1 + read-only + + + + + ETH_MACIER + ETH_MACIER + Interrupt enable register + 0xb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RGSMIIIE + RGMII or SMII Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in ETH_MACISR register. + 0 + 1 + read-write + + + PHYIE + PHY Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in ETH_MACISR register. + 3 + 1 + read-write + + + PMTIE + PMT Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in ETH_MACISR register. + 4 + 1 + read-write + + + LPIIE + LPI Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in ETH_MACISR register. + 5 + 1 + read-write + + + TSIE + Timestamp Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in ETH_MACISR register. + 12 + 1 + read-write + + + TXSTSIE + Transmit Status Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the ETH_MACISR register. + 13 + 1 + read-write + + + RXSTSIE + Receive Status Interrupt Enable +When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the ETH_MACISR register. + 14 + 1 + read-write + + + + + ETH_MACRXTXSR + ETH_MACRXTXSR + Rx Tx status register + 0xb8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the ETH_MACCR register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the ETH_MACCR register. + 0 + 1 + read-only + + + NCARR + No Carrier +When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. + 1 + 1 + read-only + + + LCARR + Loss of Carrier +When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. + 2 + 1 + read-only + + + EXDEF + Excessive Deferral +When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the ETH_MACCR register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000 Mbps mode or when Jumbo packet is enabled). + 3 + 1 + read-only + + + LCOL + Late Collision +When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier Extension in GMII mode). +This bit is not valid if the Underflow error occurs. + 4 + 1 + read-only + + + EXCOL + Excessive Collisions +When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the ETH_MACCR register, this bit is set after the first collision and the packet transmission is aborted. + 5 + 1 + read-only + + + RWT + Receive Watchdog Timeout +This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the ETH_MACCR register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the ETH_MACCR register. + 8 + 1 + read-only + + + + + ETH_MACPCSR + ETH_MACPCSR + 0xc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PWRDWN + Power Down +When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wakeup packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit before the expected magic packet or remote wakeup packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote wakeup Packet Enable bit is set high. +Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When this bit is set, a power management event is generated when the MAC receives a magic packet. + 1 + 1 + read-write + + + RWKPKTEN + Remote wakeup Packet Enable +When this bit is set, a power management event is generated when the MAC receives a remote wakeup packet. + 2 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read. + 5 + 1 + read-only + + + RWKPRCVD + Remote wakeup Packet Received +When this bit is set, it indicates that the power management event is generated because of the reception of a remote wakeup packet. This bit is cleared when this register is read. + 6 + 1 + read-only + + + GLBLUCAST + Global Unicast +When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wakeup packet. + 9 + 1 + read-write + + + RWKPFE + Remote wakeup Packet Forwarding Enable +When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wakeup frame. All frames after that event including the received wakeup frame are forwarded to application. This bit is then self-cleared on receiving the wakeup packet. +The application can also clear this bit before the expected wakeup frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set +high. +Note: If Magic Packet Enable and wakeup Frame Enable are both set along with setting of this bit and Magic Packet is received prior to wakeup frame, this bit is self-cleared on receiving Magic Packet, the received Magic packet is dropped, and all frames after received Magic Packet are forwarded to application. + 10 + 1 + read-write + + + RWKPTR + Remote wakeup FIFO Pointer +This field gives the current value (0 to 7) of the Remote wakeup Packet Filter register pointer. When the value of this pointer is equal to 7, the contents of the Remote wakeup Packet Filter Register are transferred to the eth_mii_rx_clk domain when a Write occurs to that register. + 24 + 5 + read-only + + + RWKFILTRST + Remote wakeup Packet Filter Register Pointer Reset +When this bit is set, the remote wakeup packet filter register pointer is reset to 3'b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + + + ETH_MACRWKPFR + ETH_MACRWKPFR + 0xc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MACRWKPFR + Remote wakeup packet filter +Refer to and for details on register content and programming sequence. + 0 + 32 + read-write + + + + + ETH_MACLCSR + ETH_MACLCSR + LPI control status register + 0xd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TLPIEN + Transmit LPI Entry +When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-only + + + TLPIEX + Transmit LPI Exit +When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-only + + + RLPIEN + Receive LPI Entry +When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. +Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. + 2 + 1 + read-only + + + RLPIEX + Receive LPI Exit +When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. +Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. + 3 + 1 + read-only + + + TLPIST + Transmit LPI State +When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-only + + + RLPIST + Receive LPI State +When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-only + + + LPIEN + LPI Enable +When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission. +This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. +When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down. + 17 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII Receive paths to be used for activating the LPI LS TIMER. +When this bit is set, the MAC uses the link-status bits of the ETH_MACPHYCSR register and the PLS bit for the LPI LS Timer trigger. When this bit is reset, the MAC ignores the link-status bits of the ETH_MACPHYCSR register and takes only the PLS bit. +This bit is RO and reserved if you have not selected the RGMII PHY interface. + 18 + 1 + read-write + + + LPITXA + LPI Tx Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. +If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the core) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of ETH_MTLTxQiOMR, when the MAC is in the LPI mode, it exits the LPI mode. +When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + LPITE + LPI Timer Enable +This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPITE, LPITXA and LPITXEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the ETH_MACLETR register. +After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPITXEN bit. This enables the re-entry into LPI state when it is IDLE again. +When LPITE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPITXEN bit descriptions. + 20 + 1 + read-write + + + + + ETH_MACLTCR + ETH_MACLTCR + LPI timers control register + 0xd4 + 0x20 + 0x03E80000 + 0xFFFFFFFF + + + TWT + LPI TW Timer +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + LST + LPI LS Timer +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + + + ETH_MACLETR + ETH_MACLETR + LPI entry timer register + 0xd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPIET + LPI Entry Timer +This field specifies the time in microseconds the MAC will wait to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. +Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds. + 3 + 17 + read-write + + + + + ETH_MAC1USTCR + ETH_MAC1USTCR + FIXME 1-microsecond-tick counter register + 0xdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIC_1US_CNTR + 1 µs tick Counter +The application must program this counter so that the number of clock cycles of CSR clock is 1 µs. +(Subtract 1 from the value before programming). +For example if the CSR clock is 100 MHz then this field needs to be programmed to +100 - 1 = 99 (which is 0x63). +This is required to generate the 1 µs events that are used to update some of the EEE related counters. + 0 + 12 + read-write + + + + + ETH_MACPHYCSR + ETH_MACPHYCSR + PHYIF control status register + 0xf8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TC + Transmit Configuration in RGMII +When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII port. When this bit is reset, no such information is driven to the PHY (see ). + 0 + 1 + read-write + + + LUD + Link Up or Down +This bit indicates whether the link is up or down during transmission of configuration in the RGMII interface. + 1 + 1 + read-write + + + B_0x0 + Link Down + 0x0 + + + B_0x1 + Link Up + 0x1 + + + + + LNKMOD + Link Mode +This bit indicates the current operating mode of the link: + 16 + 1 + read-only + + + B_0x0 + Half-duplex mode + 0x0 + + + B_0x1 + Full-duplex mode + 0x1 + + + + + LNKSPEED + Link Speed +This bit indicates the current speed of the link: + 17 + 2 + read-only + + + B_0x0 + 2.5 MHz + 0x0 + + + B_0x1 + 25 MHz + 0x1 + + + B_0x2 + 125 MHz + 0x2 + + + + + LNKSTS + Link Status +This bit indicates whether the link is up (1'b1) or down (1'b0). + 19 + 1 + read-only + + + JABTO + Jabber Timeout +This bit indicates the jabber timeout error (1'b1) in the received packet. This bit is reserved when the MAC is configured for the RGMII PHY interface. + 20 + 1 + read-only + + + + + ETH_MACVR + ETH_MACVR + Version register + 0x110 + 0x20 + 0x00001242 + 0xFFFFFFFF + + + SNPSVER + IP version + 0 + 8 + read-only + + + USERVER + ST-defined version + 8 + 8 + read-only + + + + + ETH_MACDR + ETH_MACDR + Debug register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status +When this bit is set, it indicates that the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the Idle state. + 0 + 1 + read-only + + + RFCFCSTS + MAC Receive Packet Controller FIFO Status +When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. + 1 + 2 + read-only + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status +When this bit is set, it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. + 16 + 1 + read-only + + + TFCSTS + MAC Transmit Packet Controller Status +This field indicates the state of the MAC Transmit Packet Controller module: +Status of the previous packet OR +IPG or backoff period to be over + 17 + 2 + read-only + + + B_0x0 + Idle state + 0x0 + + + B_0x1 + Waiting for one of the following: + 0x1 + + + B_0x2 + Generating and transmitting a Pause control packet (in full-duplex mode) + 0x2 + + + B_0x3 + Transferring input packet for transmission + 0x3 + + + + + + + ETH_MACHWF0R + ETH_MACHWF0R + HW feature 0 register + 0x11c + 0x20 + 0x0A0D73F7 + 0xFFFFFFFF + + + MIISEL + 10 or 100 Mbps Support +This bit is set to 1 when 10/100 Mbps is selected as operating mode. + 0 + 1 + read-only + + + GMIISEL + 1000 Mbps Support +This bit is set to 1 when 1000 Mbps is selected as operating mode. + 1 + 1 + read-only + + + HDSEL + Half-duplex Support +This bit is set to 1 when the half-duplex mode is selected + 2 + 1 + read-only + + + PCSSEL + PCS Registers (TBI, SGMII, or RTBI PHY interface) +This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected + 3 + 1 + read-only + + + VLHASH + VLAN Hash Filter Selected +This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected + 4 + 1 + read-only + + + SMASEL + SMA (MDIO) Interface +This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected + 5 + 1 + read-only + + + RWKSEL + PMT Remote Wakeup Packet Enable +This bit is set to 1 when the Enable Remote wakeup Packet Detection option is selected + 6 + 1 + read-only + + + MGKSEL + PMT Magic Packet Enable +This bit is set to 1 when the Enable Magic Packet Detection option is selected + 7 + 1 + read-only + + + MMCSEL + RMON Module Enable +This bit is set to 1 when the Enable MAC management counters (MMC) option is selected + 8 + 1 + read-only + + + ARPOFFSEL + ARP Offload Enabled +This bit is set to 1 when the Enable IPv4 ARP Offload option is selected + 9 + 1 + read-only + + + TSSEL + IEEE 1588-2008 Timestamp Enabled +This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + 12 + 1 + read-only + + + EEESEL + Energy Efficient Ethernet Enabled +This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected + 13 + 1 + read-only + + + TXCOESEL + Transmit Checksum Offload Enabled +This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected + 14 + 1 + read-only + + + RXCOESEL + Receive Checksum Offload Enabled +This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected + 16 + 1 + read-only + + + ADDMACADRSEL + MAC Addresses 1-31 Selected +This bit is set to 1 when the Enable Additional 1-31 MAC Address Registers option is selected + 18 + 5 + read-only + + + MACADR32SEL + MAC Addresses 32-63 Selected +This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected + 23 + 1 + read-only + + + MACADR64SEL + MAC Addresses 64-127 Selected +This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected + 24 + 1 + read-only + + + TSSTSSEL + Timestamp System Time Source +This bit indicates the source of the Timestamp system time: +This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + 25 + 2 + read-only + + + B_0x1 + Internal + 0x1 + + + B_0x2 + External + 0x2 + + + B_0x3 + Both + 0x3 + + + B_0x0 + Reserved, must not be used + 0x0 + + + + + SAVLANINS + Source Address or VLAN Insertion Enable +This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected + 27 + 1 + read-only + + + ACTPHYSEL + Active PHY Selected +When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion: +Others: Reserved, must not be used + 28 + 3 + read-only + + + B_0x0 + GMII or MII + 0x0 + + + B_0x1 + RGMII + 0x1 + + + B_0x2 + SGMII + 0x2 + + + B_0x3 + TBI + 0x3 + + + B_0x4 + RMII + 0x4 + + + B_0x5 + RTBI + 0x5 + + + B_0x6 + SMII + 0x6 + + + + + + + ETH_MACHWF1R + ETH_MACHWF1R + HW feature 1 register + 0x120 + 0x20 + 0x11041904 + 0xFFFFFFFF + + + RXFIFOSIZE + MTL Receive FIFO Size +This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: + 0 + 5 + read-only + + + B_0x0 + 128 bytes + 0x0 + + + B_0x1 + 256 bytes + 0x1 + + + B_0x2 + 512 bytes + 0x2 + + + B_0x3 + 1,024 bytes + 0x3 + + + B_0x4 + 2,048 bytes + 0x4 + + + B_0x5 + 4,096 bytes + 0x5 + + + B_0x6 + 8,192 bytes + 0x6 + + + B_0x7 + 16,384 bytes + 0x7 + + + B_0x8 + 32 Kbytes + 0x8 + + + B_0x9 + 64 Kbytes + 0x9 + + + B_0xA + 128 Kbytes + 0xA + + + B_0xB + 256 Kbytes + 0xB + + + B_0xc + Reserved, must not be used + 0xc + + + B_0xd + Reserved, must not be used + 0xd + + + B_0xe + Reserved, must not be used + 0xe + + + B_0xf + Reserved, must not be used + 0xf + + + B_0x10 + Reserved, must not be used + 0x10 + + + B_0x11 + Reserved, must not be used + 0x11 + + + B_0x12 + Reserved, must not be used + 0x12 + + + B_0x13 + Reserved, must not be used + 0x13 + + + B_0x14 + Reserved, must not be used + 0x14 + + + B_0x15 + Reserved, must not be used + 0x15 + + + B_0x16 + Reserved, must not be used + 0x16 + + + B_0x17 + Reserved, must not be used + 0x17 + + + B_0x18 + Reserved, must not be used + 0x18 + + + B_0x19 + Reserved, must not be used + 0x19 + + + B_0x1a + Reserved, must not be used + 0x1a + + + B_0x1b + Reserved, must not be used + 0x1b + + + B_0x1c + Reserved, must not be used + 0x1c + + + B_0x1d + Reserved, must not be used + 0x1d + + + B_0x1e + Reserved, must not be used + 0x1e + + + B_0x1f + Reserved, must not be used + 0x1f + + + + + TXFIFOSIZE + MTL Transmit FIFO Size +This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: + 6 + 5 + read-only + + + B_0x0 + 128 bytes + 0x0 + + + B_0x1 + 256 bytes + 0x1 + + + B_0x2 + 512 bytes + 0x2 + + + B_0x3 + 1,024 bytes + 0x3 + + + B_0x4 + 2,048 bytes + 0x4 + + + B_0x5 + 4,096 bytes + 0x5 + + + B_0x6 + 8,192 bytes + 0x6 + + + B_0x7 + 16,384 bytes + 0x7 + + + B_0x8 + 32 Kbytes + 0x8 + + + B_0x9 + 64 Kbytes + 0x9 + + + B_0xA + 128 Kbytes + 0xA + + + B_0xb + Reserved, must not be used + 0xb + + + B_0xc + Reserved, must not be used + 0xc + + + B_0xd + Reserved, must not be used + 0xd + + + B_0xe + Reserved, must not be used + 0xe + + + B_0xf + Reserved, must not be used + 0xf + + + B_0x10 + Reserved, must not be used + 0x10 + + + B_0x11 + Reserved, must not be used + 0x11 + + + B_0x12 + Reserved, must not be used + 0x12 + + + B_0x13 + Reserved, must not be used + 0x13 + + + B_0x14 + Reserved, must not be used + 0x14 + + + B_0x15 + Reserved, must not be used + 0x15 + + + B_0x16 + Reserved, must not be used + 0x16 + + + B_0x17 + Reserved, must not be used + 0x17 + + + B_0x18 + Reserved, must not be used + 0x18 + + + B_0x19 + Reserved, must not be used + 0x19 + + + B_0x1a + Reserved, must not be used + 0x1a + + + B_0x1b + Reserved, must not be used + 0x1b + + + B_0x1c + Reserved, must not be used + 0x1c + + + B_0x1d + Reserved, must not be used + 0x1d + + + B_0x1e + Reserved, must not be used + 0x1e + + + B_0x1f + Reserved, must not be used + 0x1f + + + + + OSTEN + One-Step Timestamping Enable +This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. + 11 + 1 + read-only + + + PTOEN + PTP Offload Enable +This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. + 12 + 1 + read-only + + + ADVTHWORD + IEEE 1588 High Word Register Enable +This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected + 13 + 1 + read-only + + + ADDR64 + Address width +This field indicates the configured address width. +Others: Reserved, must not be used + 14 + 2 + read-only + + + B_0x0 + 32 bits + 0x0 + + + + + DCBEN + DCB Feature Enable +This bit is set to 1 when the Enable Data Center Bridging option is selected + 16 + 1 + read-only + + + SPHEN + Split Header Feature Enable +This bit is set to 1 when the Enable Split Header Structure option is selected + 17 + 1 + read-only + + + TSOEN + TCP Segmentation Offload Enable +This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected + 18 + 1 + read-only + + + DBGMEMA + DMA Debug Registers Enable +This bit is set to 1 when the Debug Mode Enable option is selected + 19 + 1 + read-only + + + AVSEL + AV Feature Enable +This bit is set to 1 when the Enable Audio Video Bridging option is selected. + 20 + 1 + read-only + + + HASHTBLSZ + Hash Table Size +This field indicates the size of the Hash table: + 24 + 2 + read-only + + + B_0x0 + No Hash table + 0x0 + + + B_0x1 + 64 + 0x1 + + + B_0x2 + 128 + 0x2 + + + B_0x3 + 256 + 0x3 + + + + + L3L4FNUM + Total number of L3 or L4 Filters +This field indicates the total number of L3 or L4 filters: +.. + 27 + 4 + read-only + + + B_0x0 + No L3 or L4 Filter + 0x0 + + + B_0x1 + 1 L3 or L4 Filter + 0x1 + + + B_0x2 + 2 L3 or L4 Filters + 0x2 + + + B_0x8 + 8 L3 or L4 + 0x8 + + + + + + + ETH_MACHWF2R + ETH_MACHWF2R + HW feature 2 register + 0x124 + 0x20 + 0x41040041 + 0xFFFFFFFF + + + RXQCNT + Number of MTL Receive Queues +This field indicates the number of MTL Receive queues: +.. + 0 + 4 + read-only + + + B_0x0 + 1 MTL Rx queue + 0x0 + + + B_0x1 + 2 MTL Rx queues + 0x1 + + + B_0x7 + 8 MTL Rx + 0x7 + + + + + TXQCNT + Number of MTL Transmit Queues +This field indicates the number of MTL Transmit queues: +.. + 6 + 4 + read-only + + + B_0x0 + 1 MTL Tx queue + 0x0 + + + B_0x1 + 2 MTL Tx queues + 0x1 + + + B_0x7 + 8 MTL Tx + 0x7 + + + + + RXCHCNT + Number of DMA Receive Channels +This field indicates the number of DMA Receive channels: +.. + 12 + 4 + read-only + + + B_0x0 + 1 DMA Rx Channel + 0x0 + + + B_0x1 + 2 DMA Rx Channels + 0x1 + + + B_0x7 + 8 DMA Rx + 0x7 + + + + + TXCHCNT + Number of DMA Transmit Channels +This field indicates the number of DMA Transmit channels: +.. + 18 + 4 + read-only + + + B_0x0 + 1 DMA Tx Channel + 0x0 + + + B_0x1 + 2 DMA Tx Channels + 0x1 + + + B_0x7 + 8 DMA Tx + 0x7 + + + + + PPSOUTNUM + Number of PPS Outputs +This field indicates the number of PPS outputs: + 24 + 3 + read-only + + + B_0x0 + No PPS output + 0x0 + + + B_0x1 + 1 PPS output + 0x1 + + + B_0x2 + 2 PPS outputs + 0x2 + + + B_0x3 + 3 PPS outputs + 0x3 + + + B_0x4 + 4 PPS outputs + 0x4 + + + B_0x5 + Reserved, must not be used + 0x5 + + + B_0x6 + Reserved, must not be used + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + + + AUXSNAPNUM + Number of Auxiliary Snapshot Inputs +This field indicates the number of auxiliary snapshot inputs: + 28 + 3 + read-only + + + B_0x0 + No auxiliary input + 0x0 + + + B_0x1 + 1 auxiliary input + 0x1 + + + B_0x2 + 2 auxiliary inputs + 0x2 + + + B_0x3 + 3 auxiliary inputs + 0x3 + + + B_0x4 + 4 auxiliary inputs + 0x4 + + + B_0x5 + Reserved, must not be used + 0x5 + + + B_0x6 + Reserved, must not be used + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + + + + + ETH_MACHWF3R + ETH_MACHWF3R + HW feature 3 register + 0x128 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + NRVF + Number of Extended VLAN Tag Filters Enabled +This field indicates the Number of Extended VLAN Tag Filters selected: + 0 + 3 + read-only + + + B_0x0 + No Extended Rx VLAN Filters + 0x0 + + + B_0x1 + 4 Extended Rx VLAN Filters + 0x1 + + + B_0x2 + 8 Extended Rx VLAN Filters + 0x2 + + + B_0x3 + 16 Extended Rx VLAN Filters + 0x3 + + + B_0x4 + 24 Extended Rx VLAN Filters + 0x4 + + + B_0x5 + 32 Extended Rx VLAN Filters + 0x5 + + + B_0x6 + Reserved, must not be used + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + + + CBTISEL + Queue/Channel based VLAN tag insertion on Tx enable +This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx feature is selected. + 4 + 1 + read-write + + + DVLAN + Number of auxiliary snapshot inputs +This field indicates the number of auxiliary snapshot inputs /*FIXME enum values removed for the moment */ + 5 + 1 + read-write + + + + + ETH_MACMDIOAR + ETH_MACMDIOAR + MDIO address register + 0x200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GB + GMII Busy +The application sets this bit to instruct the SMA to initiate a Read or Write +access to the MDIOS. The MAC clears this bit after the MDIO frame +transfer is completed. Hence the software must not write or change any of the +fields in ETH_MACMDIOAR and ETH_MACMDIODR registers as long as this +bit is set. +For write transfers, the application must first write 16-bit data in the GD field (and also RA field when C45E is set) in ETH_MACMDIODR register before +setting this bit. When C45E is set, it should also write into the RA field of +ETH_MACMDIODR register before initiating a read transfer. When a read +transfer is completed (GMII busy=0), the data read from the PHY register is valid in +the GD field of the ETH_MACMDIODR register. +Note: Even if the addressed PHY is not present, there is no change in the +functionality of this bit. + 0 + 1 + read-write + + + C45E + Clause 45 PHY Enable +When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO. + 1 + 1 + read-write + + + GOC + GMII Operation Command +This bit indicates the operation command to the PHY. +When Clause 22 PHY is enabled, only Write and Read commands are valid. + 2 + 2 + read-write + + + B_0x0 + Reserved, must not be used + 0x0 + + + B_0x1 + Write + 0x1 + + + B_0x2 + Post Read Increment Address for Clause 45 PHY + 0x2 + + + B_0x3 + Read + 0x3 + + + + + SKAP + Skip Address Packet +When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set. + 4 + 1 + read-write + + + CR + CSR Clock Range +The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: +The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. +When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: + 8 + 4 + read-write + + + B_0x0 + CSR clock = 60-100 MHz; MDC clock = CSR clock/42 + 0x0 + + + B_0x1 + CSR clock = 100-150 MHz; MDC clock = CSR clock/62 + 0x1 + + + B_0x2 + CSR clock = 20-35 MHz; MDC clock = CSR clock/16 + 0x2 + + + B_0x3 + CSR clock = 35-60 MHz; MDC clock = CSR clock/26 + 0x3 + + + B_0x4 + CSR clock = 150-250 MHz; MDC clock = CSR clock/102 + 0x4 + + + B_0x5 + CSR clock = 250-300 MHz; MDC clock = CSR clock/124 + 0x5 + + + B_0x6 + Reserved, must not be used + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + B_0x8 + CSR clock/4 + 0x8 + + + B_0x9 + CSR clock/6 + 0x9 + + + B_0xA + CSR clock/8 + 0xA + + + B_0xB + CSR clock/10 + 0xB + + + B_0xC + CSR clock/12 + 0xC + + + B_0xD + CSR clock/14 + 0xD + + + B_0xE + CSR clock/16 + 0xE + + + B_0xF + CSR clock/18 + 0xF + + + + + NTC + Number of Training Clocks +This field controls the number of trailing clock cycles generated on ETH_MDC after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 3'h3 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer. + 12 + 3 + read-write + + + RDA + Register/Device Address +These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY. + 16 + 5 + read-write + + + PA + Physical Layer Address +This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing. + 21 + 5 + read-write + + + BTB + Back to Back transactions +When this bit is set and the NTC has value greater than 0, then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which will be executed immediately irrespective of the number trailing clocks generated for the previous frame. +When this bit is reset, then the read/write command completion (GMII busy is cleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. +This bit must not be set when NTC=0. + 26 + 1 + read-write + + + PSE + Preamble Suppression Enable +When this bit is set, the SMA will suppress the 32-bit preamble and transmit MDIO frames with only 1 preamble bit. +When this bit is 0, the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. + 27 + 1 + read-write + + + + + ETH_MACMDIODR + ETH_MACMDIODR + MDIO data register + 0x204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GD + GMII Data +This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. + 0 + 16 + read-write + + + RA + Register Address +This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for. + 16 + 16 + read-write + + + + + ETH_MACARPAR + ETH_MACARPAR + ARP address register + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ARPPA + ARP Protocol Address +This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet. + 0 + 32 + read-write + + + + + ETH_MACCSRSWCR + ETH_MACCSRSWCR + CSR software control register + 0x230 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RCWE + Register Clear on Write 1 Enable +When this bit is set, the access mode to some register fields changes to rc_w1 (clear on write) meaning that the application needs to set that respective bit to 1 to clear it. +When this bit is reset, the access mode to these register fields remains rc_r (clear on read). + 0 + 1 + read-write + + + SEEN + Slave Error Response Enable +When this bit is set, the MAC responds with a Slave Error for accesses to reserved registers in CSR space. +When this bit is reset, the MAC responds with an Okay response to any register accessed from CSR space. + 8 + 1 + read-write + + + + + ETH_MACA0HR + ETH_MACA0HR + Address 0 high register + 0x300 + 0x20 + 0x8000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address0[47:32] +This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. + 0 + 16 + read-write + + + AE + Address Enable +This bit is always set to 1. + 31 + 1 + read-only + + + + + ETH_MACA0LR + ETH_MACA0LR + Address 0 low register + 0x304 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address x [31:0] (x = 0 to 3) +This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. + 0 + 32 + read-write + + + + + ETH_MACA1HR + ETH_MACA1HR + Address 1 high register + 0x308 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. + 0 + 16 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: +Bit 29: Register 194[15:8] +Bit 28: Register 194[7:0] +Bit 27: Register 195[31:24] +.. +Bit 24: Register 195[7:0] +You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. + 30 + 1 + read-write + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + + + ETH_MACA1LR + ETH_MACA1LR + Address 1 low register + 0x30c + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address x [31:0] (x = 0 to 3) +This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. + 0 + 32 + read-write + + + + + ETH_MACA2HR + ETH_MACA2HR + Address 2 high register + 0x310 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. + 0 + 16 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: +Bit 29: Register 194[15:8] +Bit 28: Register 194[7:0] +Bit 27: Register 195[31:24] +.. +Bit 24: Register 195[7:0] +You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. + 30 + 1 + read-write + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + + + ETH_MACA2LR + ETH_MACA2LR + Address 2 low register + 0x314 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address x [31:0] (x = 0 to 3) +This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. + 0 + 32 + read-write + + + + + ETH_MACA3HR + ETH_MACA3HR + Address 3 high register + 0x318 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. + 0 + 16 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: +Bit 29: Register 194[15:8] +Bit 28: Register 194[7:0] +Bit 27: Register 195[31:24] +.. +Bit 24: Register 195[7:0] +You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. + 30 + 1 + read-write + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + + + ETH_MACA3LR + ETH_MACA3LR + Address 3 low register + 0x31c + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address x [31:0] (x = 0 to 3) +This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. + 0 + 32 + read-write + + + + + ETH_MMC_CONTROL + ETH_MMC_CONTROL + MMC control register + 0x700 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. + 0 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. +Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. +This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2Kbytes) and all packet-counters get preset to 0x7FFF_FFF0 (Half 16). +When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2Kbytes) and all packet-counters get preset to 0xFFFF_FFF0 (Full 16). +For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + UCDBC + Update MMC Counters for Dropped Broadcast Packets +The CNTRST bit has a higher priority than the CNTPRST bit. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST bit is not set. +When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of ETH_MACPFR register. +When reset, the MMC Counters are not updated for dropped Broadcast packets. + 8 + 1 + read-write + + + + + ETH_MMC_RX_INTERRUPT + ETH_MMC_RX_INTERRUPT + MMC Rx interrupt register + 0x704 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXCRCERPIS + MMC Receive CRC Error Packet Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-only + + + RXALGNERPIS + MMC Receive Alignment Error Packet Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-only + + + RXUCGPIS + MMC Receive Unicast Good Packet Counter Interrupt Status +This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-only + + + RXLPIUSCIS + MMC Receive LPI microsecond counter interrupt status +This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-only + + + RXLPITRCIS + MMC Receive LPI transition counter interrupt status +This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-only + + + + + ETH_MMC_TX_INTERRUPT + ETH_MMC_TX_INTERRUPT + MMC Tx interrupt register + 0x708 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXSCOLGPIS + MMC Transmit Single Collision Good Packet Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-only + + + TXMCOLGPIS + MMC Transmit Multiple Collision Good Packet Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-only + + + TXGPKTIS + MMC Transmit Good Packet Counter Interrupt Status +This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-only + + + TXLPIUSCIS + MMC Transmit LPI microsecond counter interrupt status +This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-only + + + TXLPITRCIS + MMC Transmit LPI transition counter interrupt status +This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-only + + + + + ETH_MMC_RX_INTERRUPT_MASK + ETH_MMC_RX_INTERRUPT_MASK + MMC Rx interrupt mask register + 0x70c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXCRCERPIM + MMC Receive CRC Error Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXALGNERPIM + MMC Receive Alignment Error Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXUCGPIM + MMC Receive Unicast Good Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXLPIUSCIM + MMC Receive LPI microsecond counter interrupt Mask +Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXLPITRCIM + MMC Receive LPI transition counter interrupt Mask +Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-only + + + + + ETH_MMC_TX_INTERRUPT_MASK + ETH_MMC_TX_INTERRUPT_MASK + MMC Tx interrupt mask register + 0x710 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXSCOLGPIM + MMC Transmit Single Collision Good Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXMCOLGPIM + MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXGPKTIM + MMC Transmit Good Packet Counter Interrupt Mask +Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXLPIUSCIM + MMC Transmit LPI microsecond counter interrupt Mask +Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + TXLPITRCIM + MMC Transmit LPI transition counter interrupt Mask +Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-only + + + + + ETH_TX_SINGLE_COLLISION_GOOD_PACKETS + ETH_TX_SINGLE_COLLISION_GOOD_PACKETS + Tx single collision good packets register + 0x74c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXSNGLCOLG + Tx Single Collision Good Packets +This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode. + 0 + 32 + read-only + + + + + ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS + ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS + Tx multiple collision good packets register + 0x750 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXMULTCOLG + Tx Multiple Collision Good Packets +This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode. + 0 + 32 + read-only + + + + + ETH_TX_PACKET_COUNT_GOOD + ETH_TX_PACKET_COUNT_GOOD + Tx packet count good register + 0x768 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXPKTG + Tx Packet Count Good +This field indicates the number of good packets transmitted. + 0 + 32 + read-only + + + + + ETH_RX_CRC_ERROR_PACKETS + ETH_RX_CRC_ERROR_PACKETS + Rx CRC error packets register + 0x794 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXCRCERR + Rx CRC Error Packets +This field indicates the number of packets received with CRC error. + 0 + 32 + read-only + + + + + ETH_RX_ALIGNMENT_ERROR_PACKETS + ETH_RX_ALIGNMENT_ERROR_PACKETS + Rx alignment error packets register + 0x798 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXALGNERR + Rx Alignment Error Packets +This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode. + 0 + 32 + read-only + + + + + ETH_RX_UNICAST_PACKETS_GOOD + ETH_RX_UNICAST_PACKETS_GOOD + Rx unicast packets good register + 0x7c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXUCASTG + Rx Unicast Packets Good +This field indicates the number of good unicast packets received. + 0 + 32 + read-only + + + + + ETH_TX_LPI_USEC_CNTR + ETH_TX_LPI_USEC_CNTR + Tx LPI microsecond timer register + 0x7ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXLPIUSC + Tx LPI Microseconds Counter +This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. + 0 + 32 + read-only + + + + + ETH_TX_LPI_TRAN_CNTR + ETH_TX_LPI_TRAN_CNTR + Tx LPI transition counter register + 0x7f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXLPITRC + Tx LPI Transition counter +This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register), the counter will increment. + 0 + 32 + read-only + + + + + ETH_RX_LPI_USEC_CNTR + ETH_RX_LPI_USEC_CNTR + Rx LPI microsecond counter register + 0x7f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXLPIUSC + Rx LPI Microseconds Counter +This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. + 0 + 32 + read-only + + + + + ETH_RX_LPI_TRAN_CNTR + ETH_RX_LPI_TRAN_CNTR + Rx LPI transition counter register + 0x7f8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXLPITRC + Rx LPI Transition counter +This field indicates the number of times Rx LPI Entry has occurred. + 0 + 32 + read-only + + + + + ETH_MACL3L4C0R + ETH_MACL3L4C0R + L3 and L4 control 0 register + 0x900 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3PEN0 + Layer 3 Protocol Enable +When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. +The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. + 0 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. +Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. + 2 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. +This bit is valid and applicable only when the L3SAM0 bit is set. + 3 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. +Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. +This bit is valid and applicable only when the L3DAM0 bit is set high. + 5 + 1 + read-write + + + L3HSBM0 + Layer 3 IP SA higher bits match +This field contains the number of lower bits of IP source address that are masked for matching in the IPv4 packets. The following list describes the values of this field: +2: Two LSbs [1:0] are masked +.. +31: All bits except MSb are masked. +IPv6 Packets: +This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP source or destination address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. + 6 + 5 + read-write + + + B_0x0 + No bits are masked. + 0x0 + + + B_0x1 + LSb[0] is masked + 0x1 + + + + + L3HDBM0 + Layer 3 IP DA higher bits match +IPv4 Packets: +For IPv4 packets, this field contains the number of higher bits of IP Destination Address that are masked in the IPv4 packets. Number of bits masked for matching goes from 0 (No bit is masked) to 31 (All bits except MSb are masked) +For IPv6 packets, bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. Number of bits masked is given by concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits from 0 (No bit is masked) to 127 (All bits except MSb are masked) +This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set. + 11 + 5 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. +The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. + 16 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. +This bit is valid and applicable only when the L4SPM0 bit is set high. + 19 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable +When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable +When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. +This bit is valid and applicable only when the L4DPM0 bit is set high. + 21 + 1 + read-write + + + + + ETH_MACL4A0R + ETH_MACL4A0R + 0x904 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L4SP0 + Layer 4 Source Port Number Field +When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. +When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. + 0 + 16 + read-write + + + L4DP0 + Layer 4 Destination Port Number Field +When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. +When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. + 16 + 16 + read-write + + + + + ETH_MACL3A00R + ETH_MACL3A00R + Layer 3 Address 0 filter 0 register + 0x910 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets. + 0 + 32 + read-write + + + + + ETH_MACL3A10R + ETH_MACL3A10R + Layer3 address 1 filter 0 register + 0x914 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. + 0 + 32 + read-write + + + + + ETH_MACL3A20R + ETH_MACL3A20R + Layer3 Address 2 filter 0 register + 0x918 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. + 0 + 32 + read-write + + + + + ETH_MACL3A30R + ETH_MACL3A30R + Layer3 Address 3 filter 0 register + 0x91c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. + 0 + 32 + read-write + + + + + ETH_MACL3L4C1R + ETH_MACL3L4C1R + L3 and L4 control 1 register + 0x930 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3PEN1 + Layer 3 Protocol Enable +When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. +The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. + 0 + 1 + read-write + + + L3SAM1 + Layer 3 IP SA Match Enable +When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. +Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. + 2 + 1 + read-write + + + L3SAIM1 + Layer 3 IP SA Inverse Match Enable +When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. +This bit is valid and applicable only when the L3SAM0 bit is set. + 3 + 1 + read-write + + + L3DAM1 + Layer 3 IP DA Match Enable +When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. +Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3DAIM1 + Layer 3 IP DA Inverse Match Enable +When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. +This bit is valid and applicable only when the L3DAM0 bit is set high. + 5 + 1 + read-write + + + L3HSBM1 + Layer 3 IP SA Higher Bits Match +IPv4 Packets: +This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: +2: Two LSbs [1:0] are masked +.. +31: All bits except MSb are masked. +IPv6 Packets: +This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. + 6 + 5 + read-write + + + B_0x0 + No bits are masked. + 0x0 + + + B_0x1 + LSb[0] is masked + 0x1 + + + + + L3HDBM1 + Layer 3 IP DA higher bits match +This field contains the number of lower bits of IP destination address that are masked for matching in the IPv4 packets. The following list describes the values of this field: +2: Two LSbs [1:0] are masked +.. +31: All bits except MSb are masked. +IPv6 Packets: +This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP source or destination address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high.IPv4 Packets: + 11 + 5 + read-write + + + B_0x0 + No bits are masked. + 0x0 + + + B_0x1 + LSb[0] is masked + 0x1 + + + + + L4PEN1 + Layer 4 Protocol Enable +When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. +The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. + 16 + 1 + read-write + + + L4SPM1 + Layer 4 Source Port Match Enable +When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4SPIM1 + Layer 4 Source Port Inverse Match Enable +When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. +This bit is valid and applicable only when the L4SPM0 bit is set high. + 19 + 1 + read-write + + + L4DPM1 + Layer 4 Destination Port Match Enable +When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4DPIM1 + Layer 4 Destination Port Inverse Match Enable +When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. +This bit is valid and applicable only when the L4DPM0 bit is set high. + 21 + 1 + read-write + + + + + ETH_MACL4A1R + ETH_MACL4A1R + 0x934 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L4SP1 + Layer 4 Source Port Number Field +When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. +When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. + 0 + 16 + read-write + + + L4DP1 + Layer 4 Destination Port Number Field +When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. +When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. + 16 + 16 + read-write + + + + + ETH_MACL3A01R + ETH_MACL3A01R + Layer3 address 0 filter 1 Register + 0x940 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A01 + Layer 3 Address 0 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets. + 0 + 32 + read-write + + + + + ETH_MACL3A11R + ETH_MACL3A11R + Layer3 address 1 filter 1 register + 0x944 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A11 + Layer 3 Address 1 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. + 0 + 32 + read-write + + + + + ETH_MACL3A21R + ETH_MACL3A21R + Layer3 address 2 filter 1 Register + 0x948 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A21 + Layer 3 Address 2 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. + 0 + 32 + read-write + + + + + ETH_MACL3A31R + ETH_MACL3A31R + Layer3 address 3 filter 1 register + 0x94c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + L3A31 + Layer 3 Address 3 Field +When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. +When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. +When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. + 0 + 32 + read-write + + + + + ETH_MACTSCR + ETH_MACTSCR + Timestamp control Register + 0xb00 + 0x20 + 0x00002000 + 0xFFFFFFFF + + + TSENA + Enable Timestamp +When this bit is set, the timestamp is added for Transmit and Receive packets. When disabled, timestamp is not added for transmit and receive packets and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. +On the Receive side, the MAC processes the 1588 packets only if this bit is set. + 0 + 1 + read-write + + + TSCFUPDT + Fine or Coarse Timestamp Update +When this bit is set, the Fine method is used to update system timestamp. When this bit is reset, Coarse method is used to update the system timestamp. + 1 + 1 + read-write + + + TSINIT + Initialize Timestamp +When this bit is set, the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update Register) and MAC Register 81 (System Time Nanoseconds Update Register). +This bit should be zero before it is updated. This bit is reset when the initialization is complete. + 2 + 1 + read-write + + + TSUPDT + Update Timestamp +When this bit is set, the system time is updated (added or subtracted) with the value specified in ETH_MACSTSUR and ETH_MACSTNUR. +This bit should be zero before updating it. This bit is reset when the update is complete in hardware. + 3 + 1 + read-write + + + TSADDREG + Update Addend Register +When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. + 5 + 1 + read-write + + + TSENALL + Enable Timestamp for All Packets +When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. + 8 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment must be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSVER2ENA + Enable PTP Packet Processing for Version 2 Format +When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset, the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588 formats are described in 'PTP Processing and Control'. + 10 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Packets +When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset, the MAC ignores the PTP over Ethernet packets. + 11 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Packets Sent over IPv6-UDP +When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear, the MAC ignores the PTP transported over IPv6-UDP packets. + 12 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Packets Sent over IPv4-UDP +When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset, the MAC ignores the PTP transported over IPv4-UDP packets. This bit is set by default. + 13 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When this bit is reset, the snapshot is taken for all messages except Announce, Management, and Signaling. For more information about the timestamp snapshots, see Timestamp Snapshot Dependency on Register Bits Table. + 14 + 1 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots +These bits, along with Bits 15 and 14, decide the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Timestamp Snapshot Dependency on Register Bits Table. + 16 + 2 + read-write + + + TSENMACADDR + Enable MAC Address for PTP Packet Filtering +When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. +When this bit is set, received PTP packets with DA containing a special multicast or unicast address that matches the one programmed in MAC address registers are considered for processing as indicated below, when PTP is directly sent over Ethernet. +For normal time stamping operation, MAC address registers 0 to 31 is considered for unicast destination address matching. +For PTP offload, only MAC address register 0 is considered for unicast destination address matching. + 18 + 1 + read-write + + + CSC + Enable checksum correction during OST for PTP over UDP/IPv4 packets +When this bit is set, the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct, for changes made to origin timestamp and/or correction field as part of one step timestamp operation. The application shall form the packet with these two dummy bytes. +When reset, no updates are done to keep the UDP checksum correct. The application shall form the packet with UDP checksum set to 0. + 19 + 1 + read-only + + + TXTSSTSM + Transmit Timestamp Status Mode +When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSTSMIS bit of the ETH_MACTXTSSNR register. +When this bit is reset, the MAC ignores the timestamp status of current packet if the timestamp status of previous packet is not read by the software. The MAC indicates this by setting the TXTSSTSHI bit of the ETH_MACTXTSSSR register. + 24 + 1 + read-write + + + + + ETH_MACSSIR + ETH_MACSSIR + Sub-second increment register + 0xb04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when the PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in ETH_MACTSCR]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465 ns. In this case, you should program a value of 43 (0x2B) which is derived by 20 ns/0.465. + 16 + 8 + read-write + + + + + ETH_MACSTSR + ETH_MACSTSR + System time seconds register + 0xb08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second +The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-only + + + + + ETH_MACSTNR + ETH_MACSTNR + System time nanoseconds register + 0xb0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub-seconds +The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When Bit 9 is set in ETH_MACTSCR, each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to zero. + 0 + 31 + read-only + + + + + ETH_MACSTSUR + ETH_MACSTSUR + System time seconds update register + 0xb10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Seconds +The value in this field is the sub-second part of the update. When ADDSUB is reset, this field must be programmed with the sub-second part of the update value, with an accuracy based on the TSCTRLSSR bit of the ETH_MACTSCR register. When ADDSUB is set, then this field must be programmed with the complement of the sub-second part of the update value as described below. +When TSCTRLSSR is set, then the programmed value must be 10^9 - <sub-second value>. When TSCTRLSSR is reset, then the programmed value must be 2^31 - <sub-second_value> +For example, when TSCTRLSSR bit is set and if 2.000000001 seconds need to be subtracted from the system time, then the TSS field in the MAC_Timestamp Seconds update register must be 0xFFFF_FFFE (that is, 2^32 - 2), ADDSUB bit in this register should be set, and the TSSS field must be 0x3B9A_C9FF (that is, 10^9 - 1). + 0 + 32 + read-write + + + + + ETH_MACSTNUR + ETH_MACSTNUR + 0xb14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub-seconds +The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When the TSCTRLSSR bit is set in the ETH_MACTSCR register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + ADDSUB + Add or Subtract Time +When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + + + ETH_MACTSAR + ETH_MACTSAR + Timestamp addend register + 0xb18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + ETH_MACTSSR + ETH_MACTSSR + Timestamp status register + 0xb20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSSOVF + Timestamp Seconds Overflow +When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. + 0 + 1 + read-only + + + TSTARGT0 + Timestamp Target Time Reached +When set, this bit indicates that the value of system time is greater than or equal to the value specified in the ETH_MACPPS_Target_Time_seconds and ETH_MACPPS_Target_Time_Nanoseconds registers. + 1 + 1 + read-only + + + AUXTSTRIG + Auxiliary Timestamp Trigger Snapshot +This bit is set high when the auxiliary snapshot is written to the FIFO. + 2 + 1 + read-only + + + TSTRGTERR0 + Timestamp Target Time Error +This bit is set when the latest target time programmed in the ETH_MACPPS_Target_Time_seconds and ETH_MACPPS_Target_Time_Nanoseconds +registers elapses. This bit is cleared when the application reads this bit. + 3 + 1 + read-only + + + TXTSSIS + Tx Timestamp Status Interrupt Status +When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MACTXTSSNR and ETH_MACTXTSSSR registers. +When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the ETH_MACTXTSSNR and ETH_MACTXTSSSR registers, for PTO generated Delay Request and Pdelay request packets. +This bit is cleared when the ETH_MACTXTSSSR register is read. +This bit is reserved in all other configurations. + 15 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: +Bit 16: Auxiliary trigger 0 +Bit 17: Auxiliary trigger 1 +Bit 18: Auxiliary trigger 2 +Bit 19: Auxiliary trigger 3 +The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed +This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. + 24 + 1 + read-only + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. + 25 + 5 + read-only + + + + + ETH_MACTXTSSNR + ETH_MACTXTSSNR + Tx timestamp status nanoseconds register + 0xb30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXTSSLO + Transmit Timestamp Status Low +This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp. + 0 + 31 + read-only + + + TXTSSMIS + Transmit Timestamp Status Missed +When this bit is set, it indicates one of the following: +The timestamp of the current packet is ignored if TXTSSTSM bit of the ETH_MACTSCR register is reset +The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the ETH_MACTSCR register is set. + 31 + 1 + read-only + + + + + ETH_MACTXTSSSR + ETH_MACTXTSSSR + Tx timestamp status seconds register + 0xb34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXTSSHI + Transmit Timestamp Status High +This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp. + 0 + 32 + read-only + + + + + ETH_MACACR + ETH_MACACR + Auxiliary control register + 0xb40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, the auxiliary snapshots are stored in the FIFO. + 0 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg0 input is enabled. When this bit is reset, the events on this input are ignored. + 4 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg1 input is enabled. When this bit is reset, the events on this input are ignored. + 5 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg2 input is enabled. When this bit is reset, the events on this input are ignored. + 6 + 1 + read-write + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg3 input is enabled. When this bit is reset, the events on this input are ignored. + 7 + 1 + read-write + + + + + ETH_MACATSNR + ETH_MACATSNR + Auxiliary timestamp nanoseconds register + 0xb48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AUXTSLO + Auxiliary Timestamp +Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. + 0 + 31 + read-only + + + + + ETH_MACATSSR + ETH_MACATSSR + Auxiliary timestamp seconds register + 0xb4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Auxiliary Timestamp +Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-only + + + + + ETH_MACTSIACR + ETH_MACTSIACR + Timestamp Ingress asymmetric correction register + 0xb50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSTIAC + One-Step Timestamp Ingress Asymmetry Correction +This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For example, 2.5 ns is represented as 0x00028000. +The value can also be negative, which is represented in 2's complement form with bit 31 representing the sign bit. + 0 + 32 + read-write + + + + + ETH_MACTSEACR + ETH_MACTSEACR + Timestamp Egress asymmetric correction register + 0xb54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSTEAC + One-Step Timestamp Egress Asymmetry Correction +This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied by 2^16. +For example, if the required correction is +2.5 ns, the programmed value must be 0xFFFD_8000, which is the 2's complement of 0x0002_8000(2.5 * 216). Similarly, if the required correction is -3.3 ns, the programmed value is 0x0003_4CCC (3.3 * 216). + 0 + 32 + read-write + + + + + ETH_MACTSICNR + ETH_MACTSICNR + Timestamp Ingress correction nanosecond register + 0xb58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSIC + Timestamp Ingress Correction +This field contains the ingress path correction value as defined by the Ingress Correction expression. + 0 + 32 + read-write + + + + + ETH_MACTSECNR + ETH_MACTSECNR + Timestamp Egress correction nanosecond register + 0xb5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSEC + Timestamp Egress Correction +This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression. + 0 + 32 + read-write + + + + + ETH_MACPPSCR + ETH_MACPPSCR + PPS control register + 0xb70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPSCTRL + PPS Output Frequency Control +This field controls the frequency of the PPS output (eth_ptp_pps_out) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +.. +Note: In the binary rollover mode, the PPS output (eth_ptp_pps_out) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: +When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms +When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of +One clock of 50 percent duty cycle and 537 ms period +Second clock of 463 ms period (268 ms low and 195 ms high) +When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of +Three clocks of 50 percent duty cycle and 268 ms period +Fourth clock of 195 ms period (134 ms low and 61 ms high) +This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MACSTNR register. + 0 + 4 + read-write + + + B_0x1 + The binary rollover is 2 Hz, and the digital rollover is 1 Hz. + 0x1 + + + B_0x2 + The binary rollover is 4 Hz, and the digital rollover is 2 Hz. + 0x2 + + + B_0x3 + The binary rollover is 8 Hz, and the digital rollover is 4 Hz. + 0x3 + + + B_0x4 + The binary rollover is 16 Hz, and the digital rollover is 8 Hz. + 0x4 + + + B_0xF + The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz. + 0xF + + + + + PPSEN0 + Flexible PPS Output Mode Enable +When this bit is set, Bits[3:0] function as PPSCMD. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). + 4 + 1 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS Output +This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: + 5 + 2 + read-write + + + B_0x0 + Target Time registers are programmed only for generating the interrupt event. + 0x0 + + + B_0x1 + Reserved, must not be used + 0x1 + + + B_0x2 + Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. + 0x2 + + + B_0x3 + Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. + 0x3 + + + + + + + ETH_MACPPSCR_alternate + ETH_MACPPSCR_alternate + PPS control register + ETH_MACPPSCR + 0xb70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPSCMD + Flexible PPS Output (eth_ptp_pps_out[0]) Control +Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are 'all-zero'. The following list describes the values of PPSCMD0: +This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS Width Register. +This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the 'Stop Pulse train at time' or 'Stop Pulse Train immediately' commands. +This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. +This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses. +This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010). +This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. + 0 + 4 + read-write + + + B_0x0 + No Command + 0x0 + + + B_0x1 + START Single Pulse + 0x1 + + + B_0x2 + START Pulse Train + 0x2 + + + B_0x3 + Cancel START + 0x3 + + + B_0x4 + STOP Pulse train at time + 0x4 + + + B_0x5 + STOP Pulse Train immediately + 0x5 + + + B_0x6 + Cancel STOP Pulse train + 0x6 + + + B_0x7 + Reserved, must not be used + 0x7 + + + B_0x8 + Reserved, must not be used + 0x8 + + + B_0x9 + Reserved, must not be used + 0x9 + + + B_0xa + Reserved, must not be used + 0xa + + + B_0xb + Reserved, must not be used + 0xb + + + B_0xc + Reserved, must not be used + 0xc + + + B_0xd + Reserved, must not be used + 0xd + + + B_0xe + Reserved, must not be used + 0xe + + + B_0xf + Reserved, must not be used + 0xf + + + + + PPSEN0 + Flexible PPS Output Mode Enable +When this bit is set, Bits[3:0] function as PPSCMD. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). + 4 + 1 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS Output +This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: + 5 + 2 + read-write + + + B_0x0 + Target Time registers are programmed only for generating the interrupt event. + 0x0 + + + B_0x1 + Reserved, must not be used + 0x1 + + + B_0x2 + Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. + 0x2 + + + B_0x3 + Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. + 0x3 + + + + + + + ETH_MACPPSTTSR + ETH_MACPPSTTSR + PPS target time seconds register + 0xb80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSTRH0 + PPS Target Time Seconds Register +This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the ETH_MACPPSCR register. + 0 + 32 + read-write + + + + + ETH_MACPPSTTNR + ETH_MACPPSTTNR + PPS target time nanoseconds register + 0xb84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TTSL0 + Target Time Low for PPS Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in ETH_MACPPSCR. +When the TSCTRLSSR bit is set in the ETH_MACTSCR register, this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + TRGTBUSY0 + PPS Target Time Register Busy +The MAC sets this bit when the PPSCMD0 field in the ETH_MACPPSCR register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. +The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + + + ETH_MACPPSIR + ETH_MACPPSIR + PPS interval register + 0xb88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPSINT0 + PPS Output Signal Interval +These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of sub-second increment value. +You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of sub-second increment value), you should program value 4 (5-1) in this register. + 0 + 32 + read-write + + + + + ETH_MACPPSWR + ETH_MACPPSWR + PPS width register + 0xb8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH0 + PPS Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of PPS signal output. The width is stored in terms of number of units of sub-second increment value. +You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS signal output is 80 ns (that is, four units of sub-second increment value), you should program value 3 (4-1) in this register. +Note: The value programmed in this register must be lesser than the value programmed in ETH_MACPP0IR register. + 0 + 32 + read-write + + + + + ETH_MACPOCR + ETH_MACPOCR + PTP Offload control register + 0xbc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PTOEN + PTP Offload Enable +When this bit is set, the PTP Offload feature is enabled. + 0 + 1 + read-write + + + ASYNCEN + Automatic PTP SYNC message Enable +When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode. + 1 + 1 + read-write + + + APDREQEN + Automatic PTP Pdelay_Req message Enable +When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode. + 2 + 1 + read-write + + + ASYNCTRIG + Automatic PTP SYNC message Trigger +When this bit is set, one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. + 4 + 1 + read-write + + + APDREQTRIG + Automatic PTP Pdelay_Req message Trigger +When this bit is set, one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this operation. + 5 + 1 + read-write + + + DRRDIS + Disable PTO Delay Request/Response response generation +When this bit is set, the Delay Request and Delay response will not be generated for received SYNC and Delay request packet respectively, as required by the programmed mode. + 6 + 1 + read-write + + + DN + Domain Number +This field indicates the domain Number in which the PTP node is operating. + 8 + 8 + read-write + + + + + ETH_MACSPI0R + ETH_MACSPI0R + PTP Source Port Identity 0 Register + 0xbc4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI0 + Source Port Identity 0 +This field indicates bits [31:0] of sourcePortIdentity of PTP node. + 0 + 32 + read-write + + + + + ETH_MACSPI1R + ETH_MACSPI1R + PTP Source port identity 1 register + 0xbc8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI1 + Source Port Identity 1 +This field indicates bits [63:32] of sourcePortIdentity of PTP node. + 0 + 32 + read-write + + + + + ETH_MACSPI2R + ETH_MACSPI2R + PTP Source port identity 2 register + 0xbcc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI2 + Source Port Identity 2 +This field indicates bits [79:64] of sourcePortIdentity of PTP node. + 0 + 16 + read-write + + + + + ETH_MACLMIR + ETH_MACLMIR + Log message interval register + 0xbd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSI + Log Sync Interval +This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. + 0 + 8 + read-write + + + DRSYNCR + Delay_Req to SYNC Ratio +In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. +2: for every 4 SYNC messages +3: for every 8 SYNC messages +4: for every 16 SYNC messages +5: for every 32 SYNC messages +Others: Reserved, must not be used +The master sends this information (logMinDelayReqInterval) in the DelayResp PTP messages to the slave. The reception processes this value from the received DelayResp messages and updates this field accordingly. In the Slave mode, the host must not write/update this register unless it has to override the received value. In Master mode, the sum of this field and logSyncInterval (LSI) field is provided in the logMinDelayReqInterval field of the generated multicast Delay_Resp PTP message. + 8 + 3 + read-write + + + B_0x0 + DelayReq generated for every received SYNC + 0x0 + + + B_0x1 + DelayReq generated every alternate reception of SYNC + 0x1 + + + + + LMPDRI + Log Min Pdelay_Req Interval +This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. + 24 + 8 + read-write + + + + + ETH_MTLOMR + ETH_MTLOMR + Operating mode Register + 0xc00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTXSTS + Drop Transmit Status +When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application. + 1 + 1 + read-write + + + RAA + Receive Arbitration Algorithm +This field is used to select the arbitration algorithm for the Rx side. +Queue 0 has the lowest priority and the last queue has the highest priority. + 2 + 1 + read-write + + + B_0x0 + Strict priority (SP) + 0x0 + + + B_0x1 + Weighted Strict Priority (WSP) + 0x1 + + + + + SCHALG + Tx Scheduling Algorithm +This field indicates the algorithm for Tx scheduling: + 5 + 2 + read-write + + + B_0x0 + WRR algorithm + 0x0 + + + B_0x1 + Reserved, must not be used. + 0x1 + + + B_0x2 + Reserved, must not be used. + 0x2 + + + B_0x3 + Strict priority algorithm. + 0x3 + + + + + CNTPRST + Counters Preset +When this bit is set: +ETH_MTLTXQiUR register is initialized/preset to 0x7F0. +Missed Packet and Overflow Packet counters in ETH_MTLRXQiMPOCR register is initialized/preset to 0x7F0 + 8 + 1 + read-write + + + CNTCLR + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. +If this bit is set along with CNT_PRESET bit, CNT_PRESET has precedence. + 9 + 1 + read-write + + + + + ETH_MTLISR + ETH_MTLISR + Interrupt status Register + 0xc20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Q0IS + Queue 0 interrupt status +This bit indicates that an interrupt has been generated by Queue 0. To reset this bit, read ETH_MTLQ0ICSR register to identify the interrupt cause and clear the source. + 0 + 1 + read-only + + + Q1IS + Queue 1 interrupt status +This bit indicates that an interrupt has been generated by Queue 1. To reset this bit, read ETH_MTLQ1ICSR register to identify the interrupt cause and clear the source. + 1 + 1 + read-only + + + + + ETH_MTLTXQ0OMR + ETH_MTLTXQ0OMR + Tx queue 0 operating mode Register + 0xd00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FTQ + Flush Transmit Queue +When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the ETH_MTLTXQ1OMR register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. +Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (eth_mii_tx_clk) should be active. + 0 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped. + 1 + 1 + read-write + + + TXQEN + Transmit Queue Enable +This field is used to enable/disable the transmit queue 0. +Others: Reserved, must not be used. +Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field. + 2 + 2 + read-write + + + B_0x0 + Not enabled + 0x0 + + + B_0x2 + Enabled + 0x2 + + + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Tx queue. The transmission starts when the packet size within the MTL Tx queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. + 4 + 3 + read-write + + + B_0x0 + 32 + 0x0 + + + B_0x1 + 64 + 0x1 + + + B_0x2 + 96 + 0x2 + + + B_0x3 + 128 + 0x3 + + + B_0x4 + 192 + 0x4 + + + B_0x5 + 256 + 0x5 + + + B_0x6 + 384 + 0x6 + + + B_0x7 + 512 + 0x7 + + + + + TQS + Transmit queue size +This field indicates the size of the allocated transmit queues in blocks of 256 bytes. +Queue size range from 256 bytes (TQS=0b000) to 2048 bytes (TQS=0b111). + 16 + 4 + read-write + + + + + ETH_MTLTXQ0UR + ETH_MTLTXQ0UR + Tx queue 0 underflow register + 0xd04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UFFRMCNT + Underflow Packet Counter +This field indicates the number of packets aborted by the controller because of Tx queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read. + 0 + 11 + read-only + + + UFCNTOVF + Overflow Bit for Underflow Packet Counter +This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. + 11 + 1 + read-only + + + + + ETH_MTLTXQ0DR + ETH_MTLTXQ0DR + Tx queue 0 debug Register + 0xd08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXQPAUSED + Transmit Queue in Pause +When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the full-duplex only mode) because of the following: +Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled +Reception of 802.3x Pause packet when PFC is disabled + 0 + 1 + read-only + + + TRCSTS + MTL Tx Queue Read Controller Status +This field indicates the state of the Tx Queue Read Controller: + 1 + 2 + read-only + + + B_0x0 + Idle state + 0x0 + + + B_0x1 + Read state (transferring data to the MAC transmitter) + 0x1 + + + B_0x2 + Waiting for pending Tx Status from the MAC transmitter + 0x2 + + + B_0x3 + Flushing the Tx queue because of the Packet Abort request from the MAC + 0x3 + + + + + TWCSTS + MTL Tx Queue Write Controller Status +When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. + 3 + 1 + read-only + + + TXQSTS + MTL Tx Queue Not Empty Status +When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. + 4 + 1 + read-only + + + TXSTSFSTS + MTL Tx Status FIFO Full Status +When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. + 5 + 1 + read-only + + + PTXQ + Number of Packets in the Transmit Queue +This field indicates the current number of packets in the Tx queue. +When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of packets in the Transmit queue. + 16 + 3 + read-only + + + STXSTSF + Number of Status Words in Tx Status FIFO of Queue +This field indicates the current number of status in the Tx Status FIFO of this queue. +When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. + 20 + 3 + read-only + + + + + ETH_MTLTXQ0ESR + ETH_MTLTXQ0ESR + Tx queue x ETS status Register + 0xd14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ABS + Average Bits per Slot +This field contains the average transmitted bits per slot. +When the DCB operation is enabled for Queue x, this field is computed over every 10 million bit times slot (10 ms in 1000 Mbps; 100 ms in 100 Mbps). The maximum value is 0x989680. +This bit is reserved in configurations with only one transmit queue. + 0 + 24 + read-only + + + + + ETH_MTLTXQ0QWR + ETH_MTLTXQ0QWR + Tx queue 0 quantum weight register + 0xd18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISCQW + Quantum weight +If WRR algorithm is enabled for queue 0 generic traffic, this field contains the weight for this queue. The maximum value is 0x64. + 0 + 7 + read-write + + + + + ETH_MTLQ0ICSR + ETH_MTLQ0ICSR + Queue 0 interrupt control status Register + 0xd2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXUNFIS + Transmit Queue Underflow Interrupt Status +This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. + 0 + 1 + read-write + + + TXUIE + Transmit Queue Underflow Interrupt Enable +When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. + 8 + 1 + read-write + + + RXOVFIS + Receive Queue Overflow Interrupt Status +This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. + 16 + 1 + read-write + + + RXOIE + Receive Queue Overflow Interrupt Enable +When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. + 24 + 1 + read-write + + + + + ETH_MTLRXQ0OMR + ETH_MTLRXQ0OMR + Rx queue 0 operating mode register + 0xd30 + 0x20 + 0x00700000 + 0xFFFFFFFF + + + RTC + Receive Queue Threshold Control +These bits control the threshold level of the MTL Rx queue (in bytes): +The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. +This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. + 0 + 2 + read-write + + + B_0x0 + 64 + 0x0 + + + B_0x1 + 32 + 0x1 + + + B_0x2 + 96 + 0x2 + + + B_0x3 + 128 + 0x3 + + + + + FUP + Forward Undersized Good Packets +When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. + 3 + 1 + read-write + + + FEP + Forward Error Packets +When this bit is reset, the Rx queue drops packets with error status (CRC error, receive error, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. +When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. + 4 + 1 + read-write + + + RSF + Receive Queue Store and Forward +When this bit is set, the Ethernet peripheral reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. + 5 + 1 + read-write + + + DIS_TCP_EF + Disable Dropping of TCP/IP Checksum Error Packets +When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. +When this bit is reset, all error packets are dropped if the FEP bit is reset. This bit is reserved and RO when Enable Receive TCP/IP Checksum Check is not selected. + 6 + 1 + read-write + + + EHFC + Enable Hardware Flow Control +When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx queue is less than 4 Kbytes. + 7 + 1 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex +These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: +For more information on encoding for this field, see RFD. + 8 + 3 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) +These bits control the threshold (fill-level of Rx queue) at which the flow control is deasserted after activation: +2: Full minus 2 Kbytes, that is, FULL 2 Kbytes +3: Full minus 2.5 Kbytes, that is, FULL 2.5 Kbytes +4: Full minus 2.5 Kbytes, that is, FULL 3 Kbytes +5: Full minus 2.5 Kbytes, that is, FULL 3.5 Kbytes +... +6: Full minus 4 Kbytes, that is, FULL 4 Kbytes +7: Full minus 4.5 Kbytes, that is, FULL 4.5 Kbytes +The deassertion is effective only after flow control is asserted. +Note: The value must be programmed in such a way to make sure that the threshold is a positive number. +When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 Kbytes. +For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 Kbyte) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register. +The width of this field depends on RX FIFO size selected during the configuration. Remaining bits are reserved and read only. +This field is reserved and read only when the RX FIFO size selected during configuration is less than 4Kbytes. + 14 + 3 + read-write + + + B_0x0 + Full minus 1 Kbyte, that is, FULL 1 Kbyte + 0x0 + + + B_0x1 + Full minus 1.5 Kbyte, that is, FULL 1.5 Kbyte + 0x1 + + + + + RQS + Receive Queue Size +This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx queues more than one and the reset value is 0x0. + 20 + 3 + read-only + + + + + ETH_MTLRXQ0MPOCR + ETH_MTLRXQ0MPOCR + Rx queue 0 missed packet and overflow counter register + 0xd34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVFPKTCNT + Overflow Packet Counter +This field indicates the number of packets discarded by the Ethernet peripheral because of Receive queue overflow. This counter is incremented each time the Ethernet peripheral discards an incoming packet because of overflow. This counter is reset when this register is read. + 0 + 11 + read-only + + + OVFCNTOVF + Overflow Counter Overflow Bit +When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. + 11 + 1 + read-only + + + MISPKTCNT + Missed Packet Counter +This field indicates the number of packets missed by the Ethernet peripheral because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read. +This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability. + 16 + 11 + read-only + + + MISCNTOVF + Missed Packet Counter Overflow Bit +When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. + 27 + 1 + read-only + + + + + ETH_MTLRXQ0DR + ETH_MTLRXQ0DR + Rx queue 0 debug register + 0xd38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RWCSTS + MTL Rx Queue Write Controller Active Status +When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue. + 0 + 1 + read-only + + + RRCSTS + MTL Rx Queue Read Controller State +This field gives the state of the Rx queue Read controller: + 1 + 2 + read-only + + + B_0x0 + Idle state + 0x0 + + + B_0x1 + Reading packet data + 0x1 + + + B_0x2 + Reading packet status (or timestamp) + 0x2 + + + B_0x3 + Flushing the packet data and status + 0x3 + + + + + RXQSTS + MTL Rx Queue Fill-Level Status +This field gives the status of the fill-level of the Rx queue: + 4 + 2 + read-only + + + B_0x0 + Rx queue empty + 0x0 + + + B_0x1 + Rx queue fill-level below flow-control deactivate threshold + 0x1 + + + B_0x2 + Rx queue fill-level above flow-control activate threshold + 0x2 + + + B_0x3 + Rx queue full + 0x3 + + + + + PRXQ + Number of Packets in Receive Queue +This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size. + 16 + 14 + read-only + + + + + ETH_MTLRXQ0CR + ETH_MTLRXQ0CR + Rx queue 0 control register + 0xd3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXQ_WEGT + Receive Queue Weight +This field indicates the weight assigned to the Rx queue 0. The weight is used as the number of continuous PBL requests or contiguous packets (depending on the RXQ_PKT_ARBIT) allocated to the queue in one arbitration cycle. + 0 + 3 + read-write + + + RXQ_FRM_ARBIT + Receive Queue Packet Arbitration +When this bit is set, the Ethernet peripheral drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. +When this bit is reset, the Ethernet peripheral drives the packet data to the ARI interface such that the following amount of data of currently-selected queue is transmitted before switching to other queue: +PBL amount of data (indicated by ari_qN_pbl_i[]) +or +complete data of a packet +The status and the timestamp are not a part of the PBL data. Therefore, the Ethernet peripheral drives the complete status (including timestamp status) during first PBL request for the packet (in store-and-forward mode) or the last PBL request for the packet (in Threshold mode). + 3 + 1 + read-only + + + + + ETH_MTLTXQ1OMR + ETH_MTLTXQ1OMR + Tx queue 1 operating mode Register + 0xd40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FTQ + Flush Transmit Queue +When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the ETH_MTLTXQ1OMR register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. +Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (eth_mii_tx_clk) should be active. + 0 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped. + 1 + 1 + read-write + + + TXQEN + Transmit Queue Enable +This field is used to enable/disable the transmit queue 0. +Others: Reserved, must not be used. +Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field. + 2 + 2 + read-write + + + B_0x0 + Not enabled + 0x0 + + + B_0x2 + Enabled + 0x2 + + + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Tx queue. The transmission starts when the packet size within the MTL Tx queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. + 4 + 3 + read-write + + + B_0x0 + 32 + 0x0 + + + B_0x1 + 64 + 0x1 + + + B_0x2 + 96 + 0x2 + + + B_0x3 + 128 + 0x3 + + + B_0x4 + 192 + 0x4 + + + B_0x5 + 256 + 0x5 + + + B_0x6 + 384 + 0x6 + + + B_0x7 + 512 + 0x7 + + + + + TQS + Transmit queue size +This field indicates the size of the allocated transmit queues in blocks of 256 bytes. +Queue size range from 256 bytes (TQS=0b000) to 2048 bytes (TQS=0b111). + 16 + 4 + read-write + + + + + ETH_MTLTXQ1UR + ETH_MTLTXQ1UR + Tx queue 1 underflow register + 0xd44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UFFRMCNT + Underflow Packet Counter +This field indicates the number of packets aborted by the controller because of Tx queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read. + 0 + 11 + read-only + + + UFCNTOVF + Overflow Bit for Underflow Packet Counter +This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. + 11 + 1 + read-only + + + + + ETH_MTLTXQ1DR + ETH_MTLTXQ1DR + Tx queue 1 debug Register + 0xd48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXQPAUSED + Transmit Queue in Pause +When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the full-duplex only mode) because of the following: +Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled +Reception of 802.3x Pause packet when PFC is disabled + 0 + 1 + read-only + + + TRCSTS + MTL Tx Queue Read Controller Status +This field indicates the state of the Tx Queue Read Controller: + 1 + 2 + read-only + + + B_0x0 + Idle state + 0x0 + + + B_0x1 + Read state (transferring data to the MAC transmitter) + 0x1 + + + B_0x2 + Waiting for pending Tx Status from the MAC transmitter + 0x2 + + + B_0x3 + Flushing the Tx queue because of the Packet Abort request from the MAC + 0x3 + + + + + TWCSTS + MTL Tx Queue Write Controller Status +When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. + 3 + 1 + read-only + + + TXQSTS + MTL Tx Queue Not Empty Status +When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. + 4 + 1 + read-only + + + TXSTSFSTS + MTL Tx Status FIFO Full Status +When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. + 5 + 1 + read-only + + + PTXQ + Number of Packets in the Transmit Queue +This field indicates the current number of packets in the Tx queue. +When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of packets in the Transmit queue. + 16 + 3 + read-only + + + STXSTSF + Number of Status Words in Tx Status FIFO of Queue +This field indicates the current number of status in the Tx Status FIFO of this queue. +When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. + 20 + 3 + read-only + + + + + ETH_MTLTXQ1ECR + ETH_MTLTXQ1ECR + Tx queue 1 ETS control Register + 0xd50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC + Credit Control +When this bit is set, the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no packet waiting in Channel 1 and another channel is transmitting. +When this bit is reset, the accumulated credit parameter in the credit-based shaper algorithm logic is set to zero when there is positive credit and no packet to transmit in Channel 1. When there is no packet waiting in Channel 1 and other channel is transmitting, no credit is accumulated. + 3 + 1 + read-write + + + + + ETH_MTLTXQ1ESR + ETH_MTLTXQ1ESR + Tx queue x ETS status Register + 0xd54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ABS + Average Bits per Slot +This field contains the average transmitted bits per slot. +When the DCB operation is enabled for Queue x, this field is computed over every 10 million bit times slot (10 ms in 1000 Mbps; 100 ms in 100 Mbps). The maximum value is 0x989680. +This bit is reserved in configurations with only one transmit queue. + 0 + 24 + read-only + + + + + ETH_MTLTXQ1QWR + ETH_MTLTXQ1QWR + Tx queue 1 quantum weight register + 0xd58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISCQW + quantum weight +If WRR algorithm is enabled for queue 1 generic traffic, this field contains the weight for this queue. The maximum value is 0x64. + 0 + 7 + read-write + + + + + ETH_MTLTXQ1HCR + ETH_MTLTXQ1HCR + Tx Queue 1 hiCredit register + 0xd60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HC + hiCredit Value +This field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024. +The maximum value is maxInterferenceSize, that is, best-effort maximum packet size (16 384 bytes or 131 072 bits). The value to be specified is 131 072 * 1 024 = 134 217 728 or 0x0800 0000. + 0 + 29 + read-write + + + + + ETH_MTLQ1ICSR + ETH_MTLQ1ICSR + Queue 1 interrupt control status Register + 0xd6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXUNFIS + Transmit Queue Underflow Interrupt Status +This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. + 0 + 1 + read-write + + + TXUIE + Transmit Queue Underflow Interrupt Enable +When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. + 8 + 1 + read-write + + + RXOVFIS + Receive Queue Overflow Interrupt Status +This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. + 16 + 1 + read-write + + + RXOIE + Receive Queue Overflow Interrupt Enable +When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. + 24 + 1 + read-write + + + + + ETH_MTLRXQ1OMR + ETH_MTLRXQ1OMR + Rx queue 1 operating mode register + 0xd70 + 0x20 + 0x00700000 + 0xFFFFFFFF + + + RTC + Receive Queue Threshold Control +These bits control the threshold level of the MTL Rx queue (in bytes): +The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. +This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. + 0 + 2 + read-write + + + B_0x0 + 64 + 0x0 + + + B_0x1 + 32 + 0x1 + + + B_0x2 + 96 + 0x2 + + + B_0x3 + 128 + 0x3 + + + + + FUP + Forward Undersized Good Packets +When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. + 3 + 1 + read-write + + + FEP + Forward Error Packets +When this bit is reset, the Rx queue drops packets with error status (CRC error, receive error, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. +When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. + 4 + 1 + read-write + + + RSF + Receive Queue Store and Forward +When this bit is set, the Ethernet peripheral reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. + 5 + 1 + read-write + + + DIS_TCP_EF + Disable Dropping of TCP/IP Checksum Error Packets +When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. +When this bit is reset, all error packets are dropped if the FEP bit is reset. This bit is reserved and RO when Enable Receive TCP/IP Checksum Check is not selected. + 6 + 1 + read-write + + + EHFC + Enable Hardware Flow Control +When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx queue is less than 4 Kbytes. + 7 + 1 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex +These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: +For more information on encoding for this field, see RFD. + 8 + 3 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) +These bits control the threshold (fill-level of Rx queue) at which the flow control is deasserted after activation: +2: Full minus 2 Kbytes, that is, FULL 2 Kbytes +3: Full minus 2.5 Kbytes, that is, FULL 2.5 Kbytes +4: Full minus 2.5 Kbytes, that is, FULL 3 Kbytes +5: Full minus 2.5 Kbytes, that is, FULL 3.5 Kbytes +... +6: Full minus 4 Kbytes, that is, FULL 4 Kbytes +7: Full minus 4.5 Kbytes, that is, FULL 4.5 Kbytes +The deassertion is effective only after flow control is asserted. +Note: The value must be programmed in such a way to make sure that the threshold is a positive number. +When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 Kbytes. +For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 Kbyte) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register. +The width of this field depends on RX FIFO size selected during the configuration. Remaining bits are reserved and read only. +This field is reserved and read only when the RX FIFO size selected during configuration is less than 4Kbytes. + 14 + 3 + read-write + + + B_0x0 + Full minus 1 Kbyte, that is, FULL 1 Kbyte + 0x0 + + + B_0x1 + Full minus 1.5 Kbyte, that is, FULL 1.5 Kbyte + 0x1 + + + + + RQS + Receive Queue Size +This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx queues more than one and the reset value is 0x0. + 20 + 3 + read-only + + + + + ETH_MTLRXQ1MPOCR + ETH_MTLRXQ1MPOCR + Rx queue 1 missed packet and overflow counter register + 0xd74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVFPKTCNT + Overflow Packet Counter +This field indicates the number of packets discarded by the Ethernet peripheral because of Receive queue overflow. This counter is incremented each time the Ethernet peripheral discards an incoming packet because of overflow. This counter is reset when this register is read. + 0 + 11 + read-only + + + OVFCNTOVF + Overflow Counter Overflow Bit +When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. + 11 + 1 + read-only + + + MISPKTCNT + Missed Packet Counter +This field indicates the number of packets missed by the Ethernet peripheral because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read. +This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability. + 16 + 11 + read-only + + + MISCNTOVF + Missed Packet Counter Overflow Bit +When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. + 27 + 1 + read-only + + + + + ETH_MTLRXQ1DR + ETH_MTLRXQ1DR + Rx queue 1 debug register + 0xd78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RWCSTS + MTL Rx Queue Write Controller Active Status +When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue. + 0 + 1 + read-only + + + RRCSTS + MTL Rx Queue Read Controller State +This field gives the state of the Rx queue Read controller: + 1 + 2 + read-only + + + B_0x0 + Idle state + 0x0 + + + B_0x1 + Reading packet data + 0x1 + + + B_0x2 + Reading packet status (or timestamp) + 0x2 + + + B_0x3 + Flushing the packet data and status + 0x3 + + + + + RXQSTS + MTL Rx Queue Fill-Level Status +This field gives the status of the fill-level of the Rx queue: + 4 + 2 + read-only + + + B_0x0 + Rx queue empty + 0x0 + + + B_0x1 + Rx queue fill-level below flow-control deactivate threshold + 0x1 + + + B_0x2 + Rx queue fill-level above flow-control activate threshold + 0x2 + + + B_0x3 + Rx queue full + 0x3 + + + + + PRXQ + Number of Packets in Receive Queue +This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size. + 16 + 14 + read-only + + + + + ETH_MTLRXQ1CR + ETH_MTLRXQ1CR + Rx queue 1 control register + 0xd7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXQ_WEGT + Receive Queue Weight +This field indicates the weight assigned to the Rx queue 0. The weight is used as the number of continuous PBL requests or contiguous packets (depending on the RXQ_PKT_ARBIT) allocated to the queue in one arbitration cycle. + 0 + 3 + read-write + + + RXQ_FRM_ARBIT + Receive Queue Packet Arbitration +When this bit is set, the Ethernet peripheral drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. +When this bit is reset, the Ethernet peripheral drives the packet data to the ARI interface such that the following amount of data of currently-selected queue is transmitted before switching to other queue: +PBL amount of data (indicated by ari_qN_pbl_i[]) +or +complete data of a packet +The status and the timestamp are not a part of the PBL data. Therefore, the Ethernet peripheral drives the complete status (including timestamp status) during first PBL request for the packet (in store-and-forward mode) or the last PBL request for the packet (in Threshold mode). + 3 + 1 + read-only + + + + + ETH_DMAMR + ETH_DMAMR + DMA mode register + 0x1000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWR + Software Reset +When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all clock domains. Before reprogramming any register, a value of zero should be read in this bit. +Note: The reset operation is complete only when all resets in all active clock domains are deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + TAA + Transmit Arbitration Algorithm +This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected. + 2 + 3 + read-only + + + B_0x0 + Fixed priority. In fixed priority, Channel 0 has the lowest priority and the last channel has the highest priority. + 0x0 + + + B_0x1 + Weighted Strict Priority (WSP) + 0x1 + + + B_0x2 + Weighted Round-Robin (WRR) + 0x2 + + + B_0x3 + Reserved, must not be used. + 0x3 + + + B_0x4 + Reserved, must not be used. + 0x4 + + + B_0x5 + Reserved, must not be used. + 0x5 + + + B_0x6 + Reserved, must not be used. + 0x6 + + + B_0x7 + Reserved, must not be used. + 0x7 + + + + + TXPR + Transmit priority +When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus. + 11 + 1 + read-write + + + PR + Priority ratio +These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. + 12 + 3 + read-write + + + B_0x0 + The priority ratio is 1:1 + 0x0 + + + B_0x1 + The priority ratio is 2:1 + 0x1 + + + B_0x2 + The priority ratio is 3:1 + 0x2 + + + B_0x3 + The priority ratio is 4:1 + 0x3 + + + B_0x4 + The priority ratio is 5:1 + 0x4 + + + B_0x5 + The priority ratio is 6:1 + 0x5 + + + B_0x6 + The priority ratio is 7:1 + 0x6 + + + B_0x7 + The priority ratio is 8:1 + 0x7 + + + + + INTM + Interrupt Mode +This field defines the interrupt mode of the Ethernet peripheral. +The behavior of the interrupt signal and of the RI/TI bits in the ETH_DMACSR register changes depending on the INTM value (refer to behavior). + 16 + 2 + read-write + + + + + ETH_DMASBMR + ETH_DMASBMR + System bus mode register + 0x1004 + 0x20 + 0x01010000 + 0xFFFFFFFF + + + FB + Fixed Burst Length +When this bit is set to 1, the AXI master will initiate burst transfers of specified lengths as given below. +Burst transfers of fixed burst lengths as indicated by the BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field +Burst transfers of length 1: when this bit is set to 0, the AXI master initiates burst transfers that are equal to or less than the maximum allowed burst length programmed in Bits[7:1]. + 0 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 4 on the AXI interface. +When the FB bit is set to 0, setting this bit has no effect. + 1 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 8 on the AXI interface. +When the FB bit is set to 0, setting this bit has no effect. + 2 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or the FB bit is set to 0, the AXI master can select a burst length of 16 on the AXI interface. +When the FB bit is set to 0, setting this bit has no effect. + 3 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the AXI master can select a burst length of 32 on the AXI interface. + 4 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the AXI master can select a burst length of 64 on the AXI interface. + 5 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the AXI master can select a burst length of 128 on the AXI interface. + 6 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the AXI master can select a burst length of 256 on the AXI interface. + 7 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set to 1, the master performs address-aligned burst transfers on Read and Write channels. + 12 + 1 + read-write + + + ONEKBBE + 1 Kbyte Boundary Crossing Enable for the AXI Master +When set, the burst transfers performed by the AXI master do not cross 1 Kbyte boundary. When reset, the burst transfers performed by the AXI master do not cross 4 Kbyte boundary. + 13 + 1 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1 + 16 + 2 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1 +Bit 27 is reserved +Bit 26 is reserved + 24 + 2 + read-write + + + LPI_XIT_PKT + Unlock on Magic Packet or Remote wakeup Packet +When set to 1, this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wakeup packet is received. When set to 0, this bit enables the AXI master to come out of the LPI mode when any packet is received. + 30 + 1 + read-write + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode and accepts the LPI request from the AXI System Clock controller. +When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + + + ETH_DMAISR + ETH_DMAISR + Interrupt status register + 0x1008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DC0IS + DMA Channel 0 Interrupt Status +This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 0, the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source. + 0 + 1 + read-only + + + DC1IS + DMA Channel 1 Interrupt Status +This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 0, the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source. + 1 + 1 + read-only + + + MTLIS + MTL Interrupt Status +This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. + 16 + 1 + read-only + + + MACIS + MAC Interrupt Status +This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. + 17 + 1 + read-only + + + + + ETH_DMADSR + ETH_DMADSR + Debug status register + 0x100c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AXWHSTS + AXI Master Write Channel +When high, this bit indicates that the write channel of the AXI master is active, and it is transferring data. + 0 + 1 + read-only + + + AXRHSTS + AXI Master Read Channel Status +When high, this bit indicates that the read channel of the AXI master is active, and it is transferring the data. + 1 + 1 + read-only + + + RPS0 + DMA Channel 0 Receive Process State +This field indicates the Rx DMA FSM state for Channel 0: +The MSB of this field always returns 0. This field does not generate an interrupt. + 8 + 4 + read-only + + + B_0x0 + Stopped (Reset or Stop Receive Command issued) + 0x0 + + + B_0x1 + Running (Fetching Rx Transfer Descriptor) + 0x1 + + + B_0x2 + Reserved for future use + 0x2 + + + B_0x3 + Running (Waiting for Rx packet) + 0x3 + + + B_0x4 + Suspended (Rx Descriptor Unavailable) + 0x4 + + + B_0x5 + Running (Closing the Rx Descriptor) + 0x5 + + + B_0x6 + Timestamp write state + 0x6 + + + B_0x7 + Running (Transferring the received packet data from the Rx buffer to the system memory) + 0x7 + + + + + TPS0 + DMA Channel 0 Transmit Process State +This field indicates the Tx DMA FSM state for Channel 0: +The MSB of this field always returns 0. This field does not generate an interrupt. + 12 + 4 + read-only + + + B_0x0 + Stopped (Reset or Stop Transmit Command issued) + 0x0 + + + B_0x1 + Running (Fetching Tx Transfer Descriptor) + 0x1 + + + B_0x2 + Running (Waiting for status) + 0x2 + + + B_0x3 + Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + 0x3 + + + B_0x4 + Timestamp write state + 0x4 + + + B_0x5 + Reserved for future use + 0x5 + + + B_0x6 + Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + 0x6 + + + B_0x7 + Running (Closing Tx Descriptor) + 0x7 + + + + + RPS1 + DMA Channel 1 Receive Process State +This field indicates the Rx DMA FSM state for Channel 1. This field is similar to the RPS0 field. + 16 + 4 + read-only + + + TPS1 + DMA Channel 1 Transmit Process State +This field indicates the Tx DMA FSM state for Channel 1. This field is similar to the TPS0 field. + 20 + 4 + read-only + + + + + ETH_DMAA4TXACR + ETH_DMAA4TXACR + AXI4 transmit channel ACE control register + 0x1020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDRC + Transmit DMA Read Descriptor Cache Control +This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor. + 0 + 4 + read-write + + + TEC + Transmit DMA Extended Packet Buffer or TSO Payload Cache Control +When TSO is NOT enabled, This field is used to drive arcache o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers). +When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO payload data. + 8 + 4 + read-write + + + THC + Transmit DMA First Packet Buffer or TSO Header Cache Control +When TSO is NOT enabled, This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor). +When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO Header data. + 16 + 4 + read-write + + + + + ETH_DMAA4RXACR + ETH_DMAA4RXACR + AXI4 receive channel ACE control register + 0x1024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDWC + Receive DMA Write Descriptor Cache Control +This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor. + 0 + 4 + read-write + + + RPC + Receive DMA Payload Cache Control +This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated. + 8 + 4 + read-write + + + RHC + Receive DMA Header Cache Control +This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated. + 16 + 4 + read-write + + + RDC + Receive DMA Buffer Cache Control +This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated. + 24 + 4 + read-write + + + + + ETH_DMAA4DACR + ETH_DMAA4DACR + AXI4 descriptor ACE control register + 0x1028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDWC + Transmit DMA Write Descriptor Cache control +This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor. + 0 + 4 + read-write + + + TDWD + Transmit DMA Write Descriptor Domain control +This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor. + 4 + 2 + read-write + + + RDRC + Receive DMA Read Descriptor Cache control +This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor. + 8 + 4 + read-write + + + + + ETH_DMAC0CR + ETH_DMAC0CR + Channel 0 control register + 0x1100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MSS + Maximum Segment Size +This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of ETH_DMACiTXCR register is set. +The value programmed in this field must be more than the configured Data width in bytes. It is recommended to use a MSS value of 64 bytes or more. + 0 + 14 + read-write + + + PBLX8 + 8xPBL mode +When this bit is set, the PBL value programmed in Bits[21:16] in ETH_DMACiTXCR is multiplied eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 16 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the 32-bit word number to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. +When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous. + 18 + 3 + read-write + + + + + ETH_DMAC0TXCR + ETH_DMAC0TXCR + Channel 0 transmit control register + 0x1104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. +The DMA tries to acquire descriptor from either of the following positions: +The current position in the list: this is the base address of the Transmit list set by the ETH_DMACiTXDLAR register. +The position at which the transmission was previously stopped +If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the ETH_DMACiSR is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the ETH_DMACiTXDLAR register, the DMA behavior is unpredictable. +When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program ETH_DMACiTXDLAR register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. + 0 + 1 + read-write + + + TCW + Transmit Channel Weight +This field indicates the weight assigned to the corresponding Transmit channel. When reset is complete, this field is set to 0 for all channels by default, resulting in equal weights to all channels. + 1 + 3 + read-only + + + OSF + Operate on Second Packet +When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. + 4 + 1 + read-write + + + TSE + TCP Segmentation Enabled +When this bit is set, the DMA performs the TCP segmentation for packets in Channel i. The TCP segmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor. When this bit is set, the TxPBL value must be greater than or equal to 4. + 12 + 1 + read-write + + + TXPBL + Transmit Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. +To transfer more than 32 beats, perform the following steps: +1. Set the PBLx8 mode in ETH_DMACiCR. +2. Set the PBL. + 16 + 6 + read-write + + + TQOS + Transmit QOS. +This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel i. + 24 + 4 + read-write + + + + + ETH_DMAC0RXCR + ETH_DMAC0RXCR + Channel 0 receive control register + 0x1108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SR + Start or Stop Receive +When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. +The DMA tries to acquire descriptor from either of the following positions: +The current position in the list: this is the address set by the ETH_DMAC0RXDLAR register. +The position at which the Rx process was previously stopped +If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the ETH_DMAC0SR is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the ETH_DMAC0RXDLAR register, the DMA behavior is unpredictable. +When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. + 0 + 1 + read-write + + + RBSZ + Receive Buffer size +This field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16 Kbytes. The buffer size is applicable to payload buffers when split headers are enabled. +Note: The buffer size must be a multiple of 4, 8, or 16 depending on the bus widths (32, 64, or 128 respectively). This is required even if the value of buffer address pointer is not aligned to bus width. If the buffer size is not a multiple of 4, 8, or 16, it may result into undefined behavior. +The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and the DMA internally takes the LSB bits as all-zero. Therefore, these LSB bits are read-only (RO). + 1 + 14 + read-write + + + RXPBL + Receive Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. +To transfer more than 32 beats, perform the following steps: +1. Set the PBLx8 mode in the ETH_DMAC0CR. +2. Set the PBL. + 16 + 6 + read-write + + + RQOS + Rx AXI4 QOS. +This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0. + 24 + 4 + read-write + + + RPF + DMA Rx Channel0 Packet Flush +When this bit is set to 1, the DMA will automatically flush the +packet from the Rx queues destined to DMA Rx Channel 0 when the DMA Rx +Channel 0 is stopped after a system bus error has occurred. +The flushing happens on the Read side of the Rx queue. +When this bit is set to 0 the EQOS will not flush the packet in the Rx queue +destined to DMA Rx Channel 0 after the DMA is stopped due to a system bus error. + 31 + 1 + read-write + + + + + ETH_DMAC0TXDLAR + ETH_DMAC0TXDLAR + Channel 0 Tx descriptor list address register + 0x1114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC0RXDLAR + ETH_DMAC0RXDLAR + Channel 0 Rx descriptor list address register + 0x111c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC0TXDTPR + ETH_DMAC0TXDTPR + Channel 0 Tx descriptor tail pointer register + 0x1120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDT + Transmit Descriptor Tail Pointer +This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers. +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC0RXDTPR + ETH_DMAC0RXDTPR + Channel 0 Rx descriptor tail pointer register + 0x1128 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDT + Receive Descriptor Tail Pointer +This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers. +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC0TXRLR + ETH_DMAC0TXRLR + Channel 0 Tx descriptor ring length register + 0x112c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDRL + Transmit Descriptor Ring Length +This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. It is recommended to put a minimum ring descriptor length of 4. + 0 + 10 + read-write + + + + + ETH_DMAC0RXRLR + ETH_DMAC0RXRLR + Channel 0 Rx descriptor ring length register + 0x1130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDRL + Receive Descriptor Ring Length +This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. + 0 + 10 + read-write + + + + + ETH_DMAC0IER + ETH_DMAC0IER + Channel 0 interrupt enable register + 0x1134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmit Interrupt Enable +When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + TXSE + Transmit Stopped Enable +When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled. + 1 + 1 + read-write + + + TBUE + Transmit Buffer Unavailable Enable +When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled. + 2 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + RBUE + Receive Buffer Unavailable Enable +When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled. + 7 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled. + 8 + 1 + read-write + + + RWTE + Receive Watchdog Timeout Enable +When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled. + 9 + 1 + read-write + + + ETIE + Early Transmit Interrupt Enable +When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled. + 10 + 1 + read-write + + + ERIE + Early Receive Interrupt Enable +When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. + 11 + 1 + read-write + + + FBEE + Fatal Bus Error Enable +When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled. + 12 + 1 + read-write + + + CDEE + Context Descriptor Error Enable +When this bit is set along with the AIE bit, the Context Descriptor error interrupt is enabled. When this bit is reset, the Context Descriptor error interrupt is disabled. + 13 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMAC0SR: +Bit 1: Transmit Process Stopped +Bit 7: Rx Buffer Unavailable +Bit 8: Receive Process Stopped +Bit 9: Receive Watchdog Timeout +Bit 10: Early Transmit Interrupt +Bit 12: Fatal Bus Error +When this bit is reset, the abnormal interrupt summary is disabled. + 14 + 1 + read-write + + + NIE + Normal Interrupt Summary Enable +When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMAC0SR: +Bit 0: Transmit Interrupt +Bit 2: Transmit Buffer Unavailable +Bit 6: Receive Interrupt +Bit 11: Early Receive Interrupt +When this bit is reset, the normal interrupt summary is disabled. + 15 + 1 + read-write + + + + + ETH_DMAC0RXIWTR + ETH_DMAC0RXIWTR + Channel 0 Rx interrupt watchdog timer register + 0x1138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RWT + Receive Interrupt Watchdog Timer Count +This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. +The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the ETH_DMAC0SR, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. +When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. + 0 + 8 + read-write + + + RWTU + Receive Interrupt Watchdog Timer Count Units +This field indicates the number of system clock cycles corresponding to one unit in RWT[7:0] field. +For example, when RWT[7:0] = 2 and RWTU[1:0] = 1, the watchdog timer is set for 2 * 512 = 1024 system clock cycles. + 16 + 2 + read-write + + + B_0x0 + 256 + 0x0 + + + B_0x1 + 512 + 0x1 + + + B_0x2 + 1024 + 0x2 + + + B_0x3 + 2048 + 0x3 + + + + + + + ETH_DMAC0CATXDR + ETH_DMAC0CATXDR + Channel 0 current application transmit descriptor register + 0x1144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Application Transmit Descriptor Address Pointer +The DMA updates this pointer during Tx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC0CARXDR + ETH_DMAC0CARXDR + Channel 0 current application receive descriptor register + 0x114c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Application Receive Descriptor Address Pointer +The DMA updates this pointer during Rx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC0CATXBR + ETH_DMAC0CATXBR + Channel 0 current application transmit buffer register + 0x1154 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Application Transmit Buffer Address Pointer +The DMA updates this pointer during Tx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC0CARXBR + ETH_DMAC0CARXBR + Channel 0 current application receive buffer register + 0x115c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Application Receive Buffer Address Pointer +The DMA updates this pointer during Rx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC0SR + ETH_DMAC0SR + Channel 0 status register + 0x1160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI + Transmit Interrupt +This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. + 0 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TBU + Transmit Buffer Unavailable +This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit Process state transitions. +To resume processing the Transmit descriptors, the application should do the following: +1. Change the ownership of the descriptor by setting Bit 31 of TDES3. +2. Issue a Transmit Poll Demand command. +For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. + 2 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. +The reception remains in the Running state. + 6 + 1 + read-write + + + RBU + Receive Buffer Unavailable +This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. + 7 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Rx process enters the Stopped state. + 8 + 1 + read-write + + + RWT + Receive Watchdog Timeout +This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. + 9 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. + 10 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. The RI bit of this register automatically clears this bit. + 11 + 1 + read-write + + + FBE + Fatal Bus Error +This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. + 12 + 1 + read-write + + + CDE + Context Descriptor Error +This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor), and the DMA Tx engine ignored it. + 13 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMACiIER register: +Bit 1: Transmit Process Stopped +Bit 7: Receive Buffer Unavailable +Bit 8: Receive Process Stopped +Bit 10: Early Transmit Interrupt +Bit 12: Fatal Bus Error +Bit 13: Context Descriptor Error +Only unmasked bits affect the Abnormal Interrupt Summary bit. +This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 14 + 1 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMACiIER register: +Bit 0: Transmit Interrupt +Bit 2: Transmit Buffer Unavailable +Bit 6: Receive Interrupt +Bit 11: Early Receive Interrupt +Only unmasked bits (interrupts for which interrupt enable is set in ETH_DMACiIER register) affect the Normal Interrupt Summary bit. +This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. + 15 + 1 + read-write + + + TEB + Tx DMA Error Bits +This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. +Bit[2]: Error during data transfer by Tx DMA when '1', no when '0' +Bit[1]: Error during descriptor access when '1', Error during data buffer access when '0' +Bit[0]: Error during read transfer when '1', Error during write transfer when '0' +This field is valid only when the FBE bit is set. This field does not generate an interrupt. + 16 + 3 + read-only + + + REB + Rx DMA Error Bits +This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. +Bit [2]: Error during data transfer by Rx DMA when '1', no when '0' +Bit[1]: Error during descriptor access when '1', Error during data buffer access when '0' +Bit[0]: Error during read transfer when '1', Error during write transfer when '0' +This field is valid only when the FBE bit is set. This field does not generate an interrupt. + 19 + 3 + read-only + + + + + ETH_DMAC0MFCR + ETH_DMAC0MFCR + Channel 0 missed frame count register + 0x116c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MFC + Dropped Packet Counters +This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing +RPF field in ETH_DMAC0RXCR register. The counter gets cleared when this register is read. + 0 + 11 + read-only + + + MFCO + Overflow status of the MFC Counter +When this bit is set then the MFC counter does not get incremented +further. The bit gets cleared when this register is read. + 15 + 1 + read-only + + + + + ETH_DMAC1CR + ETH_DMAC1CR + Channel 1 control register + 0x1180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MSS + Maximum Segment Size +This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of ETH_DMACiTXCR register is set. +The value programmed in this field must be more than the configured Data width in bytes. It is recommended to use a MSS value of 64 bytes or more. + 0 + 14 + read-write + + + PBLX8 + 8xPBL mode +When this bit is set, the PBL value programmed in Bits[21:16] in ETH_DMACiTXCR is multiplied eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 16 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the 32-bit word number to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. +When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous. + 18 + 3 + read-write + + + + + ETH_DMAC1TXCR + ETH_DMAC1TXCR + Channel 1 transmit control register + 0x1184 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. +The DMA tries to acquire descriptor from either of the following positions: +The current position in the list: this is the base address of the Transmit list set by the ETH_DMACiTXDLAR register. +The position at which the transmission was previously stopped +If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the ETH_DMACiSR is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the ETH_DMACiTXDLAR register, the DMA behavior is unpredictable. +When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program ETH_DMACiTXDLAR register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. + 0 + 1 + read-write + + + TCW + Transmit Channel Weight +This field indicates the weight assigned to the corresponding Transmit channel. When reset is complete, this field is set to 0 for all channels by default, resulting in equal weights to all channels. + 1 + 3 + read-only + + + OSF + Operate on Second Packet +When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. + 4 + 1 + read-write + + + TSE + TCP Segmentation Enabled +When this bit is set, the DMA performs the TCP segmentation for packets in Channel i. The TCP segmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor. When this bit is set, the TxPBL value must be greater than or equal to 4. + 12 + 1 + read-write + + + TXPBL + Transmit Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. +To transfer more than 32 beats, perform the following steps: +1. Set the PBLx8 mode in ETH_DMACiCR. +2. Set the PBL. + 16 + 6 + read-write + + + TQOS + Transmit QOS. +This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel i. + 24 + 4 + read-write + + + + + ETH_DMAC1TXDLAR + ETH_DMAC1TXDLAR + Channel 1 Tx descriptor list address register + 0x1194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC1TXDTPR + ETH_DMAC1TXDTPR + Channel 1 Tx descriptor tail pointer register + 0x11a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDT + Transmit Descriptor Tail Pointer +This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers. +The width of this field depends on the configuration: +31:2 for 32-bit configuration + 2 + 30 + read-write + + + + + ETH_DMAC1TXRLR + ETH_DMAC1TXRLR + Channel 1 Tx descriptor ring length register + 0x11ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDRL + Transmit Descriptor Ring Length +This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. It is recommended to put a minimum ring descriptor length of 4. + 0 + 10 + read-write + + + + + ETH_DMAC1IER + ETH_DMAC1IER + Channel 1 interrupt enable register + 0x11b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmit Interrupt Enable +When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + TXSE + Transmit Stopped Enable +When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled. + 1 + 1 + read-write + + + TBUE + Transmit Buffer Unavailable Enable +When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled. + 2 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + RBUE + Receive Buffer Unavailable Enable +When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled. + 7 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled. + 8 + 1 + read-write + + + RWTE + Receive Watchdog Timeout Enable +When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled. + 9 + 1 + read-write + + + ETIE + Early Transmit Interrupt Enable +When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled. + 10 + 1 + read-write + + + ERIE + Early Receive Interrupt Enable +When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. + 11 + 1 + read-write + + + FBEE + Fatal Bus Error Enable +When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled. + 12 + 1 + read-write + + + CDEE + Context Descriptor Error Enable +When this bit is set along with the AIE bit, the Context Descriptor error interrupt is enabled. When this bit is reset, the Context Descriptor error interrupt is disabled. + 13 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMAC0SR: +Bit 1: Transmit Process Stopped +Bit 7: Rx Buffer Unavailable +Bit 8: Receive Process Stopped +Bit 9: Receive Watchdog Timeout +Bit 10: Early Transmit Interrupt +Bit 12: Fatal Bus Error +When this bit is reset, the abnormal interrupt summary is disabled. + 14 + 1 + read-write + + + NIE + Normal Interrupt Summary Enable +When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMAC0SR: +Bit 0: Transmit Interrupt +Bit 2: Transmit Buffer Unavailable +Bit 6: Receive Interrupt +Bit 11: Early Receive Interrupt +When this bit is reset, the normal interrupt summary is disabled. + 15 + 1 + read-write + + + + + ETH_DMAC1CATXDR + ETH_DMAC1CATXDR + Channel 1 current application transmit descriptor register + 0x11c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Application Transmit Descriptor Address Pointer +The DMA updates this pointer during Tx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC1CATXBR + ETH_DMAC1CATXBR + Channel 1 current application transmit buffer register + 0x11d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Application Transmit Buffer Address Pointer +The DMA updates this pointer during Tx operation. This pointer is cleared on reset. + 0 + 32 + read-only + + + + + ETH_DMAC1SR + ETH_DMAC1SR + Channel 1 status register + 0x11e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI + Transmit Interrupt +This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. + 0 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TBU + Transmit Buffer Unavailable +This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit Process state transitions. +To resume processing the Transmit descriptors, the application should do the following: +1. Change the ownership of the descriptor by setting Bit 31 of TDES3. +2. Issue a Transmit Poll Demand command. +For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. + 2 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. +The reception remains in the Running state. + 6 + 1 + read-write + + + RBU + Receive Buffer Unavailable +This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. + 7 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Rx process enters the Stopped state. + 8 + 1 + read-write + + + RWT + Receive Watchdog Timeout +This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. + 9 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. + 10 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. The RI bit of this register automatically clears this bit. + 11 + 1 + read-write + + + FBE + Fatal Bus Error +This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. + 12 + 1 + read-write + + + CDE + Context Descriptor Error +This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor), and the DMA Tx engine ignored it. + 13 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMACiIER register: +Bit 1: Transmit Process Stopped +Bit 7: Receive Buffer Unavailable +Bit 8: Receive Process Stopped +Bit 10: Early Transmit Interrupt +Bit 12: Fatal Bus Error +Bit 13: Context Descriptor Error +Only unmasked bits affect the Abnormal Interrupt Summary bit. +This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 14 + 1 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMACiIER register: +Bit 0: Transmit Interrupt +Bit 2: Transmit Buffer Unavailable +Bit 6: Receive Interrupt +Bit 11: Early Receive Interrupt +Only unmasked bits (interrupts for which interrupt enable is set in ETH_DMACiIER register) affect the Normal Interrupt Summary bit. +This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. + 15 + 1 + read-write + + + TEB + Tx DMA Error Bits +This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. +Bit[2]: Error during data transfer by Tx DMA when '1', no when '0' +Bit[1]: Error during descriptor access when '1', Error during data buffer access when '0' +Bit[0]: Error during read transfer when '1', Error during write transfer when '0' +This field is valid only when the FBE bit is set. This field does not generate an interrupt. + 16 + 3 + read-only + + + REB + Rx DMA Error Bits +This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. +Bit [2]: Error during data transfer by Rx DMA when '1', no when '0' +Bit[1]: Error during descriptor access when '1', Error during data buffer access when '0' +Bit[0]: Error during read transfer when '1', Error during write transfer when '0' +This field is valid only when the FBE bit is set. This field does not generate an interrupt. + 19 + 3 + read-only + + + + + ETH_DMAC1MFCR + ETH_DMAC1MFCR + Channel 1 missed frame count register + 0x11ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MFC + Dropped Packet Counters +This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing +RPF field in ETH_DMAC0RXCR register. The counter gets cleared when this register is read. + 0 + 11 + read-only + + + MFCO + Overflow status of the MFC Counter +When this bit is set then the MFC counter does not get incremented +further. The bit gets cleared when this register is read. + 15 + 1 + read-only + + + + + + + ETH2 + 0x5800E000 + + ETH2 + Ethernet 2 global interrupt + 97 + + + ETH2_WKUP + Ethernet 2 wakeup interrupt (PMT) + 98 + + + + ETZPC + ETZPC + ETZPC + 0x5C007000 + + 0x0 + 0x400 + registers + + + + ETZPC_TZMA0_SIZE + ETZPC_TZMA0_SIZE + ETZPC ROM secure size definition + 0x0 + 0x20 + read-write + 0x000003FF + + + R0SIZE + R0SIZE + 0 + 10 + + + LOCK + LOCK + 31 + 1 + + + + + ETZPC_TZMA1_SIZE + ETZPC_TZMA1_SIZE + ETZPC RAM secure size definition + 0x4 + 0x20 + read-write + 0x000003FF + + + R0SIZE + R0SIZE + 0 + 10 + + + LOCK + LOCK + 31 + 1 + + + + + ETZPC_DECPROT0 + ETZPC_DECPROT0 + Register reset values + 0x10 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT1 + ETZPC_DECPROT1 + Register reset values + 0x14 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT2 + ETZPC_DECPROT2 + Register reset values + 0x18 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT3 + ETZPC_DECPROT3 + Register reset values + 0x1C + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT4 + ETZPC_DECPROT4 + Register reset values + 0x20 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT5 + ETZPC_DECPROT5 + Register reset values + 0x24 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT_LOCK0 + ETZPC_DECPROT_LOCK0 + ETZPC decprot lock 0 register + 0x30 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_DECPROT_LOCK1 + ETZPC_DECPROT_LOCK1 + ETZPC decprot lock 1 register + 0x34 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_DECPROT_LOCK2 + ETZPC_DECPROT_LOCK2 + ETZPC decprot lock 2 register + 0x38 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_HWCFGR + ETZPC_HWCFGR + ETZPC IP HW configuration register + 0x3F0 + 0x20 + read-only + 0x00006002 + + + NUM_TZMA + NUM_TZMA + 0 + 8 + + + NUM_PER_SEC + NUM_PER_SEC + 8 + 8 + + + NUM_AHB_SEC + NUM_AHB_SEC + 16 + 8 + + + CHUNKS1N4 + CHUNKS1N4 + 24 + 8 + + + + + ETZPC_VERR + ETZPC_VERR + ETZPC IP version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + ETZPC_IDR + ETZPC_IDR + ETZPC IP version register + 0x3F8 + 0x20 + read-only + 0x00100061 + + + ID + ID + 0 + 32 + + + + + ETZPC_SIDR + ETZPC_SIDR + ETZPC IP version register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + EXTI + EXTI + EXTI + 0x5000D000 + + 0x0 + 0x400 + registers + + + PVD_AVD + PVD AND AVD detector through EXTI + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI4 + EXTI Line 4 interrupt + 10 + + + EXTI5 + EXTI line 5 interrupt + 24 + + + EXTI10 + EXTI line 10 interrupt + 41 + + + EXTI11 + EXTI line 11 interrupt + 43 + + + EXTI6 + EXTI line 6 interrupt + 65 + + + EXTI7 + EXTI line 7 interrupt + 66 + + + EXTI8 + EXTI line 8 interrupt + 67 + + + EXTI9 + EXTI line 9 interrupt + 68 + + + EXTI12 + EXTI line 12 interrupt + 77 + + + EXTI13 + EXTI line 13 interrupt + 78 + + + EXTI14 + EXTI line 14 interrupt + 106 + + + EXTI15 + EXTI line 15 interrupt + 109 + + + + EXTI_RTSR1 + EXTI_RTSR1 + Contains only register bits for configurable events. + 0x0 + 0x20 + read-write + 0x00000000 + + + RT0 + RT0 + 0 + 1 + + + RT1 + RT1 + 1 + 1 + + + RT2 + RT2 + 2 + 1 + + + RT3 + RT3 + 3 + 1 + + + RT4 + RT4 + 4 + 1 + + + RT5 + RT5 + 5 + 1 + + + RT6 + RT6 + 6 + 1 + + + RT7 + RT7 + 7 + 1 + + + RT8 + RT8 + 8 + 1 + + + RT9 + RT9 + 9 + 1 + + + RT10 + RT10 + 10 + 1 + + + RT11 + RT11 + 11 + 1 + + + RT12 + RT12 + 12 + 1 + + + RT13 + RT13 + 13 + 1 + + + RT14 + RT14 + 14 + 1 + + + RT15 + RT15 + 15 + 1 + + + RT16 + RT16 + 16 + 1 + + + + + EXTI_FTSR1 + EXTI_FTSR1 + Contains only register bits for configurable events. + 0x4 + 0x20 + read-write + 0x00000000 + + + FT0 + FT0 + 0 + 1 + + + FT1 + FT1 + 1 + 1 + + + FT2 + FT2 + 2 + 1 + + + FT3 + FT3 + 3 + 1 + + + FT4 + FT4 + 4 + 1 + + + FT5 + FT5 + 5 + 1 + + + FT6 + FT6 + 6 + 1 + + + FT7 + FT7 + 7 + 1 + + + FT8 + FT8 + 8 + 1 + + + FT9 + FT9 + 9 + 1 + + + FT10 + FT10 + 10 + 1 + + + FT11 + FT11 + 11 + 1 + + + FT12 + FT12 + 12 + 1 + + + FT13 + FT13 + 13 + 1 + + + FT14 + FT14 + 14 + 1 + + + FT15 + FT15 + 15 + 1 + + + FT16 + FT16 + 16 + 1 + + + + + EXTI_SWIER1 + EXTI_SWIER1 + Contains only register bits for configurable events. + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI0 + SWI0 + 0 + 1 + + + SWI1 + SWI1 + 1 + 1 + + + SWI2 + SWI2 + 2 + 1 + + + SWI3 + SWI3 + 3 + 1 + + + SWI4 + SWI4 + 4 + 1 + + + SWI5 + SWI5 + 5 + 1 + + + SWI6 + SWI6 + 6 + 1 + + + SWI7 + SWI7 + 7 + 1 + + + SWI8 + SWI8 + 8 + 1 + + + SWI9 + SWI9 + 9 + 1 + + + SWI10 + SWI10 + 10 + 1 + + + SWI11 + SWI11 + 11 + 1 + + + SWI12 + SWI12 + 12 + 1 + + + SWI13 + SWI13 + 13 + 1 + + + SWI14 + SWI14 + 14 + 1 + + + SWI15 + SWI15 + 15 + 1 + + + SWI16 + SWI16 + 16 + 1 + + + + + EXTI_RPR1 + EXTI_RPR1 + Contains only register bits for configurable events. + 0xC + 0x20 + read-write + 0x00000000 + + + RPIF0 + RPIF0 + 0 + 1 + + + RPIF1 + RPIF1 + 1 + 1 + + + RPIF2 + RPIF2 + 2 + 1 + + + RPIF3 + RPIF3 + 3 + 1 + + + RPIF4 + RPIF4 + 4 + 1 + + + RPIF5 + RPIF5 + 5 + 1 + + + RPIF6 + RPIF6 + 6 + 1 + + + RPIF7 + RPIF7 + 7 + 1 + + + RPIF8 + RPIF8 + 8 + 1 + + + RPIF9 + RPIF9 + 9 + 1 + + + RPIF10 + RPIF10 + 10 + 1 + + + RPIF11 + RPIF11 + 11 + 1 + + + RPIF12 + RPIF12 + 12 + 1 + + + RPIF13 + RPIF13 + 13 + 1 + + + RPIF14 + RPIF14 + 14 + 1 + + + RPIF15 + RPIF15 + 15 + 1 + + + RPIF16 + RPIF16 + 16 + 1 + + + + + EXTI_FPR1 + EXTI_FPR1 + Contains only register bits for configurable events. + 0x10 + 0x20 + read-write + 0x00000000 + + + FPIF0 + FPIF0 + 0 + 1 + + + FPIF1 + FPIF1 + 1 + 1 + + + FPIF2 + FPIF2 + 2 + 1 + + + FPIF3 + FPIF3 + 3 + 1 + + + FPIF4 + FPIF4 + 4 + 1 + + + FPIF5 + FPIF5 + 5 + 1 + + + FPIF6 + FPIF6 + 6 + 1 + + + FPIF7 + FPIF7 + 7 + 1 + + + FPIF8 + FPIF8 + 8 + 1 + + + FPIF9 + FPIF9 + 9 + 1 + + + FPIF10 + FPIF10 + 10 + 1 + + + FPIF11 + FPIF11 + 11 + 1 + + + FPIF12 + FPIF12 + 12 + 1 + + + FPIF13 + FPIF13 + 13 + 1 + + + FPIF14 + FPIF14 + 14 + 1 + + + FPIF15 + FPIF15 + 15 + 1 + + + FPIF16 + FPIF16 + 16 + 1 + + + + + EXTI_TZENR1 + EXTI_TZENR1 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x14 + 0x20 + read-write + 0x00000000 + + + TZEN0 + TZEN0 + 0 + 1 + + + TZEN1 + TZEN1 + 1 + 1 + + + TZEN2 + TZEN2 + 2 + 1 + + + TZEN3 + TZEN3 + 3 + 1 + + + TZEN4 + TZEN4 + 4 + 1 + + + TZEN5 + TZEN5 + 5 + 1 + + + TZEN6 + TZEN6 + 6 + 1 + + + TZEN7 + TZEN7 + 7 + 1 + + + TZEN8 + TZEN8 + 8 + 1 + + + TZEN9 + TZEN9 + 9 + 1 + + + TZEN10 + TZEN10 + 10 + 1 + + + TZEN11 + TZEN11 + 11 + 1 + + + TZEN12 + TZEN12 + 12 + 1 + + + TZEN13 + TZEN13 + 13 + 1 + + + TZEN14 + TZEN14 + 14 + 1 + + + TZEN15 + TZEN15 + 15 + 1 + + + TZEN17 + TZEN17 + 17 + 1 + + + TZEN18 + TZEN18 + 18 + 1 + + + TZEN19 + TZEN19 + 19 + 1 + + + TZEN24 + TZEN24 + 24 + 1 + + + TZEN26 + TZEN26 + 26 + 1 + + + + + EXTI_RTSR2 + EXTI_RTSR2 + Contains only register bits for configurable events. + 0x20 + 0x20 + read-write + 0x00000000 + + + EXTI_FTSR2 + EXTI_FTSR2 + Contains only register bits for configurable events. + 0x24 + 0x20 + read-write + 0x00000000 + + + EXTI_SWIER2 + EXTI_SWIER2 + Contains only register bits for configurable events. + 0x28 + 0x20 + read-write + 0x00000000 + + + EXTI_RPR2 + EXTI_RPR2 + Contains only register bits for configurable events. + 0x2C + 0x20 + read-write + 0x00000000 + + + EXTI_FPR2 + EXTI_FPR2 + Contains only register bits for configurable events. + 0x30 + 0x20 + read-write + 0x00000000 + + + EXTI_TZENR2 + EXTI_TZENR2 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x34 + 0x20 + read-write + 0x00000000 + + + TZEN41 + TZEN41 + 9 + 1 + + + TZEN54 + TZEN54 + 22 + 1 + + + TZEN55 + TZEN55 + 23 + 1 + + + TZEN56 + TZEN56 + 24 + 1 + + + TZEN57 + TZEN57 + 25 + 1 + + + TZEN58 + TZEN58 + 26 + 1 + + + TZEN59 + TZEN59 + 27 + 1 + + + TZEN60 + TZEN60 + 28 + 1 + + + + + EXTI_RTSR3 + EXTI_RTSR3 + Contains only register bits for configurable events. + 0x40 + 0x20 + read-write + 0x00000000 + + + RT65 + RT65 + 1 + 1 + + + RT66 + RT66 + 2 + 1 + + + RT68 + RT68 + 4 + 1 + + + RT73 + RT73 + 9 + 1 + + + RT74 + RT74 + 10 + 1 + + + + + EXTI_FTSR3 + EXTI_FTSR3 + Contains only register bits for configurable events. + 0x44 + 0x20 + read-write + 0x00000000 + + + FT65 + FT65 + 1 + 1 + + + FT66 + FT66 + 2 + 1 + + + FT68 + FT68 + 4 + 1 + + + FT73 + FT73 + 9 + 1 + + + FT74 + FT74 + 10 + 1 + + + + + EXTI_SWIER3 + EXTI_SWIER3 + Contains only register bits for configurable events. + 0x48 + 0x20 + read-write + 0x00000000 + + + SWI65 + SWI65 + 1 + 1 + + + SWI66 + SWI66 + 2 + 1 + + + SWI68 + SWI68 + 4 + 1 + + + SWI73 + SWI73 + 9 + 1 + + + SWI74 + SWI74 + 10 + 1 + + + + + EXTI_RPR3 + EXTI_RPR3 + Contains only register bits for configurable events. + 0x4C + 0x20 + read-write + 0x00000000 + + + RPIF65 + RPIF65 + 1 + 1 + + + RPIF66 + RPIF66 + 2 + 1 + + + RPIF68 + RPIF68 + 4 + 1 + + + RPIF73 + RPIF73 + 9 + 1 + + + RPIF74 + RPIF74 + 10 + 1 + + + + + EXTI_FPR3 + EXTI_FPR3 + Contains only register bits for configurable events. + 0x50 + 0x20 + read-write + 0x00000000 + + + FPIF65 + FPIF65 + 1 + 1 + + + FPIF66 + FPIF66 + 2 + 1 + + + FPIF68 + FPIF68 + 4 + 1 + + + FPIF73 + FPIF73 + 9 + 1 + + + FPIF74 + FPIF74 + 10 + 1 + + + + + EXTI_TZENR3 + EXTI_TZENR3 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x54 + 0x20 + read-write + 0x00000000 + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x60 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 + 0 + 8 + + + EXTI1 + EXTI1 + 8 + 8 + + + EXTI2 + EXTI2 + 16 + 8 + + + EXTI3 + EXTI3 + 24 + 8 + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x64 + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 + 0 + 8 + + + EXTI5 + EXTI5 + 8 + 8 + + + EXTI6 + EXTI6 + 16 + 8 + + + EXTI7 + EXTI7 + 24 + 8 + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x68 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 + 0 + 8 + + + EXTI9 + EXTI9 + 8 + 8 + + + EXTI10 + EXTI10 + 16 + 8 + + + EXTI11 + EXTI11 + 24 + 8 + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x6C + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 + 0 + 8 + + + EXTI13 + EXTI13 + 8 + 8 + + + EXTI14 + EXTI14 + 16 + 8 + + + EXTI15 + EXTI15 + 24 + 8 + + + + + EXTI_IMR1 + EXTI_IMR1 + Contains register bits for configurable events and Direct events. + 0x80 + 0x20 + read-write + 0xFFFE0000 + + + IM0 + IM0 + 0 + 1 + + + IM1 + IM1 + 1 + 1 + + + IM2 + IM2 + 2 + 1 + + + IM3 + IM3 + 3 + 1 + + + IM4 + IM4 + 4 + 1 + + + IM5 + IM5 + 5 + 1 + + + IM6 + IM6 + 6 + 1 + + + IM7 + IM7 + 7 + 1 + + + IM8 + IM8 + 8 + 1 + + + IM9 + IM9 + 9 + 1 + + + IM10 + IM10 + 10 + 1 + + + IM11 + IM11 + 11 + 1 + + + IM12 + IM12 + 12 + 1 + + + IM13 + IM13 + 13 + 1 + + + IM14 + IM14 + 14 + 1 + + + IM15 + IM15 + 15 + 1 + + + IM16 + IM16 + 16 + 1 + + + IM17 + IM17 + 17 + 1 + + + IM18 + IM18 + 18 + 1 + + + IM19 + IM19 + 19 + 1 + + + IM20 + IM20 + 20 + 1 + + + IM21 + IM21 + 21 + 1 + + + IM22 + IM22 + 22 + 1 + + + IM23 + IM23 + 23 + 1 + + + IM24 + IM24 + 24 + 1 + + + IM25 + IM25 + 25 + 1 + + + IM26 + IM26 + 26 + 1 + + + IM27 + IM27 + 27 + 1 + + + IM28 + IM28 + 28 + 1 + + + IM29 + IM29 + 29 + 1 + + + IM30 + IM30 + 30 + 1 + + + IM31 + IM31 + 31 + 1 + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wakeup with event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + EM0 + EM0 + 0 + 1 + + + EM1 + EM1 + 1 + 1 + + + EM2 + EM2 + 2 + 1 + + + EM3 + EM3 + 3 + 1 + + + EM4 + EM4 + 4 + 1 + + + EM5 + EM5 + 5 + 1 + + + EM6 + EM6 + 6 + 1 + + + EM7 + EM7 + 7 + 1 + + + EM8 + EM8 + 8 + 1 + + + EM9 + EM9 + 9 + 1 + + + EM10 + EM10 + 10 + 1 + + + EM11 + EM11 + 11 + 1 + + + EM12 + EM12 + 12 + 1 + + + EM13 + EM13 + 13 + 1 + + + EM14 + EM14 + 14 + 1 + + + EM15 + EM15 + 15 + 1 + + + EM17 + EM17 + 17 + 1 + + + EM18 + EM18 + 18 + 1 + + + EM19 + EM19 + 19 + 1 + + + + + EXTI_IMR2 + EXTI_IMR2 + Contains register bits for configurable events and direct events. + 0x90 + 0x20 + read-write + 0xFFFFFFFF + + + IM32 + IM32 + 0 + 1 + + + IM33 + IM33 + 1 + 1 + + + IM34 + IM34 + 2 + 1 + + + IM35 + IM35 + 3 + 1 + + + IM36 + IM36 + 4 + 1 + + + IM37 + IM37 + 5 + 1 + + + IM38 + IM38 + 6 + 1 + + + IM39 + IM39 + 7 + 1 + + + IM40 + IM40 + 8 + 1 + + + IM41 + IM41 + 9 + 1 + + + IM42 + IM42 + 10 + 1 + + + IM43 + IM43 + 11 + 1 + + + IM44 + IM44 + 12 + 1 + + + IM45 + IM45 + 13 + 1 + + + IM46 + IM46 + 14 + 1 + + + IM47 + IM47 + 15 + 1 + + + IM48 + IM48 + 16 + 1 + + + IM49 + IM49 + 17 + 1 + + + IM50 + IM50 + 18 + 1 + + + IM51 + IM51 + 19 + 1 + + + IM52 + IM52 + 20 + 1 + + + IM53 + IM53 + 21 + 1 + + + IM54 + IM54 + 22 + 1 + + + IM55 + IM55 + 23 + 1 + + + IM56 + IM56 + 24 + 1 + + + IM57 + IM57 + 25 + 1 + + + IM58 + IM58 + 26 + 1 + + + IM59 + IM59 + 27 + 1 + + + IM60 + IM60 + 28 + 1 + + + IM61 + IM61 + 29 + 1 + + + IM62 + IM62 + 30 + 1 + + + IM63 + IM63 + 31 + 1 + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wakeup with event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + EXTI_IMR3 + EXTI_IMR3 + Contains register bits for configurable events and direct events. + 0xA0 + 0x20 + read-write + 0x00000DE9 + + + IM64 + IM64 + 0 + 1 + + + IM65 + IM65 + 1 + 1 + + + IM66 + IM66 + 2 + 1 + + + IM67 + IM67 + 3 + 1 + + + IM68 + IM68 + 4 + 1 + + + IM69 + IM69 + 5 + 1 + + + IM70 + IM70 + 6 + 1 + + + IM71 + IM71 + 7 + 1 + + + IM72 + IM72 + 8 + 1 + + + IM73 + IM73 + 9 + 1 + + + IM74 + IM74 + 10 + 1 + + + IM75 + IM75 + 11 + 1 + + + + + EXTI_EMR3 + EXTI_EMR3 + EXTI CPU wakeup with event mask register + 0xA4 + 0x20 + read-write + 0x00000000 + + + EM66 + EM66 + 2 + 1 + + + + + EXTI_C2IMR1 + EXTI_C2IMR1 + Contains register bits for configurable events and Direct events. + 0xC0 + 0x20 + read-write + 0xFFFE0000 + + + IM0 + IM0 + 0 + 1 + + + IM1 + IM1 + 1 + 1 + + + IM2 + IM2 + 2 + 1 + + + IM3 + IM3 + 3 + 1 + + + IM4 + IM4 + 4 + 1 + + + IM5 + IM5 + 5 + 1 + + + IM6 + IM6 + 6 + 1 + + + IM7 + IM7 + 7 + 1 + + + IM8 + IM8 + 8 + 1 + + + IM9 + IM9 + 9 + 1 + + + IM10 + IM10 + 10 + 1 + + + IM11 + IM11 + 11 + 1 + + + IM12 + IM12 + 12 + 1 + + + IM13 + IM13 + 13 + 1 + + + IM14 + IM14 + 14 + 1 + + + IM15 + IM15 + 15 + 1 + + + IM16 + IM16 + 16 + 1 + + + IM17 + IM17 + 17 + 1 + + + IM18 + IM18 + 18 + 1 + + + IM19 + IM19 + 19 + 1 + + + IM20 + IM20 + 20 + 1 + + + IM21 + IM21 + 21 + 1 + + + IM22 + IM22 + 22 + 1 + + + IM23 + IM23 + 23 + 1 + + + IM24 + IM24 + 24 + 1 + + + IM25 + IM25 + 25 + 1 + + + IM26 + IM26 + 26 + 1 + + + IM27 + IM27 + 27 + 1 + + + IM28 + IM28 + 28 + 1 + + + IM29 + IM29 + 29 + 1 + + + IM30 + IM30 + 30 + 1 + + + IM31 + IM31 + 31 + 1 + + + + + EXTI_C2EMR1 + EXTI_C2EMR1 + EXTI CPU2 wakeup with event mask register + 0xC4 + 0x20 + read-write + 0x00000000 + + + EM0 + EM0 + 0 + 1 + + + EM1 + EM1 + 1 + 1 + + + EM2 + EM2 + 2 + 1 + + + EM3 + EM3 + 3 + 1 + + + EM4 + EM4 + 4 + 1 + + + EM5 + EM5 + 5 + 1 + + + EM6 + EM6 + 6 + 1 + + + EM7 + EM7 + 7 + 1 + + + EM8 + EM8 + 8 + 1 + + + EM9 + EM9 + 9 + 1 + + + EM10 + EM10 + 10 + 1 + + + EM11 + EM11 + 11 + 1 + + + EM12 + EM12 + 12 + 1 + + + EM13 + EM13 + 13 + 1 + + + EM14 + EM14 + 14 + 1 + + + EM15 + EM15 + 15 + 1 + + + EM17 + EM17 + 17 + 1 + + + EM18 + EM18 + 18 + 1 + + + EM19 + EM19 + 19 + 1 + + + + + EXTI_C2IMR2 + EXTI_C2IMR2 + Contains register bits for configurable events and direct events. + 0xD0 + 0x20 + read-write + 0xFFFFFFFF + + + IM32 + IM32 + 0 + 1 + + + IM33 + IM33 + 1 + 1 + + + IM34 + IM34 + 2 + 1 + + + IM35 + IM35 + 3 + 1 + + + IM36 + IM36 + 4 + 1 + + + IM37 + IM37 + 5 + 1 + + + IM38 + IM38 + 6 + 1 + + + IM39 + IM39 + 7 + 1 + + + IM40 + IM40 + 8 + 1 + + + IM41 + IM41 + 9 + 1 + + + IM42 + IM42 + 10 + 1 + + + IM43 + IM43 + 11 + 1 + + + IM44 + IM44 + 12 + 1 + + + IM45 + IM45 + 13 + 1 + + + IM46 + IM46 + 14 + 1 + + + IM47 + IM47 + 15 + 1 + + + IM48 + IM48 + 16 + 1 + + + IM49 + IM49 + 17 + 1 + + + IM50 + IM50 + 18 + 1 + + + IM51 + IM51 + 19 + 1 + + + IM52 + IM52 + 20 + 1 + + + IM53 + IM53 + 21 + 1 + + + IM54 + IM54 + 22 + 1 + + + IM55 + IM55 + 23 + 1 + + + IM56 + IM56 + 24 + 1 + + + IM57 + IM57 + 25 + 1 + + + IM58 + IM58 + 26 + 1 + + + IM59 + IM59 + 27 + 1 + + + IM60 + IM60 + 28 + 1 + + + IM61 + IM61 + 29 + 1 + + + IM62 + IM62 + 30 + 1 + + + IM63 + IM63 + 31 + 1 + + + + + EXTI_C2EMR2 + EXTI_C2EMR2 + EXTI CPU2 wakeup with event mask register + 0xD4 + 0x20 + read-write + 0x00000000 + + + EXTI_C2IMR3 + EXTI_C2IMR3 + Contains register bits for configurable events and direct events. + 0xE0 + 0x20 + read-write + 0x00000DE9 + + + IM64 + IM64 + 0 + 1 + + + IM65 + IM65 + 1 + 1 + + + IM66 + IM66 + 2 + 1 + + + IM67 + IM67 + 3 + 1 + + + IM68 + IM68 + 4 + 1 + + + IM69 + IM69 + 5 + 1 + + + IM70 + IM70 + 6 + 1 + + + IM71 + IM71 + 7 + 1 + + + IM72 + IM72 + 8 + 1 + + + IM73 + IM73 + 9 + 1 + + + IM74 + IM74 + 10 + 1 + + + IM75 + IM75 + 11 + 1 + + + + + EXTI_C2EMR3 + EXTI_C2EMR3 + EXTI CPU2 wakeup with event mask register + 0xE4 + 0x20 + read-write + 0x00000000 + + + EM66 + EM66 + 2 + 1 + + + + + EXTI_HWCFGR13 + EXTI_HWCFGR13 + EXTI hardware configuration register 13 + 0x3C0 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR12 + EXTI_HWCFGR12 + EXTI hardware configuration register 12 + 0x3C4 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR11 + EXTI_HWCFGR11 + EXTI hardware configuration register 11 + 0x3C8 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR10 + EXTI_HWCFGR10 + EXTI hardware configuration register 10 + 0x3CC + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR9 + EXTI_HWCFGR9 + EXTI hardware configuration register 9 + 0x3D0 + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR8 + EXTI_HWCFGR8 + EXTI hardware configuration register 8 + 0x3D4 + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR7 + EXTI_HWCFGR7 + EXTI hardware configuration register 7 + 0x3D8 + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR6 + EXTI_HWCFGR6 + EXTI hardware configuration register 6 + 0x3DC + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR5 + EXTI_HWCFGR5 + EXTI hardware configuration register 5 + 0x3E0 + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR4 + EXTI_HWCFGR4 + EXTI hardware configuration register 4 + 0x3E4 + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR3 + EXTI_HWCFGR3 + EXTI hardware configuration register 3 + 0x3E8 + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR2 + EXTI_HWCFGR2 + EXTI hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR1 + EXTI_HWCFGR1 + EXTI hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x000B214B + + + NBEVENTS + NBEVENTS + 0 + 8 + + + NBCPUS + NBCPUS + 8 + 4 + + + CPUEVTEN + CPUEVTEN + 12 + 4 + + + NBIOPORT + NBIOPORT + 16 + 8 + + + + + EXTI_VERR + EXTI_VERR + EXTI IP version register + 0x3F4 + 0x20 + read-only + 0x00000030 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + EXTI_IPIDR + EXTI_IPIDR + EXTI identification register + 0x3F8 + 0x20 + read-only + 0x000E0001 + + + IPID + IPID + 0 + 32 + + + + + EXTI_SIDR + EXTI_SIDR + EXTI size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + FDCAN1 + FDCAN1 + FDCAN1 + 0x4400E000 + + 0x0 + 0x400 + registers + + + FDCAN1_IT0 + FDCAN1 interrupt 0 + 20 + + + FDCAN1_IT1 + FDCAN1 interrupt 1 + 22 + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0 + 0x20 + read-only + 0x32141218 + + + DAY + DAY + 0 + 8 + + + MON + MON + 8 + 8 + + + YEAR + YEAR + 16 + 4 + + + SUBSTEP + SUBSTEP + 20 + 4 + + + STEP + STEP + 24 + 4 + + + REL + REL + 28 + 4 + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN Endian register + 0x4 + 0x20 + read-only + 0x87654321 + + + ETV + ETV + 0 + 32 + + + + + FDCAN_DBTP + FDCAN_DBTP + This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. + 0xC + 0x20 + read-write + 0x00000A33 + + + DSJW + DSJW + 0 + 4 + + + DTSEG2 + DTSEG2 + 4 + 4 + + + DTSEG1 + DTSEG1 + 8 + 5 + + + DBRP + DBRP + 16 + 5 + + + TDC + TDC + 23 + 1 + + + + + FDCAN_TEST + FDCAN_TEST + Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. + 0x10 + 0x20 + 0x00000000 + + + LBCK + LBCK + 4 + 1 + read-write + + + TX + TX + 5 + 2 + read-write + + + RX + RX + 7 + 1 + read-only + + + + + FDCAN_RWD + FDCAN_RWD + The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. + 0x14 + 0x20 + 0x00000000 + + + WDC + WDC + 0 + 8 + read-write + + + WDV + WDV + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + For details about setting and resetting of single bits see Software initialization. + 0x18 + 0x20 + 0x00000001 + + + INIT + INIT + 0 + 1 + read-write + + + CCE + CCE + 1 + 1 + read-write + + + ASM + ASM + 2 + 1 + read-write + + + CSA + CSA + 3 + 1 + read-only + + + CSR + CSR + 4 + 1 + read-write + + + MON + MON + 5 + 1 + read-write + + + DAR + DAR + 6 + 1 + read-write + + + TEST + TEST + 7 + 1 + read-write + + + FDOE + FDOE + 8 + 1 + read-write + + + BRSE + BRSE + 9 + 1 + read-write + + + PXHD + PXHD + 12 + 1 + read-write + + + EFBI + EFBI + 13 + 1 + read-write + + + TXP + TXP + 14 + 1 + read-write + + + NISO + NISO + 15 + 1 + read-write + + + + + FDCAN_NBTP + FDCAN_NBTP + This register is dedicated to the nominal bit timing used during the arbitration phase. + 0x1C + 0x20 + read-write + 0x00000A33 + + + NTSEG2 + NTSEG2 + 0 + 7 + + + NTSEG1 + NTSEG1 + 8 + 8 + + + NBRP + NBRP + 16 + 9 + + + NSJW + NSJW + 25 + 7 + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 2 + + + TCP + TCP + 16 + 4 + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x24 + 0x20 + read-write + 0x00000000 + + + TSC + TSC + 0 + 16 + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x28 + 0x20 + read-write + 0xFFFF0000 + + + ETOC + ETOC + 0 + 1 + + + TOS + TOS + 1 + 2 + + + TOP + TOP + 16 + 16 + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + TOC + TOC + 0 + 16 + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x40 + 0x20 + 0x00000000 + + + TEC + TEC + 0 + 8 + read-only + + + TREC + TREC + 8 + 7 + read-only + + + RP + RP + 15 + 1 + read-only + + + CEL + CEL + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x44 + 0x20 + 0x00000707 + + + LEC + LEC + 0 + 3 + read-only + + + ACT + ACT + 3 + 2 + read-only + + + EP + EP + 5 + 1 + read-only + + + EW + EW + 6 + 1 + read-only + + + BO + BO + 7 + 1 + read-only + + + DLEC + DLEC + 8 + 3 + read-only + + + RESI + RESI + 11 + 1 + read-write + + + RBRS + RBRS + 12 + 1 + read-write + + + REDL + REDL + 13 + 1 + read-write + + + PXE + PXE + 14 + 1 + read-write + + + TDCV + TDCV + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x48 + 0x20 + read-write + 0x00000000 + + + TDCF + TDCF + 0 + 7 + + + TDCO + TDCO + 8 + 7 + + + + + FDCAN_IR + FDCAN_IR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. + 0x50 + 0x20 + read-write + 0x00000000 + + + RF0N + RF0N + 0 + 1 + + + RF0W + RF0W + 1 + 1 + + + RF0F + RF0F + 2 + 1 + + + RF0L + RF0L + 3 + 1 + + + RF1N + RF1N + 4 + 1 + + + RF1W + RF1W + 5 + 1 + + + RF1F + RF1F + 6 + 1 + + + RF1L + RF1L + 7 + 1 + + + HPM + HPM + 8 + 1 + + + TC + TC + 9 + 1 + + + TCF + TCF + 10 + 1 + + + TFE + TFE + 11 + 1 + + + TEFN + TEFN + 12 + 1 + + + TEFW + TEFW + 13 + 1 + + + TEFF + TEFF + 14 + 1 + + + TEFL + TEFL + 15 + 1 + + + TSW + TSW + 16 + 1 + + + MRAF + MRAF + 17 + 1 + + + TOO + TOO + 18 + 1 + + + DRX + DRX + 19 + 1 + + + ELO + ELO + 22 + 1 + + + EP + EP + 23 + 1 + + + EW + EW + 24 + 1 + + + BO + BO + 25 + 1 + + + WDI + WDI + 26 + 1 + + + PEA + PEA + 27 + 1 + + + PED + PED + 28 + 1 + + + ARA + ARA + 29 + 1 + + + + + FDCAN_IE + FDCAN_IE + The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. + 0x54 + 0x20 + read-write + 0x00000000 + + + RF0NE + RF0NE + 0 + 1 + + + RF0WE + RF0WE + 1 + 1 + + + RF0FE + RF0FE + 2 + 1 + + + RF0LE + RF0LE + 3 + 1 + + + RF1NE + RF1NE + 4 + 1 + + + RF1WE + RF1WE + 5 + 1 + + + RF1FE + RF1FE + 6 + 1 + + + RF1LE + RF1LE + 7 + 1 + + + HPME + HPME + 8 + 1 + + + TCE + TCE + 9 + 1 + + + TCFE + TCFE + 10 + 1 + + + TFEE + TFEE + 11 + 1 + + + TEFNE + TEFNE + 12 + 1 + + + TEFWE + TEFWE + 13 + 1 + + + TEFFE + TEFFE + 14 + 1 + + + TEFLE + TEFLE + 15 + 1 + + + TSWE + TSWE + 16 + 1 + + + MRAFE + MRAFE + 17 + 1 + + + TOOE + TOOE + 18 + 1 + + + DRXE + DRXE + 19 + 1 + + + BECE + BECE + 20 + 1 + + + BEUE + BEUE + 21 + 1 + + + ELOE + ELOE + 22 + 1 + + + EPE + EPE + 23 + 1 + + + EWE + EWE + 24 + 1 + + + BOE + BOE + 25 + 1 + + + WDIE + WDIE + 26 + 1 + + + PEAE + PEAE + 27 + 1 + + + PEDE + PEDE + 28 + 1 + + + ARAE + ARAE + 29 + 1 + + + + + FDCAN_ILS + FDCAN_ILS + This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. + 0x58 + 0x20 + read-write + 0x00000000 + + + RF0NL + RF0NL + 0 + 1 + + + RF0WL + RF0WL + 1 + 1 + + + RF0FL + RF0FL + 2 + 1 + + + RF0LL + RF0LL + 3 + 1 + + + RF1NL + RF1NL + 4 + 1 + + + RF1WL + RF1WL + 5 + 1 + + + RF1FL + RF1FL + 6 + 1 + + + RF1LL + RF1LL + 7 + 1 + + + HPML + HPML + 8 + 1 + + + TCL + TCL + 9 + 1 + + + TCFL + TCFL + 10 + 1 + + + TFEL + TFEL + 11 + 1 + + + TEFNL + TEFNL + 12 + 1 + + + TEFWL + TEFWL + 13 + 1 + + + TEFFL + TEFFL + 14 + 1 + + + TEFLL + TEFLL + 15 + 1 + + + TSWL + TSWL + 16 + 1 + + + MRAFL + MRAFL + 17 + 1 + + + TOOL + TOOL + 18 + 1 + + + DRXL + DRXL + 19 + 1 + + + BECL + BECL + 20 + 1 + + + BEUL + BEUL + 21 + 1 + + + ELOL + ELOL + 22 + 1 + + + EPL + EPL + 23 + 1 + + + EWL + EWL + 24 + 1 + + + BOL + BOL + 25 + 1 + + + WDIL + WDIL + 26 + 1 + + + PEAL + PEAL + 27 + 1 + + + PEDL + PEDL + 28 + 1 + + + ARAL + ARAL + 29 + 1 + + + + + FDCAN_ILE + FDCAN_ILE + Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. + 0x5C + 0x20 + read-write + 0x00000000 + + + EINT0 + EINT0 + 0 + 1 + + + EINT1 + EINT1 + 1 + 1 + + + + + FDCAN_GFC + FDCAN_GFC + Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. + 0x80 + 0x20 + read-write + 0x00000000 + + + RRFE + RRFE + 0 + 1 + + + RRFS + RRFS + 1 + 1 + + + ANFE + ANFE + 2 + 2 + + + ANFS + ANFS + 4 + 2 + + + + + FDCAN_SIDFC + FDCAN_SIDFC + Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. + 0x84 + 0x20 + read-write + 0x00000000 + + + FLSSA + FLSSA + 2 + 14 + + + LSS + LSS + 16 + 8 + + + + + FDCAN_XIDFC + FDCAN_XIDFC + Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. + 0x88 + 0x20 + read-write + 0x00000000 + + + FLESA + FLESA + 2 + 14 + + + LSE + LSE + 16 + 8 + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x90 + 0x20 + read-write + 0x1FFFFFFF + + + EIDM + EIDM + 0 + 29 + + + + + FDCAN_HPMS + FDCAN_HPMS + This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. + 0x94 + 0x20 + read-only + 0x00000000 + + + BIDX + BIDX + 0 + 6 + + + MSI + MSI + 6 + 2 + + + FIDX + FIDX + 8 + 7 + + + FLST + FLST + 15 + 1 + + + + + FDCAN_NDAT1 + FDCAN_NDAT1 + FDCAN new data 1 register + 0x98 + 0x20 + read-write + 0x00000000 + + + ND0 + ND0 + 0 + 1 + + + ND1 + ND1 + 1 + 1 + + + ND2 + ND2 + 2 + 1 + + + ND3 + ND3 + 3 + 1 + + + ND4 + ND4 + 4 + 1 + + + ND5 + ND5 + 5 + 1 + + + ND6 + ND6 + 6 + 1 + + + ND7 + ND7 + 7 + 1 + + + ND8 + ND8 + 8 + 1 + + + ND9 + ND9 + 9 + 1 + + + ND10 + ND10 + 10 + 1 + + + ND11 + ND11 + 11 + 1 + + + ND12 + ND12 + 12 + 1 + + + ND13 + ND13 + 13 + 1 + + + ND14 + ND14 + 14 + 1 + + + ND15 + ND15 + 15 + 1 + + + ND16 + ND16 + 16 + 1 + + + ND17 + ND17 + 17 + 1 + + + ND18 + ND18 + 18 + 1 + + + ND19 + ND19 + 19 + 1 + + + ND20 + ND20 + 20 + 1 + + + ND21 + ND21 + 21 + 1 + + + ND22 + ND22 + 22 + 1 + + + ND23 + ND23 + 23 + 1 + + + ND24 + ND24 + 24 + 1 + + + ND25 + ND25 + 25 + 1 + + + ND26 + ND26 + 26 + 1 + + + ND27 + ND27 + 27 + 1 + + + ND28 + ND28 + 28 + 1 + + + ND29 + ND29 + 29 + 1 + + + ND30 + ND30 + 30 + 1 + + + ND31 + ND31 + 31 + 1 + + + + + FDCAN_NDAT2 + FDCAN_NDAT2 + FDCAN new data 2 register + 0x9C + 0x20 + read-write + 0x00000000 + + + ND32 + ND32 + 0 + 1 + + + ND33 + ND33 + 1 + 1 + + + ND34 + ND34 + 2 + 1 + + + ND35 + ND35 + 3 + 1 + + + ND36 + ND36 + 4 + 1 + + + ND37 + ND37 + 5 + 1 + + + ND38 + ND38 + 6 + 1 + + + ND39 + ND39 + 7 + 1 + + + ND40 + ND40 + 8 + 1 + + + ND41 + ND41 + 9 + 1 + + + ND42 + ND42 + 10 + 1 + + + ND43 + ND43 + 11 + 1 + + + ND44 + ND44 + 12 + 1 + + + ND45 + ND45 + 13 + 1 + + + ND46 + ND46 + 14 + 1 + + + ND47 + ND47 + 15 + 1 + + + ND48 + ND48 + 16 + 1 + + + ND49 + ND49 + 17 + 1 + + + ND50 + ND50 + 18 + 1 + + + ND51 + ND51 + 19 + 1 + + + ND52 + ND52 + 20 + 1 + + + ND53 + ND53 + 21 + 1 + + + ND54 + ND54 + 22 + 1 + + + ND55 + ND55 + 23 + 1 + + + ND56 + ND56 + 24 + 1 + + + ND57 + ND57 + 25 + 1 + + + ND58 + ND58 + 26 + 1 + + + ND59 + ND59 + 27 + 1 + + + ND60 + ND60 + 28 + 1 + + + ND61 + ND61 + 29 + 1 + + + ND62 + ND62 + 30 + 1 + + + ND63 + ND63 + 31 + 1 + + + + + FDCAN_RXF0C + FDCAN_RXF0C + FDCAN Rx FIFO 0 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + F0SA + F0SA + 2 + 14 + + + F0S + F0S + 16 + 7 + + + F0WM + F0WM + 24 + 7 + + + F0OM + F0OM + 31 + 1 + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0xA4 + 0x20 + read-write + 0x00000000 + + + F0FL + F0FL + 0 + 7 + + + F0GI + F0GI + 8 + 6 + + + F0PI + F0PI + 16 + 6 + + + F0F + F0F + 24 + 1 + + + RF0L + RF0L + 25 + 1 + + + + + FDCAN_RXF0A + FDCAN_RXF0A + FDCAN Rx FIFO 0 acknowledge register + 0xA8 + 0x20 + read-write + 0x00000000 + + + F0AI + F0AI + 0 + 6 + + + + + FDCAN_RXBC + FDCAN_RXBC + FDCAN Rx buffer configuration register + 0xAC + 0x20 + read-write + 0x00000000 + + + RBSA + RBSA + 2 + 14 + + + + + FDCAN_RXF1C + FDCAN_RXF1C + FDCAN Rx FIFO 1 configuration register + 0xB0 + 0x20 + read-write + 0x00000000 + + + F1SA + F1SA + 2 + 14 + + + F1S + F1S + 16 + 7 + + + F1WM + F1WM + 24 + 7 + + + F1OM + F1OM + 31 + 1 + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0xB4 + 0x20 + read-only + 0x00000000 + + + F1FL + F1FL + 0 + 7 + + + F1GI + F1GI + 8 + 6 + + + F1PI + F1PI + 16 + 6 + + + F1F + F1F + 24 + 1 + + + RF1L + RF1L + 25 + 1 + + + DMS + DMS + 30 + 2 + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0xB8 + 0x20 + read-write + 0x00000000 + + + F1AI + F1AI + 0 + 6 + + + + + FDCAN_RXESC + FDCAN_RXESC + Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. + 0xBC + 0x20 + read-only + 0x00000000 + + + F0DS + F0DS + 0 + 3 + + + F1DS + F1DS + 4 + 3 + + + RBDS + RBDS + 8 + 3 + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0xC0 + 0x20 + read-write + 0x00000000 + + + TBSA + TBSA + 2 + 14 + + + NDTB + NDTB + 16 + 6 + + + TFQS + TFQS + 24 + 6 + + + TFQM + TFQM + 30 + 1 + + + + + FDCAN_TXFQS + FDCAN_TXFQS + The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). + 0xC4 + 0x20 + read-only + 0x00000000 + + + TFFL + TFFL + 0 + 6 + + + TFGI + TFGI + 8 + 5 + + + TFQPI + TFQPI + 16 + 5 + + + TFQF + TFQF + 21 + 1 + + + + + FDCAN_TXESC + FDCAN_TXESC + Configures the number of data bytes belonging to a Tx buffer element. Data field sizes &gt;8 bytes are intended for CAN FD operation only. + 0xC8 + 0x20 + read-only + 0x00000000 + + + TBDS + TBDS + 0 + 3 + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0xD0 + 0x20 + read-write + 0x00000000 + + + AR + AR + 0 + 32 + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0xD4 + 0x20 + read-write + 0x00000000 + + + CR + CR + 0 + 32 + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0xD8 + 0x20 + read-only + 0x00000000 + + + TO + TO + 0 + 32 + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0xDC + 0x20 + read-only + 0x00000000 + + + CF + CF + 0 + 32 + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0xE0 + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 32 + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0xE4 + 0x20 + read-write + 0x00000000 + + + CFIE + CFIE + 0 + 32 + + + + + FDCAN_TXEFC + FDCAN_TXEFC + FDCAN Tx event FIFO configuration register + 0xF0 + 0x20 + read-write + 0x00000000 + + + EFSA + EFSA + 2 + 14 + + + EFS + EFS + 16 + 6 + + + EFWM + EFWM + 24 + 6 + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0xF4 + 0x20 + read-only + 0x00000000 + + + EFFL + EFFL + 0 + 6 + + + EFGI + EFGI + 8 + 5 + + + EFPI + EFPI + 16 + 5 + + + EFF + EFF + 24 + 1 + + + TEFL + TEFL + 25 + 1 + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0xF8 + 0x20 + read-write + 0x00000000 + + + EFAI + EFAI + 0 + 5 + + + + + FDCAN_TTTMC + FDCAN_TTTMC + FDCAN TT trigger memory configuration register + 0x100 + 0x20 + read-write + 0x00000000 + + + TMSA + TMSA + 2 + 14 + + + TME + TME + 16 + 7 + + + + + FDCAN_TTRMC + FDCAN_TTRMC + FDCAN TT reference message configuration register + 0x104 + 0x20 + read-write + 0x00000000 + + + RID + RID + 0 + 29 + + + XTD + XTD + 30 + 1 + + + RMPS + RMPS + 31 + 1 + + + + + FDCAN_TTOCF + FDCAN_TTOCF + FDCAN TT operation configuration register + 0x108 + 0x20 + read-write + 0x00010000 + + + OM + OM + 0 + 2 + + + GEN + GEN + 3 + 1 + + + TM + TM + 4 + 1 + + + LDSDL + LDSDL + 5 + 3 + + + IRTO + IRTO + 8 + 7 + + + EECS + EECS + 15 + 1 + + + AWL + AWL + 16 + 8 + + + EGTF + EGTF + 24 + 1 + + + ECC + ECC + 25 + 1 + + + EVTP + EVTP + 26 + 1 + + + + + FDCAN_TTMLM + FDCAN_TTMLM + FDCAN TT matrix limits register + 0x10C + 0x20 + read-write + 0x00000000 + + + CCM + CCM + 0 + 6 + + + CSS + CSS + 6 + 2 + + + TXEW + TXEW + 8 + 4 + + + ENTT + ENTT + 16 + 12 + + + + + FDCAN_TURCF + FDCAN_TURCF + The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. + 0x110 + 0x20 + read-write + 0x00000000 + + + NCL + NCL + 0 + 16 + + + DC + DC + 16 + 14 + + + ELT + ELT + 31 + 1 + + + + + FDCAN_TTOCN + FDCAN_TTOCN + FDCAN TT operation control register + 0x114 + 0x20 + 0x00000000 + + + SGT + SGT + 0 + 1 + read-write + + + ECS + ECS + 1 + 1 + read-write + + + SWP + SWP + 2 + 1 + read-write + + + SWS + SWS + 3 + 2 + read-write + + + RTIE + RTIE + 5 + 1 + read-write + + + TMC + TMC + 6 + 2 + read-write + + + TTIE + TTIE + 8 + 1 + read-write + + + GCS + GCS + 9 + 1 + read-write + + + FGP + FGP + 10 + 1 + read-write + + + TMG + TMG + 11 + 1 + read-write + + + NIG + NIG + 12 + 1 + read-write + + + ESCN + ESCN + 13 + 1 + read-write + + + LCKC + LCKC + 15 + 1 + read-only + + + + + FDCAN_TTGTP + FDCAN_TTGTP + If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. + 0x118 + 0x20 + read-write + 0x00000000 + + + TP + TP + 0 + 16 + + + CTP + CTP + 16 + 16 + + + + + FDCAN_TTTMK + FDCAN_TTTMK + A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. + 0x11C + 0x20 + 0x00000000 + + + TM + TM + 0 + 16 + read-write + + + TICC + TICC + 16 + 7 + read-write + + + LCKM + LCKM + 31 + 1 + read-only + + + + + FDCAN_TTIR + FDCAN_TTIR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. + 0x120 + 0x20 + read-write + 0x00000000 + + + SBC + SBC + 0 + 1 + + + SMC + SMC + 1 + 1 + + + CSM + CSM + 2 + 1 + + + SOG + SOG + 3 + 1 + + + RTMI + RTMI + 4 + 1 + + + TTMI + TTMI + 5 + 1 + + + SWE + SWE + 6 + 1 + + + GTW + GTW + 7 + 1 + + + GTD + GTD + 8 + 1 + + + GTE + GTE + 9 + 1 + + + TXU + TXU + 10 + 1 + + + TXO + TXO + 11 + 1 + + + SE1 + SE1 + 12 + 1 + + + SE2 + SE2 + 13 + 1 + + + ELC + ELC + 14 + 1 + + + IWTG + IWTG + 15 + 1 + + + WT + WT + 16 + 1 + + + AW + AW + 17 + 1 + + + CER + CER + 18 + 1 + + + + + FDCAN_TTIE + FDCAN_TTIE + The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. + 0x124 + 0x20 + read-write + 0x00000000 + + + SBCE + SBCE + 0 + 1 + + + SMCE + SMCE + 1 + 1 + + + CSME + CSME + 2 + 1 + + + SOGE + SOGE + 3 + 1 + + + RTMIE + RTMIE + 4 + 1 + + + TTMIE + TTMIE + 5 + 1 + + + SWEE + SWEE + 6 + 1 + + + GTWE + GTWE + 7 + 1 + + + GTDE + GTDE + 8 + 1 + + + GTEE + GTEE + 9 + 1 + + + TXUE + TXUE + 10 + 1 + + + TXOE + TXOE + 11 + 1 + + + SE1E + SE1E + 12 + 1 + + + SE2E + SE2E + 13 + 1 + + + ELCE + ELCE + 14 + 1 + + + IWTE + IWTE + 15 + 1 + + + WTE + WTE + 16 + 1 + + + AWE + AWE + 17 + 1 + + + CERE + CERE + 18 + 1 + + + + + FDCAN_TTILS + FDCAN_TTILS + The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. + 0x128 + 0x20 + read-write + 0x00000000 + + + SBCL + SBCL + 0 + 1 + + + SMCL + SMCL + 1 + 1 + + + CSML + CSML + 2 + 1 + + + SOGL + SOGL + 3 + 1 + + + RTMIL + RTMIL + 4 + 1 + + + TTMIL + TTMIL + 5 + 1 + + + SWEL + SWEL + 6 + 1 + + + GTWL + GTWL + 7 + 1 + + + GTDL + GTDL + 8 + 1 + + + GTEL + GTEL + 9 + 1 + + + TXUL + TXUL + 10 + 1 + + + TXOL + TXOL + 11 + 1 + + + SE1L + SE1L + 12 + 1 + + + SE2L + SE2L + 13 + 1 + + + ELCL + ELCL + 14 + 1 + + + IWTL + IWTL + 15 + 1 + + + WTL + WTL + 16 + 1 + + + AWL + AWL + 17 + 1 + + + CERL + CERL + 18 + 1 + + + + + FDCAN_TTOST + FDCAN_TTOST + FDCAN TT operation status register + 0x12C + 0x20 + read-only + 0x00000080 + + + EL + EL + 0 + 2 + + + MS + MS + 2 + 2 + + + SYS + SYS + 4 + 2 + + + QGTP + QGTP + 6 + 1 + + + QCS + QCS + 7 + 1 + + + RTO + RTO + 8 + 8 + + + WGTD + WGTD + 22 + 1 + + + GFI + GFI + 23 + 1 + + + TMP + TMP + 24 + 3 + + + GSI + GSI + 27 + 1 + + + WFE + WFE + 28 + 1 + + + AWE + AWE + 29 + 1 + + + WECS + WECS + 30 + 1 + + + SPL + SPL + 31 + 1 + + + + + FDCAN_TURNA + FDCAN_TURNA + There is no drift compensation in TTCAN level 1. + 0x130 + 0x20 + read-only + 0x00000000 + + + NAV + NAV + 0 + 18 + + + + + FDCAN_TTLGT + FDCAN_TTLGT + FDCAN TT local and global time register + 0x134 + 0x20 + read-only + 0x00000000 + + + LT + LT + 0 + 16 + + + GT + GT + 16 + 16 + + + + + FDCAN_TTCTC + FDCAN_TTCTC + FDCAN TT cycle time and count register + 0x138 + 0x20 + read-only + 0x003F0000 + + + CT + CT + 0 + 16 + + + CC + CC + 16 + 6 + + + + + FDCAN_TTCPT + FDCAN_TTCPT + FDCAN TT capture time register + 0x13C + 0x20 + read-only + 0x00000000 + + + CCV + CCV + 0 + 6 + + + SWV + SWV + 16 + 16 + + + + + FDCAN_TTCSM + FDCAN_TTCSM + FDCAN TT cycle sync mark register + 0x140 + 0x20 + read-only + 0x00000000 + + + CSM + CSM + 0 + 16 + + + + + FDCAN_TTTS + FDCAN_TTTS + The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. + 0x300 + 0x20 + read-write + 0x00000000 + + + SWTDEL + SWTDEL + 0 + 2 + + + EVTSEL + EVTSEL + 4 + 2 + + + + + + + FDCAN2 + 0x4400F000 + + FDCAN2_IT0 + FDCAN2 interrupt 0 + 21 + + + FDCAN2_IT1 + FDCAN2 interrupt 1 + 23 + + + + FMC + FMC register block + FMC + 0x58002000 + + 0x0 + 0x1000 + registers + + + FMC + FMC global interrupt + 49 + + + + FMC_BCR1 + FMC_BCR1 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR1 + FMC_BTR1 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR2 + FMC_BCR2 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR2 + FMC_BTR2 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR3 + FMC_BCR3 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR3 + FMC_BTR3 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR4 + FMC_BCR4 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR4 + FMC_BTR4 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_PCSCNTR + FMC_PCSCNTR + This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h + 0x20 + 0x20 + read-write + 0x00000000 + + + CSCOUNT + CSCOUNT + 0 + 16 + + + CNTB1EN + CNTB1EN + 16 + 1 + + + CNTB2EN + CNTB2EN + 17 + 1 + + + CNTB3EN + CNTB3EN + 18 + 1 + + + CNTB4EN + CNTB4EN + 19 + 1 + + + + + FMC_PCR + FMC_PCR + NAND Flash Programmable control register + 0x80 + 0x20 + read-write + 0x0007FE08 + + + PWAITEN + PWAITEN + 1 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWID + PWID + 4 + 2 + + + ECCEN + ECCEN + 6 + 1 + + + ECCALG + ECCALG + 8 + 1 + + + TCLR + TCLR + 9 + 4 + + + TAR + TAR + 13 + 4 + + + ECCSS + ECCSS + 17 + 3 + + + TCEH + TCEH + 20 + 4 + + + BCHECC + BCHECC + 24 + 1 + + + WEN + WEN + 25 + 1 + + + + + FMC_SR + FMC_SR + This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits. + 0x84 + 0x20 + read-only + 0x00000040 + + + ISOST + ISOST + 0 + 2 + + + PEF + PEF + 4 + 1 + + + NWRF + NWRF + 6 + 1 + + + + + FMC_PMEM + FMC_PMEM + The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses. + 0x88 + 0x20 + read-write + 0x0A0A0A0A + + + MEMSET + MEMSET + 0 + 8 + + + MEMWAIT + MEMWAIT + 8 + 8 + + + MEMHOLD + MEMHOLD + 16 + 8 + + + MEMHIZ + MEMHIZ + 24 + 8 + + + + + FMC_PATT + FMC_PATT + The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function). + 0x8C + 0x20 + read-write + 0x0A0A0A0A + + + ATTSET + ATTSET + 0 + 8 + + + ATTWAIT + ATTWAIT + 8 + 8 + + + ATTHOLD + ATTHOLD + 16 + 8 + + + ATTHIZ + ATTHIZ + 24 + 8 + + + + + FMC_HPR + FMC_HPR + This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. + 0x90 + 0x20 + read-only + 0x00000000 + + + HPR + HPR + 0 + 32 + + + + + FMC_HECCR + FMC_HECCR + This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + HECC + HECC + 0 + 32 + + + + + FMC_BWTR1 + FMC_BWTR1 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x104 + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR2 + FMC_BWTR2 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x10C + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR3 + FMC_BWTR3 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x114 + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR4 + FMC_BWTR4 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x11C + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_CSQCR + FMC_CSQCR + FMC NAND Command Sequencer Control Register + 0x200 + 0x20 + write-only + 0x00000000 + + + CSQSTART + CSQSTART + 0 + 1 + + + + + FMC_CSQCFGR1 + FMC_CSQCFGR1 + FMC NAND Command Sequencer Configuration Register 1 + 0x204 + 0x20 + read-write + 0x00000000 + + + CMD2EN + CMD2EN + 1 + 1 + + + DMADEN + DMADEN + 2 + 1 + + + ACYNBR + ACYNBR + 4 + 3 + + + CMD1 + CMD1 + 8 + 8 + + + CMD2 + CMD2 + 16 + 8 + + + CMD1T + CMD1T + 24 + 1 + + + CMD2T + CMD2T + 25 + 1 + + + + + FMC_CSQCFGR2 + FMC_CSQCFGR2 + This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. . + 0x208 + 0x20 + read-write + 0x00000000 + + + SQSDTEN + SQSDTEN + 0 + 1 + + + RCMD2EN + RCMD2EN + 1 + 1 + + + DMASEN + DMASEN + 2 + 1 + + + RCMD1 + RCMD1 + 8 + 8 + + + RCMD2 + RCMD2 + 16 + 8 + + + RCMD1T + RCMD1T + 24 + 1 + + + RCMD2T + RCMD2T + 25 + 1 + + + + + FMC_CSQCFGR3 + FMC_CSQCFGR3 + FMC NAND sequencer configuration register 3 + 0x20C + 0x20 + read-write + 0x00000000 + + + SNBR + SNBR + 8 + 6 + + + AC1T + AC1T + 16 + 1 + + + AC2T + AC2T + 17 + 1 + + + AC3T + AC3T + 18 + 1 + + + AC4T + AC4T + 19 + 1 + + + AC5T + AC5T + 20 + 1 + + + SDT + SDT + 21 + 1 + + + RAC1T + RAC1T + 22 + 1 + + + RAC2T + RAC2T + 23 + 1 + + + + + FMC_CSQAR1 + FMC_CSQAR1 + This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer. + 0x210 + 0x20 + read-write + 0x00000000 + + + ADDC1 + ADDC1 + 0 + 8 + + + ADDC2 + ADDC2 + 8 + 8 + + + ADDC3 + ADDC3 + 16 + 8 + + + ADDC4 + ADDC4 + 24 + 8 + + + + + FMC_CSQAR2 + FMC_CSQAR2 + This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable. + 0x214 + 0x20 + read-write + 0x00020000 + + + ADDC5 + ADDC5 + 0 + 8 + + + NANDCEN0 + NANDCEN0 + 10 + 1 + + + NANDCEN1 + NANDCEN1 + 11 + 1 + + + SAO + SAO + 16 + 16 + + + + + FMC_CSQIER + FMC_CSQIER + FMC NAND Command Sequencer Interrupt Enable Register + 0x220 + 0x20 + read-write + 0x00000000 + + + TCIE + TCIE + 0 + 1 + + + SCIE + SCIE + 1 + 1 + + + SEIE + SEIE + 2 + 1 + + + SUEIE + SUEIE + 3 + 1 + + + CMDTCIE + CMDTCIE + 4 + 1 + + + + + FMC_CSQISR + FMC_CSQISR + FMC NAND Command Sequencer Interrupt Status Register + 0x224 + 0x20 + read-write + 0x00000000 + + + TCF + TCF + 0 + 1 + + + SCF + SCF + 1 + 1 + + + SEF + SEF + 2 + 1 + + + SUEF + SUEF + 3 + 1 + + + CMDTCF + CMDTCF + 4 + 1 + + + + + FMC_CSQICR + FMC_CSQICR + FMC NAND Command Sequencer Interrupt Clear Register + 0x228 + 0x20 + write-only + 0x00000000 + + + CTCF + CTCF + 0 + 1 + + + CSCF + CSCF + 1 + 1 + + + CSEF + CSEF + 2 + 1 + + + CSUEF + CSUEF + 3 + 1 + + + CCMDTCF + CCMDTCF + 4 + 1 + + + + + FMC_CSQEMSR + FMC_CSQEMSR + This register holds a sector error mapping status when the whole transfer is complete. + 0x230 + 0x20 + read-only + 0x00000000 + + + SEM + SEM + 0 + 16 + + + + + FMC_BCHIER + FMC_BCHIER + FMC BCH Interrupt enable register + 0x250 + 0x20 + read-write + 0x00000000 + + + DUEIE + DUEIE + 0 + 1 + + + DERIE + DERIE + 1 + 1 + + + DEFIE + DEFIE + 2 + 1 + + + DSRIE + DSRIE + 3 + 1 + + + EPBRIE + EPBRIE + 4 + 1 + + + + + FMC_BCHISR + FMC_BCHISR + This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared. + 0x254 + 0x20 + read-only + 0x00000000 + + + DUEF + DUEF + 0 + 1 + + + DERF + DERF + 1 + 1 + + + DEFF + DEFF + 2 + 1 + + + DSRF + DSRF + 3 + 1 + + + EPBRF + EPBRF + 4 + 1 + + + + + FMC_BCHICR + FMC_BCHICR + FMC BCH Interrupt Clear Register + 0x258 + 0x20 + write-only + 0x00000000 + + + CDUEF + CDUEF + 0 + 1 + + + CDERF + CDERF + 1 + 1 + + + CDEFF + CDEFF + 2 + 1 + + + CDSRF + CDSRF + 3 + 1 + + + CEPBRF + CEPBRF + 4 + 1 + + + + + FMC_BCHPBR1 + FMC_BCHPBR1 + These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant. + 0x260 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR2 + FMC_BCHPBR2 + FMC BCH Parity Bits Register 2 + 0x264 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR3 + FMC_BCHPBR3 + FMC BCH Parity Bits Register 3 + 0x268 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR4 + FMC_BCHPBR4 + FMC BCH Parity Bits Register 4 + 0x26C + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 8 + + + + + FMC_BCHDSR0 + FMC_BCHDSR0 + This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. . + 0x27C + 0x20 + read-only + 0x00000000 + + + DUE + DUE + 0 + 1 + + + DEF + DEF + 1 + 1 + + + DEN + DEN + 4 + 4 + + + + + FMC_BCHDSR1 + FMC_BCHDSR1 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors + 0x280 + 0x20 + read-only + 0x00000000 + + + EBP1 + EBP1 + 0 + 13 + + + EBP2 + EBP2 + 16 + 13 + + + + + FMC_BCHDSR2 + FMC_BCHDSR2 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively. + 0x284 + 0x20 + read-only + 0x00000000 + + + EBP3 + EBP3 + 0 + 13 + + + EBP4 + EBP4 + 16 + 13 + + + + + FMC_BCHDSR3 + FMC_BCHDSR3 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. + 0x288 + 0x20 + read-only + 0x00000000 + + + EBP5 + EBP5 + 0 + 13 + + + EBP6 + EBP6 + 16 + 13 + + + + + FMC_BCHDSR4 + FMC_BCHDSR4 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. . + 0x28C + 0x20 + read-only + 0x00000000 + + + EBP7 + EBP7 + 0 + 13 + + + EBP8 + EBP8 + 16 + 13 + + + + + FMC_HWCFGR2 + FMC_HWCFGR2 + FMC Hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00DC8762 + + + RD_LN2DPTH + RD_LN2DPTH + 0 + 4 + + + NOR_BASE + NOR_BASE + 4 + 4 + + + SDRAM_RBASE + SDRAM_RBASE + 8 + 4 + + + NAND_BASE + NAND_BASE + 12 + 4 + + + SDRAM1_BASE + SDRAM1_BASE + 16 + 4 + + + SDRAM2_BASE + SDRAM2_BASE + 20 + 4 + + + + + FMC_HWCFGR1 + FMC_HWCFGR1 + FMC Hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x2232B011 + + + NAND_SEL + NAND_SEL + 0 + 1 + + + NAND_ECC + NAND_ECC + 4 + 1 + + + SDRAM_SEL + SDRAM_SEL + 8 + 1 + + + ID_SIZE + ID_SIZE + 12 + 4 + + + WA_LN2DPTH + WA_LN2DPTH + 16 + 4 + + + WD_LN2DPTH + WD_LN2DPTH + 20 + 4 + + + WR_LN2DPTH + WR_LN2DPTH + 24 + 4 + + + RA_LN2DPTH + RA_LN2DPTH + 28 + 4 + + + + + FMC_VERR + FMC_VERR + FMC Version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + FMC_IPIDR + FMC_IPIDR + FMC Identification register + 0x3F8 + 0x20 + read-only + 0x00140001 + + + ID + ID + 0 + 32 + + + + + FMC_SIDR + FMC_SIDR + FMC Size Identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + GICD + GICD address block description + GIC + 0xA0021000 + + 0x0 + 0x1000 + registers + + + + GICD_CTLR + GICD_CTLR + GICD_CTLR + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLEGRP0 + enable group 1 interrupts +Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces + 0 + 1 + read-write + + + ENABLEGRP1 + enable group 1 interrupts +Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces + 1 + 1 + read-write + + + + + GICD_CTLRNS + GICD_CTLRNS + GICD_CTLRNS + GICD_CTLR + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces + 0 + 1 + read-write + + + ENABLEGRP1 + enable group 1 interrupts +Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces + 1 + 1 + read-write + + + + + GICD_TYPER + GICD_TYPER + 0x4 + 0x20 + 0x0000FC05 + 0xFFFFFFFF + + + ITLINESNUMBER + number of interrupt lines +Indicates the number of interrupts that the GIC supports (0b00101 = Up to 192 interrupts, 160 external interrupts) + 0 + 5 + read-only + + + CPUNUMBER + number of processors interfaces +Indicates the number of implemented processors interfaces in the GIC (0b000 = 1 processor) + 5 + 3 + read-only + + + SECURITYEXTN + security extension +Indicates whether the GIC implements the security extensions. This bit always returns a value of 1, indicating that the security extensions are implemented. + 10 + 1 + read-only + + + LSPI + lockable shared peripheral interrupt +Returns the number of LSPIs that the interrupt controller contains (0b1111 = 31 LSPIs, these are the interrupts of IDs 32-62). + 11 + 5 + read-only + + + + + GICD_IIDR + GICD_IIDR + 0x8 + 0x20 + 0x0100143B + 0xFFFFFFFF + + + IMPLEMENTER + GIC implementer (0x43B Arm implementation) + 0 + 12 + read-only + + + REVISION + Indicates the minor revision number of the GIC + 12 + 4 + read-only + + + VARIANT + Indicates the major revision number of the GIC + 16 + 4 + read-only + + + PRODUCTID + product ID of the GIC + 24 + 8 + read-only + + + + + GICD_IGROUPR0 + GICD_IGROUPR0 + GICD interrupt group register 0 + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_IGROUPR1 + GICD_IGROUPR1 + GICD interrupt group register 1 + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_IGROUPR2 + GICD_IGROUPR2 + GICD interrupt group register 2 + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_IGROUPR3 + GICD_IGROUPR3 + GICD interrupt group register 3 + 0x8c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_IGROUPR4 + GICD_IGROUPR4 + GICD interrupt group register 4 + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_IGROUPR5 + GICD_IGROUPR5 + GICD interrupt group register 5 + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IGROUPRx + group of interrupts + 0 + 32 + read-write + + + + + GICD_ISENABLER0 + GICD_ISENABLER0 + GICD interrupt set-enable register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLER0 + interrupt set-enable 0 + 0 + 32 + read-write + + + + + GICD_ISENABLER1 + GICD_ISENABLER1 + GICD interrupt set-enable register 1 + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLERx + interrupt set-enable x + 0 + 32 + read-write + + + + + GICD_ISENABLER2 + GICD_ISENABLER2 + GICD interrupt set-enable register 2 + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLERx + interrupt set-enable x + 0 + 32 + read-write + + + + + GICD_ISENABLER3 + GICD_ISENABLER3 + GICD interrupt set-enable register 3 + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLERx + interrupt set-enable x + 0 + 32 + read-write + + + + + GICD_ISENABLER4 + GICD_ISENABLER4 + GICD interrupt set-enable register 4 + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLERx + interrupt set-enable x + 0 + 32 + read-write + + + + + GICD_ISENABLER5 + GICD_ISENABLER5 + GICD interrupt set-enable register 5 + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISENABLERx + interrupt set-enable x + 0 + 32 + read-write + + + + + GICD_ICENABLER0 + GICD_ICENABLER0 + GICD interrupt clear-enable register + 0x180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLER0 + interrupt clear-enable 0 + 0 + 32 + read-write + + + + + GICD_ICENABLER1 + GICD_ICENABLER1 + GICD interrupt clear-enable register 1 + 0x184 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLERx + interrupt clear-enable x + 0 + 32 + read-write + + + + + GICD_ICENABLER2 + GICD_ICENABLER2 + GICD interrupt clear-enable register 2 + 0x188 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLERx + interrupt clear-enable x + 0 + 32 + read-write + + + + + GICD_ICENABLER3 + GICD_ICENABLER3 + GICD interrupt clear-enable register 3 + 0x18c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLERx + interrupt clear-enable x + 0 + 32 + read-write + + + + + GICD_ICENABLER4 + GICD_ICENABLER4 + GICD interrupt clear-enable register 4 + 0x190 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLERx + interrupt clear-enable x + 0 + 32 + read-write + + + + + GICD_ICENABLER5 + GICD_ICENABLER5 + GICD interrupt clear-enable register 5 + 0x194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICENABLERx + interrupt clear-enable x + 0 + 32 + read-write + + + + + GICD_ISPENDR0 + GICD_ISPENDR0 + GICD interrupt set-pending register 0 + 0x200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ISPENDR1 + GICD_ISPENDR1 + GICD interrupt set-pending register 1 + 0x204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ISPENDR2 + GICD_ISPENDR2 + GICD interrupt set-pending register 2 + 0x208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ISPENDR3 + GICD_ISPENDR3 + GICD interrupt set-pending register 3 + 0x20c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ISPENDR4 + GICD_ISPENDR4 + GICD interrupt set-pending register 4 + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ISPENDR5 + GICD_ISPENDR5 + GICD interrupt set-pending register 5 + 0x214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISPENDRx + interrupt set-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR0 + GICD_ICPENDR0 + GICD interrupt clear-pending register 0 + 0x280 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR1 + GICD_ICPENDR1 + GICD interrupt clear-pending register 1 + 0x284 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR2 + GICD_ICPENDR2 + GICD interrupt clear-pending register 2 + 0x288 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR3 + GICD_ICPENDR3 + GICD interrupt clear-pending register 3 + 0x28c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR4 + GICD_ICPENDR4 + GICD interrupt clear-pending register 4 + 0x290 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ICPENDR5 + GICD_ICPENDR5 + GICD interrupt clear-pending register 5 + 0x294 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICPENDRx + interrupt clear-pending x + 0 + 32 + read-write + + + + + GICD_ISACTIVER0 + GICD_ISACTIVER0 + GICD interrupt set-active register 0 + 0x300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ISACTIVER1 + GICD_ISACTIVER1 + GICD interrupt set-active register 1 + 0x304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ISACTIVER2 + GICD_ISACTIVER2 + GICD interrupt set-active register 2 + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ISACTIVER3 + GICD_ISACTIVER3 + GICD interrupt set-active register 3 + 0x30c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ISACTIVER4 + GICD_ISACTIVER4 + GICD interrupt set-active register 4 + 0x310 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ISACTIVER5 + GICD_ISACTIVER5 + GICD interrupt set-active register 5 + 0x314 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ISACTIVERx + interrupt set-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER0 + GICD_ICACTIVER0 + GICD interrupt clear-active register 0 + 0x380 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER1 + GICD_ICACTIVER1 + GICD interrupt clear-active register 1 + 0x384 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER2 + GICD_ICACTIVER2 + GICD interrupt clear-active register 2 + 0x388 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER3 + GICD_ICACTIVER3 + GICD interrupt clear-active register 3 + 0x38c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER4 + GICD_ICACTIVER4 + GICD interrupt clear-active register 4 + 0x390 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_ICACTIVER5 + GICD_ICACTIVER5 + GICD interrupt clear-active register 5 + 0x394 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ICACTIVERx + interrupt clear-active x + 0 + 32 + read-write + + + + + GICD_IPRIORITYR0 + GICD_IPRIORITYR0 + 0x400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR1 + GICD_IPRIORITYR1 + 0x404 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR2 + GICD_IPRIORITYR2 + 0x408 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR3 + GICD_IPRIORITYR3 + 0x40c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR4 + GICD_IPRIORITYR4 + 0x410 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR5 + GICD_IPRIORITYR5 + 0x414 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR6 + GICD_IPRIORITYR6 + 0x418 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR7 + GICD_IPRIORITYR7 + 0x41c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR8 + GICD_IPRIORITYR8 + 0x420 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR9 + GICD_IPRIORITYR9 + 0x424 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR10 + GICD_IPRIORITYR10 + 0x428 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR11 + GICD_IPRIORITYR11 + 0x42c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR12 + GICD_IPRIORITYR12 + 0x430 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR13 + GICD_IPRIORITYR13 + 0x434 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR14 + GICD_IPRIORITYR14 + 0x438 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR15 + GICD_IPRIORITYR15 + 0x43c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR16 + GICD_IPRIORITYR16 + 0x440 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR17 + GICD_IPRIORITYR17 + 0x444 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR18 + GICD_IPRIORITYR18 + 0x448 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR19 + GICD_IPRIORITYR19 + 0x44c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR20 + GICD_IPRIORITYR20 + 0x450 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR21 + GICD_IPRIORITYR21 + 0x454 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR22 + GICD_IPRIORITYR22 + 0x458 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR23 + GICD_IPRIORITYR23 + 0x45c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR24 + GICD_IPRIORITYR24 + 0x460 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR25 + GICD_IPRIORITYR25 + 0x464 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR26 + GICD_IPRIORITYR26 + 0x468 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR27 + GICD_IPRIORITYR27 + 0x46c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR28 + GICD_IPRIORITYR28 + 0x470 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR29 + GICD_IPRIORITYR29 + 0x474 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR30 + GICD_IPRIORITYR30 + 0x478 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR31 + GICD_IPRIORITYR31 + 0x47c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR32 + GICD_IPRIORITYR32 + 0x480 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR33 + GICD_IPRIORITYR33 + 0x484 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR34 + GICD_IPRIORITYR34 + 0x488 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR35 + GICD_IPRIORITYR35 + 0x48c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR36 + GICD_IPRIORITYR36 + 0x490 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR37 + GICD_IPRIORITYR37 + 0x494 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR38 + GICD_IPRIORITYR38 + 0x498 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR39 + GICD_IPRIORITYR39 + 0x49c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR40 + GICD_IPRIORITYR40 + 0x4a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR41 + GICD_IPRIORITYR41 + 0x4a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR42 + GICD_IPRIORITYR42 + 0x4a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR43 + GICD_IPRIORITYR43 + 0x4ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR44 + GICD_IPRIORITYR44 + 0x4b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR45 + GICD_IPRIORITYR45 + 0x4b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR46 + GICD_IPRIORITYR46 + 0x4b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_IPRIORITYR47 + GICD_IPRIORITYR47 + 0x4bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY0 + priority for interrupt ID = x * 4 + 3 + 5 + read-write + + + PRIORITY1 + priority for interrupt ID = x * 4 + 1 + 11 + 5 + read-write + + + PRIORITY2 + priority for interrupt ID = x * 4 + 2 + 19 + 5 + read-write + + + PRIORITY3 + priority for interrupt ID = x * 4 + 3 + 27 + 5 + read-write + + + + + GICD_ITARGETSR0 + GICD_ITARGETSR0 + GICD interrupt processor target register 0 + 0x800 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR1 + GICD_ITARGETSR1 + GICD interrupt processor target register 1 + 0x804 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR2 + GICD_ITARGETSR2 + GICD interrupt processor target register 2 + 0x808 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR3 + GICD_ITARGETSR3 + GICD interrupt processor target register 3 + 0x80c + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR4 + GICD_ITARGETSR4 + GICD interrupt processor target register 4 + 0x810 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR5 + GICD_ITARGETSR5 + GICD interrupt processor target register 5 + 0x814 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR6 + GICD_ITARGETSR6 + GICD interrupt processor target register 6 + 0x818 + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR7 + GICD_ITARGETSR7 + GICD interrupt processor target register 7 + 0x81c + 0x20 + 0x00000000 + 0x00000000 + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-only + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-only + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-only + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-only + + + + + GICD_ITARGETSR8 + GICD_ITARGETSR8 + 0x820 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR9 + GICD_ITARGETSR9 + 0x824 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR10 + GICD_ITARGETSR10 + 0x828 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR11 + GICD_ITARGETSR11 + 0x82c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR12 + GICD_ITARGETSR12 + 0x830 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR13 + GICD_ITARGETSR13 + 0x834 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR14 + GICD_ITARGETSR14 + 0x838 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR15 + GICD_ITARGETSR15 + 0x83c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR16 + GICD_ITARGETSR16 + 0x840 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR17 + GICD_ITARGETSR17 + 0x844 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR18 + GICD_ITARGETSR18 + 0x848 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR19 + GICD_ITARGETSR19 + 0x84c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR20 + GICD_ITARGETSR20 + 0x850 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR21 + GICD_ITARGETSR21 + 0x854 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR22 + GICD_ITARGETSR22 + 0x858 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR23 + GICD_ITARGETSR23 + 0x85c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR24 + GICD_ITARGETSR24 + 0x860 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR25 + GICD_ITARGETSR25 + 0x864 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR26 + GICD_ITARGETSR26 + 0x868 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR27 + GICD_ITARGETSR27 + 0x86c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR28 + GICD_ITARGETSR28 + 0x870 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR29 + GICD_ITARGETSR29 + 0x874 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR30 + GICD_ITARGETSR30 + 0x878 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR31 + GICD_ITARGETSR31 + 0x87c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR32 + GICD_ITARGETSR32 + 0x880 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR33 + GICD_ITARGETSR33 + 0x884 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR34 + GICD_ITARGETSR34 + 0x888 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR35 + GICD_ITARGETSR35 + 0x88c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR36 + GICD_ITARGETSR36 + 0x890 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR37 + GICD_ITARGETSR37 + 0x894 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR38 + GICD_ITARGETSR38 + 0x898 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR39 + GICD_ITARGETSR39 + 0x89c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR40 + GICD_ITARGETSR40 + 0x8a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR41 + GICD_ITARGETSR41 + 0x8a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR42 + GICD_ITARGETSR42 + 0x8a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR43 + GICD_ITARGETSR43 + 0x8ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR44 + GICD_ITARGETSR44 + 0x8b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR45 + GICD_ITARGETSR45 + 0x8b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR46 + GICD_ITARGETSR46 + 0x8b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ITARGETSR47 + GICD_ITARGETSR47 + 0x8bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CPU_TARGETS0 + CPU(s) target for interrupt ID = x * 4 + 0 + 2 + read-write + + + CPU_TARGETS1 + CPU(s) target for interrupt ID = x * 4 + 1 + 8 + 2 + read-write + + + CPU_TARGETS2 + CPU(s) target for interrupt ID = x * 4 + 2 + 16 + 2 + read-write + + + CPU_TARGETS3 + CPU(s) target for interrupt ID = x * 4 + 3 + 24 + 2 + read-write + + + + + GICD_ICFGR0 + GICD_ICFGR0 + 0xc00 + 0x20 + 0xAAAAAAAA + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = 0 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = 15 + 30 + 2 + read-write + + + + + GICD_ICFGR1 + GICD_ICFGR1 + GICD interrupt configuration register + 0xc04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = 17 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = 18 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = 19 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = 20 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = 21 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = 22 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = 23 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = 24 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = 25 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = 26 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = 27 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = 28 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = 29 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = 30 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = 31 + 30 + 2 + read-write + + + + + GICD_ICFGR2 + GICD_ICFGR2 + 0xc08 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR3 + GICD_ICFGR3 + 0xc0c + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR4 + GICD_ICFGR4 + 0xc10 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR5 + GICD_ICFGR5 + 0xc14 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR6 + GICD_ICFGR6 + 0xc18 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR7 + GICD_ICFGR7 + 0xc1c + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR8 + GICD_ICFGR8 + 0xc20 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR9 + GICD_ICFGR9 + 0xc24 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR10 + GICD_ICFGR10 + 0xc28 + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_ICFGR11 + GICD_ICFGR11 + 0xc2c + 0x20 + 0x55555555 + 0xFFFFFFFF + + + INT_CONFIG0 + interrupt config for interrupt ID = x * 16 + 0 + 2 + read-write + + + INT_CONFIG1 + interrupt config for interrupt ID = x * 16 + 1 + 2 + 2 + read-write + + + INT_CONFIG2 + interrupt config for interrupt ID = x * 16 + 2 + 4 + 2 + read-write + + + INT_CONFIG3 + interrupt config for interrupt ID = x * 16 + 3 + 6 + 2 + read-write + + + INT_CONFIG4 + interrupt config for interrupt ID = x * 16 + 4 + 8 + 2 + read-write + + + INT_CONFIG5 + interrupt config for interrupt ID = x * 16 + 5 + 10 + 2 + read-write + + + INT_CONFIG6 + interrupt config for interrupt ID = x * 16 + 6 + 12 + 2 + read-write + + + INT_CONFIG7 + interrupt config for interrupt ID = x * 16 + 7 + 14 + 2 + read-write + + + INT_CONFIG8 + interrupt config for interrupt ID = x * 16 + 8 + 16 + 2 + read-write + + + INT_CONFIG9 + interrupt config for interrupt ID = x * 16 + 9 + 18 + 2 + read-write + + + INT_CONFIG10 + interrupt config for interrupt ID = x * 16 + 10 + 20 + 2 + read-write + + + INT_CONFIG11 + interrupt config for interrupt ID = x * 16 + 11 + 22 + 2 + read-write + + + INT_CONFIG12 + interrupt config for interrupt ID = x * 16 + 12 + 24 + 2 + read-write + + + INT_CONFIG13 + interrupt config for interrupt ID = x * 16 + 13 + 26 + 2 + read-write + + + INT_CONFIG14 + interrupt config for interrupt ID = x * 16 + 14 + 28 + 2 + read-write + + + INT_CONFIG15 + interrupt config for interrupt ID = x * 16 + 15 + 30 + 2 + read-write + + + + + GICD_PPISR + GICD_PPISR + 0xd00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PPI6 + virtual maintenance interrupt + 9 + 1 + read-only + + + PPI5 + hypervisor timer event + 10 + 1 + read-only + + + PPI4 + virtual timer event + 11 + 1 + read-only + + + PPI0 + nFIQ (not used) + 12 + 1 + read-only + + + PPI1 + secure physical timer event + 13 + 1 + read-only + + + PPI2 + secure physical timer event + 14 + 1 + read-only + + + PPI3 + nIRQ (not used) + 15 + 1 + read-only + + + + + GICD_SPISR0 + GICD_SPISR0 + GICD shared peripheral interrupt register 0 + 0xd04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPISRx + shared peripheral interrupt + 0 + 32 + read-only + + + + + GICD_SPISR1 + GICD_SPISR1 + GICD shared peripheral interrupt register 1 + 0xd08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPISRx + shared peripheral interrupt + 0 + 32 + read-only + + + + + GICD_SPISR2 + GICD_SPISR2 + GICD shared peripheral interrupt register 2 + 0xd0c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPISRx + shared peripheral interrupt + 0 + 32 + read-only + + + + + GICD_SPISR3 + GICD_SPISR3 + GICD shared peripheral interrupt register 3 + 0xd10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPISRx + shared peripheral interrupt + 0 + 32 + read-only + + + + + GICD_SPISR4 + GICD_SPISR4 + GICD shared peripheral interrupt register 4 + 0xd14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPISRx + shared peripheral interrupt + 0 + 32 + read-only + + + + + GICD_SGIR + GICD_SGIR + 0xf00 + 0x20 + 0x00000000 + 0x00000000 + + + SGIINTID + SGI interrupt ID +The value of this field is the interrupt ID of the SGI to forward to the specified CPU interfaces, in the range 0-15 (for example: a value of 0b0011 specifies interrupt ID 3). + 0 + 4 + write-only + + + NSATT + non-secure attribute +It specifies the required security value of the SGI: +0 - Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the SGI is configured as group 0 on that interface. +1 - Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if the SGI is configured as group 1 on that interface. +This field is writable only by a secure access. Any non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as group 1. + 15 + 1 + write-only + + + CPUTARGETLIST + CPU target list +When TARGETLISTFILTER = 0b00, defines the CPU interfaces to which the GICD must forward the interrupt. Each bit of CPUTARGETLIST[1:0] refers to the corresponding CPU interface. If this field is 0 when TARGETLISTFILTER is 0b00, the GICD does not forward the interrupt to any CPU interface. + 16 + 2 + write-only + + + TARGETLISTFILTER + target list filter +Determines how the distributor must process the requested SGI +2: Forward the interrupt only to the CPU interface of the processor which requested the interrupt +3: Reserved, must be kept at reset value. + 24 + 2 + write-only + + + B_0x0 + Forward the interrupt to the CPU interfaces specified in the CPUTARGETLIST field + 0x0 + + + B_0x1 + Forward the interrupt to all CPU interfaces except the processor which requested the interrupt + 0x1 + + + + + + + GICD_CPENDSGIR0 + GICD_CPENDSGIR0 + GICD SGI clear-pending register 0 + 0xf10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_CLEAR_PENDING0 + clear-pending state for SGI [x * 4] +Writing a 1 clears the pending state of the SGI [x * 4] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_CLEAR_PENDING1 + clear-pending state for SGI [x * 4 + 1] +Writing a 1 clears the pending state of the SGI [x * 4 + 1] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_CLEAR_PENDING2 + clear-pending state for SGI [x * 4 + 2] +Writing a 1 clears the pending state of the SGI [x * 4 + 2] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_CLEAR_PENDING3 + clear-pending state for SGI [x * 4 + 3] +Writing a 1 clears the pending state of the SGI [x * 4 + 3] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_CPENDSGIR1 + GICD_CPENDSGIR1 + GICD SGI clear-pending register 1 + 0xf14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_CLEAR_PENDING0 + clear-pending state for SGI [x * 4] +Writing a 1 clears the pending state of the SGI [x * 4] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_CLEAR_PENDING1 + clear-pending state for SGI [x * 4 + 1] +Writing a 1 clears the pending state of the SGI [x * 4 + 1] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_CLEAR_PENDING2 + clear-pending state for SGI [x * 4 + 2] +Writing a 1 clears the pending state of the SGI [x * 4 + 2] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_CLEAR_PENDING3 + clear-pending state for SGI [x * 4 + 3] +Writing a 1 clears the pending state of the SGI [x * 4 + 3] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_CPENDSGIR2 + GICD_CPENDSGIR2 + GICD SGI clear-pending register 2 + 0xf18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_CLEAR_PENDING0 + clear-pending state for SGI [x * 4] +Writing a 1 clears the pending state of the SGI [x * 4] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_CLEAR_PENDING1 + clear-pending state for SGI [x * 4 + 1] +Writing a 1 clears the pending state of the SGI [x * 4 + 1] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_CLEAR_PENDING2 + clear-pending state for SGI [x * 4 + 2] +Writing a 1 clears the pending state of the SGI [x * 4 + 2] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_CLEAR_PENDING3 + clear-pending state for SGI [x * 4 + 3] +Writing a 1 clears the pending state of the SGI [x * 4 + 3] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_CPENDSGIR3 + GICD_CPENDSGIR3 + GICD SGI clear-pending register 3 + 0xf1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_CLEAR_PENDING0 + clear-pending state for SGI [x * 4] +Writing a 1 clears the pending state of the SGI [x * 4] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_CLEAR_PENDING1 + clear-pending state for SGI [x * 4 + 1] +Writing a 1 clears the pending state of the SGI [x * 4 + 1] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_CLEAR_PENDING2 + clear-pending state for SGI [x * 4 + 2] +Writing a 1 clears the pending state of the SGI [x * 4 + 2] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_CLEAR_PENDING3 + clear-pending state for SGI [x * 4 + 3] +Writing a 1 clears the pending state of the SGI [x * 4 + 3] for the corresponding source processor, and no longer targets the processor performing the write. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_SPENDSGIR0 + GICD_SPENDSGIR0 + GICD SGI set-pending register 0 + 0xf20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_SET_PENDING0 + set-pending state for SGI [x * 4] +Writing a 1 sets the pending state of the SGI [x * 4] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_SET_PENDING1 + set-pending state for SGI [x * 4 + 1] +Writing a 1 sets the pending state of the SGI [x * 4 + 1] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_SET_PENDING2 + set-pending state for SGI [x * 4 + 2] +Writing a 1 sets the pending state of the SGI [x * 4 + 2] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_SET_PENDING3 + set-pending state for SGI [x * 4 + 3] +Writing a 1 sets the pending state of the SGI [x * 4 + 3] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_SPENDSGIR1 + GICD_SPENDSGIR1 + GICD SGI set-pending register 1 + 0xf24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_SET_PENDING0 + set-pending state for SGI [x * 4] +Writing a 1 sets the pending state of the SGI [x * 4] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_SET_PENDING1 + set-pending state for SGI [x * 4 + 1] +Writing a 1 sets the pending state of the SGI [x * 4 + 1] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_SET_PENDING2 + set-pending state for SGI [x * 4 + 2] +Writing a 1 sets the pending state of the SGI [x * 4 + 2] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_SET_PENDING3 + set-pending state for SGI [x * 4 + 3] +Writing a 1 sets the pending state of the SGI [x * 4 + 3] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_SPENDSGIR2 + GICD_SPENDSGIR2 + GICD SGI set-pending register 2 + 0xf28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_SET_PENDING0 + set-pending state for SGI [x * 4] +Writing a 1 sets the pending state of the SGI [x * 4] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_SET_PENDING1 + set-pending state for SGI [x * 4 + 1] +Writing a 1 sets the pending state of the SGI [x * 4 + 1] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_SET_PENDING2 + set-pending state for SGI [x * 4 + 2] +Writing a 1 sets the pending state of the SGI [x * 4 + 2] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_SET_PENDING3 + set-pending state for SGI [x * 4 + 3] +Writing a 1 sets the pending state of the SGI [x * 4 + 3] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_SPENDSGIR3 + GICD_SPENDSGIR3 + GICD SGI set-pending register 3 + 0xf2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SGI_SET_PENDING0 + set-pending state for SGI [x * 4] +Writing a 1 sets the pending state of the SGI [x * 4] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4] is pending, from the corresponding source processor, on the reading processor. + 0 + 2 + read-write + + + SGI_SET_PENDING1 + set-pending state for SGI [x * 4 + 1] +Writing a 1 sets the pending state of the SGI [x * 4 + 1] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 1] is pending, from the corresponding source processor, on the reading processor. + 8 + 2 + read-write + + + SGI_SET_PENDING2 + set-pending state for SGI [x * 4 + 2] +Writing a 1 sets the pending state of the SGI [x * 4 + 2] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 2] is pending, from the corresponding source processor, on the reading processor. + 16 + 2 + read-write + + + SGI_SET_PENDING3 + set-pending state for SGI [x * 4 + 3] +Writing a 1 sets the pending state of the SGI [x * 4 + 3] for the corresponding source processor. +Writing a 0 has no effect. +Reading a bit identifies whether the SGI [x * 4 + 3] is pending, from the corresponding source processor, on the reading processor. + 24 + 2 + read-write + + + + + GICD_PIDR4 + GICD_PIDR4 + 0xfd0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + PIDR4 + peripheral ID4 + 0 + 32 + read-only + + + + + GICD_PIDR5 + GICD_PIDR5 + 0xfd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDRx + peripheral ID5 to ID7 + 0 + 32 + read-only + + + + + GICD_PIDR6 + GICD_PIDR6 + 0xfd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDRx + peripheral ID5 to ID7 + 0 + 32 + read-only + + + + + GICD_PIDR7 + GICD_PIDR7 + 0xfdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDRx + peripheral ID5 to ID7 + 0 + 32 + read-only + + + + + GICD_PIDR0 + GICD_PIDR0 + 0xfe0 + 0x20 + 0x00000090 + 0xFFFFFFFF + + + PIDR0 + peripheral ID0 + 0 + 32 + read-only + + + + + GICD_PIDR1 + GICD_PIDR1 + 0xfe4 + 0x20 + 0x000000B4 + 0xFFFFFFFF + + + PIDR1 + peripheral ID1 + 0 + 32 + read-only + + + + + GICD_PIDR2 + GICD_PIDR2 + 0xfe8 + 0x20 + 0x0000002B + 0xFFFFFFFF + + + PIDR2 + peripheral ID2 + 0 + 32 + read-only + + + + + GICD_PIDR3 + GICD_PIDR3 + 0xfec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR3 + peripheral ID3 + 0 + 32 + read-only + + + + + GICD_CIDR0 + GICD_CIDR0 + 0xff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + CIDR0 + component ID0 + 0 + 32 + read-only + + + + + GICD_CIDR1 + GICD_CIDR1 + 0xff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + CIDR1 + component ID1 + 0 + 32 + read-only + + + + + GICD_CIDR2 + GICD_CIDR2 + 0xff8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + CIDR2 + component ID2 + 0 + 32 + read-only + + + + + GICD_CIDR3 + GICD_CIDR3 + 0xffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + CIDR3 + component ID3 + 0 + 32 + read-only + + + + + + + GICC + GICC address block description + GIC + 0xA0022000 + + 0x0 + 0x2000 + registers + + + + GICC_CTLR + GICC_CTLR + GICC control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLEGRP0 + Enable group 0 interrupts +It enables for the signaling of group 0interrupts by the CPU interface to the connected processor. + 0 + 1 + read-write + + + ENABLEGRP1 + Enable group 1 interrupts +It enables for the signaling of group 1 interrupts by the CPU interface to the connected processor. + 1 + 1 + read-write + + + ACKCTL + Acknowledge control +When the highest priority pending interrupt is a group 1 interrupt, this bit determines both: +- whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID +- whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or returns a spurious interrupt ID. +Arm deprecates use of this bit and strongly recommends using a software model where this bit is set to 0. + 2 + 1 + read-write + + + FIQEN + FIQ enable for group 0 interrupts +Controls whether the CPU interface signals group 0 interrupts to a target processor using the FIQ or the IRQ signal. +The GIC always signals group 1 interrupts using the IRQ signal. + 3 + 1 + read-write + + + CBPR + BPR control +Controls whether the GICC_BPR provides common control to group 0 and group 1 interrupts. + 4 + 1 + read-write + + + FIQBYPDISGRP0 + FIQ bypass disable for group 0 interrupts +When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass FIQ signal is signaled to the processor. + 5 + 1 + read-write + + + IRQBYPDISGRP0 + IRQ bypass disable for group 0 interrupts +When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass IRQ signal is signaled to the processor. + 6 + 1 + read-write + + + FIQBYPDISGRP1 + Alias of FIQBYPDISGRP1 from the non-secure copy of this register. + 7 + 1 + read-write + + + IRQBYPDISGRP1 + Alias of IRQBYPDISGRP1 from the non-secure copy of this register. + 8 + 1 + read-write + + + EOIMODES + EOI mode for secure accesses +Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. This control applies only to secure accesses. + 9 + 1 + read-write + + + EOIMODENS + Alias of EOIMODENS from the non-secure copy of this register. + 10 + 1 + read-write + + + + + GICC_CTLRNS + GICC_CTLRNS + GICC control register + GICC_CTLR + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLEGRP1 + ENABLEGRP1 + 0 + 1 + read-write + + + FIQBYPDISGRP1 + FIQBYPDISGRP1 + 5 + 1 + read-write + + + IRQBYPDISGRP1 + IRQBYPDISGRP1 + 6 + 1 + read-write + + + EOIMODENS + EOI mode for non- secure accesses + 9 + 1 + read-write + + + + + GICC_PMR + GICC_PMR + GICC input priority mask register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY + priority mask level for the CPU interface +If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor. + 3 + 5 + read-write + + + + + GICC_BPR + GICC_BPR + GICC binary point register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BINARY_POINT + The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption and a sub-priority field. Minimum value is 2. + 0 + 3 + read-write + + + + + GICC_BPRNS + GICC_BPRNS + GICC_BPRNS + GICC_BPR + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BINARY_POINT + The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption and a sub-priority field. Minimum value is 2. + 0 + 3 + read-write + + + + + GICC_IAR + GICC_IAR + GICC interrupt acknowledge register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT_ID + The interrupt ID + 0 + 10 + read-only + + + CPUID + For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request. +For example, a value of 1 means the request was generated by a write to the GICD_SGIR on CPU interface 1. + 10 + 1 + read-only + + + + + GICC_EOIR + GICC_EOIR + 0x10 + 0x20 + 0x00000000 + 0x00000000 + + + EOIINTID + It contains the interrupt ID value from the corresponding GICC_IAR access. + 0 + 10 + write-only + + + CPUID + On a multiprocessor implementation, if the write refers to an SGI, this field contains the CPUID value from the corresponding GICC_IAR access. + 10 + 1 + write-only + + + + + GICC_RPR + GICC_RPR + GICC running priority register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY + current running priority on the CPU interface + 3 + 5 + read-only + + + + + GICC_HPPIR + GICC_HPPIR + GICC highest priority pending interrupt register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PENDINTID + interrupt ID of the highest-priority pending interrupt + 0 + 10 + read-only + + + CPUID + On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. + 10 + 1 + read-only + + + + + GICC_ABPR + GICC_ABPR + GICC aliased binary point register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BINARY_POINT + The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption, and a subpriority field. Minimun value is 3. + 0 + 3 + read-write + + + + + GICC_AIAR + GICC_AIAR + GICC aliased interrupt acknowledge register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT_ID + interrupt ID + 0 + 10 + read-only + + + CPUID + For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request. +For example, a value of 1 means the request was generated by a write to the GICD_SGIR on CPU interface 1. + 10 + 1 + read-only + + + + + GICC_AEOIR + GICC_AEOIR + GICC aliased end of interrupt register + 0x24 + 0x20 + 0x00000000 + 0x00000000 + + + EOIINTID + It contains the interrupt ID value from the corresponding GICC_AIAR, or non-secure GICC_IAR, access. + 0 + 10 + write-only + + + CPUID + On a multiprocessor implementation, when processing an SGI, this field must contain the CPUID value from the corresponding GICC_AIAR, or non-secure GICC_IAR, access. + 10 + 1 + write-only + + + + + GICC_AHPPIR + GICC_AHPPIR + GICC aliased highest priority pending interrupt register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PENDINTID + interrupt ID of the highest-priority pending interrupt +It contains the interrupt ID of the highest-priority pending interrupt If that interrupt is a group 1 interrupt. Otherwise, its value is the spurious interrupt ID, 1023. + 0 + 10 + read-only + + + CPUID + On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. + 10 + 1 + read-only + + + + + GICC_APR0 + GICC_APR0 + 0xd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + APR0 + active priority + 0 + 32 + read-write + + + + + GICC_NSAPR0 + GICC_NSAPR0 + 0xe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAPR0 + non-secure active priority + 0 + 32 + read-write + + + + + GICC_IIDR + GICC_IIDR + 0xfc + 0x20 + 0x0102143B + 0xFFFFFFFF + + + IMPLEMENTER + GIC implementer (0x43B Arm implementation) + 0 + 12 + read-only + + + REVISION + revision number for the CPU interface + 12 + 4 + read-only + + + ARCH + architecture version of the GIC + 16 + 4 + read-only + + + PRODUCTID + product ID + 20 + 12 + read-only + + + + + GICC_DIR + GICC_DIR + 0x1000 + 0x20 + 0x00000000 + 0x00000000 + + + INTERRUPT_ID + interrupt ID + 0 + 10 + write-only + + + CPUID + CPU ID +For an SGI in a multiprocessor implementation, this field identifies the processor that requested the interrupt + 10 + 1 + write-only + + + + + + + GICH + GICH address block description + GIC + 0xA0024000 + + 0x0 + 0x2000 + registers + + + + GICH_HCR + GICH_HCR + GICH hypervisor control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + global enable bit for the virtual CPU interface + 0 + 1 + read-write + + + UIE + underflow interrupt enable. +Enables the signaling of a maintenance interrupt when the list registers are empty, or hold only one valid entry. + 1 + 1 + read-write + + + LRENPIE + list register entry not present interrupt enable +Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid list register entry for an EOI request. + 2 + 1 + read-write + + + NPIE + no pending interrupt enable +Enables the signaling of a maintenance interrupt while no pending interrupts are present in the list registers. + 3 + 1 + read-write + + + VGRP0EIE + virtual machine enable group 0interrupt enable +Enables the signaling of a maintenance interrupt while signaling of group 0interrupts from the virtual CPU interface to the connected virtual machine, is enabled. + 4 + 1 + read-write + + + VGRP0DIE + virtual machine disable group 0interrupt enable +Enables the signaling of a maintenance interrupt while signaling of group 0interrupts from the virtual CPU interface to the connected virtual machine, is disabled. + 5 + 1 + read-write + + + VGRP1EIE + virtual machine enable group 1 interrupt enable +Enables the signaling of a maintenance interrupt while signaling of group 1 interrupts from the virtual CPU interface to the connected virtual machine, is enabled. + 6 + 1 + read-write + + + VGRP1DIE + virtual machine disable group 1 interrupt enable +Enables the signaling of a maintenance interrupt while signaling of group 1 interrupts from the virtual CPU interface to the connected virtual machine, is disabled. + 7 + 1 + read-write + + + EOICOUNT + end-of-interrupt counter +Counts the number of EOIs received that do not have a corresponding entry in the list registers. The virtual CPU interface increments this field automatically when a matching EOI is received. When EOIs that do not clear a bit in the active priorities register, GICH_APR does not cause an increment. +Although not possible under correct operation, if an EOI occurs when the value of this field is 31, this field wraps to 0. +The maintenance interrupt is asserted whenever this field is non-zero and the LRENPIE bit is set to 1. + 27 + 5 + read-write + + + + + GICH_VTR + GICH_VTR + 0x4 + 0x20 + 0x90000003 + 0xFFFFFFFF + + + LISTREGS + list registers +Indicates the number of implemented list registers, minus one. +For example, 0x3 means 4 list registers. + 0 + 5 + read-only + + + PREBITS + preemption bits +Indicates the number of preemption bits implemented, minus one. +For example, 0x4 means 5 bits of preemption and 32 preemption levels + 26 + 3 + read-only + + + PRIBITS + priority bits +Indicates the number of priority bits implemented, minus one. +For example, 0x4 means 5 bits of priority and 32 priority levels. + 29 + 3 + read-only + + + + + GICH_VMCR + GICH_VMCR + GICH virtual machine control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VMGRP0EN + alias of GICV_CTLR.ENABLEGRP0 + 0 + 1 + read-write + + + VMGRP1EN + alias of GICV_CTLR.ENABLEGRP1 + 1 + 1 + read-write + + + VMACKCTL + alias of GICV_CTLR.ACKCTL + 2 + 1 + read-write + + + VMFIQEN + alias of GICV_CTLR.FIQEN + 3 + 1 + read-write + + + VMCBPR + alias of GICV_CTLR.CBPR + 4 + 1 + read-write + + + VEM + alias of GICV_CTLR.EOIMODE + 9 + 1 + read-write + + + VMABP + alias of GICV_ABPR.BINARY_POINT. + 18 + 3 + read-write + + + VMBP + alias of GICV_BPR.BINARY_POINT + 21 + 3 + read-write + + + VMPRIMASK + alias of GICV_PMR.PRIORITY + 27 + 5 + read-write + + + + + GICH_MISR + GICH_MISR + GICH maintenance interrupt status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOI + End of interrupt maintenance interrupt +Asserted whenever at least one list register is asserting an EOI Interrupt., which means at least one bit in GICH_EISRx=1. + 0 + 1 + read-only + + + U + underflow maintenance interrupt +Asserted whenever GICH_HCR.UIE is set and if none, or only one, of the list register entries are marked as a valid interrupt, that is, if the corresponding GICH_LRx.STATE bits do not equal 0x0. + 1 + 1 + read-only + + + LRENP + list register entry not present maintenance interrupt +Asserted whenever GICH_HCR.LRENPIE=1 and GICH_HCR.EOICOUNT is non-zero. + 2 + 1 + read-only + + + NP + no pending maintenance interrupt +Asserted whenever GICH_HCR.NPIE=1 and no list register is in pending state. + 3 + 1 + read-only + + + VGRP0E + enabled group 0 maintenance interrupt +Asserted whenever GICH_HCR.VGRP0EIE is set and GICH_VMCR.VMGRP0EN=1. + 4 + 1 + read-only + + + VGRP0D + disabled group 0 maintenance interrupt +Asserted whenever GICH_HCR.VGRP0DIE is set and GICH_VMCR.VMGRP0EN=0. + 5 + 1 + read-only + + + VGRP1E + enabled group 1 maintenance interrupt +Asserted whenever GICH_HCR.VGRP1EIE is set and GICH_VMCR.VMGRP1EN=1. + 6 + 1 + read-only + + + VGRP1D + disabled group 1 maintenance interrupt +Asserted whenever GICH_HCR.VGRP1DIE is set and GICH_VMCR.VMGRP1EN=0. + 7 + 1 + read-only + + + + + GICH_EISR0 + GICH_EISR0 + GICH end of interrupt status register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EISR0 + end of interrupt status + 0 + 32 + read-only + + + + + GICH_ELSR0 + GICH_ELSR0 + GICH empty list status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ELSR0 + empty list status + 0 + 32 + read-only + + + + + GICH_APR0 + GICH_APR0 + 0xf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + APR0 + active priority + 0 + 32 + read-write + + + + + GICH_LR0 + GICH_LR0 + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VIRTUALID + virtual ID +This ID is returned to the guest OS when the interrupt is acknowledged through the VM interrupt acknowledge register, GICV_IAR. Each valid interrupt stored in the list registers must have a unique virtual ID for that virtual CPU interface. +If the value of VIRTUALID is 1020-1023, behavior is unpredictable. + 0 + 10 + read-write + + + PHYSICALID + physical ID +The function of this bit depends on the value of the GICH_LR.HW bit, as follows. +1) When GICH_LR.HW is set to 0, bits [9:0] have the following meanings: +- [19] EOI when this interrupt triggers an EOI maintenance interrupt +- [12:10] CPUID If the interrupt has the VirtualID for an SGI, that is, 0-15. This field shows the requesting CPU ID. This appears in the relevant field of the virtual machine interrupt acknowledge register, GICV_IAR or GICV_AIAR. Otherwise, this field must be set to 0. +2) When GICH_LR.HW is set to 1, PHYSICALID[9:0] indicates the physical interrupt ID that the hypervisor forwards to the GICD. +If the value of PHYSICALID is 0-15, or 1020-1023, behavior is unpredictable. +If the value of PHYSICALID is 16-31, this field applies to the PPI associated with the same physical CPUID as the virtual CPU interface requesting the deactivation. + 10 + 10 + read-write + + + PRIORITY + priority of the interrupt + 23 + 5 + read-write + + + STATE + state of the interrupt + 28 + 2 + read-write + + + GRP1 + Indicates whether this virtual interrupt is a group 1 virtual interrupt + 30 + 1 + read-write + + + HW + hardware interrupt +Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the PhysicalID field indicates. + 31 + 1 + read-write + + + + + GICH_LR1 + GICH_LR1 + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VIRTUALID + virtual ID +This ID is returned to the guest OS when the interrupt is acknowledged through the VM interrupt acknowledge register, GICV_IAR. Each valid interrupt stored in the list registers must have a unique virtual ID for that virtual CPU interface. +If the value of VIRTUALID is 1020-1023, behavior is unpredictable. + 0 + 10 + read-write + + + PHYSICALID + physical ID +The function of this bit depends on the value of the GICH_LR.HW bit, as follows. +1) When GICH_LR.HW is set to 0, bits [9:0] have the following meanings: +- [19] EOI when this interrupt triggers an EOI maintenance interrupt +- [12:10] CPUID If the interrupt has the VirtualID for an SGI, that is, 0-15. This field shows the requesting CPU ID. This appears in the relevant field of the virtual machine interrupt acknowledge register, GICV_IAR or GICV_AIAR. Otherwise, this field must be set to 0. +2) When GICH_LR.HW is set to 1, PHYSICALID[9:0] indicates the physical interrupt ID that the hypervisor forwards to the GICD. +If the value of PHYSICALID is 0-15, or 1020-1023, behavior is unpredictable. +If the value of PHYSICALID is 16-31, this field applies to the PPI associated with the same physical CPUID as the virtual CPU interface requesting the deactivation. + 10 + 10 + read-write + + + PRIORITY + priority of the interrupt + 23 + 5 + read-write + + + STATE + state of the interrupt + 28 + 2 + read-write + + + GRP1 + Indicates whether this virtual interrupt is a group 1 virtual interrupt + 30 + 1 + read-write + + + HW + hardware interrupt +Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the PhysicalID field indicates. + 31 + 1 + read-write + + + + + GICH_LR2 + GICH_LR2 + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VIRTUALID + virtual ID +This ID is returned to the guest OS when the interrupt is acknowledged through the VM interrupt acknowledge register, GICV_IAR. Each valid interrupt stored in the list registers must have a unique virtual ID for that virtual CPU interface. +If the value of VIRTUALID is 1020-1023, behavior is unpredictable. + 0 + 10 + read-write + + + PHYSICALID + physical ID +The function of this bit depends on the value of the GICH_LR.HW bit, as follows. +1) When GICH_LR.HW is set to 0, bits [9:0] have the following meanings: +- [19] EOI when this interrupt triggers an EOI maintenance interrupt +- [12:10] CPUID If the interrupt has the VirtualID for an SGI, that is, 0-15. This field shows the requesting CPU ID. This appears in the relevant field of the virtual machine interrupt acknowledge register, GICV_IAR or GICV_AIAR. Otherwise, this field must be set to 0. +2) When GICH_LR.HW is set to 1, PHYSICALID[9:0] indicates the physical interrupt ID that the hypervisor forwards to the GICD. +If the value of PHYSICALID is 0-15, or 1020-1023, behavior is unpredictable. +If the value of PHYSICALID is 16-31, this field applies to the PPI associated with the same physical CPUID as the virtual CPU interface requesting the deactivation. + 10 + 10 + read-write + + + PRIORITY + priority of the interrupt + 23 + 5 + read-write + + + STATE + state of the interrupt + 28 + 2 + read-write + + + GRP1 + Indicates whether this virtual interrupt is a group 1 virtual interrupt + 30 + 1 + read-write + + + HW + hardware interrupt +Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the PhysicalID field indicates. + 31 + 1 + read-write + + + + + GICH_LR3 + GICH_LR3 + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VIRTUALID + virtual ID +This ID is returned to the guest OS when the interrupt is acknowledged through the VM interrupt acknowledge register, GICV_IAR. Each valid interrupt stored in the list registers must have a unique virtual ID for that virtual CPU interface. +If the value of VIRTUALID is 1020-1023, behavior is unpredictable. + 0 + 10 + read-write + + + PHYSICALID + physical ID +The function of this bit depends on the value of the GICH_LR.HW bit, as follows. +1) When GICH_LR.HW is set to 0, bits [9:0] have the following meanings: +- [19] EOI when this interrupt triggers an EOI maintenance interrupt +- [12:10] CPUID If the interrupt has the VirtualID for an SGI, that is, 0-15. This field shows the requesting CPU ID. This appears in the relevant field of the virtual machine interrupt acknowledge register, GICV_IAR or GICV_AIAR. Otherwise, this field must be set to 0. +2) When GICH_LR.HW is set to 1, PHYSICALID[9:0] indicates the physical interrupt ID that the hypervisor forwards to the GICD. +If the value of PHYSICALID is 0-15, or 1020-1023, behavior is unpredictable. +If the value of PHYSICALID is 16-31, this field applies to the PPI associated with the same physical CPUID as the virtual CPU interface requesting the deactivation. + 10 + 10 + read-write + + + PRIORITY + priority of the interrupt + 23 + 5 + read-write + + + STATE + state of the interrupt + 28 + 2 + read-write + + + GRP1 + Indicates whether this virtual interrupt is a group 1 virtual interrupt + 30 + 1 + read-write + + + HW + hardware interrupt +Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the PhysicalID field indicates. + 31 + 1 + read-write + + + + + + + GICV + GICV address block description + GIC + 0xA0026000 + + 0x0 + 0x2000 + registers + + + + GICV_CTLR + GICV_CTLR + GICV virtual machine control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLEGRP0 + Enables the signaling of group 0 virtual interrupts by the virtual CPU interface to the virtual machine. + 0 + 1 + read-write + + + ENABLEGRP1 + Enables the signaling of group 1 virtual interrupts by the virtual CPU interface to the virtual machine. + 1 + 1 + read-write + + + ACKCTL + acknowledge control +Controls whether a read of the GICV_IAR, when the highest priority pending interrupt is a group 1 interrupt, causes the CPU interface to acknowledge the interrupt. +Arm deprecates use of this bit. Arm strongly recommends that software is written to operate with this bit always set to 0. + 2 + 1 + read-write + + + FIQEN + FIQ enable for group 0 interrupts +Controls whether interrupts marked as group 0 are presented as virtual FIQs. + 3 + 1 + read-write + + + CBPR + BPR control +Controls whether the GICV_BPR controls both group 0 and group 1 virtual interrupts. + 4 + 1 + read-write + + + EOIMODE + end of interrupt mode +Controls the behavior associated with the GICV_EOIR, GICV_AEOIR, and GICV_DIR registers. + 9 + 1 + read-write + + + + + GICV_PMR + GICV_PMR + GICV VM priority mask register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY + priority mask level for the virtual CPU interface +Only virtual interrupts with higher priority than the value in this register can be signaled to the processor + 3 + 5 + read-write + + + + + GICV_BPR + GICV_BPR + GICV VM binary point register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BINARY_POINT + The value of this field controls how the 8-bit virtual interrupt priority field is split into a group priority field, used to determine virtual interrupt preemption, and a subpriority field. Minimun value is 2. + 0 + 3 + read-write + + + + + GICV_IAR + GICV_IAR + GICV VM interrupt acknowledge register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT_ID + The interrupt ID + 0 + 10 + read-only + + + CPUID + If the GICH_LRx.HW bit is set to 0, indicating that the interrupt is triggered in software, then CPUID of the GICH_LRx, that indicate the CPU ID, are returned in the GICV_IAR.CPUID field. Otherwise GICV_IAR.CPUID field reads as zero. + 10 + 1 + read-only + + + + + GICV_EOIR + GICV_EOIR + 0x10 + 0x20 + 0x00000000 + 0x00000000 + + + EOIINTID + If the GICH_LRx.HW bit in the matching list register is set to 1, indicating a hardware interrupt, then a deactivate request is sent to the physical Distributor, identifying the Physical ID from the corresponding field in the list register. + 0 + 10 + write-only + + + CPUID + On a multiprocessor implementation, if the write refers to an SGI, this field contains the CPUID value from the corresponding GICV_IAR access. + 10 + 1 + write-only + + + + + GICV_RPR + GICV_RPR + GICV VM running priority register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY + current running priority on the virtual CPU interface + 3 + 5 + read-only + + + + + GICV_HPPIR + GICV_HPPIR + GICV VM highest priority pending interrupt register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PENDINTID + The virtual interrupt ID of the highest priority pending virtual interrupt + 0 + 10 + read-only + + + CPUID + On a multiprocessor implementation, if GICH_LRx.HW bit=0, this field contains the CPUID value for that virtual interrupt. This identifies the virtual processor that generated the virtual interrupt. + 10 + 1 + read-only + + + + + GICV_ABPR + GICV_ABPR + GICV VM aliased binary point register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BINARY_POINT + The value of this field controls how the 8-bit virtual interrupt priority field is split into a group priority field, used to determine virtual interrupt preemption, and a subpriority field. Minimun value is 3. + 0 + 3 + read-write + + + + + GICV_AIAR + GICV_AIAR + GICV VM aliased interrupt register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT_ID + The interrupt ID. If the GICH_LRx.Grp1 bit is 0, the interrupt is Group 0. The spurious interrupt ID 1023 is returned and the interrupt is not acknowledged. + 0 + 10 + read-only + + + CPUID + If the GICH_LRx.HW bit is set to 0, indicating that the interrupt is triggered in software, then CPUID of the GICH_LRx, that indicate the CPU ID, are returned in the GICV_AIAR.CPUID field. Otherwise GICV_AIAR.CPUID field reads as zero.. + 10 + 1 + read-only + + + + + GICV_AEOIR + GICV_AEOIR + 0x24 + 0x20 + 0x00000000 + 0x00000000 + + + EOIINTID + If the GICH_LRx.HW bit in the matching list register is set to 1, indicating a hardware interrupt, then a deactivate request is sent to the physical Distributor, identifying the Physical ID from the corresponding field in the list register. + 0 + 10 + write-only + + + CPUID + On a multiprocessor implementation, if the write refers to an SGI, this field contains the CPUID value from the corresponding GICV_IAR access. + 10 + 1 + write-only + + + + + GICV_AHPPIR + GICV_AHPPIR + GICV VM aliased highest priority pending interrupt register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PENDINTID + The virtual interrupt ID of the highest-priority pending virtual interrupt, if that virtual interrupt is a group 1 virtual interrupt. Otherwise, the spurious virtual interrupt ID, 1023. + 0 + 10 + read-only + + + CPUID + If the GICH_LRx.HW bit in the matching List register is set to 1, indicating a hardware interrupt, then a deactivate request is sent to the physical Distributor, identifying the physical ID from the corresponding field in the List register. + 10 + 1 + read-only + + + + + GICV_APR0 + GICV_APR0 + GICV VM active priority register + 0xd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + APR0 + active priority + 0 + 32 + read-write + + + + + GICV_IIDR + GICV_IIDR + GICV VM CPU interface identification register + 0xfc + 0x20 + 0x0102143B + 0xFFFFFFFF + + + IIDR + see description of GICC_IIDR register + 0 + 32 + read-only + + + + + GICV_DIR + GICV_DIR + 0x1000 + 0x20 + 0x00000000 + 0x00000000 + + + INTERRUPT_ID + The interrupt ID + 0 + 10 + write-only + + + CPUID + This field identifies the processor that requested the interrupt. + 10 + 1 + write-only + + + + + + + GPIOA + GPIOA + GPIOA + 0x50002000 + + 0x0 + 0x400 + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOA_LCKR + GPIOA_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOA_SECCFGR + GPIOA_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOA_HWCFGR10 + GPIOA_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOA_HWCFGR9 + GPIOA_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOA_HWCFGR8 + GPIOA_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOA_HWCFGR7 + GPIOA_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOA_HWCFGR6 + GPIOA_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOA_HWCFGR5 + GPIOA_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOA_HWCFGR4 + GPIOA_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOA_HWCFGR3 + GPIOA_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOA_HWCFGR2 + GPIOA_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOA_HWCFGR1 + GPIOA_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOA_HWCFGR0 + GPIOA_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOA_VERR + GPIOA_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOA_IPIDR + GPIOA_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOA_SIDR + GPIOA_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOB + GPIOB + GPIOB + 0x50003000 + + 0x0 + 0x400 + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOB_LCKR + GPIOB_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOB_SECCFGR + GPIOB_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOB_HWCFGR10 + GPIOB_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOB_HWCFGR9 + GPIOB_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOB_HWCFGR8 + GPIOB_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOB_HWCFGR7 + GPIOB_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOB_HWCFGR6 + GPIOB_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOB_HWCFGR5 + GPIOB_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOB_HWCFGR4 + GPIOB_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOB_HWCFGR3 + GPIOB_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOB_HWCFGR2 + GPIOB_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOB_HWCFGR1 + GPIOB_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOB_HWCFGR0 + GPIOB_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOB_VERR + GPIOB_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOB_IPIDR + GPIOB_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOB_SIDR + GPIOB_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOC + GPIOC + GPIOC + 0x50004000 + + 0x0 + 0x400 + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOC_LCKR + GPIOC_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOC_SECCFGR + GPIOC_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOC_HWCFGR10 + GPIOC_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOC_HWCFGR9 + GPIOC_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOC_HWCFGR8 + GPIOC_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOC_HWCFGR7 + GPIOC_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOC_HWCFGR6 + GPIOC_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOC_HWCFGR5 + GPIOC_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOC_HWCFGR4 + GPIOC_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOC_HWCFGR3 + GPIOC_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOC_HWCFGR2 + GPIOC_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOC_HWCFGR1 + GPIOC_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOC_HWCFGR0 + GPIOC_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOC_VERR + GPIOC_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOC_IPIDR + GPIOC_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOC_SIDR + GPIOC_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOD + GPIOD + GPIOD + 0x50005000 + + 0x0 + 0x400 + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOD_LCKR + GPIOD_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOD_SECCFGR + GPIOD_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOD_HWCFGR10 + GPIOD_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOD_HWCFGR9 + GPIOD_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOD_HWCFGR8 + GPIOD_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOD_HWCFGR7 + GPIOD_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOD_HWCFGR6 + GPIOD_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOD_HWCFGR5 + GPIOD_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOD_HWCFGR4 + GPIOD_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOD_HWCFGR3 + GPIOD_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOD_HWCFGR2 + GPIOD_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOD_HWCFGR1 + GPIOD_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOD_HWCFGR0 + GPIOD_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOD_VERR + GPIOD_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOD_IPIDR + GPIOD_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOD_SIDR + GPIOD_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOE + GPIOE + GPIOE + 0x50006000 + + 0x0 + 0x400 + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOE_LCKR + GPIOE_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOE_SECCFGR + GPIOE_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOE_HWCFGR10 + GPIOE_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOE_HWCFGR9 + GPIOE_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOE_HWCFGR8 + GPIOE_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOE_HWCFGR7 + GPIOE_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOE_HWCFGR6 + GPIOE_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOE_HWCFGR5 + GPIOE_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOE_HWCFGR4 + GPIOE_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOE_HWCFGR3 + GPIOE_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOE_HWCFGR2 + GPIOE_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOE_HWCFGR1 + GPIOE_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOE_HWCFGR0 + GPIOE_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOE_VERR + GPIOE_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOE_IPIDR + GPIOE_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOE_SIDR + GPIOE_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOF + GPIOF + GPIOF + 0x50007000 + + 0x0 + 0x400 + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOF_LCKR + GPIOF_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOF_SECCFGR + GPIOF_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOF_HWCFGR10 + GPIOF_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOF_HWCFGR9 + GPIOF_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOF_HWCFGR8 + GPIOF_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOF_HWCFGR7 + GPIOF_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOF_HWCFGR6 + GPIOF_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOF_HWCFGR5 + GPIOF_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOF_HWCFGR4 + GPIOF_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOF_HWCFGR3 + GPIOF_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOF_HWCFGR2 + GPIOF_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOF_HWCFGR1 + GPIOF_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOF_HWCFGR0 + GPIOF_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOF_VERR + GPIOF_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOF_IPIDR + GPIOF_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOF_SIDR + GPIOF_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOG + GPIOG + GPIOG + 0x50008000 + + 0x0 + 0x400 + registers + + + + GPIOG_MODER + GPIOG_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOG_OTYPER + GPIOG_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOG_OSPEEDR + GPIOG_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOG_PUPDR + GPIOG_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOG_IDR + GPIOG_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOG_ODR + GPIOG_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOG_BSRR + GPIOG_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOG_LCKR + GPIOG_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOG_AFRL + GPIOG_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOG_AFRH + GPIOG_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOG_BRR + GPIOG_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOG_SECCFGR + GPIOG_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOG_HWCFGR10 + GPIOG_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOG_HWCFGR9 + GPIOG_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOG_HWCFGR8 + GPIOG_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOG_HWCFGR7 + GPIOG_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOG_HWCFGR6 + GPIOG_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOG_HWCFGR5 + GPIOG_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOG_HWCFGR4 + GPIOG_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOG_HWCFGR3 + GPIOG_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOG_HWCFGR2 + GPIOG_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOG_HWCFGR1 + GPIOG_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOG_HWCFGR0 + GPIOG_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOG_VERR + GPIOG_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOG_IPIDR + GPIOG_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOG_SIDR + GPIOG_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOH + GPIOH + GPIOH + 0x50009000 + + 0x0 + 0x400 + registers + + + + GPIOH_MODER + GPIOH_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOH_OTYPER + GPIOH_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOH_OSPEEDR + GPIOH_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOH_PUPDR + GPIOH_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOH_IDR + GPIOH_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOH_ODR + GPIOH_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOH_BSRR + GPIOH_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOH_LCKR + GPIOH_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOH_AFRL + GPIOH_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOH_AFRH + GPIOH_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOH_BRR + GPIOH_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOH_SECCFGR + GPIOH_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOH_HWCFGR10 + GPIOH_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOH_HWCFGR9 + GPIOH_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOH_HWCFGR8 + GPIOH_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOH_HWCFGR7 + GPIOH_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOH_HWCFGR6 + GPIOH_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOH_HWCFGR5 + GPIOH_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOH_HWCFGR4 + GPIOH_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOH_HWCFGR3 + GPIOH_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOH_HWCFGR2 + GPIOH_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOH_HWCFGR1 + GPIOH_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOH_HWCFGR0 + GPIOH_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOH_VERR + GPIOH_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOH_IPIDR + GPIOH_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOH_SIDR + GPIOH_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOI + GPIOI + GPIOI + 0x5000A000 + + 0x0 + 0x400 + registers + + + + GPIOI_MODER + GPIOI_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOI_OTYPER + GPIOI_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOI_OSPEEDR + GPIOI_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOI_PUPDR + GPIOI_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOI_IDR + GPIOI_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOI_ODR + GPIOI_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOI_BSRR + GPIOI_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOI_LCKR + GPIOI_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOI_AFRL + GPIOI_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOI_AFRH + GPIOI_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOI_BRR + GPIOI_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOI_SECCFGR + GPIOI_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x0000FFFF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + SEC8 + SEC8 + 8 + 1 + + + SEC9 + SEC9 + 9 + 1 + + + SEC10 + SEC10 + 10 + 1 + + + SEC11 + SEC11 + 11 + 1 + + + SEC12 + SEC12 + 12 + 1 + + + SEC13 + SEC13 + 13 + 1 + + + SEC14 + SEC14 + 14 + 1 + + + SEC15 + SEC15 + 15 + 1 + + + + + GPIOI_HWCFGR10 + GPIOI_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOI_HWCFGR9 + GPIOI_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOI_HWCFGR8 + GPIOI_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOI_HWCFGR7 + GPIOI_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOI_HWCFGR6 + GPIOI_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOI_HWCFGR5 + GPIOI_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOI_HWCFGR4 + GPIOI_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOI_HWCFGR3 + GPIOI_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOI_HWCFGR2 + GPIOI_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOI_HWCFGR1 + GPIOI_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOI_HWCFGR0 + GPIOI_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOI_VERR + GPIOI_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOI_IPIDR + GPIOI_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOI_SIDR + GPIOI_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + HASH + HASH register bank + HASH + 0x54003000 + + 0x0 + 0x400 + registers + + + HASH + HASH interrupt + 81 + + + + HASH_CR + HASH_CR + HASH control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INIT + Initialize message digest calculation +Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. +Writing this bit to 0 has no effect. Reading this bit always returns 0. + 2 + 1 + read-write + + + DMAE + DMA enable +After this bit is set, it is cleared by hardware while the last data of the message is written into the hash processor. +Setting this bit to 0 while a DMA transfer is ongoing does not abort the current transfer. Instead, the DMA interface of the HASH remains internally enabled until the transfer is completed or INIT is written to 1. +Setting INIT bit to 1 does not clear DMAE bit. + 3 + 1 + read-write + + + B_0x0 + DMA transfers disabled + 0x0 + + + B_0x1 + DMA transfers enabled. A DMA request is sent as soon as the hash core is ready to receive data. + 0x1 + + + + + DATATYPE + Data type selection +This bitfield defines the format of the data entered into the HASH_DIN register: + 4 + 2 + read-write + + + B_0x0 + 32-bit data. The data written into HASH_DIN are directly used by the HASH processing, without reordering. + 0x0 + + + B_0x1 + 16-bit data or half-word. The data written into HASH_DIN are considered as two half-words, and are swapped before being used by the HASH processing. + 0x1 + + + B_0x2 + 8-bit data or bytes. The data written into HASH_DIN are considered as four bytes, and are swapped before being used by the HASH processing. + 0x2 + + + B_0x3 + bit data or bit string. The data written into HASH_DIN are considered as 32 bits (1st bit of the string at position 0), and are swapped before being used by the HASH processing (1st bit of the string at position 31). + 0x3 + + + + + MODE + Mode selection +This bit selects the normal or the keyed HMAC mode for the selected algorithm: +This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. + 6 + 1 + read-write + + + B_0x0 + Hash mode selected + 0x0 + + + B_0x1 + HMAC mode selected. LKEY bit must be set if the key being used is longer than the algorithm block size. + 0x1 + + + + + NBW + Number of words already pushed +Refer to NBWP[3:0] bitfield of HASH_SR for a description of NBW[3:0] bitfield. +This bit is read-only. + 8 + 4 + read-only + + + DINNE + DIN not empty +Refer to DINNE bit of HASH_SR for a description of DINNE bit. +This bit is read-only. + 12 + 1 + read-only + + + MDMAT + Multiple DMA transfers +This bit is set when hashing large files when multiple DMA transfers are needed. + 13 + 1 + read-write + + + B_0x0 + DCAL is automatically set at the end of a DMA transfer. + 0x0 + + + B_0x1 + DCAL is not automatically set at the end of a DMA transfer. + 0x1 + + + + + DMAA + DMA Abort +This bit is used to abort the usage of DMA to compute a digest. When DMAA is set, DMA requests are no more issued towards the DMA, with DMAE in HASH_CR register and DMAS in HASH_SR register both cleared. +If DMAA is read, DMAA always returns 0. Writing 0 to this bit has no effect. + 14 + 1 + read-write + + + LKEY + Long key selection +The application must set this bit if the HMAC key is greater than the block size corresponding to the hash algorithm (see algorithms for details). For example the block size is 64 bytes for SHA2-256. +This selection is only taken into account when the INIT and MODE bits are set (HMAC mode selected). Changing this bit during a computation has no effect. + 16 + 1 + read-write + + + B_0x0 + HMAC key is shorter or equal to the block size (short key). The actual key value written in HASH_DIN is used during the HMAC computation. + 0x0 + + + B_0x1 + HMAC key is longer than the block size (long key). The hash of the key is used instead of the real key during the HMAC computation. + 0x1 + + + + + ALGO + Algorithm selection +These bits select the hash algorithm: +11xx: reserved +This selection is only taken into account when the INIT bit is set. Changing this bitfield during a computation has no effect. +When the ALGO bitfield is updated and INIT bit is set, NBWE in HASH_SR is automatically updated to 0x11 when ALGO = 0x00XX. + 17 + 4 + read-write + + + B_0x0 + SHA-1 + 0x0 + + + B_0x2 + SHA2-224 + 0x2 + + + B_0x3 + SHA2-256 + 0x3 + + + B_0xC + SHA2-384 + 0xC + + + B_0xD + SHA2-512/224 + 0xD + + + B_0xE + SHA2-512/256 + 0xE + + + B_0xF + SHA2-512 + 0xF + + + B_0x4 + SHA3-224 + 0x4 + + + B_0x5 + SHA3-256 + 0x5 + + + B_0x6 + SHA3-384 + 0x6 + + + B_0x7 + SHA3-512 + 0x7 + + + B_0x8 + SHAKE128 + 0x8 + + + B_0x9 + SHAKE256 + 0x9 + + + B_0xA + RawSHAKE128 + 0xA + + + B_0xB + RawSHAKE256 + 0xB + + + + + + + HASH_DIN + HASH_DIN + HASH data input register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATAIN + Data input +Writing this register pushes the current register content into the FIFO, and the register takes the new value presented on the AHB bus. +Reading this register returns zeros. + 0 + 32 + write-only + + + + + HASH_STR + HASH_STR + HASH start register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NBLW + Number of valid bits in the last word +When the last word of the message bit string is written to HASH_DIN register, the hash processor takes only the valid bits, specified as below, after internal data swapping: +... +Note: When SHA-3 is selected, bits 0 to 2 are kept at zero (byte oriented input). +The above mechanism is valid only if DCAL = 0. If NBLW bits are written while DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not possible to configure NBLW and set DCAL at the same time. +Reading NBLW bits returns the last value written to NBLW. + 0 + 5 + read-write + + + B_0x0 + All the 32 bits of the last data written are valid message bits, that is M[31:0] + 0x0 + + + B_0x1 + Only one bit of the last data written (after swapping) is valid, that is M[0] + 0x1 + + + B_0x2 + Only two bits of the last data written (after swapping) are valid, that is M[1:0] + 0x2 + + + B_0x3 + Only three bits of the last data written (after swapping) are valid that is M[2:0] + 0x3 + + + B_0x1F + Only 31 bits of the last data written (after swapping) are valid that is M[30:0] + 0x1F + + + + + DCAL + Digest calculation +Writing this bit to 1 starts the message padding using the previously written value of NBLW, and starts the calculation of the final message digest with all the data words written to the input FIFO since the INIT bit was last written to 1. +Reading this bit returns 0. + 8 + 1 + read-write + + + + + HASH_HRA0 + HASH_HRA0 + HASH aliased digest register 0 + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + H + Hash data +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HRA1 + HASH_HRA1 + HASH aliased digest register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + H + Hash data +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HRA2 + HASH_HRA2 + HASH aliased digest register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + H + Hash data +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HRA3 + HASH_HRA3 + HASH aliased digest register 3 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + H + Hash data +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HRA4 + HASH_HRA4 + HASH aliased digest register 4 + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + H + Hash data +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_IMR + HASH_IMR + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DINIE + Data input interrupt enable + 0 + 1 + read-write + + + B_0x0 + Data input interrupt disabled + 0x0 + + + B_0x1 + Data input interrupt enabled + 0x1 + + + + + DCIE + Digest calculation completion interrupt enable + 1 + 1 + read-write + + + B_0x0 + Digest calculation completion interrupt disabled + 0x0 + + + B_0x1 + Digest calculation completion interrupt enabled. + 0x1 + + + + + + + HASH_SR + HASH_SR + 0x24 + 0x20 + 0x00110001 + 0xFFFFFFFF + + + DINIS + Data input interrupt status +This bit is set by hardware when the FIFO is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. +When DINIS = 0, HASH_CSRx registers reads as zero. + 0 + 1 + read-write + + + B_0x0 + Less than 16 locations are free in the input buffer + 0x0 + + + B_0x1 + A new block can be entered into the input buffer. An interrupt is generated if the DINIE bit is set in the HASH_IMR register. + 0x1 + + + + + DCIS + Digest calculation completion interrupt status +This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. + 1 + 1 + read-write + + + B_0x0 + No digest available in the HASH_HRx registers (zeros are returned) + 0x0 + + + B_0x1 + Digest calculation complete, a digest is available in the HASH_HRx registers. An interrupt is generated if the DCIE bit is set in the HASH_IMR register. + 0x1 + + + + + DMAS + DMA Status +This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is associated with this bit. + 2 + 1 + read-only + + + B_0x0 + DMA interface is disabled (DMAE = 0) and no transfer is ongoing + 0x0 + + + B_0x1 + DMA interface is enabled (DMAE = 1) or a transfer is ongoing + 0x1 + + + + + BUSY + Busy bit + 3 + 1 + read-only + + + B_0x0 + No block is currently being processed + 0x0 + + + B_0x1 + The hash core is processing a block of data + 0x1 + + + + + NBWP + Number of words already pushed +This bitfield is the exact number of words in the message that have already been pushed into the FIFO. NBWP is incremented by 1 when a write access is performed to the HASH_DIN register. +When a digest calculation starts, NBWP is updated to NBWP- block size (in words), and NBWP goes to zero when the INIT bit is written to 1. + 9 + 6 + read-only + + + DINNE + DIN not empty +This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. + 15 + 1 + read-only + + + B_0x0 + No data are present in the data input buffer + 0x0 + + + B_0x1 + The input buffer contains at least one word of data + 0x1 + + + + + NBWE + Number of words expected +This bitfield reflects the number of words in the message that must be pushed into the FIFO to trigger a partial computation. NBWE is decremented by 1 when a write access is performed to the HASH_DIN register. +NBWE is set to the expected block size +1 in words when INIT bit is set in HASH_CR. It is set to the expected block size when the partial digest calculation ends. + 16 + 6 + read-only + + + + + HASH_CSR0 + HASH_CSR0 + HASH context swap register 0 + 0xf8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS0 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR1 + HASH_CSR1 + HASH context swap register 1 + 0xfc + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS1 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR2 + HASH_CSR2 + HASH context swap register 2 + 0x100 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS2 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR3 + HASH_CSR3 + HASH context swap register 3 + 0x104 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS3 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR4 + HASH_CSR4 + HASH context swap register 4 + 0x108 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS4 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR5 + HASH_CSR5 + HASH context swap register 5 + 0x10c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS5 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR6 + HASH_CSR6 + HASH context swap register 6 + 0x110 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS6 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR7 + HASH_CSR7 + HASH context swap register 7 + 0x114 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS7 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR8 + HASH_CSR8 + HASH context swap register 8 + 0x118 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS8 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR9 + HASH_CSR9 + HASH context swap register 9 + 0x11c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS9 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR10 + HASH_CSR10 + HASH context swap register 10 + 0x120 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS10 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR11 + HASH_CSR11 + HASH context swap register 11 + 0x124 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS11 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR12 + HASH_CSR12 + HASH context swap register 12 + 0x128 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS12 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR13 + HASH_CSR13 + HASH context swap register 13 + 0x12c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS13 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR14 + HASH_CSR14 + HASH context swap register 14 + 0x130 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS14 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR15 + HASH_CSR15 + HASH context swap register 15 + 0x134 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS15 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR16 + HASH_CSR16 + HASH context swap register 16 + 0x138 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS16 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR17 + HASH_CSR17 + HASH context swap register 17 + 0x13c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS17 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR18 + HASH_CSR18 + HASH context swap register 18 + 0x140 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS18 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR19 + HASH_CSR19 + HASH context swap register 19 + 0x144 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS19 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR20 + HASH_CSR20 + HASH context swap register 20 + 0x148 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS20 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR21 + HASH_CSR21 + HASH context swap register 21 + 0x14c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS21 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR22 + HASH_CSR22 + HASH context swap register 22 + 0x150 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS22 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR23 + HASH_CSR23 + HASH context swap register 23 + 0x154 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS23 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR24 + HASH_CSR24 + HASH context swap register 24 + 0x158 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS24 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR25 + HASH_CSR25 + HASH context swap register 25 + 0x15c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS25 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR26 + HASH_CSR26 + HASH context swap register 26 + 0x160 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS26 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR27 + HASH_CSR27 + HASH context swap register 27 + 0x164 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS27 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR28 + HASH_CSR28 + HASH context swap register 28 + 0x168 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS28 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR29 + HASH_CSR29 + HASH context swap register 29 + 0x16c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS29 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR30 + HASH_CSR30 + HASH context swap register 30 + 0x170 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS30 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR31 + HASH_CSR31 + HASH context swap register 31 + 0x174 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS31 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR32 + HASH_CSR32 + HASH context swap register 32 + 0x178 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS32 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR33 + HASH_CSR33 + HASH context swap register 33 + 0x17c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS33 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR34 + HASH_CSR34 + HASH context swap register 34 + 0x180 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS34 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR35 + HASH_CSR35 + HASH context swap register 35 + 0x184 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS35 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR36 + HASH_CSR36 + HASH context swap register 36 + 0x188 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS36 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR37 + HASH_CSR37 + HASH context swap register 37 + 0x18c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS37 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR38 + HASH_CSR38 + HASH context swap register 38 + 0x190 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS38 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR39 + HASH_CSR39 + HASH context swap register 39 + 0x194 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS39 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR40 + HASH_CSR40 + HASH context swap register 40 + 0x198 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS40 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR41 + HASH_CSR41 + HASH context swap register 41 + 0x19c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS41 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR42 + HASH_CSR42 + HASH context swap register 42 + 0x1a0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS42 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR43 + HASH_CSR43 + HASH context swap register 43 + 0x1a4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS43 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR44 + HASH_CSR44 + HASH context swap register 44 + 0x1a8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS44 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR45 + HASH_CSR45 + HASH context swap register 45 + 0x1ac + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS45 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR46 + HASH_CSR46 + HASH context swap register 46 + 0x1b0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS46 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR47 + HASH_CSR47 + HASH context swap register 47 + 0x1b4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS47 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR48 + HASH_CSR48 + HASH context swap register 48 + 0x1b8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS48 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR49 + HASH_CSR49 + HASH context swap register 49 + 0x1bc + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS49 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR50 + HASH_CSR50 + HASH context swap register 50 + 0x1c0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS50 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR51 + HASH_CSR51 + HASH context swap register 51 + 0x1c4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS51 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR52 + HASH_CSR52 + HASH context swap register 52 + 0x1c8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS52 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR53 + HASH_CSR53 + HASH context swap register 53 + 0x1cc + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS53 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR54 + HASH_CSR54 + HASH context swap register 54 + 0x1d0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS54 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR55 + HASH_CSR55 + HASH context swap register 55 + 0x1d4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS55 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR56 + HASH_CSR56 + HASH context swap register 56 + 0x1d8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS56 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR57 + HASH_CSR57 + HASH context swap register 57 + 0x1dc + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS57 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR58 + HASH_CSR58 + HASH context swap register 58 + 0x1e0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS58 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR59 + HASH_CSR59 + HASH context swap register 59 + 0x1e4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS59 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR60 + HASH_CSR60 + HASH context swap register 60 + 0x1e8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS60 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR61 + HASH_CSR61 + HASH context swap register 61 + 0x1ec + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS61 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR62 + HASH_CSR62 + HASH context swap register 62 + 0x1f0 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS62 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR63 + HASH_CSR63 + HASH context swap register 63 + 0x1f4 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS63 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR64 + HASH_CSR64 + HASH context swap register 64 + 0x1f8 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS64 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR65 + HASH_CSR65 + HASH context swap register 65 + 0x1fc + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS65 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR66 + HASH_CSR66 + HASH context swap register 66 + 0x200 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS66 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR67 + HASH_CSR67 + HASH context swap register 67 + 0x204 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS67 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR68 + HASH_CSR68 + HASH context swap register 68 + 0x208 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS68 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR69 + HASH_CSR69 + HASH context swap register 69 + 0x20c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS69 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR70 + HASH_CSR70 + HASH context swap register 70 + 0x210 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS70 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR71 + HASH_CSR71 + HASH context swap register 71 + 0x214 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS71 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR72 + HASH_CSR72 + HASH context swap register 72 + 0x218 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS72 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR73 + HASH_CSR73 + HASH context swap register 73 + 0x21c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS73 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR74 + HASH_CSR74 + HASH context swap register 74 + 0x220 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS74 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR75 + HASH_CSR75 + HASH context swap register 75 + 0x224 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS75 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR76 + HASH_CSR76 + HASH context swap register 76 + 0x228 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS76 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR77 + HASH_CSR77 + HASH context swap register 77 + 0x22c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS77 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR78 + HASH_CSR78 + HASH context swap register 78 + 0x230 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS78 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR79 + HASH_CSR79 + HASH context swap register 79 + 0x234 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS79 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR80 + HASH_CSR80 + HASH context swap register 80 + 0x238 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CS80 + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR81 + HASH_CSR81 + HASH context swap register 81 + 0x23c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR82 + HASH_CSR82 + HASH context swap register 82 + 0x240 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR83 + HASH_CSR83 + HASH context swap register 83 + 0x244 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR84 + HASH_CSR84 + HASH context swap register 84 + 0x248 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR85 + HASH_CSR85 + HASH context swap register 85 + 0x24c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR86 + HASH_CSR86 + HASH context swap register 86 + 0x250 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR87 + HASH_CSR87 + HASH context swap register 87 + 0x254 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR88 + HASH_CSR88 + HASH context swap register 88 + 0x258 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR89 + HASH_CSR89 + HASH context swap register 89 + 0x25c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR90 + HASH_CSR90 + HASH context swap register 90 + 0x260 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR91 + HASH_CSR91 + HASH context swap register 91 + 0x264 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR92 + HASH_CSR92 + HASH context swap register 92 + 0x268 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR93 + HASH_CSR93 + HASH context swap register 93 + 0x26c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR94 + HASH_CSR94 + HASH context swap register 94 + 0x270 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR95 + HASH_CSR95 + HASH context swap register 95 + 0x274 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR96 + HASH_CSR96 + HASH context swap register 96 + 0x278 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR97 + HASH_CSR97 + HASH context swap register 97 + 0x27c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR98 + HASH_CSR98 + HASH context swap register 98 + 0x280 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR99 + HASH_CSR99 + HASH context swap register 99 + 0x284 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR100 + HASH_CSR100 + HASH context swap register 100 + 0x288 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR101 + HASH_CSR101 + HASH context swap register 101 + 0x28c + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_CSR102 + HASH_CSR102 + HASH context swap register 102 + 0x290 + 0x20 + 0x00220002 + 0xFFFFFFFF + + + CSx + Context swap x (x = 0 to 102) +Refer to introduction. + 0 + 32 + read-write + + + + + HASH_HR0 + HASH_HR0 + 0x310 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 0 to 4) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR1 + HASH_HR1 + 0x314 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 0 to 4) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR2 + HASH_HR2 + 0x318 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 0 to 4) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR3 + HASH_HR3 + 0x31c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 0 to 4) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR4 + HASH_HR4 + 0x320 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 0 to 4) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR5 + HASH_HR5 + 0x324 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR6 + HASH_HR6 + 0x328 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR7 + HASH_HR7 + 0x32c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR8 + HASH_HR8 + 0x330 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR9 + HASH_HR9 + 0x334 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR10 + HASH_HR10 + 0x338 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR11 + HASH_HR11 + 0x33c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR12 + HASH_HR12 + 0x340 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR13 + HASH_HR13 + 0x344 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR14 + HASH_HR14 + 0x348 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR15 + HASH_HR15 + 0x34c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR16 + HASH_HR16 + 0x350 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR17 + HASH_HR17 + 0x354 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR18 + HASH_HR18 + 0x358 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR19 + HASH_HR19 + 0x35c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR20 + HASH_HR20 + 0x360 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR21 + HASH_HR21 + 0x364 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR22 + HASH_HR22 + 0x368 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR23 + HASH_HR23 + 0x36c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR24 + HASH_HR24 + 0x370 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR25 + HASH_HR25 + 0x374 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR26 + HASH_HR26 + 0x378 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR27 + HASH_HR27 + 0x37c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR28 + HASH_HR28 + 0x380 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR29 + HASH_HR29 + 0x384 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR30 + HASH_HR30 + 0x388 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR31 + HASH_HR31 + 0x38c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR32 + HASH_HR32 + 0x390 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR33 + HASH_HR33 + 0x394 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR34 + HASH_HR34 + 0x398 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR35 + HASH_HR35 + 0x39c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR36 + HASH_HR36 + 0x3a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR37 + HASH_HR37 + 0x3a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR38 + HASH_HR38 + 0x3a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR39 + HASH_HR39 + 0x3ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR40 + HASH_HR40 + 0x3b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR41 + HASH_HR41 + 0x3b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR42 + HASH_HR42 + 0x3b8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR43 + HASH_HR43 + 0x3bc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR44 + HASH_HR44 + 0x3c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR45 + HASH_HR45 + 0x3c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR46 + HASH_HR46 + 0x3c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR47 + HASH_HR47 + 0x3cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR48 + HASH_HR48 + 0x3d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HR49 + HASH_HR49 + 0x3d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + Hx + Hash data x (x = 5 to 49) +Refer to introduction. + 0 + 32 + read-only + + + + + HASH_HWCFGR + HASH_HWCFGR + 0x3f0 + 0x20 + 0x00010111 + 0xFFFFFFFF + + + CFG1 + HW generic 1 +this bitfield reflects the DMA type connected to this HASH peripheral. + 0 + 4 + read-only + + + CFG2 + HW generic 2 +This bitfield reflects that the HMAC is supported. + 4 + 4 + read-only + + + CFG3 + HW generic 3 +This bitfield reflects that the SHA3 algorithm is supported. + 8 + 4 + read-only + + + CFG4 + HW generic 4 +This bitfield is read as zero. + 12 + 4 + read-only + + + CFG5 + HW generic 5 +This bitfield reflects that the SHA384 and SHA512 algorithms are supported. + 16 + 4 + read-only + + + + + HASH_VERR + HASH_VERR + 0x3f4 + 0x20 + 0x00000040 + 0xFFFFFFFF + + + MINREV + Minor revision +These bits return the HASH minor revision + 0 + 4 + read-only + + + MAJREV + Major revision +These bits return the HASH major revision + 4 + 4 + read-only + + + + + HASH_IPIDR + HASH_IPIDR + 0x3f8 + 0x20 + 0x00170031 + 0xFFFFFFFF + + + ID + [31: 0]: Identifier +These bits return the unique identifier of the HASH peripheral. + 0 + 32 + read-only + + + + + HASH_SIDR + HASH_SIDR + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification code +This bitfield returns the size identification code of the HASH peripheral as defined below: +Bits[31:8] = 0xA3C5DD (fixed code) +Bits[7:0] = 0x01 (1-Kbyte address decoding) + 0 + 32 + read-only + + + + + + + HDP + HDP register block + HDP + 0x5002A000 + + 0x0 + 0x400 + registers + + + + HDP_CTRL + HDP_CTRL + HDP control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable HDP +Valid if enabled in BSEC. + 0 + 1 + read-write + + + + + HDP_MUX + HDP_MUX + HDP multiplexers control register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MUX0 + Select the HDP0 output among the 16 available signals + 0 + 4 + read-write + + + MUX1 + Select the HDP1 output among the 16 available signals + 4 + 4 + read-write + + + MUX2 + Select the HDP2 output among the 16 available signals + 8 + 4 + read-write + + + MUX3 + Select the HDP3 output among the 16 available signals + 12 + 4 + read-write + + + MUX4 + Select the HDP4 output among the 16 available signals + 16 + 4 + read-write + + + MUX5 + Select the HDP5 output among the 16 available signals + 20 + 4 + read-write + + + MUX6 + Select the HDP6 output among the 16 available signals + 24 + 4 + read-write + + + MUX7 + Select the HDP7 output among the 16 available signals + 28 + 4 + read-write + + + + + HDP_VAL + HDP_VAL + HDP read back value register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HDPVAL + HDP read back value +Provides the value of the HDP signals. + 0 + 8 + read-only + + + + + HDP_GPOSET + HDP_GPOSET + HDP general purpose output set register + 0x14 + 0x20 + 0x00000000 + 0x00000000 + + + HDPGPOSET + HDP general purpose output set +When a bit is written to 1, the corresponding HDP GPO is set. Writing a bit to 0 has no effect. + 0 + 8 + write-only + + + + + HDP_GPOCLR + HDP_GPOCLR + HDP general purpose output clear register + 0x18 + 0x20 + 0x00000000 + 0x00000000 + + + HDPGPOCLR + HDP general purpose output clear +When a bit is written to 1, the corresponding HDP GPO is cleared. Writing a bit to 0 has no effect. + 0 + 8 + write-only + + + + + HDP_GPOVAL + HDP_GPOVAL + HDP general purpose output value register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HDPGPOVAL + HDP general purpose output value +When written, defines the value of the HDP GPO. When read, provides the current GPO value. + 0 + 8 + read-write + + + + + HDP_VERR + HDP_VERR + HDP version register + 0x3f4 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MINREV + Minor revision of the IP + 0 + 4 + read-only + + + MAJREV + Major revision of the IP + 4 + 4 + read-only + + + + + HDP_IPIDR + HDP_IPIDR + HDP IP identification register + 0x3f8 + 0x20 + 0x00030002 + 0xFFFFFFFF + + + ID + IP Identifier + 0 + 32 + read-only + + + + + HDP_SIDR + HDP_SIDR + HDP size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identifier + 0 + 32 + read-only + + + + + + + IWDG1 + IWDG1 + IWDG1 + 0x5C003000 + + 0x0 + 0x400 + registers + + + IWDG1_IT + IWDG1 early wake + 126 + + + + IWDG_KR + IWDG_KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + KEY + 0 + 16 + + + + + IWDG_PR + IWDG_PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000007 + + + PR + PR + 0 + 3 + + + + + IWDG_RLR + IWDG_RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + RL + 0 + 12 + + + + + IWDG_SR + IWDG_SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + PVU + 0 + 1 + + + RVU + RVU + 1 + 1 + + + WVU + WVU + 2 + 1 + + + + + IWDG_WINR + IWDG_WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + WIN + 0 + 12 + + + + + IWDG_HWCFGR + IWDG_HWCFGR + IWDG hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000111 + + + WINDOW + WINDOW + 0 + 4 + + + PR_DEFAULT + PR_DEFAULT + 4 + 4 + + + + + IWDG_VERR + IWDG_VERR + IWDG version register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + IWDG_IDR + IWDG_IDR + IWDG identification register + 0x3F8 + 0x20 + read-only + 0x00120041 + + + ID + ID + 0 + 32 + + + + + IWDG_SIDR + IWDG_SIDR + IWDG size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + IWDG2 + 0x5A002000 + + IWDG2_IT + IWDG2 early wake + 127 + + + + I2C1 + I2C + I2C + 0x40012000 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 32 + + + I2C1_ERR + I2C1 global error interrupt + 33 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match Interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received Interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection Interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer Complete interrupt enable +Note: Any of these events generate an interrupt: +Transfer Complete (TC) +Transfer Complete Reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer Complete interrupt disabled + 0x0 + + + B_0x1 + Transfer Complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK +... +Note: If the analog filter is also enabled, the digital filter is added to the analog filter. +This filter can only be programmed when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 tI2CCLK + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 tI2CCLK + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wakeup from Stop mode enable +Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . +Note: WUPEN can be set only when DNF = ‘0000’ + 18 + 1 + read-write + + + B_0x0 + Wakeup from Stop mode disable. + 0x0 + + + B_0x1 + Wakeup from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] should be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer. + 0x0 + + + B_0x1 + Master requests a read transfer. + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode, + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit generates a START condition once the bus is free. +Note: Writing ‘0’ to this bit has no effect. +The START bit can be set even if the bus is BUSY or I2C is in slave mode. +This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation. + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In Master Mode: +Note: Writing ‘0’ to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation. + 0x0 + + + B_0x1 + Stop generation after current byte transfer. + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. +Note: Writing ‘0’ to this bit has no effect. +This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. +When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. +Note: Writing ‘0’ to this bit has no effect. +This bit has no effect when RELOAD is set. +This bit has no effect is slave mode when SBC=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 26 + 1 + read-write + + + B_0x0 + No PEC transfer. + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN=0. + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +Note: This bit can be written only when OA1EN=0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own Address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +Note: These bits can be written only when OA2EN=0. +As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don’t care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own Address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale i2c_ker_ck in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK +The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to ‘1’ by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I2C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I2C bus +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + I2C_HWCFGR + I2C_HWCFGR + I2C hardware configuration register + 0x3f0 + 0x20 + read-only + 0x00000111 + 0xFFFFFFFF + + + SMBUS + SMBus mode + 0 + 4 + read-only + + + B_0x0 + SMBus mode not implemented + 0x0 + + + B_0x1 + SMBus mode implemented + 0x1 + + + + + ASYN + Independent kernel clock + 4 + 4 + read-only + + + B_0x0 + Independent kernel clock not implemented + 0x0 + + + B_0x1 + Independent kernel clock implemented + 0x1 + + + + + WKP + Wakeup from Stop mode + 8 + 4 + read-only + + + B_0x0 + Wakeup from Stop mode not implemented + 0x0 + + + B_0x1 + Wakeup from Stop mode implemented + 0x1 + + + + + + + I2C_VERR + I2C_VERR + I2C version register + 0x3f4 + 0x20 + 0x00000014 + 0xFFFFFFFF + + + MINREV + Minor revision + 0 + 4 + read-only + + + MAJREV + Major revision + 4 + 4 + read-only + + + + + I2C_IPIDR + I2C_IPIDR + I2C identification register + 0x3f8 + 0x20 + 0x00130012 + 0xFFFFFFFF + + + ID + Identifier. + 0 + 32 + read-only + + + + + I2C_SIDR + I2C_SIDR + I2C size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identifier. + 0 + 32 + read-only + + + + + + + I2C2 + 0x40013000 + + I2C2_EVT + I2C2 event interrupt + 34 + + + I2C2_ERR + I2C2 global error interrupt + 35 + + + + I2C3 + 0x4C004000 + + I2C3_EVT + I2C3 event interrupt + 73 + + + I2C3_ERR + I2C3 global error interrupt + 74 + + + + I2C4 + 0x4C005000 + + I2C4_EVT + I2C4 event interrupt + 93 + + + I2C4_ERR + I2C4 global error interrupt + 94 + + + + I2C5 + 0x4C006000 + + I2C5_EVT + I2C5 event interrupt + 114 + + + I2C5_ERR + I2C5 global error interrupt + 115 + + + + LPTIM1 + LPTIM + LPTIM + 0x40009000 + + 0x0 + 0x0400 + registers + + + LPTIM1 + LPTIMER1 global interrupt + 92 + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMPM + Compare match +The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. + 0 + 1 + read-only + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMPOK + Compare register update OK +CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 6 + 1 + read-only + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMPMCF + Compare match clear flag +Writing 1 to this bit clears the CMPM flag in the LPTIM_ISR register + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMPOKCF + Compare register update OK clear flag +Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 6 + 1 + write-only + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + read-write + + + B_0x0 + CMPM interrupt disabled + 0x0 + + + B_0x1 + CMPM interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + read-write + + + B_0x0 + CMPOK interrupt disabled + 0x0 + + + B_0x1 + CMPOK interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM will use: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +If LPTIM is clocked by an external clock source: +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +Refer to for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: +See for details. + 13 + 3 + read-write + + + B_0x0 + lptim_ext_trig0 + 0x0 + + + B_0x1 + lptim_ext_trig1 + 0x1 + + + B_0x2 + lptim_ext_trig2 + 0x2 + + + B_0x3 + lptim_ext_trig3 + 0x3 + + + B_0x4 + lptim_ext_trig4 + 0x4 + + + B_0x5 + lptim_ext_trig5 + 0x5 + + + B_0x6 + lptim_ext_trig6 + 0x6 + + + B_0x7 + lptim_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started will be ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started will reset and restart the counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode, PWM or One Pulse waveform depending on how the timer was started, CNTSTRT for PWM or SNGSTRT for One Pulse waveform. + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + WAVPOL + Waveform shape polarity +The WAVEPOL bit controls the output polarity + 21 + 1 + read-write + + + B_0x0 + The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers + 0x0 + + + B_0x1 + The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to . + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. +This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = '00’), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than '00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content. + 4 + 1 + read-write + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMP + Compare value +CMP is the compare value used by the LPTIM. + 0 + 16 + read-write + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CMP[15:0] value. + 0 + 16 + read-write + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. +It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. + 0 + 16 + read-only + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. +For connection details refer to . +Note: If LPTIM does not implement external input clock, these bits are reserved. Please refer to . + 0 + 2 + read-write + + + B_0x0 + lptim_in1_mux0 + 0x0 + + + B_0x1 + lptim_in1_mux1 + 0x1 + + + B_0x2 + lptim_in1_mux2 + 0x2 + + + B_0x3 + lptim_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. +For connection details refer to . +Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to . + 4 + 2 + read-write + + + B_0x0 + lptim_in2_mux0 + 0x0 + + + B_0x1 + lptim_in2_mux1 + 0x1 + + + B_0x2 + lptim_in2_mux2 + 0x2 + + + B_0x3 + lptim_in2_mux3 + 0x3 + + + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3f4 + 0x20 + 0x00000014 + 0xFFFFFFFF + + + MINREV + Minor revision +This is a read only bit-field and is read as MINREV[3:0] = 4. + 0 + 4 + read-only + + + MAJREV + Major revision +This is read only bit-field and is read as MAJREV[7:4] = 1. + 4 + 4 + read-only + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3f8 + 0x20 + 0x00120011 + 0xFFFFFFFF + + + P_ID + Peripheral type identifier +This a read only register and is always read as P_ID[31:0] = 0x00120011. + 0 + 32 + read-only + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + S_ID + Registers map size identifier +This a read only register and is always read as S_ID[31:0] = 0xA3C5DD01. +This register identifies the size of the memory region allocated to the LPTIM registers. The size of this memory region is 1 KB. + 0 + 32 + read-only + + + + + + + LPTIM2 + 0x50021000 + + LPTIM2 + LPTIMER2 global interrupt + 116 + + + + LPTIM3 + 0x50022000 + + LPTIM3 + LPTIMER3 global interrupt + 117 + + + + LPTIM4 + 0x50023000 + + LPTIM4 + LPTIMER4 global interrupt + 118 + + + + LPTIM5 + 0x50024000 + + LPTIM5 + LPTIMER5 global interrupt + 119 + + + + LTDC + LTDC register block + LTDC + 0x5A001000 + + 0x0 + 0x400 + registers + + + LTDC + LTCD global interrupt + 88 + + + + LTDC_IDR + LTDC_IDR + LTDC identification register + 0x0 + 0x20 + 0x00040100 + 0xFFFFFFFF + + + REV + revision + 0 + 8 + read-only + + + MINVER + minor version + 8 + 8 + read-only + + + MAJVER + major version + 16 + 8 + read-only + + + + + LTDC_LCR + LTDC_LCR + LDTC layer count register + 0x4 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + LNBR + number of layers + 0 + 8 + read-only + + + + + LTDC_SSCR + LTDC_SSCR + LTDC synchronization size configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + VSH + vertical synchronization height (in units of horizontal scan line) +This field defines the vertical synchronization height minus 1. It represents the number of horizontal synchronization lines. + 0 + 16 + read-write + + + HSW + horizontal synchronization width (in units of pixel clock period) +This field defines the number of horizontal synchronization pixel minus 1. + 16 + 16 + read-write + + + + + LTDC_BPCR + LTDC_BPCR + LTDC back porch configuration register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AVBP + accumulated Vertical back porch (in units of horizontal scan line) +This field defines the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1. +The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. + 0 + 16 + read-write + + + AHBP + accumulated horizontal back porch (in units of pixel clock period) +This field defines the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1. +The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. + 16 + 16 + read-write + + + + + LTDC_AWCR + LTDC_AWCR + LTDC active width configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AAH + accumulated active height (in units of horizontal scan line) +This field defines the accumulated height that includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel. +Refer to device datasheet for maximum active height supported following maximum pixel clock. + 0 + 16 + read-write + + + AAW + accumulated active width (in units of pixel clock period) +This field defines the accumulated active width that includes the horizontal synchronization, horizontal back porch and active pixels minus 1. The active width is the number of pixels in active display area of the panel scan line. +Refer to device datasheet for maximum active width supported following maximum pixel clock. + 16 + 16 + read-write + + + + + LTDC_TWCR + LTDC_TWCR + LTDC total width configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TOTALH + total height (in units of horizontal scan line) +This field defines the accumulated height that includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. + 0 + 16 + read-write + + + TOTALW + total width (in units of pixel clock period) +This field defines the accumulated total width that includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. + 16 + 16 + read-write + + + + + LTDC_GCR + LTDC_GCR + LTDC global control register + 0x18 + 0x20 + 0x00002220 + 0xFFFFFFFF + + + LTDCEN + LTDC global enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LTDC disabled + 0x0 + + + B_0x1 + LTDC enabled + 0x1 + + + + + GAMEN + Gamma correction enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Gamma correction disabled (pixels bypass the gamma operator) + 0x0 + + + B_0x1 + Gamma correction enabled + 0x1 + + + + + DBW + dither blue width +This field returns the dither blue bits. + 4 + 3 + read-only + + + DGW + dither green width +This field returns the dither green bits. + 8 + 3 + read-only + + + DRW + dither red width +This field returns the dither red bits. + 12 + 3 + read-only + + + DEN + dither enable +This bit is set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + dither disabled + 0x0 + + + B_0x1 + dither enabled + 0x1 + + + + + CRCEN + CRC enable +This bit is set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + CRC disabled + 0x0 + + + B_0x1 + CRC enabled + 0x1 + + + + + SFEN + single-frame mode: mode enable +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + single-frame disabled: a trigger (on SFSWTR) generates a continuous flow. + 0x0 + + + B_0x1 + single-frame enabled: a trigger (on SFSWTR) generates a single frame. + 0x1 + + + + + SFSWTR + single-frame mode: software trigger +This bit is set by software and cleared by hardware. + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + triggers one frame + 0x1 + + + + + PCPOL + pixel clock polarity +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + the pixel and sync data are generated at the rising-edge of the output LCD_CLK clock. + 0x0 + + + B_0x1 + the pixel and sync data are generated at the falling-edge of the output LCD_CLK clock. + 0x1 + + + + + DEPOL + blanking (no data/pixel) polarity +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + blanking (no data/pixel) polarity is active low. + 0x0 + + + B_0x1 + blanking (no data/pixel) polarity is active high. + 0x1 + + + + + VSPOL + vertical synchronization polarity +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + vertical synchronization is active low. + 0x0 + + + B_0x1 + vertical synchronization is active high. + 0x1 + + + + + HSPOL + horizontal synchronization polarity +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + horizontal synchronization polarity is active low. + 0x0 + + + B_0x1 + horizontal synchronization polarity is active high. + 0x1 + + + + + + + LTDC_GC1R + LTDC_GC1R + LTDC global configuration 1 register + 0x1c + 0x20 + 0x6BE4D888 + 0xFFFFFFFF + + + WBCH + width of blue channel output + 0 + 4 + read-only + + + WGCH + width of green channel output + 4 + 4 + read-only + + + WRCH + width of red channel output + 8 + 4 + read-only + + + PRBA + precise blending ability + 12 + 1 + read-only + + + DT + dithering technique implemented +1.: ordered 4x4 custom + 14 + 2 + read-only + + + B_0x0 + no dithering + 0x0 + + + B_0x1 + ordered 4x4 Bayer + 0x1 + + + B_0x3 + pseudo-random LFSR + 0x3 + + + + + GCT + gamma correction technique implemented +others: reserved + 17 + 3 + read-only + + + B_0x0 + no gamma + 0x0 + + + B_0x1 + gamma with 256 samples + 0x1 + + + B_0x2 + gamma with 8 interpolated segments + 0x2 + + + + + SHRA + shadow registers ability + 21 + 1 + read-only + + + BCP + background color programmability (unique color blended as background) + 22 + 1 + read-only + + + BBA + background blending ability + 23 + 1 + read-only + + + LNIP + line-IRQ: line position programmability + 24 + 1 + read-only + + + TP + timing programmability + 25 + 1 + read-only + + + SPP + sync polarity programmability + 27 + 1 + read-only + + + DWP + dither width programmability + 28 + 1 + read-only + + + STRA + status register ability + 29 + 1 + read-only + + + CRMA + configuration reading mode ability + 30 + 1 + read-only + + + BMA + blind mode ability + 31 + 1 + read-only + + + + + LTDC_GC2R + LTDC_GC2R + LTDC global configuration 2 register + 0x20 + 0x20 + 0x0000BB30 + 0xFFFFFFFF + + + BLA + background layer ability (pixels of background layer are read from memory) + 0 + 1 + read-only + + + STSA + slave timings synchronization ability + 1 + 1 + read-only + + + DVA + dual-view ability + 2 + 1 + read-only + + + DPA + secondary RGB output port ability + 3 + 1 + read-only + + + BW + bus width (log2 of number of bytes) +others: reserved + 4 + 3 + read-only + + + B_0x2 + 32-bit bus + 0x2 + + + B_0x3 + 64-bit bus + 0x3 + + + B_0x4 + 128-bit bus + 0x4 + + + + + EDCA + external display control ability + 7 + 1 + read-only + + + OCA + output conversion ability (RGB to YCbCr) + 8 + 1 + read-only + + + AXIIDA + AXIID ability + 9 + 1 + read-only + + + ROTA + rotation support ability + 10 + 1 + read-only + + + SISA + second interrupt set ability + 11 + 1 + read-only + + + B_0x0 + second interrupt set not available + 0x0 + + + B_0x1 + second interrupt set available + 0x1 + + + + + SFA + single frame mode ability + 12 + 1 + read-only + + + B_0x0 + single frame not available + 0x0 + + + B_0x1 + single frame available + 0x1 + + + + + CRCA + CRC ability + 13 + 1 + read-only + + + B_0x0 + CRC no computation available + 0x0 + + + B_0x1 + CRC computation available + 0x1 + + + + + BOA + blending order ability + 15 + 1 + read-only + + + B_0x0 + blending order fixed + 0x0 + + + B_0x1 + blending order configurable + 0x1 + + + + + + + LTDC_SRCR + LTDC_SRCR + LTDC shadow reload configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMR + immediate reload trigger +This bit is set by software and cleared only by hardware after reload. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded immediately. + 0x1 + + + + + VBR + vertical blanking reload request +This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 0x1 + + + + + + + LTDC_GCCR + LTDC_GCCR + LTDC gamma correction configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR + address of the R,G,B table where the COMP component is written +When LTDC_GC1R.GCT=2, the gamma is implemented with eight interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255. +Note: For ADDR = 255, the gamma interpolation hardware considers that the address is 256. + 0 + 8 + write-only + + + COMP + color component to be written, in either (or all) the R,G,B tables + 8 + 8 + write-only + + + BEN + write trigger to the blue table + 16 + 1 + write-only + + + B_0x0 + no action done + 0x0 + + + B_0x1 + COMP is written at ADDR in the blue table. + 0x1 + + + + + GEN + write trigger to the green table + 17 + 1 + write-only + + + B_0x0 + no action done + 0x0 + + + B_0x1 + COMP is written at ADDR in the green table. + 0x1 + + + + + REN + write trigger to the red table + 18 + 1 + write-only + + + B_0x0 + no action done + 0x0 + + + B_0x1 + COMP is written at ADDR in the red table. + 0x1 + + + + + + + LTDC_BCCR + LTDC_BCCR + LTDC background color configuration register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BCBLUE + background color blue value +This field configures the background blue value. + 0 + 8 + read-write + + + BCGREEN + background color green value +This field configures the background green value. + 8 + 8 + read-write + + + BCRED + background color red value +This field configures the background red value. + 16 + 8 + read-write + + + + + LTDC_IER + LTDC_IER + LTDC interrupt enable register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIE + Line interrupt enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + line interrupt disabled + 0x0 + + + B_0x1 + line interrupt enabled + 0x1 + + + + + FUWIE + FIFO underrun warning interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + FIFO underrun interrupt disabled + 0x0 + + + B_0x1 + FIFO underrun Interrupt enabled + 0x1 + + + + + TERRIE + Transfer Error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + transfer error interrupt disabled + 0x0 + + + B_0x1 + transfer error interrupt enabled + 0x1 + + + + + RRIE + Register reload interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + register reload interrupt disabled + 0x0 + + + B_0x1 + register reload interrupt enabled + 0x1 + + + + + FUIE + FIFO underrun interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + FIFO underrun interrupt disabled + 0x0 + + + B_0x1 + FIFO underrun Interrupt enabled + 0x1 + + + + + CRCIE + CRC error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + CRC error disabled + 0x0 + + + B_0x1 + CRC error interrupt enabled + 0x1 + + + + + + + LTDC_ISR + LTDC_ISR + LTDC interrupt status register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIF + Line interrupt flag + 0 + 1 + read-only + + + B_0x0 + no line interrupt generated + 0x0 + + + B_0x1 + line interrupt generated when a programmed line is reached + 0x1 + + + + + FUWIF + FIFO underrun warning interrupt flag + 1 + 1 + read-only + + + B_0x0 + no FIFO underrun warning interrupt generated + 0x0 + + + B_0x1 + FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO + 0x1 + + + + + TERRIF + Transfer error interrupt flag + 2 + 1 + read-only + + + B_0x0 + no transfer error interrupt generated + 0x0 + + + B_0x1 + transfer error interrupt generated when a bus error occurs + 0x1 + + + + + RRIF + Register reload interrupt flag + 3 + 1 + read-only + + + B_0x0 + no register reload interrupt generated + 0x0 + + + B_0x1 + register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + 0x1 + + + + + FUIF + FIFO underrun interrupt flag + 6 + 1 + read-only + + + B_0x0 + no FIFO underrun interrupt generated + 0x0 + + + B_0x1 + FIFO underrun interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO + 0x1 + + + + + CRCIF + CRC error interrupt flag + 7 + 1 + read-only + + + B_0x0 + no CRC error interrupt generated + 0x0 + + + B_0x1 + CRC error interrupt generated when a bus error occurs + 0x1 + + + + + + + LTDC_ICR + LTDC_ICR + LTDC interrupt clear register + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLIF + clears the line interrupt flag + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the LIF flag in LTDC_ISR. + 0x1 + + + + + CFUWIF + clears the FIFO underrun warning interrupt flag + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the FUWIF flag in LTDC_ISR. + 0x1 + + + + + CTERRIF + clears the transfer error interrupt flag + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the TERRIF flag in LTDC_ISR. + 0x1 + + + + + CRRIF + clears register reload interrupt flag + 3 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the RRIF flag in LTDC_ISR. + 0x1 + + + + + CFUIF + clears the FIFO underrun interrupt flag + 6 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the FUIF flag in LTDC_ISR. + 0x1 + + + + + CCRCIF + clears the CRC error interrupt flag + 7 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the CRCIF flag in LTDC_ISR. + 0x1 + + + + + + + LTDC_LIPCR + LTDC_LIPCR + LTDC line interrupt position configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIPOS + line interrupt position +This field configures the line interrupt position. + 0 + 16 + read-write + + + + + LTDC_CPSR + LTDC_CPSR + LTDC current position status register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CYPOS + current Y position +This field returns the current Y position. + 0 + 16 + read-only + + + CXPOS + current X position +This field returns the current X position. + 16 + 16 + read-only + + + + + LTDC_CDSR + LTDC_CDSR + LTDC current display status register + 0x48 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + VDES + vertical data enable display status + 0 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + HDES + horizontal data enable display status + 1 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + VSYNCS + vertical synchronization display status + 2 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + HSYNCS + horizontal synchronization display status + 3 + 1 + read-only + + + B_0x0 + active low + 0x0 + + + B_0x1 + active high + 0x1 + + + + + + + LTDC_EDCR + LTDC_EDCR + LTDC external display control register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OCYEN + output conversion to YCbCr 422 enable + 25 + 1 + read-write + + + B_0x0 + conversion disabled + 0x0 + + + B_0x1 + conversion enabled + 0x1 + + + + + OCYSEL + output conversion to YCbCr 422 +This bit selects the set of CCIR hard-wired coefficients (ITU-R BT.601 or 709). + 26 + 1 + read-write + + + B_0x0 + use ITU-R BT.601 set (for typically SDTV analog-like displays) + 0x0 + + + B_0x1 + use ITU-R BT.709 set (for typically HDTV digital-like displays) + 0x1 + + + + + OCYCO + output conversion to YCbCr 422 +This bit defines the chrominance order (whether Cb or Cr is output first). + 27 + 1 + read-write + + + B_0x0 + Cb is output first (Y0Cb, then Y1Cr, Y2Cb and so on). + 0x0 + + + B_0x1 + Cr is output first (Y0Cr, then Y1Cb, Y2Cr and so on). + 0x1 + + + + + + + LTDC_IER2 + LTDC_IER2 + LTDC interrupt enable register 2 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIE + Line interrupt enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + line interrupt disabled + 0x0 + + + B_0x1 + line interrupt enabled + 0x1 + + + + + FUWIE + FIFO underrun warning interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + FIFO underrun interrupt disabled + 0x0 + + + B_0x1 + FIFO underrun Interrupt enabled + 0x1 + + + + + TERRIE + Transfer error interrupt enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + transfer error interrupt disabled + 0x0 + + + B_0x1 + transfer error interrupt enabled + 0x1 + + + + + RRIE + Register reload interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + register reload interrupt disabled + 0x0 + + + B_0x1 + register reload interrupt enabled + 0x1 + + + + + FUIE + FIFO underrun interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + FIFO underrun interrupt disabled + 0x0 + + + B_0x1 + FIFO underrun Interrupt enabled + 0x1 + + + + + CRCIE + CRC error interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + CRC error disabled + 0x0 + + + B_0x1 + CRC error interrupt enabled + 0x1 + + + + + + + LTDC_ISR2 + LTDC_ISR2 + LTDC interrupt status register 2 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIF + Line interrupt flag + 0 + 1 + read-only + + + B_0x0 + no line interrupt generated + 0x0 + + + B_0x1 + line interrupt generated when a programmed line is reached + 0x1 + + + + + FUWIF + FIFO underrun warning interrupt flag + 1 + 1 + read-only + + + B_0x0 + no FIFO underrun warning interrupt generated. + 0x0 + + + B_0x1 + FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO + 0x1 + + + + + TERRIF + Transfer error interrupt flag + 2 + 1 + read-only + + + B_0x0 + no transfer error interrupt generated + 0x0 + + + B_0x1 + transfer error interrupt generated when a bus error occurs + 0x1 + + + + + RRIF + Register reload interrupt flag + 3 + 1 + read-only + + + B_0x0 + no register reload interrupt generated + 0x0 + + + B_0x1 + register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + 0x1 + + + + + FUIF + FIFO underrun interrupt flag + 6 + 1 + read-only + + + B_0x0 + no FIFO underrun interrupt generated. + 0x0 + + + B_0x1 + FIFO underrun interrupt generated, if one of the layer FIFO is empty and many pixel data are read from the FIFO + 0x1 + + + + + CRCIF + CRC Error interrupt flag + 7 + 1 + read-only + + + B_0x0 + no CRC error interrupt generated + 0x0 + + + B_0x1 + CRC error interrupt generated when a bus error occurs + 0x1 + + + + + + + LTDC_ICR2 + LTDC_ICR2 + LTDC interrupt clear register 2 + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLIF + clears the Line interrupt flag + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the LIF flag in LTDC_ISR2. + 0x1 + + + + + CFUWIF + clears the FIFO underrun warning interrupt flag + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the FUWIF flag in LTDC_ISR2. + 0x1 + + + + + CTERRIF + clears the Transfer Error interrupt flag + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the TERRIF flag in LTDC_ISR2. + 0x1 + + + + + CRRIF + clears register reload interrupt flag + 3 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the RRIF flag in LTDC_ISR2. + 0x1 + + + + + CFUIF + clears the FIFO underrun interrupt flag + 6 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the FUIF flag in LTDC_ISR2. + 0x1 + + + + + CCRCIF + clears the CRC error interrupt flag + 7 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears the CRCIF flag in LTDC_ISR2. + 0x1 + + + + + + + LTDC_LIPCR2 + LTDC_LIPCR2 + LTDC line interrupt position configuration register 2 + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LIPOS + line interrupt position +This field configures the line interrupt position. + 0 + 16 + read-write + + + + + LTDC_ECRCR + LTDC_ECRCR + LTDC expected CRC register + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ECRC + expected CRC of frame + 0 + 16 + read-write + + + + + LTDC_CCRCR + LTDC_CCRCR + LTDC computed CRC register + 0x7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCRC + computed CRC of frame + 0 + 16 + read-only + + + + + LTDC_FUTR + LTDC_FUTR + LTDC FIFO underrun threshold register + 0x90 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + THRE + threshold to trigger a FIFO underrun interrupt (per FIFO word, 64 bits) +Threshold above which a FIFO underrun warning becomes a FIFO underrun error. + 0 + 16 + read-write + + + + + LTDC_L1C0R + LTDC_L1C0R + LTDC Layerx configuration 0 register + 0x100 + 0x20 + 0xFF50A076 + 0xFFFFFFFF + + + CKTA + color key transparency ability + 0 + 1 + read-only + + + CFBDA + color frame buffer duplication ability + 1 + 1 + read-only + + + CFBPA + color frame buffer pitch ability + 2 + 1 + read-only + + + APA + alpha plane ability + 3 + 1 + read-only + + + DCP + default color programmability + 4 + 1 + read-only + + + WINA + windowing ability + 5 + 1 + read-only + + + CLUTA + CLUT ability + 6 + 1 + read-only + + + CKRA + color key replace ability + 7 + 1 + read-only + + + F21 + blending factor 2, ability for: 1.0 + 8 + 1 + read-only + + + F20 + blending factor 2, ability for: 0.0 + 9 + 1 + read-only + + + F2P + blending factor 2, ability for: pixel_alpha + 10 + 1 + read-only + + + F21P + blending factor 2, ability for: 1.0 - pixel_alpha + 11 + 1 + read-only + + + F2C + blending factor 2, ability for: constant_alpha + 12 + 1 + read-only + + + F21C + blending factor 2, ability for: 1.0 - constant_alpha + 13 + 1 + read-only + + + F2PC + blending factor 2, ability for: pixel_alpha * constant_alpha + 14 + 1 + read-only + + + F21PC + blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) + 15 + 1 + read-only + + + F11 + blending factor 1, ability for: 1.0 + 16 + 1 + read-only + + + F10 + blending factor 1,ability for: 0.0 + 17 + 1 + read-only + + + F1P + blending factor 1, ability for: pixel_alpha + 18 + 1 + read-only + + + F11P + blending factor 1, ability for: 1.0 - pixel_alpha + 19 + 1 + read-only + + + F1C + blending factor 1, ability for: constant_alpha + 20 + 1 + read-only + + + F11C + blending factor 1, ability for: 1.0 - constant_alpha + 21 + 1 + read-only + + + F1PC + blending factor 1, ability for: pixel_alpha * constant_alpha + 22 + 1 + read-only + + + F11PC + blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) + 23 + 1 + read-only + + + FF + flexible pixel format, ability + 24 + 1 + read-only + + + RGB888 + pixel format, ability for rgb888 + 25 + 1 + read-only + + + BGR565 + pixel format, ability for bgr565 + 26 + 1 + read-only + + + RGB565 + pixel format, ability for rgb565 + 27 + 1 + read-only + + + BGRA888 + pixel format, ability for bgra8888 + 28 + 1 + read-only + + + RGBA8888 + pixel format, ability for rgba8888 + 29 + 1 + read-only + + + ABGR8888 + pixel format, ability for abgr8888 + 30 + 1 + read-only + + + ARGB8888 + pixel format, ability for argb8888 + 31 + 1 + read-only + + + + + LTDC_L1C1R + LTDC_L1C1R + LTDC Layerx configuration 1 register + 0x104 + 0x20 + 0x80000007 + 0xFFFFFFFF + + + YIA + YCbCr 422 interleaved ability for that layer + 0 + 1 + write-only + + + B_0x0 + interleaved not available + 0x0 + + + B_0x1 + interleaved available + 0x1 + + + + + YSPA + YCbCr 420 semi-planar ability for that layer + 1 + 1 + read-write + + + B_0x0 + semi-planar not available + 0x0 + + + B_0x1 + semi-planar available + 0x1 + + + + + YFPA + YCbCr 420 full-planar ability for that layer + 2 + 1 + read-write + + + B_0x0 + full planar not available + 0x0 + + + B_0x1 + full planar available + 0x1 + + + + + SCA + scaling ability for that layer + 31 + 1 + read-write + + + B_0x0 + scaling not available + 0x0 + + + B_0x1 + scaling available + 0x1 + + + + + + + LTDC_L1RCR + LTDC_L1RCR + LTDC Layerx reload control register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMR + immediate reload trigger +This bit is set by software and cleared only by hardware after reload. + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded immediately. + 0x1 + + + + + VBR + vertical blanking reload request +This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 0x1 + + + + + GRMSK + shadow reload control, global (centralized) reload masked +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + global reload active for this layer (control from LTDC_SRCR enabled) + 0x0 + + + B_0x1 + global reload masked for this layer (control from LTDC_SRCR disabled) + 0x1 + + + + + + + LTDC_L1CR + LTDC_L1CR + LTDC Layerx control register + 0x10c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LEN + layer enable: the bit is used to enable/disable the presence of this whole layer. +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + layer disabled + 0x0 + + + B_0x1 + layer enabled + 0x1 + + + + + CKEN + color keying enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + color keying disabled + 0x0 + + + B_0x1 + color keying enabled: if RGB matches, then the ARGB are set to 0. + 0x1 + + + + + CLUTEN + color look-up table enable +This bit is set and cleared by software. +The CLUT is only meaningful for L8, AL44 and AL88 pixel format. + 4 + 1 + read-write + + + B_0x0 + color look-up table disabled + 0x0 + + + B_0x1 + color look-up table enabled + 0x1 + + + + + HMEN + horizontal mirroring enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + mirror disabled + 0x0 + + + B_0x1 + mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299) + 0x1 + + + + + DCBEN + default color blending enable +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + blending disabled + 0x0 + + + B_0x1 + blending enabled + 0x1 + + + + + + + LTDC_L1WHPCR + LTDC_L1WHPCR + LTDC Layerx window horizontal position configuration register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WHSTPOS + window horizontal start position +This field configures the first visible pixel of a line of the layer window. +WHSTPOS[15:0] must be ≤ AAW[15:0] bits (programmed in LTDC_AWCR). + 0 + 16 + read-write + + + WHSPPOS + window horizontal stop position +This field configures the last visible pixel of a line of the layer window. +WHSPPOS[15:0] must be ≥ AHBP[15:0] bits + 1 (programmed in LTDC_BPCR). + 16 + 16 + read-write + + + + + LTDC_L1WVPCR + LTDC_L1WVPCR + LTDC Layerx window vertical position configuration register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WVSTPOS + window vertical start position +This field configures the first visible line of the layer window. +WVSTPOS[15:0] must be ≤ AAH[15:0] bits (programmed in LTDC_AWCR). + 0 + 16 + read-write + + + WVSPPOS + window vertical stop position +This field configures the last visible line of the layer window. +WVSPPOS[11:0] must be ≥ AVBP[15:0] bits + 1 (programmed in LTDC_BPCR). + 16 + 16 + read-write + + + + + LTDC_L1CKCR + LTDC_L1CKCR + LTDC Layerx color keying configuration register + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKBLUE + color key blue value + 0 + 8 + read-write + + + CKGREEN + color key green value + 8 + 8 + read-write + + + CKRED + color key red value + 16 + 8 + read-write + + + + + LTDC_L1PFCR + LTDC_L1PFCR + LTDC Layerx pixel format configuration register + 0x11c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PF + pixel format +This field configures the pixel format. + 0 + 3 + read-write + + + B_0x0 + ARGB8888 (32 bpp) + 0x0 + + + B_0x1 + ABGR888 (32 bpp) + 0x1 + + + B_0x2 + RGBA888 (32 bpp) + 0x2 + + + B_0x3 + BGRA8888 (32 bpp) + 0x3 + + + B_0x4 + RGB565 (16 bpp, A = 255) + 0x4 + + + B_0x5 + BGR565 (16 bpp, A = 255) + 0x5 + + + B_0x6 + RGB888 (24 bpp packed, A = 255) + 0x6 + + + B_0x7 + Flexible pixel format selected (see Section 54.7.50 and Section 54.7.51) + 0x7 + + + + + + + LTDC_L1CACR + LTDC_L1CACR + LTDC Layerx constant alpha configuration register + 0x120 + 0x20 + 0x000000FF + 0xFFFFFFFF + + + CONSTA + constant alpha +This field configures the constant alpha used for blending. The constant alpha is divided by 255 by hardware. +Example: if the programmed constant alpha is 0xFF, the floating alpha value is 255 / 255 = 1. + 0 + 8 + read-write + + + + + LTDC_L1DCCR + LTDC_L1DCCR + LTDC Layerx default color configuration register + 0x124 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCBLUE + default color blue +This field configures the default blue value. + 0 + 8 + read-write + + + DCGREEN + default color green +This field configures the default green value. + 8 + 8 + read-write + + + DCRED + default color red +This field configures the default red value. + 16 + 8 + read-write + + + DCALPHA + default color alpha +This field configures the default alpha value. + 24 + 8 + read-write + + + + + LTDC_L1BFCR + LTDC_L1BFCR + LTDC Layerx blending factors configuration register + 0x128 + 0x20 + 0x00000607 + 0xFFFFFFFF + + + BF2 + blending factor 2 +This field selects the blending factor F2 +others: reserved + 0 + 3 + read-write + + + B_0x5 + 1 - constant alpha + 0x5 + + + B_0x7 + 1 - (pixel alpha x constant alpha) + 0x7 + + + + + BF1 + blending factor 1 +This field selects the blending factor F1. +others: reserved + 8 + 3 + read-write + + + B_0x4 + constant alpha + 0x4 + + + B_0x6 + pixel alpha x constant alpha + 0x6 + + + + + BOR + blending order +This bit defines the blending order of the layer. If two layers have the same BOR value, the layer with the highest index is on the foreground. + 16 + 1 + read-write + + + B_0x0 + layer set in background + 0x0 + + + B_0x1 + layer set in foreground + 0x1 + + + + + + + LTDC_L1BLCR + LTDC_L1BLCR + LTDC Layerx burst length configuration register + 0x12c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BL + burst length +others: reserved + 0 + 8 + read-write + + + B_0x0 + maximum burst length (16 words 64 bits, thus 128 Bytes) + 0x0 + + + B_0x1 + 1 word (of 64 bits) per burst + 0x1 + + + B_0x10 + 16 words (of 64 bits) per burst + 0x10 + + + + + + + LTDC_L1PCR + LTDC_L1PCR + LTDC Layerx planar configuration register + 0x130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + YCEN + YCbCr-to-RGB conversion enable + 3 + 1 + read-write + + + B_0x0 + conversion disabled + 0x0 + + + B_0x1 + YCbCr conversion enabled, using the YCM setting above + 0x1 + + + + + YCM + YCbCr conversion mode +Defines the type of input that is considered and converted to a YCbCr 444. + 4 + 2 + read-write + + + B_0x0 + interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1) + 0x0 + + + B_0x1 + semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). + 0x1 + + + B_0x2 + full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). + 0x2 + + + + + YF + Y component first +Defines if the byte 0 of a word (in LSB) contains the Y component. + 6 + 1 + read-write + + + B_0x0 + Y component disabled (thus Cr or Cb component is on byte 0) + 0x0 + + + B_0x1 + Y component enabled (thus Y component is on byte 0) + 0x1 + + + + + CBF + Cb component first +Defines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode. + 7 + 1 + read-write + + + B_0x0 + Cb disabled (thus Cr component is on byte 0 and 1) + 0x0 + + + B_0x1 + Cb enabled (thus Cb component is on byte 0 and 1) + 0x1 + + + + + OF + Odd pixel first +Defines if the byte 0 of a word (in LSB) contains the odd pixel. + 8 + 1 + read-write + + + B_0x0 + odd pixel disabled (thus even pixel on byte 0) + 0x0 + + + B_0x1 + odd pixel enabled (thus odd pixel on byte 0) + 0x1 + + + + + YREN + Y rescale enable for the color dynamic range +When enabled, incoming Y values in range 16 to 235, are re-scaled to range 0 to 255. + 9 + 1 + read-write + + + B_0x0 + rescaling disabled (input component thus assumed provided in 0 to 255) + 0x0 + + + B_0x1 + rescaling enabled (input component thus assumed provided in 16 to 235). + 0x1 + + + + + + + LTDC_L1CFBAR + LTDC_L1CFBAR + LTDC Layerx color frame buffer address register + 0x134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBADD + color frame buffer start address +This field defines the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L1CFBLR + LTDC_L1CFBLR + LTDC Layerx color frame buffer length register + 0x138 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLL + color frame buffer line length +This field defines the length of one line of pixels in bytes + 7. +The line length is computed as follows: active high width * number of bytes per pixel + 7. + 0 + 16 + read-write + + + CFBP + color frame buffer pitch in bytes +This field defines the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. +Negative values (with MSB bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. + 16 + 16 + read-write + + + + + LTDC_L1CFBLNR + LTDC_L1CFBLNR + LTDC Layerx color frame buffer line number register + 0x13c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLNBR + frame buffer line number +This field defines the number of lines in the frame buffer that corresponds to the active high width. + 0 + 16 + read-write + + + + + LTDC_L1AFBA0R + LTDC_L1AFBA0R + LTDC Layer1 auxiliary frame buffer address 0 register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFBADD0 + frame buffer start address +This field defines the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L1AFBA1R + LTDC_L1AFBA1R + LTDC Layer1 auxiliary frame buffer address 1 register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFBADD1 + auxiliary frame buffer start address +This field defines the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L1AFBLR + LTDC_L1AFBLR + LTDC Layer1 auxiliary frame buffer length register + 0x148 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFBLL + auxiliary frame buffer line length +This field defines the length of one line of pixels in bytes + 7. +The line length is computed as follows: +active high width * number of bytes per pixel + 7. + 0 + 16 + read-write + + + AFBP + auxiliary frame buffer pitch in bytes +This field defines the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. +Negative values (with MSB bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. + 16 + 16 + read-write + + + + + LTDC_L1AFBLNR + LTDC_L1AFBLNR + LTDC Layer1 auxiliary frame buffer line number register + 0x14c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFBLNBR + auxiliary frame buffer line number +This field defines the number of lines in the auxiliary frame buffer that corresponds to the active high width. + 0 + 16 + read-write + + + + + LTDC_L1CLUTWR + LTDC_L1CLUTWR + LTDC Layerx CLUT write register + 0x150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BLUE + blue value +This field configures the blue value. + 0 + 8 + write-only + + + GREEN + green value +This field configures the green value. + 8 + 8 + write-only + + + RED + red value +This field configures the red value. + 16 + 8 + write-only + + + CLUTADD + CLUT address +This field configures the CLUT address (color position within the CLUT) of each RGB value. + 24 + 8 + write-only + + + + + LTDC_L1CYR0R + LTDC_L1CYR0R + LTDC Layerx conversion YCbCr RGB 0 register + 0x16c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR2R + Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 0 + 10 + read-write + + + CB2B + Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 16 + 10 + read-write + + + + + LTDC_L1CYR1R + LTDC_L1CYR1R + LTDC Layerx conversion YCbCr RGB 1 register + 0x170 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR2G + Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 0 + 10 + read-write + + + CB2G + Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 16 + 10 + read-write + + + + + LTDC_L1FPF0R + LTDC_L1FPF0R + LTDC Layerx flexible pixel format 0 register + 0x174 + 0x20 + 0x00011100 + 0xFFFFFFFF + + + APOS + Location of the Alpha component inside the pixel memory word (in bits) + 0 + 5 + read-write + + + ALEN + Width of the Alpha component (in bits) + 5 + 4 + read-write + + + RPOS + Location of the Red component inside the pixel memory word (in bits) + 9 + 5 + read-write + + + RLEN + Width of the Red component (in bits) + 14 + 4 + read-write + + + + + LTDC_L1FPF1R + LTDC_L1FPF1R + LTDC Layerx flexible pixel format 1 register + 0x178 + 0x20 + 0x00093110 + 0xFFFFFFFF + + + GPOS + Location of the Green Component inside the Pixel Memory Word (in bits). + 0 + 5 + read-write + + + GLEN + Width of the Green Component (in bits). + 5 + 4 + read-write + + + BPOS + Location of the Blue Component inside the Pixel Memory Word (in bits). + 9 + 5 + read-write + + + BLEN + Width of the Blue Component (in bits). + 14 + 4 + read-write + + + PSIZE + Pixel Size (in Bytes). + 18 + 3 + read-write + + + + + LTDC_L2C0R + LTDC_L2C0R + LTDC Layerx configuration 0 register + 0x200 + 0x20 + 0xFF50A076 + 0xFFFFFFFF + + + CKTA + color key transparency ability + 0 + 1 + read-only + + + CFBDA + color frame buffer duplication ability + 1 + 1 + read-only + + + CFBPA + color frame buffer pitch ability + 2 + 1 + read-only + + + APA + alpha plane ability + 3 + 1 + read-only + + + DCP + default color programmability + 4 + 1 + read-only + + + WINA + windowing ability + 5 + 1 + read-only + + + CLUTA + CLUT ability + 6 + 1 + read-only + + + CKRA + color key replace ability + 7 + 1 + read-only + + + F21 + blending factor 2, ability for: 1.0 + 8 + 1 + read-only + + + F20 + blending factor 2, ability for: 0.0 + 9 + 1 + read-only + + + F2P + blending factor 2, ability for: pixel_alpha + 10 + 1 + read-only + + + F21P + blending factor 2, ability for: 1.0 - pixel_alpha + 11 + 1 + read-only + + + F2C + blending factor 2, ability for: constant_alpha + 12 + 1 + read-only + + + F21C + blending factor 2, ability for: 1.0 - constant_alpha + 13 + 1 + read-only + + + F2PC + blending factor 2, ability for: pixel_alpha * constant_alpha + 14 + 1 + read-only + + + F21PC + blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) + 15 + 1 + read-only + + + F11 + blending factor 1, ability for: 1.0 + 16 + 1 + read-only + + + F10 + blending factor 1,ability for: 0.0 + 17 + 1 + read-only + + + F1P + blending factor 1, ability for: pixel_alpha + 18 + 1 + read-only + + + F11P + blending factor 1, ability for: 1.0 - pixel_alpha + 19 + 1 + read-only + + + F1C + blending factor 1, ability for: constant_alpha + 20 + 1 + read-only + + + F11C + blending factor 1, ability for: 1.0 - constant_alpha + 21 + 1 + read-only + + + F1PC + blending factor 1, ability for: pixel_alpha * constant_alpha + 22 + 1 + read-only + + + F11PC + blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) + 23 + 1 + read-only + + + FF + flexible pixel format, ability + 24 + 1 + read-only + + + RGB888 + pixel format, ability for rgb888 + 25 + 1 + read-only + + + BGR565 + pixel format, ability for bgr565 + 26 + 1 + read-only + + + RGB565 + pixel format, ability for rgb565 + 27 + 1 + read-only + + + BGRA888 + pixel format, ability for bgra8888 + 28 + 1 + read-only + + + RGBA8888 + pixel format, ability for rgba8888 + 29 + 1 + read-only + + + ABGR8888 + pixel format, ability for abgr8888 + 30 + 1 + read-only + + + ARGB8888 + pixel format, ability for argb8888 + 31 + 1 + read-only + + + + + LTDC_L2C1R + LTDC_L2C1R + LTDC Layerx configuration 1 register + 0x204 + 0x20 + 0x80000007 + 0xFFFFFFFF + + + YIA + YCbCr 422 interleaved ability for that layer + 0 + 1 + write-only + + + B_0x0 + interleaved not available + 0x0 + + + B_0x1 + interleaved available + 0x1 + + + + + YSPA + YCbCr 420 semi-planar ability for that layer + 1 + 1 + read-write + + + B_0x0 + semi-planar not available + 0x0 + + + B_0x1 + semi-planar available + 0x1 + + + + + YFPA + YCbCr 420 full-planar ability for that layer + 2 + 1 + read-write + + + B_0x0 + full planar not available + 0x0 + + + B_0x1 + full planar available + 0x1 + + + + + SCA + scaling ability for that layer + 31 + 1 + read-write + + + B_0x0 + scaling not available + 0x0 + + + B_0x1 + scaling available + 0x1 + + + + + + + LTDC_L2RCR + LTDC_L2RCR + LTDC Layerx reload control register + 0x208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IMR + immediate reload trigger +This bit is set by software and cleared only by hardware after reload. + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded immediately. + 0x1 + + + + + VBR + vertical blanking reload request +This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 0x1 + + + + + GRMSK + shadow reload control, global (centralized) reload masked +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + global reload active for this layer (control from LTDC_SRCR enabled) + 0x0 + + + B_0x1 + global reload masked for this layer (control from LTDC_SRCR disabled) + 0x1 + + + + + + + LTDC_L2CR + LTDC_L2CR + LTDC Layerx control register + 0x20c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LEN + layer enable: the bit is used to enable/disable the presence of this whole layer. +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + layer disabled + 0x0 + + + B_0x1 + layer enabled + 0x1 + + + + + CKEN + color keying enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + color keying disabled + 0x0 + + + B_0x1 + color keying enabled: if RGB matches, then the ARGB are set to 0. + 0x1 + + + + + CLUTEN + color look-up table enable +This bit is set and cleared by software. +The CLUT is only meaningful for L8, AL44 and AL88 pixel format. + 4 + 1 + read-write + + + B_0x0 + color look-up table disabled + 0x0 + + + B_0x1 + color look-up table enabled + 0x1 + + + + + HMEN + horizontal mirroring enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + mirror disabled + 0x0 + + + B_0x1 + mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instance: if line is 100 pixels, 24 bpp, then address is set to 299) + 0x1 + + + + + DCBEN + default color blending enable +This bit is set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + blending disabled + 0x0 + + + B_0x1 + blending enabled + 0x1 + + + + + + + LTDC_L2WHPCR + LTDC_L2WHPCR + LTDC Layerx window horizontal position configuration register + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WHSTPOS + window horizontal start position +This field configures the first visible pixel of a line of the layer window. +WHSTPOS[15:0] must be ≤ AAW[15:0] bits (programmed in LTDC_AWCR). + 0 + 16 + read-write + + + WHSPPOS + window horizontal stop position +This field configures the last visible pixel of a line of the layer window. +WHSPPOS[15:0] must be ≥ AHBP[15:0] bits + 1 (programmed in LTDC_BPCR). + 16 + 16 + read-write + + + + + LTDC_L2WVPCR + LTDC_L2WVPCR + LTDC Layerx window vertical position configuration register + 0x214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WVSTPOS + window vertical start position +This field configures the first visible line of the layer window. +WVSTPOS[15:0] must be ≤ AAH[15:0] bits (programmed in LTDC_AWCR). + 0 + 16 + read-write + + + WVSPPOS + window vertical stop position +This field configures the last visible line of the layer window. +WVSPPOS[11:0] must be ≥ AVBP[15:0] bits + 1 (programmed in LTDC_BPCR). + 16 + 16 + read-write + + + + + LTDC_L2CKCR + LTDC_L2CKCR + LTDC Layerx color keying configuration register + 0x218 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKBLUE + color key blue value + 0 + 8 + read-write + + + CKGREEN + color key green value + 8 + 8 + read-write + + + CKRED + color key red value + 16 + 8 + read-write + + + + + LTDC_L2PFCR + LTDC_L2PFCR + LTDC Layerx pixel format configuration register + 0x21c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PF + pixel format +This field configures the pixel format. + 0 + 3 + read-write + + + B_0x0 + ARGB8888 (32 bpp) + 0x0 + + + B_0x1 + ABGR888 (32 bpp) + 0x1 + + + B_0x2 + RGBA888 (32 bpp) + 0x2 + + + B_0x3 + BGRA8888 (32 bpp) + 0x3 + + + B_0x4 + RGB565 (16 bpp, A = 255) + 0x4 + + + B_0x5 + BGR565 (16 bpp, A = 255) + 0x5 + + + B_0x6 + RGB888 (24 bpp packed, A = 255) + 0x6 + + + B_0x7 + Flexible pixel format selected (see Section 54.7.50 and Section 54.7.51) + 0x7 + + + + + + + LTDC_L2CACR + LTDC_L2CACR + LTDC Layerx constant alpha configuration register + 0x220 + 0x20 + 0x000000FF + 0xFFFFFFFF + + + CONSTA + constant alpha +This field configures the constant alpha used for blending. The constant alpha is divided by 255 by hardware. +Example: if the programmed constant alpha is 0xFF, the floating alpha value is 255 / 255 = 1. + 0 + 8 + read-write + + + + + LTDC_L2DCCR + LTDC_L2DCCR + LTDC Layerx default color configuration register + 0x224 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DCBLUE + default color blue +This field configures the default blue value. + 0 + 8 + read-write + + + DCGREEN + default color green +This field configures the default green value. + 8 + 8 + read-write + + + DCRED + default color red +This field configures the default red value. + 16 + 8 + read-write + + + DCALPHA + default color alpha +This field configures the default alpha value. + 24 + 8 + read-write + + + + + LTDC_L2BFCR + LTDC_L2BFCR + LTDC Layerx blending factors configuration register + 0x228 + 0x20 + 0x00000607 + 0xFFFFFFFF + + + BF2 + blending factor 2 +This field selects the blending factor F2 +others: reserved + 0 + 3 + read-write + + + B_0x5 + 1 - constant alpha + 0x5 + + + B_0x7 + 1 - (pixel alpha x constant alpha) + 0x7 + + + + + BF1 + blending factor 1 +This field selects the blending factor F1. +others: reserved + 8 + 3 + read-write + + + B_0x4 + constant alpha + 0x4 + + + B_0x6 + pixel alpha x constant alpha + 0x6 + + + + + BOR + blending order +This bit defines the blending order of the layer. If two layers have the same BOR value, the layer with the highest index is on the foreground. + 16 + 1 + read-write + + + B_0x0 + layer set in background + 0x0 + + + B_0x1 + layer set in foreground + 0x1 + + + + + + + LTDC_L2BLCR + LTDC_L2BLCR + LTDC Layerx burst length configuration register + 0x22c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BL + burst length +others: reserved + 0 + 8 + read-write + + + B_0x0 + maximum burst length (16 words 64 bits, thus 128 Bytes) + 0x0 + + + B_0x1 + 1 word (of 64 bits) per burst + 0x1 + + + B_0x10 + 16 words (of 64 bits) per burst + 0x10 + + + + + + + LTDC_L2PCR + LTDC_L2PCR + LTDC Layerx planar configuration register + 0x230 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + YCEN + YCbCr-to-RGB conversion enable + 3 + 1 + read-write + + + B_0x0 + conversion disabled + 0x0 + + + B_0x1 + YCbCr conversion enabled, using the YCM setting above + 0x1 + + + + + YCM + YCbCr conversion mode +Defines the type of input that is considered and converted to a YCbCr 444. + 4 + 2 + read-write + + + B_0x0 + interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1) + 0x0 + + + B_0x1 + semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). + 0x1 + + + B_0x2 + full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). + 0x2 + + + + + YF + Y component first +Defines if the byte 0 of a word (in LSB) contains the Y component. + 6 + 1 + read-write + + + B_0x0 + Y component disabled (thus Cr or Cb component is on byte 0) + 0x0 + + + B_0x1 + Y component enabled (thus Y component is on byte 0) + 0x1 + + + + + CBF + Cb component first +Defines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode. + 7 + 1 + read-write + + + B_0x0 + Cb disabled (thus Cr component is on byte 0 and 1) + 0x0 + + + B_0x1 + Cb enabled (thus Cb component is on byte 0 and 1) + 0x1 + + + + + OF + Odd pixel first +Defines if the byte 0 of a word (in LSB) contains the odd pixel. + 8 + 1 + read-write + + + B_0x0 + odd pixel disabled (thus even pixel on byte 0) + 0x0 + + + B_0x1 + odd pixel enabled (thus odd pixel on byte 0) + 0x1 + + + + + YREN + Y rescale enable for the color dynamic range +When enabled, incoming Y values in range 16 to 235, are re-scaled to range 0 to 255. + 9 + 1 + read-write + + + B_0x0 + rescaling disabled (input component thus assumed provided in 0 to 255) + 0x0 + + + B_0x1 + rescaling enabled (input component thus assumed provided in 16 to 235). + 0x1 + + + + + + + LTDC_L2CFBAR + LTDC_L2CFBAR + LTDC Layerx color frame buffer address register + 0x234 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBADD + color frame buffer start address +This field defines the color frame buffer start address. + 0 + 32 + read-write + + + + + LTDC_L2CFBLR + LTDC_L2CFBLR + LTDC Layerx color frame buffer length register + 0x238 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLL + color frame buffer line length +This field defines the length of one line of pixels in bytes + 7. +The line length is computed as follows: active high width * number of bytes per pixel + 7. + 0 + 16 + read-write + + + CFBP + color frame buffer pitch in bytes +This field defines the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. +Negative values (with MSB bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. + 16 + 16 + read-write + + + + + LTDC_L2CFBLNR + LTDC_L2CFBLNR + LTDC Layerx color frame buffer line number register + 0x23c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CFBLNBR + frame buffer line number +This field defines the number of lines in the frame buffer that corresponds to the active high width. + 0 + 16 + read-write + + + + + LTDC_L2CLUTWR + LTDC_L2CLUTWR + LTDC Layerx CLUT write register + 0x250 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BLUE + blue value +This field configures the blue value. + 0 + 8 + write-only + + + GREEN + green value +This field configures the green value. + 8 + 8 + write-only + + + RED + red value +This field configures the red value. + 16 + 8 + write-only + + + CLUTADD + CLUT address +This field configures the CLUT address (color position within the CLUT) of each RGB value. + 24 + 8 + write-only + + + + + LTDC_L2CYR0R + LTDC_L2CYR0R + LTDC Layerx conversion YCbCr RGB 0 register + 0x26c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR2R + Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 0 + 10 + read-write + + + CB2B + Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 16 + 10 + read-write + + + + + LTDC_L2CYR1R + LTDC_L2CYR1R + LTDC Layerx conversion YCbCr RGB 1 register + 0x270 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CR2G + Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 0 + 10 + read-write + + + CB2G + Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. + 16 + 10 + read-write + + + + + LTDC_L2FPF0R + LTDC_L2FPF0R + LTDC Layerx flexible pixel format 0 register + 0x274 + 0x20 + 0x00011100 + 0xFFFFFFFF + + + APOS + Location of the Alpha component inside the pixel memory word (in bits) + 0 + 5 + read-write + + + ALEN + Width of the Alpha component (in bits) + 5 + 4 + read-write + + + RPOS + Location of the Red component inside the pixel memory word (in bits) + 9 + 5 + read-write + + + RLEN + Width of the Red component (in bits) + 14 + 4 + read-write + + + + + LTDC_L2FPF1R + LTDC_L2FPF1R + LTDC Layerx flexible pixel format 1 register + 0x278 + 0x20 + 0x00093110 + 0xFFFFFFFF + + + GPOS + Location of the Green Component inside the Pixel Memory Word (in bits). + 0 + 5 + read-write + + + GLEN + Width of the Green Component (in bits). + 5 + 4 + read-write + + + BPOS + Location of the Blue Component inside the Pixel Memory Word (in bits). + 9 + 5 + read-write + + + BLEN + Width of the Blue Component (in bits). + 14 + 4 + read-write + + + PSIZE + Pixel Size (in Bytes). + 18 + 3 + read-write + + + + + LTDC_L3FPF1R + LTDC_L3FPF1R + LTDC Layerx flexible pixel format 1 register + 0x378 + 0x20 + 0x00093110 + 0xFFFFFFFF + + + GPOS + Location of the Green Component inside the Pixel Memory Word (in bits). + 0 + 5 + read-write + + + GLEN + Width of the Green Component (in bits). + 5 + 4 + read-write + + + BPOS + Location of the Blue Component inside the Pixel Memory Word (in bits). + 9 + 5 + read-write + + + BLEN + Width of the Blue Component (in bits). + 14 + 4 + read-write + + + PSIZE + Pixel Size (in Bytes). + 18 + 3 + read-write + + + + + + + MCE + MCE + MCE + 0x58001000 + + 0x0 + 0x0400 + registers + + + MCE + MCE interrupt + 139 + + + + MCE_CR + MCE_CR + MCE configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GLOCK + Global lock +Lock the configuration of most MCE registers until next reset. This bit is cleared by default and once set it cannot be reset until MCE reset. + 0 + 1 + read-write + + + B_0x0 + MCE registers are writable + 0x0 + + + B_0x1 + All writes to MCE registers are ignored, with the exception of MCE_IACR and MCE_IAIER registers. + 0x1 + + + + + MKLOCK + Master keys lock +Lock the master key configurations until next reset. This bit is cleared by default and once set it cannot be reset until MCE reset. + 1 + 1 + read-write + + + B_0x0 + Writes to MCE_MKEYRx register is allowed + 0x0 + + + B_0x1 + Writes to MCE_MKEYRx register is ignored until next MCE reset. + 0x1 + + + + + + + MCE_SR + MCE_SR + MCE status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MKVALID + Master key valid + 0 + 1 + read-only + + + B_0x0 + A valid key has not been written in MCE_MKEYRx registers + 0x0 + + + B_0x1 + A valid key has been written in MCE_MKEYRx registers (write R0 -> R1 -> R2 -> R3 or the reverse) + 0x1 + + + + + ENCDIS + encryption disabled +This bit is set by hardware when the encryption feature is not functional. +When ENCDIS is set application must reset MCE peripheral to be able to use the encryption feature again. + 4 + 1 + read-only + + + B_0x0 + When ENC bit and BREN are set in MCE_REGCR all allowed write accesses are encrypted, and all allowed read requests are decrypted. + 0x0 + + + B_0x1 + When ENC bit and BREN are set in MCE_REGCR all write accesses are ignored, and all read requests return zero. All previously written key material are also erased. + 0x1 + + + + + + + MCE_IASR + MCE_IASR + MCE illegal access status register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CAEF + Configuration access error flag +This bit is set when an illegal access to any MCE configuration register is detected. Bit is cleared by setting corresponding bit in MCE_IACR register. No additional details on the error is available. + 0 + 1 + read-only + + + + + MCE_IACR + MCE_IACR + MCE illegal access clear register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CAEF + Configuration access error flag clear +Set this bit to clear CAEF bit in MCE_IASR register. + 0 + 1 + write-only + + + + + MCE_IAIER + MCE_IAIER + MCE illegal access interrupt enable register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CAEIE + Configuration access error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Interrupt generation on configuration access errors is disabled + 0x0 + + + B_0x1 + Interrupt generation when a configuration access error occurs (CAEF=1) + 0x1 + + + + + + + MCE_PRIVCFGR + MCE_PRIVCFGR + MCE privileged configuration register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIV + Privileged configuration + 0 + 1 + read-write + + + B_0x0 + Privileged and unprivileged access are granted to MCE registers + 0x0 + + + B_0x1 + Only privileged access are granted to MCE registers, excluding ID registers (MCE_HWCFGR1/2, MCE_VERR, MCE_IPIDR, MCE_SIDR) + 0x1 + + + + + + + MCE_REGCR + MCE_REGCR + MCE region x configuration register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BREN + Base region enable +BREN cannot be set if BADDRSTART > BADDREND. + 0 + 1 + read-write + + + B_0x0 + Region is disabled. Access control of primary region (any-privilege, no encryption) applies to any access between this region start and end addresses. + 0x0 + + + B_0x1 + Region is enable. Access controls and encryption option defined in this region apply to any access between this region start and end addresses. + 0x1 + + + + + ENC + Encrypted region +This bit is taken into account only if BREN is set. + 15 + 1 + read-write + + + B_0x0 + No effects + 0x0 + + + B_0x1 + All allowed read (resp. write) requests are decrypted (resp. encrypted) using the block cipher. If MKVALID=0 bypass mode is selected instead. + 0x1 + + + + + + + MCE_SADDR + MCE_SADDR + MCE start address register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BADDSTART + Region address start +This bitfield defines the absolute start address of the region on 64 kBytes boundary (inclusive). +BREN cannot be set if BADDRSTART > BADDREND. +When MCE determines the region, the first 16 bits (LSB) and the last 2 bits (MSB) in this register are ignored, and when this register is accessed in read the 2 MSB bits and the 16 LSB bits return zeros (reference value in MCE). + 16 + 16 + read-write + + + + + MCE_EADDR + MCE_EADDR + MCE end address register + 0x48 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + BADDEND + Region address end +This bitfield defines the absolute end address of the region on 64 kBytes boundary (inclusive). +BREN cannot be set if BADDRSTART > BADDREND. +When MCE determines the region, the first 16 bits (LSB) and the last 2 bits (MSB) in this register are ignored, and when this register is accessed in read the 2 MSB bits return zeros and the 16 LSB bits return ones (reference value in MCE). + 16 + 16 + read-write + + + + + MCE_MKEYR0 + MCE_MKEYR0 + MCE master key 0 + 0x200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MKEY + Master key, bits [31:0] +This key is used by the MCE block cipher + 0 + 32 + write-only + + + + + MCE_MKEYR1 + MCE_MKEYR1 + MCE master key 1 + 0x204 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MKEY + Master key, bits [63:32] +This key is used by the MCE block cipher + 0 + 32 + write-only + + + + + MCE_MKEYR2 + MCE_MKEYR2 + MCE master key 2 + 0x208 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MKEY + Master key, bits [95:64] +This key is used by the MCE block cipher + 0 + 32 + write-only + + + + + MCE_MKEYR3 + MCE_MKEYR3 + MCE master key 3 + 0x20c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MKEY + Master key, bits [127:96] +This key is used by the MCE block cipher + 0 + 32 + write-only + + + + + MCE_HWCFGR3 + MCE_HWCFGR3 + MCE version register + 0x3e8 + 0x20 + 0x3B000102 + 0xFFFFFFFF + + + CFG1 + HW Generic 1 +This field returns the generic value aes_core + 0 + 4 + read-only + + + CFG2 + HW Generic 2 +This field returns the generic value nk_core + 4 + 4 + read-only + + + CFG3 + HW Generic 3 +This field returns the generic value priv_enable + 8 + 4 + read-only + + + CFG4 + HW Generic 4 +This field returns the generic value sec_enable + 12 + 4 + read-only + + + CFG5 + HW Generic 5 +This field returns the generic value rif_enable + 16 + 4 + read-only + + + CFG6 + HW Generic 6 +This field returns the generic value priv_enable_axi + 20 + 4 + read-only + + + CFG7 + HW Generic 7 +This field returns the generic value id_size + 24 + 4 + read-only + + + CFG8 + HW Generic 8 +This field returns the generic value ooo_enable | interconnect_enable + 28 + 4 + read-only + + + + + MCE_HWCFGR2 + MCE_HWCFGR2 + MCE version register + 0x3ec + 0x20 + 0x11071444 + 0xFFFFFFFF + + + CFG1 + HW Generic 1 +This field returns the generic value burst_fifo_depth + 0 + 4 + read-only + + + CFG2 + HW Generic 2 +This field returns the generic value info_fifo_depth + 4 + 4 + read-only + + + CFG3 + HW Generic 3 +This field returns the generic value mask_fifo_depth + 8 + 4 + read-only + + + CFG4 + HW Generic 4 +This field returns the generic value ilac_is_int + 12 + 4 + read-only + + + CFG5 + HW Generic 5 +This field returns the generic value nb_dpa_cycles + 16 + 4 + read-only + + + CFG6 + HW Generic 6 +This field returns the generic value nb_cctx + 20 + 4 + read-only + + + CFG7 + HW Generic 7 +This field returns the generic value nb_mkey + 24 + 4 + read-only + + + CFG8 + HW Generic 8 +This field returns the generic value nb_breg + 28 + 4 + read-only + + + + + MCE_HWCFGR1 + MCE_HWCFGR1 + MCE version register + 0x3f0 + 0x20 + 0x00001D10 + 0xFFFFFFFF + + + CFG1 + HW Generic 1 +This field returns the generic value address_region_lsb_max_bits + 0 + 8 + read-only + + + CFG2 + HW Generic 2 +This field returns the generic value address_region_msb_max_bits + 8 + 8 + read-only + + + CFG3 + HW Generic 3 +This field returns the generic value opbits_gen + 16 + 8 + read-only + + + + + MCE_VERR + MCE_VERR + MCE version register + 0x3f4 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MINREV + Minor revision +This field returns the MCE IP Minor Version. + 0 + 4 + read-only + + + MAJREV + Major revision +This field returns the MCE IP Major Version. + 4 + 4 + read-only + + + + + MCE_IPIDR + MCE_IPIDR + MCE identification register + 0x3f8 + 0x20 + 0x00170081 + 0xFFFFFFFF + + + ID + Identification Code +This field returns the identification code of the MCE IP. + 0 + 32 + read-only + + + + + MCE_SIDR + MCE_SIDR + MCE size ID register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size Identification Code +This field returns the size identification code of the MCE IP as defined below: +Bits[31:8] = 0xA3C5DD (fixed code) +Bits[7:0] = 0x01 (1KB address decoding) + 0 + 32 + read-only + + + + + + + MDMA + MDMA + MDMA + 0x58000000 + + 0x0 + 0x1000 + registers + + + MDMA + MDMA global interrupt + 107 + + + + MDMA_GISR0 + MDMA_GISR0 + MDMA global interrupt/status register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + GIF0 + 0 + 1 + + + GIF1 + GIF1 + 1 + 1 + + + GIF2 + GIF2 + 2 + 1 + + + GIF3 + GIF3 + 3 + 1 + + + GIF4 + GIF4 + 4 + 1 + + + GIF5 + GIF5 + 5 + 1 + + + GIF6 + GIF6 + 6 + 1 + + + GIF7 + GIF7 + 7 + 1 + + + GIF8 + GIF8 + 8 + 1 + + + GIF9 + GIF9 + 9 + 1 + + + GIF10 + GIF10 + 10 + 1 + + + GIF11 + GIF11 + 11 + 1 + + + GIF12 + GIF12 + 12 + 1 + + + GIF13 + GIF13 + 13 + 1 + + + GIF14 + GIF14 + 14 + 1 + + + GIF15 + GIF15 + 15 + 1 + + + GIF16 + GIF16 + 16 + 1 + + + GIF17 + GIF17 + 17 + 1 + + + GIF18 + GIF18 + 18 + 1 + + + GIF19 + GIF19 + 19 + 1 + + + GIF20 + GIF20 + 20 + 1 + + + GIF21 + GIF21 + 21 + 1 + + + GIF22 + GIF22 + 22 + 1 + + + GIF23 + GIF23 + 23 + 1 + + + GIF24 + GIF24 + 24 + 1 + + + GIF25 + GIF25 + 25 + 1 + + + GIF26 + GIF26 + 26 + 1 + + + GIF27 + GIF27 + 27 + 1 + + + GIF28 + GIF28 + 28 + 1 + + + GIF29 + GIF29 + 29 + 1 + + + GIF30 + GIF30 + 30 + 1 + + + GIF31 + GIF31 + 31 + 1 + + + + + MDMA_SGISR0 + MDMA_SGISR0 + MDMA secure global interrupt/status register + 0x8 + 0x20 + read-only + 0x00000000 + + + GIF0 + GIF0 + 0 + 1 + + + GIF1 + GIF1 + 1 + 1 + + + GIF2 + GIF2 + 2 + 1 + + + GIF3 + GIF3 + 3 + 1 + + + GIF4 + GIF4 + 4 + 1 + + + GIF5 + GIF5 + 5 + 1 + + + GIF6 + GIF6 + 6 + 1 + + + GIF7 + GIF7 + 7 + 1 + + + GIF8 + GIF8 + 8 + 1 + + + GIF9 + GIF9 + 9 + 1 + + + GIF10 + GIF10 + 10 + 1 + + + GIF11 + GIF11 + 11 + 1 + + + GIF12 + GIF12 + 12 + 1 + + + GIF13 + GIF13 + 13 + 1 + + + GIF14 + GIF14 + 14 + 1 + + + GIF15 + GIF15 + 15 + 1 + + + GIF16 + GIF16 + 16 + 1 + + + GIF17 + GIF17 + 17 + 1 + + + GIF18 + GIF18 + 18 + 1 + + + GIF19 + GIF19 + 19 + 1 + + + GIF20 + GIF20 + 20 + 1 + + + GIF21 + GIF21 + 21 + 1 + + + GIF22 + GIF22 + 22 + 1 + + + GIF23 + GIF23 + 23 + 1 + + + GIF24 + GIF24 + 24 + 1 + + + GIF25 + GIF25 + 25 + 1 + + + GIF26 + GIF26 + 26 + 1 + + + GIF27 + GIF27 + 27 + 1 + + + GIF28 + GIF28 + 28 + 1 + + + GIF29 + GIF29 + 29 + 1 + + + GIF30 + GIF30 + 30 + 1 + + + GIF31 + GIF31 + 31 + 1 + + + + + MDMA_C0ISR + MDMA_C0ISR + MDMA channel 0 interrupt/status register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C0IFCR + MDMA_C0IFCR + MDMA channel 0 interrupt flag clear register + 0x44 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C0ESR + MDMA_C0ESR + MDMA channel 0 error status register + 0x48 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C0CR + MDMA_C0CR + This register is used to control the concerned channel. + 0x4C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C0TCR + MDMA_C0TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x50 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C0BNDTR + MDMA_C0BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x54 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C0SAR + MDMA_C0SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x58 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C0DAR + MDMA_C0DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x5C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C0BRUR + MDMA_C0BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x60 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C0LAR + MDMA_C0LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x64 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C0TBR + MDMA_C0TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x68 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C0MAR + MDMA_C0MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x70 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C0MDR + MDMA_C0MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x74 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C1ISR + MDMA_C1ISR + MDMA channel 1 interrupt/status register + 0x80 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C1IFCR + MDMA_C1IFCR + MDMA channel 1 interrupt flag clear register + 0x84 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C1ESR + MDMA_C1ESR + MDMA channel 1 error status register + 0x88 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C1CR + MDMA_C1CR + This register is used to control the concerned channel. + 0x8C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C1TCR + MDMA_C1TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x90 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C1BNDTR + MDMA_C1BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x94 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C1SAR + MDMA_C1SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x98 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C1DAR + MDMA_C1DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x9C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C1BRUR + MDMA_C1BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0xA0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C1LAR + MDMA_C1LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0xA4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C1TBR + MDMA_C1TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0xA8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C1MAR + MDMA_C1MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0xB0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C1MDR + MDMA_C1MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0xB4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C2ISR + MDMA_C2ISR + MDMA channel 2 interrupt/status register + 0xC0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C2IFCR + MDMA_C2IFCR + MDMA channel 2 interrupt flag clear register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C2ESR + MDMA_C2ESR + MDMA channel 2 error status register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C2CR + MDMA_C2CR + This register is used to control the concerned channel. + 0xCC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C2TCR + MDMA_C2TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0xD0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C2BNDTR + MDMA_C2BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0xD4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C2SAR + MDMA_C2SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0xD8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C2DAR + MDMA_C2DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0xDC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C2BRUR + MDMA_C2BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0xE0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C2LAR + MDMA_C2LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0xE4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C2TBR + MDMA_C2TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0xE8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C2MAR + MDMA_C2MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0xF0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C2MDR + MDMA_C2MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0xF4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C3ISR + MDMA_C3ISR + MDMA channel 3 interrupt/status register + 0x100 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C3IFCR + MDMA_C3IFCR + MDMA channel 3 interrupt flag clear register + 0x104 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C3ESR + MDMA_C3ESR + MDMA channel 3 error status register + 0x108 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C3CR + MDMA_C3CR + This register is used to control the concerned channel. + 0x10C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C3TCR + MDMA_C3TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x110 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C3BNDTR + MDMA_C3BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x114 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C3SAR + MDMA_C3SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x118 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C3DAR + MDMA_C3DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x11C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C3BRUR + MDMA_C3BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x120 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C3LAR + MDMA_C3LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x124 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C3TBR + MDMA_C3TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x128 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C3MAR + MDMA_C3MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x130 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C3MDR + MDMA_C3MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x134 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C4ISR + MDMA_C4ISR + MDMA channel 4 interrupt/status register + 0x140 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C4IFCR + MDMA_C4IFCR + MDMA channel 4 interrupt flag clear register + 0x144 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C4ESR + MDMA_C4ESR + MDMA channel 4 error status register + 0x148 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C4CR + MDMA_C4CR + This register is used to control the concerned channel. + 0x14C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C4TCR + MDMA_C4TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x150 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C4BNDTR + MDMA_C4BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x154 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C4SAR + MDMA_C4SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x158 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C4DAR + MDMA_C4DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x15C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C4BRUR + MDMA_C4BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x160 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C4LAR + MDMA_C4LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x164 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C4TBR + MDMA_C4TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x168 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C4MAR + MDMA_C4MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x170 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C4MDR + MDMA_C4MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x174 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C5ISR + MDMA_C5ISR + MDMA channel 5 interrupt/status register + 0x180 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C5IFCR + MDMA_C5IFCR + MDMA channel 5 interrupt flag clear register + 0x184 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C5ESR + MDMA_C5ESR + MDMA channel 5 error status register + 0x188 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C5CR + MDMA_C5CR + This register is used to control the concerned channel. + 0x18C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C5TCR + MDMA_C5TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x190 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C5BNDTR + MDMA_C5BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x194 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C5SAR + MDMA_C5SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x198 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C5DAR + MDMA_C5DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x19C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C5BRUR + MDMA_C5BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C5LAR + MDMA_C5LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x1A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C5TBR + MDMA_C5TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C5MAR + MDMA_C5MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x1B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C5MDR + MDMA_C5MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x1B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C6ISR + MDMA_C6ISR + MDMA channel 6 interrupt/status register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C6IFCR + MDMA_C6IFCR + MDMA channel 6 interrupt flag clear register + 0x1C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C6ESR + MDMA_C6ESR + MDMA channel 6 error status register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C6CR + MDMA_C6CR + This register is used to control the concerned channel. + 0x1CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C6TCR + MDMA_C6TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x1D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C6BNDTR + MDMA_C6BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x1D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C6SAR + MDMA_C6SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x1D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C6DAR + MDMA_C6DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x1DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C6BRUR + MDMA_C6BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x1E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C6LAR + MDMA_C6LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x1E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C6TBR + MDMA_C6TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C6MAR + MDMA_C6MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x1F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C6MDR + MDMA_C6MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x1F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C7ISR + MDMA_C7ISR + MDMA channel 7 interrupt/status register + 0x200 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C7IFCR + MDMA_C7IFCR + MDMA channel 7 interrupt flag clear register + 0x204 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C7ESR + MDMA_C7ESR + MDMA channel 7 error status register + 0x208 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C7CR + MDMA_C7CR + This register is used to control the concerned channel. + 0x20C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C7TCR + MDMA_C7TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x210 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C7BNDTR + MDMA_C7BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x214 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C7SAR + MDMA_C7SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x218 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C7DAR + MDMA_C7DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x21C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C7BRUR + MDMA_C7BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x220 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C7LAR + MDMA_C7LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x224 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C7TBR + MDMA_C7TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x228 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C7MAR + MDMA_C7MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x230 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C7MDR + MDMA_C7MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x234 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C8ISR + MDMA_C8ISR + MDMA channel 8 interrupt/status register + 0x240 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C8IFCR + MDMA_C8IFCR + MDMA channel 8 interrupt flag clear register + 0x244 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C8ESR + MDMA_C8ESR + MDMA channel 8 error status register + 0x248 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C8CR + MDMA_C8CR + This register is used to control the concerned channel. + 0x24C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C8TCR + MDMA_C8TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x250 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C8BNDTR + MDMA_C8BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x254 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C8SAR + MDMA_C8SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x258 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C8DAR + MDMA_C8DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x25C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C8BRUR + MDMA_C8BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x260 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C8LAR + MDMA_C8LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x264 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C8TBR + MDMA_C8TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x268 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C8MAR + MDMA_C8MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x270 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C8MDR + MDMA_C8MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x274 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C9ISR + MDMA_C9ISR + MDMA channel 9 interrupt/status register + 0x280 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C9IFCR + MDMA_C9IFCR + MDMA channel 9 interrupt flag clear register + 0x284 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C9ESR + MDMA_C9ESR + MDMA channel 9 error status register + 0x288 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C9CR + MDMA_C9CR + This register is used to control the concerned channel. + 0x28C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C9TCR + MDMA_C9TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x290 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C9BNDTR + MDMA_C9BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x294 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C9SAR + MDMA_C9SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x298 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C9DAR + MDMA_C9DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x29C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C9BRUR + MDMA_C9BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x2A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C9LAR + MDMA_C9LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x2A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C9TBR + MDMA_C9TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x2A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C9MAR + MDMA_C9MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x2B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C9MDR + MDMA_C9MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x2B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C10ISR + MDMA_C10ISR + MDMA channel 10 interrupt/status register + 0x2C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C10IFCR + MDMA_C10IFCR + MDMA channel 10 interrupt flag clear register + 0x2C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C10ESR + MDMA_C10ESR + MDMA channel 10 error status register + 0x2C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C10CR + MDMA_C10CR + This register is used to control the concerned channel. + 0x2CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C10TCR + MDMA_C10TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x2D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C10BNDTR + MDMA_C10BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x2D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C10SAR + MDMA_C10SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x2D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C10DAR + MDMA_C10DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x2DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C10BRUR + MDMA_C10BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x2E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C10LAR + MDMA_C10LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x2E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C10TBR + MDMA_C10TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x2E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C10MAR + MDMA_C10MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x2F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C10MDR + MDMA_C10MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x2F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C11ISR + MDMA_C11ISR + MDMA channel 11 interrupt/status register + 0x300 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C11IFCR + MDMA_C11IFCR + MDMA channel 11 interrupt flag clear register + 0x304 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C11ESR + MDMA_C11ESR + MDMA channel 11 error status register + 0x308 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C11CR + MDMA_C11CR + This register is used to control the concerned channel. + 0x30C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C11TCR + MDMA_C11TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x310 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C11BNDTR + MDMA_C11BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x314 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C11SAR + MDMA_C11SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x318 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C11DAR + MDMA_C11DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x31C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C11BRUR + MDMA_C11BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x320 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C11LAR + MDMA_C11LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x324 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C11TBR + MDMA_C11TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x328 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C11MAR + MDMA_C11MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x330 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C11MDR + MDMA_C11MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x334 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C12ISR + MDMA_C12ISR + MDMA channel 12 interrupt/status register + 0x340 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C12IFCR + MDMA_C12IFCR + MDMA channel 12 interrupt flag clear register + 0x344 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C12ESR + MDMA_C12ESR + MDMA channel 12 error status register + 0x348 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C12CR + MDMA_C12CR + This register is used to control the concerned channel. + 0x34C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C12TCR + MDMA_C12TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x350 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C12BNDTR + MDMA_C12BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x354 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C12SAR + MDMA_C12SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x358 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C12DAR + MDMA_C12DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x35C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C12BRUR + MDMA_C12BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x360 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C12LAR + MDMA_C12LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x364 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C12TBR + MDMA_C12TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x368 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C12MAR + MDMA_C12MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x370 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C12MDR + MDMA_C12MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x374 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C13ISR + MDMA_C13ISR + MDMA channel 13 interrupt/status register + 0x380 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C13IFCR + MDMA_C13IFCR + MDMA channel 13 interrupt flag clear register + 0x384 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C13ESR + MDMA_C13ESR + MDMA channel 13 error status register + 0x388 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C13CR + MDMA_C13CR + This register is used to control the concerned channel. + 0x38C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C13TCR + MDMA_C13TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x390 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C13BNDTR + MDMA_C13BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x394 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C13SAR + MDMA_C13SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x398 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C13DAR + MDMA_C13DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x39C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C13BRUR + MDMA_C13BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x3A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C13LAR + MDMA_C13LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x3A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C13TBR + MDMA_C13TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x3A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C13MAR + MDMA_C13MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x3B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C13MDR + MDMA_C13MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x3B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C14ISR + MDMA_C14ISR + MDMA channel 14 interrupt/status register + 0x3C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C14IFCR + MDMA_C14IFCR + MDMA channel 14 interrupt flag clear register + 0x3C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C14ESR + MDMA_C14ESR + MDMA channel 14 error status register + 0x3C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C14CR + MDMA_C14CR + This register is used to control the concerned channel. + 0x3CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C14TCR + MDMA_C14TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x3D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C14BNDTR + MDMA_C14BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x3D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C14SAR + MDMA_C14SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x3D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C14DAR + MDMA_C14DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x3DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C14BRUR + MDMA_C14BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x3E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C14LAR + MDMA_C14LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x3E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C14TBR + MDMA_C14TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x3E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C14MAR + MDMA_C14MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x3F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C14MDR + MDMA_C14MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x3F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C15ISR + MDMA_C15ISR + MDMA channel 15 interrupt/status register + 0x400 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C15IFCR + MDMA_C15IFCR + MDMA channel 15 interrupt flag clear register + 0x404 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C15ESR + MDMA_C15ESR + MDMA channel 15 error status register + 0x408 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C15CR + MDMA_C15CR + This register is used to control the concerned channel. + 0x40C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C15TCR + MDMA_C15TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x410 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C15BNDTR + MDMA_C15BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x414 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C15SAR + MDMA_C15SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x418 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C15DAR + MDMA_C15DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x41C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C15BRUR + MDMA_C15BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x420 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C15LAR + MDMA_C15LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x424 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C15TBR + MDMA_C15TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x428 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C15MAR + MDMA_C15MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x430 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C15MDR + MDMA_C15MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x434 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C16ISR + MDMA_C16ISR + MDMA channel 16 interrupt/status register + 0x440 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C16IFCR + MDMA_C16IFCR + MDMA channel 16 interrupt flag clear register + 0x444 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C16ESR + MDMA_C16ESR + MDMA channel 16 error status register + 0x448 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C16CR + MDMA_C16CR + This register is used to control the concerned channel. + 0x44C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C16TCR + MDMA_C16TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x450 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C16BNDTR + MDMA_C16BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x454 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C16SAR + MDMA_C16SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x458 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C16DAR + MDMA_C16DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x45C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C16BRUR + MDMA_C16BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x460 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C16LAR + MDMA_C16LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x464 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C16TBR + MDMA_C16TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x468 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C16MAR + MDMA_C16MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x470 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C16MDR + MDMA_C16MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x474 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C17ISR + MDMA_C17ISR + MDMA channel 17 interrupt/status register + 0x480 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C17IFCR + MDMA_C17IFCR + MDMA channel 17 interrupt flag clear register + 0x484 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C17ESR + MDMA_C17ESR + MDMA channel 17 error status register + 0x488 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C17CR + MDMA_C17CR + This register is used to control the concerned channel. + 0x48C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C17TCR + MDMA_C17TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x490 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C17BNDTR + MDMA_C17BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x494 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C17SAR + MDMA_C17SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x498 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C17DAR + MDMA_C17DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x49C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C17BRUR + MDMA_C17BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x4A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C17LAR + MDMA_C17LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x4A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C17TBR + MDMA_C17TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x4A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C17MAR + MDMA_C17MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x4B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C17MDR + MDMA_C17MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x4B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C18ISR + MDMA_C18ISR + MDMA channel 18 interrupt/status register + 0x4C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C18IFCR + MDMA_C18IFCR + MDMA channel 18 interrupt flag clear register + 0x4C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C18ESR + MDMA_C18ESR + MDMA channel 18 error status register + 0x4C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C18CR + MDMA_C18CR + This register is used to control the concerned channel. + 0x4CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C18TCR + MDMA_C18TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x4D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C18BNDTR + MDMA_C18BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x4D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C18SAR + MDMA_C18SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x4D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C18DAR + MDMA_C18DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x4DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C18BRUR + MDMA_C18BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x4E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C18LAR + MDMA_C18LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x4E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C18TBR + MDMA_C18TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x4E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C18MAR + MDMA_C18MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x4F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C18MDR + MDMA_C18MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x4F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C19ISR + MDMA_C19ISR + MDMA channel 19 interrupt/status register + 0x500 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C19IFCR + MDMA_C19IFCR + MDMA channel 19 interrupt flag clear register + 0x504 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C19ESR + MDMA_C19ESR + MDMA channel 19 error status register + 0x508 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C19CR + MDMA_C19CR + This register is used to control the concerned channel. + 0x50C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C19TCR + MDMA_C19TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x510 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C19BNDTR + MDMA_C19BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x514 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C19SAR + MDMA_C19SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x518 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C19DAR + MDMA_C19DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x51C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C19BRUR + MDMA_C19BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x520 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C19LAR + MDMA_C19LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x524 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C19TBR + MDMA_C19TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x528 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C19MAR + MDMA_C19MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x530 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C19MDR + MDMA_C19MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x534 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C20ISR + MDMA_C20ISR + MDMA channel 20 interrupt/status register + 0x540 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C20IFCR + MDMA_C20IFCR + MDMA channel 20 interrupt flag clear register + 0x544 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C20ESR + MDMA_C20ESR + MDMA channel 20 error status register + 0x548 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C20CR + MDMA_C20CR + This register is used to control the concerned channel. + 0x54C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C20TCR + MDMA_C20TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x550 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C20BNDTR + MDMA_C20BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x554 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C20SAR + MDMA_C20SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x558 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C20DAR + MDMA_C20DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x55C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C20BRUR + MDMA_C20BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x560 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C20LAR + MDMA_C20LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x564 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C20TBR + MDMA_C20TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x568 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C20MAR + MDMA_C20MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x570 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C20MDR + MDMA_C20MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x574 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C21ISR + MDMA_C21ISR + MDMA channel 21 interrupt/status register + 0x580 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C21IFCR + MDMA_C21IFCR + MDMA channel 21 interrupt flag clear register + 0x584 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C21ESR + MDMA_C21ESR + MDMA channel 21 error status register + 0x588 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C21CR + MDMA_C21CR + This register is used to control the concerned channel. + 0x58C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C21TCR + MDMA_C21TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x590 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C21BNDTR + MDMA_C21BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x594 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C21SAR + MDMA_C21SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x598 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C21DAR + MDMA_C21DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x59C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C21BRUR + MDMA_C21BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x5A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C21LAR + MDMA_C21LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x5A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C21TBR + MDMA_C21TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x5A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C21MAR + MDMA_C21MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x5B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C21MDR + MDMA_C21MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x5B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C22ISR + MDMA_C22ISR + MDMA channel 22 interrupt/status register + 0x5C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C22IFCR + MDMA_C22IFCR + MDMA channel 22 interrupt flag clear register + 0x5C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C22ESR + MDMA_C22ESR + MDMA channel 22 error status register + 0x5C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C22CR + MDMA_C22CR + This register is used to control the concerned channel. + 0x5CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C22TCR + MDMA_C22TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x5D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C22BNDTR + MDMA_C22BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x5D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C22SAR + MDMA_C22SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x5D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C22DAR + MDMA_C22DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x5DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C22BRUR + MDMA_C22BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x5E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C22LAR + MDMA_C22LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x5E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C22TBR + MDMA_C22TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x5E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C22MAR + MDMA_C22MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x5F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C22MDR + MDMA_C22MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x5F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C23ISR + MDMA_C23ISR + MDMA channel 23 interrupt/status register + 0x600 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C23IFCR + MDMA_C23IFCR + MDMA channel 23 interrupt flag clear register + 0x604 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C23ESR + MDMA_C23ESR + MDMA channel 23 error status register + 0x608 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C23CR + MDMA_C23CR + This register is used to control the concerned channel. + 0x60C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C23TCR + MDMA_C23TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x610 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C23BNDTR + MDMA_C23BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x614 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C23SAR + MDMA_C23SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x618 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C23DAR + MDMA_C23DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x61C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C23BRUR + MDMA_C23BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x620 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C23LAR + MDMA_C23LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x624 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C23TBR + MDMA_C23TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x628 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C23MAR + MDMA_C23MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x630 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C23MDR + MDMA_C23MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x634 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C24ISR + MDMA_C24ISR + MDMA channel 24 interrupt/status register + 0x640 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C24IFCR + MDMA_C24IFCR + MDMA channel 24 interrupt flag clear register + 0x644 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C24ESR + MDMA_C24ESR + MDMA channel 24 error status register + 0x648 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C24CR + MDMA_C24CR + This register is used to control the concerned channel. + 0x64C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C24TCR + MDMA_C24TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x650 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C24BNDTR + MDMA_C24BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x654 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C24SAR + MDMA_C24SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x658 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C24DAR + MDMA_C24DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x65C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C24BRUR + MDMA_C24BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x660 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C24LAR + MDMA_C24LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x664 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C24TBR + MDMA_C24TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x668 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C24MAR + MDMA_C24MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x670 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C24MDR + MDMA_C24MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x674 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C25ISR + MDMA_C25ISR + MDMA channel 25 interrupt/status register + 0x680 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C25IFCR + MDMA_C25IFCR + MDMA channel 25 interrupt flag clear register + 0x684 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C25ESR + MDMA_C25ESR + MDMA channel 25 error status register + 0x688 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C25CR + MDMA_C25CR + This register is used to control the concerned channel. + 0x68C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C25TCR + MDMA_C25TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x690 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C25BNDTR + MDMA_C25BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x694 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C25SAR + MDMA_C25SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x698 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C25DAR + MDMA_C25DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x69C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C25BRUR + MDMA_C25BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x6A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C25LAR + MDMA_C25LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x6A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C25TBR + MDMA_C25TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x6A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C25MAR + MDMA_C25MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x6B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C25MDR + MDMA_C25MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x6B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C26ISR + MDMA_C26ISR + MDMA channel 26 interrupt/status register + 0x6C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C26IFCR + MDMA_C26IFCR + MDMA channel 26 interrupt flag clear register + 0x6C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C26ESR + MDMA_C26ESR + MDMA channel 26 error status register + 0x6C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C26CR + MDMA_C26CR + This register is used to control the concerned channel. + 0x6CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C26TCR + MDMA_C26TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x6D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C26BNDTR + MDMA_C26BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x6D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C26SAR + MDMA_C26SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x6D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C26DAR + MDMA_C26DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x6DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C26BRUR + MDMA_C26BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x6E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C26LAR + MDMA_C26LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x6E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C26TBR + MDMA_C26TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x6E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C26MAR + MDMA_C26MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x6F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C26MDR + MDMA_C26MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x6F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C27ISR + MDMA_C27ISR + MDMA channel 27 interrupt/status register + 0x700 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C27IFCR + MDMA_C27IFCR + MDMA channel 27 interrupt flag clear register + 0x704 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C27ESR + MDMA_C27ESR + MDMA channel 27 error status register + 0x708 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C27CR + MDMA_C27CR + This register is used to control the concerned channel. + 0x70C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C27TCR + MDMA_C27TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x710 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C27BNDTR + MDMA_C27BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x714 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C27SAR + MDMA_C27SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x718 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C27DAR + MDMA_C27DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x71C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C27BRUR + MDMA_C27BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x720 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C27LAR + MDMA_C27LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x724 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C27TBR + MDMA_C27TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x728 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C27MAR + MDMA_C27MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x730 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C27MDR + MDMA_C27MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x734 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C28ISR + MDMA_C28ISR + MDMA channel 28 interrupt/status register + 0x740 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C28IFCR + MDMA_C28IFCR + MDMA channel 28 interrupt flag clear register + 0x744 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C28ESR + MDMA_C28ESR + MDMA channel 28 error status register + 0x748 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C28CR + MDMA_C28CR + This register is used to control the concerned channel. + 0x74C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C28TCR + MDMA_C28TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x750 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C28BNDTR + MDMA_C28BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x754 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C28SAR + MDMA_C28SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x758 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C28DAR + MDMA_C28DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x75C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C28BRUR + MDMA_C28BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x760 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C28LAR + MDMA_C28LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x764 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C28TBR + MDMA_C28TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x768 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C28MAR + MDMA_C28MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x770 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C28MDR + MDMA_C28MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x774 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C29ISR + MDMA_C29ISR + MDMA channel 29 interrupt/status register + 0x780 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C29IFCR + MDMA_C29IFCR + MDMA channel 29 interrupt flag clear register + 0x784 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C29ESR + MDMA_C29ESR + MDMA channel 29 error status register + 0x788 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C29CR + MDMA_C29CR + This register is used to control the concerned channel. + 0x78C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C29TCR + MDMA_C29TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x790 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C29BNDTR + MDMA_C29BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x794 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C29SAR + MDMA_C29SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x798 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C29DAR + MDMA_C29DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x79C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C29BRUR + MDMA_C29BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x7A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C29LAR + MDMA_C29LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x7A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C29TBR + MDMA_C29TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x7A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C29MAR + MDMA_C29MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x7B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C29MDR + MDMA_C29MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x7B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C30ISR + MDMA_C30ISR + MDMA channel 30 interrupt/status register + 0x7C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C30IFCR + MDMA_C30IFCR + MDMA channel 30 interrupt flag clear register + 0x7C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C30ESR + MDMA_C30ESR + MDMA channel 30 error status register + 0x7C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C30CR + MDMA_C30CR + This register is used to control the concerned channel. + 0x7CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C30TCR + MDMA_C30TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x7D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C30BNDTR + MDMA_C30BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x7D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C30SAR + MDMA_C30SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x7D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C30DAR + MDMA_C30DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x7DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C30BRUR + MDMA_C30BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x7E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C30LAR + MDMA_C30LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x7E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C30TBR + MDMA_C30TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x7E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C30MAR + MDMA_C30MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x7F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C30MDR + MDMA_C30MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x7F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C31ISR + MDMA_C31ISR + MDMA channel 31 interrupt/status register + 0x800 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C31IFCR + MDMA_C31IFCR + MDMA channel 31 interrupt flag clear register + 0x804 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C31ESR + MDMA_C31ESR + MDMA channel 31 error status register + 0x808 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C31CR + MDMA_C31CR + This register is used to control the concerned channel. + 0x80C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C31TCR + MDMA_C31TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x810 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C31BNDTR + MDMA_C31BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x814 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C31SAR + MDMA_C31SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x818 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C31DAR + MDMA_C31DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x81C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C31BRUR + MDMA_C31BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x820 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C31LAR + MDMA_C31LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x824 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C31TBR + MDMA_C31TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x828 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C31MAR + MDMA_C31MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x830 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C31MDR + MDMA_C31MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x834 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + + + OTG + OTG + OTG + 0x49000000 + + 0x0 + 0x40000 + registers + + + OTG + USB On-The-Go global interrupt + 96 + + + + OTG_GOTGCTL + OTG_GOTGCTL + OTG control and status register + 0x0 + 0x20 + 0x00010000 + 0xFFFFFFFF + + + SRQSCS + Session request success +The core sets this bit when a session request initiation is successful. +Note: Only accessible in device mode. + 0 + 1 + read-only + + + B_0x0 + Session request failure + 0x0 + + + B_0x1 + Session request success + 0x1 + + + + + SRQ + Session request +The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. +Note: Only accessible in device mode. + 1 + 1 + read-write + + + B_0x0 + No session request + 0x0 + + + B_0x1 + Session request + 0x1 + + + + + VBVALOEN + VBUS valid override enable. +This bit is used to enable/disable the software to override the vbusvalid signal using the VBVALOVAL bit. +Note: Only accessible in host mode. + 2 + 1 + read-write + + + B_0x0 + Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + B_0x1 + Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value + 0x1 + + + + + VBVALOVAL + VBUS valid override value. +This bit is used to set override value for vbusvalid signal when VBVALOEN bit is set. +Note: Only accessible in host mode. + 3 + 1 + read-write + + + B_0x0 + vbusvalid value is '0' when VBVALOEN = 1 + 0x0 + + + B_0x1 + vbusvalid value is '1' when VBVALOEN = 1 + 0x1 + + + + + AVALOEN + A-peripheral session valid override enable. +This bit is used to enable/disable the software to override the Avalid signal using the AVALOVAL bit. +Note: Only accessible in host mode. + 4 + 1 + read-write + + + B_0x0 + Override is disabled and Avalid signal from the respective PHY selected is used internally by the core + 0x0 + + + B_0x1 + Internally Avalid received from the PHY is overridden with AVALOVAL bit value + 0x1 + + + + + AVALOVAL + A-peripheral session valid override value. +This bit is used to set override value for Avalid signal when AVALOEN bit is set. +Note: Only accessible in host mode. + 5 + 1 + read-write + + + B_0x0 + Avalid value is '0' when AVALOEN = 1 + 0x0 + + + B_0x1 + Avalid value is '1' when AVALOEN = 1 + 0x1 + + + + + BVALOEN + B-peripheral session valid override enable. +This bit is used to enable/disable the software to override the Bvalid signal using the BVALOVAL bit. +Note: Only accessible in device mode. + 6 + 1 + read-write + + + B_0x0 + Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + B_0x1 + Internally Bvalid received from the PHY is overridden with BVALOVAL bit value + 0x1 + + + + + BVALOVAL + B-peripheral session valid override value. +This bit is used to set override value for Bvalid signal when BVALOEN bit is set. +Note: Only accessible in device mode. + 7 + 1 + read-write + + + B_0x0 + Bvalid value is '0' when BVALOEN = 1 + 0x0 + + + B_0x1 + Bvalid value is '1' when BVALOEN = 1 + 0x1 + + + + + HNGSCS + Host negotiation success +The core sets this bit when host negotiation is successful. The core clears this bit when the HNP request (HNPRQ) bit in this register is set. +Note: Only accessible in device mode. + 8 + 1 + read-only + + + B_0x0 + Host negotiation failure + 0x0 + + + B_0x1 + Host negotiation success + 0x1 + + + + + HNPRQ + HNP request +The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. +Note: Only accessible in device mode. + 9 + 1 + read-write + + + B_0x0 + No HNP request + 0x0 + + + B_0x1 + HNP request + 0x1 + + + + + HSHNPEN + host set HNP enable +The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device. +Note: Only accessible in host mode. + 10 + 1 + read-write + + + B_0x0 + Host Set HNP is not enabled + 0x0 + + + B_0x1 + Host Set HNP is enabled + 0x1 + + + + + DHNPEN + Device HNP enabled +The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host. +Note: Only accessible in device mode. + 11 + 1 + read-write + + + B_0x0 + HNP is not enabled in the application + 0x0 + + + B_0x1 + HNP is enabled in the application + 0x1 + + + + + EHEN + Embedded host enable +It is used to select between OTG A device state machine and embedded host state machine. + 12 + 1 + read-write + + + B_0x0 + OTG A device state machine is selected + 0x0 + + + B_0x1 + Embedded host state machine is selected + 0x1 + + + + + CIDSTS + Connector ID status +Indicates the connector ID status on a connect event. +Note: Accessible in both device and host modes. + 16 + 1 + read-only + + + B_0x0 + The OTG controller is in A-device mode + 0x0 + + + B_0x1 + The OTG controller is in B-device mode + 0x1 + + + + + DBCT + Long/short debounce time +Indicates the debounce time of a detected connection. +Note: Only accessible in host mode. + 17 + 1 + read-only + + + B_0x0 + Long debounce time, used for physical connections (100 ms + 2.5 µs) + 0x0 + + + B_0x1 + Short debounce time, used for soft connections (2.5 µs) + 0x1 + + + + + ASVLD + A-session valid +Indicates the host mode transceiver status. +Note: Only accessible in host mode. + 18 + 1 + read-only + + + B_0x0 + A-session is not valid + 0x0 + + + B_0x1 + A-session is valid + 0x1 + + + + + BSVLD + B-session valid +Indicates the device mode transceiver status. +In OTG mode, the user can use this bit to determine if the device is connected or disconnected. +Note: Only accessible in device mode. + 19 + 1 + read-only + + + B_0x0 + B-session is not valid. + 0x0 + + + B_0x1 + B-session is valid. + 0x1 + + + + + OTGVER + OTG version +Selects the OTG revision. + 20 + 1 + read-write + + + B_0x0 + OTG Version 1.3. OTG1.3 is obsolete for new product development. + 0x0 + + + B_0x1 + OTG Version 2.0. In this version the core supports only data line pulsing for SRP. + 0x1 + + + + + CURMOD + Current mode of operation +Indicates the current mode (host or device). + 21 + 1 + read-only + + + B_0x0 + Device mode + 0x0 + + + B_0x1 + Host mode + 0x1 + + + + + + + OTG_GOTGINT + OTG_GOTGINT + OTG interrupt register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEDET + Session end detected +The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V. +Note: Accessible in both device and host modes. + 2 + 1 + read-write + + + SRSSCHG + Session request success status change +The core sets this bit on the success or failure of a session request. The application must read the session request success bit in the OTG_GOTGCTL register (SRQSCS bit in OTG_GOTGCTL) to check for success or failure. +Note: Accessible in both device and host modes. + 8 + 1 + read-write + + + HNSSCHG + Host negotiation success status change +The core sets this bit on the success or failure of a USB host negotiation request. The application must read the host negotiation success bit of the OTG_GOTGCTL register (HNGSCS bit in OTG_GOTGCTL) to check for success or failure. +Note: Accessible in both device and host modes. + 9 + 1 + read-write + + + HNGDET + Host negotiation detected +The core sets this bit when it detects a host negotiation request on the USB. +Note: Accessible in both device and host modes. + 17 + 1 + read-write + + + ADTOCHG + A-device timeout change +The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. +Note: Accessible in both device and host modes. + 18 + 1 + read-write + + + DBCDNE + Debounce done +The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the OTG_GUSBCFG register (HNPCAP bit or SRPCAP bit in OTG_GUSBCFG, respectively). +Note: Only accessible in host mode. + 19 + 1 + read-write + + + + + OTG_GAHBCFG + OTG_GAHBCFG + OTG AHB configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GINTMSK + Global interrupt mask +The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the core. +Note: Accessible in both device and host modes. + 0 + 1 + read-write + + + B_0x0 + Mask the interrupt assertion to the application. + 0x0 + + + B_0x1 + Unmask the interrupt assertion to the application. + 0x1 + + + + + HBSTLEN + Burst length/type +0000 Single: Bus transactions use single 32 bit accesses (not recommended) +0001 INCR: Bus transactions use unspecified length accesses (not recommended, uses the INCR AHB bus command) +0011 INCR4: Bus transactions target 4x 32 bit accesses +0101 INCR8: Bus transactions target 8x 32 bit accesses +0111 INCR16: Bus transactions based on 16x 32 bit accesses +Others: Reserved + 1 + 4 + read-write + + + DMAEN + DMA enabled + 5 + 1 + read-write + + + B_0x0 + The core operates in slave mode + 0x0 + + + B_0x1 + The core operates in DMA mode + 0x1 + + + + + TXFELVL + Tx FIFO empty level +In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered +In host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) is triggered + 7 + 1 + read-write + + + B_0x0_DEVICE_MODE + The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty + 0x0 + + + B_0x1_DEVICE_MODE + The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty + 0x1 + + + B_0x0_HOST_MODE + The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is half empty + 0x0 + + + B_0x1_HOST_MODE + The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is completely empty + 0x1 + + + + + PTXFELVL + Periodic Tx FIFO empty level +Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered. +Note: Only accessible in host mode. + 8 + 1 + read-write + + + B_0x0 + PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty + 0x0 + + + B_0x1 + PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty + 0x1 + + + + + + + OTG_GUSBCFG + OTG_GUSBCFG + OTG USB configuration register + 0xc + 0x20 + 0x00001400 + 0xFFFFFFFF + + + TOCAL + FS timeout calibration +The number of PHY clocks that the application programs in this field is added to the full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the line state condition can vary from one PHY to another. +The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock is 0.25 bit times. + 0 + 3 + read-write + + + SRPCAP + SRP-capable +The application uses this bit to control the OTG controller's SRP capabilities. If the core operates as a non-SRP-capable +B-device, it cannot request the connected A-device (host) to activate VBUS and start a session. +Note: Accessible in both device and host modes. + 8 + 1 + read-write + + + B_0x0 + SRP capability is not enabled. + 0x0 + + + B_0x1 + SRP capability is enabled. + 0x1 + + + + + HNPCAP + HNP-capable +The application uses this bit to control the OTG controller's HNP capabilities. +Note: Accessible in both device and host modes. + 9 + 1 + read-write + + + B_0x0 + HNP capability is not enabled. + 0x0 + + + B_0x1 + HNP capability is enabled. + 0x1 + + + + + TRDT + USB turnaround time +These bits allows to set the turnaround time in PHY clocks. They must be configured according to or , depending on the application AHB frequency. Higher TRDT values allow stretching the USB response time to IN tokens in order to compensate for longer AHB read access latency to the data FIFO. +Note: Only accessible in device mode. + 10 + 4 + read-write + + + PHYLPC + PHY Low-power clock select +This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power. +In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates at 48 MHz in FS and LS modes. + 15 + 1 + read-write + + + B_0x0 + 480 MHz internal PLL clock + 0x0 + + + B_0x1 + 48 MHz external clock + 0x1 + + + + + TSDPS + TermSel DLine pulsing selection +This bit selects utmi_termselect to drive the data line pulse during SRP (session request protocol). + 22 + 1 + read-write + + + B_0x0 + Data line pulsing using utmi_txvalid (default) + 0x0 + + + B_0x1 + Data line pulsing using utmi_termsel + 0x1 + + + + + FHMOD + Force host mode +Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin. +After setting the force bit, the application must wait at least 25 ms before the change takes effect. +Note: Accessible in both device and host modes. + 29 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Force host mode + 0x1 + + + + + FDMOD + Force device mode +Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin. +After setting the force bit, the application must wait at least 25 ms before the change takes effect. +Note: Accessible in both device and host modes. + 30 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Force device mode + 0x1 + + + + + + + OTG_GRSTCTL + OTG_GRSTCTL + OTG reset register + 0x10 + 0x20 + 0x80000000 + 0xFFFFFFFF + + + CSRST + Core soft reset +Resets the HCLK and PHY clock domains as follows: +Clears the interrupts and all the CSR register bits except for the following bits: +GATEHCLK bit in OTG_PCGCCTL +STPPCLK bit in OTG_PCGCCTL +FSLSPCS bits in OTG_HCFG +DSPD bit in OTG_DCFG +SDIS bit in OTG_DCTL +OTG_GCCFG register +All module state machines (except for the AHB slave unit) are reset to the Idle state, and all the transmit FIFOs and the receive FIFO are flushed. +Any transactions on the AHB Master are terminated as soon as possible, after completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. +The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit has been cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation. +Typically, the software reset is used during software development and also when the user dynamically changes the PHY selection bits in the above listed USB configuration registers. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation. +Note: Accessible in both device and host modes. + 0 + 1 + read-write + + + PSRST + Partial soft reset +Resets the internal state machines but keeps the enumeration info. Could be used to recover some specific PHY errors. +Note: Accessible in both device and host modes. + 1 + 1 + read-write + + + FCRST + Host frame counter reset +The application writes this bit to reset the (micro-)frame number counter inside the core. When the (micro-)frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. +When application writes '1' to the bit, it might not be able to read back the value as it gets cleared by the core in a few clock cycles. +Note: Only accessible in host mode. + 2 + 1 + read-write + + + RXFFLSH + Rx FIFO flush +The application can flush the entire Rx FIFO using this bit, but must first ensure that the core is not in the middle of a transaction. +The application must only write to this bit after checking that the core is neither reading from the Rx FIFO nor writing to the Rx FIFO. +The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear. +Note: Accessible in both device and host modes. + 4 + 1 + read-write + + + TXFFLSH + Tx FIFO flush +This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. +The application must write this bit only after checking that the core is neither writing to the Tx FIFO nor reading from the Tx FIFO. Verify using these registers: +Read—NAK Effective interrupt ensures the core is not reading from the FIFO +Write—AHBIDL bit in OTG_GRSTCTL ensures the core is not writing anything to the FIFO. +Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk. +Note: Accessible in both device and host modes. + 5 + 1 + read-write + + + TXFNUM + Tx FIFO number +This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not be changed until the core clears the Tx FIFO Flush bit. +Others: Reserved, must not be used +... +Note: Accessible in both device and host modes. + 6 + 5 + read-write + + + B_0x0_HOST_MODE + Non-periodic Tx FIFO flush + 0x0 + + + B_0x1_HOST_MODE + Periodic Tx FIFO flush + 0x1 + + + B_0x10_HOST_MODE + Flush all the transmit FIFOs + 0x10 + + + B_0x0_DEVICE_MODE + Tx FIFO 0 flush + 0x0 + + + B_0x1_DEVICE_MODE + Tx FIFO 1 flush + 0x1 + + + B_0x2_DEVICE_MODE + Tx FIFO 2 flush in device mode + 0x2 + + + B_0xF_DEVICE_MODE + Tx FIFO 15 flush in device mode + 0xF + + + B_0x10_DEVICE_MODE + Flush all the transmit FIFOs + 0x10 + + + + + DMAREQ + DMA request signal enabled +This bit indicates that the DMA request is in progress. Used for debug. + 30 + 1 + read-only + + + AHBIDL + AHB master idle +Indicates that the AHB master state machine is in the Idle condition. +Note: Accessible in both device and host modes. + 31 + 1 + read-only + + + + + OTG_GINTSTS + OTG_GINTSTS + OTG core interrupt register + 0x14 + 0x20 + 0x04000020 + 0xFFFFFFFF + + + CMOD + Current mode of operation +Indicates the current mode. +Note: Accessible in both host and device modes. + 0 + 1 + read-only + + + B_0x0 + Device mode + 0x0 + + + B_0x1 + Host mode + 0x1 + + + + + MMIS + Mode mismatch interrupt +The core sets this bit when the application is trying to access: +A host mode register, when the core is operating in device mode +A device mode register, when the core is operating in host mode +The register access is completed on the AHB with an OKAY response, but is ignored by the core internally and does not affect the operation of the core. +Note: Accessible in both host and device modes. + 1 + 1 + read-write + + + OTGINT + OTG interrupt +The core sets this bit to indicate an OTG protocol event. The application must read the OTG interrupt status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit. +Note: Accessible in both host and device modes. + 2 + 1 + read-only + + + SOF + Start of frame +In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. +In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the OTG_DSTS register to get the current frame number. This interrupt is seen only when the core is operating in FS. +Note: This register may return '1' if read immediately after power on reset. If the register bit reads '1' immediately after power on reset it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode). The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit. +Note: Accessible in both host and device modes. + 3 + 1 + read-write + + + RXFLVL + Rx FIFO non-empty +Indicates that there is at least one packet pending to be read from the Rx FIFO. +Note: Accessible in both host and device modes. + 4 + 1 + read-only + + + NPTXFE + Non-periodic Tx FIFO empty +This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). +Note: Accessible in host mode only. + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK effective +Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL). +This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit. +Note: Only accessible in device mode. + 6 + 1 + read-only + + + GONAKEFF + Global OUT NAK effective +Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). +Note: Only accessible in device mode. + 7 + 1 + read-only + + + ESUSP + Early suspend +The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. +Note: Only accessible in device mode. + 10 + 1 + read-write + + + USBSUSP + USB suspend +The core sets this bit to indicate that a suspend was detected on the USB. The core enters the suspended state when there is no activity on the data lines for an extended period of time. +Note: Only accessible in device mode. + 11 + 1 + read-write + + + USBRST + USB reset +The core sets this bit to indicate that a reset is detected on the USB. +Note: Only accessible in device mode. + 12 + 1 + read-write + + + ENUMDNE + Enumeration done +The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed. +Note: Only accessible in device mode. + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped interrupt +The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint. +Note: Only accessible in device mode. + 14 + 1 + read-write + + + EOPF + End of periodic frame interrupt +Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame. +Note: Only accessible in device mode. + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt +The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit. +Note: Only accessible in device mode. + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt +The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. +Note: Only accessible in device mode. + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN transfer +The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. +Note: Only accessible in device mode. + 20 + 1 + read-write + + + IPXFR + Incomplete periodic transfer +In host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. The alternate description for device mode is in next paragraph + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended +This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue space. This interrupt is used by the application for an endpoint mismatch algorithm. For example, after detecting an endpoint mismatch, the application: +Sets a global nonperiodic IN NAK handshake +Disables IN endpoints +Flushes the FIFO +Determines the token sequence from the IN token sequence learning queue +Re-enables the endpoints +Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an “IN token received when FIFO empty” interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the “IN token received when FIFO empty” interrupt when clearing a global IN NAK handshake. + 22 + 1 + read-write + + + RSTDET + Reset detected interrupt +In device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in suspend. +Note: Only accessible in device mode. + 23 + 1 + read-write + + + HPRTINT + Host port interrupt +The core sets this bit to indicate a change in port status of one of the OTG controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. +Note: Only accessible in host mode. + 24 + 1 + read-only + + + HCINT + Host channels interrupt +The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit. +Note: Only accessible in host mode. + 25 + 1 + read-only + + + PTXFE + Periodic Tx FIFO empty +Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG). +Note: Only accessible in host mode. + 26 + 1 + read-only + + + LPMINT + LPM interrupt +In device mode, this interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. +In host mode, this interrupt is asserted when the device responds to an LPM transaction with a non-ERRORed response or when the host core has completed LPM transactions for the programmed number of times (RETRYCNT bit in OTG_GLPMCFG). +This field is valid only if the LPMEN bit in OTG_GLPMCFG is set to 1. + 27 + 1 + read-write + + + CIDSCHG + Connector ID status change +The core sets this bit when there is a change in connector ID status. +Note: Accessible in both device and host modes. + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt +Asserted when a device disconnect is detected. +Note: Only accessible in host mode. + 29 + 1 + read-write + + + SRQINT + Session request/new session detected interrupt +In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected interrupt +Wakeup interrupt during suspend(L2) or LPM(L1) state. +During suspend(L2): +In device mode, this interrupt is asserted when a resume is detected on the USB. In host mode, this interrupt is asserted when a remote wakeup is detected on the USB. +During LPM(L1): +This interrupt is asserted for either host initiated resume or device initiated remote wakeup on USB. +Note: Accessible in both device and host modes. + 31 + 1 + read-write + + + + + OTG_GINTMSK + OTG_GINTMSK + OTG interrupt mask register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MMISM + Mode mismatch interrupt mask +Note: Accessible in both device and host modes. + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + OTGINT + OTG interrupt mask +Note: Accessible in both device and host modes. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + SOFM + Start of frame mask +Note: Accessible in both device and host modes. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + RXFLVLM + Receive FIFO non-empty mask +Note: Accessible in both device and host modes. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NPTXFEM + Non-periodic Tx FIFO empty mask +Note: Only accessible in host mode. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + GINAKEFFM + Global non-periodic IN NAK effective mask +Note: Only accessible in device mode. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + GONAKEFFM + Global OUT NAK effective mask +Note: Only accessible in device mode. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ESUSPM + Early suspend mask +Note: Only accessible in device mode. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + USBSUSPM + USB suspend mask +Note: Only accessible in device mode. + 11 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + USBRST + USB reset mask +Note: Only accessible in device mode. + 12 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ENUMDNEM + Enumeration done mask +Note: Only accessible in device mode. + 13 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ISOODRPM + Isochronous OUT packet dropped interrupt mask +Note: Only accessible in device mode. + 14 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + EOPFM + End of periodic frame interrupt mask +Note: Only accessible in device mode. + 15 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + IEPINT + IN endpoints interrupt mask +Note: Only accessible in device mode. + 18 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + OEPINT + OUT endpoints interrupt mask +Note: Only accessible in device mode. + 19 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + IISOIXFRM + Incomplete isochronous IN transfer mask +Note: Only accessible in device mode. + 20 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + IPXFRM + Incomplete periodic transfer mask +Note: Only accessible in host mode. The alternate descripton for device mode is defined in next paragraph + 21 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FSUSPM + Data fetch suspended mask +Only accessible in peripheral mode. + 22 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + RSTDETM + Reset detected interrupt mask +Note: Only accessible in device mode. + 23 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + PRTIM + Host port interrupt mask +Note: Only accessible in host mode. + 24 + 1 + read-only + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + HCIM + Host channels interrupt mask +Note: Only accessible in host mode. + 25 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + PTXFEM + Periodic Tx FIFO empty mask +Note: Only accessible in host mode. + 26 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + LPMINTM + LPM interrupt mask +Note: Accessible in both host and device modes. + 27 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CIDSCHGM + Connector ID status change mask +Note: Accessible in both host and device modes. + 28 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DISCINT + Disconnect detected interrupt mask +Note: Only accessible in host mode. + 29 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + SRQIM + Session request/new session detected interrupt mask +Note: Accessible in both host and device modes. + 30 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + WUIM + Resume/remote wakeup detected interrupt mask +Note: Accessible in both host and device modes. + 31 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_GRXSTSR + OTG_GRXSTSR + OTG receive status debug read register + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EPNUM + Endpoint number +Indicates the endpoint number to which the current received packet belongs. + 0 + 4 + read-only + + + BCNT + Byte count +Indicates the byte count of the received data packet. + 4 + 11 + read-only + + + DPID + Data PID +Indicates the data PID of the received OUT data packet + 15 + 2 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x2 + DATA1 + 0x2 + + + B_0x1 + DATA2 + 0x1 + + + B_0x3 + MDATA + 0x3 + + + + + PKTSTS + Packet status +Indicates the status of the received packet +Others: Reserved + 17 + 4 + read-only + + + B_0x1 + Global OUT NAK (triggers an interrupt) + 0x1 + + + B_0x2 + OUT data packet received + 0x2 + + + B_0x3 + OUT transfer completed (triggers an interrupt) + 0x3 + + + B_0x4 + SETUP transaction completed (triggers an interrupt) + 0x4 + + + B_0x6 + SETUP data packet received + 0x6 + + + + + FRMNUM + Frame number +This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. + 21 + 4 + read-only + + + STSPHST + Status phase start +Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern. + 27 + 1 + read-only + + + + + OTG_GRXSTSP + OTG_GRXSTSP + OTG status read and pop register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EPNUM + Endpoint number +Indicates the endpoint number to which the current received packet belongs. + 0 + 4 + read-only + + + BCNT + Byte count +Indicates the byte count of the received data packet. + 4 + 11 + read-only + + + DPID + Data PID +Indicates the data PID of the received OUT data packet + 15 + 2 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x2 + DATA1 + 0x2 + + + B_0x1 + DATA2 + 0x1 + + + B_0x3 + MDATA + 0x3 + + + + + PKTSTS + Packet status +Indicates the status of the received packet +Others: Reserved + 17 + 4 + read-only + + + B_0x1 + Global OUT NAK (triggers an interrupt) + 0x1 + + + B_0x2 + OUT data packet received + 0x2 + + + B_0x3 + OUT transfer completed (triggers an interrupt) + 0x3 + + + B_0x4 + SETUP transaction completed (triggers an interrupt) + 0x4 + + + B_0x6 + SETUP data packet received + 0x6 + + + + + FRMNUM + Frame number +This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. + 21 + 4 + read-only + + + STSPHST + Status phase start +Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern. + 27 + 1 + read-only + + + + + OTG_GRXFSIZ + OTG_GRXFSIZ + OTG receive FIFO size register + 0x24 + 0x20 + 0x00000400 + 0xFFFFFFFF + + + RXFD + Rx FIFO depth +This value is in terms of 32-bit words. +Maximum value is 1024 +Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. + 0 + 16 + read-write + + + + + OTG_HNPTXFSIZ + OTG_HNPTXFSIZ + OTG host non-periodic transmit FIFO size register + 0x28 + 0x20 + 0x02000200 + 0xFFFFFFFF + + + NPTXFSA + Non-periodic transmit RAM start address +This field configures the memory start address for non-periodic transmit FIFO RAM. + 0 + 16 + read-write + + + NPTXFD + Non-periodic Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 +Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. + 16 + 16 + read-write + + + + + OTG_HNPTXSTS + OTG_HNPTXSTS + OTG non-periodic transmit FIFO/queue status register + 0x2c + 0x20 + 0x00080400 + 0xFFFFFFFF + + + NPTXFSAV + Non-periodic Tx FIFO space available +Indicates the amount of free space available in the non-periodic Tx FIFO. +Values are in terms of 32-bit words. +2: 2 words available +n: n words available (where 0 ≤ n ≤ 512) +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Non-periodic Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + + + NPTQXSAV + Non-periodic transmit request queue space available +Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests. +2: locations available +n: n locations available (0 ≤ n ≤ 8) +Others: Reserved + 16 + 8 + read-only + + + B_0x0 + Non-periodic transmit request queue is full + 0x0 + + + B_0x1 + 1 location available + 0x1 + + + + + NPTXQTOP + Top of the non-periodic transmit request queue +Entry in the non-periodic Tx request queue that is currently being processed by the MAC. +Bits 30:27: Channel/endpoint number +Bits 26:25: +Bit 24: Terminate (last entry for selected channel/endpoint) + 24 + 7 + read-only + + + B_0x0 + IN/OUT token + 0x0 + + + B_0x1 + Zero-length transmit packet (device IN/host OUT) + 0x1 + + + B_0x3 + Channel halt command + 0x3 + + + + + + + OTG_GCCFG + OTG_GCCFG + 0x38 + 0x20 + 0x00000000 + 0xFFFF0000 + + + VBDEN + USB VBUS detection enable +Enables VBUS sensing comparators to detect VBUS valid levels on the VBUS PAD for USB host and device operation. If HNP and/or SRP support is enabled, VBUS comparators are automatically enabled independently of VBDEN value. +0 = VBUS detection disabled +1 = VBUS detection enabled + 21 + 1 + read-write + + + IDEN + USB ID detection enable +Enables detection of the ID pin state. + 22 + 1 + read-write + + + B_0x0 + Disable ID pin state detection + 0x0 + + + B_0x1 + Enable ID pin state detection + 0x1 + + + + + + + OTG_CID + OTG_CID + OTG core ID register + 0x3c + 0x20 + 0x00004000 + 0xFFFFFFFF + + + PRODUCT_ID + Product ID field +Application-programmable ID field. + 0 + 32 + read-write + + + + + OTG_GLPMCFG + OTG_GLPMCFG + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable +The application uses this bit to control the OTG core LPM capabilities. +If the core operates as a non-LPM-capable host, it cannot request the connected device or hub to activate LPM mode. +If the core operates as a non-LPM-capable device, it cannot respond to any LPM transactions. + 0 + 1 + read-write + + + B_0x0 + LPM capability is not enabled + 0x0 + + + B_0x1 + LPM capability is enabled + 0x1 + + + + + LPMACK + LPM token acknowledge enable +Handshake response to LPM token preprogrammed by device application software. +Even though ACK is preprogrammed, the core device responds with ACK only on successful LPM transaction. The LPM transaction is successful if: +No PID/CRC5 errors in either EXT token or LPM token (else ERROR) +Valid bLinkState = 0001B (L1) received in LPM transaction (else STALL) +No data pending in transmit queue (else NYET). +The preprogrammed software bit is over-ridden for response to LPM token when: +The received bLinkState is not L1 (STALL response), or +An error is detected in either of the LPM token packets because of corruption (ERROR response). +Note: Accessible only in device mode. + 1 + 1 + read-write + + + B_0x1 + ACK + 0x1 + + + B_0x0 + NYET + 0x0 + + + + + BESL + Best effort service latency +Host mode: +The value of BESL to be sent in an LPM transaction. This value is also used to initiate resume for a duration TL1HubDrvResume1 for host initiated resume. +Device mode (read-only): +This field is updated with the received LPM token BESL bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. +BESL[3:0] TBESL (μs) + 2 + 4 + read-write + + + B_0x0 + 125 + 0x0 + + + B_0x1 + 150 + 0x1 + + + B_0x2 + 200 + 0x2 + + + B_0x3 + 300 + 0x3 + + + B_0x4 + 400 + 0x4 + + + B_0x5 + 500 + 0x5 + + + B_0x6 + 1000 + 0x6 + + + B_0x7 + 2000 + 0x7 + + + B_0x8 + 3000 + 0x8 + + + B_0x9 + 4000 + 0x9 + + + B_0xA + 5000 + 0xA + + + B_0xB + 6000 + 0xB + + + B_0xC + 7000 + 0xC + + + B_0xD + 8000 + 0xD + + + B_0xE + 9000 + 0xE + + + B_0xF + 10000 + 0xF + + + + + REMWAKE + bRemoteWake value +Host mode: +The value of remote wake up to be sent in the wIndex field of LPM transaction. +Device mode (read-only): +This field is updated with the received LPM token bRemoteWake bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. + 6 + 1 + read-write + + + L1SSEN + L1 Shallow Sleep enable +Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. + 7 + 1 + read-write + + + BESLTHRS + BESL threshold +Device mode: +The core puts the PHY into deep low power mode in L1 when BESL value is greater than or equal to the value defined in this field BESL_Thres[3:0]. +Host mode: +The core puts the PHY into deep low power mode in L1. BESLTHRS[3:0] specifies the time for which resume signaling is to be reflected by host (TL1HubDrvResume2) on the USB bus when it detects device initiated resume. +BESLTHRS must not be programmed with a value greater than 1100b in host mode, because this exceeds maximum TL1HubDrvResume2. +Thres[3:0] host mode resume signaling time (μs): +All other values: reserved + 8 + 4 + read-write + + + B_0x0 + 75 + 0x0 + + + B_0x1 + 100 + 0x1 + + + B_0x2 + 150 + 0x2 + + + B_0x3 + 250 + 0x3 + + + B_0x4 + 350 + 0x4 + + + B_0x5 + 450 + 0x5 + + + B_0x6 + 950 + 0x6 + + + + + L1DSEN + L1 deep sleep enable +Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. + 12 + 1 + read-write + + + LPMRSP + LPM response +Device mode: +The response of the core to LPM transaction received is reflected in these two bits. +Host mode: +Handshake response received from local device for LPM transaction + 13 + 2 + read-only + + + B_0x3 + ACK + 0x3 + + + B_0x2 + NYET + 0x2 + + + B_0x1 + STALL + 0x1 + + + B_0x0 + ERROR (No handshake response) + 0x0 + + + + + SLPSTS + Port sleep status +Device mode: +This bit is set as long as a Sleep condition is present on the USB bus. The core enters the Sleep state when an ACK response is sent to an LPM transaction and the TL1TokenRetry timer has expired. To stop the PHY clock, the application must set the STPPCLK bit in OTG_PCGCCTL, which asserts the PHY suspend input signal. +The application must rely on SLPSTS and not ACK in LPMRSP to confirm transition into sleep. +The core comes out of sleep: +When there is any activity on the USB linestate +When the application writes to the RWUSIG bit in OTG_DCTL or when the application resets or soft-disconnects the device. +Host mode: +The host transitions to Sleep (L1) state as a side-effect of a successful LPM transaction by the core to the local port with ACK response from the device. The read value of this bit reflects the current Sleep status of the port. +The core clears this bit after: +The core detects a remote L1 wakeup signal, +The application sets the PRST bit or the PRES bit in the OTG_HPRT register, or +The application sets the L1Resume/ remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (WKUPINT or DISCINT bit in OTG_GINTSTS, respectively). + 15 + 1 + read-only + + + B_0x0 + Core not in L1 + 0x0 + + + B_0x1 + Core in L1 + 0x1 + + + + + L1RSMOK + Sleep state resume OK +Indicates that the device or host can start resume from Sleep state. This bit is valid in LPM sleep (L1) state. It is set in sleep mode after a delay of 50 μs (TL1Residency). +This bit is reset when SLPSTS is 0. + 16 + 1 + read-only + + + B_0x1 + The application or host can start resume from Sleep state + 0x1 + + + B_0x0 + The application or host cannot start resume from Sleep state + 0x0 + + + + + LPMCHIDX + LPM Channel Index +The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. Based on the LPM channel index, the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction. +Note: Accessible only in host mode. + 17 + 4 + read-write + + + LPMRCNT + LPM retry count +When the device gives an ERROR response, this is the number of additional LPM retries that the host performs until a valid device response (STALL, NYET, or ACK) is received. +Note: Accessible only in host mode. + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction +When the application software sets this bit, an LPM transaction containing two tokens, EXT and LPM is sent. The hardware clears this bit once a valid response (STALL, NYET, or ACK) is received from the device or the core has finished transmitting the programmed number of LPM retries. +Note: This bit must be set only when the host is connected to a local port. +Note: Accessible only in host mode. + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status +Number of LPM host retries still remaining to be transmitted for the current LPM sequence. +Note: Accessible only in host mode. + 25 + 3 + read-only + + + ENBESL + Enable best effort service latency +This bit enables the BESL feature as defined in the LPM errata: +USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 +Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 +Note: Only the updated behavior (described in LPM Errata) is considered in this document and so the ENBESL bit should be set to '1' by application SW. + 28 + 1 + read-write + + + B_0x0 + The core works as described in the following document: + 0x0 + + + B_0x1 + The core works as described in the LPM Errata: + 0x1 + + + + + + + OTG_HPTXFSIZ + OTG_HPTXFSIZ + 0x100 + 0x20 + 0x04000800 + 0xFFFFFFFF + + + PTXSA + Host periodic Tx FIFO start address +This field configures the memory start address for periodic transmit FIFO RAM. + 0 + 16 + read-write + + + PTXFSIZ + Host periodic Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF1 + OTG_DIEPTXF1 + 0x104 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF2 + OTG_DIEPTXF2 + 0x108 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF3 + OTG_DIEPTXF3 + 0x10c + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF4 + OTG_DIEPTXF4 + 0x110 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF5 + OTG_DIEPTXF5 + 0x114 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF6 + OTG_DIEPTXF6 + 0x118 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF7 + OTG_DIEPTXF7 + 0x11c + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_DIEPTXF8 + OTG_DIEPTXF8 + 0x120 + 0x20 + 0x02000400 + 0xFFFFFFFF + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address +This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. + 0 + 16 + read-write + + + INEPTXFD + IN endpoint Tx FIFO depth +This value is in terms of 32-bit words. +Minimum value is 16 + 16 + 16 + read-write + + + + + OTG_HCFG + OTG_HCFG + OTG host configuration register + 0x400 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FSLSPCS + FS/LS PHY clock select +Others: Reserved +Note: The FSLSPCS must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). + 0 + 2 + read-write + + + B_0x1_CORE_IN_FS_HOST_MODE + PHY clock is running at 48 MHz + 0x1 + + + B_0x1_CORE_IN_LS_HOST_MODE + Select 48 MHz PHY clock frequency + 0x1 + + + B_0x2_CORE_IN_LS_HOST_MODE + Select 6 MHz PHY clock frequency + 0x2 + + + + + FSLSS + FS- and LS-only support +The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. + 2 + 1 + read-only + + + DESCDMA + Enable scatter/gather DMA in host mode +The application can set this bit during initialization to enable the Scatter/Gather DMA operation. This bit must be modified only once after a reset. The following combinations are available for programming: +OTG_GAHBCFG.DMAEN=0,OTG_HCFG.DESCDMA=0 => Slave mode +OTG_GAHBCFG.DMAEN=0,OTG_HCFG.DESCDMA=1 => Invalid +OTG_GAHBCFG.DMAEN=1,OTG_HCFG.DESCDMA=0 => Buffered DMA mode +OTG_GAHBCFG.DMAEN=1,OTG_HCFG.DESCDMA=1 => Scatter/Gather DMA mode + 23 + 1 + read-write + + + FRLSTEN + Frame list entries +The value in the register specifies the number of entries in the Frame list. This field is valid only in Scatter/Gather DMA mode. +2'b00: Reserved +2'b01: 8 Entries +2'b10: 16 Entries +2'b11: 32 Entries In non-Scatter/Gather + 24 + 2 + read-write + + + PERSSCHEDENA + Enable periodic scheduling +Applicable in host scatter/gather DMA mode only. Enables periodic scheduling within the core. Initially, the bit is res and the core does not process any periodic channels. As soon as this bit is set, the core gets ready to start scheduling periodic channels and sets OTG_HCFG.PERSCHEDSTAT. The setting of PERSCHEDSTAT indicates the core has enabled periodic scheduling. Once PERSSCHEDENA is set, the application is not supposed to reset the bit unless PERSCHEDSTAT is set. As soon as this bit is reset, the core gets ready to stop scheduling periodic channels and resets HCFG. PerSchedStat. In non-Scatter/Gather DMA mode, this bit is reserved. + 26 + 1 + read-write + + + + + OTG_HFIR + OTG_HFIR + OTG host frame interval register + 0x404 + 0x20 + 0x0000EA60 + 0xFFFFFFFF + + + FRIVL + Frame interval +The value that the application programs to this field, specifies the interval between two consecutive micro-SOFs (HS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the port enable bit of the host port control and status register (PENA bit in OTG_HPRT) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY clock select field of the host configuration register (FSLSPCS in OTG_HCFG). Do not change the value of this field after the initial configuration, unless the RLDCTRL bit is set. In such case, the FRIVL is reloaded with each SOF event. +Frame interval = 125 μs × (FRIVL - 1) in high speed operation +Frame interval = 1 ms × (FRIVL - 1) in low/full speed operation + 0 + 16 + read-write + + + RLDCTRL + Reload control +This bit allows dynamic reloading of the HFIR register during run time. +This bit needs to be programmed during initial configuration and its value must not be changed during run time. +RLDCTRL = 0 is not recommended. + 16 + 1 + read-write + + + B_0x0 + The HFIR cannot be reloaded dynamically + 0x0 + + + B_0x1 + The HFIR can be dynamically reloaded during run time. + 0x1 + + + + + + + OTG_HFNUM + OTG_HFNUM + OTG host frame number/frame time remaining register + 0x408 + 0x20 + 0x00003FFF + 0xFFFFFFFF + + + FRNUM + Frame number +This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when it reaches 0x3FFF. + 0 + 16 + read-only + + + FTREM + Frame time remaining +Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB. + 16 + 16 + read-only + + + + + OTG_HPTXSTS + OTG_HPTXSTS + OTG_Host periodic transmit FIFO/queue status register + 0x410 + 0x20 + 0x00080100 + 0xFFFFFFFF + + + PTXFSAVL + Periodic transmit data FIFO space available +Indicates the number of free locations available to be written to in the periodic Tx FIFO. +Values are in terms of 32-bit words +bxn: n words available (where 0 ≤ n ≤ PTXFD) +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Periodic Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + PTXQSAV + Periodic transmit request queue space available +Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. +Others: Reserved + 16 + 8 + read-only + + + B_0x0 + Periodic transmit request queue is full + 0x0 + + + B_0x1 + 1 location available + 0x1 + + + B_0x2 + 2 locations available + 0x2 + + + B_0x4 + 3 locations available + 0x4 + + + B_0x8 + 4 locations available + 0x8 + + + B_0x10 + 5 locations available + 0x10 + + + B_0x20 + 6 locations available + 0x20 + + + B_0x40 + 7 locations available + 0x40 + + + B_0x80 + 8 locations available + 0x80 + + + + + PTXQTOP + Top of the periodic transmit request queue +This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. +This register is used for debugging. +Bit 31 = 0 send in even frame +Bit 31 = 1 send in odd frame +Bits 30:27: Channel/endpoint number +Bits 26:25 = 00: Type IN/OUT +Bits 26:25 = 01: Type Zero-length packet +Bits 26:25 = 11: disable channel command +Bit 24: Terminate (last entry for the selected channel/endpoint) + 24 + 8 + read-only + + + + + OTG_HAINT + OTG_HAINT + OTG host all channels interrupt register + 0x414 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HAINT + Channel interrupts +One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 + 0 + 16 + read-only + + + + + OTG_HAINTMSK + OTG_HAINTMSK + OTG host all channels interrupt mask register + 0x418 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HAINTM + Channel interrupt mask +One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 + 0 + 16 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_HFLBADDR + OTG_HFLBADDR + OTG host frame list base address register + 0x41c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HFLBADDR + The starting address of the frame list (scatter/gather mode). +This register is used only for isochronous and interrupt channels. + 0 + 32 + read-write + + + + + OTG_HPRT + OTG_HPRT + OTG host port control and status register + 0x440 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PCSTS + Port connect status + 0 + 1 + read-only + + + B_0x0 + No device is attached to the port + 0x0 + + + B_0x1 + A device is attached to the port + 0x1 + + + + + PCDET + Port connect detected +The core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit in the core interrupt register (HPRTINT bit in OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt. + 1 + 1 + read-write + + + PENA + Port enable +A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port. This bit does not trigger any interrupt to the application. + 2 + 1 + read-write + + + B_0x0 + Port disabled + 0x0 + + + B_0x1 + Port enabled + 0x1 + + + + + PENCHNG + Port enable/disable change +The core sets this bit when the status of the port enable bit 2 in this register changes. + 3 + 1 + read-write + + + POCA + Port overcurrent active +Indicates the overcurrent condition of the port. + 4 + 1 + read-only + + + B_0x0 + No overcurrent condition + 0x0 + + + B_0x1 + Overcurrent condition + 0x1 + + + + + POCCHNG + Port overcurrent change +The core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. + 5 + 1 + read-write + + + PRES + Port resume +The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. +If the core detects a USB remote wakeup sequence, as indicated by the port resume/remote wakeup detected interrupt bit of the core interrupt register (WKUPINT bit in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling. +When LPM is enabled and the core is in L1 state, the behavior of this bit is as follow: +1. The application sets this bit to drive resume signaling on the port. +2. The core continues to drive the resume signal until a predetermined time specified in BESLTHRS[3:0] field of OTG_GLPMCFG register. +3. If the core detects a USB remote wakeup sequence, as indicated by the port L1Resume/Remote L1Wakeup detected interrupt bit of the core interrupt register (WKUPINT in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit at the end of resume.This bit can be set or cleared by both the core and the application. This bit is cleared by the core even if there is no device connected to the host. + 6 + 1 + read-write + + + B_0x0 + No resume driven + 0x0 + + + B_0x1 + Resume driven + 0x1 + + + + + PSUSP + Port suspend +The application sets this bit to put this port in suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set the port clock stop bit, which asserts the suspend input pin of the PHY. +The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the port reset bit or port resume bit in this register or the resume/remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (WKUPINT or DISCINT in OTG_GINTSTS, respectively). + 7 + 1 + read-write + + + B_0x0 + Port not in suspend mode + 0x0 + + + B_0x1 + Port in suspend mode + 0x1 + + + + + PRST + Port reset +When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. +The application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the USB standard. +High speed: 50 ms +Full speed/Low speed: 10 ms + 8 + 1 + read-write + + + B_0x0 + Port not in reset + 0x0 + + + B_0x1 + Port in reset + 0x1 + + + + + PLSTS + Port line status +Indicates the current logic level USB data lines +Bit 10: Logic level of OTG_DP +Bit 11: Logic level of OTG_DM + 10 + 2 + read-only + + + PPWR + Port power +The application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. + 12 + 1 + read-write + + + B_0x0 + Power off + 0x0 + + + B_0x1 + Power on + 0x1 + + + + + PTCTL + Port test control +The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. +Others: Reserved + 13 + 4 + read-write + + + B_0x0 + Test mode disabled + 0x0 + + + B_0x1 + Test_J mode + 0x1 + + + B_0x2 + Test_K mode + 0x2 + + + B_0x3 + Test_SE0_NAK mode + 0x3 + + + B_0x4 + Test_Packet mode + 0x4 + + + B_0x5 + Test_Force_Enable + 0x5 + + + + + PSPD + Port speed +Indicates the speed of the device attached to this port. + 17 + 2 + read-only + + + B_0x1 + Full speed + 0x1 + + + B_0x2 + Low speed + 0x2 + + + B_0x0 + High speed + 0x0 + + + + + + + OTG_HCCHAR0 + OTG_HCCHAR0 + 0x500 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT0 + OTG_HCSPLT0 + 0x504 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT0 + OTG_HCINT0 + OTG host channel 0 interrupt register + 0x508 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK0 + OTG_HCINTMSK0 + OTG host channel 0 interrupt mask register + 0x50c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ0 + OTG_HCTSIZ0 + 0x510 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA0 + OTG_HCDMA0 + 0x514 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB0 + OTG_HCDMAB0 + 0x51c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR1 + OTG_HCCHAR1 + 0x520 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT1 + OTG_HCSPLT1 + 0x524 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT1 + OTG_HCINT1 + OTG host channel 1 interrupt register + 0x528 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK1 + OTG_HCINTMSK1 + OTG host channel 1 interrupt mask register + 0x52c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ1 + OTG_HCTSIZ1 + 0x530 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA1 + OTG_HCDMA1 + 0x534 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB1 + OTG_HCDMAB1 + 0x53c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR2 + OTG_HCCHAR2 + 0x540 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT2 + OTG_HCSPLT2 + 0x544 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT2 + OTG_HCINT2 + OTG host channel 2 interrupt register + 0x548 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK2 + OTG_HCINTMSK2 + OTG host channel 2 interrupt mask register + 0x54c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ2 + OTG_HCTSIZ2 + 0x550 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA2 + OTG_HCDMA2 + 0x554 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB2 + OTG_HCDMAB2 + 0x55c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR3 + OTG_HCCHAR3 + 0x560 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT3 + OTG_HCSPLT3 + 0x564 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT3 + OTG_HCINT3 + OTG host channel 3 interrupt register + 0x568 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK3 + OTG_HCINTMSK3 + OTG host channel 3 interrupt mask register + 0x56c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ3 + OTG_HCTSIZ3 + 0x570 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA3 + OTG_HCDMA3 + 0x574 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB3 + OTG_HCDMAB3 + 0x57c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR4 + OTG_HCCHAR4 + 0x580 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT4 + OTG_HCSPLT4 + 0x584 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT4 + OTG_HCINT4 + OTG host channel 4 interrupt register + 0x588 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK4 + OTG_HCINTMSK4 + OTG host channel 4 interrupt mask register + 0x58c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ4 + OTG_HCTSIZ4 + 0x590 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA4 + OTG_HCDMA4 + 0x594 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB4 + OTG_HCDMAB4 + 0x59c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR5 + OTG_HCCHAR5 + 0x5a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT5 + OTG_HCSPLT5 + 0x5a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT5 + OTG_HCINT5 + OTG host channel 5 interrupt register + 0x5a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK5 + OTG_HCINTMSK5 + OTG host channel 5 interrupt mask register + 0x5ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ5 + OTG_HCTSIZ5 + 0x5b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA5 + OTG_HCDMA5 + 0x5b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB5 + OTG_HCDMAB5 + 0x5bc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR6 + OTG_HCCHAR6 + 0x5c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT6 + OTG_HCSPLT6 + 0x5c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT6 + OTG_HCINT6 + OTG host channel 6 interrupt register + 0x5c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK6 + OTG_HCINTMSK6 + OTG host channel 6 interrupt mask register + 0x5cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ6 + OTG_HCTSIZ6 + 0x5d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA6 + OTG_HCDMA6 + 0x5d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB6 + OTG_HCDMAB6 + 0x5dc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR7 + OTG_HCCHAR7 + 0x5e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT7 + OTG_HCSPLT7 + 0x5e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT7 + OTG_HCINT7 + OTG host channel 7 interrupt register + 0x5e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK7 + OTG_HCINTMSK7 + OTG host channel 7 interrupt mask register + 0x5ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ7 + OTG_HCTSIZ7 + 0x5f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA7 + OTG_HCDMA7 + 0x5f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB7 + OTG_HCDMAB7 + 0x5fc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR8 + OTG_HCCHAR8 + 0x600 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT8 + OTG_HCSPLT8 + 0x604 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT8 + OTG_HCINT8 + OTG host channel 8 interrupt register + 0x608 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK8 + OTG_HCINTMSK8 + OTG host channel 8 interrupt mask register + 0x60c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ8 + OTG_HCTSIZ8 + 0x610 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA8 + OTG_HCDMA8 + 0x614 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB8 + OTG_HCDMAB8 + 0x61c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR9 + OTG_HCCHAR9 + 0x620 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT9 + OTG_HCSPLT9 + 0x624 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT9 + OTG_HCINT9 + OTG host channel 9 interrupt register + 0x628 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK9 + OTG_HCINTMSK9 + OTG host channel 9 interrupt mask register + 0x62c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ9 + OTG_HCTSIZ9 + 0x630 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA9 + OTG_HCDMA9 + 0x634 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB9 + OTG_HCDMAB9 + 0x63c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR10 + OTG_HCCHAR10 + 0x640 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT10 + OTG_HCSPLT10 + 0x644 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT10 + OTG_HCINT10 + OTG host channel 10 interrupt register + 0x648 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK10 + OTG_HCINTMSK10 + OTG host channel 10 interrupt mask register + 0x64c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ10 + OTG_HCTSIZ10 + 0x650 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA10 + OTG_HCDMA10 + 0x654 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB10 + OTG_HCDMAB10 + 0x65c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR11 + OTG_HCCHAR11 + 0x660 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT11 + OTG_HCSPLT11 + 0x664 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT11 + OTG_HCINT11 + OTG host channel 11 interrupt register + 0x668 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK11 + OTG_HCINTMSK11 + OTG host channel 11 interrupt mask register + 0x66c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ11 + OTG_HCTSIZ11 + 0x670 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA11 + OTG_HCDMA11 + 0x674 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB11 + OTG_HCDMAB11 + 0x67c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR12 + OTG_HCCHAR12 + 0x680 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT12 + OTG_HCSPLT12 + 0x684 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT12 + OTG_HCINT12 + OTG host channel 12 interrupt register + 0x688 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK12 + OTG_HCINTMSK12 + OTG host channel 12 interrupt mask register + 0x68c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ12 + OTG_HCTSIZ12 + 0x690 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA12 + OTG_HCDMA12 + 0x694 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB12 + OTG_HCDMAB12 + 0x69c + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR13 + OTG_HCCHAR13 + 0x6a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT13 + OTG_HCSPLT13 + 0x6a4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT13 + OTG_HCINT13 + OTG host channel 13 interrupt register + 0x6a8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK13 + OTG_HCINTMSK13 + OTG host channel 13 interrupt mask register + 0x6ac + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ13 + OTG_HCTSIZ13 + 0x6b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA13 + OTG_HCDMA13 + 0x6b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB13 + OTG_HCDMAB13 + 0x6bc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR14 + OTG_HCCHAR14 + 0x6c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT14 + OTG_HCSPLT14 + 0x6c4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT14 + OTG_HCINT14 + OTG host channel 14 interrupt register + 0x6c8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK14 + OTG_HCINTMSK14 + OTG host channel 14 interrupt mask register + 0x6cc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ14 + OTG_HCTSIZ14 + 0x6d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA14 + OTG_HCDMA14 + 0x6d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB14 + OTG_HCDMAB14 + 0x6dc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_HCCHAR15 + OTG_HCCHAR15 + 0x6e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +Indicates the maximum packet size of the associated endpoint. + 0 + 11 + read-write + + + EPNUM + Endpoint number +Indicates the endpoint number on the device serving as the data source or sink. + 11 + 4 + read-write + + + EPDIR + Endpoint direction +Indicates whether the transaction is IN or OUT. + 15 + 1 + read-write + + + B_0x0 + OUT + 0x0 + + + B_0x1 + IN + 0x1 + + + + + LSDEV + Low-speed device +This field is set by the application to indicate that this channel is communicating to a low-speed device. + 17 + 1 + read-write + + + EPTYP + Endpoint type +Indicates the transfer type selected. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + MCNT + Multicount +This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used +Note: This field must be set to at least 01. + 20 + 2 + read-write + + + B_0x0 + Reserved. This field yields undefined results + 0x0 + + + B_0x1 + 1 transaction + 0x1 + + + B_0x2 + 2 transactions per frame to be issued for this endpoint + 0x2 + + + B_0x3 + 3 transactions per frame to be issued for this endpoint + 0x3 + + + + + DAD + Device address +This field selects the specific device serving as the data source or sink. + 22 + 7 + read-write + + + ODDFRM + Odd frame +This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. + 29 + 1 + read-write + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + CHDIS + Channel disable +The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. + 30 + 1 + read-write + + + CHENA + Channel enable +When Scatter/Gather mode is enabled: +1'b0: Indicates that the descriptor structure is not yet ready +1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor +When Scatter/Gather mode is disabled: This field is set by the application and cleared by the OTG host. + 31 + 1 + read-write + + + B_0x0 + Channel disabled + 0x0 + + + B_0x1 + Channel enabled + 0x1 + + + + + + + OTG_HCSPLT15 + OTG_HCSPLT15 + 0x6e4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRTADDR + Port address +This field is the port number of the recipient transaction translator. + 0 + 7 + read-write + + + HUBADDR + Hub address +This field holds the device address of the transaction translator's hub. + 7 + 7 + read-write + + + XACTPOS + Transaction position +This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. + 14 + 2 + read-write + + + B_0x3 + All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) + 0x3 + + + B_0x2 + Begin. This is the first data payload of this transaction (which is larger than 188 bytes) + 0x2 + + + B_0x0 + Mid. This is the middle payload of this transaction (which is larger than 188 bytes) + 0x0 + + + B_0x1 + End. This is the last payload of this transaction (which is larger than 188 bytes) + 0x1 + + + + + COMPLSPLT + Do complete split +The application sets this bit to request the OTG host to perform a complete split transaction. + 16 + 1 + read-write + + + SPLITEN + Split enable +The application sets this bit to indicate that this channel is enabled to perform split transactions. + 31 + 1 + read-write + + + + + OTG_HCINT15 + OTG_HCINT15 + OTG host channel 15 interrupt register + 0x6e8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRC + Transfer completed. +Transfer completed normally without any errors. + 0 + 1 + read-write + + + CHH + Channel halted. +In non scatter/gather DMA mode indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. +In scatter/gather DMA mode, this indicates that transfer completed due to any of the following: +EOL being set in descriptor +AHB error +Excessive transaction errors +In response to disable request by the application +Babble +Stall + 1 + 1 + read-write + + + AHBERR + AHB error +This error is generated only in Internal DMA mode when an AHB error occurs during an AHB +read/write operation. The application can read the corresponding DMA channel address +register to get the error address. + 2 + 1 + read-write + + + STALL + STALL response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + NAK + NAK response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + ACK + ACK response received/transmitted interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + NYET + Not yet ready response received interrupt. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + TXERR + Transaction error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. +Indicates one of the following errors occurred on the USB. +CRC check failure +Timeout +Bit stuff error +False EOP + 7 + 1 + read-write + + + BBERR + Babble error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + FRMOR + Frame overrun. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + DTERR + Data toggle error. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + BNA + Buffer not available interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the core to process. BNA interrupt is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 11 + 1 + read-write + + + XCSXACTERR + Excessive transaction error. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR is not generated for isochronous channels. For non Scatter/Gather DMA mode, this bit is reserved. + 12 + 1 + read-write + + + DESCLSTROLL + Descriptor rollover interrupt. +This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel descriptor list rolls over. For non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCINTMSK15 + OTG_HCINTMSK15 + OTG host channel 15 interrupt mask register + 0x6ec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + CHHM + Channel halted mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error. In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in OTG_HCINTx. + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STALLM + STALL response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ACKM + ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYET + response received interrupt mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXERRM + Transaction error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 7 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BBERRM + Babble error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + FRMORM + Frame overrun mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + DTERRM + Data toggle error mask. In Scatter/Gather DMA mode, the interrupt due to this bit is masked. + 10 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAMSK + Buffer not available interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved + 11 + 1 + read-write + + + DESCLSTROLLMSK + Descriptor rollover interrupt mask register. +This bit is valid only when Scatter/Gather DMA mode is enabled. +In non Scatter/Gather DMA mode, this bit is reserved. + 13 + 1 + read-write + + + + + OTG_HCTSIZ15 + OTG_HCTSIZ15 + 0x6f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +For an OUT, this field is the number of data bytes the host sends during the transfer. +For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). + 0 + 19 + read-write + + + PKTCNT + Packet count +This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). +The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. + 19 + 10 + read-write + + + DPID + Data PID +The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + SETUP (control) / MDATA (non-control) + 0x3 + + + + + DOPNG + Do Ping +This bit is used only for OUT transfers. Setting this field to 1 directs the host to do PING protocol. +Note: Do not set this bit for IN transfers. If this bit is set for IN transfers, it disables the channel. + 31 + 1 + read-write + + + + + OTG_HCDMA15 + OTG_HCDMA15 + 0x6f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA address +This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_HCDMAB15 + OTG_HCDMAB15 + 0x6fc + 0x20 + 0x00000000 + 0x00000000 + + + HCDMAB + DMA address +This register holds the current buffer address (scatter/gather mode). + 0 + 32 + read-only + + + + + OTG_DCFG + OTG_DCFG + OTG device configuration register + 0x800 + 0x20 + 0x02200000 + 0xFFFFFFFF + + + DSPD + Device speed +Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. + 0 + 2 + read-write + + + B_0x0 + High speed + 0x0 + + + B_0x1 + Full speed + 0x1 + + + + + NZLSOHSK + Non-zero-length status OUT handshake +The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's status stage. + 2 + 1 + read-write + + + B_0x1 + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. + 0x1 + + + B_0x0 + Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register. + 0x0 + + + + + DAD + Device address +The application must program this field after every SetAddress control command. + 4 + 7 + read-write + + + PFIVL + Periodic frame interval +Indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. This can be used to determine if all the isochronous traffic for that frame is complete. + 11 + 2 + read-write + + + B_0x0 + 80% of the frame interval + 0x0 + + + B_0x1 + 85% of the frame interval + 0x1 + + + B_0x2 + 90% of the frame interval + 0x2 + + + B_0x3 + 95% of the frame interval + 0x3 + + + + + ERRATIM + Erratic error interrupt mask + 15 + 1 + read-write + + + B_0x1 + Mask early suspend interrupt on erratic error + 0x1 + + + B_0x0 + Early suspend interrupt is generated on erratic error + 0x0 + + + + + DESCDMA + Enable scatter/gather DMA in device mode +The application can set this bit during initialization to enable the Scatter/Gather DMA operation. This bit must be modified only once after a reset. The following combinations are available for programming: +OTG_GAHBCFG.DMAEN=0,OTG_DCFG.DESCDMA=0 => Slave mode +OTG_GAHBCFG.DMAEN=0,OTG_DCFG.DESCDMA=1 => Invalid +OTG_GAHBCFG.DMAEN=1,OTG_DCFG.DESCDMA=0 => Buffer DMA mode +OTG_GAHBCFG.DMAEN=1,OTG_DCFG.DESCDMA=1 => Scatter/Gather DMA mode + 23 + 1 + read-write + + + PERSCHIVL + Periodic schedule interval +This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25, 50 or 75% of the (micro) frame. +When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data +When no periodic endpoint is active, then the internal DMA engine services nonperiodic endpoints, ignoring this field +After the specified time within a (micro) frame, the DMA switches to fetching nonperiodic endpoints +Note: Periodic Scheduling Interval (PERSCHIVL) must be programmed for Scatter/Gather DMA mode. + 24 + 2 + read-write + + + B_0x0 + 25% of (micro)frame + 0x0 + + + B_0x1 + 50% of (micro)frame + 0x1 + + + B_0x2 + 75% of (micro)frame + 0x2 + + + + + + + OTG_DCTL + OTG_DCTL + 0x804 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + RWUSIG + Remote wakeup signaling +When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. +If LPM is enabled and the core is in the L1 (sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 µs (TL1DevDrvResume) after being set by the application. The application must not set this bit when bRemoteWake from the previous LPM transaction is zero (refer to REMWAKE bit in GLPMCFG register). + 0 + 1 + read-write + + + SDIS + Soft disconnect +The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. + 1 + 1 + read-write + + + B_0x0 + Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. + 0x0 + + + B_0x1 + The core generates a device disconnect event to the USB host. + 0x1 + + + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + B_0x0 + A handshake is sent out based on the data availability in the transmit FIFO. + 0x0 + + + B_0x1 + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + 0x1 + + + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + B_0x0 + A handshake is sent based on the FIFO status and the NAK and STALL bit settings. + 0x0 + + + B_0x1 + No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + 0x1 + + + + + TCTL + Test control +Others: Reserved + 4 + 3 + read-write + + + B_0x0 + Test mode disabled + 0x0 + + + B_0x1 + Test_J mode + 0x1 + + + B_0x2 + Test_K mode + 0x2 + + + B_0x3 + Test_SE0_NAK mode + 0x3 + + + B_0x4 + Test_Packet mode + 0x4 + + + B_0x5 + Test_Force_Enable + 0x5 + + + + + SGINAK + Set global IN NAK +Writing 1 to this field sets the Global non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. +The application must set this bit only after making sure that the Global IN NAK effective bit in the core interrupt register (GINAKEFF bit in OTG_GINTSTS) is cleared. + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK +Writing 1 to this field clears the Global IN NAK. + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK +Writing 1 to this field sets the Global OUT NAK. +The application uses this bit to send a NAK handshake on all OUT endpoints. +The application must set the this bit only after making sure that the Global OUT NAK effective bit in the core interrupt register (GONAKEFF bit in OTG_GINTSTS) is cleared. + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK +Writing 1 to this field clears the Global OUT NAK. + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done +The application uses this bit to indicate that register programming is completed after a wakeup from power down mode. + 11 + 1 + read-write + + + ENCONTONBNA + Enable continue on BNA +This bit enables the core to continue on BNA for Bulk OUT and INTR OUT endpoints. With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA interrupt the core starts processing the descriptor that caused the BNA interrupt after the endpoint re-enables the endpoint. + 17 + 1 + read-write + + + B_0x0 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. + 0x0 + + + B_0x1 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt. It is a one-time programmable after reset bit like any other OTG_DCTL register bit. + 0x1 + + + + + DSBESLRJCT + Deep sleep BESL reject +Core rejects LPM request with BESL value greater than BESL threshold programmed. NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By default, the deep sleep BESL reject feature is disabled. + 18 + 1 + read-write + + + + + OTG_DSTS + OTG_DSTS + OTG device status register + 0x808 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + SUSPSTS + Suspend status +In device mode, this bit is set as long as a suspend condition is detected on the USB. The core enters the suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend: +When there is an activity on the USB data lines +When the application writes to the remote wakeup signaling bit in the OTG_DCTL register (RWUSIG bit in OTG_DCTL). + 0 + 1 + read-only + + + ENUMSPD + Enumerated speed +Indicates the speed at which the OTG controller has come up after speed detection through a chirp sequence. +Others: reserved + 1 + 2 + read-only + + + B_0x0 + High Speed + 0x0 + + + B_0x1 + Full Speed + 0x1 + + + + + EERR + Erratic error +The core sets this bit to report any erratic errors. +Due to erratic errors, the OTG controller goes into suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. + 3 + 1 + read-only + + + FNSOF + Frame number of the received SOF + 8 + 14 + read-only + + + DEVLNSTS + Device line status +Indicates the current logic level USB data lines. +Bit [23]: Logic level of D+ +Bit [22]: Logic level of D- + 22 + 2 + read-only + + + + + OTG_DIEPMSK + OTG_DIEPMSK + OTG device IN endpoint common interrupt mask register + 0x810 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error mask + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TOM + Timeout condition mask (Non-isochronous endpoints) + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + ITTXFEMSK + IN token received when Tx FIFO empty mask + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + INEPNMM + IN token received with EP mismatch mask + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + INEPNEM + IN endpoint NAK effective mask + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + TXFURM + FIFO underrun mask + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAM + BNA interrupt mask + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKM + NAK interrupt mask + 13 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_DOEPMSK + OTG_DOEPMSK + OTG device OUT endpoint common interrupt mask register + 0x814 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + AHBERRM + AHB error mask + 2 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STUPM + STUPM: SETUP phase done mask. Applies to control endpoints only. + 3 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + OTEPDM + OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. + 4 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + STSPHSRXM + Status phase received for control write mask + 5 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + B2BSTUPM + Back-to-back SETUP packets received mask +Applies to control OUT endpoints only. + 6 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + OUTPKTERRM + Out packet error mask + 8 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BNAM + BNA interrupt mask + 9 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + BERRM + Babble error interrupt mask + 12 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NAKMSK + NAK interrupt mask + 13 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + NYETMSK + NYET interrupt mask + 14 + 1 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_DAINT + OTG_DAINT + OTG device all endpoints interrupt register + 0x818 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IEPINT + IN endpoint interrupt bits +One bit per IN endpoint: +Bit 0 for IN endpoint 0, bit 3 for endpoint 3. + 0 + 16 + read-only + + + OEPINT + OUT endpoint interrupt bits +One bit per OUT endpoint: +Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. + 16 + 16 + read-only + + + + + OTG_DAINTMSK + OTG_DAINTMSK + OTG all endpoints interrupt mask register + 0x81c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IEPM + IN EP interrupt mask bits +One bit per IN endpoint: +Bit 0 for IN EP 0, bit 3 for IN EP 3 + 0 + 16 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + OEPM + OUT EP interrupt mask bits +One per OUT endpoint: +Bit 16 for OUT EP 0, bit 19 for OUT EP 3 + 16 + 16 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_DVBUSDIS + OTG_DVBUSDIS + OTG device VBUS discharge time register + 0x828 + 0x20 + 0x000017D7 + 0xFFFFFFFF + + + VBUSDT + Device VBUS discharge time +Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals: +VBUS discharge time in PHY clocks / 1 024 +Depending on your VBUS load, this value may need adjusting. + 0 + 16 + read-write + + + + + OTG_DVBUSPULSE + OTG_DVBUSPULSE + OTG device VBUS pulsing time register + 0x82c + 0x20 + 0x000005B8 + 0xFFFFFFFF + + + DVBUSP + Device VBUS pulsing time. This feature is only relevant to OTG1.3. +Specifies the VBUS pulsing time during SRP. This value equals: +VBUS pulsing time in PHY clocks / 1 024 + 0 + 16 + read-write + + + + + OTG_DTHRCTL + OTG_DTHRCTL + 0x830 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NONISOTHREN + Nonisochronous IN endpoints threshold enable +When this bit is set, the core enables thresholding for nonisochronous IN endpoints. + 0 + 1 + read-write + + + ISOTHREN + ISO IN endpoint threshold enable +When this bit is set, the core enables thresholding for isochronous IN endpoints. + 1 + 1 + read-write + + + TXTHRLEN + Transmit threshold length +This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). + 2 + 9 + read-write + + + RXTHREN + Receive threshold enable +When this bit is set, the core enables thresholding in the receive direction. + 16 + 1 + read-write + + + RXTHRLEN + Receive threshold length +This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). + 17 + 9 + read-write + + + ARPEN + Arbiter parking enable +This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. + 27 + 1 + read-write + + + + + OTG_DIEPEMPMSK + OTG_DIEPEMPMSK + OTG device IN endpoint FIFO empty interrupt mask register + 0x834 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask bits +These bits act as mask bits for OTG_DIEPINTx. +TXFE interrupt one bit per IN endpoint: +Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 + 0 + 16 + read-write + + + B_0x0 + Masked interrupt + 0x0 + + + B_0x1 + Unmasked interrupt + 0x1 + + + + + + + OTG_DIEPCTL0 + OTG_DIEPCTL0 + OTG device IN endpoint 0 control register + 0x900 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT0 + OTG_DIEPINT0 + OTG device IN endpoint 0 interrupt register + 0x908 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ0 + OTG_DIEPTSIZ0 + OTG device IN endpoint 0 transfer size register + 0x910 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 7 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for endpoint 0. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 2 + read-write + + + + + OTG_DIEPDMA0 + OTG_DIEPDMA0 + 0x914 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS0 + OTG_DTXFSTS0 + OTG device IN endpoint transmit FIFO status register + 0x918 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL1 + OTG_DIEPCTL1 + OTG device IN endpoint 1 control register + 0x920 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT1 + OTG_DIEPINT1 + OTG device IN endpoint 1 interrupt register + 0x928 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ1 + OTG_DIEPTSIZ1 + OTG device IN endpoint 1 transfer size register + 0x930 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA1 + OTG_DIEPDMA1 + 0x934 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS1 + OTG_DTXFSTS1 + OTG device IN endpoint transmit FIFO status register + 0x938 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL2 + OTG_DIEPCTL2 + OTG device IN endpoint 2 control register + 0x940 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT2 + OTG_DIEPINT2 + OTG device IN endpoint 2 interrupt register + 0x948 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ2 + OTG_DIEPTSIZ2 + OTG device IN endpoint 2 transfer size register + 0x950 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA2 + OTG_DIEPDMA2 + 0x954 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS2 + OTG_DTXFSTS2 + OTG device IN endpoint transmit FIFO status register + 0x958 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL3 + OTG_DIEPCTL3 + OTG device IN endpoint 3 control register + 0x960 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT3 + OTG_DIEPINT3 + OTG device IN endpoint 3 interrupt register + 0x968 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ3 + OTG_DIEPTSIZ3 + OTG device IN endpoint 3 transfer size register + 0x970 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA3 + OTG_DIEPDMA3 + 0x974 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS3 + OTG_DTXFSTS3 + OTG device IN endpoint transmit FIFO status register + 0x978 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL4 + OTG_DIEPCTL4 + OTG device IN endpoint 4 control register + 0x980 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT4 + OTG_DIEPINT4 + OTG device IN endpoint 4 interrupt register + 0x988 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ4 + OTG_DIEPTSIZ4 + OTG device IN endpoint 4 transfer size register + 0x990 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA4 + OTG_DIEPDMA4 + 0x994 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS4 + OTG_DTXFSTS4 + OTG device IN endpoint transmit FIFO status register + 0x998 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL5 + OTG_DIEPCTL5 + OTG device IN endpoint 5 control register + 0x9a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT5 + OTG_DIEPINT5 + OTG device IN endpoint 5 interrupt register + 0x9a8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ5 + OTG_DIEPTSIZ5 + OTG device IN endpoint 5 transfer size register + 0x9b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA5 + OTG_DIEPDMA5 + 0x9b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS5 + OTG_DTXFSTS5 + OTG device IN endpoint transmit FIFO status register + 0x9b8 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL6 + OTG_DIEPCTL6 + OTG device IN endpoint 6 control register + 0x9c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT6 + OTG_DIEPINT6 + OTG device IN endpoint 6 interrupt register + 0x9c8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ6 + OTG_DIEPTSIZ6 + OTG device IN endpoint 6 transfer size register + 0x9d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA6 + OTG_DIEPDMA6 + 0x9d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS6 + OTG_DTXFSTS6 + OTG device IN endpoint transmit FIFO status register + 0x9d8 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL7 + OTG_DIEPCTL7 + OTG device IN endpoint 7 control register + 0x9e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT7 + OTG_DIEPINT7 + OTG device IN endpoint 7 interrupt register + 0x9e8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ7 + OTG_DIEPTSIZ7 + OTG device IN endpoint 7 transfer size register + 0x9f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA7 + OTG_DIEPDMA7 + 0x9f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS7 + OTG_DTXFSTS7 + OTG device IN endpoint transmit FIFO status register + 0x9f8 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DIEPCTL8 + OTG_DIEPCTL8 + OTG device IN endpoint 8 control register + 0xa00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + EONUM + Even/odd frame +Applies to isochronous IN endpoints only. The alternate description that applies for interrupt/bulk IN endpoint only is defined in next paragraph +Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. + 16 + 1 + read-only + + + B_0x0 + Even frame + 0x0 + + + B_0x1 + Odd frame + 0x1 + + + + + NAKSTS + NAK status +It indicates the following: +When either the application or the core sets this bit: +For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. +For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + STALL + STALL handshake +Applies to non-control, non-isochronous IN endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. + 21 + 1 + read-write + + + TXFNUM + Tx FIFO number +These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. +This field is valid only for IN endpoints. + 22 + 4 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SEVNFRM + Set even frame +Applies to isochronous IN endpoints only. The alternate description for interrupt/bluk IN endpoint is defined in the next paragraph +Writing to this field sets the Even/Odd frame (EONUM) field to even frame. + 28 + 1 + write-only + + + SODDFRM + Set odd frame +Applies to isochronous IN and OUT endpoints only. +Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DIEPINT8 + OTG_DIEPINT8 + OTG device IN endpoint 8 interrupt register + 0xa08 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + TOC + Timeout condition +Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. + 3 + 1 + read-write + + + ITTXFE + IN token received when Tx FIFO is empty +Indicates that an IN token was received when the associated Tx FIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. + 4 + 1 + read-write + + + INEPNM + IN token received with EP mismatch +Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. + 5 + 1 + read-write + + + INEPNE + IN endpoint NAK effective +This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. +This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. +This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty +This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun (TxfifoUndrn) +The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status +This bit indicates to the application that an ISOC OUT packet has been dropped. This bit +does not have an associated mask bit and does not generate an interrupt. + 11 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ8 + OTG_DIEPTSIZ8 + OTG device IN endpoint 8 transfer size register + 0xa10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet from the external memory is written to the Tx FIFO. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. + 19 + 10 + read-write + + + MCNT + Multi count +For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DIEPDMA8 + OTG_DIEPDMA8 + 0xa14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DTXFSTS8 + OTG_DTXFSTS8 + OTG device IN endpoint transmit FIFO status register + 0xa18 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + INEPTFSAV + IN endpoint Tx FIFO space available +Indicates the amount of free space available in the endpoint Tx FIFO. +Values are in terms of 32-bit words: +0xn: n words available +Others: Reserved + 0 + 16 + read-only + + + B_0x0 + Endpoint Tx FIFO is full + 0x0 + + + B_0x1 + 1 word available + 0x1 + + + B_0x2 + 2 words available + 0x2 + + + + + + + OTG_DOEPCTL0 + OTG_DOEPCTL0 + OTG device control OUT endpoint 0 control register + 0xb00 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0. + 0 + 2 + read-only + + + B_0x0 + 64 bytes + 0x0 + + + B_0x1 + 32 bytes + 0x1 + + + B_0x2 + 16 bytes + 0x2 + + + B_0x3 + 8 bytes + 0x3 + + + + + USBAEP + USB active endpoint +This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. + 15 + 1 + read-only + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit, the core stops receiving data, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +Hardcoded to 2'b00 for control. + 18 + 2 + read-only + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + EPDIS + Endpoint disable +The application cannot disable control OUT endpoint 0. + 30 + 1 + read-only + + + EPENA + Endpoint enable +The application sets this bit to start transmitting data on endpoint 0. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + write-only + + + + + OTG_DOEPINT0 + OTG_DOEPINT0 + OTG device OUT endpoint 0 interrupt register + 0xb08 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ0 + OTG_DOEPTSIZ0 + OTG device OUT endpoint 0 transfer size register + 0xb10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 7 + read-write + + + PKTCNT + Packet count +This field is decremented to zero after a packet is written into the Rx FIFO. + 19 + 1 + read-write + + + STUPCNT + SETUP packet count +This field specifies the number of back-to-back SETUP data packets the endpoint can receive. + 29 + 2 + read-write + + + B_0x1 + 1 packet + 0x1 + + + B_0x2 + 2 packets + 0x2 + + + B_0x3 + 3 packets + 0x3 + + + + + + + OTG_DOEPDMA0 + OTG_DOEPDMA0 + 0xb14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL1 + OTG_DOEPCTL1 + OTG device OUT endpoint 1 control register + 0xb20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT1 + OTG_DOEPINT1 + OTG device OUT endpoint 1 interrupt register + 0xb28 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ1 + OTG_DOEPTSIZ1 + OTG device OUT endpoint 1 transfer size register + 0xb30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA1 + OTG_DOEPDMA1 + 0xb34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL2 + OTG_DOEPCTL2 + OTG device OUT endpoint 2 control register + 0xb40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT2 + OTG_DOEPINT2 + OTG device OUT endpoint 2 interrupt register + 0xb48 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ2 + OTG_DOEPTSIZ2 + OTG device OUT endpoint 2 transfer size register + 0xb50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA2 + OTG_DOEPDMA2 + 0xb54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL3 + OTG_DOEPCTL3 + OTG device OUT endpoint 3 control register + 0xb60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT3 + OTG_DOEPINT3 + OTG device OUT endpoint 3 interrupt register + 0xb68 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ3 + OTG_DOEPTSIZ3 + OTG device OUT endpoint 3 transfer size register + 0xb70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA3 + OTG_DOEPDMA3 + 0xb74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL4 + OTG_DOEPCTL4 + OTG device OUT endpoint 4 control register + 0xb80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT4 + OTG_DOEPINT4 + OTG device OUT endpoint 4 interrupt register + 0xb88 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ4 + OTG_DOEPTSIZ4 + OTG device OUT endpoint 4 transfer size register + 0xb90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA4 + OTG_DOEPDMA4 + 0xb94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL5 + OTG_DOEPCTL5 + OTG device OUT endpoint 5 control register + 0xba0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT5 + OTG_DOEPINT5 + OTG device OUT endpoint 5 interrupt register + 0xba8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ5 + OTG_DOEPTSIZ5 + OTG device OUT endpoint 5 transfer size register + 0xbb0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA5 + OTG_DOEPDMA5 + 0xbb4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL6 + OTG_DOEPCTL6 + OTG device OUT endpoint 6 control register + 0xbc0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT6 + OTG_DOEPINT6 + OTG device OUT endpoint 6 interrupt register + 0xbc8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ6 + OTG_DOEPTSIZ6 + OTG device OUT endpoint 6 transfer size register + 0xbd0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA6 + OTG_DOEPDMA6 + 0xbd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL7 + OTG_DOEPCTL7 + OTG device OUT endpoint 7 control register + 0xbe0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT7 + OTG_DOEPINT7 + OTG device OUT endpoint 7 interrupt register + 0xbe8 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ7 + OTG_DOEPTSIZ7 + OTG device OUT endpoint 7 transfer size register + 0xbf0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA7 + OTG_DOEPDMA7 + 0xbf4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_DOEPCTL8 + OTG_DOEPCTL8 + OTG device OUT endpoint 8 control register + 0xc00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MPSIZ + Maximum packet size +The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. + 0 + 11 + read-write + + + USBAEP + USB active endpoint +Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + 15 + 1 + read-write + + + DPID + Endpoint data PID +Applies to interrupt/bulk OUT endpoints only. +Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. + 16 + 1 + read-only + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA1 + 0x1 + + + + + NAKSTS + NAK status +Indicates the following: +When either the application or the core sets this bit: +The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. +Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 17 + 1 + read-only + + + B_0x0 + The core is transmitting non-NAK handshakes based on the FIFO status. + 0x0 + + + B_0x1 + The core is transmitting NAK handshakes on this endpoint. + 0x1 + + + + + EPTYP + Endpoint type +This is the transfer type supported by this logical endpoint. + 18 + 2 + read-write + + + B_0x0 + Control + 0x0 + + + B_0x1 + Isochronous + 0x1 + + + B_0x2 + Bulk + 0x2 + + + B_0x3 + Interrupt + 0x3 + + + + + SNPM + Snoop mode +This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. + 20 + 1 + read-write + + + STALL + STALL handshake +Applies to non-control, non-isochronous OUT endpoints only (access type is rw). +The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. +Applies to control endpoints only (access type is rs). +The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + 21 + 1 + read-write + + + CNAK + Clear NAK +A write to this bit clears the NAK bit for the endpoint. + 26 + 1 + write-only + + + SNAK + Set NAK +A write to this bit sets the NAK bit for the endpoint. +Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a transfer completed interrupt, or after a SETUP is received on the endpoint. + 27 + 1 + write-only + + + SD0PID + Set DATA0 PID +Applies to interrupt/bulk OUT endpoints only. +Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. + 28 + 1 + write-only + + + SD1PID + Set DATA1 PID +Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. + 29 + 1 + write-only + + + EPDIS + Endpoint disable +The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. + 30 + 1 + read-write + + + EPENA + Endpoint enable +Applies to IN and OUT endpoints. +The application sets this bit to start transmitting data on an endpoint. +The core clears this bit before setting any of the following interrupts on this endpoint: +SETUP phase done +Endpoint disabled +Transfer completed + 31 + 1 + read-write + + + + + OTG_DOEPINT8 + OTG_DOEPINT8 + OTG device OUT endpoint 8 interrupt register + 0xc08 + 0x20 + 0x00000080 + 0xFFFFFFFF + + + XFRC + Transfer completed interrupt +This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt +This bit indicates that the endpoint is disabled per the application's request. + 1 + 1 + read-write + + + AHBERR + AHB error +This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. + 2 + 1 + read-write + + + STUP + SETUP phase done +Applies to control OUT endpoint only.Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. + 3 + 1 + read-write + + + OTEPDIS + OUT token received when endpoint disabled +Applies only to control OUT endpoints. +Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. + 4 + 1 + read-write + + + STSPHSRX + Status phase received for control write +This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. + 5 + 1 + read-write + + + B2BSTUP + Back-to-back SETUP packets received +Applies to control OUT endpoint only. +This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. + 6 + 1 + read-write + + + OUTPKTERR + OUT packet error +This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. + 8 + 1 + read-write + + + BNA + Buffer not available interrupt +The core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or DMA done. +This bit is only valid when Scatter/Gather DMA mode is enabled. + 9 + 1 + read-write + + + BERR + Babble error interrupt +The core generates this interrupt when babble is received for the endpoint. + 12 + 1 + read-write + + + NAK + NAK input +The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is +transmitted due to unavailability of data in the Tx FIFO. + 13 + 1 + read-write + + + NYET + NYET interrupt +This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. + 14 + 1 + read-write + + + STPKTRX + Setup packet received +Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG can receive any number of back to back setup packets and one buffer for every setup packet is used. + 15 + 1 + read-write + + + + + OTG_DOEPTSIZ8 + OTG_DOEPTSIZ8 + OTG device OUT endpoint 8 transfer size register + 0xc10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + XFRSIZ + Transfer size +This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. +The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. + 0 + 19 + read-write + + + PKTCNT + Packet count +Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. +This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. + 19 + 10 + read-write + + + RXDPID + Received data PID +Applies to isochronous OUT endpoints only. Control OUT endpoints only description is defined at the next paragraph. +This is the data PID received in the last packet for this endpoint. + 29 + 2 + read-write + + + B_0x0 + DATA0 + 0x0 + + + B_0x1 + DATA2 + 0x1 + + + B_0x2 + DATA1 + 0x2 + + + B_0x3 + MDATA + 0x3 + + + + + + + OTG_DOEPDMA8 + OTG_DOEPDMA8 + 0xc14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAADDR + DMA Address +This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. + 0 + 32 + read-write + + + + + OTG_PCGCCTL + OTG_PCGCCTL + OTG power and clock gating control register + 0xe00 + 0x20 + 0x200B8000 + 0xFFFFFFFF + + + STPPCLK + Stop PHY clock +The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. + 0 + 1 + read-write + + + GATEHCLK + Gate HCLK +The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. + 1 + 1 + read-write + + + PHYSUSP + PHY suspended +Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit. + 4 + 1 + read-only + + + ENL1GTG + Enable sleep clock gating +When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. + 5 + 1 + read-write + + + PHYSLEEP + PHY in Sleep +This bit indicates that the PHY is in the Sleep state. + 6 + 1 + read-only + + + SUSP + Deep Sleep +This bit indicates that the PHY is in Deep Sleep when in L1 state. + 7 + 1 + read-only + + + + + + + PKA + PKA + PKA + 0x54006000 + + 0x0 + 0x2000 + registers + + + PKA + PKA interrupt + 105 + + + + PKA_CR + PKA_CR + PKA control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + PKA enable. +When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. +When EN=0 PKA RAM can still be accessed by the application. + 0 + 1 + read-write + + + B_0x0 + Disable PKA + 0x0 + + + B_0x1 + Enable PKA.PKA becomes functional when INITOK is set by hardware in PKA_SR. + 0x1 + + + + + START + start the operation +Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. +When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. +START is ignored if PKA is busy. + 1 + 1 + read-write + + + MODE + PKA operation code +When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. +When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + 8 + 6 + read-write + + + B_0x0 + Montgomery parameter computation then modular exponentiation + 0x0 + + + B_0x1 + Montgomery parameter computation only + 0x1 + + + B_0x2 + Modular exponentiation only (Montgomery parameter must be loaded first) + 0x2 + + + B_0x3 + Modular exponentiation (protected, used when manipulating secrets) + 0x3 + + + B_0x20 + Montgomery parameter computation then ECC scalar multiplication + 0x20 + + + B_0x24 + ECDSA sign + 0x24 + + + B_0x26 + ECDSA verification + 0x26 + + + B_0x28 + Point on elliptic curve Fp check + 0x28 + + + B_0x7 + RSA CRT exponentiation + 0x7 + + + B_0x8 + Modular inversion + 0x8 + + + B_0x9 + Arithmetic addition + 0x9 + + + B_0xA + Arithmetic subtraction + 0xA + + + B_0xB + Arithmetic multiplication + 0xB + + + B_0xC + Arithmetic comparison + 0xC + + + B_0xD + Modular reduction + 0xD + + + B_0xE + Modular addition + 0xE + + + B_0xF + Modular subtraction + 0xF + + + B_0x10 + Montgomery multiplication + 0x10 + + + B_0x23 + ECC complete addition + 0x23 + + + B_0x27 + ECC double base ladder + 0x27 + + + B_0x2F + ECC projective to affine + 0x2F + + + + + PROCENDIE + End of operation interrupt enable + 17 + 1 + read-write + + + B_0x0 + No interrupt is generated when PROCENDF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when PROCENDF flag is set in PKA_SR. + 0x1 + + + + + RAMERRIE + RAM error interrupt enable + 19 + 1 + read-write + + + B_0x0 + No interrupt is generated when RAMERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when RAMERRF flag is set in PKA_SR. + 0x1 + + + + + ADDRERRIE + Address error interrupt enable + 20 + 1 + read-write + + + B_0x0 + No interrupt is generated when ADDRERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when ADDRERRF flag is set in PKA_SR. + 0x1 + + + + + OPERRIE + Operation error interrupt enable + 21 + 1 + read-write + + + B_0x0 + No interrupt is generated when OPERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when OPERRF flag is set in PKA_SR. + 0x1 + + + + + + + PKA_SR + PKA_SR + PKA status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + INITOK + PKA initialization OK +This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + 0 + 1 + read-only + + + B_0x0 + PKA is not initialized correctly. START bit cannot be set. + 0x0 + + + B_0x1 + PKA is initialized correctly and can be used normally. + 0x1 + + + + + LMF + Limited mode flag +This bit is updated when EN bit in PKA_CR is set + 1 + 1 + read-only + + + B_0x0 + All values documented in MODE bitfield can be used. + 0x0 + + + B_0x1 + Only ECDSA verification (MODE = 0x26) is supported by the PKA. + 0x1 + + + + + BUSY + PKA operation is in progress +This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. +If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + 16 + 1 + read-only + + + B_0x0 + No operation is in progress (default) + 0x0 + + + B_0x1 + An operation is in progress + 0x1 + + + + + PROCENDF + PKA End of Operation flag + 17 + 1 + read-only + + + B_0x0 + Operation in progress + 0x0 + + + B_0x1 + PKA operation is completed. This flag is set when the BUSY bit is deasserted. + 0x1 + + + + + RAMERRF + PKA RAM error flag +This bit is cleared using RAMERRFC bit in PKA_CLRFR. + 19 + 1 + read-only + + + B_0x0 + No PKA RAM access error + 0x0 + + + B_0x1 + An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). + 0x1 + + + + + ADDRERRF + Address error flag +This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + 20 + 1 + read-only + + + B_0x0 + No address error + 0x0 + + + B_0x1 + Address access is out of range (unmapped address) + 0x1 + + + + + OPERRF + Operation error flag +This bit is cleared using OPERRFC bit in PKA_CLRFR. + 21 + 1 + read-only + + + B_0x0 + No event error + 0x0 + + + B_0x1 + An illegal or unknown operation has been selected in PKA_CR register + 0x1 + + + + + + + PKA_CLRFR + PKA_CLRFR + PKA clear flag register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PROCENDFC + Clear PKA End of Operation flag + 17 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the PROCENDF flag in PKA_SR + 0x1 + + + + + RAMERRFC + Clear PKA RAM error flag + 19 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the RAMERRF flag in PKA_SR + 0x1 + + + + + ADDRERRFC + Clear address error flag + 20 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the ADDRERRF flag in PKA_SR + 0x1 + + + + + OPERRFC + Clear operation error flag + 21 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the OPERRF flag in PKA_SR + 0x1 + + + + + + + PKA_HWCFGR + PKA_HWCFGR + PKA hardware configuration register + 0x1ff0 + 0x20 + 0x00000011 + 0xFFFFFFFF + + + CFG1 + HW Generic 2 +This field returns the PKA64_SEL generic value (0x1) + 0 + 4 + read-only + + + CFG2 + HW Generic 2 +This field returns the DPAEN generic value (0x1) + 4 + 4 + read-only + + + + + PKA_VERR + PKA_VERR + PKA version register + 0x1ff4 + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MINREV + Minor revision +This field returns the PKA minor version. + 0 + 4 + read-only + + + MAJREV + Major revision +This field returns the PKA major version. + 4 + 4 + read-only + + + + + PKA_IPIDR + PKA_IPIDR + PKA identification register + 0x1ff8 + 0x20 + 0x00170072 + 0xFFFFFFFF + + + ID + Identification Code +This field returns the PKA identification code. + 0 + 32 + read-only + + + + + PKA_SIDR + PKA_SIDR + PKA size ID register + 0x1ffc + 0x20 + 0xA3C5DD08 + 0xFFFFFFFF + + + SID + Size Identification Code +This field returns the size identification code of the PKA as defined below: +Bits[31:8] = 0xA3C5DD (fixed code) +Bits[7:0] = 0x08 (8 KB address decoding) + 0 + 32 + read-only + + + + + + + PWR + PWR + PWR + 0x50001000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + PWR control register 1 + 0x0 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + LPDS + Low Power Deepsleep Stop mode selection. + 0 + 1 + read-write + + + B_0x0 + Stop mode selected, External regulator kept in Main power mode (pwr_lp = 1). + 0x0 + + + B_0x1 + low-power stop mode selected External regulator may enter Low-power mode (pwr_lp = 0). Further low power mode selection is provided by LVDS. + 0x1 + + + + + LPCFG + PWR_ON pin configuration. + 1 + 1 + read-write + + + B_0x0 + PWR_ON pin signals Standby mode (PWR_ON =1 in Run, Stop, LP-Stop, LPLV-Stop, LPLV-Stop2 and 0 in Standby). + 0x0 + + + B_0x1 + PWR_ON pin signals Standby, LP-Stop, LPLV-Stop and LPLV-Stop2 modes (PWR_ON = 1 in Run, Stop, and 0 in LP-Stop, LPLV-Stop, LPLV-Stop2 and Standby). + 0x1 + + + + + LVDS + Low Voltage Deepsleep LPLV-Stop mode selection. +This bit has only effect when the low power stop mode is selected in LPDS and changes the VDDCORE and VDDCPU domains supply reset level. + 2 + 1 + read-write + + + B_0x0 + LP-Stop mode VDDCORE and VDDCPU domains supply reset level at same level as Run mode. The VDDCORE and VDDCPU domains supply level in LP-Stop mode must be kept at same level as Run mode. + 0x0 + + + B_0x1 + LPLV-Stop mode VDDCORE and VDDCPU domains supply reset level at lower level than Run mode. Allows to lower VDDCORE and VDDCPU domains supply level in LPLV-Stop mode (see the datasheet for voltage levels). + 0x1 + + + + + STOP2 + System LPLV-Stop2 mode selection + 3 + 1 + read-write + + + B_0x0 + Keeps System Stop mode when PDDS=0 and MPU enters CStop + 0x0 + + + B_0x1 + Allows System LPLV-Stop2 mode when PDDS = 0 + 0x1 + + + + + PVDEN + Programmable Voltage detector enable. +This bit is read only when the SYSCFG register bit PVDL is set (when PVDL is set, there is no bus errors generated when writing this register). + 4 + 1 + read-write + + + B_0x0 + Programmable Voltage detector disabled. + 0x0 + + + B_0x1 + Programmable Voltage detector enabled. + 0x1 + + + + + PLS + Programmable Voltage Detector level selection. +These bits are read only when the SYSCFG register bit PVDL is set (when PVDL is set, there is no bus errors generated when writing this register). +These bits select the voltage threshold detected by the PVD. + 5 + 3 + read-write + + + B_0x0 + 1.95 V + 0x0 + + + B_0x1 + 2.1 V + 0x1 + + + B_0x2 + 2.25 V + 0x2 + + + B_0x3 + 2.4 V + 0x3 + + + B_0x4 + 2.55 V + 0x4 + + + B_0x5 + 2.7 V + 0x5 + + + B_0x6 + 2.85 V + 0x6 + + + B_0x7 + External voltage level on PVD_IN (compared to internal VREFINT) + 0x7 + + + + + DBP + Disable backup domain write protection. +In reset state, the RCC_BDCR, PWR_CR2, RTC, and backup registers are protected against parasitic write access. This bit must be set to enable write access to these. + 8 + 1 + read-write + + + B_0x0 + Write access to RTC and backup domain registers disabled. + 0x0 + + + B_0x1 + Write access to RTC and backup domain registers enabled. + 0x1 + + + + + MPU_RAM_LOWSPEED + Low speed selection for MPU memories +This bit must be reset by software when MPU needs to operate in Overdrive (High speed) mode +It must be set after decreasing the MPU frequency to operate in standard frequency range. + 9 + 1 + read-write + + + B_0x0 + MPU can operate in High speed mode (VDDCPU > 1.2V) + 0x0 + + + B_0x1 + MPU can only operate in Low speed mode (VDDCPU ≤ 1.2 V) + 0x1 + + + + + AVDEN + Peripheral Voltage Monitor on VDDA enable. + 16 + 1 + read-write + + + B_0x0 + Peripheral Voltage Monitor on VDDA disabled + 0x0 + + + B_0x1 + Peripheral Voltage Monitor on VDDA enabled + 0x1 + + + + + ALS + Analog Voltage Detector level selection. +These bits select the voltage threshold detected by the AVD. + 17 + 2 + read-write + + + B_0x0 + 1.7V + 0x0 + + + B_0x1 + 2.1V + 0x1 + + + B_0x2 + 2.5V + 0x2 + + + B_0x3 + 2.8V + 0x3 + + + + + + + PWR_CSR1 + PWR_CSR1 + PWR control status register 1 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDO + Programmable Voltage Detect Output +This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDEN bit. +Note: The PVD is disabled in Standby mode and after a system reset. For this reason, this bit is equal to 0 after Standby and system reset. + 4 + 1 + read-only + + + B_0x0 + VDD or voltage level on PVD_IN is equal or higher than the PVD threshold selected with the PLS[2:0] bits. + 0x0 + + + B_0x1 + VDD or voltage level on PVD_IN is lower than the PVD threshold selected with the PLS[2:0] bits. + 0x1 + + + + + AVDO + Analog Voltage detector Output on VDDA. +This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. +Note: The AVD is disabled in Standby mode and after system reset. For this reason, this bit is equal to 0 after Standby and reset. + 16 + 1 + read-only + + + B_0x0 + VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + 0x0 + + + B_0x1 + VDDA is lower than the AVD threshold selected with the ALS[2:0] bits + 0x1 + + + + + + + PWR_CR2 + PWR_CR2 + PWR control register 2 + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BREN + Backup regulator enable +When set, the backup regulator (used to maintain backup RAM content in Standby and VBAT modes) is enabled. +If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run mode and Stop mode but its content is lost in the Standby and VBAT modes. Once set, the application must wait that the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in the Standby and VBAT modes. + 0 + 1 + read-write + + + B_0x0 + Backup regulator disabled + 0x0 + + + B_0x1 + Backup regulator enabled + 0x1 + + + + + MONEN + VBAT and temperature monitoring enable +When set, the VBAT supply and temperature monitoring is enabled. + 4 + 1 + read-write + + + B_0x0 + VBAT and temperature monitoring disabled. + 0x0 + + + B_0x1 + VBAT and temperature monitoring enabled. + 0x1 + + + + + BRRDY + Backup Regulator ready +Set by hardware to indicate that the Backup Regulator is ready. Entering Standby or VBAT mode before the Backup Regulator is ready may cause loss of Backup RAM content. + 16 + 1 + read-only + + + B_0x0 + Backup Regulator not ready. + 0x0 + + + B_0x1 + Backup Regulator ready. + 0x1 + + + + + VBATL + Monitored VBAT level above low threshold + 20 + 1 + read-only + + + B_0x0 + VBAT level above low threshold level, or Monitor disabled. + 0x0 + + + B_0x1 + VBAT level equal or below low threshold level. + 0x1 + + + + + VBATH + Monitored VBAT level above high threshold + 21 + 1 + read-only + + + B_0x0 + VBAT level below high threshold level, or Monitor disabled. + 0x0 + + + B_0x1 + VBAT level equal or above high threshold level. + 0x1 + + + + + TEMPL + Monitored temperature level above low threshold + 22 + 1 + read-only + + + B_0x0 + Temperature above low threshold level, or Monitor disabled. + 0x0 + + + B_0x1 + Temperature equal or below low threshold level. + 0x1 + + + + + TEMPH + Monitored temperature level above high threshold + 23 + 1 + read-only + + + B_0x0 + Temperature below high threshold level, or Monitor disabled. + 0x0 + + + B_0x1 + Temperature equal or above high threshold level. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + PWR control register 3 + 0xc + 0x20 + 0x5000A000 + 0xFFFFFFFF + + + VBE + VBAT charging enable + 8 + 1 + read-write + + + B_0x0 + VBAT battery charging disabled. + 0x0 + + + B_0x1 + VBAT battery charging enabled. + 0x1 + + + + + VBRS + VBAT charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charges VBAT through a 5 kOhm resistor. + 0x0 + + + B_0x1 + Charges VBAT through a 1.5 kOhm resistor. + 0x1 + + + + + DDRSREN + DDR self-refresh in standby mode enable +When set, the DDR PHY puts its pads in retention when entering Standby mode. + 10 + 1 + read-write + + + B_0x0 + DDR self-refresh retention when entering standby mode disabled. + 0x0 + + + B_0x1 + DDR self-refresh retention when entering standby mode enabled (DDR self-refresh retention after Standby must be disabled by DDRSRDIS). + 0x1 + + + + + DDRSRDIS + DDR self-refresh retention after standby disable +When written 'b1, the DDR PHY pads retention, enabled due to DDRSREN, is disabled. + 11 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When DDRSREN is 'b1: Disable DDR self-refresh retention after standby mode. This bit is reset by hardware once DDR self-refresh retention has been disabled. When DRRSREN is 'b0 no action. + 0x1 + + + + + DDRRETEN + DDR retention enable +Set by Hardware on NRST pad reset, when the reset delay control is enabled in the RCC_MP_APRSTCR.RDCTLEN register bit, or when written 'b1 by software, the DDR PHY puts its pads in retention. +To disable retention software must write this bit to 'b0. + 12 + 1 + read-write + + + B_0x0 + DDR self-refresh retention disabled. + 0x0 + + + B_0x1 + DDR self-refresh retention enabled. + 0x1 + + + + + VDDSD1DEN + VDDSD1 voltage level detector enable +The voltage level detector is active by default. It enables the I/Os in the VDDSD1 domain if and when the VDDSD1 supply voltage is higher than VDDSDx_TH. Once the supply is stable above this threshold (VDDSD1RDY = 1), the level detectors can be switched off to save power, without disabling the I/Os, by setting VDDSD1VALID = 1 followed by VDDSD1EN = 0 (refer to datasheet for VDDSDx_TH value). + 13 + 1 + read-write + + + B_0x0 + VDDSD1 level detector switched off. I/Os in VDDSD1 domain are also disabled if VDDSD1VALID = 0 + 0x0 + + + B_0x1 + VDDSD1 level detector is active. I/Os in VDDSD1 domain are active if VDDSD1RDY = 1 + 0x1 + + + + + VDDSD1RDY + VDDSD1 supply ready +When the level detector is active (VDDSD1DEN = 1), this bit indicates if a voltage higher than VDDSDx_TH is present on the VDDSD1 supply (refer to datasheet for VDDSDx_TH value). + 14 + 1 + read-only + + + B_0x0 + VDDSD1 supply not present, or voltage detector switched off (VDDSD1EN = 0) + 0x0 + + + B_0x1 + VDDSD1 supply present + 0x1 + + + + + VDDSD2DEN + VDDSD2 voltage level detector enable +The voltage level detector is active by default. It enables the I/Os in the VDDSD2 domain if and when the VDDSD2 supply voltage is higher than VDDSDx_TH. Once the supply is stable above this threshold (VDDSD2RDY = 1), the level detectors can be switched off to save power, without disabling the I/Os, by setting VDDSD2VALID = 1 followed by VDDSD2EN = 0 (refer to datasheet for VDDSDx_TH value). + 15 + 1 + read-write + + + B_0x0 + VDDSD2 level detector switched off. I/Os in VDDSD2 domain are also disabled if VDDSD2VALID = 0 + 0x0 + + + B_0x1 + VDDSD2 level detector is active. I/Os in VDDSD2 domain are active if VDDSD2RDY = 1 + 0x1 + + + + + VDDSD2RDY + VDDSD2 supply ready +When the level detector is active (VDDSD2DEN = 1), this bit indicates if a voltage higher than VDDSDx_TH is present on the VDDSD2 supply (refer to datasheet for VDDSDx_TH value). + 16 + 1 + read-only + + + B_0x0 + VDDSD2 supply not present, or voltage detector switched off (VDDSD2EN = 0) + 0x0 + + + B_0x1 + VDDSD2 supply present + 0x1 + + + + + POPL + PWR_ON, PWR_CPU_ON Standby pulse low configuration +These bits are set and cleared by software. They define the minimum guaranteed duration of the PWR_ON and PWR_CPU_ON low pulse in Standby mode (there is no impact on the LP-Stop and LPLV-Stop modes). +The LSI oscillator is automatically enabled when needed by the POPL pulse low configuration. +... + 17 + 5 + read-write + + + B_0x0 + ~ 62.5 us guaranteed minimum low time (2 LSI cycles) + 0x0 + + + B_0x1 + ~ 1 ms guaranteed minimum low time (1 x 32 LSI cycles) + 0x1 + + + B_0x2 + ~ 2 ms guaranteed minimum low time (2 x 32 LSI cycles) + 0x2 + + + B_0x1F + ~ 31 ms guaranteed minimum low time (31 x 32 LSI cycles) + 0x1F + + + + + VDDSD1VALID + Override VDDSD1 voltage detector +This bit enables the I/Os in the VDDSD1 domain whatever the state of VDDSD1RDY. This bit can be set by software once VDDSD1 is higher than VDDSDx_TH and stable (bit VDDSD1RDY = 1). Subsequently VDDSD1EN can be reset to 0 to disable the voltage detector and save power (refer to datasheet for VDDSDx_TH value). + 22 + 1 + read-write + + + B_0x0 + I/O enable/disable is controlled by the VDDSD1 voltage detector + 0x0 + + + B_0x1 + I/O enable is forced active + 0x1 + + + + + VDDSD2VALID + Override VDDSD2 voltage detector +This bit enables the I/Os in the VDDSD2 domain whatever the state of VDDSD2RDY. This bit can be set by software once VDDSD2 is higher than VDDSDx_TH and stable (bit VDDSD2RDY = 1). Subsequently VDDSD2EN can be reset to 0 to disable the voltage detector and save power (refer to datasheet for VDDSDx_TH value). + 23 + 1 + read-write + + + B_0x0 + I/O enable/disable is controlled by the VDDSD2 voltage detector + 0x0 + + + B_0x1 + I/O enable is forced active + 0x1 + + + + + USB33DEN + USB 3.3V voltage level detector enable + 24 + 1 + read-write + + + B_0x0 + USB 3.3V voltage level detector + 0x0 + + + B_0x1 + USB 3.3V voltage level detector + 0x1 + + + + + USB33RDY + USB 3.3V supply ready + 26 + 1 + read-only + + + B_0x0 + USB 3.3V supply not ready + 0x0 + + + B_0x1 + USB 3.3V supply ready + 0x1 + + + + + REG18EN + 1V8 regulator enable + 28 + 1 + read-write + + + B_0x0 + 1V8 regulator disabled + 0x0 + + + B_0x1 + 1V8 regulator enabled, when also pin BYPASS_REG1V8 is low (when in Standby mode the 1V8 regulator is disabled). + 0x1 + + + + + REG18RDY + 1V8 regulator supply ready + 29 + 1 + read-only + + + B_0x0 + 1V8 supply not ready + 0x0 + + + B_0x1 + 1V8 supply ready + 0x1 + + + + + REG11EN + 1V1 regulator enable + 30 + 1 + read-write + + + B_0x0 + 1V1 regulator disabled + 0x0 + + + B_0x1 + 1V1 regulator enabled (when in Standby mode the 1V1 regulator is disabled) + 0x1 + + + + + REG11RDY + 1V1 regulator supply ready + 31 + 1 + read-only + + + B_0x0 + 1V1 supply not ready + 0x0 + + + B_0x1 + 1V1 supply ready + 0x1 + + + + + + + PWR_MPUCR + PWR_MPUCR + PWR MPU control register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PDDS + System Power Down Deepsleep selection +This bit is reset only by a VDD POR reset (not reset when exit from Standby mode). +Allows to define the Deepsleep mode for the system. + 0 + 1 + read-write + + + B_0x0 + Keeps System Stop when MPU enters to CStop or System LPLV-Stop2 mode when MPU enters to CStandby. + 0x0 + + + B_0x1 + Allows System Standby mode when MPU enters to CStandby. + 0x1 + + + + + STOPF + Stop flag +This bit is set by hardware and cleared only by any system reset or by setting the MPU CSSF bit. This bit is cleared by the MPU Boot ROM. For more information refer to Boot ROM application note. + 5 + 1 + read-only + + + B_0x0 + System has not been in Stop mode + 0x0 + + + B_0x1 + System has been in Stop mode, clock system has been stopped. + 0x1 + + + + + SBF + System Standby flag +This bit is set by hardware and cleared only by a VDD POR reset or by setting the MPU CSSF bit (not reset when exit from Standby mode). This bit is cleared by the MPU Boot ROM. For more information refer to Boot ROM application note. + 6 + 1 + read-only + + + B_0x0 + System has not been in Standby mode. + 0x0 + + + B_0x1 + System has been in Standby mode, system contents has been lost. + 0x1 + + + + + SBFMPU + MPU Standby flag +This bit is set by hardware and cleared only by a VDD POR reset or by setting the MPU CSSF bit (not reset when exit from Standby mode). This bit is cleared by the MPU Boot ROM. For more information refer to Boot ROM application note. + 7 + 1 + read-only + + + B_0x0 + MPU has not been in CStandby mode. + 0x0 + + + B_0x1 + MPU has been in CStandby mode. + 0x1 + + + + + CSSF + Clear MPU Standby, Stop flags.(Always read as 0) +This bit is reset on any system reset. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + When written, clears the MPU flags (STOPF, SBF, and SBFMPU). The register bit is cleared to 0 by hardware. + 0x1 + + + + + STANDBYWFIL2 + MPU system idle indication +This bit is set and reset by hardware based on the MPU operation mode. + 15 + 1 + read-only + + + B_0x0 + MPU system CRun or CSleep + 0x0 + + + B_0x1 + MPU system CStop or CStandby + 0x1 + + + + + + + PWR_WKUPCR + PWR_WKUPCR + PWR wakeup control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WKUPC1 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPC2 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPC3 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPC4 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPC5 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPC6 + Clear Wakeup Flag for WKUPn pin, n range [6:1] +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. +These bits are always read as 0. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Writing 1 clears the WKUPFn wakeup flag (the bit is cleared to 0 by hardware). + 0x1 + + + + + WKUPP1 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 8 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPP2 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 9 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPP3 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 10 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPP4 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 11 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPP5 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 12 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPP6 + Wakeup Polarity bit for WKUPn pin, n range [6:1] +These bits define the polarity used for event detection on external wake-up WKUPn pin. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit n can only be written by a secure access, a non-secure write on this bit is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit n can be written by a secure and non-secure access. + 13 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WKUPPUPD1 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 16 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + WKUPPUPD2 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 18 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + WKUPPUPD3 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 20 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + WKUPPUPD4 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 22 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + WKUPPUPD5 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 24 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + WKUPPUPD6 + Wakeup pull configuration for WKUPn pin (n = 6 to 1) +These bits define the IO pad pull configuration used when WKUPENn = 1 (note that the associated GPIO port pull configuration must be set to the same value or 00). The wakeup pin pull configuration is maintained in Standby mode. +When TZEN is enabled in the RCC and WKUPENn in (PWR_MPUWKUPENR) is set, bit pair n can only be written by a secure access, a non-secure write on this bit pair is discarded. +When TZEN is disabled in the RCC or WKUPENn in (PWR_MPUWKUPENR) is clear, bit pair n can be written by a secure and non-secure access. + 26 + 2 + read-write + + + B_0x0 + No pulls + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + PWR_WKUPFR + PWR_WKUPFR + PWR wakeup flag register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WKUPF1 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 0 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + WKUPF2 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 1 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + WKUPF3 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 2 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + WKUPF4 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 3 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + WKUPF5 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 4 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + WKUPF6 + Wakeup flag for WKUPn pin before enable, n range [6:1]. +This bit is set by hardware and cleared only by a NRST Reset or by setting the WKUPCn bit in the + 5 + 1 + read-only + + + B_0x0 + No wakeup event occurred + 0x0 + + + B_0x1 + A wakeup event was received from WKUPCn pin + 0x1 + + + + + + + PWR_MPUWKUPENR + PWR_MPUWKUPENR + PWR MPU wakeup enable register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WKUPEN1 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 0 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + WKUPEN2 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 1 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + WKUPEN3 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 2 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + WKUPEN4 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 3 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + WKUPEN5 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 4 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + WKUPEN6 + Enable Wakeup WKUPn pin and interrupt for MPU, n range [6:1] +Each bit is set and cleared by software. +When TZEN is enabled in the RCC, these bits can only be written by a secure access, a non-secure write is discarded. +When TZEN is disabled in the RCC, these bits can be written by a secure and non-secure access. + 5 + 1 + read-write + + + B_0x0 + An event on WKUPn pin does not wake up the system from Standby and Stop mode, nor generates an interrupt to MPU. + 0x0 + + + B_0x1 + A rising or falling edge on WKUPn pin wakes up the system from Standby and Stop mode and generates an interrupt to MPU. + 0x1 + + + + + + + PWR_VER + PWR_VER + PWR IP version register + 0x3f4 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + MINREV + Minor revision number + 0 + 4 + read-only + + + MAJREV + Major revision number + 4 + 4 + read-only + + + + + PWR_ID + PWR_ID + PWR IP identification register + 0x3f8 + 0x20 + 0x00010001 + 0xFFFFFFFF + + + IPID + IP identification + 0 + 32 + read-only + + + + + PWR_SID + PWR_SID + PWR size ID register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification + 0 + 32 + read-only + + + + + + + QUADSPI + QUADSPI1 + QUADSPI1 + 0x58003000 + + 0x0 + 0x1000 + registers + + + QUADSPI + QUADSPI global interrupt + 91 + + + + QUADSPI_CR + QUADSPI_CR + QUADSPI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + ABORT + ABORT + 1 + 1 + + + DMAEN + DMAEN + 2 + 1 + + + TCEN + TCEN + 3 + 1 + + + SSHIFT + SSHIFT + 4 + 1 + + + DFM + DFM + 6 + 1 + + + FSEL + FSEL + 7 + 1 + + + FTHRES + FTHRES + 8 + 4 + + + TEIE + TEIE + 16 + 1 + + + TCIE + TCIE + 17 + 1 + + + FTIE + FTIE + 18 + 1 + + + SMIE + SMIE + 19 + 1 + + + TOIE + TOIE + 20 + 1 + + + APMS + APMS + 22 + 1 + + + PMM + PMM + 23 + 1 + + + PRESCALER + PRESCALER + 24 + 8 + + + + + QUADSPI_DCR + QUADSPI_DCR + QUADSPI device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + CKMODE + 0 + 1 + + + CSHT + CSHT + 8 + 3 + + + FSIZE + FSIZE + 16 + 5 + + + + + QUADSPI_SR + QUADSPI_SR + QUADSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + TEF + 0 + 1 + + + TCF + TCF + 1 + 1 + + + FTF + FTF + 2 + 1 + + + SMF + SMF + 3 + 1 + + + TOF + TOF + 4 + 1 + + + BUSY + BUSY + 5 + 1 + + + FLEVEL + FLEVEL + 8 + 5 + + + + + QUADSPI_FCR + QUADSPI_FCR + QUADSPI flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CTEF + CTEF + 0 + 1 + + + CTCF + CTCF + 1 + 1 + + + CSMF + CSMF + 3 + 1 + + + CTOF + CTOF + 4 + 1 + + + + + QUADSPI_DLR + QUADSPI_DLR + QUADSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + DL + 0 + 32 + + + + + QUADSPI_CCR + QUADSPI_CCR + QUADSPI communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + INSTRUCTION + 0 + 8 + + + IMODE + IMODE + 8 + 2 + + + ADMODE + ADMODE + 10 + 2 + + + ADSIZE + ADSIZE + 12 + 2 + + + ABMODE + ABMODE + 14 + 2 + + + ABSIZE + ABSIZE + 16 + 2 + + + DCYC + DCYC + 18 + 5 + + + DMODE + DMODE + 24 + 2 + + + FMODE + FMODE + 26 + 2 + + + SIOO + SIOO + 28 + 1 + + + FRCM + FRCM + 29 + 1 + + + DHHC + DHHC + 30 + 1 + + + DDRM + DDRM + 31 + 1 + + + + + QUADSPI_AR + QUADSPI_AR + QUADSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + ADDRESS + 0 + 32 + + + + + QUADSPI_ABR + QUADSPI_ABR + QUADSPI alternate bytes registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + QUADSPI_DR + QUADSPI_DR + QUADSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + QUADSPI_PSMKR + QUADSPI_PSMKR + QUADSPI polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + MASK + 0 + 32 + + + + + QUADSPI_PSMAR + QUADSPI_PSMAR + QUADSPI polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + MATCH + 0 + 32 + + + + + QUADSPI_PIR + QUADSPI_PIR + QUADSPI polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + INTERVAL + 0 + 16 + + + + + QUADSPI_LPTR + QUADSPI_LPTR + QUADSPI low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + TIMEOUT + 0 + 16 + + + + + QUADSPI_HWCFGR + QUADSPI_HWCFGR + QUADSPI HW configuration register + 0x3F0 + 0x20 + read-only + 0x0000B058 + + + FIFOSIZE + FIFOSIZE + 0 + 4 + + + FIFOPTR + FIFOPTR + 4 + 4 + + + PRESCVAL + PRESCVAL + 8 + 4 + + + IDLENGTH + IDLENGTH + 12 + 4 + + + + + QUADSPI_VERR + QUADSPI_VERR + QUADSPI version register + 0x3F4 + 0x20 + read-only + 0x00000041 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + QUADSPI_IPIDR + QUADSPI_IPIDR + QUADSPI identification register + 0x3F8 + 0x20 + read-only + 0x00140031 + + + ID + ID + 0 + 32 + + + + + QUADSPI_SIDR + QUADSPI_SIDR + QUADSPI size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + RCC + RCC + RCC + 0x50000000 + + 0x0 + 0x1000 + registers + + + RCC + RCC global interrupt + 5 + + + RCC_WAKEUP + RCC MPU wakeup interrupt + 122 + + + + RCC_SECCFGR + RCC_SECCFGR + RCC secure configuration register + 0x0 + 0x20 + 0x83FF3F1F + + + HSISEC + Secure state of the HSI clock + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + CSISEC + Secure state of the CSI clock + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + HSESEC + Secure state of the HSE clock + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + LSISEC + Secure state of the LSI clock + 3 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + LSESEC + Secure state of the LSE clock + 4 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + PLL12SEC + Secure state of the PLL1 and PLL2 clocks + 8 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + PLL3SEC + Secure state of the PLL3 clock + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + PLL4SEC + Secure state of the PLL4 clock + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + MPUSEC + Secure state of the MPU sub-system clock + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + AXISEC + Secure state of the AXI sub-system clock + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + MLAHBSEC + Secure state of the MLAHB sub-system clock + 13 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + APB3DIVSEC + Secure state of the APB3DIV divider + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + APB4DIVSEC + Secure state of the APB4DIV divider + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + APB5DIVSEC + Secure state of the APB5DIV divider + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + APB6DIVSEC + Secure state of the APB6DIV divider + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + TIMG3SEC + Secure state of the TIMG3 prescaler + 20 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + CPERSEC + Secure state of the common peripheral clock + 21 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + MCO1SEC + Secure state of the MCO1 clock + 22 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + MCO2SEC + Secure state of the MCO2 clock + 23 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + STPSEC + Secure state of the Stop modes + 24 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + RSTSEC + Secure state of the reset + 25 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + PWRSEC + Secure state of the PWR block + This control bit generates the output signal rcc_pwr_sec which is connected to the PWR block. + 31 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure (default after reset) + 0x1 + + + + + + + RCC_MP_SREQSETR + RCC_MP_SREQSETR + RCC stop request set register + 0x100 + 0x20 + 0x00000000 + + + STPREQ_P0 + Stop request from MPU processor + Set by software + Indicates if the MPU processor allow or not the entry in CStop/CStandby modes for MPU domain, when the MPU is in WFI. + Note: the entry selection between CStop and CStandby is controlled by PWR_MPUCR.PDDS and PWR_CR1.STOP2 control bits. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the MPU processor does not allow the MPU domain to go to CStop/CStandby; then if MPU is in WFI, it is kept in CSleep + 0x0 + + + B_0x1 + Writing '1' sets the STPREQ_P0 bit, reading '1' means that the MPU processor allows the MPU domain to go to CStop + 0x1 + + + + + + + RCC_MP_SREQCLRR + RCC_MP_SREQCLRR + RCC stop request clear register + 0x104 + 0x20 + 0x00000000 + + + STPREQ_P0 + Stop request from MPU processor + Cleared by software + Indicates if the MPU processor allow or not the entry in CStop/CStandby modes for MPU domain, when the MPU is in WFI. + Note: the entry selection between CStop and CStandby is controlled by PWR_MPUCR.PDDS and PWR_CR1.STOP2 control bits. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the MPU processor does not allow the MPU domain to go to CStop/CStandby; then if MPU is in WFI, it is kept in CSleep + 0x0 + + + B_0x1 + Writing '1' clears the STPREQ_P0 bit, reading '1' means that the MPU processor allows the MPU domain to go to CStop + 0x1 + + + + + + + RCC_MP_APRSTCR + RCC_MP_APRSTCR + RCC application reset control register + 0x108 + 0x20 + 0x00007F00 + + + RDCTLEN + Reset delay control enable + Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + The RDCTL control block is bypassed (default after reset) + 0x0 + + + B_0x1 + The RDCTL control block is enabled. + 0x1 + + + + + RSTTO + Reset timeout delay adjust + 8 + 7 + read-write + + + B_0x0 + The timeout function is disabled + 0x0 + + + B_0x1 + The timeout is set to 2 x 2HSIDIV us + 0x1 + + + B_0x7F + The timeout is set to 128 x 2HSIDIV us (default after reset) + 0x7F + + + + + + + RCC_MP_APRSTSR + RCC_MP_APRSTSR + RCC application reset status register + 0x10C + 0x20 + 0x00000000 + + + RSTTOV + Reset timeout delay value + Set by hardware in order to give the value of the timeout counter. This function is only available when the RDCTLEN = '1'. + If RSTTOS = '0' it means that a timeout occurred. + 8 + 7 + read-only + + + + + RCC_PWRLPDLYCR + RCC_PWRLPDLYCR + RCC low-power Stop modes delay control register + 0x110 + 0x20 + 0x00000000 + + + PWRLP_DLY + PWRLP_TEMPO value + Written by software. + This register contains the delay value to be observed before activating the PLLs and interconnect clocks, after one of the system Stop modes. + The delay is counted with the HSI clock. The user has to take into account HSIDIV value. + The delay value is given by the following formula: PWRLP_DLY[21:0] / FHSI + ... + 0 + 22 + read-write + + + B_0x0 + the PWRLP_TEMPO delay is bypassed (default after reset) + 0x0 + + + B_0x1 + a PWRLP_TEMPO delay of one period of HSI (at 64 MHz) is observed + 0x1 + + + B_0x3FFFFF + a PWRLP_TEMPO delay of about 65.5 milliseconds is observed + 0x3FFFFF + + + + + + + RCC_MP_GRSTCSETR + RCC_MP_GRSTCSETR + RCC global reset control set register + 0x114 + 0x20 + 0x00000000 + + + MPSYSRST + System reset + Set by software, cleared by hardware. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' generates a system reset, see Figure 3. + 0x1 + + + + + MPUP0RST + MPU processor reset + Set by software, cleared by hardware when the reset command is completed. + Note that the Snoop Control Unit of the MPU (SCU) is not reset. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' generates a reset of the MPU processor 0, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_BR_RSTSCLRR + RCC_BR_RSTSCLRR + RCC BOOTROM reset status clear register + 0x118 + 0x20 + 0x00000015 + + + PORRSTF + POR/PDR reset flag + Cleared by software, set by hardware when a POR/PDR reset occurred. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no POR/PDR reset occurred + 0x0 + + + B_0x1 + Writing '1' clears the PORRSTF flag, reading '1' means that a POR/PDR reset occurred (default after por_rst reset) + 0x1 + + + + + BORRSTF + BOR reset flag + Cleared by software, set by hardware when a BOR reset occurred. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no BOR reset occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the BORRSTF flag, reading '1' means that a BOR reset occurred + 0x1 + + + + + PADRSTF + NRST reset flag + Cleared by software, set by hardware when a PAD reset occurred. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no PAD reset occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the PADRSTF flag, reading '1' means that a PAD reset occurred + 0x1 + + + + + HCSSRSTF + HSE CSS reset flag + Cleared by software, set by hardware when a failure is detected on HSE. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no HSE CSS reset occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the HCSSRSTF flag, reading '1' means that a HSE CSS reset occurred + 0x1 + + + + + VCORERSTF + VDDCORE reset flag + Cleared by software, set by hardware when a reset occurred because VDDCORE is lower than the expected value. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that VDDCORE is not the origin of the reset + 0x0 + + + B_0x1 + Writing '1' clears the VCORERSTF flag, reading '1' means that VDDCORE is the origin of the reset (default after por_rst reset) + 0x1 + + + + + VCPURSTF + VDDCPU reset flag + Cleared by software, set by hardware when a reset occurred because VDDCPU is lower than the expected value. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that VDDCPU is not the origin of the reset + 0x0 + + + B_0x1 + Writing '1' clears the VCPURSTF flag, reading '1' means that VDDCPU is the origin of the reset (default after por_rst reset) + 0x1 + + + + + MPSYSRSTF + MPU System reset flag + Cleared by software, set by hardware when a MPU system reset occurred. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no system reset generated by the MPU occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the MPSYSRSTF flag, reading '1' means that a system reset generated by the MPU occurred + 0x1 + + + + + IWDG1RSTF + IWDG1 reset flag + Cleared by software, set by hardware when a IWDG1 reset occurred. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no IWDG1 reset occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the IWDG1RSTF flag, reading '1' means that a IWDG1 reset occurred + 0x1 + + + + + IWDG2RSTF + IWDG2 reset flag + Cleared by software, set by hardware when a IWDG2 reset occurred. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no IWDG2 reset occurred (default after por_rst reset) + 0x0 + + + B_0x1 + Writing '1' clears the IWDG2RSTF flag, reading '1' means that a IWDG2 reset occurred + 0x1 + + + + + MPUP0RSTF + MPU processor reset flag + Cleared by software, set by hardware when a MPU processor reset occurred. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that no MPU processor reset occurred (default after nreset reset) + 0x0 + + + B_0x1 + Writing '1' clears the MPUP0RSTF flag, reading '1' means that MPU processor reset occurred + 0x1 + + + + + + + RCC_MP_RSTSSETR + RCC_MP_RSTSSETR + RCC reset status set register + 0x11C + 0x20 + 0x00000000 + + + PORRSTF + POR/PDR reset flag + Set by the BOOTROM code when a POR/PDR reset occurred. + 0 + 1 + read-write + + + B_0x0 + No POR/PDR reset occurred + 0x0 + + + B_0x1 + A POR/PDR reset occurred + 0x1 + + + + + BORRSTF + BOR reset flag + Set by the BOOTROM code when a BOR reset occurred. + 1 + 1 + read-write + + + B_0x0 + No BOR reset occurred + 0x0 + + + B_0x1 + A BOR reset occurred + 0x1 + + + + + PADRSTF + NRST reset flag + Set by the BOOTROM code when a PAD reset occurred. + 2 + 1 + read-write + + + B_0x0 + No PAD reset occurred + 0x0 + + + B_0x1 + A PAD reset occurred + 0x1 + + + + + HCSSRSTF + HSE CSS reset flag + Set by the BOOTROM code when a failure is detected on HSE. + 3 + 1 + read-write + + + B_0x0 + No HSE CSS reset occurred + 0x0 + + + B_0x1 + A HSE CSS reset occurred + 0x1 + + + + + VCORERSTF + VDDCORE reset flag + Set by the BOOTROM code when a reset occurred because VDDCORE is lower than the expected value. + 4 + 1 + read-write + + + B_0x0 + VDDCORE is not the origin of the reset + 0x0 + + + B_0x1 + VDDCORE is the origin of the reset + 0x1 + + + + + VCPURSTF + VCPU reset flag + Set by the BOOTROM code when a reset occurred because VCPU is lower than the expected value. + 5 + 1 + read-write + + + B_0x0 + VCPU is not the origin of the reset + 0x0 + + + B_0x1 + VCPU is the origin of the reset + 0x1 + + + + + MPSYSRSTF + MPU System reset flag + Set by the BOOTROM code when a MPU system reset occurred. + 6 + 1 + read-write + + + B_0x0 + No system reset generated by the MPU occurred + 0x0 + + + B_0x1 + A system reset generated by the MPU occurred + 0x1 + + + + + IWDG1RSTF + IWDG1 reset flag + Set by the BOOTROM code when a IWDG1 reset occurred. + 8 + 1 + read-write + + + B_0x0 + No IWDG1 reset occurred + 0x0 + + + B_0x1 + An IWDG1 reset occurred + 0x1 + + + + + IWDG2RSTF + IWDG2 reset flag + Set by the BOOTROM code when a IWDG2 reset occurred. + 9 + 1 + read-write + + + B_0x0 + No IWDG2 reset occurred + 0x0 + + + B_0x1 + An IWDG2 reset occurred + 0x1 + + + + + STP2RSTF + Stop2 reset flag + Set by the BOOTROM code when exiting from Stop2. + 10 + 1 + read-write + + + B_0x0 + System has not been in Stop2 mode + 0x0 + + + B_0x1 + System has been in Stop2 mode + 0x1 + + + + + STDBYRSTF + System Standby reset flag + Set by the BOOTROM code when exiting from Standby. + 11 + 1 + read-write + + + B_0x0 + System has not been in Standby mode + 0x0 + + + B_0x1 + System has been in Standby mode + 0x1 + + + + + CSTDBYRSTF + MPU CStandby reset flag + Set by the BOOTROM code when the MPU exits from CStandby. + 12 + 1 + read-write + + + B_0x0 + MPU has not been in CStandby + 0x0 + + + B_0x1 + MPU has been in CStandby + 0x1 + + + + + MPUP0RSTF + MPU processor reset flag + Set by the BOOTROM code when a MPU processor reset occurred. + 13 + 1 + read-write + + + B_0x0 + No MPU processor reset occurred (default after nreset reset) + 0x0 + + + B_0x1 + MPU processor reset occurred + 0x1 + + + + + SPARE + Spare bit + Set and reset by software. Reserved for future use. + 15 + 1 + read-write + + + + + RCC_MP_RSTSCLRR + RCC_MP_RSTSCLRR + RCC reset status clear register + 0x120 + 0x20 + 0x00000000 + + + PORRSTF + POR/PDR reset flag + Cleared by software, set by the BOOTROM code when a POR/PDR reset occurred. + 0 + 1 + read-write + + + B_0x0 + No POR/PDR reset occurred + 0x0 + + + B_0x1 + A POR/PDR reset occurred + 0x1 + + + + + BORRSTF + BOR reset flag + Cleared by software, set by the BOOTROM code when a BOR reset occurred. + 1 + 1 + read-write + + + B_0x0 + No BOR reset occurred + 0x0 + + + B_0x1 + A BOR reset occurred + 0x1 + + + + + PADRSTF + NRST reset flag + Cleared by software, set by the BOOTROM code when a PAD reset occurred. + 2 + 1 + read-write + + + B_0x0 + No PAD reset occurred + 0x0 + + + B_0x1 + A PAD reset occurred + 0x1 + + + + + HCSSRSTF + HSE CSS reset flag + Cleared by software, set by the BOOTROM code when a failure is detected on HSE. + 3 + 1 + read-write + + + B_0x0 + No HSE CSS reset occurred + 0x0 + + + B_0x1 + A HSE CSS reset occurred + 0x1 + + + + + VCORERSTF + VDDCORE reset flag + Cleared by software, set by the BOOTROM code when a reset occurred because VDDCORE is lower than the expected value. + 4 + 1 + read-write + + + B_0x0 + VDDCORE is not the origin of the reset + 0x0 + + + B_0x1 + VDDCORE is the origin of the reset + 0x1 + + + + + VCPURSTF + VDDCPU reset flag + Cleared by software, set by the BOOTROM code when a reset occurred because VDDCPU is lower than the expected value. + 5 + 1 + read-write + + + B_0x0 + VDDCPU is not the origin of the reset + 0x0 + + + B_0x1 + VDDCPU is the origin of the reset + 0x1 + + + + + MPSYSRSTF + MPU System reset flag + Cleared by software, set by the BOOTROM code when a MPU system reset occurred. + 6 + 1 + read-write + + + B_0x0 + No system reset generated by the MPU occurred + 0x0 + + + B_0x1 + A system reset generated by the MPU occurred + 0x1 + + + + + IWDG1RSTF + IWDG1 reset flag + Cleared by software, set by the BOOTROM code when a IWDG1 reset occurred. + 8 + 1 + read-write + + + B_0x0 + No IWDG1 reset occurred + 0x0 + + + B_0x1 + An IWDG1 reset occurred + 0x1 + + + + + IWDG2RSTF + IWDG2 reset flag + Cleared by software, set by the BOOTROM code when a IWDG2 reset occurred. + 9 + 1 + read-write + + + B_0x0 + No IWDG2 reset occurred + 0x0 + + + B_0x1 + An IWDG2 reset occurred + 0x1 + + + + + STP2RSTF + Stop2 reset flag + Cleared by software, set by the BOOTROM code when exiting from Stop2. + 10 + 1 + read-write + + + B_0x0 + System has not been in Stop2 mode + 0x0 + + + B_0x1 + System has been in Stop2 mode + 0x1 + + + + + STDBYRSTF + System Standby reset flag + Cleared by software, set by the BOOTROM code when exiting from Standby. + 11 + 1 + read-write + + + B_0x0 + System has not been in Standby mode + 0x0 + + + B_0x1 + System has been in Standby mode + 0x1 + + + + + CSTDBYRSTF + MPU CStandby reset flag + Cleared by software, set by the BOOTROM code when the MPU exits from CStandby. + 12 + 1 + read-write + + + B_0x0 + MPU has not been in CStandby mode + 0x0 + + + B_0x1 + MPU has been in CStandby mode + 0x1 + + + + + MPUP0RSTF + MPU processor reset flag + Cleared by software, set by the BOOTROM code when a MPU processor reset occurred. + 13 + 1 + read-write + + + B_0x0 + No MPU processor reset occurred (default after nreset reset) + 0x0 + + + B_0x1 + MPU processor reset occurred + 0x1 + + + + + SPARE + Spare bit + Set and reset by software. Reserved for future use. + 15 + 1 + read-write + + + + + RCC_MP_IWDGFZSETR + RCC_MP_IWDGFZSETR + RCC IWDG clock freeze set register + 0x124 + 0x20 + 0x00000000 + + + FZ_IWDG1 + Freeze the IWDG1 clock + If IWDG1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. + Set once by the BOOTROM software after a system reset or Standby reset, or a CStandby reset, in order to freeze the IWDG1. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the IWDG1 clock is not frozen (default after reset) + 0x0 + + + B_0x1 + Writing '1' freeze the IWDG1 clock, reading '1' means that the IWDG1 clock is frozen + 0x1 + + + + + FZ_IWDG2 + Freeze the IWDG2 clock + Set once by the BOOTROM software after a system reset or Standby reset, or a CStandby reset, in order to freeze the IWDG2. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the IWDG2 clock is not frozen (default after reset) + 0x0 + + + B_0x1 + Writing '1' freeze the IWDG2 clock, reading '1' means that the IWDG2 clock is frozen + 0x1 + + + + + + + RCC_MP_IWDGFZCLRR + RCC_MP_IWDGFZCLRR + RCC IWDG clock freeze clear register + 0x128 + 0x20 + 0x00000000 + + + FZ_IWDG1 + Unfreeze the IWDG1 clock + If IWDG1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. + Cleared by the BOOTROM software, in order to unfreeze the IWDG1. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the IWDG1 clock is not frozen (default after reset) + 0x0 + + + B_0x1 + Writing '1' unfreeze the IWDG1 clock, reading '1' means that the IWDG1 clock is frozen + 0x1 + + + + + FZ_IWDG2 + Unfreeze the IWDG2 clock +Cleared by the BOOTROM software, in order to unfreeze the IWDG2. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the IWDG2 clock is not frozen (default after reset) + 0x0 + + + B_0x1 + Writing '1' unfreeze the IWDG2 clock, reading '1' means that the IWDG2 clock is frozen + 0x1 + + + + + + + RCC_MP_CIER + RCC_MP_CIER + RCC clock source interrupt enable register + 0x200 + 0x20 + 0x00000000 + + + LSIRDYIE + LSI ready Interrupt Enable + If RCC_SECCFGR.LSISEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready Interrupt Enable + If RCC_SECCFGR.LSESEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI ready Interrupt Enable + If RCC_SECCFGR.HSISEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. + 2 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready Interrupt Enable + If RCC_SECCFGR.HSESEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + CSIRDYIE + CSI ready Interrupt Enable + If RCC_SECCFGR.CSISEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + CSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + CSI ready interrupt enabled + 0x1 + + + + + PLL1DYIE + PLL1 ready Interrupt Enable + If RCC_SECCFGR.PLL12SEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by PLL1 lock. + 8 + 1 + read-write + + + B_0x0 + PLL1 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL1 lock interrupt enabled + 0x1 + + + + + PLL2DYIE + PLL2 ready Interrupt Enable + If RCC_SECCFGR.PLL12SEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by PLL2 lock. + 9 + 1 + read-write + + + B_0x0 + PLL2 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL2 lock interrupt enabled + 0x1 + + + + + PLL3DYIE + PLL3 ready Interrupt Enable + If RCC_SECCFGR.PLL3SEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by PLL3 lock. + 10 + 1 + read-write + + + B_0x0 + PLL3 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL3 lock interrupt enabled + 0x1 + + + + + PLL4DYIE + PLL4 ready Interrupt Enable + If RCC_SECCFGR.PLL4SEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by PLL4 lock. + 11 + 1 + read-write + + + B_0x0 + PLL4 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL4 lock interrupt enabled + 0x1 + + + + + LSECSSIE + LSE clock security system Interrupt Enable + If RCC_SECCFGR.LSESEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable interrupt caused by the Clock Security System on + external 32 kHz oscillator. + 16 + 1 + read-write + + + B_0x0 + LSE CSS interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSE CSS interrupt enabled + 0x1 + + + + + WKUPIE + Wake up from CStop Interrupt Enable + If RCC_SECCFGR.STPSEC, a write access to this field must be secure. A read access may be secure or non-secure. + Set and reset by software to enable/disable the generation of the interrupt used to wake up the MPU from CStop. + 20 + 1 + read-write + + + B_0x0 + Wakeup interrupt disabled (default after reset) + 0x0 + + + B_0x1 + Wakeup interrupt enabled + 0x1 + + + + + + + RCC_MP_CIFR + RCC_MP_CIFR + RCC clock source interrupt flag register + 0x204 + 0x20 + 0x00000000 + + + LSIRDYF + LSI ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the LSI clock becomes stable. + 0 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSI (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI, writing '1' clears this flag + 0x1 + + + + + LSERDYF + LSE ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the LSE clock becomes stable. + 1 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSE (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE, writing '1' clears this flag + 0x1 + + + + + HSIRDYF + HSI ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the HSI clock becomes stable. + 2 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI, writing '1' clears this flag + 0x1 + + + + + HSERDYF + HSE ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the HSE clock becomes stable. + 3 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSE (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE, writing '1' clears this flag + 0x1 + + + + + CSIRDYF + CSI ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the CSI clock becomes stable. + 4 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the CSI (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by the CSI, writing '1' clears this flag + 0x1 + + + + + PLL1DYF + PLL1 ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the PLL1 locks. + 8 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by PLL1 lock (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL1 lock, writing '1' clears this flag + 0x1 + + + + + PLL2DYF + PLL2 ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the PLL2 locks. + 9 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by PLL2 lock (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL2 lock, writing '1' clears this flag + 0x1 + + + + + PLL3DYF + PLL3 ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the PLL3 locks. + 10 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by PLL3 lock (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL3 lock, writing '1' clears this flag + 0x1 + + + + + PLL4DYF + PLL4 ready Interrupt Flag +If RCC_SECCFGR.PLLSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the PLL4 locks. + 11 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by PLL4 lock (default after reset) + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL4 lock, writing '1' clears this flag + 0x1 + + + + + LSECSSF + LSE clock security system Interrupt Flag +If RCC_SECCFGR.LSESEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when a failure is detected on the external 32 kHz oscillator. + 16 + 1 + read-write + + + B_0x0 + No failure detected on the external 32 kHz oscillator (default after reset) + 0x0 + + + B_0x1 + A failure is detected on the external 32 kHz oscillator, writing '1' clears this flag + 0x1 + + + + + WKUPF + Wake up from CStop Interrupt Flag +If RCC_SECCFGR.STPSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reset by software by writing this flag to '1'. +Set by hardware when the MPU needs to exit from CStop. + 20 + 1 + read-write + + + B_0x0 + No wakeup interrupt pending (default after reset) + 0x0 + + + B_0x1 + Wakeup interrupt pending, writing '1' clears this flag + 0x1 + + + + + + + RCC_BDCR + RCC_BDCR + RCC backup domain control register + 0x400 + 0x20 + 0x00000020 + + + LSEON + LSE oscillator enabled +Set and reset by software. +If RCC_SECCFGR.LSESEC, a write access to this register field must be secure. A read access may be secure or non-secure. + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF (default after backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and reset by software to bypass oscillator in debug mode. +If RCC_SECCFGR.LSESEC, a write access to this register field must be secure. A read access may be secure or non-secure. +This bit must not be written when the LSE is enabled (LSEON = '1'). +Refer to Stop. for details. + 1 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed (default after backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to '0'. + 2 + 1 + read-only + + + B_0x0 + LSE oscillator not ready (default after backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + DIGBYP + LSE digital bypass +Set and reset by software to select the analog or digital bypass mode. +If RCC_SECCFGR.LSESEC, a write access to this register field must be secure. A read access may be secure or non-secure. + 3 + 1 + read-write + + + B_0x0 + The LSE is in analog bypass mode (default after backup domain reset) + 0x0 + + + B_0x1 + The LSE is in digital bypass mode + 0x1 + + + + + LSEDRV + LSE oscillator driving capability +Written by software to select the driving capability of the LSE oscillator. +If RCC_SECCFGR.LSESEC, a write access to this register field must be secure. A read access may be secure or non-secure. + 4 + 2 + read-write + + + B_0x0 + Lowest drive + 0x0 + + + B_0x1 + Medium low drive + 0x1 + + + B_0x2 + Medium high drive (default after backup domain reset) + 0x2 + + + B_0x3 + Highest drive + 0x3 + + + + + LSECSSON + LSE clock security system enable +Set by software to enable the Clock Security System on 32 kHz oscillator. +If RCC_SECCFGR.LSESEC, a write access to this register field must be secure. A read access may be secure or non-secure. +Refer to for details on the activation and deactivation sequences. +Once the LSECSSON bit is enabled it cannot be disabled, except after a LSE failure detection (LSECSSD = '1'). + 8 + 1 + read-write + + + B_0x0 + Clock Security System on 32 kHz oscillator OFF (default after backup domain reset) + 0x0 + + + B_0x1 + Clock Security System on 32 kHz oscillator ON + 0x1 + + + + + LSECSSD + LSE clock security system failure detection +Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator. + 9 + 1 + read-only + + + B_0x0 + No failure detected on 32 kHz oscillator (default after backup domain reset) + 0x0 + + + B_0x1 + Failure detected on 32 kHz oscillator + 0x1 + + + + + RTCSRC + RTC clock source selection +Set by software to select the clock source for the RTC. +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. +This field can be written only one time after backup domain reset. +When a LSE failure occurs, the RTCSRC[1:0] is set to '00', and the software is allowed to write it again once. +This field must be written before LSECSSON is enabled. +Refer to for details. + 16 + 2 + read-write + + + B_0x0 + No clock (default after backup domain reset) + 0x0 + + + B_0x1 + LSE clock used as RTC clock + 0x1 + + + B_0x2 + LSI clock used as RTC clock + 0x2 + + + B_0x3 + HSE clock divided by RTCDIV value is used as RTC clock + 0x3 + + + + + RTCCKEN + RTC clock enable +Set and reset by software. +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. + 20 + 1 + read-write + + + B_0x0 + rtc_ck clock is disabled (default after backup domain reset) + 0x0 + + + B_0x1 + rtc_ck clock enabled + 0x1 + + + + + VSWRST + VSW domain software reset +Set and reset by software. +If RCC_SECCFGR.RSTSEC, a write access to this field must be secure. A read access may be secure or non-secure. + 31 + 1 + read-write + + + B_0x0 + write: release the software reset; read: software reset not activated (default after backup domain reset) + 0x0 + + + B_0x1 + write: reset the entire VSW domain; read: software reset activated + 0x1 + + + + + + + RCC_RDLSICR + RCC_RDLSICR + RCC reset duration and LSI control register + 0x404 + 0x20 + 0x00000000 + + + LSION + LSI oscillator enabled +Set and reset by software. +If RCC_SECCFGR.LSISEC, a write access to this field must be secure. A read access may be secure or non-secure. +This bit is used to request the activation of the LSI oscillator. Note that IWDG1 and IWDG2 can also request the activation of LSI. + 0 + 1 + read-write + + + B_0x0 + LSI oscillator is OFF if no other requester needs it, such as IWDG[2:1] (default after reset) + 0x0 + + + B_0x1 + LSI oscillator ON + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and reset by hardware to indicate when the LSI is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to '0'. + 1 + 1 + read-only + + + B_0x0 + LSI oscillator not ready (default after reset) + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + MRD + Minimum reset duration +Written by software. +If RCC_SECCFGR.RSTSEC, a write access to this field must be secure. A read access may be secure or non-secure. +This field defines the minimum guaranteed duration of the NRST low pulse. The LSI oscillator is automatically enabled when needed by the RPCTL. +... + 16 + 5 + read-write + + + B_0x0 + NRST low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset) + 0x0 + + + B_0x1 + The guaranteed NRST low pulse duration is about 1 ms (1 x 32 lsi_ck cycles), + 0x1 + + + B_0x2 + The guaranteed NRST low pulse duration is about 2 ms (2 x 32 lsi_ck cycles), + 0x2 + + + B_0x1F + The guaranteed NRST low pulse duration is about 31 ms (31 x 32 lsi_ck cycles). + 0x1F + + + + + EADLY + External access delays +Written by software. +If RCC_SECCFGR.RSTSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Time to wait before the BOOTROM performs any external access (UART, USB, QUADSPI, FMC, SDMMC,...) + 24 + 3 + read-write + + + B_0x0 + 10 ms (default after reset) + 0x0 + + + B_0x1 + No extra delay added by the BOOTROM + 0x1 + + + B_0x2 + 100 us + 0x2 + + + B_0x3 + 200 us + 0x3 + + + B_0x4 + 500 us + 0x4 + + + B_0x5 + 1 ms + 0x5 + + + B_0x6 + 2 ms + 0x6 + + + B_0x7 + 5 ms + 0x7 + + + + + SPARE + Spare bits +Written by software. +If RCC_SECCFGR.RSTSEC, a write access to this field must be secure. A read access may be secure or non-secure. +Reserved for future use. + 27 + 5 + read-write + + + + + RCC_OCENSETR + RCC_OCENSETR + RCC oscillator clock enable set register + 0x420 + 0x20 + 0x00000001 + + + HSION + Set HSION bit +Set by software to enable the HSI clock. +This bit must be written by a secure agent if the HSI clock is configured as secure (i.e. if RCC_SECCFGR.HSISEC=1). +The HSION is also set by hardware to force the HSI to ON when the product leaves Standby mode or one of the Stop modes. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the HSION bit + 0x1 + + + + + HSIKERON + Set HSIKERON bit +Set by software to force the HSI to ON, even in (LP-)Stop mode, in order to be quickly available as kernel clock for peripherals. +This bit must be written by a secure agent if the HSI clock is configured as secure (i.e. if RCC_SECCFGR.HSISEC=1). +This bit has no effect on the value of HSION. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the HSIKERON bit + 0x1 + + + + + CSION + Set CSION bit +Set by software to enable CSI clock. +This bit must be written by a secure agent if the CSI clock is configured as secure (i.e. if RCC_SECCFGR.CSISEC=1). + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the CSION bit + 0x1 + + + + + CSIKERON + Set CSIKERON bit +Set by software to force the CSI to ON, even in (LP-)Stop mode, in order to be quickly available as kernel clock for some peripherals. +This bit must be written by a secure agent if the CSI clock is configured as secure (i.e. if RCC_SECCFGR.CSISEC=1). +This bit has no effect on the value of CSION. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the CSIKERON bit + 0x1 + + + + + DIGBYP + Set DIGBYP bit +Set by software when the external HSE clock is connected to OSC_IN as a full-swing digital signal. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set DIGBYP bit (digital bypass) + 0x1 + + + + + HSEON + Set HSEON bit +Set by software to enable the HSE. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set HSEON bit + 0x1 + + + + + HSEKERON + Set HSEKERON bit +Set by software to force the HSE to ON, even in (LP-)Stop mode, in order to be quickly available as kernel clock for some peripherals. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). +This bit has no effect on the value of HSEON. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the HSEKERON bit + 0x1 + + + + + HSEBYP + Set HSEBYP bit +Set by software in order to enable the bypass mode. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Set the HSEBYP bit + 0x1 + + + + + HSECSSON + Set the HSECSSON bit + 11 + 1 + read-write + + + B_0x0 + Reading '0' means that the Clock Security System on HSE is OFF (default after reset) + 0x0 + + + B_0x1 + Writing '1' enables the Clock Security System on HSE, reading '1' means that the Clock Security System on HSE is ON + 0x1 + + + + + + + RCC_OCENCLRR + RCC_OCENCLRR + RCC oscillator clock enable clear register + 0x424 + 0x20 + 0x00000001 + + + HSION + Clear of HSION bit +Cleared by software to disable the HSI clock. +This bit must be written by a secure agent if the HSI clock is configured as secure (i.e. if RCC_SECCFGR.HSISEC=1). + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSION bit + 0x1 + + + + + HSIKERON + Clear of HSIKERON bit +Cleared by software in order to allow the HSI to be switched off in one of the Stop modes. +This bit must be written by a secure agent if the HSI clock is configured as secure (i.e. if RCC_SECCFGR.HSISEC=1). +This bit has no effect on the value of HSION. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSIKERON bit + 0x1 + + + + + CSION + Clear of CSION bit +Cleared by software to disable the CSI clock. +This bit must be written by a secure agent if the CSI clock is configured as secure (i.e. if RCC_SECCFGR.CSISEC=1). + 4 + 1 + read-write + + + B_0x0 + CSI is OFF + 0x0 + + + B_0x1 + Clear the CSION bit + 0x1 + + + + + CSIKERON + Clear of CSIKERON bit +Cleared by software in order to allow the CSI to be switched off in one of the Stop modes. +This bit must be written by a secure agent if the CSI clock is configured as secure (i.e. if RCC_SECCFGR.CSISEC=1). +This bit has no effect on the value of CSION. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the CSIKERON bit + 0x1 + + + + + DIGBYP + Clear of DIGBYP bit +Cleared by software when the external clock connected to OSC_IN is a low-swing signal. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the DIGBYP bit (analog bypass) + 0x1 + + + + + HSEON + Clear of HSEON bit +Cleared by software to disable the HSE clock. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSEON bit + 0x1 + + + + + HSEKERON + Clear HSEKERON bit +Cleared by software in order to allow the HSE to be switched off in one of the Stop modes. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSEKERON bit + 0x1 + + + + + HSEBYP + Clear the HSEBYP bit +Cleared by software in order to disable the bypass mode. +This bit must be written by a secure agent if the HSE clock is configured as secure (i.e. if RCC_SECCFGR.HSESEC=1). + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSEBYP bit + 0x1 + + + + + + + RCC_OCRDYR + RCC_OCRDYR + RCC oscillators and MPU and AXI clock ready register + 0x428 + 0x20 + 0x00000000 + + + HSIRDY + HSI clock ready flag +Set by hardware to indicate that the HSI oscillator is stable. + 0 + 1 + read-only + + + B_0x0 + HSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSI clock is ready + 0x1 + + + + + HSIDIVRDY + HSI divider ready flag +Set and reset by hardware. +As a write in HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF will go immediately to '0' when HSIDIV value is changed, and will be set back to '1' when the output frequency matches the value programmed into HSIDIV + 2 + 1 + read-only + + + B_0x0 + the new division ratio is not yet propagated to hsi_ck (hsi_ker_ck) (default after reset) + 0x0 + + + B_0x1 + the hsi_ck (hsi_ker_ck) clock frequency reflects the new HSIDIV value + 0x1 + + + + + CSIRDY + CSI clock ready flag +Set by hardware to indicate that the CSI oscillator is stable. + 4 + 1 + read-only + + + B_0x0 + CSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + CSI clock is ready + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. + 8 + 1 + read-only + + + B_0x0 + HSE clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSE clock is ready + 0x1 + + + + + MPUCKRDY + MPU clock ready flag +Set by hardware to indicate that the mpuss_ck clock is available. + 23 + 1 + read-only + + + B_0x0 + mpuss_ck clock is not available (default after reset) + 0x0 + + + B_0x1 + mpuss_ck clock is available + 0x1 + + + + + AXICKRDY + AXI sub-system clock ready flag +Set by hardware to indicate that the axiss_ck clock is available. + 24 + 1 + read-only + + + B_0x0 + axiss_ck clock is not available (default after reset) + 0x0 + + + B_0x1 + axiss_ck clock is available + 0x1 + + + + + + + RCC_HSICFGR + RCC_HSICFGR + RCC HSI configuration register + 0x440 + 0x20 + 0x00000000 + + + HSIDIV + HSI clock divider +Written by software. +These bits allows the user to select a division ratio in order to select the wanted HSI clock frequency. The bit HSIDIVRDY of (RCC_OCRDYR) indicates when the new division ratio is taken into account. + 0 + 2 + read-write + + + B_0x0 + Division by 1, hsi_ck (hsi_ker_ck) = 64 MHz (default after reset) + 0x0 + + + B_0x1 + Division by 2, hsi_ck (hsi_ker_ck) = 32 MHz + 0x1 + + + B_0x2 + Division by 4, hsi_ck (hsi_ker_ck) = 16 MHz + 0x2 + + + B_0x3 + Division by 8, hsi_ck (hsi_ker_ck) = 8 MHz + 0x3 + + + + + HSITRIM + HSI clock trimming +Set by software to adjust calibration. HSITRIM represents a signed value. +HSITRIM field is added to the engineering Option Bytes loaded during reset phase (bsec_hsi_cal[11:0]) in order to form the calibration trimming value. +HSICAL[11:0] = HSITRIM[6:0] + bsec_hsi_cal[11:0]. +... +... + 8 + 7 + read-write + + + B_0x40 + bsec_hsi_cal[11:0] - 64 + 0x40 + + + B_0x41 + bsec_hsi_cal[11:0] - 63 + 0x41 + + + B_0x0 + bsec_hsi_cal[11:0] (default after reset) + 0x0 + + + B_0x3E + bsec_hsi_cal[11:0] + 62 + 0x3E + + + B_0x3F + bsec_hsi_cal[11:0] + 63 + 0x3F + + + + + HSICAL + HSI clock calibration +Set by hardware by option byte loading during system reset +Adjusted by software through trimming bits HSITRIM. +This field represents the sum of engineering Option Byte calibration value and HSITRIM bits value. + 16 + 12 + read-only + + + + + RCC_CSICFGR + RCC_CSICFGR + RCC CSI configuration register + 0x444 + 0x20 + 0x00001000 + + + CSITRIM + CSI clock trimming +Set by software to adjust calibration. +CSITRIM field is added to the engineering Option Bytes loaded during reset phase (bsec_csi_cal[7:0]) in order to form the calibration trimming value. +CSICAL[7:0] = CSITRIM[4:0] + bsec_csi_cal[7:0]. + 8 + 5 + read-write + + + CSICAL + CSI clock calibration +Set by hardware by option byte loading during system reset. +Adjusted by software through trimming bits CSITRIM. +This field represents the sum of engineering Option Byte calibration value and CSITRIM bits value + 16 + 8 + read-only + + + + + RCC_MCO1CFGR + RCC_MCO1CFGR + RCC MCO1 configuration register + 0x460 + 0x20 + 0x00000000 + + + MCO1SEL + MCO1 clock output selection +Set and cleared by software. Clock source selection may generate glitches on MCO1. +It is highly recommended to configure these bits only after reset, before enabling the external +oscillators and the PLLs. +others: reserved + 0 + 3 + read-write + + + B_0x0 + HSI clock selected (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE clock selected (hse_ck) + 0x1 + + + B_0x2 + CSI clock selected (csi_ck) + 0x2 + + + B_0x3 + LSI clock selected (lsi_ck) + 0x3 + + + B_0x4 + LSE oscillator clock selected (lse_ck) + 0x4 + + + + + MCO1DIV + MCO1 prescaler +Set and cleared by software to configure the prescaler of the MCO1. Modification of this +prescaler may generate glitches on MCO1. It is highly recommended to change this +prescaler only after reset, before enabling the external oscillators and the PLLs. +Refer to for details. +... + 4 + 4 + read-write + + + B_0x0 + bypass (default after reset) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + MCO1ON + Control of the MCO1 output +Set and cleared by software to enable the MCO1 output + 12 + 1 + read-write + + + B_0x0 + The MCO1 output is disabled + 0x0 + + + B_0x1 + The MCO1 output is enabled + 0x1 + + + + + + + RCC_MCO2CFGR + RCC_MCO2CFGR + RCC MCO2 configuration register + 0x464 + 0x20 + 0x00000000 + + + MCO2SEL + Micro-controller clock output 2 +Set and cleared by software. Clock source selection may generate glitches on MCO2. +It is highly recommended to configure these bits only after reset, before enabling the external +oscillators and the PLLs. +others: reserved + 0 + 3 + read-write + + + B_0x0 + MPU clock selected (mpuss_ck) (default after reset) + 0x0 + + + B_0x1 + AXI clock selected (axiss_ck) + 0x1 + + + B_0x2 + MLAHB clock selected (mlahbss_ck) + 0x2 + + + B_0x3 + PLL4 clock selected (pll4_p_ck) + 0x3 + + + B_0x4 + HSE clock selected (hse_ck) + 0x4 + + + B_0x5 + HSI clock selected (hsi_ck) + 0x5 + + + + + MCO2DIV + MCO2 prescaler +Set and cleared by software to configure the prescaler of the MCO2. Modification of this +prescaler may generate glitches on MCO2. It is highly recommended to change this +prescaler only after reset, before enabling the external oscillators and the PLLs. +Refer to Section1.4.4: Clock Output generation (MCO1 & MCO2) for details. +... + 4 + 4 + read-write + + + B_0x0 + bypass (default after reset) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + MCO2ON + Control of the MCO2 output +Set and cleared by software to enable the MCO2 output + 12 + 1 + read-write + + + B_0x0 + The MCO2 output is disabled + 0x0 + + + B_0x1 + The MCO2 output is enabled + 0x1 + + + + + + + RCC_DBGCFGR + RCC_DBGCFGR + RCC debug configuration register + 0x468 + 0x20 + 0x00000001 + + + TRACEDIV + Clock divider for the trace clock (ck_trace) +Written by software to control the ck_trace clock division factor. +It is possible to change this division ratio on-the-fly. +others: aclk / 16 + 0 + 3 + read-write + + + B_0x0 + aclk + 0x0 + + + B_0x1 + aclk / 2 (default after reset) + 0x1 + + + B_0x2 + aclk / 4 + 0x2 + + + B_0x3 + aclk / 8 + 0x3 + + + + + DBGCKEN + Clock enable for debug function +Set and cleared by software to control the generation of the ck_apb_dbg clock (DEBUG APB clock), the ck_sys_dbg. See for additional information. + 8 + 1 + read-write + + + B_0x0 + The enabling of the clock for the debug function is controlled by cdbgwrupreq signal from DAP. (default after reset) + 0x0 + + + B_0x1 + The clock for the debug function is enabled + 0x1 + + + + + TRACECKEN + Clock enable for trace function +Set and cleared by software to control the generation of the trace_ck clock. +See for additional information. + 9 + 1 + read-write + + + B_0x0 + The clock for the trace function is disabled (default after reset) + 0x0 + + + B_0x1 + The clock for the trace function is enabled + 0x1 + + + + + DBGRST + Reset of the debug function +Set and cleared by software to control the generation of the reset (dbg_rstn) for the trace and debug parts. + 12 + 1 + read-write + + + B_0x0 + The trace and debug parts are not reset. (default after reset) + 0x0 + + + B_0x1 + The trace and debug parts are under reset. + 0x1 + + + + + + + RCC_RCK12SELR + RCC_RCK12SELR + RCC PLL1 and PLL2 reference clock selection register + 0x480 + 0x20 + 0x80000000 + + + PLL12SRC + Source clock selection for PLL12 +Written by software to select the PLL12 source clock. +In order to save power when PLL12 is not used, PLL12SRC[1:0] must be set to '1x'. +others: No clock send to DIVM1 divider and PLL12 + 0 + 2 + read-write + + + B_0x0 + HSI selected as PLL12 clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as PLL12 clock (hse_ck) + 0x1 + + + + + PLL12SRCRDY + PLL12 source clock switch status +Set and reset by hardware to indicate if the PLL12 clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The PLL12 switch is not ready or in position '1x': no clock is generated on its output + 0x0 + + + B_0x1 + The PLL12 switch is ready: the clock switch is selecting the clock given by PLL12SRC[1:0] field. (default after reset) + 0x1 + + + + + + + RCC_RCK3SELR + RCC_RCK3SELR + RCC PLL3 reference clock selection register + 0x484 + 0x20 + 0x80000000 + + + PLL3SRC + Source clock selection for PLL3 +Written by software to select the PLL3 clock source. +In order to save power, when PLL3 is not used, PLL3SRC[1:0] must be set to '11'. + 0 + 2 + read-write + + + B_0x0 + HSI selected as PLL clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as PLL clock (hse_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + No clock send to DIVM3 divider and PLL3 + 0x3 + + + + + PLL3SRCRDY + PLL3 source clock switch status +Set and reset by hardware to indicate if the PLL3 clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The PLL3 switch is not ready or in position '11': no clock is generated on its output + 0x0 + + + B_0x1 + The PLL3 switch is ready: the clock switch is selecting the clock given by PLL3SRC[1:0] field. (default after reset) + 0x1 + + + + + + + RCC_RCK4SELR + RCC_RCK4SELR + RCC PLL4 reference clock selection register + 0x488 + 0x20 + 0x80000000 + + + PLL4SRC + Source clock selection for PLL4 +Written by software to select the PLL4 clock source. + 0 + 2 + read-write + + + B_0x0 + HSI selected as PLL clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as PLL clock (hse_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + Signal I2S_CKIN used as source clock + 0x3 + + + + + PLL4SRCRDY + PLL4 source clock switch status +Set and reset by hardware to indicate if the PLL4 clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The PLL4 switch is not ready or in position '11': no clock is generated on its output + 0x0 + + + B_0x1 + The PLL4 switch is ready: the clock switch is selecting the clock given by PLL4SRC[1:0] field. (default after reset) + 0x1 + + + + + + + RCC_PLL1CR + RCC_PLL1CR + RCC PLL1 control register + 0x4a0 + 0x20 + 0x00000000 + + + PLLON + PLL1 enable. + 0 + 1 + read-write + + + B_0x0 + PLL1 OFF (default after reset) + 0x0 + + + B_0x1 + PLL1 is ON, and ref1_ck is provided to the PLL1 + 0x1 + + + + + PLL1RDY + PLL1 clock ready flag +Set by hardware to indicate that the PLL1 is locked. + 1 + 1 + read-only + + + B_0x0 + PLL1 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL1 locked + 0x1 + + + + + SSCG_CTRL + Spread Spectrum Clock Generator of PLL1 enable +Set and reset by software to enable the spread spectrum clock generator of PLL1, in order to reduce the amount of EMI peaks. + 2 + 1 + read-write + + + B_0x0 + Clock Spreading Generator disabled (default after reset) + 0x0 + + + B_0x1 + Clock Spreading Generator enabled + 0x1 + + + + + DIVPEN + PLL1 DIVP divider output enable +Set and reset by software to enable the pll1_p_ck output of the PLL1. +In order to save power, when the pll1_p_ck is not needed, DIVPEN and DIVP must be set to '0'. + 4 + 1 + read-write + + + B_0x0 + pll1_p_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll1_p_ck output is enabled + 0x1 + + + + + DIVQEN + PLL1 DIVQ divider output enable +Set and reset by software to enable the pll1_q_ck output of the PLL1. +In order to save power, when the pll1_q_ck is not needed, DIVQEN and DIVQ must be set to '0'. + 5 + 1 + read-write + + + B_0x0 + pll1_q_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck output is enabled + 0x1 + + + + + DIVREN + PLL1 DIVR divider output enable +Set and reset by software to enable the pll1_r_ck output of the PLL1. +In order to save power, when the pll1_r_ck is not needed, DIVREN and DIVR must be set to '0'. + 6 + 1 + read-write + + + B_0x0 + pll1_r_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll1_r_ck output is enabled + 0x1 + + + + + + + RCC_PLL1CFGR1 + RCC_PLL1CFGR1 + RCC PLL1 configuration register 1 + 0x4a4 + 0x20 + 0x00010031 + + + DIVN + Multiplication factor for PLL1 VCO +Written by software to control the multiplication factor of the VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is: 992 to 1800 MHz. +VCO output frequency = Fref1_ck x 2 x (DIVN+1), when value 0 has been loaded into FRACV, with: +- Valid division ratios for DIVN: between 25 and 100 +- The input frequency Fref1_ck between 8 and 16 MHz +... +... +Others: wrong configurations + 0 + 9 + read-write + + + B_0x18 + Division ratio is 25 + 0x18 + + + B_0x19 + Division ratio is 26 + 0x19 + + + B_0x31 + Division ratio is 50 (default after reset) + 0x31 + + + B_0x63 + Division ratio is 100 + 0x63 + + + + + DIVM1 + Prescaler for PLL1 +Set and cleared by software to configure the prescaler of the PLL1. +... + 16 + 6 + read-write + + + B_0x0 + bypass + 0x0 + + + B_0x1 + division by 2 (default after reset) + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0x3F + division by 64 + 0x3F + + + + + + + RCC_PLL1CFGR2 + RCC_PLL1CFGR2 + RCC PLL1 configuration register 2 + 0x4a8 + 0x20 + 0x00010100 + + + DIVP + PLL1 DIVP division factor +Written by software to control the frequency of the pll1_p_ck clock. +Odd division factors are not recommended due to duty cycle degradation. +... + 0 + 7 + read-write + + + B_0x0 + pll1_p_ck = fout1_ck (default after reset) + 0x0 + + + B_0x1 + pll1_p_ck = fout1_ck / 2 + 0x1 + + + B_0x2 + pll1_p_ck = fout1_ck / 3 + 0x2 + + + B_0x7F + pll1_p_ck = fout1_ck / 128 + 0x7F + + + + + DIVQ + PLL1 DIVQ division factor +Written by software to control the frequency of the pll1_q_ck clock. +... + 8 + 7 + read-write + + + B_0x0 + pll1_q_ck = fout1_ck + 0x0 + + + B_0x1 + pll1_q_ck = fout1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_q_ck = fout1_ck / 3 + 0x2 + + + B_0x7F + pll1_q_ck = fout1_ck / 128 + 0x7F + + + + + DIVR + PLL1 DIVR division factor +Written by software to control the frequency of the pll1_r_ck clock. +... + 16 + 7 + read-write + + + B_0x0 + pll1_r_ck = fout1_ck + 0x0 + + + B_0x1 + pll1_r_ck = fout1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_r_ck = fout1_ck / 3 + 0x2 + + + B_0x7F + pll1_r_ck = fout1_ck / 128 + 0x7F + + + + + + + RCC_PLL1FRACR + RCC_PLL1FRACR + RCC PLL1 fractional register + 0x4ac + 0x20 + 0x00000000 + + + FRACV + Fractional part of the multiplication factor for PLL1 VCO +Written by software to control the fractional part of the multiplication factor of the VCO. +These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is: 800 to 1600 MHz +VCO output frequency = Fref1_ck x ((DIVN+1) + (FRACV / 8192)), with +- DIVN shall be between 4 and 512 +- FRACV can be between 0 and 8191 +- The input frequency Fref1_ck shall be between 4 and 16 MHz +In order to change the FRACV value on-the-fly even if the PLL is enabled, the application has to proceed as follow: +- set the bit FRACLE to '0', +- write the new fractional value into FRACV, +- set the bit FRACLE to '1'. + 3 + 13 + read-write + + + FRACLE + PLL1 fractional latch enable +Set and reset by software to latch the content of FRACV into the Sigma-Delta modulator. +In order to latch the FRACV value into the Sigma-Delta modulator, FRACLE must be set to '0', then set to '1': the transition 0 to '1' transfers the content of FRACV into the modulator. Refer to and for additional information on the PLL programming. + 16 + 1 + read-write + + + + + RCC_PLL1CSGR + RCC_PLL1CSGR + RCC PLL1 clock spreading generator register + 0x4b0 + 0x20 + 0x00000000 + + + MOD_PER + Modulation Period Adjustment for PLL1 +Written by software to adjust the modulation period of the clock spreading generator. + 0 + 13 + read-write + + + TPDFN_DIS + Dithering TPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + 13 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + RPDFN_DIS + Dithering RPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + 14 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + SSCG_MODE + Spread spectrum clock generator mode +Set and reset by software to select the clock spreading mode. + 15 + 1 + read-write + + + B_0x0 + Center-spread modulation selected (default after reset) + 0x0 + + + B_0x1 + Down-spread modulation selected + 0x1 + + + + + INC_STEP + Modulation Depth Adjustment for PLL1 +Written by software to adjust the modulation depth of the clock spreading generator. + 16 + 15 + read-write + + + + + RCC_PLL2CR + RCC_PLL2CR + RCC PLL2 control register + 0x4d0 + 0x20 + 0x00000000 + + + PLLON + PLL2 enable +Set and cleared by software to enable the PLL2. + 0 + 1 + read-write + + + B_0x0 + PLL2 OFF (default after reset) + 0x0 + + + B_0x1 + PLL2 ON, and ref2_ck is provided to the PLL2 + 0x1 + + + + + PLL2RDY + PLL2 clock ready flag +Set by hardware to indicate that the PLL2 is locked. + 1 + 1 + read-only + + + B_0x0 + PLL2 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL2 locked + 0x1 + + + + + SSCG_CTRL + Clock Spreading Generator of PLL2 enable +Set and reset by software to enable the clock spreading generator of PLL2, in order to reduce the amount of EMI peaks. + 2 + 1 + read-write + + + B_0x0 + Clock Spreading Generator disabled (default after reset) + 0x0 + + + B_0x1 + Clock Spreading Generator enabled + 0x1 + + + + + DIVPEN + PLL2 DIVP divider output enable +Set and reset by software to enable the pll2_p_ck output of the PLL2. +In order to save power, when the pll2_p_ck is not needed, DIVPEN and DIVP must be set to '0'. + 4 + 1 + read-write + + + B_0x0 + pll2_p_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck output is enabled + 0x1 + + + + + DIVQEN + PLL2 DIVQ divider output enable +Set and reset by software to enable the pll2_q_ck output of the PLL2. +In order to save power, when the pll2_q_ck is not needed, DIVQEN and DIVQ must be set to '0'. + 5 + 1 + read-write + + + B_0x0 + pll2_q_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck output is enabled + 0x1 + + + + + DIVREN + PLL2 DIVR divider output enable +Set and reset by software to enable the pll2_r_ck output of the PLL2. +In order to save power, when the pll2_r_ck is not needed, DIVREN and DIVR must be set to '0'. + 6 + 1 + read-write + + + B_0x0 + pll2_r_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll2_r_ck output is enabled + 0x1 + + + + + + + RCC_PLL2CFGR1 + RCC_PLL2CFGR1 + RCC PLL2 configuration register 1 + 0x4d4 + 0x20 + 0x00010063 + + + DIVN + Multiplication factor for PLL2 VCO +Written by software to control the multiplication factor of the VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is: 800 to 1600 MHz. +VCO output frequency = Fref2_ck x (DIVN+1), when value 0 has been loaded into FRACV, with: +- Valid division ratios for DIVN: between 25 and 100 +- The input frequency Fref2_ck between 8 and 16 MHz +Others: wrong configurations +... +... + 0 + 9 + read-write + + + B_0x18 + Division ratio is 25 + 0x18 + + + B_0x19 + Division ratio is 26 + 0x19 + + + B_0x31 + Division ratio is 50 + 0x31 + + + B_0x63 + Division ratio is 100 (default after reset) + 0x63 + + + + + DIVM2 + Prescaler for PLL2 +Set and cleared by software to configure the prescaler of the PLL2. +... + 16 + 6 + read-write + + + B_0x0 + bypass + 0x0 + + + B_0x1 + division by 2 (default after reset) + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0x3F + division by 64 + 0x3F + + + + + + + RCC_PLL2CFGR2 + RCC_PLL2CFGR2 + RCC PLL2 configuration register 2 + 0x4d8 + 0x20 + 0x00010101 + + + DIVP + PLL2 DIVP division factor +Written by software to control the frequency of the pll2_p_ck clock. +... + 0 + 7 + read-write + + + B_0x0 + pll2_p_ck = fout2_ck + 0x0 + + + B_0x1 + pll2_p_ck = fout2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_p_ck = fout2_ck / 3 + 0x2 + + + B_0x7F + pll2_p_ck = fout2_ck / 128 + 0x7F + + + + + DIVQ + PLL2 DIVQ division factor +Written by software to control the frequency of the pll2_q_ck clock. +... + 8 + 7 + read-write + + + B_0x0 + pll2_q_ck = fout2_ck + 0x0 + + + B_0x1 + pll2_q_ck = fout2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_q_ck = fout2_ck / 3 + 0x2 + + + B_0x7F + pll2_q_ck = fout2_ck / 128 + 0x7F + + + + + DIVR + PLL2 DIVR division factor +Written by software to control the frequency of the pll2_r_ck clock. +... + 16 + 7 + read-write + + + B_0x0 + pll2_r_ck = fout2_ck + 0x0 + + + B_0x1 + pll2_r_ck = fout2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_r_ck = fout2_ck / 3 + 0x2 + + + B_0x7F + pll2_r_ck = fout2_ck / 128 + 0x7F + + + + + + + RCC_PLL2FRACR + RCC_PLL2FRACR + RCC PLL2 fractional register + 0x4dc + 0x20 + 0x00000000 + + + FRACV + Fractional part of the multiplication factor for PLL2 VCO +Written by software to control the fractional part of the multiplication factor of the VCO. +These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is: 800 to 1600 MHz +VCO output frequency = Fref2_ck x ((DIVN+1) + (FRACV / 8192)), with +- DIVN shall be between 4 and 512 +- FRACV can be between 0 and 8191 +- The input frequency Fref2_ck shall be between 4 and 16 MHz +In order to change the FRACV value on-the-fly even if the PLL is enabled, the application has to proceed as follow: +- set the bit FRACLE to '0', +- write the new fractional value into FRACV, +- set the bit FRACLE to '1'. + 3 + 13 + read-write + + + FRACLE + PLL2 fractional latch enable +Set and reset by software to latch the content of FRACV into the Sigma-Delta modulator. +In order to latch the FRACV value into the Sigma-Delta modulator, FRACLE must be set to '0', then set to '1': the transition 0 to '1' transfers the content of FRACV into the modulator. Refer to and for additional information on the PLL programming. + 16 + 1 + read-write + + + + + RCC_PLL2CSGR + RCC_PLL2CSGR + RCC PLL2 clock spreading generator register + 0x4e0 + 0x20 + 0x00000000 + + + MOD_PER + Modulation Period Adjustment for PLL2 +Written by software to adjust the modulation period of the clock spreading generator. + 0 + 13 + read-write + + + TPDFN_DIS + Dithering TPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + 13 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + RPDFN_DIS + Dithering RPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + 14 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + SSCG_MODE + Spread spectrum clock generator mode +Set and reset by software to select the clock spreading mode. + 15 + 1 + read-write + + + B_0x0 + Center-spread modulation selected (default after reset) + 0x0 + + + B_0x1 + Down-spread modulation selected + 0x1 + + + + + INC_STEP + Modulation Depth Adjustment for PLL2 +Written by software to adjust the modulation depth of the clock spreading generator. + 16 + 15 + read-write + + + + + RCC_PLL3CR + RCC_PLL3CR + RCC PLL3 control register + 0x500 + 0x20 + 0x00000000 + + + PLLON + PLL3 enable + 0 + 1 + read-write + + + B_0x0 + PLL3 OFF (default after reset) + 0x0 + + + B_0x1 + PLL3 ON, and ref3_ck is provided to the PLL3 + 0x1 + + + + + PLL3RDY + PLL3 clock ready flag +Set by hardware to indicate that the PLL3 is locked. + 1 + 1 + read-only + + + B_0x0 + PLL3 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL3 locked + 0x1 + + + + + SSCG_CTRL + Clock Spreading Generator of PLL3 enable +Set and reset by software to enable the clock spreading generator of PLL3, in order to reduce the amount of EMI peaks. + 2 + 1 + read-write + + + B_0x0 + Clock Spreading Generator disabled (default after reset) + 0x0 + + + B_0x1 + Clock Spreading Generator enabled + 0x1 + + + + + DIVPEN + PLL3 DIVP divider output enable +Set and reset by software to enable the pll3_p_ck output of the PLL3. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll3_p_ck is not needed, DIVPEN and DIVP must be set to '0'. + 4 + 1 + read-write + + + B_0x0 + pll3_p_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll3_p_ck output is enabled + 0x1 + + + + + DIVQEN + PLL3 DIVQ divider output enable +Set and reset by software to enable the pll3_q_ck output of the PLL3. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll3_q_ck is not needed, DIVQEN and DIVQ must be set to '0'. + 5 + 1 + read-write + + + B_0x0 + pll3_q_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck output is enabled + 0x1 + + + + + DIVREN + PLL3 DIVR divider output enable +Set and reset by software to enable the pll3_r_ck output of the PLL3. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll3_r_ck is not needed, DIVREN and DIVR must be set to '0'. + 6 + 1 + read-write + + + B_0x0 + pll3_r_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck output is enabled + 0x1 + + + + + + + RCC_PLL3CFGR1 + RCC_PLL3CFGR1 + RCC PLL3 configuration register 1 + 0x504 + 0x20 + 0x00010031 + + + DIVN + Multiplication factor for PLL3 VCO +Written by software to control the multiplication factor of the VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is between 400 and 800 MHz. +VCO output frequency = Fref3_ck x (DIVN+1), when value 0 has been loaded into FRACV, with: +- Valid division ratios for DIVN: between 25 and 200 +- The input frequency Fref3_ck between 4 and 16 MHz +... +... +Others: wrong configurations + 0 + 9 + read-write + + + B_0x18 + Division ratio is 25 + 0x18 + + + B_0x19 + Division ratio is 26 + 0x19 + + + B_0x1A + Division ratio is 27 + 0x1A + + + B_0x31 + Division ratio is 50 (default after reset) + 0x31 + + + B_0xC7 + Division ratio is 200 + 0xC7 + + + + + DIVM3 + Prescaler for PLL3 +Set and cleared by software to configure the prescaler of the PLL3. +... + 16 + 6 + read-write + + + B_0x0 + bypass + 0x0 + + + B_0x1 + division by 2 (default after reset) + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0x3F + division by 64 + 0x3F + + + + + IFRGE + PLL3 input frequency range +Written by software to select the proper reference frequency range used for PLL3. +x0: The PLL3 input (ref3_ck) clock range frequency is between 4 and 8 MHz (default after reset) +x1: The PLL3 input (ref3_ck) clock range frequency is between 8 and 16 MHz. +Note that if ref3_ck is equal to 8 MHz, it is recommended to set IFRGE = 'x1’ + 24 + 2 + read-write + + + + + RCC_PLL3CFGR2 + RCC_PLL3CFGR2 + RCC PLL3 configuration register 2 + 0x508 + 0x20 + 0x00010101 + + + DIVP + PLL3 DIVP division factor +Written by software to control the frequency of the pll3_p_ck clock. +... + 0 + 7 + read-write + + + B_0x0 + pll3_p_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_p_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_p_ck = vco3_ck / 3 + 0x2 + + + B_0x7F + pll3_p_ck = vco3_ck / 128 + 0x7F + + + + + DIVQ + PLL3 DIVQ division factor +Written by software to control the frequency of the pll3_q_ck clock. +... + 8 + 7 + read-write + + + B_0x0 + pll3_q_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_q_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_q_ck = vco3_ck / 3 + 0x2 + + + B_0x7F + pll3_q_ck = vco3_ck / 128 + 0x7F + + + + + DIVR + PLL3 DIVR division factor +Written by software to control the frequency of the pll3_r_ck clock. +... + 16 + 7 + read-write + + + B_0x0 + pll3_r_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_r_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_r_ck = vco3_ck / 3 + 0x2 + + + B_0x7F + pll3_r_ck = vco3_ck / 128 + 0x7F + + + + + + + RCC_PLL3FRACR + RCC_PLL3FRACR + RCC PLL3 Fractional register + 0x50c + 0x20 + 0x00000000 + + + FRACV + Fractional part of the multiplication factor for PLL3 VCO +Written by software to control the fractional part of the multiplication factor of the VCO. +These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is between 400 and 800 MHz. +VCO output frequency = Fref3_ck x ((DIVN+1) + (FRACV / 8192)), with +- DIVN shall be between 4 and 512 +- FRACV can be between 0 and 8191 +- The input frequency Fref3_ck shall be between 1 and 16 MHz +In order to change the FRACV value on-the-fly even if the PLL is enabled, the application has to proceed as follow: +- set the bit FRACLE to '0', +- write the new fractional value into FRACV, +- set the bit FRACLE to '1'. + 3 + 13 + read-write + + + FRACLE + PLL3 fractional latch enable +Set and reset by software to latch the content of FRACV into the Sigma-Delta modulator. +In order to latch the FRACV value into the Sigma-Delta modulator, FRACLE must be set to '0', then set to '1': the transition 0 to '1' transfers the content of FRACV into the modulator. Refer to and for additional information on the PLL programming. + 16 + 1 + read-write + + + + + RCC_PLL3CSGR + RCC_PLL3CSGR + RCC PLL3 clock spreading generator register + 0x510 + 0x20 + 0x00000000 + + + MOD_PER + Modulation Period Adjustment for PLL3 +Written by software to adjust the modulation period of the clock spreading generator. + 0 + 13 + read-write + + + TPDFN_DIS + Dithering TPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + 13 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + RPDFN_DIS + Dithering RPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + 14 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + SSCG_MODE + Spread spectrum clock generator mode +Set and reset by software to select the clock spreading mode. + 15 + 1 + read-write + + + B_0x0 + Center-spread modulation selected (default after reset) + 0x0 + + + B_0x1 + Down-spread modulation selected + 0x1 + + + + + INC_STEP + Modulation Depth Adjustment for PLL3 +Written by software to adjust the modulation depth of the clock spreading generator. + 16 + 15 + read-write + + + + + RCC_PLL4CR + RCC_PLL4CR + RCC PLL4 control register + 0x520 + 0x20 + 0x00000000 + + + PLLON + PLL4 enable + 0 + 1 + read-write + + + B_0x0 + PLL4 OFF (default after reset) + 0x0 + + + B_0x1 + PLL4 ON, and ref4_ck is provided to the PLL4 + 0x1 + + + + + PLL4RDY + PLL4 clock ready flag +Set by hardware to indicate that the PLL4 is locked. + 1 + 1 + read-only + + + B_0x0 + PLL4 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL4 locked + 0x1 + + + + + SSCG_CTRL + Clock Spreading Generator of PLL4 enable +Set and reset by software to enable the clock spreading generator of PLL4, in order to reduce the amount of EMI peaks. + 2 + 1 + read-write + + + B_0x0 + Clock Spreading Generator disabled (default after reset) + 0x0 + + + B_0x1 + Clock Spreading Generator enabled + 0x1 + + + + + DIVPEN + PLL4 DIVP divider output enable +Set and reset by software to enable the pll4_p_ck output of the PLL4. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll4_p_ck is not needed, DIVPEN must be set to '0'. + 4 + 1 + read-write + + + B_0x0 + pll4_p_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll4_p_ck output is enabled + 0x1 + + + + + DIVQEN + PLL4 DIVQ divider output enable +Set and reset by software to enable the pll4_q_ck output of the PLL4. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll4_q_ck is not needed, DIVQEN must be set to '0'. + 5 + 1 + read-write + + + B_0x0 + pll4_q_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck output is enabled + 0x1 + + + + + DIVREN + PLL4 DIVR divider output enable +Set and reset by software to enable the pll4_r_ck output of the PLL4. +Cleared by hardware when entering a Stop mode or Standby. +In order to save power, when the pll4_r_ck is not needed, DIVREN must be set to '0'. + 6 + 1 + read-write + + + B_0x0 + pll4_r_ck output is disabled (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck output is enabled + 0x1 + + + + + + + RCC_PLL4CFGR1 + RCC_PLL4CFGR1 + RCC PLL4 configuration register 1 + 0x524 + 0x20 + 0x00010031 + + + DIVN + Multiplication factor for PLL4 VCO +Written by software to control the multiplication factor of the VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is between 400 and 800 MHz. +VCO output frequency = Fref4_ck x (DIVN+1), when value 0 has been loaded into FRACV, with: +- Valid division ratios for DIVN: between 25 and 200 +- The input frequency Fref4_ck between 4 and 16 MHz +... +... +Others: wrong configurations + 0 + 9 + read-write + + + B_0x18 + Division ratio is 25 + 0x18 + + + B_0x19 + Division ratio is 26 + 0x19 + + + B_0x1A + Division ratio is 27 + 0x1A + + + B_0x31 + Division ratio is 50 (default after reset) + 0x31 + + + B_0xC7 + Division ratio is 200 + 0xC7 + + + + + DIVM4 + Prescaler for PLL4 +Set and cleared by software to configure the prescaler of the PLL4. +... + 16 + 6 + read-write + + + B_0x0 + bypass + 0x0 + + + B_0x1 + division by 2 (default after reset) + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0x3F + division by 64 + 0x3F + + + + + IFRGE + PLL4 input frequency range +Written by software to select the proper reference frequency range used for PLL4. +x0: The PLL4 input (ref4_ck) clock range frequency is between 4 and 8 MHz (default after reset) +x1: The PLL4 input (ref4_ck) clock range frequency is between 8 and 16 MHz +Note that if ref3_ck is equal to 8 MHz, it is recommended to set IFRGE = 'x1’ + 24 + 2 + read-write + + + + + RCC_PLL4CFGR2 + RCC_PLL4CFGR2 + RCC PLL4 configuration register 2 + 0x528 + 0x20 + 0x00000000 + + + DIVP + PLL4 DIVP division factor +Written by software to control the frequency of the pll4_p_ck clock. +... + 0 + 7 + read-write + + + B_0x0 + pll4_p_ck = vco4_ck (default after reset) + 0x0 + + + B_0x1 + pll4_p_ck = vco4_ck / 2 + 0x1 + + + B_0x2 + pll4_p_ck = vco4_ck / 3 + 0x2 + + + B_0x7F + pll4_p_ck = vco4_ck / 128 + 0x7F + + + + + DIVQ + PLL4 DIVQ division factor +Written by software to control the frequency of the pll4_q_ck clock. +... + 8 + 7 + read-write + + + B_0x0 + pll4_q_ck = vco4_ck (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck = vco4_ck / 2 + 0x1 + + + B_0x2 + pll4_q_ck = vco4_ck / 3 + 0x2 + + + B_0x7F + pll4_q_ck = vco4_ck / 128 + 0x7F + + + + + DIVR + PLL4 DIVR division factor +Written by software to control the frequency of the pll4_r_ck clock. +... + 16 + 7 + read-write + + + B_0x0 + pll4_r_ck = vco4_ck (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck = vco4_ck / 2 + 0x1 + + + B_0x2 + pll4_r_ck = vco4_ck / 3 + 0x2 + + + B_0x7F + pll4_r_ck = vco4_ck / 128 + 0x7F + + + + + + + RCC_PLL4FRACR + RCC_PLL4FRACR + RCC PLL4 fractional register + 0x52c + 0x20 + 0x00000000 + + + FRACV + Fractional part of the multiplication factor for PLL4 VCO +Written by software to control the fractional part of the multiplication factor of the VCO. +These bits can be written at any time, allowing dynamic fine-tuning of the PLL4 VCO. +Warning: the software has to set correctly these bits to ensure that the VCO output frequency +is between its valid frequency range, which is between 400 and 800 MHz. +VCO output frequency = Fref4_ck x ((DIVN+1) + (FRACV / 8192)), with +- DIVN shall be between 4 and 512 +- FRACV can be between 0 and 8191 +- The input frequency Fref4_ck shall be between 1 and 16 MHz +In order to change the FRACV value on-the-fly even if the PLL is enabled, the application has to proceed as follow: +- set the bit FRACLE to '0', +- write the new fractional value into FRACV, +- set the bit FRACLE to '1'. + 3 + 13 + read-write + + + FRACLE + PLL4 fractional latch enable +Set and reset by software to latch the content of FRACV into the Sigma-Delta modulator. +In order to latch the FRACV value into the Sigma-Delta modulator, FRACLE must be set to '0', then set to '1': the transition 0 to '1' transfers the content of FRACV into the modulator. Refer to Section: Refer to and dividers for additional information. + 16 + 1 + read-write + + + + + RCC_PLL4CSGR + RCC_PLL4CSGR + RCC PLL4 clock spreading generator register + 0x530 + 0x20 + 0x00000000 + + + MOD_PER + Modulation Period Adjustment for PLL4 +Written by software to adjust the modulation period of the clock spreading generator. + 0 + 13 + read-write + + + TPDFN_DIS + Dithering TPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + 13 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + RPDFN_DIS + Dithering RPDF noise control +Set and reset by software. +This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + 14 + 1 + read-write + + + B_0x0 + Dithering noise injection enabled (default after reset) + 0x0 + + + B_0x1 + Dithering noise injection disabled + 0x1 + + + + + SSCG_MODE + Spread spectrum clock generator mode +Set and reset by software to select the clock spreading mode. + 15 + 1 + read-write + + + B_0x0 + Center-spread modulation selected (default after reset) + 0x0 + + + B_0x1 + Down-spread modulation selected + 0x1 + + + + + INC_STEP + Modulation Depth Adjustment for PLL4 +Written by software to adjust the modulation depth of the clock spreading generator. + 16 + 15 + read-write + + + + + RCC_MPCKSELR + RCC_MPCKSELR + RCC MPU clock selection register + 0x540 + 0x20 + 0x80000000 + + + MPUSRC + MPU clock switch +Written by software to select the MPU sub-system clock source (mpuss_ck). +Note that MPUDIV is disabled if MPUSRC[1:0] is different from '11'. +Be sure that MPUDIV is different from '000' before setting MPUSRC to '11'. + 0 + 2 + read-write + + + B_0x0 + HSI selected as MPU sub-system clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as MPU sub-system clock (hse_ck) + 0x1 + + + B_0x2 + PLL1 selected as MPU sub-system clock (pll1_p_ck) + 0x2 + + + B_0x3 + divided PLL1 pll1_p_ck clock is selected as MPU sub-system clock, c.f. RCC_MPCKDIVR.MPUDIV[3:0] + 0x3 + + + + + MPUSRCRDY + MPU clock switch status +Set and reset by hardware to indicate if the MPU clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The MPU switch is not ready: no clock is generated on its output + 0x0 + + + B_0x1 + The MPU switch is ready: the clock switch is selecting the clock given by MPUSRC field. (default after reset) + 0x1 + + + + + + + RCC_ASSCKSELR + RCC_ASSCKSELR + RCC AXI sub-system clock selection register. + 0x544 + 0x20 + 0x80000000 + + + AXISSRC + AXI sub-system clock switch +Written by software to select the AXI sub-system clock source (axiss_ck). +others: axiss_ck is gated + 0 + 3 + read-write + + + B_0x0 + HSI selected as AXI sub-system clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as AXI sub-system clock (hse_ck) + 0x1 + + + B_0x2 + PLL2 selected as AXI sub-system clock (pll2_p_ck) + 0x2 + + + + + AXISSRCRDY + AXI sub-system clock switch status +Set and reset by hardware to indicate if the AXI clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The AXI sub-system switch is not ready or in positions higher than '011': no clock is generated on its output + 0x0 + + + B_0x1 + The AXI sub-system switch is ready: the clock switch is selecting the clock given by AXISSRC field. (default after reset) + 0x1 + + + + + + + RCC_MSSCKSELR + RCC_MSSCKSELR + RCC MLAHB sub-system clock selection register + 0x548 + 0x20 + 0x80000000 + + + MLAHBSSRC + MLAHB sub-system clock switch +Written by software to select the MLAHB sub-system clock source (mlahbss_ck). +Reset by hardware in order to select hsi_ck when the system exits from one of the Stop modes. + 0 + 2 + read-write + + + B_0x0 + HSI selected as MLAHB sub-system clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + HSE selected as MLAHB sub-system clock (hse_ck) + 0x1 + + + B_0x2 + CSI selected as MLAHB sub-system clock (csi_ck) + 0x2 + + + B_0x3 + PLL3 selected as MLAHB sub-system clock (pll3_p_ck) + 0x3 + + + + + MLAHBSSRCRDY + MLAHB sub-system clock switch status +Set and reset by hardware to indicate if the MLAHB clock switch transition has been properly performed. + 31 + 1 + read-only + + + B_0x0 + The MLAHB sub-system switch is not ready or in positions higher than '011': no clock is generated on its output + 0x0 + + + B_0x1 + The MLAHB sub-system switch is ready: the clock switch is selecting the clock given by MLAHBSSRC field. (default after reset) + 0x1 + + + + + + + RCC_CPERCKSELR + RCC_CPERCKSELR + RCC common peripheral kernel clock selection register + 0x54c + 0x20 + 0x00000000 + + + CKPERSRC + Oscillator selection for kernel clock +Set and cleared by software. + 0 + 2 + read-write + + + B_0x0 + hsi_ker_ck clock selected (default after reset) + 0x0 + + + B_0x1 + csi_ker_ck clock selected + 0x1 + + + B_0x2 + hse_ker_ck clock selected + 0x2 + + + B_0x3 + Clock disabled + 0x3 + + + + + + + RCC_RTCDIVR + RCC_RTCDIVR + RCC RTC clock division register + 0x560 + 0x20 + 0x00000000 + + + RTCDIV + HSE division factor for RTC clock +Set and cleared by software to divide the HSE to generate a clock for RTC. +Caution: The software has to set these bits correctly to ensure that the clock supplied to the +RTC is lower than 4 MHz. These bits must be configured if needed before selecting the RTC +clock source. +Note that when the RTCSRC is different from 3, this divider is disabled (does not provide clock). +... + 0 + 6 + read-write + + + B_0x0 + HSE (default after reset) + 0x0 + + + B_0x1 + HSE/2 + 0x1 + + + B_0x2 + HSE/3 + 0x2 + + + B_0x3 + HSE/4 + 0x3 + + + B_0x3E + HSE/63 + 0x3E + + + B_0x3F + HSE/64 + 0x3F + + + + + + + RCC_MPCKDIVR + RCC_MPCKDIVR + RCC MPU clock divider register + 0x564 + 0x20 + 0x80000001 + + + MPUDIV + MPU Core clock divider +Written by software to control the MPU clock division factor when the MPUSRC is set to position 3. +It is possible to change this division ratio on-the-fly. It impacts only the frequency of the MPU clock. The clocks are divided with the new prescaler factor, from 1 to 16 pll1_p_ck cycles after MPUDIV update. The application can check if the new division factor is taken into account by reading back the MPUDIVRDY flag. Note that this divider is disabled if MPUSRC[1:0] is different from '11'. +0x<n>: The mpuss_ck is equal to pll1_p_ck divided by 0x<n>+1 + 0 + 4 + read-write + + + B_0x0 + The MPUDIV is disabled; i.e. no clock generated + 0x0 + + + B_0x1 + The mpuss_ck is equal to pll1_p_ck divided by 2 (default after reset) + 0x1 + + + B_0x2 + The mpuss_ck is equal to pll1_p_ck divided by 3 + 0x2 + + + B_0xF + The mpuss_ck is equal to pll1_p_ck divided by 16 + 0xF + + + + + MPUDIVRDY + MPU sub-system clock divider status +Set and reset by hardware to indicate if the new division factor is taken into account. +This bit significant only when MPUSRC[1:0] = '11'. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_AXIDIVR + RCC_AXIDIVR + RCC AXI clock divider register + 0x568 + 0x20 + 0x80000000 + + + AXIDIV + AXI, AHB5 and AHB6 clock divider +Written by software to control the AXI, AHB5 and AHB6 clock division factor. +It is possible to change this division ratio on-the-fly. It impacts the frequency of AXI, APB4, APB5 AHB5 and AHB6 clocks. +The clocks are divided with the new prescaler factor, from 1 to 4 axiss_ck cycles after AXIDIV +update. The application can check if the new division factor is taken into account by reading back the AXIDIVRDY flag. +others: axiss_ck / 4 + 0 + 3 + read-write + + + B_0x0 + axiss_ck (default after reset) + 0x0 + + + B_0x1 + axiss_ck / 2 + 0x1 + + + B_0x2 + axiss_ck / 3 + 0x2 + + + + + AXIDIVRDY + AXI sub-system clock divider status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_MLAHBDIVR + RCC_MLAHBDIVR + RCC MLAHB clock divider register + 0x56c + 0x20 + 0x80000000 + + + MLAHBDIV + MLAHB clock divider +Written by software to control the MLAHB clock division factor. +Changing this division ratio has an impact on the frequency of MLAHB clock, and all bus matrix clocks. The clocks are divided with the new prescaler factor, from 1 to 512 cycles of mlahbss_ck, after MLAHBDIV update. The application can check if the new division factor is taken into account by reading back the MLAHBDIVRDY flag. +others: mlahbss_ck divided by 512 + 0 + 4 + read-write + + + B_0x0 + mlahbss_ck not divided (default after reset) + 0x0 + + + B_0x1 + mlahbss_ck divided by 2 + 0x1 + + + B_0x2 + mlahbss_ck divided by 4 + 0x2 + + + B_0x3 + mlahbss_ck divided by 8 + 0x3 + + + B_0x4 + mlahbss_ck divided by 16 + 0x4 + + + B_0x5 + mlahbss_ck divided by 32 + 0x5 + + + B_0x6 + mlahbss_ck divided by 64 + 0x6 + + + B_0x7 + mlahbss_ck divided by 128 + 0x7 + + + B_0x8 + mlahbss_ck divided by 256 + 0x8 + + + + + MLAHBDIVRDY + MLAHB clock prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB1DIVR + RCC_APB1DIVR + RCC APB1 clock divider register + 0x570 + 0x20 + 0x80000000 + + + APB1DIV + APB1 clock divider +Written by software to control the APB1 clock division factor. +The APB1 peripheral clock is divided with the new prescaler factor, from 1 to 16 mlhclk cycles after APB1DIV update. The application can check if the new division factor is taken into account by reading back the APB1DIVRDY flag. +others: Not allowed + 0 + 3 + read-write + + + B_0x0 + mlhclk (default after reset) + 0x0 + + + B_0x1 + mlhclk / 2 + 0x1 + + + B_0x2 + mlhclk / 4 + 0x2 + + + B_0x3 + mlhclk / 8 + 0x3 + + + B_0x4 + mlhclk / 16 + 0x4 + + + + + APB1DIVRDY + APB1 clock prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB2DIVR + RCC_APB2DIVR + RCC APB2 clock divider register + 0x574 + 0x20 + 0x80000000 + + + APB2DIV + APB2 clock divider +Written by software to control the APB2 clock division factor. +The APB2 clock is divided with the new prescaler factor, from 1 to 16 mlhclk cycles after APB2DIV +update. The application can check if the new division factor is taken into account by reading back the APB2DIVRDY flag. +others: Not allowed + 0 + 3 + read-write + + + B_0x0 + mlhclk (default after reset) + 0x0 + + + B_0x1 + mlhclk / 2 + 0x1 + + + B_0x2 + mlhclk / 4 + 0x2 + + + B_0x3 + mlhclk / 8 + 0x3 + + + B_0x4 + mlhclk / 16 + 0x4 + + + + + APB2DIVRDY + APB2 clock prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB3DIVR + RCC_APB3DIVR + RCC APB3 clock divider register + 0x578 + 0x20 + 0x80000000 + + + APB3DIV + APB3 clock divider +Written by software to control the APB3 clock division factor. +The APB3 clock is divided by this new prescaler factor, from 1 to 16 hclk cycles after APB3DIV +update. The application can check if the new division factor is taken into account by reading back the APB3DIVRDY flag. +others: hclk / 16 + 0 + 3 + read-write + + + B_0x0 + hclk (default after reset) + 0x0 + + + B_0x1 + hclk / 2 + 0x1 + + + B_0x2 + hclk / 4 + 0x2 + + + B_0x3 + hclk / 8 + 0x3 + + + + + APB3DIVRDY + APB3 clock prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB4DIVR + RCC_APB4DIVR + RCC APB4 clock divider register. + 0x57c + 0x20 + 0x80000000 + + + APB4DIV + APB4 clock divider +Written by software to control the APB4 clock division factor. +It is possible to change this division ratio on-the-fly. It impacts only the frequency of APB4 clock. +The clocks are divided with the new prescaler factor, from 1 to 16 aclk cycles after APB4DIV +update. The application can check if the new division factor is taken into account by reading back the APB4DIVRDY flag. +others: aclk / 16 + 0 + 3 + read-write + + + B_0x0 + aclk (default after reset) + 0x0 + + + B_0x1 + aclk / 2 + 0x1 + + + B_0x2 + aclk / 4 + 0x2 + + + B_0x3 + aclk / 8 + 0x3 + + + + + APB4DIVRDY + APB4 clock divider status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB5DIVR + RCC_APB5DIVR + RCC APB5 clock divider register + 0x580 + 0x20 + 0x80000000 + + + APB5DIV + APB5 clock divider +Written by software to control the APB5 clock division factor. +It is possible to change this division ratio on-the-fly. It impacts only the frequency of APB5 clock. +The clocks are divided with the new prescaler factor, from 1 to 16 aclk cycles after APB5DIV +update. The application can check if the new division factor is taken into account by reading the APB5DIVRDY flag. +others: aclk / 16 + 0 + 3 + read-write + + + B_0x0 + aclk (default after reset) + 0x0 + + + B_0x1 + aclk / 2 + 0x1 + + + B_0x2 + aclk / 4 + 0x2 + + + B_0x3 + aclk / 8 + 0x3 + + + + + APB5DIVRDY + APB5 clock divider status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_APB6DIVR + RCC_APB6DIVR + RCC APB6 clock divider register + 0x584 + 0x20 + 0x80000000 + + + APB6DIV + APB6 clock divider +Written by software to control the APB6 clock division factor. +It is possible to change this division ratio on-the-fly. It impacts only the frequency of APB6 clock. +The clocks are divided with the new prescaler factor, from 1 to 16 aclk cycles after APB6DIV +update. The application can check if the new division factor is taken into account by reading the APB6DIVRDY flag. +others: aclk / 16 + 0 + 3 + read-write + + + B_0x0 + aclk (default after reset) + 0x0 + + + B_0x1 + aclk / 2 + 0x1 + + + B_0x2 + aclk / 4 + 0x2 + + + B_0x3 + aclk / 8 + 0x3 + + + + + APB6DIVRDY + APB6 clock divider status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account. (default after reset) + 0x1 + + + + + + + RCC_TIMG1PRER + RCC_TIMG1PRER + RCC APB1 timers group1 prescaler register. + 0x5a0 + 0x20 + 0x80000000 + + + TIMG1PRE + Timers clocks prescaler selection +This bit is set and reset by software to control the clock frequency of all the timers connected +to APB1 domain. +Refer to . + 0 + 1 + read-write + + + B_0x0 + The Timers kernel clock is equal to mlhclk if APB1DIV is corresponding to a division by 1 or 2, else it is equal to 2 x Fpclk1 (default after reset) + 0x0 + + + B_0x1 + The Timers kernel clock is equal to mlhclk if APB1DIV is corresponding to division by 1, 2 or 4, else it is equal to 4 x Fpclk1 + 0x1 + + + + + TIMG1PRERDY + Timers clocks prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account (default after reset). + 0x1 + + + + + + + RCC_TIMG2PRER + RCC_TIMG2PRER + RCC APB2 timers group2 prescaler register + 0x5a4 + 0x20 + 0x80000000 + + + TIMG2PRE + Timers clocks prescaler selection +This bit is set and reset by software to control the clock frequency of all the timers connected +to APB2 domain. +Refer to . + 0 + 1 + read-write + + + B_0x0 + The Timers kernel clock is equal to mlhclk if APB2DIV is corresponding to a division by 1 or 2, else it is equal to 2 x Fpclk2 (default after reset) + 0x0 + + + B_0x1 + The Timers kernel clock is equal to mlhclk if APB2DIV is corresponding to division by 1, 2 or 4, else it is equal to 4 x Fpclk2 + 0x1 + + + + + TIMG2PRERDY + Timers clocks prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account (default after reset). + 0x1 + + + + + + + RCC_TIMG3PRER + RCC_TIMG3PRER + RCC APB6 timers group3 prescaler register + 0x5a8 + 0x20 + 0x80000000 + + + TIMG3PRE + Timers clocks prescaler selection +This bit is set and reset by software to control the clock frequency of all the timers connected +to APB6 domain. +Refer to . + 0 + 1 + read-write + + + B_0x0 + The Timers kernel clock is equal to mlhclk if APB6DIV is corresponding to a division by 1 or 2, else it is equal to 2 x Fpclk6 (default after reset) + 0x0 + + + B_0x1 + The Timers kernel clock is equal to mlhclk if APB6DIV is corresponding to division by 1, 2 or 4, else it is equal to 4 x Fpclk6 + 0x1 + + + + + TIMG3PRERDY + Timers clocks prescaler status +Set and reset by hardware to indicate if the new division factor is taken into account. + 31 + 1 + read-only + + + B_0x0 + The new division factor is not yet taken into account. + 0x0 + + + B_0x1 + The new division factor is taken into account (default after reset). + 0x1 + + + + + + + RCC_DDRITFCR + RCC_DDRITFCR + RCC DDR interface control register + 0x5c0 + 0x20 + 0x000FD022 + + + DDRC1EN + DDRC port 1 peripheral clocks enable +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of ddrc_ker_ckg, aclk1_ddrc and pclk4_ddrc clocks. + 0 + 1 + read-write + + + B_0x0 + Means that the DDRC peripheral clocks are disabled + 0x0 + + + B_0x1 + Means that the DDRC peripheral clocks are enabled + 0x1 + + + + + DDRC1LPEN + DDRC port 1 peripheral clocks enable during CSleep mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of ddrc_ker_ckg, aclk1_ddrc and pclk4_ddrc in CSleep. + 1 + 1 + read-write + + + B_0x0 + means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DDRPHYCEN + DDRPHYC peripheral clocks enable +If DDRPHYC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of dphy_ker_ck and pclk4_dphy + 4 + 1 + read-write + + + B_0x0 + means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + means that the peripheral clocks are enabled + 0x1 + + + + + DDRPHYCLPEN + DDRPHYC peripheral clocks enable during CSleep mode +If DDRPHYC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of dphy_ker_ck and pclk4_dphy in CSleep + 5 + 1 + read-write + + + B_0x0 + means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DDRCAPBEN + DDRC APB clock enable +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of pclk4_ddrc clock. + 6 + 1 + read-write + + + B_0x0 + means that the APB clock is disabled + 0x0 + + + B_0x1 + means that the APB clock is enabled + 0x1 + + + + + DDRCAPBLPEN + DDRC APB clock enable during CSleep mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of pclk4_ddrc clock during CSleep mode. + 7 + 1 + read-write + + + B_0x0 + means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + means that the APB clock is enabled in CSleep + 0x1 + + + + + AXIDCGEN + AXIDCG enable during MPU CRun mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +When the dynamic clock gating is disabled, the clock is always provided to the DDRC if provided by the RCC. + 8 + 1 + read-write + + + B_0x0 + means that the dynamic clock gating of AXIDCG[2:1] is disabled during MPU CRun, + 0x0 + + + B_0x1 + means that the dynamic clock gating of AXIDCG[2:1] is enabled during MPU CRun + 0x1 + + + + + DDRPHYCAPBEN + DDRPHYC APB clock enable +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of pclk4_dphy clock. + 9 + 1 + read-write + + + B_0x0 + means that the APB clock is disabled + 0x0 + + + B_0x1 + means that the APB clock is enabled + 0x1 + + + + + DDRPHYCAPBLPEN + DDRPHYC APB clock enable during CSleep mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This bit is controlling the gating of pclk4_dphy clock during CSleep mode. + 10 + 1 + read-write + + + B_0x0 + means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + means that the APB clock is enabled in CSleep + 0x1 + + + + + KERDCG_DLY + AXIDCG delay +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +It represents the delay between the falling edge of the cactive_ddrc signal and the moment where the KERDCG will gate the ddrc_ker_ckg. +... + 11 + 3 + read-write + + + B_0x0 + 1 period of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg. + 0x0 + + + B_0x1 + 3 periods of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg. + 0x1 + + + B_0x7 + 15 periods of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg + 0x7 + + + + + DDRCAPBRST + DDRC APB interface reset +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 14 + 1 + read-write + + + B_0x0 + does not reset the DDRC APB interface + 0x0 + + + B_0x1 + reset the DDRC APB interface + 0x1 + + + + + DDRCAXIRST + DDRC AXI interface reset +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 15 + 1 + read-write + + + B_0x0 + does not reset the DDRC AXI interface + 0x0 + + + B_0x1 + reset the DDRC AXI interface + 0x1 + + + + + DDRCORERST + DDRC core reset +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 16 + 1 + read-write + + + B_0x0 + does not reset the DDRC core + 0x0 + + + B_0x1 + reset the DDRC core + 0x1 + + + + + DPHYAPBRST + DDRPHYC APB interface reset +If DDRPHYC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 17 + 1 + read-write + + + B_0x0 + does not reset the DDRPHYC APB interface + 0x0 + + + B_0x1 + reset the DDRPHYC APB interface + 0x1 + + + + + DPHYRST + DDRPHYC reset +If DDRPHYC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 18 + 1 + read-write + + + B_0x0 + does not reset the DDRPHYC + 0x0 + + + B_0x1 + reset the DDRPHYC + 0x1 + + + + + DPHYCTLRST + DDRPHYC Control reset +If DDRPHYC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 19 + 1 + read-write + + + B_0x0 + does not reset the DDRPHYC Control + 0x0 + + + B_0x1 + reset the DDRPHYC Control + 0x1 + + + + + DDRCKMOD + RCC mode for DDR clock control +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +This mode can be used when the application wants to maintain a clock to the DLLs in order to avoid the re-lock sequences. In this mode it is recommended to have DDRCxEN = DDRCxLPEN = DDRPHYCEN = DDRPHYCLPEN = '1'. +This mode can be used when the DLLs are in bypass. In this mode it is recommended to have DDRCxEN = DDRCxLPEN = DDRPHYCEN = DDRPHYCLPEN = '1'. +This mode can be used when the application wants to maintain a clock to the DLLs. In this mode it is recommended to have DDRCxEN = DDRCxLPEN = DDRPHYCEN = DDRPHYCLPEN = '1'. +This mode can be used when the DLLs are in bypass. In this mode it is recommended to have DDRCxEN = DDRCxLPEN = DDRPHYCEN = DDRPHYCLPEN = '1'. +other: reserved + 20 + 3 + read-write + + + B_0x0 + Normal mode: the gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. The gating of the ddrc_ker_ckg clock depends on the DDRCxEN, DDRCxLPEN and MPU mode. This mode must be selected during DDRC and DDRPHYC initialization phase, and if the application is using the software self-refresh (SSR). + 0x0 + + + B_0x1 + Automatic Self-Refresh mode (ASR1): the clock ddrc_ker_ckg is gated automatically according to cactive_ddrc signal. The gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. + 0x1 + + + B_0x5 + Full Automatic Self-Refresh mode (ASR2): the clocks ddrc_ker_ckg and dphy_ker_ck are gated automatically according to cactive_ddrc signal. + 0x5 + + + B_0x2 + Hardware Self-Refresh mode (HSR1): the gating of the ddrc_ker_ckg clock is controlled by the AXI-Low-Power interface connected to the DDRC. The gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. + 0x2 + + + B_0x6 + Full Hardware Self-Refresh mode (HSR2): the gating of ddrc_ker_ckg and dphy_ker_ck clocks are controlled by the AXI-Low-Power interface connected to the DDRC. + 0x6 + + + + + GSKPMOD + Glitch Skipper (GSKP) Mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. + 23 + 1 + read-write + + + B_0x0 + The GSKP block is controlled by the GSKPCTRL bit + 0x0 + + + B_0x1 + The GSKP block is controlled automatically by the DFI + 0x1 + + + + + GSKPCTRL + Glitch skipper (GSKP) control +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set and clear by software. +This has effect only if GSKPMOD = '0'. + 24 + 1 + read-write + + + B_0x0 + The GSKP block is providing the clock phy_out_ck (provided by the DDRPHYC) + 0x0 + + + B_0x1 + The GSKP block is providing the clock dphy_ker_ck (provided by the RCC) + 0x1 + + + + + DFILP_WIDTH + Minimum duration of low-power request command +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +The low power request duration must always be bigger or equal to 1 microsecond. If this duration is not respected, the DDR interface behavior is not guaranteed. The application has to program properly DFILP_WIDTH in order to ensure a delay bigger or equal to 1 microsecond. Note that the delay is also dependent of the frequency of the dphy_ker_ck clock. +Others: Forces a delay of 544 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 410 and 533MHz + 25 + 3 + read-write + + + B_0x0 + Bypass, delay disabled + 0x0 + + + B_0x1 + Forces a delay of 160 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 120 and 160 MHz + 0x1 + + + B_0x2 + Forces a delay of 224 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 160 and 220 MHz + 0x2 + + + B_0x3 + Forces a delay of 320 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 220 and 320 MHz + 0x3 + + + B_0x4 + Forces a delay of 416 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 320 and 410 MHz + 0x4 + + + + + GSKP_DUR + Glitch skipper duration in automatic mode +If DDRC block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +This field allow the application to define the amount of time where the glitch skipper is providing the clock dphy_ker_ck instead of the clock ddrc_ker_ck to the DDRC block. This feature is only working when the glitch skipper is set in automatic mode (GSKPMOD = '1'). +This delay is equal to (GSKP_DUR + 1) x 32 x Tdphy_ker_ck +... + 28 + 4 + read-write + + + B_0x0 + Sets a delay of 32 x Tdphy_ker_ck + 0x0 + + + B_0x1 + Sets a delay of 2 x 32 x Tdphy_ker_ck + 0x1 + + + B_0x2 + Sets a delay of 3 x 32 x Tdphy_ker_ck + 0x2 + + + B_0xF + Sets a delay of 16 x 32 x Tdphy_ker_ck + 0xF + + + + + + + RCC_I2C12CKSELR + RCC_I2C12CKSELR + RCC I2C1 and I2C2 kernel clock selection register + 0x600 + 0x20 + 0x00000000 + + + I2C12SRC + I2C1 and I2C2 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk1 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_I2C345CKSELR + RCC_I2C345CKSELR + RCC I2C3, I2C4 and I2C5 kernel clock selection register. + 0x604 + 0x20 + 0x00000000 + + + I2C3SRC + I2C3 kernel clock source selection +If I2C3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + + + I2C4SRC + I2C4 kernel clock source selection +If I2C4 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 3 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + + + I2C5SRC + I2C5 kernel clock source selection +If I2C5 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 6 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_SPI2S1CKSELR + RCC_SPI2S1CKSELR + RCC SPI/I2S1 kernel clock selection register + 0x608 + 0x20 + 0x00000000 + + + SPI1SRC + SPI/I2S1 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pll4_p_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + I2S_CKIN clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + pll3_r_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_SPI2S23CKSELR + RCC_SPI2S23CKSELR + RCC SPI/I2S2 and SPI/I2S3 kernel clock selection register + 0x60c + 0x20 + 0x00000000 + + + SPI23SRC + SPI/I2S2 and SPI/I2S3 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pll4_p_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + I2S_CKIN clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + pll3_r_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_SPI45CKSELR + RCC_SPI45CKSELR + RCC SPI/I2S4 and SPI5 kernel clock selection register + 0x610 + 0x20 + 0x00000000 + + + SPI4SRC + SPI/I2S4 kernel clock source selection +If SPI/I2S4 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + B_0x5 + I2S_CKIN clock selected as kernel peripheral clock + 0x5 + + + + + SPI5SRC + SPI5 kernel clock source selection +If SPI5 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 3 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_UART12CKSELR + RCC_UART12CKSELR + RCC USART1 and USART2 kernel clock selection register + 0x614 + 0x20 + 0x00000000 + + + UART1SRC + USART1 kernel clock source selection +If USART1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + pll4_q_ck clock selected as kernel peripheral clock + 0x4 + + + B_0x5 + hse_ker_ck clock selected as kernel peripheral clock + 0x5 + + + + + UART2SRC + USART2 kernel clock source selection +If USART2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 3 + 3 + read-write + + + B_0x0 + pclk6 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + pll4_q_ck clock selected as kernel peripheral clock + 0x4 + + + B_0x5 + hse_ker_ck clock selected as kernel peripheral clock + 0x5 + + + + + + + RCC_UART35CKSELR + RCC_UART35CKSELR + RCC USART3 and UART5 kernel clock selection register + 0x618 + 0x20 + 0x00000000 + + + UART35SRC + USART3 and UART5 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk1 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_UART4CKSELR + RCC_UART4CKSELR + RCC UART4 kernel clock selection register + 0x61c + 0x20 + 0x00000000 + + + UART4SRC + UART4 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk1 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_UART6CKSELR + RCC_UART6CKSELR + RCC USART6 kernel clock selection register + 0x620 + 0x20 + 0x00000000 + + + UART6SRC + USART6 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk2 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_UART78CKSELR + RCC_UART78CKSELR + RCC UART7 and UART8 kernel clock selection register + 0x624 + 0x20 + 0x00000000 + + + UART78SRC + UART7 and UART8 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk1 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + csi_ker_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + hse_ker_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_LPTIM1CKSELR + RCC_LPTIM1CKSELR + RCC LPTIM1 kernel clock selection register + 0x628 + 0x20 + 0x00000000 + + + LPTIM1SRC + LPTIM1 kernel clock source selection +Written by software. +others: the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk1 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_p_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll3_q_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lse_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + lsi_ck clock selected as kernel peripheral clock + 0x4 + + + B_0x5 + per_ck clock selected as kernel peripheral clock + 0x5 + + + + + + + RCC_LPTIM23CKSELR + RCC_LPTIM23CKSELR + RCC LPTIM2 and LPTIM3 kernel clock selection register + 0x62c + 0x20 + 0x00000000 + + + LPTIM2SRC + LPTIM2 kernel clock source selection +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk3 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + per_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lse_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + lsi_ck clock selected as kernel peripheral clock + 0x4 + + + + + LPTIM3SRC + LPTIM3 kernel clock source selection +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 3 + 3 + read-write + + + B_0x0 + pclk3 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + per_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lse_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + lsi_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_LPTIM45CKSELR + RCC_LPTIM45CKSELR + RCC LPTIM4 and LPTIM5 kernel clock selection register + 0x630 + 0x20 + 0x00000000 + + + LPTIM45SRC + LPTIM4 and LPTIM5 kernel clock source selection +Written by software. +others: the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pclk3 clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_p_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll3_q_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lse_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + lsi_ck clock selected as kernel peripheral clock + 0x4 + + + B_0x5 + per_ck clock selected as kernel peripheral clock + 0x5 + + + + + + + RCC_SAI1CKSELR + RCC_SAI1CKSELR + RCC SAI1 kernel clock selection register + 0x634 + 0x20 + 0x00000000 + + + SAI1SRC + SAI1 and DFSDM kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pll4_q_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + I2S_CKIN clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + pll3_r_ck clock selected as kernel peripheral clock + 0x4 + + + + + + + RCC_SAI2CKSELR + RCC_SAI2CKSELR + RCC SAI2 kernel clock selection register + 0x638 + 0x20 + 0x00000000 + + + SAI2SRC + SAI2 kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + pll4_q_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + I2S_CKIN clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + B_0x4 + spdif_ck_symb clock from SPDIFRX selected as kernel peripheral clock + 0x4 + + + B_0x5 + pll3_r_ck clock selected as kernel peripheral clock + 0x5 + + + + + + + RCC_FDCANCKSELR + RCC_FDCANCKSELR + RCC FDCAN kernel clock selection register + 0x63c + 0x20 + 0x00000000 + + + FDCANSRC + FDCAN kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + hse_ker_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_q_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + pll4_r_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_SPDIFCKSELR + RCC_SPDIFCKSELR + RCC SPDIFRX kernel clock selection register + 0x640 + 0x20 + 0x00000000 + + + SPDIFSRC + SPDIFRX kernel clock source selection +Written by software. +others: reserved, the kernel clock is disabled + 0 + 2 + read-write + + + B_0x0 + pll4_p_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hsi_ker_ck clock selected as kernel peripheral clock + 0x2 + + + + + + + RCC_ADC12CKSELR + RCC_ADC12CKSELR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to control the selection of the kernel clock for the (AHB2) ADC1 and +ADC2 blocks. Note that changing the clock source on-the-fly is allowed, and will not +generate any timing violation, however the user has to ensure that both the previous and the +new clock sources are present during the switching, and for the whole transition time. Refer +to Section : Clock enabling delays. + 0x644 + 0x20 + 0x00000000 + + + ADC1SRC + ADC1 kernel clock source selection +If ADC1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 0 + 2 + read-write + + + B_0x0 + pll4_r_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + per_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll3_q_ck clock selected as kernel peripheral clock + 0x2 + + + + + ADC2SRC + ADC2 kernel clock source selection +If ADC2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 2 + 2 + read-write + + + B_0x0 + pll4_r_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + per_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll3_q_ck clock selected as kernel peripheral clock + 0x2 + + + + + + + RCC_SDMMC12CKSELR + RCC_SDMMC12CKSELR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to control the selection of the kernel clock for the (AHB6) SDMMC1 and +SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate +any timing violation, however the user has to ensure that both the previous and the new +clock sources are present during the switching, and for the whole transition time. Refer to +Section : Clock enabling delays. + 0x648 + 0x20 + 0x00000003 + + + SDMMC1SRC + SDMMC1 kernel clock source selection +If SDMMC1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 0 + 3 + read-write + + + B_0x0 + hclk6 clock selected as kernel peripheral clock + 0x0 + + + B_0x1 + pll3_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_p_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + hsi_ker_ck clock selected as kernel peripheral clock (default after reset) + 0x3 + + + + + SDMMC2SRC + SDMMC2 kernel clock source selection +If SDMMC2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: reserved, the kernel clock is disabled + 3 + 3 + read-write + + + B_0x0 + hclk6 clock selected as kernel peripheral clock + 0x0 + + + B_0x1 + pll3_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_p_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + hsi_ker_ck clock selected as kernel peripheral clock (default after reset) + 0x3 + + + + + + + RCC_ETH12CKSELR + RCC_ETH12CKSELR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to control the selection of the kernel clock for the ETH1 and ETH2 +blocks. Note that changing the clock source on-the-fly is allowed, and will not generate any +timing violation, however the user has to ensure that both the previous and the new clock +sources are present during the switching, and for the whole transition time. Refer to +Section : Clock enabling delays. + 0x64c + 0x20 + 0x00000000 + + + ETH1SRC + ETH1 kernel clock source selection +If ETH1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 0 + 2 + read-write + + + B_0x0 + pll4_p_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + + + ETH1PTPDIV + ETH1 clock divider for Precision Time Protocol (PTP) +If ETH1 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software to configure the divider value. +... + 4 + 4 + read-write + + + B_0x0 + bypass (default after reset) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + ETH2SRC + ETH2 kernel clock source selection +If ETH2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +others: the kernel clock is disabled + 8 + 2 + read-write + + + B_0x0 + pll4_p_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck clock selected as kernel peripheral clock + 0x1 + + + + + ETH2PTPDIV + ETH2 clock divider for Precision Time Protocol (PTP) +If ETH2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software to configure the divider value. +... + 12 + 4 + read-write + + + B_0x0 + bypass (default after reset) + 0x0 + + + B_0x1 + division by 2 + 0x1 + + + B_0x2 + division by 3 + 0x2 + + + B_0xF + division by 16 + 0xF + + + + + + + RCC_USBCKSELR + RCC_USBCKSELR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to control the selection of the kernel clock for the USBPHY PLL of the +USB Host (USBH) and the USB On-The-Go (USBO). It also controls the pre-divider for the +reference clock for the USBPHY. Note that changing the clock source on-the-fly is allowed, +and will not generate any timing violation, however the user has to ensure that both the +previous and the new clock sources are present during the switching, and for the whole +transition time. Refer to Section : Clock enabling delays. + 0x650 + 0x20 + 0x00000000 + + + USBPHYSRC + USB PHY kernel clock source selection +If USBPHY block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. +other: clock disabled + 0 + 2 + read-write + + + B_0x0 + hse_ker_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + hse_ker_ck/2 clock selected as kernel peripheral clock + 0x2 + + + + + USBOSRC + USB OTG kernel clock source selection +If USBO block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Written by software. + 4 + 1 + read-write + + + B_0x0 + pll4_r_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + clock provided by the USB PHY (rcc_ck_usbo_48m) selected as kernel peripheral clock + 0x1 + + + + + + + RCC_QSPICKSELR + RCC_QSPICKSELR + If (AHB6) QUADSPI is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +This register is used to control the selection of the kernel clock for the QUADSPI. Note that +changing the clock source on-the-fly is allowed, and will not generate any timing violation, +however the user has to ensure that both the previous and the new clock sources are +present during the switching, and for the whole transition time. Refer to Section : Clock +enabling delays. + 0x654 + 0x20 + 0x00000000 + + + QSPISRC + QUADSPI kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + aclk clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_p_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_FMCCKSELR + RCC_FMCCKSELR + If (AHB6) FMC is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +This register is used to control the selection of the kernel clock for the FMC block. Note that +changing the clock source on-the-fly is allowed, and will not generate any timing violation, +however the user has to ensure that both the previous and the new clock sources are +present during the switching, and for the whole transition time. Refer to Section : Clock +enabling delays. + 0x658 + 0x20 + 0x00000000 + + + FMCSRC + FMC kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + aclk clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_p_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_RNG1CKSELR + RCC_RNG1CKSELR + If (AHB5) RNG1 is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +This register is used to control the selection of the kernel clock for the RNG1. Note that +changing the clock source on-the-fly is allowed, and will not generate any timing violation, +however the user has to ensure that both the previous and the new clock sources are +present during the switching, and for the whole transition time. Refer to Section : Clock +enabling delays. + 0x65c + 0x20 + 0x00000000 + + + RNG1SRC + RNG1 kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + csi_ker_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll4_r_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + lse_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lsi_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_STGENCKSELR + RCC_STGENCKSELR + If (APB5) STGENC is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +STGEN is a dual APB interface IP, with STGENC APB5 controller part which may be secure +or non-secure depending on the corresponding DECPROT[1]. Its other STGENRO APB4 +read-only interface is non-secure. +This register is used to select the peripheral clock for the STGEN block. Note that this clock +is used to provide a time reference for the application. Refer to Section : Clock enabling +delays. + 0x660 + 0x20 + 0x00000000 + + + STGENSRC + Oscillator selection for kernel clock +Set and cleared by software. +others: Clock disabled + 0 + 2 + read-write + + + B_0x0 + hsi_ker_ck clock selected (default after reset) + 0x0 + + + B_0x1 + hse_ker_ck clock selected + 0x1 + + + + + + + RCC_DCMIPPCKSELR + RCC_DCMIPPCKSELR + If (APB4) DCMIPP is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +This register is used to control the selection of the kernel clock for the DCMIPP block. Note +that changing the clock source on-the-fly is allowed, and will not generate any timing +violation, however the user has to ensure that both the previous and the new clock sources +are present during the switching, and for the whole transition time. Refer to Section : Clock +enabling delays. + 0x664 + 0x20 + 0x00000000 + + + DCMIPPSRC + DCMIPP kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + aclk clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll4_p_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + per_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_SAESCKSELR + RCC_SAESCKSELR + If (AHB5) SAES is configured as secure via the corresponding DECPROT[1] field of the +ETZPC register, a write access to this register must be secure. A read access may be +secure or non-secure. +This register is used to control the selection of the kernel clock for the SAES block. Note that +changing the clock source on-the-fly is allowed, and will not generate any timing violation, +however the user has to ensure that both the previous and the new clock sources are +present during the switching, and for the whole transition time. Refer to Section : Clock +enabling delays. + 0x668 + 0x20 + 0x00000000 + + + SAESSRC + SAES kernel clock source selection +Written by software. + 0 + 2 + read-write + + + B_0x0 + axiss_ck clock selected as kernel peripheral clock (default after reset) + 0x0 + + + B_0x1 + per_ck clock selected as kernel peripheral clock + 0x1 + + + B_0x2 + pll_4_r_ck clock selected as kernel peripheral clock + 0x2 + + + B_0x3 + lsi_ck clock selected as kernel peripheral clock + 0x3 + + + + + + + RCC_APB1RSTSETR + RCC_APB1RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6a0 + 0x20 + 0x00000000 + + + TIM2RST + TIM2 block reset +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM3RST + TIM3 block reset +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM4RST + TIM4 block reset +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM5RST + TIM5 block reset +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM6RST + TIM6 block reset +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM7RST + TIM7 block reset +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM1RST + LPTIM1 block reset +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI2RST + SPI/I2S2 block reset +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI3RST + SPI3 block reset +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART3RST + USART3 block reset +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART4RST + UART4 block reset +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART5RST + UART5 block reset +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART7RST + UART7 block reset +Set by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART8RST + UART8 block reset +Set by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C1RST + I2C1 block reset +Set by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C2RST + I2C2 block reset +Set by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPDIFRST + SPDIFRX block reset +Set by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB1RSTCLRR + RCC_APB1RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6a4 + 0x20 + 0x00000000 + + + TIM2RST + TIM2 block reset +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM3RST + TIM3 block reset +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM4RST + TIM4 block reset +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM5RST + TIM5 block reset +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM6RST + TIM6 block reset +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM7RST + TIM7 block reset +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM1RST + LPTIM1 block reset +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI2RST + SPI2 block reset +Cleared by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI3RST + SPI3 block reset +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART3RST + USART3 block reset +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART4RST + UART4 block reset +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART5RST + UART5 block reset +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART7RST + UART7 block reset +Cleared by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + UART8RST + UART8 block reset +Cleared by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C1RST + I2C1 block reset +Cleared by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C2RST + I2C2 block reset +Cleared by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPDIFRST + SPDIFRX block reset +Cleared by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' release the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB2RSTSETR + RCC_APB2RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6a8 + 0x20 + 0x00000000 + + + TIM1RST + TIM1 block reset +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM8RST + TIM8 block reset +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI1RST + SPI/I2S1 block reset +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART6RST + USART6 block reset +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAI1RST + SAI1 block reset +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAI2RST + SAI2 block reset +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DFSDMRST + DFSDM block reset +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + FDCANRST + FDCAN block reset +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB2RSTCLRR + RCC_APB2RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6ac + 0x20 + 0x00000000 + + + TIM1RST + TIM1 block reset +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM8RST + TIM8 block reset +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI1RST + SPI/I2S1 block reset +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART6RST + USART6 block reset +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAI1RST + SAI1 block reset +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAI2RST + SAI2 block reset +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DFSDMRST + DFSDM block reset +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + FDCANRST + FDCAN block reset +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB3RSTSETR + RCC_APB3RSTSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6b0 + 0x20 + 0x00000000 + + + LPTIM2RST + LPTIM2 block reset +Set by software. +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM3RST + LPTIM3 block reset +Set by software. +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM4RST + LPTIM4 block reset +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM5RST + LPTIM5 block reset +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SYSCFGRST + SYSCFG block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + VREFRST + VREF block reset +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DTSRST + DTS block reset +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + PMBCTRLRST + PMBCTRL block reset +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + + + RCC_APB3RSTCLRR + RCC_APB3RSTCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6b4 + 0x20 + 0x00000000 + + + LPTIM2RST + LPTIM2 block reset +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM3RST + LPTIM3 block reset +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM4RST + LPTIM4 block reset +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + LPTIM5RST + LPTIM5 block reset +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SYSCFGRST + SYSCFG block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + VREFRST + VREF block reset +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DTSRST + DTS block reset +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + PMBCTRLRST + PMBCTRL block reset +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + + + RCC_APB4RSTSETR + RCC_APB4RSTSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6b8 + 0x20 + 0x00000000 + + + LTDCRST + LTDC block reset +If LTDC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DCMIPPRST + DCMIPP block reset +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DDRPERFMRST + DDRPERFM block reset +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBPHYRST + USBPHYC block reset +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB4RSTCLRR + RCC_APB4RSTCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6bc + 0x20 + 0x00000000 + + + LTDCRST + LTDC block reset +If LTDC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DCMIPPRST + DCMIPP block reset +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DDRPERFMRST + DDRPERFM block reset +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBPHYRST + USBPHYC block reset +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB5RSTSETR + RCC_APB5RSTSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6c0 + 0x20 + 0x00000000 + + + STGENRST + STGEN block reset +If STGENC (STGEN controller sub-part) is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB5RSTCLRR + RCC_APB5RSTCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6c4 + 0x20 + 0x00000000 + + + STGENRST + STGEN block reset +If STGENC (STGEN controller sub-part) is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB6RSTSETR + RCC_APB6RSTSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6c8 + 0x20 + 0x00000000 + + + USART1RST + USART1 block reset +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART2RST + USART2 block reset +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI4RST + SPI4 block reset +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI5RST + SPI5 block reset +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C3RST + I2C3 block reset +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C4RST + I2C4 block reset +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C5RST + I2C5 block reset +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM12RST + TIM12 block reset +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM13RST + TIM13 block reset +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM14RST + TIM14 block reset +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM15RST + TIM15 block reset +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM16RST + TIM16 block reset +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM17RST + TIM17 block reset +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_APB6RSTCLRR + RCC_APB6RSTCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6cc + 0x20 + 0x00000000 + + + USART1RST + USART1 block reset +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USART2RST + USART2 block reset +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI4RST + SPI4 block reset +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SPI5RST + SPI5 block reset +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C3RST + I2C3 block reset +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C4RST + I2C4 block reset +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + I2C5RST + I2C5 block reset +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM12RST + TIM12 block reset +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM13RST + TIM13 block reset +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM14RST + TIM14 block reset +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM15RST + TIM15 block reset +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM16RST + TIM16 block reset +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TIM17RST + TIM17 block reset +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB2RSTSETR + RCC_AHB2RSTSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6d0 + 0x20 + 0x00000000 + + + DMA1RST + DMA1 block reset +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMA2RST + DMA2 block reset +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMAMUX1RST + DMAMUX1 block reset +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMA3RST + DMA3 block reset +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMAMUX2RST + DMAMUX2 block reset +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ADC1RST + ADC1 block reset +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ADC2RST + ADC2 block reset +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBORST + USBO block reset +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB2RSTCLRR + RCC_AHB2RSTCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6d4 + 0x20 + 0x00000000 + + + DMA1RST + DMA1 block reset +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMA2RST + DMA2 block reset +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMAMUX1RST + DMAMUX1 block reset +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMA3RST + DMA3 block reset +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + DMAMUX2RST + DMAMUX2 block reset +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ADC1RST + ADC1 block reset +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ADC2RST + ADC2 block reset +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBORST + USBO block reset +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB4RSTSETR + RCC_AHB4RSTSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6e0 + 0x20 + 0x00000000 + + + GPIOARST + GPIOA block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOBRST + GPIOB block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOCRST + GPIOC block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIODRST + GPIOD block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOERST + GPIOE block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOFRST + GPIOF block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOGRST + GPIOG block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOHRST + GPIOH block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOIRST + GPIOI block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TSCRST + TSC block reset +If TSC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB4RSTCLRR + RCC_AHB4RSTCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6e4 + 0x20 + 0x00000000 + + + GPIOARST + GPIOA block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOBRST + GPIOB block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOCRST + GPIOC block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIODRST + GPIOD block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOERST + GPIOE block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOFRST + GPIOF block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOGRST + GPIOG block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOHRST + GPIOH block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + GPIOIRST + GPIOI block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + TSCRST + TSC block reset +If TSC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB5RSTSETR + RCC_AHB5RSTSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6e8 + 0x20 + 0x00000000 + + + PKARST + PKA block reset +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAESRST + SAES block reset +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + CRYP1RST + CRYP (3DES/AES) block reset +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + HASH1RST + HASH block reset +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + RNG1RST + RNG1 block reset +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + AXIMCRST + AXIMC block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB5RSTCLRR + RCC_AHB5RSTCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6ec + 0x20 + 0x00000000 + + + PKARST + PKA block reset +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SAESRST + SAES block reset +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + CRYP1RST + CRYP (3DES/AES) block reset +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + HASH1RST + HASH block reset +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + RNG1RST + RNG1 block reset +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + AXIMCRST + AXIMC block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB6RSTSETR + RCC_AHB6RSTSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to activate the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' +activates the reset of the corresponding peripheral. + 0x6f0 + 0x20 + 0x00000000 + + + MDMARST + MDMA block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + MCERST + MCE block reset +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ETH1MACRST + ETH1 MAC block reset +If ETH1 MAC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + FMCRST + FMC block reset +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + QSPIRST + QUADSPI and the QUADSPI delay block reset +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SDMMC1RST + SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SDMMC2RST + SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + CRC1RST + CRC block reset +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBHRST + USBH block reset +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ETH2MACRST + ETH2 MAC block reset +If ETH2 MAC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' asserts the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_AHB6RSTCLRR + RCC_AHB6RSTCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to release the reset of the corresponding peripheral. Writing '0' has no +effect, reading will return the effective values of the corresponding bits. Writing a '1' releases +the reset of the corresponding peripheral. + 0x6f4 + 0x20 + 0x00000000 + + + MDMARST + MDMA block reset +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + MCERST + MCE block reset +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ETH1MACRST + ETH1 MAC block reset +If ETH1 MAC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + FMCRST + FMC block reset +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + QSPIRST + QUADSPI and the QUADSPI delay block reset +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SDMMC1RST + SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + SDMMC2RST + SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + CRC1RST + CRC block reset +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + USBHRST + USBH block reset +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + ETH2MACRST + ETH2 MAC block reset +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the block reset is released + 0x0 + + + B_0x1 + Writing '1' releases the block reset, reading '1' means that the block reset is asserted + 0x1 + + + + + + + RCC_MP_APB1ENSETR + RCC_MP_APB1ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective value of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x700 + 0x20 + 0x00000000 + + + TIM2EN + TIM2 peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM3EN + TIM3 peripheral clocks enable +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM4EN + TIM4 peripheral clocks enable +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM5EN + TIM5 peripheral clocks enable +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM6EN + TIM6 peripheral clocks enable +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM7EN + TIM7 peripheral clocks enable +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM1EN + LPTIM1 peripheral clocks enable +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI2EN + SPI2 peripheral clocks enable +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI3EN + SPI3 peripheral clocks enable +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USART3EN + USART3 peripheral clocks enable +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART4EN + UART4 peripheral clocks enable +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART5EN + UART5 peripheral clocks enable +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART7EN + UART7 peripheral clocks enable +Set by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART8EN + UART8 peripheral clocks enable +Set by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + I2C1EN + I2C1 peripheral clocks enable +Set by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + I2C2EN + I2C2 peripheral clocks enable +Set by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPDIFEN + SPDIFRX peripheral clocks enable +Set by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB1ENCLRR + RCC_MP_APB1ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x704 + 0x20 + 0x00000000 + + + TIM2EN + TIM2 peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM3EN + TIM3 peripheral clocks enable +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM4EN + TIM4 peripheral clocks enable +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM5EN + TIM5 peripheral clocks enable +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM6EN + TIM6 peripheral clocks enable +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM7EN + TIM7 peripheral clocks enable +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM1EN + LPTIM1 peripheral clocks enable +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI2EN + SPI2 peripheral clocks enable +Cleared by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI3EN + SPI3 peripheral clocks enable +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USART3EN + USART3 peripheral clocks enable +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART4EN + UART4 peripheral clocks enable +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART5EN + UART5 peripheral clocks enable +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART7EN + UART7 peripheral clocks enable +Cleared by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + UART8EN + UART8 peripheral clocks enable +Cleared by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + I2C1EN + I2C1 peripheral clocks enable +Cleared by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + I2C2EN + I2C2 peripheral clocks enable +Cleared by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPDIFEN + SPDIFRX peripheral clocks enable +Cleared by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB2ENSETR + RCC_MP_APB2ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x708 + 0x20 + 0x00000000 + + + TIM1EN + TIM1 peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM8EN + TIM8 peripheral clocks enable +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI1EN + SPI/I2S1 peripheral clocks enable +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USART6EN + USART6 peripheral clocks enable +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAI1EN + SAI1 peripheral clocks enable +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAI2EN + SAI2 peripheral clocks enable +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DFSDMEN + DFSDM peripheral clocks enable +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADFSDMEN + Audio DFSDM peripheral clocks enable +Set by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + FDCANEN + FDCAN and CANRAM peripheral clocks enable +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB2ENCLRR + RCC_MP_APB2ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to ’0’. + 0x70c + 0x20 + 0x00000000 + + + TIM1EN + TIM1 peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TIM8EN + TIM8 peripheral clocks enable +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SPI1EN + SPI/I2S1 peripheral clocks enable +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USART6EN + USART6 peripheral clocks enable +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAI1EN + SAI1 peripheral clocks enable +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAI2EN + SAI2 peripheral clocks enable +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DFSDMEN + DFSDM peripheral clocks enable +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADFSDMEN + Audio DFSDM peripheral clocks enable +Cleared by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + FDCANEN + FDCAN and CANRAM peripheral clocks enable +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB3ENSETR + RCC_MP_APB3ENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x710 + 0x20 + 0x00000000 + + + LPTIM2EN + LPTIM2 peripheral clocks enable +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM3EN + LPTIM3 peripheral clocks enable +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM4EN + LPTIM4 peripheral clocks enable +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM5EN + LPTIM5 peripheral clocks enable +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + VREFEN + VREF peripheral clocks enable +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DTSEN + DTS peripheral clocks enable +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + PMBCTRLEN + PMBCTRL peripheral clocks enable +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + HDPEN + HDP peripheral clocks enable +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB3ENCLRR + RCC_MP_APB3ENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x714 + 0x20 + 0x00000000 + + + LPTIM2EN + LPTIM2 peripheral clocks enable +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM3EN + LPTIM3 peripheral clocks enable +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM4EN + LPTIM4 peripheral clocks enable +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + LPTIM5EN + LPTIM5 peripheral clocks enable +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + VREFEN + VREF peripheral clocks enable +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DTSEN + DTS peripheral clocks enable +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + PMBCTRLEN + PMBCTRL peripheral clocks enable +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + HDPEN + HDP peripheral clocks enable +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_APB3ENSETR + RCC_MP_S_APB3ENSETR + This is a secure register for enabling the clock of the SYSCFG. + 0x718 + 0x20 + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clocks enable +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_APB3ENCLRR + RCC_MP_S_APB3ENCLRR + This is a secure register for disabling the clock of the SYSCFG. A write access to this +register field must be secure. A read access may be secure or non-secure. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x71c + 0x20 + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clocks enable +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB3ENSETR + RCC_MP_NS_APB3ENSETR + This is a non-secure register, for enabling the clock of the SYSCFG. + 0x720 + 0x20 + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB3ENCLRR + RCC_MP_NS_APB3ENCLRR + This is a non-secure register, for disabling the clock of the SYSCFG. + 0x724 + 0x20 + 0x00000000 + + + SYSCFGEN + SYSCFG peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB4ENSETR + RCC_MP_APB4ENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x728 + 0x20 + 0x00000000 + + + DCMIPPEN + DCMIPP peripheral clocks enable +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DDRPERFMEN + DDRPERFM APB clock enable +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + IWDG2APBEN + IWDG2 APB clock enable +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + USBPHYEN + USBPHYC peripheral clocks enable +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + STGENROEN + STGEN read-only interface peripheral clocks enable +Set by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled, and that the kernel clock gating is defined by RCC_MP_APB5ENxxxR.STGENCEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk4 and the kernel clock; reading '1' means that the pck4 and the kernel clock are enabled + 0x1 + + + + + + + RCC_MP_APB4ENCLRR + RCC_MP_APB4ENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x72c + 0x20 + 0x00000000 + + + DCMIPPEN + DCMIPP peripheral clocks enable +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DDRPERFMEN + DDRPERFM APB clock enable +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + IWDG2APBEN + IWDG2 APB clock enable +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + USBPHYEN + USBPHYC peripheral clocks enable +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + STGENROEN + STGEN read-only interface peripheral clocks enable +Cleared by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled, and that the kernel clock gating is defined by RCC_MP_APB5ENxxxR.STGENCEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' disables the pclk4, and disables the kernel clock provided that RCC_MP_APB5ENSETR.STGENCEN=0 else it has no effect; reading '1' means that the pck4 and the kernel clock are enabled + 0x1 + + + + + + + RCC_MP_S_APB4ENSETR + RCC_MP_S_APB4ENSETR + This is a secure register for enabling the clock of the LTDC when it is used with a secure +composition layer. A write access to this register field must be secure. A read access may +be secure or non-secure. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x730 + 0x20 + 0x00000000 + + + LTDCEN + LTDC peripheral clocks enable +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_APB4ENCLRR + RCC_MP_S_APB4ENCLRR + This is a secure register for enabling the clock of the LTDC when it is used with a secure +composition layer. + 0x734 + 0x20 + 0x00000000 + + + LTDCEN + LTDC peripheral clocks enable +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB4ENSETR + RCC_MP_NS_APB4ENSETR + This is a non-secure register, for enabling the clock of the LTDC when it is used with one or +two non-secure composition layers. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x738 + 0x20 + 0x00000000 + + + LTDCEN + LTDC peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB4ENCLRR + RCC_MP_NS_APB4ENCLRR + This is a non-secure register, for enabling the clock of the LTDC when it is used with one or +two non-secure composition layers. + 0x73c + 0x20 + 0x00000000 + + + LTDCEN + LTDC peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB5ENSETR + RCC_MP_APB5ENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x740 + 0x20 + 0x00000000 + + + RTCAPBEN + RTC APB clock enable +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TZCEN + TZC clocks enable +Set by (secure) software. +See for details. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the pclk5 and aclk_tzc1 clocks, reading '1' means that the clocks are enabled + 0x1 + + + + + ETZPCEN + ETZPC peripheral clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + IWDG1APBEN + IWDG1 APB clock enable +If IWDG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + BSECEN + BSEC peripheral clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + STGENCEN + STGEN controller part, peripheral clocks enable +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled, and that the kernel clock gating is defined by RCC_MP_APB4ENxxxR.STGENROEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk5 and the kernel clock; reading '1' means that the pck5 and the kernel clock are enabled + 0x1 + + + + + + + RCC_MP_APB5ENCLRR + RCC_MP_APB5ENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x744 + 0x20 + 0x00000000 + + + RTCAPBEN + RTC APB clock enable +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + TZCEN + TZC clocks enable +Cleared by (secure) software. +See for details. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the pclk5 and aclk_tzc1 clocks, reading '1' means that the clocks are enabled + 0x1 + + + + + ETZPCEN + ETZPC peripheral clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + IWDG1APBEN + IWDG1 APB clock enable +If IWDG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the APB clock, reading '1' means that the APB clock is enabled + 0x1 + + + + + BSECEN + BSEC peripheral clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + STGENCEN + STGEN controller part, peripheral clocks enable +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled, and that the kernel clock gating is defined by RCC_MP_APB4ENxxxR.STGENROEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk5, and disables the kernel clock provided that RCC_MP_APB4ENSETR.STGENROEN=0 else it has no effect; reading '1' means that the pck5 and the kernel clock are enabled + 0x1 + + + + + + + RCC_MP_APB6ENSETR + RCC_MP_APB6ENSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x748 + 0x20 + 0x00000000 + + + USART1EN + USART1 peripherals clocks +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + USART2EN + USART2 peripherals clocks +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + SPI4EN + SPI4 peripherals clocks +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + SPI5EN + SPI5 peripherals clocks +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C3EN + I2C3 peripherals clocks +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C4EN + I2C4 peripherals clocks +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C5EN + I2C5 peripherals clocks +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM12EN + TIM12 peripherals clocks +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM13EN + TIM13 peripherals clocks +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM14EN + TIM14 peripherals clocks +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM15EN + TIM15 peripherals clocks +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM16EN + TIM16 peripherals clocks +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM17EN + TIM17 peripherals clocks +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + + + RCC_MP_APB6ENCLRR + RCC_MP_APB6ENCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x74c + 0x20 + 0x00000000 + + + USART1EN + USART1 peripherals clocks +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + USART2EN + USART2 peripherals clocks +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + SPI4EN + SPI4 peripherals clocks +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + SPI5EN + SPI5 peripherals clocks +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C3EN + I2C3 peripherals clocks +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C4EN + I2C4 peripherals clocks +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + I2C5EN + I2C5 peripherals clocks +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM12EN + TIM12 peripherals clocks +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM13EN + TIM13 peripherals clocks +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM14EN + TIM14 peripherals clocks +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM15EN + TIM15 peripherals clocks +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM16EN + TIM16 peripherals clocks +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + TIM17EN + TIM17 peripherals clocks +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks, reading '1' means that the peripherals clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB2ENSETR + RCC_MP_AHB2ENSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x750 + 0x20 + 0x00000000 + + + DMA1EN + DMA1 peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMA2EN + DMA2 peripheral clocks enable +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMAMUX1EN + DMAMUX1 peripheral clocks enable +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMA3EN + DMA3 peripheral clocks enable +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMAMUX2EN + DMAMUX2 peripheral clocks enable +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADC1EN + ADC1 peripheral clocks enable +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADC2EN + ADC2 peripheral clocks enable +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USBOEN + USBO peripheral clocks enable +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB2ENCLRR + RCC_MP_AHB2ENCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x754 + 0x20 + 0x00000000 + + + DMA1EN + DMA1 peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMA2EN + DMA2 peripheral clocks enable +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMAMUX1EN + DMAMUX1 peripheral clocks enable +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMA3EN + DMA3 peripheral clocks enable +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + DMAMUX2EN + DMAMUX2 peripheral clocks enable +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADC1EN + ADC1 peripheral clocks enable +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ADC2EN + ADC2 peripheral clocks enable +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USBOEN + USBO peripheral clocks enable +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB4ENSETR + RCC_MP_AHB4ENSETR + This register may be write-protected depending on the secure state of the TSC peripheral, +i.e. depending on the corresponding DECPROT[1] field of the ETZPC register. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x760 + 0x20 + 0x00000000 + + + TSCEN + TSC peripheral clocks enable +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB4ENCLRR + RCC_MP_AHB4ENCLRR + This register may be write-protected depending on the secure state of the TSC peripheral, +i.e. depending on the corresponding DECPROT[1] field of the ETZPC register. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x764 + 0x20 + 0x00000000 + + + TSCEN + TSC peripheral clocks enable +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_AHB4ENSETR + RCC_MP_S_AHB4ENSETR + This is a secure register, for enabling the clock of the secure (AHB4) GPIO ports, as defined +by the GPIO register file and more specifically the GPIOxSECCFGR.SECy control bit with +x=A..I, and y = 0..15 (or 2 for x=I). A write access to this register field must be secure. A +read access may be secure or non-secure. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x768 + 0x20 + 0x00000000 + + + GPIOAEN + GPIOA peripheral clocks enable +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOBEN + GPIOB peripheral clocks enable +Set by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOCEN + GPIOC peripheral clocks enable +Set by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIODEN + GPIOD peripheral clocks enable +Set by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOEEN + GPIOE peripheral clocks enable +Set by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOFEN + GPIOF peripheral clocks enable +Set by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOGEN + GPIOG peripheral clocks enable +Set by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOHEN + GPIOH peripheral clocks enable +Set by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOIEN + GPIOI peripheral clocks enable +Set by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_AHB4ENCLRR + RCC_MP_S_AHB4ENCLRR + This is a secure register, for disabling of the secure (AHB4) GPIO ports, as defined by the +GPIO register file and more specifically the GPIOxSECCFGR.SECy control bit with x=A..I, +and y = 0..15 (or 2 for x=I). A write access to this register field must be secure. A read +access may be secure or non-secure. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x76c + 0x20 + 0x00000000 + + + GPIOAEN + GPIOA peripheral clocks enable +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOBEN + GPIOB peripheral clocks enable +Cleared by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOCEN + GPIOC peripheral clocks enable +Cleared by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIODEN + GPIOD peripheral clocks enable +Cleared by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOEEN + GPIOE peripheral clocks enable +Cleared by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOFEN + GPIOF peripheral clocks enable +Cleared by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOGEN + GPIOG peripheral clocks enable +Cleared by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOHEN + GPIOH peripheral clocks enable +Cleared by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOIEN + GPIOI peripheral clocks enable +Cleared by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_AHB4ENSETR + RCC_MP_NS_AHB4ENSETR + This is a non-secure register, for enabling the non-secure GPIO ports, as defined by the +GPIO register file and more specifically the GPIOxSECCFGR.SECy control bit with x=A..I, +and y = 0..15 (or 2 for x=I). +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x770 + 0x20 + 0x00000000 + + + GPIOAEN + GPIOA peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOBEN + GPIOB peripheral clocks enable +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOCEN + GPIOC peripheral clocks enable +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIODEN + GPIOD peripheral clocks enable +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOEEN + GPIOE peripheral clocks enable +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOFEN + GPIOF peripheral clocks enable +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOGEN + GPIOG peripheral clocks enable +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOHEN + GPIOH peripheral clocks enable +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOIEN + GPIOI peripheral clocks enable +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_AHB4ENCLRR + RCC_MP_NS_AHB4ENCLRR + This is a non-secure register, for disabling the non-secure GPIO ports, as defined by the +GPIO register file and more specifically the GPIOxSECCFGR.SECy control bit with x=A..I, +and y = 0..15 (or 2 for x=I). +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x774 + 0x20 + 0x00000000 + + + GPIOAEN + GPIOA peripheral clocks enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOBEN + GPIOB peripheral clocks enable +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOCEN + GPIOC peripheral clocks enable +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIODEN + GPIOD peripheral clocks enable +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOEEN + GPIOE peripheral clocks enable +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOFEN + GPIOF peripheral clocks enable +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOGEN + GPIOG peripheral clocks enable +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOHEN + GPIOH peripheral clocks enable +Cleared by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + GPIOIEN + GPIOI peripheral clocks enable +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB5ENSETR + RCC_MP_AHB5ENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral to the MPU. Writing '0' has no effect, reading will return +the effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x778 + 0x20 + 0x00010000 + + + PKAEN + PKA peripheral clocks enable +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAESEN + SAES peripheral clocks enable +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + CRYP1EN + CRYP (3DES/AES) peripheral clocks enable +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + HASH1EN + HASH peripheral clocks enable +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + RNG1EN + RNG1 peripheral clocks enable +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + BKPSRAMEN + BKPSRAM clocks enable +If BKPSRAM is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + AXIMCEN + AXIMC clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB5ENCLRR + RCC_MP_AHB5ENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x77c + 0x20 + 0x00010000 + + + PKAEN + PKA peripheral clocks enable +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SAESEN + SAES peripheral clocks enable +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + CRYP1EN + CRYP (3DES/AES) peripheral clocks enable +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + HASH1EN + HASH peripheral clocks enable +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + RNG1EN + RNG1 peripheral clocks enable +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + BKPSRAMEN + BKPSRAM clocks enable +If BKPSRAM is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + AXIMCEN + AXIMC clocks enable +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_AHB6ENSETR + RCC_MP_AHB6ENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x780 + 0x20 + 0x00000000 + + + MCEEN + MCE peripheral clocks enable +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ETH1CKEN + Enable of the ETH1 clock generated by the RCC (eth1_ker_ck) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth1_ker_ck clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the eth1_ker_ck clock, reading '1' means that the eth1_ker_ck clock is enabled + 0x1 + + + + + ETH1TXEN + ETH1 transmission clock enable +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the transmission clock, reading '1' means that the transmission clock is enabled + 0x1 + + + + + ETH1RXEN + ETH1 reception clock enable +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the reception clock, reading '1' means that the reception clock is enabled + 0x1 + + + + + ETH1MACEN + ETH1 MAC bus interface clock enable (hclk6 and aclk) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the bus interface clock, reading '1' means that the bus interface clock is enabled + 0x1 + + + + + FMCEN + FMC peripheral clocks enable +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + QSPIEN + QUADSPI peripheral clocks enable +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SDMMC1EN + SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SDMMC2EN + SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + CRC1EN + CRC peripheral clocks enable +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USBHEN + USBH peripheral clocks enable +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ETH2CKEN + Enable of the ETH2 clock generated by the RCC (eth2_ker_ck) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 27 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth2_ker_ck clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the eth2_ker_ck clock, reading '1' means that the eth2_ker_ck clock is enabled + 0x1 + + + + + ETH2TXEN + ETH2 transmission clock enable +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 28 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the transmission clock, reading '1' means that the transmission clock is enabled + 0x1 + + + + + ETH2RXEN + ETH2 reception clock enable +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 29 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the reception clock, reading '1' means that the reception clock is enabled + 0x1 + + + + + ETH2MACEN + ETH2 MAC bus interface clock enable (hclk6 and aclk) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled + 0x0 + + + B_0x1 + Writing '1' enables the bus interface clock, reading '1' means that the bus interface clock is enabled + 0x1 + + + + + + + RCC_MP_AHB6ENCLRR + RCC_MP_AHB6ENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x784 + 0x20 + 0x00000000 + + + MCEEN + MCE peripheral clocks enable +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ETH1CKEN + Enable of the ETH1 clock generated by the RCC (eth1_ker_ck) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth1_ker_ck clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the eth1_ker_ck clock, reading '1' means that the eth1_ker_ck clock is enabled + 0x1 + + + + + ETH1TXEN + ETH1 transmission clock enable +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the transmission clock, reading '1' means that the transmission clock is enabled + 0x1 + + + + + ETH1RXEN + ETH1 reception clock enable +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the reception clock, reading '1' means that the reception clock is enabled + 0x1 + + + + + ETH1MACEN + ETH1 MAC bus interface clock enable (hclk6 and aclk) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the bus interface clock, reading '1' means that the bus interface clock is enabled + 0x1 + + + + + FMCEN + FMC peripheral clocks enable +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + QSPIEN + QUADSPI peripheral clocks enable +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SDMMC1EN + SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + SDMMC2EN + SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + CRC1EN + CRC peripheral clocks enable +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + USBHEN + USBH peripheral clocks enable +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + ETH2CKEN + Enable of the ETH2 clock generated by the RCC (eth2_ker_ck) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 27 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth2_ker_ck clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the eth2_ker_ck clock, reading '1' means that the eth2_ker_ck clock is enabled + 0x1 + + + + + ETH2TXEN + ETH2 transmission clock enable +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 28 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the transmission clock, reading '1' means that the transmission clock is enabled + 0x1 + + + + + ETH2RXEN + ETH2 reception clock enable +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 29 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the reception clock, reading '1' means that the reception clock is enabled + 0x1 + + + + + ETH2MACEN + ETH2 MAC bus interface clock enable (hclk6 and aclk) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled + 0x0 + + + B_0x1 + Writing '1' disables the bus interface clock, reading '1' means that the bus interface clock is enabled + 0x1 + + + + + + + RCC_MP_S_AHB6ENSETR + RCC_MP_S_AHB6ENSETR + This is a secure register for enabling the clock of the MDMA when it is used as secure. A +write access to this register field must be secure. A read access may be secure or non- +secure. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x788 + 0x20 + 0x00000000 + + + MDMAEN + MDMA peripheral clocks enable +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_AHB6ENCLRR + RCC_MP_S_AHB6ENCLRR + This is a secure register for disabling the clock of the MDMA when it is not used as secure. +A write access to this register field must be secure. A read access may be secure or non- +secure. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x78c + 0x20 + 0x00000000 + + + MDMAEN + MDMA peripheral clocks enable +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_AHB6ENSETR + RCC_MP_NS_AHB6ENSETR + This is a non-secure register for enabling the clock of the MDMA when it is used as non- +secure. +This register is used to set the peripheral clock enable bit of the corresponding peripheral. It +shall be used to allocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '1'. + 0x790 + 0x20 + 0x00000000 + + + MDMAEN + MDMA peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_AHB6ENCLRR + RCC_MP_NS_AHB6ENCLRR + This is a non-secure register for disabling the clock of the MDMA when it is not used as non- +secure. +This register is used to clear the peripheral clock enable bit of the corresponding peripheral. +It shall be used to deallocate a peripheral. Writing '0' has no effect, reading will return the +effective values of the corresponding bits. Writing a '1' sets the corresponding bit to '0'. + 0x794 + 0x20 + 0x00000000 + + + MDMAEN + MDMA peripheral clocks enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB1LPENSETR + RCC_MP_APB1LPENSETR + This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x800 + 0x20 + 0x046F9A3F + + + TIM2LPEN + TIM2 peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM3LPEN + TIM3 peripheral clocks enable during CSleep mode +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM4LPEN + TIM4 peripheral clocks enable during CSleep mode +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM5LPEN + TIM5 peripheral clocks enable during CSleep mode +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM6LPEN + TIM6 peripheral clocks enable during CSleep mode +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM7LPEN + TIM7 peripheral clocks enable during CSleep mode +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM1LPEN + LPTIM1 peripheral clocks enable during CSleep mode +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI2LPEN + SPI2 peripheral clocks enable during CSleep mode +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI3LPEN + SPI3 peripheral clocks enable during CSleep mode +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USART3LPEN + USART3 peripheral clocks enable during CSleep mode +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART4LPEN + UART4 peripheral clocks enable during CSleep mode +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART5LPEN + UART5 peripheral clocks enable during CSleep mode +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART7LPEN + UART7 peripheral clocks enable during CSleep mode +Set by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART8LPEN + UART8 peripheral clocks enable during CSleep mode +Set by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + I2C1LPEN + I2C1 peripheral clocks enable during CSleep mode +Set by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + I2C2LPEN + I2C2 peripheral clocks enable during CSleep mode +Set by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPDIFLPEN + SPDIFRX peripheral clocks enable during CSleep mode +Set by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB1LPENCLRR + RCC_MP_APB1LPENCLRR + This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x804 + 0x20 + 0x046F9A3F + + + TIM2LPEN + TIM2 peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM3LPEN + TIM3 peripheral clocks enable during CSleep mode +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM4LPEN + TIM4 peripheral clocks enable during CSleep mode +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM5LPEN + TIM5 peripheral clocks enable during CSleep mode +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM6LPEN + TIM6 peripheral clocks enable during CSleep mode +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM7LPEN + TIM7 peripheral clocks enable during CSleep mode +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM1LPEN + LPTIM1 peripheral clocks enable during CSleep mode +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI2LPEN + SPI2 peripheral clocks enable during CSleep mode +Cleared by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI3LPEN + SPI3 peripheral clocks enable during CSleep mode +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USART3LPEN + USART3 peripheral clocks enable during CSleep mode +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART4LPEN + UART4 peripheral clocks enable during CSleep mode +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART5LPEN + UART5 peripheral clocks enable during CSleep mode +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART7LPEN + UART7 peripheral clocks enable during CSleep mode +Cleared by software. + 18 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + UART8LPEN + UART8 peripheral clocks enable during CSleep mode +Cleared by software. + 19 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + I2C1LPEN + I2C1 peripheral clocks enable during CSleep mode +Cleared by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + I2C2LPEN + I2C2 peripheral clocks enable during CSleep mode +Cleared by software. + 22 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPDIFLPEN + SPDIFRX peripheral clocks enable during CSleep mode +Cleared by software. + 26 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB2LPENSETR + RCC_MP_APB2LPENSETR + This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x808 + 0x20 + 0x01332103 + + + TIM1LPEN + TIM1 peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM8LPEN + TIM8 peripheral clocks enable during CSleep mode +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI1LPEN + SPI/I2S1 peripheral clocks enable during CSleep mode +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USART6LPEN + USART6 peripheral clocks enable during CSleep mode +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAI1LPEN + SAI1 peripheral clocks enable during CSleep mode +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAI2LPEN + SAI2 peripheral clocks enable during CSleep mode +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DFSDMLPEN + DFSDM peripheral clocks enable during CSleep mode +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADFSDMLPEN + Audio DFSDM peripheral clocks enable during CSleep mode +Set by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + FDCANLPEN + FDCAN and CANRAM peripheral clocks enable during CSleep mode +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB2LPENCLRR + RCC_MP_APB2LPENCLRR + This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x80c + 0x20 + 0x01332103 + + + TIM1LPEN + TIM1 peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TIM8LPEN + TIM8 peripheral clocks enable during CSleep mode +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SPI1LPEN + SPI/I2S1 peripheral clocks enable during CSleep mode +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USART6LPEN + USART6 peripheral clocks enable during CSleep mode +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAI1LPEN + SAI1 peripheral clocks enable during CSleep mode +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAI2LPEN + SAI2 peripheral clocks enable during CSleep mode +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DFSDMLPEN + DFSDM peripheral clocks enable during CSleep mode +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADFSDMLPEN + Audio DFSDM peripheral clocks enable during CSleep mode +Cleared by software. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + FDCANLPEN + FDCAN and CANRAM peripheral clocks enable during CSleep mode +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB3LPENSETR + RCC_MP_APB3LPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x810 + 0x20 + 0x0003200F + + + LPTIM2LPEN + LPTIM2 peripheral clocks enable during CSleep mode +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM3LPEN + LPTIM3 peripheral clocks enable during CSleep mode +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM4LPEN + LPTIM4 peripheral clocks enable during CSleep mode +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM5LPEN + LPTIM5 peripheral clocks enable during CSleep mode +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + VREFLPEN + VREF peripheral clocks enable during CSleep mode +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DTSLPEN + DTS peripheral clocks enable during CSleep mode +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + PMBCTRLLPEN + PMBCTRL peripheral clocks enable during CSeep mode +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + + + RCC_MP_APB3LPENCLRR + RCC_MP_APB3LPENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x814 + 0x20 + 0x0003200F + + + LPTIM2LPEN + LPTIM2 peripheral clocks enable during CSleep mode +If LPTIM2 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM3LPEN + LPTIM3 peripheral clocks enable during CSleep mode +If LPTIM3 block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM4LPEN + LPTIM4 peripheral clocks enable during CSleep mode +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + LPTIM5LPEN + LPTIM5 peripheral clocks enable during CSleep mode +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + VREFLPEN + VREF peripheral clocks enable during CSleep mode +If VREF block is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DTSLPEN + DTS peripheral clocks enable during CSleep mode +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + PMBCTRLLPEN + PMBCTRL peripheral clocks enable during CSeep mode +(non-user): this bit is present in the RTL and is internally used as: +SPIRIT parameter RTLPRESENT + 17 + 1 + read-write + + + + + RCC_MP_S_APB3LPENSETR + RCC_MP_S_APB3LPENSETR + This is a secure register for enabling the clock of the SYSCFG. A write access to this +register field must be secure. A read access may be secure or non-secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x818 + 0x20 + 0x00000001 + + + SYSCFGLPEN + SYSCFG peripheral clocks enable during CSleep mode +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_APB3LPENCLRR + RCC_MP_S_APB3LPENCLRR + This is a secure register for disabling the clock of the SYSCFG. A write access to this +register field must be secure. A read access may be secure or non-secure. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x81c + 0x20 + 0x00000001 + + + SYSCFGLPEN + SYSCFG peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_APB3LPENSETR + RCC_MP_NS_APB3LPENSETR + This is a non-secure register, for enabling the clock of the SYSCFG. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x820 + 0x20 + 0x00000001 + + + SYSCFGLPEN + SYSCFG peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_APB3LPENCLRR + RCC_MP_NS_APB3LPENCLRR + This is a non-secure register, for disabling the clock of the SYSCFG. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x824 + 0x20 + 0x00000001 + + + SYSCFGLPEN + SYSCFG peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB4LPENSETR + RCC_MP_APB4LPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x828 + 0x20 + 0x00118102 + + + DCMIPPLPEN + DCMIPP peripheral clocks enable during CSleep mode +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DDRPERFMLPEN + DDRPERFM APB clock enable during CSleep mode +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + IWDG2APBLPEN + IWDG2 APB clock enable during CSleep mode +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + USBPHYLPEN + USBPHYC peripheral clocks enable during CSleep mode +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + STGENROLPEN + STGEN read-only interface peripheral clocks enable during CSleep mode +Set by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled in CSleep, and that the kernel clock gating is defined by RCC_MP_APB5ENxxxR.STGENCEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk4 and the kernel clock in CSleep; reading '1' means that the pck4 and the kernel clock are enabled in CSleep + 0x1 + + + + + STGENROSTPEN + STGEN read-only interface peripheral clocks enable during CStop mode +Set by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled in CStop, and that the kernel clock gating is defined by RCC_MP_APB5ENxxxR.STGENCEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk4 and the kernel clock in CStop; reading '1' means that the pck4 and the kernel clock are enabled in CStop + 0x1 + + + + + + + RCC_MP_APB4LPENCLRR + RCC_MP_APB4LPENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x82c + 0x20 + 0x00118102 + + + DCMIPPLPEN + DCMIPP peripheral clocks enable during CSleep mode +If DCMIPP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DDRPERFMLPEN + DDRPERFM APB clock enable during CSleep mode +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + IWDG2APBLPEN + IWDG2 APB clock enable during CSleep mode +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + USBPHYLPEN + USBPHYC peripheral clocks enable during CSleep mode +If USB PHY is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + STGENROLPEN + STGEN read-only interface peripheral clocks enable during CSleep mode +Cleared by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled in CSleep, and that the kernel clock gating is defined by RCC_MP_APB5LPENxxxR.STGENCLPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' disables the pclk4 and the kernel clock in CSleep; reading '1' means that the pck4 and the kernel clock are enabled in CSleep + 0x1 + + + + + STGENROSTPEN + STGEN read-only interface peripheral clocks enable during CStop mode +Cleared by software. +The peripheral clocks of the STGEN read-only interface are the pclk4, and the kernel clock as selected by the RCC_STGENCKSELR register. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk4 is disabled in CStop, and that the kernel clock gating is defined by RCC_MP_APB5LPENxxxR.STGENCLPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' disables the pclk4 and the kernel clock in CStop; reading '1' means that the pck4 and the kernel clock are enabled in CStop + 0x1 + + + + + + + RCC_MP_S_APB4LPENSETR + RCC_MP_S_APB4LPENSETR + This is a secure register for enabling the clock of the LTDC when it is used with a secure +composition layer. A write access to this register field must be secure. A read access may +be secure or non-secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x830 + 0x20 + 0x00000001 + + + LTDCLPEN + LTDC peripheral clocks enable during CSleep mode +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_S_APB4LPENCLRR + RCC_MP_S_APB4LPENCLRR + This is a secure register for disabling the clock of the LTDC when it is used with a secure +composition layer. A write access to this register field must be secure. A read access may +be secure or non-secure. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x834 + 0x20 + 0x00000001 + + + LTDCLPEN + LTDC peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB4LPENSETR + RCC_MP_NS_APB4LPENSETR + This is a non-secure register, for enabling the clock of the LTDC when it is used with one or +two non-secure composition layers. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x838 + 0x20 + 0x00000001 + + + LTDCLPEN + LTDC peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_NS_APB4LPENCLRR + RCC_MP_NS_APB4LPENCLRR + This is a non-secure register, for disabling the clock of the LTDC when it is used with one or +two non-secure composition layers. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x83c + 0x20 + 0x00000001 + + + LTDCLPEN + LTDC peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled + 0x1 + + + + + + + RCC_MP_APB5LPENSETR + RCC_MP_APB5LPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x840 + 0x20 + 0x0011A900 + + + RTCAPBLPEN + RTC APB clock enable during CSleep mode +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TZCLPEN + TZC clocks enable during CSleep mode +Set by (secure) software. +See for details. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the pclk5 and aclk_tzc1 clocks in CSleep, reading '1' means that the clocks are enabled in CSleep + 0x1 + + + + + ETZPCLPEN + ETZPC peripheral clocks enable during CSleep mode +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + IWDG1APBLPEN + IWDG1 APB clock enable during CSleep mode +If IWDG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + BSECLPEN + BSEC peripheral clocks enable during CSleep mode +A write access to this register field must be secure. A read access may be secure or non-secure. +Set by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + STGENCLPEN + STGEN controller part, peripheral clocks enable during CSleep mode +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled in CSleep, and that the kernel clock gating is defined by RCC_MP_APB4ENxxxR.STGENROLPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk5 and the kernel clock in CSleep; reading '1' means that the pck5 and the kernel clock are enabled in CSleep + 0x1 + + + + + STGENCSTPEN + STGEN controller part, peripheral clocks enable during CStop mode +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled in CStop, and that the kernel clock gating is defined by RCC_MP_APB4ENxxxR.STGENROSTPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' enables the pclk5 and the kernel clock in CStop; reading '1' means that the pck5 and the kernel clock are enabled in CStop + 0x1 + + + + + + + RCC_MP_APB5LPENCLRR + RCC_MP_APB5LPENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x844 + 0x20 + 0x0011A900 + + + RTCAPBLPEN + RTC APB clock enable during CSleep mode +If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + TZCLPEN + TZC clocks enable during CSleep mode +Cleared by (secure) software. +See for details. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the pclk5 and aclk_tzc1 clocks in CSleep, reading '1' means that the clocks are enabled in CSleep + 0x1 + + + + + ETZPCLPEN + ETZPC peripheral clocks enable during CSleep mode +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 13 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + IWDG1APBLPEN + IWDG1 APB clock enable during CSleep mode +If IWDG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the APB clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the APB clock in CSleep, reading '1' means that the APB clock is enabled in CSleep + 0x1 + + + + + BSECLPEN + BSEC peripheral clocks enable during CSleep mode +A write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by (secure) software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + STGENCLPEN + STGEN controller part, peripheral clocks enable during CSleep mode +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled in CSleep, and that the kernel clock gating is defined by RCC_MP_APB4LPENxxxR.STGENROLPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' disables the pclk5 and the kernel clock in CSleep; reading '1' means that the pck5 and the kernel clock are enabled in CSleep + 0x1 + + + + + STGENCSTPEN + STGEN controller part, peripheral clocks enable during CStop mode +If STGENC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. +The peripheral clocks of the STGEN controller part are the pclk5, and the kernel clock as selected by the RCC_STGENCKSELR register. + 21 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the pclk5 is disabled in CStop, and that the kernel clock gating is defined by RCC_MP_APB4LPENxxxR.STGENROSTPEN with xxx=SET/CLR + 0x0 + + + B_0x1 + Writing '1' disables the pclk5 and the kernel clock in CStop; reading '1' means that the pck5 and the kernel clock are enabled in CStop + 0x1 + + + + + + + RCC_MP_APB6LPENSETR + RCC_MP_APB6LPENSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x848 + 0x20 + 0x00001FFF + + + USART1LPEN + USART1 peripherals clocks during CSleep mode +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + USART2LPEN + USART2 peripherals clocks during CSleep mode +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + SPI4LPEN + SPI4 peripherals clocks during CSleep mode +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + SPI5LPEN + SPI5 peripherals clocks during CSleep mode +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C3LPEN + I2C3 peripherals clocks during CSleep mode +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C4LPEN + I2C4 peripherals clocks during CSleep mode +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C5LPEN + I2C5 peripherals clocks during CSleep mode +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM12LPEN + TIM12 peripherals clocks during CSleep mode +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM13LPEN + TIM13 peripherals clocks during CSleep mode +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM14LPEN + TIM14 peripherals clocks during CSleep mode +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM15LPEN + TIM15 peripherals clocks during CSleep mode +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM16LPEN + TIM16 peripherals clocks during CSleep mode +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM17LPEN + TIM17 peripherals clocks during CSleep mode +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_APB6LPENCLRR + RCC_MP_APB6LPENCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x84c + 0x20 + 0x00001FFF + + + USART1LPEN + USART1 peripherals clocks during CSleep mode +If USART1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + USART2LPEN + USART2 peripherals clocks during CSleep mode +If USART2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + SPI4LPEN + SPI4 peripherals clocks during CSleep mode +If SPI4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + SPI5LPEN + SPI5 peripherals clocks during CSleep mode +If SPI5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C3LPEN + I2C3 peripherals clocks during CSleep mode +If I2C3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C4LPEN + I2C4 peripherals clocks during CSleep mode +If I2C4 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + I2C5LPEN + I2C5 peripherals clocks during CSleep mode +If I2C5 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM12LPEN + TIM12 peripherals clocks during CSleep mode +If TIM12 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM13LPEN + TIM13 peripherals clocks during CSleep mode +If TIM13 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM14LPEN + TIM14 peripherals clocks during CSleep mode +If TIM14 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM15LPEN + TIM15 peripherals clocks during CSleep mode +If TIM15 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM16LPEN + TIM16 peripherals clocks during CSleep mode +If TIM16 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + TIM17LPEN + TIM17 peripherals clocks during CSleep mode +If TIM17 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripherals clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripherals clocks in CSleep, reading '1' means that the peripherals clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB2LPENSETR + RCC_MP_AHB2LPENSETR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x850 + 0x20 + 0x0000017F + + + DMA1LPEN + DMA1 peripheral clocks enable during Sleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMA2LPEN + DMA2 peripheral clocks enable during Sleep mode +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMAMUX1LPEN + DMAMUX1 peripheral clocks enable during Sleep mode +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMA3LPEN + DMA3 peripheral clocks enable during Sleep mode +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMAMUX2LPEN + DMAMUX2 peripheral clocks enable during Sleep mode +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADC1LPEN + ADC1 peripheral clocks enable during Sleep mode +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADC2LPEN + ADC2 peripheral clocks enable during Sleep mode +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USBOLPEN + USBO peripheral clocks enable during Sleep mode +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB2LPENCLRR + RCC_MP_AHB2LPENCLRR + This register may be separately and securely write-protected at a field level depending on +the secure state of the corresponding peripheral, i.e. depending on the corresponding +DECPROT[1] field of the ETZPC register. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x854 + 0x20 + 0x0000017F + + + DMA1LPEN + DMA1 peripheral clocks enable during Sleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMA2LPEN + DMA2 peripheral clocks enable during Sleep mode +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMAMUX1LPEN + DMAMUX1 peripheral clocks enable during Sleep mode +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMA3LPEN + DMA3 peripheral clocks enable during Sleep mode +If DMA3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + DMAMUX2LPEN + DMAMUX2 peripheral clocks enable during Sleep mode +If DMAMUX2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADC1LPEN + ADC1 peripheral clocks enable during Sleep mode +If ADC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ADC2LPEN + ADC2 peripheral clocks enable during Sleep mode +If ADC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USBOLPEN + USBO peripheral clocks enable during Sleep mode +If USBO is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB4LPENSETR + RCC_MP_AHB4LPENSETR + This register may be write-protected depending on the secure state of the TSC peripheral, +i.e. depending on the corresponding DECPROT[1] field of the ETZPC register. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x858 + 0x20 + 0x00008000 + + + TSCLPEN + TSC peripheral clocks enable during CSleep mode +Set by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB4LPENCLRR + RCC_MP_AHB4LPENCLRR + RCC AHB4 Sleep clock enable clear register + 0x85c + 0x20 + 0x00008000 + + + TSCLPEN + TSC peripheral clocks enable during CSleep mode +Cleared by software. + 15 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_AHB4LPENSETR + RCC_MP_S_AHB4LPENSETR + This is a secure register, for enabling the clock of the secure (AHB4) GPIO ports, as defined +by the GPIO register file and more specifically the GPIOxSECCFGR.SECy control bit with +x=A..I, and y = 0..15 (or 2 for x=I). A write access to this register field must be secure. A +read access may be secure or non-secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x868 + 0x20 + 0x000001FF + + + GPIOALPEN + GPIOA peripheral clocks enable during CSleep mode +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOBLPEN + GPIOB peripheral clocks enable during CSleep mode +Set by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOCLPEN + GPIOC peripheral clocks enable during CSleep mode +Set by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIODLPEN + GPIOD peripheral clocks enable during CSleep mode +Set by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOELPEN + GPIOE peripheral clocks enable during CSleep mode +Set by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOFLPEN + GPIOF peripheral clocks enable during CSleep mode +Set by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOGLPEN + GPIOG peripheral clocks enable during CSleep mode +Set by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOHLPEN + GPIOH peripheral clocks enable during CSleep mode +Set by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOILPEN + GPIOI peripheral clocks enable during CSleep mode +Set by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_AHB4LPENCLRR + RCC_MP_S_AHB4LPENCLRR + This is a secure register, for disabling the clock of the secure (AHB4) GPIO ports + 0x86c + 0x20 + 0x000001FF + + + GPIOALPEN + GPIOA peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOBLPEN + GPIOB peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOCLPEN + GPIOC peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIODLPEN + GPIOD peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOELPEN + GPIOE peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOFLPEN + GPIOF peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOGLPEN + GPIOG peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOHLPEN + GPIOH peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOILPEN + GPIOI peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AHB4LPENSETR + RCC_MP_NS_AHB4LPENSETR + This is a non-secure register, for enabling the clock of the non-secure (AHB4) GPIO ports, +as defined by the GPIO register file and more specifically the GPIOxSECCFGR.SECy +control bit with x=A..I, and y = 0..15 (or 2 for x=I). +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x870 + 0x20 + 0x000001FF + + + GPIOALPEN + GPIOA peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOBLPEN + GPIOB peripheral clocks enable during CSleep mode +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOCLPEN + GPIOC peripheral clocks enable during CSleep mode +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIODLPEN + GPIOD peripheral clocks enable during CSleep mode +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOELPEN + GPIOE peripheral clocks enable during CSleep mode +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOFLPEN + GPIOF peripheral clocks enable during CSleep mode +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOGLPEN + GPIOG peripheral clocks enable during CSleep mode +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOHLPEN + GPIOH peripheral clocks enable during CSleep mode +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOILPEN + GPIOI peripheral clocks enable during CSleep mode +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AHB4LPENCLRR + RCC_MP_NS_AHB4LPENCLRR + This is a non-secure register, for disabling the clock of the non-secure (AHB4) GPIO ports, +as defined by the GPIO register file and more specifically the GPIOxSECCFGR.SECy +control bit with x=A..I, and y = 0..15 (or 2 for x=I). + + 0x874 + 0x20 + 0x000001FF + + + GPIOALPEN + GPIOA peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOBLPEN + GPIOB peripheral clocks enable during CSleep mode +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOCLPEN + GPIOC peripheral clocks enable during CSleep mode +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIODLPEN + GPIOD peripheral clocks enable during CSleep mode +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOELPEN + GPIOE peripheral clocks enable during CSleep mode +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOFLPEN + GPIOF peripheral clocks enable during CSleep mode +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOGLPEN + GPIOG peripheral clocks enable during CSleep mode +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOHLPEN + GPIOH peripheral clocks enable during CSleep mode +Cleared by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + GPIOILPEN + GPIOI peripheral clocks enable during CSleep mode +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB5LPENSETR + RCC_MP_AHB5LPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x878 + 0x20 + 0x0000017C + + + PKALPEN + PKA peripheral clocks enable during CSleep mode +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAESLPEN + SAES peripheral clocks enable during CSleep mode +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + CRYP1LPEN + CRYP (3DES/AES) peripheral clocks enable during CSleep mode +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + HASH1LPEN + HASH peripheral clocks enable during CSleep mode +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + RNG1LPEN + RNG1 peripheral clocks enable during CSleep mode +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + BKPSRAMLPEN + BKPSRAM clocks enable during CSleep mode +If BKPSRAM is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB5LPENCLRR + RCC_MP_AHB5LPENCLRR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x87c + 0x20 + 0x0000017C + + + PKALPEN + PKA peripheral clocks enable during CSleep mode +If PKA is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SAESLPEN + SAES peripheral clocks enable during CSleep mode +If SAES is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + CRYP1LPEN + CRYP (3DES/AES) peripheral clocks enable during CSleep mode +If CRYP is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + HASH1LPEN + HASH peripheral clocks enable during CSleep mode +If HASH is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 5 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + RNG1LPEN + RNG1 peripheral clocks enable during CSleep mode +If RNG1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 6 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + BKPSRAMLPEN + BKPSRAM clocks enable during CSleep mode +If BKPSRAM is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_AHB6LPENSETR + RCC_MP_AHB6LPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x880 + 0x20 + 0x79135782 + + + MCELPEN + MCE peripheral clocks enable during CSleep mode +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ETH1CKLPEN + Enable of the ETH1 clock generated by the RCC (eth1_ker_ck) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth1_ker_ck clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the eth1_ker_ck clock in CSleep, reading '1' means that the eth1_ker_ck clock is enabled in CSleep + 0x1 + + + + + ETH1TXLPEN + ETH1 transmission clock enable during CSleep mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the transmission clock in CSleep, reading '1' means that the transmission clock is enabled in CSleep + 0x1 + + + + + ETH1RXLPEN + ETH1 reception clock enable during CSleep mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the reception clock in CSleep, reading '1' means that the reception clock is enabled in CSleep + 0x1 + + + + + ETH1MACLPEN + ETH1 MAC bus interface clock enable during CSleep mode (hclk6 and aclk) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the bus interface clock in CSleep, reading '1' means that the bus interface clock is enabled in CSleep + 0x1 + + + + + ETH1STPEN + ETH1 peripheral clock enable during CStop mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software in order to allow the ETH1 block to receive from pads ETH1_TX_CLK and ETH1_RX_CLK clocks during CStop. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the ETH1_TX_CLK and ETH1_RX_CLK clocks are disabled in CStop + 0x0 + + + B_0x1 + Writing '1' enables the ETH1_TX_CLK and ETH1_RX_CLK clocks in CStop, reading '1' means that the ETH1_TX_CLK and ETH1_RX_CLK clocks are enabled in CStop + 0x1 + + + + + FMCLPEN + FMC peripheral clocks enable during CSleep mode +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + QSPILPEN + QUADSPI peripheral clocks enable during CSleep mode +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SDMMC1LPEN + SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SDMMC2LPEN + SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + CRC1LPEN + CRC peripheral clocks enable during CSleep mode +Set by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USBHLPEN + USBH peripheral clocks enable during CSleep mode +Set by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ETH2CKLPEN + Enable of the ETH2 clock generated by the RCC (eth2_ker_ck) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 27 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth2_ker_ck clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the eth2_ker_ck clock in CSleep, reading '1' means that the eth2_ker_ck clock is enabled in CSleep + 0x1 + + + + + ETH2TXLPEN + ETH2 transmission clock enable during CSleep mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 28 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the transmission clock in CSleep, reading '1' means that the transmission clock is enabled in CSleep + 0x1 + + + + + ETH2RXLPEN + ETH2 reception clock enable during CSleep mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 29 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the reception clock in CSleep, reading '1' means that the reception clock is enabled in CSleep + 0x1 + + + + + ETH2MACLPEN + ETH2 MAC bus interface clock enable during CSleep mode (hclk6 and aclk) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the bus interface clock in CSleep, reading '1' means that the bus interface clock is enabled in CSleep + 0x1 + + + + + ETH2STPEN + ETH2 peripheral clock enable during CStop mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software in order to allow the ETH2 block to receive from pads ETH2_TX_CLK and ETH2_RX_CLK clocks during CStop. + 31 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the ETH2_TX_CLK and ETH2_RX_CLK clocks are disabled in CStop + 0x0 + + + B_0x1 + Writing '1' enables the ETH2_TX_CLK and ETH2_RX_CLK clocks in CStop, reading '1' means that the ETH2_TX_CLK and ETH2_RX_CLK clocks are enabled in CStop + 0x1 + + + + + + + RCC_MP_AHB6LPENCLRR + RCC_MP_AHB6LPENCLRR + This register may be separately and securely write-protected at a field level. + 0x884 + 0x20 + 0x79135782 + + + MCELPEN + MCE peripheral clocks enable during CSleep mode +If MCE is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ETH1CKLPEN + Enable of the ETH1 clock generated by the RCC (eth1_ker_ck) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 7 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth1_ker_ck clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the eth1_ker_ck clock in CSleep, reading '1' means that the eth1_ker_ck clock is enabled in CSleep + 0x1 + + + + + ETH1TXLPEN + ETH1 transmission clock enable during CSleep mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the transmission clock in CSleep, reading '1' means that the transmission clock is enabled in CSleep + 0x1 + + + + + ETH1RXLPEN + ETH1 reception clock enable during CSleep mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the reception clock in CSleep, reading '1' means that the reception clock is enabled in CSleep + 0x1 + + + + + ETH1MACLPEN + ETH1 MAC bus interface clock enable during CSleep mode (hclk6 and aclk) +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 10 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the bus interface clock in CSleep, reading '1' means that the bus interface clock is enabled in CSleep + 0x1 + + + + + ETH1STPEN + ETH1 peripheral clock enable during CStop mode +If ETH1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software in order to allow the ETH1 block to receive from pads ETH1_TX_CLK and ETH1_RX_CLK clocks during CStop. + 11 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the ETH1_TX_CLK and ETH1_RX_CLK clocks are disabled in CStop + 0x0 + + + B_0x1 + Writing '1' disables the ETH1_TX_CLK and ETH1_RX_CLK clocks in CStop, reading '1' means that the ETH1_TX_CLK and ETH1_RX_CLK clocks are enabled in CStop + 0x1 + + + + + FMCLPEN + FMC peripheral clocks enable during CSleep mode +If FMC is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 12 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + QSPILPEN + QUADSPI peripheral clocks enable during CSleep mode +If QSPI is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 14 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SDMMC1LPEN + SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode +If SDMMC1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + SDMMC2LPEN + SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode +If SDMMC2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + CRC1LPEN + CRC peripheral clocks enable during CSleep mode +Cleared by software. + 20 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + USBHLPEN + USBH peripheral clocks enable during CSleep mode +Cleared by software. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + ETH2CKLPEN + Enable of the ETH2 clock generated by the RCC (eth2_ker_ck) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 27 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that eth2_ker_ck clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the eth2_ker_ck clock in CSleep, reading '1' means that the eth2_ker_ck clock is enabled in CSleep + 0x1 + + + + + ETH2TXLPEN + ETH2 transmission clock enable during CSleep mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 28 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the transmission clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the transmission clock in CSleep, reading '1' means that the transmission clock is enabled in CSleep + 0x1 + + + + + ETH2RXLPEN + ETH2 reception clock enable during CSleep mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 29 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the reception clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the reception clock in CSleep, reading '1' means that the reception clock is enabled in CSleep + 0x1 + + + + + ETH2MACLPEN + ETH2 MAC bus interface clock enable during CSleep mode (hclk6 and aclk) +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 30 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the bus interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the bus interface clock in CSleep, reading '1' means that the bus interface clock is enabled in CSleep + 0x1 + + + + + ETH2STPEN + ETH2 peripheral clock enable during CStop mode +If ETH2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software in order to allow the ETH2 block to receive from pads ETH2_TX_CLK and ETH2_RX_CLK clocks during CStop. + 31 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the ETH2_TX_CLK and ETH2_RX_CLK clocks are disabled in CStop + 0x0 + + + B_0x1 + Writing '1' disables the ETH2_TX_CLK and ETH2_RX_CLK clocks in CStop, reading '1' means that the ETH2_TX_CLK and ETH2_RX_CLK clocks are enabled in CStop + 0x1 + + + + + + + RCC_MP_S_AHB6LPENSETR + RCC_MP_S_AHB6LPENSETR + This is a secure register for enabling the clock of the MDMA in Sleep mode when it is used +as secure. A write access to this register field must be secure. A read access may be secure +or non-secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x888 + 0x20 + 0x00000001 + + + MDMALPEN + MDMA peripheral clocks enable during CSleep mode +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_AHB6LPENCLRR + RCC_MP_S_AHB6LPENCLRR + This is a secure register for disabling the clock of the MDMA in Sleep mode when it is not +used as secure. A write access to this register field must be secure. A read access may be +secure or non-secure. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x88c + 0x20 + 0x00000001 + + + MDMALPEN + MDMA peripheral clocks enable during CSleep mode +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AHB6LPENSETR + RCC_MP_NS_AHB6LPENSETR + This is a non-secure register for enabling the clock of the MDMA in Sleep mode when it is +not used as secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x890 + 0x20 + 0x00000001 + + + MDMALPEN + MDMA peripheral clocks enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AHB6LPENCLRR + RCC_MP_NS_AHB6LPENCLRR + This is a non-secure register for disabling the clock of the MDMA in Sleep mode when it is +not used as secure. +This register is used in order to clear the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '0'. + 0x894 + 0x20 + 0x00000001 + + + MDMALPEN + MDMA peripheral clocks enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the peripheral clocks are disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the peripheral clocks in CSleep, reading '1' means that the peripheral clocks are enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_AXIMLPENSETR + RCC_MP_S_AXIMLPENSETR + This is a secure register, for enabling the clock of the SYSRAM during CSleep mode. A write +access to this register field must be secure. A read access may be secure or non-secure. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x898 + 0x20 + 0x00000001 + + + SYSRAMLPEN + SYSRAM interface clock enable during CSleep mode +Set by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the memory interface clock in CSleep, reading '1' means that the memory interface clock is enabled in CSleep + 0x1 + + + + + + + RCC_MP_S_AXIMLPENCLRR + RCC_MP_S_AXIMLPENCLRR + This is a secure register, for disabling the clock of the SYSRAM during CSleep mode. + 0x89c + 0x20 + 0x00000001 + + + SYSRAMLPEN + SYSRAM interface clock enable during CSleep mode +Cleared by (secure) software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the memory interface in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AXIMLPENSETR + RCC_MP_NS_AXIMLPENSETR + This is a non-secure register, for enabling the clock of the SYSRAM during CSleep mode. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x8a0 + 0x20 + 0x00000001 + + + SYSRAMLPEN + SYSRAM interface clock enable during CSleep mode +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the memory interface clock in CSleep, reading '1' means that the memory interface clock is enabled in CSleep + 0x1 + + + + + + + RCC_MP_NS_AXIMLPENCLRR + RCC_MP_NS_AXIMLPENCLRR + This is a non-secure register, for disabling the clock of the SYSRAM during CSleep mode. + 0x8a4 + 0x20 + 0x00000001 + + + SYSRAMLPEN + SYSRAM interface clock enable during CSleep mode +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the memory interface in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + + + RCC_MP_MLAHBLPENSETR + RCC_MP_MLAHBLPENSETR + This register may be separately and securely write-protected at a field level, as detailed in +the following register fields description. +This register is used in order to set the PERxLPEN bit of the corresponding peripheral. +Writing '0' has no effect, reading will return the effective values of the corresponding bits. +Writing a '1' sets the corresponding bit to '1'. + 0x8a8 + 0x20 + 0x00000007 + + + SRAM1LPEN + SRAM1 interface clock enable during CSleep mode +If SRAM1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + SRAM2LPEN + SRAM2 interface clock enable during CSleep mode +If SRAM2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + SRAM3LPEN + SRAM3 interface clock enable during CSleep mode +If SRAM3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Set by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' enables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + + + RCC_MP_MLAHBLPENCLRR + RCC_MP_MLAHBLPENCLRR + This register may be separately and securely write-protected at a field level + 0x8ac + 0x20 + 0x00000007 + + + SRAM1LPEN + SRAM1 interface clock enable during CSleep mode +If SRAM1 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + SRAM2LPEN + SRAM2 interface clock enable during CSleep mode +If SRAM2 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + SRAM3LPEN + SRAM3 interface clock enable during CSleep mode +If SRAM3 is configured as secure via the corresponding DECPROT[1] field of the ETZPC register, a write access to this register field must be secure. A read access may be secure or non-secure. +Cleared by software. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means that the memory interface clock is disabled in CSleep + 0x0 + + + B_0x1 + Writing '1' disables the memory interface clock in CSleep, reading '1' means that the memory interface is enabled in CSleep + 0x1 + + + + + + + RCC_APB3SECSR + RCC_APB3SECSR + This read register reflects at a bit level the secure state of each APB3 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8c0 + 0x20 + 0x00004003 + + + LPTIM2SECF + LPTIM2 block secure status flag + This bit reflects the LPTIM2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + LPTIM3SECF + LPTIM3 block secure status flag + This bit reflects the LPTIM3 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 1 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + VREFSECF + VREF block secure status flag + This bit reflects the VREF block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 13 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_APB4SECSR + RCC_APB4SECSR + This read register reflects at a bit level the secure state of each APB4 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8c4 + 0x20 + 0x00010002 + + + DCMIPPSECF + DCMIPP block secure status flag +This bit reflects the DCMIPP block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 1 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + USBPHYSECF + USBPHY block secure status flag +This bit reflects the USBPHY block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 16 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_APB5SECSR + RCC_APB5SECSR + This read register reflects at a bit level the secure state of each APB5 secure or securable +peripheral, as configured either via the corresponding DECPROT[1] field of the ETZPC +register or via the TrustZone-aware peripheral itself. + 0x8c8 + 0x20 + 0x0031A800 + + + RTCSECF + RTC block secure status flag +This bit reflects the RTC block secure state. If at least one function of the RTC is configured as secure via the RTC_SECCFGR register (i.e. if the input signal rtc_sec driven by RTC is asserted), this bit is asserted. + 8 + 1 + read-only + + + B_0x0 + peripheral is non-secure (default) + 0x0 + + + B_0x1 + peripheral is secure (at least one RTC sub-function) + 0x1 + + + + + TZCSECF + TZC block secure status flag +This bit reflects the TZC block secure state. + 11 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + ETZPCSECF + ETZPC block secure status flag +This bit reflects the ETZPC block secure state. + 13 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + IWDG1SECF + IWDG1 block secure status flag +This bit reflects the IWDG1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 15 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + BSECSECF + BSEC block secure status flag +This bit reflects the BSEC block secure state. + 16 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + STGENCSECF + STGENC block secure status flag +This field reflects the STGENC block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 20 + 2 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x3 + peripheral is secure + 0x3 + + + + + + + RCC_APB6SECSR + RCC_APB6SECSR + This read register reflects at a bit level the secure state of each APB6 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8cc + 0x20 + 0x00001FFF + + + USART1SECF + USART1 block secure status flag +This bit reflects the USART1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + USART2SECF + USART2 block secure status flag +This bit reflects the USART2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 1 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + SPI4SECF + SPI4 block secure status flag +This bit reflects the SPI4 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 2 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + SPI5SECF + SPI5 block secure status flag +This bit reflects the SPI5 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 3 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + I2C3SECF + I2C3 block secure status flag +This bit reflects the I2C3 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 4 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + I2C4SECF + I2C4 block secure status flag +This bit reflects the I2C4 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 5 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + I2C5SECF + I2C5 block secure status flag +This bit reflects the I2C5 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 6 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM12SECF + TIM12 block secure status flag +This bit reflects the TIM12 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 7 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM13SECF + TIM13 block secure status flag +This bit reflects the TIM13 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 8 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM14SECF + TIM14 block secure status flag +This bit reflects the TIM14 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 9 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM15SECF + TIM15 block secure status flag +This bit reflects the TIM15 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 10 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM16SECF + TIM16 block secure status flag +This bit reflects the TIM16 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 11 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + TIM17SECF + TIM17 block secure status flag +This bit reflects the TIM17 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 12 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_AHB2SECSR + RCC_AHB2SECSR + This read register reflects at a bit level the secure state of each AHB2 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8d0 + 0x20 + 0x00000178 + + + DMA3SECF + DMA3 block secure status flag +This bit reflects the DMA3 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 3 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + DMAMUX2SECF + DMAMUX2 block secure status flag +This bit reflects the DMAMUX2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 4 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + ADC1SECF + ADC1 block secure status flag +This bit reflects the ADC1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 5 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + ADC2SECF + ADC2 block secure status flag +This bit reflects the ADC2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 6 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + USBOSECF + USBO block secure status flag +This bit reflects the USBO block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 8 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_AHB4SECSR + RCC_AHB4SECSR + This read register reflects at a bit level the secure state of each AHB4 securable peripheral, +as configured either via the corresponding DECPROT[1] field of the ETZPC register or via +the TrustZone-aware peripheral itself. + 0x8d4 + 0x20 + 0x00004000 + + + TSCSECF + TSC block secure status flag +This bit reflects the TSC block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 15 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_AHB5SECSR + RCC_AHB5SECSR + This read register reflects at a bit level the secure state of each AHB5 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8d8 + 0x20 + 0x0000017C + + + PKASECF + PKA block secure status flag +This bit reflects the PKA block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 2 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + SAESSECF + SAES block secure status flag +This bit reflects the SAES block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 3 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + CRYP1SECF + CRYP1 block secure status flag +This bit reflects the CRYP1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 4 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + HASH1SECF + HASH1 block secure status flag +This bit reflects the HASH1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 5 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + RNG1SECF + RNG1 block secure status flag +This bit reflects the RNG1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 6 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + BKPSRAMSECF + BKPSRAM block secure status flag +This bit reflects the BKPSRAM block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 8 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + + + RCC_AHB6SECSR + RCC_AHB6SECSR + This read register reflects at a bit level the secure state of each AHB6 securable peripheral, +as configured via the corresponding DECPROT[1] field of the ETZPC register. + 0x8dc + 0x20 + 0xF8035F82 + + + MCESECF + MCE block secure status flag +This bit reflects the MCE block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 1 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + ETH1SECF + ETH1 block secure status flag +This field reflects the ETH1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 7 + 5 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1F + peripheral is secure + 0x1F + + + + + FMCSECF + FMC block secure status flag +This bit reflects the FMC block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 12 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + QSPISECF + QSPI block secure status flag +This bit reflects the QSPI block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 14 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + SDMMC1SECF + SDMMC1 block secure status flag +This bit reflects the SDMMC1 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 16 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + SDMMC2SECF + SDMMC2 block secure status flag +This bit reflects the SDMMC2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 17 + 1 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1 + peripheral is secure + 0x1 + + + + + ETH2SECF + ETH2 block secure status flag +This field reflects the ETH2 block secure state, as configured via the corresponding DECPROT[1] field of the ETZPC register. + 27 + 5 + read-only + + + B_0x0 + peripheral is non-secure + 0x0 + + + B_0x1F + peripheral is secure + 0x1F + + + + + + + RCC_VERR + RCC_VERR + This register gives the IP version + 0xff4 + 0x20 + 0x00000020 + + + MINREV + Minor Revision of the IP + 0 + 4 + read-only + + + MAJREV + Major Revision of the IP + 4 + 4 + read-only + + + + + RCC_IDR + RCC_IDR + This register gives the unique identifier of the RCC + 0xff8 + 0x20 + 0x00000001 + + + ID + Identifier of the RCC + 0 + 32 + read-only + + + + + RCC_SIDR + RCC_SIDR + This register gives the decoding space, which is for the RCC of 4 kB. + 0xffc + 0x20 + 0xA3C5DD04 + + + SID + Decoding space is 4 kbytes + 0 + 32 + read-only + + + + + + + RNG + RNG + RNG + 0x54004000 + + 0x0 + 0x400 + registers + + + RNG + RNG interrupt + 113 + + + + RNG_CR + RNG_CR + RNG control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt Enable + 3 + 1 + read-write + + + B_0x0 + RNG Interrupt is disabled + 0x0 + + + B_0x1 + RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or CEIS=1 in the RNG_SR register. + 0x1 + + + + + CED + Clock error detection +The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled. + 5 + 1 + read-write + + + B_0x0 + Clock error detection is enable + 0x0 + + + B_0x1 + Clock error detection is disable + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data Ready +Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. +Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR register). +If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1. + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status +Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. + 0x0 + + + B_0x1 + The RNG clock is too slow (fRNGCLK< fHCLK/32). + 0x1 + + + + + SECS + Seed error current status +One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bit patterns (“01” or “10”) +Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bit patterns (“01” or “10”) + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. + 0x0 + + + B_0x1 + At least one of the following faulty sequence has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status +This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (fRNGCLK> fHCLK/32) + 0x0 + + + B_0x1 + The RNG has been detected too slow (fRNGCLK< fHCLK/32) + 0x1 + + + + + SEIS + Seed error interrupt status +This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence has been detected. See SECS bit description for details. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data +32-bit random data which are valid when DRDY=1. When DRDY=0 RNDATA value is zero. +It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). + 0 + 32 + read-only + + + + + RNG_VERR + RNG_VERR + RNG version register + 0x3f4 + 0x20 + 0x00000021 + 0xFFFFFFFF + + + MINREV + Minor revision +This bitfield returns the RNG peripheral minor version. + 0 + 4 + read-only + + + MAJREV + Major revision +This bitfield returns the RNG peripheral major version. + 4 + 4 + read-only + + + + + RNG_IPIDR + RNG_IPIDR + RNG identification register + 0x3f8 + 0x20 + 0x00170041 + 0xFFFFFFFF + + + ID + Identification code of the peripheral +This bitfield returns the identification code of the RNG peripheral. + 0 + 32 + read-only + + + + + RNG_SIDR + RNG_SIDR + RNG size ID register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification code +This bitfield returns the size identification code of the RNG peripheral as defined below: +Bits[31:8] = 0xA3C5DD (fixed code) +Bits[7:0] = 0x01 (1 Kbyte address decoding) + 0 + 32 + read-only + + + + + + + RTC + RTC + RTC + 0x5C004000 + + 0x0 + 0x400 + registers + + + RTC_WKUP_ALARM + RTC wakeup timer and alarms (A and B) interrupt + 3 + + + RTC_WKUP_ALARM_S + RTC wakeup timer and alarms (A and B) secure interrupt + 129 + + + RTC_TS + RTC timestamp interrupt + 42 + + + RTC_TS_S + RTC timestamp secure interrupt + 130 + + + + RTC_TR + RTC_TR + The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x0 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + + + RTC_DR + RTC_DR + The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x4 + 0x20 + read-write + 0x00002101 + + + DU + DU + 0 + 4 + + + DT + DT + 4 + 2 + + + MU + MU + 8 + 4 + + + MT + MT + 12 + 1 + + + WDU + WDU + 13 + 3 + + + YU + YU + 16 + 4 + + + YT + YT + 20 + 4 + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + SS + 0 + 16 + + + + + RTC_ICSR + RTC_ICSR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0xC + 0x20 + 0x00000007 + + + ALRAWF + ALRAWF + 0 + 1 + read-only + + + ALRBWF + ALRBWF + 1 + 1 + read-only + + + WUTWF + WUTWF + 2 + 1 + read-only + + + SHPF + SHPF + 3 + 1 + read-only + + + INITS + INITS + 4 + 1 + read-only + + + RSF + RSF + 5 + 1 + read-write + + + INITF + INITF + 6 + 1 + read-only + + + INIT + INIT + 7 + 1 + read-write + + + RECALPF + RECALPF + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + PREDIV_S + 0 + 15 + + + PREDIV_A + PREDIV_A + 16 + 7 + + + + + RTC_WUTR + RTC_WUTR + This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + WUT + 0 + 16 + + + + + RTC_CR + RTC_CR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x18 + 0x20 + 0x00000000 + + + WUCKSEL + WUCKSEL + 0 + 3 + read-write + + + TSEDGE + TSEDGE + 3 + 1 + read-write + + + REFCKON + REFCKON + 4 + 1 + read-write + + + BYPSHAD + BYPSHAD + 5 + 1 + read-write + + + FMT + FMT + 6 + 1 + read-write + + + ALRAE + ALRAE + 8 + 1 + read-write + + + ALRBE + ALRBE + 9 + 1 + read-write + + + WUTE + WUTE + 10 + 1 + read-write + + + TSE + TSE + 11 + 1 + read-write + + + ALRAIE + ALRAIE + 12 + 1 + read-write + + + ALRBIE + ALRBIE + 13 + 1 + read-write + + + WUTIE + WUTIE + 14 + 1 + read-write + + + TSIE + TSIE + 15 + 1 + read-write + + + ADD1H + ADD1H + 16 + 1 + write-only + + + SUB1H + SUB1H + 17 + 1 + write-only + + + BKP + BKP + 18 + 1 + read-write + + + COSEL + COSEL + 19 + 1 + read-write + + + POL + POL + 20 + 1 + read-write + + + OSEL + OSEL + 21 + 2 + read-write + + + COE + COE + 23 + 1 + read-write + + + ITSE + ITSE + 24 + 1 + read-write + + + TAMPTS + TAMPTS + 25 + 1 + read-write + + + TAMPOE + TAMPOE + 26 + 1 + read-write + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + read-write + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + read-write + + + OUT2EN + OUT2EN + 31 + 1 + read-write + + + + + RTC_SMCR + RTC_SMCR + This register can be written only when the APB access is secure. + 0x20 + 0x20 + read-write + 0x0000E00F + + + ALRADPROT + ALRADPROT + 0 + 1 + + + ALRBDPROT + ALRBDPROT + 1 + 1 + + + WUTDPROT + WUTDPROT + 2 + 1 + + + TSDPROT + TSDPROT + 3 + 1 + + + CALDPROT + CALDPROT + 13 + 1 + + + INITDPROT + INITDPROT + 14 + 1 + + + DECPROT + DECPROT + 15 + 1 + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + KEY + 0 + 8 + + + + + RTC_CALR + RTC_CALR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x28 + 0x20 + read-write + 0x00000000 + + + CALM + CALM + 0 + 9 + + + CALW16 + CALW16 + 13 + 1 + + + CALW8 + CALW8 + 14 + 1 + + + CALP + CALP + 15 + 1 + + + + + RTC_SHIFTR + RTC_SHIFTR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x2C + 0x20 + write-only + 0x00000000 + + + SUBFS + SUBFS + 0 + 15 + + + ADD1S + ADD1S + 31 + 1 + + + + + RTC_TSTR + RTC_TSTR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + + + RTC_TSDR + RTC_TSDR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x34 + 0x20 + read-only + 0x00000000 + + + DU + DU + 0 + 4 + + + DT + DT + 4 + 2 + + + MU + MU + 8 + 4 + + + MT + MT + 12 + 1 + + + WDU + WDU + 13 + 3 + + + + + RTC_TSSSR + RTC_TSSSR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + SS + 0 + 16 + + + + + RTC_ALRMAR + RTC_ALRMAR + This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x40 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MSK1 + MSK1 + 7 + 1 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + MSK2 + MSK2 + 15 + 1 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + MSK3 + MSK3 + 23 + 1 + + + DU + DU + 24 + 4 + + + DT + DT + 28 + 2 + + + WDSEL + WDSEL + 30 + 1 + + + MSK4 + MSK4 + 31 + 1 + + + + + RTC_ALRMASSR + RTC_ALRMASSR + This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + SS + 0 + 15 + + + MASKSS + MASKSS + 24 + 4 + + + + + RTC_ALRMBR + RTC_ALRMBR + This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x48 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MSK1 + MSK1 + 7 + 1 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + MSK2 + MSK2 + 15 + 1 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + MSK3 + MSK3 + 23 + 1 + + + DU + DU + 24 + 4 + + + DT + DT + 28 + 2 + + + WDSEL + WDSEL + 30 + 1 + + + MSK4 + MSK4 + 31 + 1 + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x4C + 0x20 + read-write + 0x00000000 + + + SS + SS + 0 + 15 + + + MASKSS + MASKSS + 24 + 4 + + + + + RTC_SR + RTC_SR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + RTC_MISR + RTC_MISR + RTC non-secure masked interrupt status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + RTC_SMISR + RTC_SMISR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x58 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + RTC_SCR + RTC_SCR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + RTC_CFGR + RTC_CFGR + RTC configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + OUT2_RMP + OUT2_RMP + 0 + 1 + + + LSCOEN + LSCOEN + 1 + 2 + + + + + RTC_HWCFGR + RTC_HWCFGR + RTC hardware configuration register + 0x3F0 + 0x20 + read-only + 0x01031111 + + + ALARMB + ALARMB + 0 + 4 + + + WAKEUP + WAKEUP + 4 + 4 + + + SMOOTH_CALIB + SMOOTH_CALIB + 8 + 4 + + + TIMESTAMP + TIMESTAMP + 12 + 4 + + + OPTIONREG_OUT + OPTIONREG_OUT + 16 + 8 + + + TRUST_ZONE + TRUST_ZONE + 24 + 4 + + + + + RTC_VERR + RTC_VERR + RTC version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + RTC_IPIDR + RTC_IPIDR + RTC identification register + 0x3F8 + 0x20 + read-only + 0x00120033 + + + ID + ID + 0 + 32 + + + + + RTC_SIDR + RTC_SIDR + RTC size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + SAES + SAES register block + SAES + 0x54005000 + + 0x0 + 0x400 + registers + + + SAES + Secure AES global interrupt + 82 + + + + SAES_CR + SAES_CR + SAES control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + SAES enable +This bit enables/disables the SAES peripheral: +At any moment, clearing then setting the bit re-initializes the SAES peripheral. +This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. +The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. +Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DATATYPE + Data type selection +This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: +For more details, refer to . +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 1 + 2 + read-write + + + B_0x0 + None + 0x0 + + + B_0x1 + Half-word (16-bit) + 0x1 + + + B_0x2 + Byte (8-bit) + 0x2 + + + B_0x3 + Bit + 0x3 + + + + + MODE + SAES operating mode +This bitfield selects the SAES operating mode: +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 3 + 2 + read-write + + + B_0x0 + Mode 1: encryption + 0x0 + + + B_0x1 + Mode 2: key derivation (or key preparation for ECB/CBC decryption) + 0x1 + + + B_0x2 + Mode 3: decryption + 0x2 + + + + + CHMOD1 + Chaining mode selection +This bitfield selects the AES chaining mode: +others: Reserved +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 5 + 2 + read-write + + + DMAINEN + DMA input enable +This bit enables/disables data transferring with DMA, in the input phase: +When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMAOUTEN + DMA output enable +This bit enables/disables data transferring with DMA, in the output phase: +When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GCMPH + GCM or CCM phase selection +This bitfield selects the phase of GCM, GMAC or CCM algorithm: +The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield). + 13 + 2 + read-write + + + B_0x0 + Init phase + 0x0 + + + B_0x1 + Header phase + 0x1 + + + B_0x2 + Payload phase + 0x2 + + + B_0x3 + Final phase + 0x3 + + + + + CHMOD2 + Chaining mode selection +This bitfield selects the AES chaining mode: +others: Reserved +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 16 + 1 + read-write + + + KEYSIZE + Key size selection +This bitfield defines the length of the key used in the SAES cryptographic core, in bits: +When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. +Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 18 + 1 + read-write + + + B_0x0 + 128 + 0x0 + + + B_0x1 + 256 + 0x1 + + + + + KEYPROT + Key protection +When set hardware-based key protection is enabled. +Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 19 + 1 + read-write + + + B_0x0 + When KEYVALID is set and KEYSEL=0 application can transfer the ownership of the SAES, with its loaded key, to an application running in another security context (such as non-secure, secure, specific CPU). + 0x0 + + + B_0x1 + When KEYVALID is set, key error flag (KEIF) is set when an access to any registers is detected, this access having a security context (for example, secure, non-secure, Compartment ID) that does not match the one of the application that loaded the key. + 0x1 + + + + + NPBLB + Number of padding bytes in last block +The bitfield sets the number of padding bytes in last block of payload: +... + 20 + 4 + read-write + + + B_0x0 + All bytes are valid (no padding) + 0x0 + + + B_0x1 + Padding for one least-significant byte of last block + 0x1 + + + B_0xF + Padding for 15 least-significant bytes of last block + 0xF + + + + + KMOD + Key mode selection +The bitfield defines how the SAES key can be used by the application: +Others: Reserved +With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. +With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. +With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. +With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (such as secure, non-secure, another CPU) results in automatic key erasure and setting of the KEIF flag. +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 24 + 2 + read-write + + + B_0x0 + Normal key + 0x0 + + + B_0x1 + Wrapped key + 0x1 + + + B_0x2 + Shared key + 0x2 + + + + + KSHAREID + Key share identification +This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. +Others: Reserved +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 26 + 2 + read-write + + + B_0x0 + CRYP1 peripheral + 0x0 + + + B_0x1 + CRYP2 peripheral + 0x1 + + + + + KEYSEL + Key selection +The bitfield defines the source of the key information to use in the AES cryptographic core. +Others: Reserved (if used, unfreeze SAES with IPRST) +When KEYSEL is different from zero selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in SAES_SR register. Key error flag KEIF is set otherwise. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. +When application changes the key selection by writing to KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. +At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. +With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure, specific CPU). More specifically, when security or Compartment ID of an access to any register does not match the information recorded by SAES, the KEIF flag is set. +Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + 28 + 3 + read-write + + + B_0x0 + Software key, loaded in key registers SAES_KEYx + 0x0 + + + B_0x1 + Derived hardware unique key (DHUK) + 0x1 + + + B_0x2 + Boot hardware key (BHK) + 0x2 + + + B_0x4 + XOR of DHUK and BHK + 0x4 + + + B_0x7 + Test mode key (256-bit hardware constant 0xA5A5...A5A5) + 0x7 + + + + + IPRST + SAES peripheral software reset +Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. +The bit must be low while writing any configuration registers. + 31 + 1 + read-write + + + + + SAES_SR + SAES_SR + SAES status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation completed flag +This bit mirrors the CCF bit of the SAES_ISR register. + 0 + 1 + read-only + + + RDERR + Read error flag +This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): +The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. +Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. +The flag setting has no impact on the SAES operation. Unexpected read returns zero. + 1 + 1 + read-only + + + B_0x0 + Not detected + 0x0 + + + B_0x1 + Detected + 0x1 + + + + + WRERR + Write error +This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): +The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. +Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. +The flag setting has no impact on the SAES operation. Unexpected write is ignored. + 2 + 1 + read-only + + + B_0x0 + Not detected + 0x0 + + + B_0x1 + Detected + 0x1 + + + + + BUSY + Busy +This flag indicates whether SAES is idle or busy during GCM payload encryption phase: +The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. +When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase. + 3 + 1 + read-only + + + B_0x0 + Idle + 0x0 + + + B_0x1 + Busy + 0x1 + + + + + KEYVALID + Key Valid flag +This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. +In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. +When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. +When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. +For more information on key loading please refer to . + 7 + 1 + read-only + + + B_0x0 + No valid key information is available in key registers. EN bit in SAES_CR cannot be set. + 0x0 + + + B_0x1 + Valid key information, defined by KEYSIZE in SAES_CR, is loaded in key registers. + 0x1 + + + + + + + SAES_DINR + SAES_DINR + SAES data input register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIN + Input data word +A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. +The data signification of the input data block depends on the SAES operating mode: +- Mode 1 (encryption): plaintext +- Mode 2 (key derivation): the bitfield is not used (SAES_KEYRx registers used for input if KEYSEL=0) +- Mode 3 (decryption): ciphertext +The data swap operation is described in on page 1718. + 0 + 32 + write-only + + + + + SAES_DOUTR + SAES_DOUTR + SAES data output register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DOUT + Output data word +This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. +Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. +The data signification of the output data block depends on the SAES operating mode: +- Mode 1 (encryption): ciphertext +- Mode 2 (key derivation): the bitfield is not used +- Mode 3 (decryption): plaintext +The data swap operation is described in on page 1718. + 0 + 32 + read-only + + + + + SAES_KEYR0 + SAES_KEYR0 + SAES key register 0 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [31:0] +This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: +- In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key. +- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. +The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL is different from 0 and KEYVALID = 0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). +Refer to for more details. + 0 + 32 + write-only + + + + + SAES_KEYR1 + SAES_KEYR1 + SAES key register 1 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [63:32] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_KEYR2 + SAES_KEYR2 + SAES key register 2 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [95:64] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_KEYR3 + SAES_KEYR3 + SAES key register 3 + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [127:96] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_IVR0 + SAES_IVR0 + SAES initialization vector register 0 + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [31:0] +Refer to for description of the IVI[127:0] bitfield. +The initialization vector is only used in chaining modes other than ECB. +The SAES_IVRx registers may be written only when the SAES peripheral is disabled + 0 + 32 + read-write + + + + + SAES_IVR1 + SAES_IVR1 + SAES initialization vector register 1 + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [63:32] +Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + SAES_IVR2 + SAES_IVR2 + SAES initialization vector register 2 + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [95:64] +Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + SAES_IVR3 + SAES_IVR3 + SAES initialization vector register 3 + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [127:96] +Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + SAES_KEYR4 + SAES_KEYR4 + SAES key register 4 + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [159:128] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_KEYR5 + SAES_KEYR5 + SAES key register 5 + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [191:160] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_KEYR6 + SAES_KEYR6 + SAES key register 6 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [223:192] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_KEYR7 + SAES_KEYR7 + SAES key register 7 + 0x3c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [255:224] +Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + 0 + 32 + write-only + + + + + SAES_SUSP0R + SAES_SUSP0R + SAES suspend registers + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP1R + SAES_SUSP1R + SAES suspend registers + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP2R + SAES_SUSP2R + SAES suspend registers + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP3R + SAES_SUSP3R + SAES suspend registers + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP4R + SAES_SUSP4R + SAES suspend registers + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP5R + SAES_SUSP5R + SAES suspend registers + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP6R + SAES_SUSP6R + SAES suspend registers + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_SUSP7R + SAES_SUSP7R + SAES suspend registers + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + SAES suspend +Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + 0 + 32 + read-write + + + + + SAES_IER + SAES_IER + SAES interrupt enable register + 0x300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCFIE + Computation complete flag interrupt enable +This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. + 0 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RWEIE + Read or write error interrupt enable +This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. + 1 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + KEIE + Key error interrupt enable +This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. + 2 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RNGEIE + RNG error interrupt enable +This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. + 3 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + + + SAES_ISR + SAES_ISR + SAES interrupt status register + 0x304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag +This flag indicates whether the computation is completed: +The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. +Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. +The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1. + 0 + 1 + read-only + + + B_0x0 + Not completed + 0x0 + + + B_0x1 + Completed + 0x1 + + + + + RWEIF + Read or write error interrupt flag +This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. +RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. +This flags has no meaning when key derivation mode is selected. + 1 + 1 + read-only + + + B_0x0 + No read or write error detected + 0x0 + + + B_0x1 + Read or write error detected (see SAES_SR register for details) + 0x1 + + + + + KEIF + Key error interrupt flag +This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. +KEIF bit is cleared when application sets the corresponding bit in SAES_ICR register. An interrupt is generated if the KEIE bit has been previously set in the SAES_IER register. +KEIF is triggered if one of below error occurred: +Application did not write SAES_KEYRx registers in the correct sequence. Specifically, If KEYSIZE=0 SAES_KEYR0, then SAES_KEYR1, then SAES_KEYR2 then SAES_KEYR3 register must be written (or the reverse order). If KEYSIZE=1 SAES_KEYR0, then SAES_KEYR1, then SAES_KEYR2 then SAES_KEYR3, then SAES_KEYR4, then SAES_KEYR5, then SAES_KEYR6, then SAES_KEYR7 register must be written (or the reverse order). +SAES failed to load the DHUK (KEYSEL=001 or 100) +SAES failed to load the BHK (KEYSEL=010 or 100) using the same sequence as above. +AES failed to load the key shared by SAES peripheral (KMOD=10) +When KEYVALID=1 and (KEYPROT=1 or KEYSEL not 0x0), security context of the application that loaded the key (secure, non-secure, CPU) does not match the security or Compartment ID attribute of the access to SAES_CR or SAES_DOUT. In this case KEYVALID and EN bits are cleared. +KEIF must be cleared by application otherwise KEYVALID cannot be set. + 2 + 1 + read-only + + + B_0x0 + No key error detected + 0x0 + + + B_0x1 + Key information failed to load into key registers, or key register usage is forbidden + 0x1 + + + + + RNGEIF + RNG error interrupt flag +This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). +RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. + 3 + 1 + read-only + + + B_0x0 + RNG bus is functional + 0x0 + + + B_0x1 + Error detected on RNG bus interface (random seed fetching error) + 0x1 + + + + + + + SAES_ICR + SAES_ICR + SAES interrupt clear register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag clear +Application must set this bit to clear the CCF status bit in SAES_SR and SAES_ISR register. + 0 + 1 + write-only + + + RWEIF + Read or write error interrupt flag clear +Application must set this bit to clear the RWEIF status bit in SAES_ISR register, and both RDERR and WRERR flags in SAES_SR register. + 1 + 1 + write-only + + + KEIF + Key error interrupt flag clear +Application must set this bit to clear the KEIF status bit in SAES_ISR register. + 2 + 1 + write-only + + + RNGEIF + RNG error interrupt flag clear +Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. + 3 + 1 + write-only + + + + + SAES_HWCFGR + SAES_HWCFGR + SAES hardware configuration register + 0x3F0 + 0x20 + 0x00000112 + 0xFFFFFFFF + + + CFG1 + HW Generic 1 + 0 + 4 + read-only + + + CFG2 + HW Generic 2 + 4 + 4 + read-only + + + CFG3 + HW Generic 3 + 8 + 4 + read-only + + + + + SAES_VERR + SAES_VERR + SAES version register + 0x3f4 + 0x20 + 0x00000030 + 0xFFFFFFFF + + + MINREV + Minor revision +This bitfield returns the SAES peripheral minor version (0x0). + 0 + 4 + read-only + + + MAJREV + Major revision +This bitfield returns the SAES peripheral major version (0x3). + 4 + 4 + read-only + + + + + SAES_IPIDR + SAES_IPIDR + SAES identification register + 0x3f8 + 0x20 + 0x00170023 + 0xFFFFFFFF + + + ID + Identification code of the peripheral +This bitfield returns the identification code of the SAES peripheral. + 0 + 32 + read-only + + + + + SAES_SIDR + SAES_SIDR + SAES size ID register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification code +This bitfield returns the size identification code of the SAES peripheral as defined below: +Bits[31:8] = 0xA3C5DD (fixed code) +Bits[7:0] = 0x01 (1 Kbyte address decoding) + 0 + 32 + read-only + + + + + + + SAI1 + SAI1 register block + SAI + 0x4400A000 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 87 + + + + SAI_GCR + SAI_GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + SYNCIN + 0 + 2 + + + SYNCOUT + SYNCOUT + 4 + 2 + + + + + SAI_ACR1 + SAI_ACR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + MODE + 0 + 2 + + + PRTCFG + PRTCFG + 2 + 2 + + + DS + DS + 5 + 3 + + + LSBFIRST + LSBFIRST + 8 + 1 + + + CKSTR + CKSTR + 9 + 1 + + + SYNCEN + SYNCEN + 10 + 2 + + + MONO + MONO + 12 + 1 + + + OUTDRIV + OUTDRIV + 13 + 1 + + + SAIEN + SAIEN + 16 + 1 + + + DMAEN + DMAEN + 17 + 1 + + + NODIV + NODIV + 19 + 1 + + + MCKDIV + MCKDIV + 20 + 6 + + + OSR + OSR + 26 + 1 + + + MCKEN + MCKEN + 27 + 1 + + + + + SAI_ACR2 + SAI_ACR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FTH + 0 + 3 + read-write + + + FFLUSH + FFLUSH + 3 + 1 + write-only + + + TRIS + TRIS + 4 + 1 + read-write + + + MUTE + MUTE + 5 + 1 + read-write + + + MUTEVAL + MUTEVAL + 6 + 1 + read-write + + + MUTECNT + MUTECNT + 7 + 6 + read-write + + + CPL + CPL + 13 + 1 + read-write + + + COMP + COMP + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in and SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + FRL + 0 + 8 + read-write + + + FSALL + FSALL + 8 + 7 + read-write + + + FSDEF + FSDEF + 16 + 1 + read-only + + + FSPOL + FSPOL + 17 + 1 + read-write + + + FSOFF + FSOFF + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in and SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + FBOFF + 0 + 5 + + + SLOTSZ + SLOTSZ + 6 + 2 + + + NBSLOT + NBSLOT + 8 + 4 + + + SLOTEN + SLOTEN + 16 + 16 + + + + + SAI_AIM + SAI_AIM + Interrupt mask register + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + OVRUDRIE + 0 + 1 + + + MUTEDETIE + MUTEDETIE + 1 + 1 + + + WCKCFGIE + WCKCFGIE + 2 + 1 + + + FREQIE + FREQIE + 3 + 1 + + + CNRDYIE + CNRDYIE + 4 + 1 + + + AFSDETIE + AFSDETIE + 5 + 1 + + + LFSDETIE + LFSDETIE + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + OVRUDR + 0 + 1 + + + MUTEDET + MUTEDET + 1 + 1 + + + WCKCFG + WCKCFG + 2 + 1 + + + FREQ + FREQ + 3 + 1 + + + CNRDY + CNRDY + 4 + 1 + + + AFSDET + AFSDET + 5 + 1 + + + LFSDET + LFSDET + 6 + 1 + + + FLVL + FLVL + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + COVRUDR + COVRUDR + 0 + 1 + + + CMUTEDET + CMUTEDET + 1 + 1 + + + CWCKCFG + CWCKCFG + 2 + 1 + + + CCNRDY + CCNRDY + 4 + 1 + + + CAFSDET + CAFSDET + 5 + 1 + + + CLFSDET + CLFSDET + 6 + 1 + + + + + SAI_ADR + SAI_ADR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + SAI_BCR1 + SAI_BCR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + MODE + 0 + 2 + + + PRTCFG + PRTCFG + 2 + 2 + + + DS + DS + 5 + 3 + + + LSBFIRST + LSBFIRST + 8 + 1 + + + CKSTR + CKSTR + 9 + 1 + + + SYNCEN + SYNCEN + 10 + 2 + + + MONO + MONO + 12 + 1 + + + OUTDRIV + OUTDRIV + 13 + 1 + + + SAIEN + SAIEN + 16 + 1 + + + DMAEN + DMAEN + 17 + 1 + + + NODIV + NODIV + 19 + 1 + + + MCKDIV + MCKDIV + 20 + 6 + + + OSR + OSR + 26 + 1 + + + MCKEN + MCKEN + 27 + 1 + + + + + SAI_BCR2 + SAI_BCR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FTH + 0 + 3 + read-write + + + FFLUSH + FFLUSH + 3 + 1 + write-only + + + TRIS + TRIS + 4 + 1 + read-write + + + MUTE + MUTE + 5 + 1 + read-write + + + MUTEVAL + MUTEVAL + 6 + 1 + read-write + + + MUTECNT + MUTECNT + 7 + 6 + read-write + + + CPL + CPL + 13 + 1 + read-write + + + COMP + COMP + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in and SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + FRL + 0 + 8 + read-write + + + FSALL + FSALL + 8 + 7 + read-write + + + FSDEF + FSDEF + 16 + 1 + read-only + + + FSPOL + FSPOL + 17 + 1 + read-write + + + FSOFF + FSOFF + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in and SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + FBOFF + 0 + 5 + + + SLOTSZ + SLOTSZ + 6 + 2 + + + NBSLOT + NBSLOT + 8 + 4 + + + SLOTEN + SLOTEN + 16 + 16 + + + + + SAI_BIM + SAI_BIM + Interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + OVRUDRIE + 0 + 1 + + + MUTEDETIE + MUTEDETIE + 1 + 1 + + + WCKCFGIE + WCKCFGIE + 2 + 1 + + + FREQIE + FREQIE + 3 + 1 + + + CNRDYIE + CNRDYIE + 4 + 1 + + + AFSDETIE + AFSDETIE + 5 + 1 + + + LFSDETIE + LFSDETIE + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + OVRUDR + 0 + 1 + + + MUTEDET + MUTEDET + 1 + 1 + + + WCKCFG + WCKCFG + 2 + 1 + + + FREQ + FREQ + 3 + 1 + + + CNRDY + CNRDY + 4 + 1 + + + AFSDET + AFSDET + 5 + 1 + + + LFSDET + LFSDET + 6 + 1 + + + FLVL + FLVL + 16 + 3 + + + + + SAI_BCLRFR + SAI_BCLRFR + Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + COVRUDR + COVRUDR + 0 + 1 + + + CMUTEDET + CMUTEDET + 1 + 1 + + + CWCKCFG + CWCKCFG + 2 + 1 + + + CCNRDY + CCNRDY + 4 + 1 + + + CAFSDET + CAFSDET + 5 + 1 + + + CLFSDET + CLFSDET + 6 + 1 + + + + + SAI_BDR + SAI_BDR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + SAI_PDMCR + SAI_PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + SAI_PDMDLY + SAI_PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + SAI_HWCFGR + SAI_HWCFGR + SAI hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000108 + + + FIFO_SIZE + FIFO_SIZE + 0 + 8 + + + SPDIF_PDM + SPDIF_PDM + 8 + 4 + + + OPTION_REGOUT + OPTION_REGOUT + 12 + 8 + + + + + SAI_VERR + SAI_VERR + SAI version register + 0x3F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SAI_IPIDR + SAI_IPIDR + SAI identification register + 0x3F8 + 0x20 + read-only + 0x00130031 + + + ID + ID + 0 + 32 + + + + + SAI_SIDR + SAI_SIDR + SAI size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + SAI2 + 0x4400B000 + + SAI2 + SAI2 global interrupt + 90 + + + + SPDIFRX + SPDIFRX + SPDIFRX + 0x4000D000 + + 0x0 + 0x400 + registers + + + SPDIFRX + SPDIFRX global interrupt + 95 + + + + SPDIFRX_CR + SPDIFRX_CR + Control register + 0x00 + 0x20 + read-write + 0x00000000 + + + SPDIFRXEN + SPDIFRXEN + 0 + 2 + read-write + + + RXDMAEN + RXDMAEN + 2 + 1 + read-write + + + RXSTEO + RXSTEO + 3 + 1 + read-write + + + DRFMT + DRFMT + 4 + 2 + read-write + + + PMSK + PMSK + 6 + 1 + read-write + + + VMSK + VMSK + 7 + 1 + read-write + + + CUMSK + CUMSK + 8 + 1 + read-write + + + PTMSK + PTMSK + 9 + 1 + read-write + + + CBDMAEN + CBDMAEN + 10 + 1 + read-write + + + CHSEL + CHSEL + 11 + 1 + read-write + + + NBTR + NBTR + 12 + 2 + read-write + + + WFA + WFA + 14 + 1 + read-write + + + INSEL + INSEL + 16 + 3 + read-write + + + CKSEN + CKSEN + 20 + 1 + read-write + + + CKSBKPEN + CKSBKPEN + 21 + 1 + read-write + + + + + SPDIFRX_IMR + SPDIFRX_IMR + Interrupt mask register + 0x04 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNEIE + 0 + 1 + read-write + + + CSRNEIE + CSRNEIE + 1 + 1 + read-write + + + PERRIE + PERRIE + 2 + 1 + read-write + + + OVRIE + OVRIE + 3 + 1 + read-write + + + SBLKIE + SBLKIE + 4 + 1 + read-write + + + SYNCDIE + SYNCDIE + 5 + 1 + read-write + + + IFEIE + IFEIE + 6 + 1 + read-write + + + + + SPDIFRX_SR + SPDIFRX_SR + Status register + 0x08 + 0x20 + read-only + 0x00000000 + + + RXNE + RXNE + 0 + 1 + read-only + + + CSRNE + CSRNE + 1 + 1 + read-only + + + PERR + PERR + 2 + 1 + read-only + + + OVR + OVR + 3 + 1 + read-only + + + SBD + SBD + 4 + 1 + read-only + + + SYNCD + SYNCD + 5 + 1 + read-only + + + FERR + FERR + 6 + 1 + read-only + + + SERR + SERR + 7 + 1 + read-only + + + TERR + TERR + 8 + 1 + read-only + + + WIDTH5 + WIDTH5 + 16 + 15 + read-only + + + + + SPDIFRX_IFCR + SPDIFRX_IFCR + Interrupt flag clear register + 0x0C + 0x20 + read-write + 0x00000000 + + + PERRCF + PERRCF + 2 + 1 + write-only + + + OVRCF + OVRCF + 3 + 1 + write-only + + + SBDCF + SBDCF + 4 + 1 + write-only + + + SYNCDCF + SYNCDCF + 5 + 1 + write-only + + + + + SPDIFRX_FMT0_DR + SPDIFRX_FMT0_DR + This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00: + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + DR + 0 + 24 + read-only + + + PE + PE + 24 + 1 + read-only + + + V + V + 25 + 1 + read-only + + + U + U + 26 + 1 + read-only + + + C + C + 27 + 1 + read-only + + + PT + PT + 28 + 2 + read-only + + + + + SPDIFRX_CSR + SPDIFRX_CSR + Channel status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + USR + 0 + 16 + read-only + + + CS + CS + 16 + 8 + read-only + + + SOB + SOB + 24 + 1 + read-only + + + + + SPDIFRX_DIR + SPDIFRX_DIR + Debug information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + THI + 0 + 13 + read-only + + + TLO + TLO + 16 + 13 + read-only + + + + + SPDIFRX_VERR + SPDIFRX_VERR + SPDIFRX version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + MINREV + 0 + 4 + read-only + + + MAJREV + MAJREV + 4 + 4 + read-only + + + + + SPDIFRX_IPIDR + SPDIFRX_IPIDR + SPDIFRX identification register + 0x3F8 + 0x20 + read-only + 0x00130041 + + + ID + ID + 0 + 32 + read-only + + + + + SPDIFRX_SIDR + SPDIFRX_SIDR + SPDIFRX size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + read-only + + + + + + + SPI1 + SPI1 + SPI1 + 0x44004000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 36 + + + + SPI_CR1 + SPI_CR1 + SPI/I2S control register 1 + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPE + serial peripheral enable +This bit is set by and cleared by software. +When SPE=1, the SPI data transfer is enabled, the configuration registers SPI_CFG1, SPI_CFG2, CRCPOLY and UDRDR and the IOLOCK bit in SPI_CR1 are write protected. They can be changed only when SPE=0. +When SPE=0 any SPI operation is stopped and disabled, all the not cleared requests with enabled interrupt stay pending and propagates the spi_plck clock request, the SS output is deactivated at master, internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. +SPE is cleared and cannot be set when MODF error flag is active. + 0 + 1 + read-write + + + B_0x0 + serial peripheral disabled. + 0x0 + + + B_0x1 + serial peripheral enabled + 0x1 + + + + + MASRX + master automatic SUSP in Receive mode +This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. +When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. +That is why the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles must always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. + 8 + 1 + read-write + + + B_0x0 + SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost) + 0x0 + + + B_0x1 + SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when SPI communication is suspended. + 0x1 + + + + + CSTART + master transfer start +This bit is set by software to start an SPI or I2S/PCM communication. In SPI mode, it is cleared by hardware when End Of Transfer (EOT) flag is set or when a transaction suspend request is accepted. In I2S/PCM mode, it is also cleared by hardware as described in the section stop sequence. +In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. + 9 + 1 + read-write + + + B_0x0 + master transfer is at idle + 0x0 + + + B_0x1 + master transfer is on-going or temporary suspended by automatic suspend + 0x1 + + + + + CSUSP + master suspend request +This bit reads as zero. +In master mode, when this bit is set by software, CSTART bit is reset at the end of the current frame and SPI communication is suspended. The user has to check SUSP flag to check end of the frame transaction. +The master mode communication must be suspended (using this bit or keeping TXDR empty) before disabling the SPI or going to low-power mode. +After software suspension, the SUSP flag has to be cleared and the SPI disabled and re-enabled before any next transaction starts. + 10 + 1 + write-only + + + HDDIR + Rx/Tx direction at Half-duplex mode +In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. + 11 + 1 + read-write + + + B_0x0 + SPI is Receiver + 0x0 + + + B_0x1 + SPI is transmitter + 0x1 + + + + + SSI + internal SS signal input level +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input and the I/O value of the SS pin is ignored. + 12 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial configuration + 13 + 1 + read-write + + + B_0x0 + full size (33-bit or 17-bit) CRC polynomial is not used + 0x0 + + + B_0x1 + full size (33-bit or 17-bit) CRC polynomial is used + 0x1 + + + + + RCRCINI + CRC calculation initialization pattern control for receiver + 14 + 1 + read-write + + + B_0x0 + all zero pattern is applied + 0x0 + + + B_0x1 + all ones pattern is applied + 0x1 + + + + + TCRCINI + CRC calculation initialization pattern control for transmitter + 15 + 1 + read-write + + + B_0x0 + All zero pattern is applied + 0x0 + + + B_0x1 + All ones pattern is applied + 0x1 + + + + + IOLOCK + locking the AF configuration of associated IOs +This bit is set by software and cleared by hardware whenever SPE bit is changed from 1 to 0. +When this bit is set, the SPI_CFG2 register content cannot be modified. This bit can be set when SPI is disabled only else it is write protected. It is cleared and cannot be set when the MODF bit is set. + 16 + 1 + read-write + + + B_0x0 + AF configuration is not locked + 0x0 + + + B_0x1 + AF configuration is locked + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSIZE + number of data at current transfer +When these bits are changed by software, the SPI must be disabled. The field can be updated by hardware optionally, too, to be reloaded by the TSER value if applicable. +Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF value when CRC is enabled. + 0 + 16 + read-write + + + TSER + number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted +This register can be set by software when its content is cleared only. It is cleared by hardware once TSIZE reload is done. The TSER value must be programmed in advance before CTSIZE counter reaches zero otherwise the reload is not taken into account and traffic terminates with normal EOT event. + 16 + 16 + read-write + + + + + SPI_CFG1 + SPI_CFG1 + SPI configuration register 1 + 0x8 + 0x20 + 0x00070007 + 0xFFFFFFFF + + + DSIZE + number of bits in at single SPI data frame +..... +Note: The most significant bit at DSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. + 0 + 5 + read-write + + + B_0x0 + not used + 0x0 + + + B_0x1 + not used + 0x1 + + + B_0x2 + not used + 0x2 + + + B_0x3 + 4-bits + 0x3 + + + B_0x4 + 5-bits + 0x4 + + + B_0x5 + 6-bits + 0x5 + + + B_0x6 + 7-bits + 0x6 + + + B_0x7 + 8-bits + 0x7 + + + B_0x1D + 30-bits + 0x1D + + + B_0x1E + 31-bits + 0x1E + + + B_0x1F + 32-bits + 0x1F + + + + + FTHLV + FIFO threshold level +Defines number of data frames at single data packet. The size of the packet must not exceed 1/2 of FIFO space. +SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: +If SPI data register is accessed as a 16-bit register and DSIZE<=8bit, better to select FTHLV=2, 4, 6 etc, +If SPI data register is accessed as a 32-bit register and DSIZE>8bit, better to select FTHLV=2, 4, 6 etc, while if DSIZE<=8bit, better to select FTHLV=4, 8, 12 etc + 5 + 4 + read-write + + + B_0x0 + 1-data + 0x0 + + + B_0x1 + 2-data + 0x1 + + + B_0x2 + 3-data + 0x2 + + + B_0x3 + 4-data + 0x3 + + + B_0x4 + 5-data + 0x4 + + + B_0x5 + 6-data + 0x5 + + + B_0x6 + 7-data + 0x6 + + + B_0x7 + 8-data + 0x7 + + + B_0x8 + 9-data + 0x8 + + + B_0x9 + 10-data + 0x9 + + + B_0xA + 11-data + 0xA + + + B_0xB + 12-data + 0xB + + + B_0xC + 13-data + 0xC + + + B_0xD + 14-data + 0xD + + + B_0xE + 15-data + 0xE + + + B_0xF + 16-data + 0xF + + + + + UDRCFG + behavior of slave transmitter at underrun condition +When slave is configured at transmit only mode (COMM[1:0]=01), slave repeats all zeros pattern at UDRCFG[1:0]=01 setting. +For more details see underrun condition. + 9 + 2 + read-write + + + B_0x0 + slave sends a constant pattern defined by the user at SPI_UDRDR register + 0x0 + + + B_0x1 + slave repeats lastly received data frame from master + 0x1 + + + B_0x2 + slave repeats its lastly transmitted data frame + 0x2 + + + + + UDRDET + detection of underrun condition at slave transmitter +For more details see underrun condition. + 11 + 2 + read-write + + + B_0x0 + underrun is detected at begin of data frame (no protection of 1-st bit) + 0x0 + + + B_0x1 + underrun is detected at end of last data frame + 0x1 + + + B_0x2 + underrun is detected by begin of active SS signal + 0x2 + + + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + read-write + + + B_0x0 + Rx-DMA disabled + 0x0 + + + B_0x1 + Rx-DMA enabled + 0x1 + + + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + read-write + + + B_0x0 + Tx DMA disabled + 0x0 + + + B_0x1 + Tx DMA enabled + 0x1 + + + + + CRCSIZE + length of CRC frame to be transacted and compared +Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. +..... +The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size cannot exceed the DSIZE maximum at the instance. +Note: If crc calculation is disabled by CRCEN=0, the CRCSIZE field must be kept at its default setting. +Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where the data size is limited to 16-bit. + 16 + 5 + read-write + + + B_0x3 + 4-bits + 0x3 + + + B_0x4 + 5-bits + 0x4 + + + B_0x5 + 6-bits + 0x5 + + + B_0x6 + 7-bits + 0x6 + + + B_0x7 + 8-bits + 0x7 + + + B_0x1D + 30-bits + 0x1D + + + B_0x1E + 31-bits + 0x1E + + + B_0x1F + 32-bits + 0x1F + + + + + CRCEN + hardware CRC computation enable + 22 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation Enabled + 0x1 + + + + + MBR + master baud rate +Note: MBR setting is considered at slave working at TI mode, too (see mode). + 28 + 3 + read-write + + + B_0x0 + SPI master clock/2 + 0x0 + + + B_0x1 + SPI master clock/4 + 0x1 + + + B_0x2 + SPI master clock/8 + 0x2 + + + B_0x3 + SPI master clock/16 + 0x3 + + + B_0x4 + SPI master clock/32 + 0x4 + + + B_0x5 + SPI master clock/64 + 0x5 + + + B_0x6 + SPI master clock/128 + 0x6 + + + B_0x7 + SPI master clock/256 + 0x7 + + + + + + + SPI_CFG2 + SPI_CFG2 + SPI configuration register 2 + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MSSI + master SS idleness +Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data of a session start in master mode when SSOE is enabled. +... +Note: This feature is not supported in TI mode. + 0 + 4 + read-write + + + B_0x0 + no extra delay + 0x0 + + + B_0x1 + 1 clock cycle period delay added + 0x1 + + + B_0xF + 15 clock cycle periods delay added + 0xF + + + + + MIDI + master Inter-Data Idleness +Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode. +... +Note: This feature is not supported in TI mode. + 4 + 4 + read-write + + + B_0x0 + no delay + 0x0 + + + B_0x1 + 1 clock cycle period delay + 0x1 + + + B_0xF + 15 clock cycle periods delay + 0xF + + + + + IOSWP + swap functionality of MISO and MOSI pins +When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. +Original MISO pin becomes MOSI and original MOSI pin becomes MISO. +Note: This bit can be also used in PCM and I2S modes. + 15 + 1 + read-write + + + B_0x0 + no swap + 0x0 + + + B_0x1 + MOSI and MISO are swapped + 0x1 + + + + + COMM + SPI communication mode + 17 + 2 + read-write + + + B_0x0 + full-duplex + 0x0 + + + B_0x1 + simplex transmitter + 0x1 + + + B_0x2 + simplex receiver + 0x2 + + + B_0x3 + half-duplex + 0x3 + + + + + SP + Serial protocol +others: Reserved, must not be used + 19 + 3 + read-write + + + B_0x0 + SPI Motorola + 0x0 + + + B_0x1 + SPI TI + 0x1 + + + + + MASTER + SPI master + 22 + 1 + read-write + + + B_0x0 + SPI Slave + 0x0 + + + B_0x1 + SPI Master + 0x1 + + + + + LSBFRST + data frame format +Note: This bit can be also used in PCM and I2S modes. + 23 + 1 + read-write + + + B_0x0 + MSB transmitted first + 0x0 + + + B_0x1 + LSB transmitted first + 0x1 + + + + + CPHA + clock phase + 24 + 1 + read-write + + + B_0x0 + the first clock transition is the first data capture edge + 0x0 + + + B_0x1 + the second clock transition is the first data capture edge + 0x1 + + + + + CPOL + clock polarity + 25 + 1 + read-write + + + B_0x0 + SCK signal is at 0 when idle + 0x0 + + + B_0x1 + SCK signal is at 1 when idle + 0x1 + + + + + SSM + software management of SS signal input +When master uses hardware SS output (SSM=0 and SSOE=1), the SS signal input is forced to non active state internally to prevent master mode fault error. + 26 + 1 + read-write + + + B_0x0 + SS input value is determined by the SS PAD + 0x0 + + + B_0x1 + SS input value is determined by the SSI bit + 0x1 + + + + + SSIOP + SS input/output polarity + 28 + 1 + read-write + + + B_0x0 + low level is active for SS signal + 0x0 + + + B_0x1 + high level is active for SS signal + 0x1 + + + + + SSOE + SS output enable +This bit is taken into account at master mode only + 29 + 1 + read-write + + + B_0x0 + SS output is disabled and the SPI can work in multi-master configuration + 0x0 + + + B_0x1 + SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting + 0x1 + + + + + SSOM + SS output management in master mode +This bit is taken into account in master mode when SSOE is enabled. It allows to configure SS output between two consecutive data transfers. + 30 + 1 + read-write + + + B_0x0 + SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag + 0x0 + + + B_0x1 + SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 + 0x1 + + + + + AFCNTR + alternate function GPIOs control +This bit is taken into account when SPE=0 only +When SPI master has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. This bit must be never used at slave mode as any slave transmitter must not force its MISO output once the SPI is disabled. +Note: This bit can be also used in PCM and I2S modes. + 31 + 1 + read-write + + + B_0x0 + the peripheral takes no control of GPIOs while it is disabled + 0x0 + + + B_0x1 + the peripheral keeps always control of all associated GPIOs + 0x1 + + + + + + + SPI_IER + SPI_IER + SPI/I2S interrupt enable register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXPIE + RXP Interrupt Enable + 0 + 1 + read-write + + + B_0x0 + RXP interrupt disabled + 0x0 + + + B_0x1 + RXP interrupt enabled + 0x1 + + + + + TXPIE + TXP interrupt enable +TXPIE is set by software and cleared by TXTF flag set event. + 1 + 1 + read-write + + + B_0x0 + TXP interrupt disabled + 0x0 + + + B_0x1 + TXP interrupt enabled + 0x1 + + + + + DXPIE + DXP interrupt enabled +DXPIE is set by software and cleared by TXTF flag set event. + 2 + 1 + read-write + + + B_0x0 + DXP interrupt disabled + 0x0 + + + B_0x1 + DXP interrupt enabled + 0x1 + + + + + EOTIE + EOT, SUSP and TXC interrupt enable + 3 + 1 + read-write + + + B_0x0 + EOT/SUSP/TXC interrupt disabled + 0x0 + + + B_0x1 + EOT/SUSP/TXC interrupt enabled + 0x1 + + + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + B_0x0 + TXTF interrupt disabled + 0x0 + + + B_0x1 + TXTF interrupt enabled + 0x1 + + + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + B_0x0 + UDR interrupt disabled + 0x0 + + + B_0x1 + UDR interrupt enabled + 0x1 + + + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + B_0x0 + OVR interrupt disabled + 0x0 + + + B_0x1 + OVR interrupt enabled + 0x1 + + + + + CRCEIE + CRC error interrupt enable + 7 + 1 + read-write + + + B_0x0 + CRC interrupt disabled + 0x0 + + + B_0x1 + CRC interrupt enabled + 0x1 + + + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + B_0x0 + TIFRE interrupt disabled + 0x0 + + + B_0x1 + TIFRE interrupt enabled + 0x1 + + + + + MODFIE + mode fault interrupt enable + 9 + 1 + read-write + + + B_0x0 + MODF interrupt disabled + 0x0 + + + B_0x1 + MODF interrupt enabled + 0x1 + + + + + TSERFIE + additional number of transactions reload interrupt enable + 10 + 1 + read-write + + + B_0x0 + TSERF interrupt disabled + 0x0 + + + B_0x1 + TSERF interrupt enabled + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI/I2S status register + 0x14 + 0x20 + 0x00001002 + 0xFFFFFFFF + + + RXP + Rx-packet available +RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It has to be checked once a data packet is completely read out from RxFIFO. + 0 + 1 + read-only + + + B_0x0 + RxFIFO is empty or a not complete data packet is received + 0x0 + + + B_0x1 + RxFIFO contains at least 1 data packet + 0x1 + + + + + TXP + Tx-packet space available +TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO if SPI is enabled. It has to be checked once a complete data packet is stored at TxFIFO. + 1 + 1 + read-only + + + B_0x0 + there is not enough space to locate next data packet at TxFIFO + 0x0 + + + B_0x1 + TxFIFO has enough free location to host 1 data packet + 0x1 + + + + + DXP + duplex packet +The DXP flag is set whenever both TXP and RXP flags are set regardless the SPI mode. + 2 + 1 + read-only + + + B_0x0 + TxFIFO is Full and/or RxFIFO is Empty + 0x0 + + + B_0x1 + Both TxFIFO has space for write and RxFIFO contains for read a single packet at least + 0x1 + + + + + EOT + end of transfer +EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared by software write 1 to EOTC bit at SPI_IFCR. +EOT flag triggers an interrupt if EOTIE bit is set. +If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. +In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. + 3 + 1 + read-only + + + B_0x0 + transfer is on-going or not started + 0x0 + + + B_0x1 + transfer complete + 0x1 + + + + + TXTF + transmission transfer filled +TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. +This bit is cleared by software write 1 to TXTFC bit at SPI_IFCR +TXTF flag triggers an interrupt if TXTFIE bit is set. +TXTF setting clears the TXIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. + 4 + 1 + read-only + + + B_0x0 + upload of TxFIFO is on-going or not started + 0x0 + + + B_0x1 + TxFIFO upload is finished + 0x1 + + + + + UDR + underrun at slave transmission mode +This bit is cleared by write 1 to UDRC bit at SPI_IFCR +Note: UDR flag applies to Slave mode only + 5 + 1 + read-only + + + B_0x0 + no underrun + 0x0 + + + B_0x1 + underrun detected + 0x1 + + + + + OVR + overrun +This bit is cleared by write 1 to OVRC bit at SPI_IFCR + 6 + 1 + read-only + + + B_0x0 + no overrun + 0x0 + + + B_0x1 + overrun detected + 0x1 + + + + + CRCE + CRC error +This bit is cleared by write 1 to CRCEC bit at SPI_IFCR + 7 + 1 + read-only + + + B_0x0 + no CRC error + 0x0 + + + B_0x1 + CRC error detected + 0x1 + + + + + TIFRE + TI frame format error +This bit is cleared by write 1 to TIFREC bit at SPI_IFCR + 8 + 1 + read-only + + + B_0x0 + no TI Frame Error + 0x0 + + + B_0x1 + TI Frame Error detected + 0x1 + + + + + MODF + mode fault +This bit is cleared by write 1 to MODFC bit at SPI_IFCR. When MODF is set, the SPE and IOLOCK bits at the SPI_CR1 register are reset and their setting is blocked. + 9 + 1 + read-only + + + B_0x0 + no mode fault + 0x0 + + + B_0x1 + mode fault detected + 0x1 + + + + + TSERF + additional number of SPI data to be transacted was reload +This bit is cleared by write 1 to TSERFC bit at SPI_IFCR or by writing the TSER[15:0] (SPI_CR2) register + 10 + 1 + read-only + + + B_0x0 + no acceptation + 0x0 + + + B_0x1 + additional number of data accepted, current transaction continues + 0x1 + + + + + SUSP + suspension status +In Master mode, SUSP is set by hardware when a CSUSP request is done, either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. +SUSP generates an interrupt when EOTIE is set. +This bit has to be cleared prior SPI is disabled by write 1 to SUSPC bit at SPI_IFCR + 11 + 1 + read-only + + + B_0x0 + SPI not suspended (master mode active or other mode). + 0x0 + + + B_0x1 + Master mode is suspended (current frame completed) + 0x1 + + + + + TXC + TxFIFO transmission complete +The flag behavior depends on TSIZE setting. +When TSIZE=0 the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. +If TSIZE <>0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set. + 12 + 1 + read-only + + + B_0x0 + Current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going. + 0x0 + + + B_0x1 + Last TxFIFO frame transmission completed + 0x1 + + + + + RXPLVL + RxFIFO packing leveL +When RXWNE=0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. +(*) optional count when the data size is set up to 8-bit. +When the frame size is greater than 16-bit, these bits read as 00. In consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user then must apply other methods like TSIZE>0 or FTHLV=0. + 13 + 2 + read-only + + + B_0x0 + no next frame is available at RxFIFO + 0x0 + + + B_0x1 + 1 frame is available + 0x1 + + + B_0x2 + 2 frames are available* + 0x2 + + + B_0x3 + 3 frames are available* + 0x3 + + + + + RXWNE + RxFIFO word not empty +Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data. + 15 + 1 + read-only + + + B_0x0 + less than four bytes of RxFIFO space is occupied by data + 0x0 + + + B_0x1 + at least four bytes of RxFIFO space is occupied by data + 0x1 + + + + + CTSIZE + number of data frames remaining in current TSIZE session +The value is not quite reliable when traffic is ongoing on bus and at LP mode too. + 16 + 16 + read-only + + + + + SPI_IFCR + SPI_IFCR + SPI/I2S interrupt/status flags clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOTC + end of transfer flag clear +Writing a 1 into this bit clears EOT flag in the SPI_SR register + 3 + 1 + write-only + + + TXTFC + transmission Transfer Filled flag clear +Writing a 1 into this bit clears TXTF flag in the SPI_SR register + 4 + 1 + write-only + + + UDRC + underrun flag clear +Writing a 1 into this bit clears UDR flag in the SPI_SR register + 5 + 1 + write-only + + + OVRC + overrun flag clear +Writing a 1 into this bit clears OVR flag in the SPI_SR register + 6 + 1 + write-only + + + CRCEC + CRC error flag clear +Writing a 1 into this bit clears CRCE flag in the SPI_SR register + 7 + 1 + write-only + + + TIFREC + TI frame format error flag clear +Writing a 1 into this bit clears TIFRE flag in the SPI_SR register + 8 + 1 + write-only + + + MODFC + mode fault flag clear +Writing a 1 into this bit clears MODF flag in the SPI_SR register + 9 + 1 + write-only + + + TSERFC + TSERFC flag clear +Writing a 1 into this bit clears TSERF flag in the SPI_SR register +Note: TSERF is also reset by writing the TSER[15:0] (SPI_CR2) register + 10 + 1 + write-only + + + SUSPC + SUSPend flag clear +Writing a 1 into this bit clears SUSP flag in the SPI_SR register + 11 + 1 + write-only + + + + + SPI_TXDR + SPI_TXDR + SPI/I2S transmit data register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXDR + transmit data register +The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. +Note: data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. +Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. +halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. +word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. +Write access of this register less than the configured data size is forbidden. + 0 + 32 + write-only + + + + + SPI_RXDR + SPI_RXDR + SPI/I2S receive data register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXDR + receive data register +The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. +Note: Data is always right-aligned. Unused bits are read as zero when the register is read. Writing to the register is ignored. +Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access. +halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access +word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access. +Read access of this register less than the configured data size is forbidden. + 0 + 32 + read-only + + + + + SPI_CRCPOLY + SPI_CRCPOLY + SPI polynomial register + 0x40 + 0x20 + 0x00000107 + 0xFFFFFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used at some other ST products with fixed length of the polynomial string where the most significant bit of the string is always kept hidden. +Length of the polynomial is given by the most significant bit of the value stored at this register. It has to be set greater than DSIZE. CRC33_17 bit has to be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). +Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. + 0 + 32 + read-write + + + + + SPI_TXCRC + SPI_TXCRC + SPI transmitter CRC register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXCRC + CRC register for transmitter +When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. +The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. +Note: A read to this register when the communication is ongoing could return an incorrect value. +Not used for the I2S mode. +Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. +Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. + 0 + 32 + read-only + + + + + SPI_RXCRC + SPI_RXCRC + SPI receiver CRC register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXCRC + CRC register for receiver +When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. +The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. +Note: A read to this register when the communication is ongoing could return an incorrect value. +Not used for the I2S mode. +Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. +Note: The configuration of CRCSIZE bit field is not taken into account when the content of this register is read by software. No masking is applied for unused bits at this case. + 0 + 32 + read-only + + + + + SPI_UDRDR + SPI_UDRDR + SPI underrun data register + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UDRDR + data at slave underrun condition +The register is taken into account at slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings at SPI_CFG1 register. Underrun condition handling depends on setting if UDRDET and UDRCFG bits at SPI_CFG1 register. +Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. + 0 + 32 + read-write + + + + + SPI_I2SCFGR + SPI_I2SCFGR + SPI/I2S configuration register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2SMOD + I2S mode selection + 0 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S/PCM mode is selected + 0x1 + + + + + I2SCFG + I2S configuration mode +others, not used + 1 + 3 + read-write + + + B_0x0 + slave - transmit + 0x0 + + + B_0x1 + slave - receive + 0x1 + + + B_0x2 + master - transmit + 0x2 + + + B_0x3 + master - receive + 0x3 + + + B_0x4 + slave - full duplex + 0x4 + + + B_0x5 + master - full duplex + 0x5 + + + + + I2SSTD + I2S standard selection +For more details on I2S standards, refer to + 4 + 2 + read-write + + + B_0x0 + I2S Philips standard. + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + read-write + + + B_0x0 + short frame synchronization + 0x0 + + + B_0x1 + long frame synchronization + 0x1 + + + + + DATLEN + data length to be transferred + 8 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CHLEN + channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 10 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + CKPOL + serial audio clock polarity + 11 + 1 + read-write + + + B_0x0 + the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK. + 0x0 + + + B_0x1 + the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK. + 0x1 + + + + + FIXCH + fixed channel length in slave + 12 + 1 + read-write + + + B_0x0 + the channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) + 0x0 + + + B_0x1 + the channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) + 0x1 + + + + + WSINV + Word select inversion +This bit is used to invert the default polarity of WS signal. +WS is low. +In PCM mode the start of frame is indicated by a rising edge. +WS is high. +In PCM mode the start of frame is indicated by a falling edge. + 13 + 1 + read-write + + + B_0x0 + in I2S Philips standard, Left channel is transfered when WS is low, and right channel when WS is high. In MSB or LSB justified mode, Left channel is transfered when WS is high, and right channel when + 0x0 + + + B_0x1 + in I2S Philips standard, Left channel is transfered when WS is high, and right channel when WS is low.In MSB or LSB justified mode, Left channel is transfered when WS is low, and right channel when + 0x1 + + + + + DATFMT + data format + 14 + 1 + read-write + + + B_0x0 + the data inside the SPI_RXDR or SPI_TXDR are right aligned + 0x0 + + + B_0x1 + the data inside the SPI_RXDR or SPI_TXDR are left aligned. + 0x1 + + + + + I2SDIV + I2S linear prescaler +I2SDIV can take any values except the value 1, when ODD is also equal to 1. +Refer to for details + 16 + 8 + read-write + + + ODD + odd factor for the prescaler +Refer to for details + 24 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + master clock output enable + 25 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + SPI_I2S_HWCFGR + SPI_I2S_HWCFGR + SPI/I2S hardware configuration register + 0x3f0 + 0x20 + 0x00000000 + 0xFFF00000 + + + TXFCFG + TxFIFO size +0002: the FIFO size is 4 bytes +0003: the FIFO size is 8 bytes +0004: the FIFO size is 16 bytes +0005: the FIFO size is 32 bytes +All the other combinations are reserved. + 0 + 4 + read-only + + + RXFCFG + RxFIFO size +0002: the FIFO size is 4 bytes +0003: the FIFO size is 8 bytes +0004: the FIFO size is 16 bytes +0005: the FIFO size is 32 bytes +All the other combinations are reserved. + 4 + 4 + read-only + + + CRCCFG + CRC configuration for SPI +All the other combinations are reserved. + 8 + 4 + read-only + + + B_0x0 + CRC support is not implemented + 0x0 + + + B_0x1 + CRC support is implemented + 0x1 + + + + + I2SCFG + I2S configuration +All the other combinations are reserved. + 12 + 4 + read-only + + + B_0x0 + I2S support is not implemented + 0x0 + + + B_0x1 + I2S support is implemented + 0x1 + + + + + DSCFG + SPI data size configuration +All the other combinations are reserved. + 16 + 4 + read-only + + + B_0x0 + data size is configurable from 4-bits to 16-bits + 0x0 + + + B_0x1 + data size is configurable from 4-bits to 32-bits + 0x1 + + + + + + + SPI_VERR + SPI_VERR + SPI/I2S version register + 0x3f4 + 0x20 + 0x00000011 + 0xFFFFFFFF + + + MINREV + minor revision of the IP. + 0 + 4 + read-only + + + MAJREV + major revision of the IP. + 4 + 4 + read-only + + + + + SPI_IPIDR + SPI_IPIDR + SPI/I2S identification register + 0x3f8 + 0x20 + 0x00130022 + 0xFFFFFFFF + + + ID + IP identification +MCD identification code which identifies the IP. + 0 + 32 + read-only + + + + + SPI_SIDR + SPI_SIDR + SPI/I2S size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + size identification +Bits[31:8]: fixed code 0xA3C5DD0 +Bits[7:0]: range of address decoding boundary +All the other combination are reserved. + 0 + 32 + read-only + + + B_0x1 + 1 Kbyte + 0x1 + + + B_0x2 + 2 Kbytes + 0x2 + + + B_0x4 + 4 Kbytes + 0x4 + + + B_0x8 + 8 Kbytes + 0x8 + + + + + + + + + SPI2 + 0x4000B000 + + SPI2 + SPI2 global interrupt + 37 + + + + SPI3 + 0x4000C000 + + SPI3 + SPI3 global interrupt + 52 + + + + SPI4 + 0x4C002000 + + SPI4 + SPI4 global interrupt + 85 + + + + SPI5 + 0x4C003000 + + SPI5 + SPI5 global interrupt + 86 + + + + STGENC + STGEN + STGEN + 0x5C008000 + + 0x0 + 0x1000 + registers + + + + STGENC_CNTCR + STGENC_CNTCR + STGENC control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-write + + + B_0x0 + counter disabled and not incrementing + 0x0 + + + B_0x1 + counter enabled and incrementing + 0x1 + + + + + HLTDBG + halt on debug + 1 + 1 + read-write + + + B_0x0 + do not halt on debug; hltdbg signal into the counter has no effect + 0x0 + + + B_0x1 + halt on debug; when hltdbg is driven high, the count value is held static. + 0x1 + + + + + + + STGENC_CNTSR + STGENC_CNTSR + STGENC status register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-only + + + B_0x0 + counter disabled and not incrementing + 0x0 + + + B_0x1 + counter enabled and incrementing + 0x1 + + + + + HLTDBG + halt on debug + 1 + 1 + read-only + + + B_0x0 + do not halt on debug; hltdbg signal into the counter has no effect + 0x0 + + + B_0x1 + halt on debug; when hltdbg is driven high, the count value is held static. + 0x1 + + + + + + + STGENC_CNTCVL + STGENC_CNTCVL + STGENC value lower register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNTCVL_L_32 + current value of the timestamp counter, lower 32 bits +To change the current timestamp value, write the lower 32 bits of the new value to this register before writing the upper 32 bits to STGENC_CNTCVU. The timestamp value is not changed until the STGENC_CNTCVU register is written to. + 0 + 32 + read-write + + + + + STGENC_CNTCVU + STGENC_CNTCVU + STGENC value upper register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNTCVU_U_32 + current value of the timestamp counter, upper 32 bits +To change the current timestamp value, write the lower 32 bits of the new value to STGENC_CNTCVL before writing the upper 32 bits to this register. The 64-bit timestamp value is updated with the value from both writes when this register is written to. + 0 + 32 + read-write + + + + + STGENC_CNTFID0 + STGENC_CNTFID0 + STGENC base frequency register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FREQ + frequency in number of ticks per second. +It can be specified up to 4 GHz. This register must be programmed to match the clock frequency of the clock input to TSGEN (tsgen_clk), in ticks per second. For example, for a 50 MHz clock, the register value has to be 0x02FAF080. + 0 + 32 + read-write + + + + + STGENC_PIDR4 + STGENC_PIDR4 + STGENC peripheral ID4 register + 0xfd0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + DES_2 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. +0b0100 JEDEC continuation code. + 0 + 4 + read-only + + + SIZE + always 0b0000 +Indicates that the device only occupies 4 Kbytes of memory. + 4 + 4 + read-only + + + + + STGENC_PIDR5 + STGENC_PIDR5 + STGENC peripheral ID5 register + 0xfd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR5 + peripheral ID5 + 0 + 32 + read-only + + + + + STGENC_PIDR6 + STGENC_PIDR6 + STGENC peripheral ID6 register + 0xfd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR6 + peripheral ID6 + 0 + 32 + read-only + + + + + STGENC_PIDR7 + STGENC_PIDR7 + STGENC peripheral ID7 register + 0xfdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR7 + peripheral ID7 + 0 + 32 + read-only + + + + + STGENC_PIDR0 + STGENC_PIDR0 + STGENC peripheral ID0 register + 0xfe0 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + PART_0 + bits[7:0] of the 12-bit part number of the component. +The designer of the component assigns this part number. + 0 + 8 + read-only + + + + + STGENC_PIDR1 + STGENC_PIDR1 + STGENC peripheral ID1 register + 0xfe4 + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PART_1 + Bits[11:8] of the 12-bit part number of the component +The designer of the component assigns this part number.. + 0 + 4 + read-only + + + DES_0 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 4 + read-only + + + + + STGENC_PIDR2 + STGENC_PIDR2 + STGENC peripheral ID2 register + 0xfe8 + 0x20 + 0x0000001B + 0xFFFFFFFF + + + DES_1 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + read-only + + + JEDEC + always 1 +Indicates that the JEDEC-assigned designer ID is used. + 3 + 1 + read-only + + + REVISION + device revision number + 4 + 4 + read-only + + + + + STGENC_PIDR3 + STGENC_PIDR3 + STGENC peripheral ID3 register + 0xfec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified +Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000 (no modification done). Customers change this value when they make authorized modifications to this component. + 0 + 4 + read-only + + + REVAND + customer version +0b0000 indicates there are no errata fixes to this component. + 4 + 4 + read-only + + + + + STGENC_CIDR0 + STGENC_CIDR0 + STGENC component ID0 register + 0xff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PRMBL_0 + preamble 0 +Contains bits[7:0] of the component identification code. + 0 + 8 + read-only + + + + + STGENC_CIDR1 + STGENC_CIDR1 + STGENC component ID1 register + 0xff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PRMBL_1 + preamble 1 +Contains bits[11:8] of the component identification code. + 0 + 4 + read-only + + + CLASS + class of the component +For example, the component can be a ROM table or a generic CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. +0b1111 Indicates the component is a CoreSight SoC-400 component. + 4 + 4 + read-only + + + + + STGENC_CIDR2 + STGENC_CIDR2 + STGENC component ID2 register + 0xff8 + 0x20 + 0x00000050 + 0xFFFFFFFF + + + PRMBL_2 + preamble 2 +Contains bits[23:16] of the component identification code + 0 + 8 + read-only + + + + + STGENC_CIDR3 + STGENC_CIDR3 + STGENC component ID3 register + 0xffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PRMBL_3 + preamble 3 +Contains bits[31:24] of the component identification code + 0 + 8 + read-only + + + + + + + STGENR + STGENR + STGENR + 0x5A005000 + + 0x0 + 0x1000 + registers + + + + STGENR_CNTCVL + STGENR_CNTCVL + STGENR value lower register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNTCVL_L_32 + current value of the timestamp counter (the lower 32 bits) + 0 + 32 + read-only + + + + + STGENR_CNTCVU + STGENR_CNTCVU + STGENR value upper register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNTCVU_U_32 + current value of the timestamp counter (the upper 32 bits) + 0 + 32 + read-only + + + + + STGENR_PIDR4 + STGENR_PIDR4 + STGENR peripheral ID4 register + 0xfd0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + DES_2 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 4 + read-only + + + SIZE + always 0b0000 +Indicates that the device only occupies 4 Kbytes of memory. + 4 + 4 + read-only + + + + + STGENR_PIDR5 + STGENR_PIDR5 + STGENR peripheral ID5 register + 0xfd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR5 + peripheral ID5 + 0 + 32 + read-only + + + + + STGENR_PIDR6 + STGENR_PIDR6 + STGENR peripheral ID6 register + 0xfd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR6 + peripheral ID6 + 0 + 32 + read-only + + + + + STGENR_PIDR7 + STGENR_PIDR7 + STGENR peripheral ID7 register + 0xfdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PIDR7 + peripheral ID7 + 0 + 32 + read-only + + + + + STGENR_PIDR0 + STGENR_PIDR0 + STGENR peripheral ID0 register + 0xfe0 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + PART_0 + bits[7:0] of the 12-bit part number of the component. + 0 + 8 + read-only + + + + + STGENR_PIDR1 + STGENR_PIDR1 + STGENR peripheral ID1 register + 0xfe4 + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PART_1 + Bits[11:8] of the 12-bit part number of the component + 0 + 4 + read-only + + + DES_0 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 4 + read-only + + + + + STGENR_PIDR2 + STGENR_PIDR2 + STGENR peripheral ID2 register + 0xfe8 + 0x20 + 0x0000001B + 0xFFFFFFFF + + + DES_1 + part of designer identification +Together PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2, identify the designer of the component. + 0 + 3 + read-only + + + JEDEC + always 1 +Indicates that the JEDEC-assigned designer ID is used. + 3 + 1 + read-only + + + REVISION + device revision number + 4 + 4 + read-only + + + + + STGENR_PIDR3 + STGENR_PIDR3 + STGENR peripheral ID3 register + 0xfec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified +Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000 (no modification done). Customers change this value when they make authorized modifications to this component. + 0 + 4 + read-only + + + REVAND + errata fix identification +0b0000 indicates there are no errata fixes to this component. + 4 + 4 + read-only + + + + + STGENR_CIDR0 + STGENR_CIDR0 + STGENR component ID0 register + 0xff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PRMBL_0 + preamble 0 +Contains bits[7:0] of the component identification code. + 0 + 8 + read-only + + + + + STGENR_CIDR1 + STGENR_CIDR1 + STGENR component ID1 register + 0xff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PRMBL_1 + preamble 1 +Contains bits[11:8] of the component identification code. + 0 + 4 + read-only + + + CLASS + class of the component +Contains bits[15:12] of the component identification code. + 4 + 4 + read-only + + + + + STGENR_CIDR2 + STGENR_CIDR2 + STGENR component ID2 register + 0xff8 + 0x20 + 0x00000050 + 0xFFFFFFFF + + + PRMBL_2 + preamble 2 +Contains bits[23:16] of the component identification code. + 0 + 8 + read-only + + + + + STGENR_CIDR3 + STGENR_CIDR3 + STGENR component ID3 register + 0xffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PRMBL_3 + preamble 3 +Contains bits[31:24] of the component identification code. + 0 + 8 + read-only + + + + + + + SYSCFG + SYSCFG + SYSCFG + 0x50020000 + + 0x0 + 0x400 + registers + + + + SYSCFG_BOOTR + SYSCFG_BOOTR + SYSCFG boot pins control register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + BOOT0 + BOOT0 pin value + 0 + 1 + read-only + + + low + BOOT0 pin connected to VSS + 0x0 + + + high + BOOT0 pin connected to VDD + 0x1 + + + + + BOOT1 + BOOT1 pin value + 1 + 1 + read-only + + + low + BOOT1 pin connected to VSS + 0x0 + + + high + BOOT1 pin connected to VDD + 0x1 + + + + + BOOT2 + BOOT2 pin value + 2 + 1 + read-only + + + low + BOOT2 pin connected to VSS + 0x0 + + + high + BOOT2 pin connected to VDD + 0x1 + + + + + + + SYSCFG_PMCSETR + SYSCFG_PMCSETR + SYSCFG peripheral mode configuration set register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C1_FMP + Fast Mode Plus (FM+) Enable +Set by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C1 use is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C1 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C2_FMP + Fast Mode Plus (FM+) Enable +Set by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C2 use is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C2 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C3_FMP + Fast Mode Plus (FM+) Enable +Set by software. +This bit is secure if I2C3 is set to secure in the ETZPC. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C3 use is possible up to 400kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C3 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C4_FMP + Fast Mode Plus (FM+) Enable +Set by software. +This bit is secure if I2C4 is set to secure in the ETZPC. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C4 use is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C4 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C5_FMP + Fast mode plus (FM+) enable +Set by software. +This bit is secure if I2C5 is set to secure in the ETZPC. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C5 use is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C5 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + EN_BOOSTER + GPIO analog switch supply voltage booster enable. +Set by software. +Used to reduce the total harmonic distortion of the I/O analog switches when VDDA and VDD supplies are below 2.7 V. Activating the booster guarantees the AC performance on I/O analog switches. When activated the performance of the analog switch is the same over the full voltage range. +This bit is always secure. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means booster is disabled + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means booster is enabled. + 0x1 + + + + + ANASWVDD + GPIO analog switch supply voltage selection +Cleared by software. +This bit is always secure. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means analog switches are supplied by VDDA (if present and EN_BOOSTER=0) or by the booster output (EN_BOOSTER=1) + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means analog switches are supplied by VDD. + 0x1 + + + + + ETH1_CLK_SEL + Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY. +Set by software. +This bit is secure if ETH1 is set to secure in the ETZPC. + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the transmit clock comes from the ETHx_CLK125 pin. + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the transmit clock comes from the RCC. + 0x1 + + + + + ETH1_REF_CLK_SEL + Ethernet reference clock selection. +Set by software. +This bit is secure if ETH1 is set to secure in the ETZPC. + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the receive clock (MII/RGMII mode) or the reference clock (RMII mode) comes from the ETH1_RX_CLK/ETH1_REF_CLK pin. + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the reference clock (RMII mode) comes from the RCC + 0x1 + + + + + ETH1_SEL + Ethernet PHY interface selection. +Set by software. Writing '0' has no effect. Set individual bits by writing '1’. Reading means: +Note: Configuration must be done while the ETH is under reset and before enabling the ETH clocks +This bit field is secure if ETH1 is set to secure in the ETZPC. + 21 + 3 + read-write + + + B_0x0 + MII + 0x0 + + + B_0x1 + RGMII + 0x1 + + + B_0x4 + RMII + 0x4 + + + + + ETH2_CLK_SEL + Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY. +Set by software. +This bit is secure if ETH2 is set to secure in the ETZPC. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the transmit clock comes from the ETHx_CLK125 pin. + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the transmit clock comes from the RCC. + 0x1 + + + + + ETH2_REF_CLK_SEL + Ethernet reference clock selection. +Set by software. +This bit is secure if ETH2 is set to secure in the ETZPC. + 25 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the receive clock (MII/RGMII mode) or the reference clock (RMII mode) comes from the ETH2_RX_CLK/ETH2_REF_CLK pin. + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the reference clock (RMII mode) comes from the RCC + 0x1 + + + + + ETH2_SEL + Ethernet PHY interface selection. +Set by software. Writing '0' has no effect. Set individual bits by writing '1’. Reading means: +Note: Configuration must be done while the ETH is under reset and before enabling the ETH clocks +This bit field is secure if ETH2 is set to secure in the ETZPC. + 29 + 3 + read-write + + + B_0x0 + MII + 0x0 + + + B_0x1 + RGMII + 0x1 + + + B_0x4 + RMII + 0x4 + + + + + + + SYSCFG_PMCCLRR + SYSCFG_PMCCLRR + SYSCFG peripheral mode configuration clear register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C1_FMP + Fast Mode Plus (FM+) Enable +Cleared by software. + 0 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C1 usage is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C1 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C2_FMP + Fast Mode Plus (FM+) Enable +Cleared by software. + 1 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C2 usage is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C2 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C3_FMP + Fast Mode Plus (FM+) Enable +Cleared by software. +This bit is secure if I2C3 is set to secure in the ETZPC. + 2 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C3 usage is possible up to 400kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C3 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C4_FMP + Fast Mode Plus (FM+) Enable +Cleared by software. +This bit is secure if I2C4 is set to secure in the ETZPC. + 3 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C4 usage is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C4 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + I2C5_FMP + Fast Mode Plus (FM+) Enable +Cleared by software. +This bit is secure if I2C5 is set to secure in the ETZPC. + 4 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means I2C5 usage is possible up to 400 kHz + 0x0 + + + B_0x1 + Writing '1' sets this bit, reading '1' means the I2C5 SCL & SDA I/Os are in Fast mode plus (FM+), when the corresponding alternate function is selected. The I/O low drive is enhanced to support up to 1 MHz. + 0x1 + + + + + EN_BOOSTER + GPIO analog switch supply voltage booster enable. +Cleared by software. +Used to reduce the Total harmonic distortion of the I/O analog switches when VDDA and VDD supplies are below 2.7 V. Activating the booster guarantees the AC performance on I/O analog switches. When activated the performance of the analog switch is the same over the full voltage range. +This bit is always secure. + 8 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means Booster is disabled + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means Booster is enabled. + 0x1 + + + + + ANASWVDD + GPIO analog switch supply voltage selection +Cleared by software. +(if present and EN_BOOSTER=0) or by the booster output (EN_BOOSTER=1) +This bit is always secure. + 9 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means analog switches are supplied by VDDA + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means analog switches are supplied by VDD. + 0x1 + + + + + ETH1_CLK_SEL + Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY. +Set by software. +This bit is secure if ETH1 is set to secure in the ETZPC + 16 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the transmit clock comes from the ETHx_CLK125 pin. + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means the transmit clock comes from the RCC. + 0x1 + + + + + ETH1_REF_CLK_SEL + Ethernet reference clock selection. +Set by software. +This bit is secure if ETH1 is set to secure in the ETZPC + 17 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the receive clock (MII/RGMII mode) or the reference clock (RMII mode) comes from the ETH1_RX_CLK/ETH1_REF_CLK pin. + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means the reference clock (RMII mode) comes from the RCC + 0x1 + + + + + ETH1_SEL + Ethernet PHY interface selection. +Set by software. Writing '0' has no effect. Clear individual bits by writing '1’. Reading means: +Note: Configuration must be done while the ETH is under reset and before enabling the ETH clocks +This bit field is secure if ETH1 is set to secure in the ETZPC. + 21 + 3 + read-write + + + B_0x0 + MII + 0x0 + + + B_0x1 + RGMII + 0x1 + + + B_0x4 + RMII + 0x4 + + + + + ETH2_CLK_SEL + Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY. +Set by software. +This bit is secure if ETH2 is set to secure in the ETZPC. + 24 + 1 + read-write + + + B_0x0 + Writing '0' has no effect, reading '0' means the transmit clock comes from the ETHx_CLK125 pin. + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means the transmit clock comes from the RCC. + 0x1 + + + + + ETH2_REF_CLK_SEL + Ethernet reference clock selection. +Set by software. +This bit is secure if ETH2 is set to secure in the ETZPC. + 25 + 1 + read-write + + + B_0x0 + 'Writing '0' has no effect, reading '0' means the receive clock (MII/RGMII mode) or the reference clock (RMII mode) comes from the ETH2_RX_CLK/ETH2_REF_CLK pin. + 0x0 + + + B_0x1 + Writing '1' clears this bit, reading '1' means the reference clock (RMII mode) comes from the RCC + 0x1 + + + + + ETH2_SEL + Ethernet PHY interface selection. +Set by software. Writing '0' has no effect. Clear individual bits by writing '1’. Reading means: +Note: Configuration must be done while the ETH is under reset and before enabling the ETH clocks +This bit field is secure if ETH2 is set to secure in the ETZPC. + 29 + 3 + read-write + + + B_0x0 + MII + 0x0 + + + B_0x1 + RGMII + 0x1 + + + B_0x4 + RMII + 0x4 + + + + + + + SYSCFG_BOOTCR + SYSCFG_BOOTCR + SYSCFG boot control register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BMEN + Boot mode enable +This bit is writable only by secure privileged code. It should be used only during secure boot time, to ensure the timely execution of the firmware in charge of tamper management. +When this bit is cleared from 1 to 0 while a potential tamper event is active, accesses to SRAM3 are automatically blocked (as defined above) and PKA, SAES, HASH and CRYP peripherals are reset. +When a confirmed (not potential) tamper is raised by TAMP peripheral, SRAM3 is erased (as defined in TAMP) and PKA, SAES, HASH and CRYP peripherals are reset regardless of BMEN value. + 0 + 1 + read-write + + + B_0x0 + While a potential tamper event is raised by TAMP peripheral, multiple blocking and erase actions occur in the device. Among those actions the SRAM3 reads as zero and the writes to SRAM3 are ignored. Also a reset pulse is triggered on PKA, SAES, HASH and CRYP peripherals. See TAMP section for details. + 0x0 + + + B_0x1 + While a potential tamper event is raised by TAMP peripheral, read and write accesses to the SRAM3 are allowed, and the PKA, SAES, HASH and CRYP peripherals are not reset. The other blocking and erasing actions defined in TAMP peripheral are not impacted. + 0x1 + + + + + + + SYSCFG_SRAM3ERASER + SYSCFG_SRAM3ERASER + SYSCFG SRAM3 erase register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRAM3ER + SRAM3 erase request +This bit is set by software and automatically reset by hardware at the end of the erase operation. It can only be set if the correct unlock sequence has previously been written to the SYSCFG_SRAM3KR.KEY[7:0] register field. This bit is secure if SRAM3 is set to secure in the ETZPC. + 0 + 1 + read-write + + + SRAM3EO + SRAM3 erase ongoing +This bit indicates whether an erase of SRAM3 is being carried out, whatever the trigger (tamper or software). + 1 + 1 + read-only + + + B_0x0 + no erase ongoing + 0x0 + + + B_0x1 + erase ongoing + 0x1 + + + + + + + SYSCFG_SRAM3KR + SYSCFG_SRAM3KR + SYSCFG SRAM3 erase key register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + SRAM3 software erase key +Writing the following sequence to KEY[7:0] unlocks the SRAM3 software erase feature: +0xCA +0x53 +Writing any other value locks the feature. + 0 + 8 + write-only + + + + + SYSCFG_CMPCR + SYSCFG_CMPCR + SYSCFG main compensation cell control register + 0x20 + 0x20 + 0x00870000 + 0x00FFFFFF + + + SW_CTRL + Compensation software control +Note: SW_CTRL = 0 is not taken into account until READY = 1. +This means that whatever SW_CTRL value, the RANSRC[3:0] and RAPSRC[3:0] are used for I/O compensation when the compensation cell is in power down (EN = 0, which is the case after a reset). + 1 + 1 + read-write + + + B_0x0 + I/O compensation values come from compensation values in ANSRC[3:0] and APSRC[3:0] + 0x0 + + + B_0x1 + I/O compensation values come from RANSRC[3:0] and RAPSRC[3:0] register values + 0x1 + + + + + READY + Compensation cell ready flag + 8 + 1 + read-only + + + B_0x0 + I/O compensation cell not ready + 0x0 + + + B_0x1 + I/O compensation cell ready, the values of APSRC[3:0] and ANSRC[3:0] are valid + 0x1 + + + + + RANSRC + NMOS I/O compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation + 16 + 4 + read-write + + + B_0x1 + maximum compensation of slow conditions + 0x1 + + + B_0x7 + compensation for typical conditions + 0x7 + + + B_0xE + maximum compensation of fast conditions + 0xE + + + + + RAPSRC + PMOS I/O Compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation + 20 + 4 + read-write + + + B_0x1 + maximum compensation of fast conditions + 0x1 + + + B_0x8 + compensation for typical conditions + 0x8 + + + B_0xE + maximum compensation of slow conditions + 0xE + + + + + ANSRC + NMOS I/O compensation value provided by compensation cell +Value sent to I/Os when SW_CTRL = 0 and READY = 1. + 24 + 4 + read-only + + + APSRC + PMOS I/O compensation value provided by compensation cell +Value sent to I/O compensation when SW_CTRL = 0 and READY = 1. + 28 + 4 + read-only + + + + + SYSCFG_CMPENSETR + SYSCFG_CMPENSETR + SYSCFG main compensation cell enable set register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Set by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if EN is set to 0. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in power-down mode + 0x0 + + + enabled + Writing '1' enables I/O compensation cell, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_CMPENCLRR + SYSCFG_CMPENCLRR + SYSCFG main compensation cell enable set register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Cleared by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if EN is set to 0. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in powerdown mode + 0x0 + + + enabled + Writing '1' clears EN bit, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_CBR + SYSCFG_CBR + SYSCFG control timer break register + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDL + PVD lock enable bit +This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application. + 0x0 + + + B_0x1 + PVD interrupt connected to TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits are read only. + 0x1 + + + + + + + SYSCFG_CMPSD1CR + SYSCFG_CMPSD1CR + SYSCFG VDDSD1 compensation cell control register + 0x30 + 0x20 + 0x00870000 + 0x00FFFFFF + + + SW_CTRL + Compensation software control +Note: SW_CTRL = 0 is not taken into account until READY = 1. +This means that whatever SW_CTRL value, the RANSRC[3:0] and RAPSRC[3:0] are used for I/O compensation when the compensation cell is in power down (EN = 0, which is the case after a reset). +This bit is secure if SDMMC1 is set to secure in the ETZPC. + 1 + 1 + read-write + + + B_0x0 + I/O compensation values come from compensation values in ANSRC[3:0] and APSRC[3:0] + 0x0 + + + B_0x1 + I/O compensation values come from RANSRC[3:0] and RAPSRC[3:0] register values + 0x1 + + + + + READY + Compensation cell ready flag + 8 + 1 + read-only + + + B_0x0 + I/O compensation cell not ready. + 0x0 + + + B_0x1 + I/O compensation cell ready, the values of APSRC[3:0] and ANSRC[3:0] are valid + 0x1 + + + + + RANSRC + NMOS I/O compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation +This bit field is secure if SDMMC1 is set to secure in the ETZPC. + 16 + 4 + read-write + + + B_0x1 + maximum compensation of slow conditions + 0x1 + + + B_0x7 + compensation for typical conditions + 0x7 + + + B_0xE + maximum compensation of fast conditions + 0xE + + + + + RAPSRC + PMOS I/O compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation +This bit field is secure if SDMMC1 is set to secure in the ETZPC. + 20 + 4 + read-write + + + B_0x1 + maximum compensation of fast conditions + 0x1 + + + B_0x8 + compensation for typical conditions + 0x8 + + + B_0xE + maximum compensation of slow conditions + 0xE + + + + + ANSRC + NMOS I/O Compensation value provided by compensation cell +Value sent to I/Os when SW_CTRL = 0 and READY = 1. + 24 + 4 + read-only + + + APSRC + PMOS I/O Compensation value provided by compensation cell +Value sent to I/Os compensation when SW_CTRL = 0 and READY = 1. + 28 + 4 + read-only + + + + + SYSCFG_CMPSD1ENSETR + SYSCFG_CMPSD1ENSETR + SYSCFG VDDSD1 compensation cell enable set register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Set by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if MPU_EN is set to 0. +This bit is secure if SDMMC1 is set to secure in the ETZPC. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in power-down mode + 0x0 + + + enabled + Writing '1' enables I/O compensation cell, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_CMPSD1ENCLRR + SYSCFG_CMPSD1ENCLRR + SYSCFG VDDSD1 compensation cell enable clear register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Cleared by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if EN is set to 0. +This bit is secure if SDMMC1 is set to secure in the ETZPC. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in powerdown mode + 0x0 + + + enabled + Writing '1' clear EN bit, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_CMPSD2CR + SYSCFG_CMPSD2CR + SYSCFG VDDSD2 compensation cell control register + 0x40 + 0x20 + 0x00870000 + 0x00FFFFFF + + + SW_CTRL + Compensation Software Control +Note: SW_CTRL = 0 is not taken into account until READY = 1. +This means that whatever SW_CTRL value, the RANSRC[3:0] and RAPSRC[3:0] are used for I/O compensation when the compensation cell is in power down (EN = 0, which is the case after a reset). +This bit is secure if SDMMC2 is set to secure in the ETZPC + 1 + 1 + read-write + + + B_0x0 + I/O compensation values come from compensation values in ANSRC[3:0] and APSRC[3:0] + 0x0 + + + B_0x1 + I/O compensation values come from RANSRC[3:0] and RAPSRC[3:0] register values + 0x1 + + + + + READY + Compensation cell ready flag + 8 + 1 + read-only + + + B_0x0 + I/O compensation cell not ready. + 0x0 + + + B_0x1 + I/O compensation cell ready, the values of APSRC[3:0] and ANSRC[3:0] are valid + 0x1 + + + + + RANSRC + NMOS I/O compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation +This bit field is secure if SDMMC2 is set to secure in the ETZPC. + 16 + 4 + read-write + + + B_0x1 + maximum compensation of slow conditions + 0x1 + + + B_0x7 + compensation for typical conditions + 0x7 + + + B_0xE + maximum compensation of fast conditions + 0xE + + + + + RAPSRC + PMOS I/O compensation value sent to I/Os when SW_CTRL = 1 +.... +.... +Note: If compensation is needed, it is recommended to use automatic compensation +This bit field is secure if SDMMC2 is set to secure in the ETZPC. + 20 + 4 + read-write + + + B_0x1 + maximum compensation of fast conditions + 0x1 + + + B_0x8 + compensation for typical conditions + 0x8 + + + B_0xE + maximum compensation of slow conditions + 0xE + + + + + ANSRC + NMOS I/O Compensation value provided by compensation cell +Value sent to I/Os when SW_CTRL = 0 and READY = 1 + 24 + 4 + read-only + + + APSRC + PMOS I/O Compensation value provided by compensation cell +Value sent to I/Os compensation when SW_CTRL = 0 and READY = 1 + 28 + 4 + read-only + + + + + SYSCFG_CMPSD2ENSETR + SYSCFG_CMPSD2ENSETR + SYSCFG VDDSD2 compensation cell enable set register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Set by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if EN is set to 0. +This bit is secure if SDMMC2 is set to secure in the ETZPC. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in power-down mode + 0x0 + + + enabled + Writing '1' enables I/O compensation cell, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_CMPSD2ENCLRR + SYSCFG_CMPSD2ENCLRR + SYSCFG VDDSD2 compensation cell enable clear register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Compensation cell enable +Cleared by software. +Note: The CSI oscillator must be enabled and ready (controlled in RCC) before EN can be set to 1. Similarly, the CSI oscillator can be disabled only if EN is set to 0. +This bit is secure if SDMMC2 is set to secure in the ETZPC. + 0 + 1 + read-write + + + power_down + Writing '0' has no effect, reading '0’ means I/O compensation cell in powerdown mode + 0x0 + + + enabled + Writing '1' clear MPU_EN bit, reading '1’ means I/O compensation cell is enabled + 0x1 + + + + + + + SYSCFG_HSLVEN0R + SYSCFG_HSLVEN0R + SYSCFG high-speed low-voltage enable register 0 + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN1R + SYSCFG_HSLVEN1R + SYSCFG high-speed low-voltage enable register 1 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN2R + SYSCFG_HSLVEN2R + SYSCFG high-speed low-voltage enable register 2 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN3R + SYSCFG_HSLVEN3R + SYSCFG high-speed low-voltage enable register 3 + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN4R + SYSCFG_HSLVEN4R + SYSCFG high-speed low-voltage enable register 4 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN5R + SYSCFG_HSLVEN5R + SYSCFG high-speed low-voltage enable register 5 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN6R + SYSCFG_HSLVEN6R + SYSCFG high-speed low-voltage enable register 6 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN7R + SYSCFG_HSLVEN7R + SYSCFG high-speed low-voltage enable register 7 + 0x6c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN8R + SYSCFG_HSLVEN8R + SYSCFG high-speed low-voltage enable register 8 + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN9R + SYSCFG_HSLVEN9R + SYSCFG high-speed low-voltage enable register 9 + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN10R + SYSCFG_HSLVEN10R + SYSCFG high-speed low-voltage enable register 10 + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_HSLVEN11R + SYSCFG_HSLVEN11R + SYSCFG high-speed low-voltage enable register 11 + 0x7c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSLVEN + High-speed low-voltage I/O mode enable. +Controls the speed of _h and _vh type I/Os associated with an interface when that interface is selected in the AFMUX +When writing: +Others: disables high speed mode +When reading: + 0 + 16 + write-only + + + B_0x1018 + enables high speed mode + 0x1018 + + + B_0x1 + high speed mode enabled + 0x1 + + + B_0x0 + high speed mode disabled + 0x0 + + + + + + + SYSCFG_IDC + SYSCFG_IDC + SYSCFG identity code register + 0x380 + 0x20 + 0x10006501 + 0xFFFFFFFF + + + DEV_ID + device ID + 0 + 12 + read-only + + + B_0x501 + STM32MP13xx + 0x501 + + + + + REV_ID + device revision +0x1000 = Rev. 1 + 16 + 16 + read-only + + + + + SYSCFG_VERR + SYSCFG_VERR + SYSCFG version register + 0x3f4 + 0x20 + 0x00000030 + 0xFFFFFFFF + + + MINREV + Minor revision +These bits return the SYSCFG minor revision. +Minor revision is 0. + 0 + 4 + read-only + + + MAJREV + Major revision +These bits return the SYSCFG major revision. +Major revision is 3. + 4 + 4 + read-only + + + + + SYSCFG_IPIDR + SYSCFG_IPIDR + SYSCFG identification register + 0x3f8 + 0x20 + 0x00030001 + 0xFFFFFFFF + + + ID + SYSCFG identifier +These bits return the SYSCFG identifier value. + 0 + 32 + read-only + + + + + SYSCFG_SIDR + SYSCFG_SIDR + SYSCFG size identification register + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size identification +These bits return the size of the memory region allocated to SYSCFG registers. + 0 + 32 + read-only + + + + + + + TAMP + TAMP + TAMP + 0x5C00A000 + + 0x0 + 0x400 + registers + + + TAMP + Tamper interrupt (include LSECSS interrupts) + 2 + + + TAMP_S + TAMP tamper secure interrupt + 128 + + + + TAMP_CR1 + TAMP_CR1 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP3E + 2 + 1 + + + ITAMP1E + ITAMP1E + 16 + 1 + + + ITAMP2E + ITAMP2E + 17 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP8E + ITAMP8E + 23 + 1 + + + + + TAMP_CR2 + TAMP_CR2 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + TAMP_FLTCR + TAMP_FLTCR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + TAMP_ATCR1 + TAMP_ATCR1 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x10 + 0x20 + read-write + 0x00070000 + + + TAMP1AM + TAMP1AM + 0 + 1 + + + TAMP2AM + TAMP2AM + 1 + 1 + + + TAMP3AM + TAMP3AM + 2 + 1 + + + ATOSEL1 + ATOSEL1 + 8 + 2 + + + ATOSEL2 + ATOSEL2 + 10 + 2 + + + ATOSEL3 + ATOSEL3 + 12 + 2 + + + ATCKSEL + ATCKSEL + 16 + 3 + + + ATPER + ATPER + 24 + 3 + + + ATOSHARE + ATOSHARE + 30 + 1 + + + FLTEN + FLTEN + 31 + 1 + + + + + TAMP_ATSEEDR + TAMP_ATSEEDR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x14 + 0x20 + write-only + 0x00000000 + + + SEED + SEED + 0 + 32 + + + + + TAMP_ATOR + TAMP_ATOR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x18 + 0x20 + read-only + 0x00000000 + + + PRNG + PRNG + 0 + 8 + + + SEEDF + SEEDF + 14 + 1 + + + INITS + INITS + 15 + 1 + + + + + TAMP_SMCR + TAMP_SMCR + This register can be written only when the APB access is secure. + 0x20 + 0x20 + read-write + 0x80000000 + + + BKPRWDPROT + BKPRWDPROT + 0 + 8 + + + BKPWDPROT + BKPWDPROT + 16 + 8 + + + TAMPDPROT + TAMPDPROT + 31 + 1 + + + + + TAMP_IER + TAMP_IER + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP1IE + ITAMP1IE + 16 + 1 + + + ITAMP2IE + ITAMP2IE + 17 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP8IE + ITAMP8IE + 23 + 1 + + + + + TAMP_SR + TAMP_SR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP1F + ITAMP1F + 16 + 1 + + + ITAMP2F + ITAMP2F + 17 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP8F + ITAMP8F + 23 + 1 + + + + + TAMP_MISR + TAMP_MISR + TAMP non-secure masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP1MF + ITAMP1MF + 16 + 1 + + + ITAMP2MF + ITAMP2MF + 17 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP8MF + ITAMP8MF + 23 + 1 + + + + + TAMP_SMISR + TAMP_SMISR + TAMP secure masked interrupt status register + 0x38 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP1MF + ITAMP1MF + 16 + 1 + + + ITAMP2MF + ITAMP2MF + 17 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP8MF + ITAMP8MF + 23 + 1 + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + write-only + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP1F + CITAMP1F + 16 + 1 + + + CITAMP2F + CITAMP2F + 17 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP8F + CITAMP8F + 23 + 1 + + + + + TAMP_COUNTR + TAMP_COUNTR + TAMP monotonic counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + COUNT + COUNT + 0 + 32 + + + + + TAMP_CFGR + TAMP_CFGR + TAMP configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + OUT3_RMP + OUT3_RMP + 0 + 1 + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP9R + TAMP_BKP9R + TAMP backup 9 register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP10R + TAMP_BKP10R + TAMP backup 10 register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP11R + TAMP_BKP11R + TAMP backup 11 register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP12R + TAMP_BKP12R + TAMP backup 12 register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP13R + TAMP_BKP13R + TAMP backup 13 register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP14R + TAMP_BKP14R + TAMP backup 14 register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP15R + TAMP_BKP15R + TAMP backup 15 register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP16R + TAMP_BKP16R + TAMP backup 16 register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP17R + TAMP_BKP17R + TAMP backup 17 register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP18R + TAMP_BKP18R + TAMP backup 18 register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP19R + TAMP_BKP19R + TAMP backup 19 register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP20R + TAMP_BKP20R + TAMP backup 20 register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP21R + TAMP_BKP21R + TAMP backup 21 register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP22R + TAMP_BKP22R + TAMP backup 22 register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP23R + TAMP_BKP23R + TAMP backup 23 register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP24R + TAMP_BKP24R + TAMP backup 24 register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP25R + TAMP_BKP25R + TAMP backup 25 register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP26R + TAMP_BKP26R + TAMP backup 26 register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP27R + TAMP_BKP27R + TAMP backup 27 register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP28R + TAMP_BKP28R + TAMP backup 28 register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP29R + TAMP_BKP29R + TAMP backup 29 register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP30R + TAMP_BKP30R + TAMP backup 30 register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP31R + TAMP_BKP31R + TAMP backup 31 register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_HWCFGR2 + TAMP_HWCFGR2 + TAMP hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000101 + + + OPTIONREG_OUT + OPTIONREG_OUT + 0 + 8 + + + TRUST_ZONE + TRUST_ZONE + 8 + 4 + + + + + TAMP_HWCFGR1 + TAMP_HWCFGR1 + TAMP hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x009D1320 + + + BACKUP_REGS + BACKUP_REGS + 0 + 8 + + + TAMPER + TAMPER + 8 + 4 + + + ACTIVE_TAMPER + ACTIVE_TAMPER + 12 + 4 + + + INT_TAMPER + INT_TAMPER + 16 + 16 + + + + + TAMP_VERR + TAMP_VERR + TAMP version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + TAMP_IPIDR + TAMP_IPIDR + TAMP identification register + 0x3F8 + 0x20 + read-only + 0x00121033 + + + ID + ID + 0 + 32 + + + + + TAMP_SIDR + TAMP_SIDR + TAMP size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + TIM1 + TIM + TIM + 0x44000000 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 break interrupt + 25 + + + TIM1_UP + TIM1 update interrupt + 26 + + + TIM1_TRG_COM + TIM1 trigger and commutation interrupt + 27 + + + TIM1_CC + TIM1 capture compare interrupt + 28 + + + + TIM1_CR1 + TIM1_CR1 + 0x0 + 16 + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): +Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT. + 8 + 2 + read-write + + + B_0x0 + tDTS=tCK_INT + 0x0 + + + B_0x1 + tDTS=2*tCK_INT + 0x1 + + + B_0x2 + tDTS=4*tCK_INT + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM1_SMCR + TIM1_SMCR + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + TS1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS2 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + TS2 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + + + TIM1_DIER + TIM1_DIER + 0xc + 16 + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM1_EGR + TIM1_EGR + 0x14 + 16 + 0x00000000 + 0x0000FFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM1_CCMR1_output + TIM1_CCMR1_output + TIM1 capture/compare mode register 1 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M1 + Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M2 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + OC2M2 + Output Compare 2 mode +Refer to OC1M[3:0] description. + 24 + 1 + read-write + + + + + TIM1_CCMR1_input + TIM1_CCMR1_input + TIM1 capture/compare mode register 1 [alternate] + TIM1_CCMR1_output + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR2_output + TIM1_CCMR2_output + TIM1 capture/compare mode register 2 [alternate] + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M1 + Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M1 + Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M2 + Output compare 3 mode +Refer to OC1M[3:0] description. + 16 + 1 + read-write + + + OC4M2 + Output compare 4 mode +Refer to OC3M[3:0] description. + 24 + 1 + read-write + + + + + TIM1_CCMR2_input + TIM1_CCMR2_input + TIM1 capture/compare mode register 2 [alternate] + TIM1_CCMR2_output + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCER + TIM1_CCER + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + 0x28 + 16 + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + 0x2c + 16 + 0x0000FFFF + 0x0000FFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM1_RCR + TIM1_RCR + 0x30 + 16 + 0x00000000 + 0x0000FFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + 0x34 + 16 + 0x00000000 + 0x0000FFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + 0x38 + 16 + 0x00000000 + 0x0000FFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + 0x3c + 16 + 0x00000000 + 0x0000FFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + 0x40 + 16 + 0x00000000 + 0x0000FFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup +This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. +DTG[7:5] = 0xx => DT = DTG[7:0] x tDTG with tDTG = tDTS. +DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x tDTG with tDTG = 2 x tDTS. +DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 8 x tDTS. +DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 16 x tDTS. +Example if tDTS = 125 ns (8 MHz), dead-time possible values are: +0 to 15875 ns by 125 ns steps, +16 μs to 31750 ns  by 250 ns steps, +32 μs to 63 μs by 1 μs steps, +64 μs to 126 μs by 2 μs steps +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per ). +Note: The BKIN2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM1_DCR + TIM1_DCR + 0x48 + 16 + 0x00000000 + 0x0000FFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM1_DMAR + TIM1_DMAR + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M1 + Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M1 + Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M2 + Output compare 5 mode +Refer to OC1M description. + 16 + 1 + read-write + + + OC6M2 + Output compare 6 mode +Refer to OC1M description. + 24 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + 0x5c + 16 + 0x00000000 + 0x0000FFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM1_AF1 + TIM1_AF1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKDF1BK0E + BRK dfsdm1_break[0] enable +This bit enables the dfsdm1_break[0] for the timer’s BRK input. dfsdm1_break[0] output is 'ORed’ with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + dfsdm1_break[0] input disabled + 0x0 + + + B_0x1 + dfsdm1_break[0] input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR input is connected to I/O + 0x0 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + ADC2 AWD1 + 0x6 + + + B_0x7 + ADC2 AWD2 + 0x7 + + + B_0x8 + ADC2 AWD3 + 0x8 + + + + + + + TIM1_AF2 + TIM1_AF2 + 0x64 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2DF1BK1E + BRK2 dfsdm1_break[1] enable +This bit enables the dfsdm1_break[1] for the timer’s BRK2 input. dfsdm1_break[1] output is 'ORed’ with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + dfsdm1_break[1] input disabled + 0x0 + + + B_0x1 + dfsdm1_break[1] input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM1_TISEL + TIM1_TISEL + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM1_CH1 input + 0x0 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM1_CH2 input + 0x0 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM1_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM1_CH4 input + 0x0 + + + + + + + + + TIM2 + TIM2 + TIM2 + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 29 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM2_CCMR1_output + TIM2_CCMR1ALTERNATE2 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable +Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + B_0x8 + Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. + 0x8 + + + B_0x9 + Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. + 0x9 + + + B_0xC + Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. + 0xC + + + B_0xD + Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. + 0xD + + + B_0xE + Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. + 0xE + + + B_0xF + Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. + 0xF + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M1 + Output compare 2 mode +refer to OC1M description on bits 6:4 + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M2 + Output compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + B_0x8 + Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. + 0x8 + + + B_0x9 + Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. + 0x9 + + + B_0xC + Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. + 0xC + + + B_0xD + Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. + 0xD + + + B_0xE + Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. + 0xE + + + B_0xF + Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. + 0xF + + + + + OC2M2 + Output compare 2 mode +refer to OC1M description on bits 6:4 + 24 + 1 + read-write + + + + + TIM2_CCMR1_input + TIM2_CCMR1_input + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + TIM2_CCMR1_output + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM2_CCMR2_output + TIM2_CCMR2_output + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M1 + Output compare 3 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M1 + Output compare 4 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M2 + Output compare 3 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 16 + 1 + read-write + + + OC4M2 + Output compare 4 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 24 + 1 + read-write + + + + + TIM2_CCMR2_intput + TIM2_CCMR2_intput + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + TIM2_CCMR2_output + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM2_AF1 + TIM2_AF1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR input is connected to I/O + 0x0 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + ADC2 AWD1 + 0x6 + + + B_0x7 + ADC2 AWD2 + 0x7 + + + B_0x8 + ADC2 AWD3 + 0x8 + + + + + + + TIM8_TISEL + TIM8_TISEL + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM8_CH1 input + 0x0 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM8_CH2 input + 0x0 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM8_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM8_CH4 input + 0x0 + + + + + + + + + TIM3 + 0x40001000 + + TIM3 + TIM3 global interrupt + 30 + + + + TIM4 + 0x40002000 + + TIM4 + TIM4 global interrupt + 31 + + + + TIM5 + 0x40003000 + + TIM5 + TIM5 global interrupt + 51 + + + + TIM6 + TIM6 + TIM6 + 0x40004000 + + 0x0 + 0x400 + registers + + + TIM6 + TIM6 global interrupt + 55 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + ARPE + ARPE + 7 + 1 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + MMS + 4 + 3 + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + UDE + UDE + 8 + 1 + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + + + TIM7 + 0x40005000 + + TIM7 + TIM7 global interrupt + 56 + + + + TIM8 + TIM + TIM + 0x44001000 + + 0x0 + 0x400 + registers + + + TIM8_BRK + TIM8 break interrupt + 44 + + + TIM8_UP + TIM8 update interrupt + 45 + + + TIM8_TRG_COM + TIM8 trigger and commutation interrupt + 46 + + + TIM8_CC + TIM8 capture compare interrupt + 47 + + + + TIM8_CR1 + TIM8_CR1 + 0x0 + 16 + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): +Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT. + 8 + 2 + read-write + + + B_0x0 + tDTS=tCK_INT + 0x0 + + + B_0x1 + tDTS=2*tCK_INT + 0x1 + + + B_0x2 + tDTS=4*tCK_INT + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM8_CR2 + TIM8_CR2 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM8_SMCR + TIM8_SMCR + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + TS1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS2 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + TS2 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + + + TIM8_DIER + TIM8_DIER + 0xc + 16 + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM8_SR + TIM8_SR + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM8_EGR + TIM8_EGR + 0x14 + 16 + 0x00000000 + 0x0000FFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM8_CCMR1_input + TIM8_CCMR1_input + TIM8 capture/compare mode register 1 [alternate] + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM8_CCMR1_output + TIM8_CCMR1_output + TIM8 capture/compare mode register 1 [alternate] + TIM8_CCMR1_input + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M1 + Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M2 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + + + OC2M2 + Output Compare 2 mode +Refer to OC1M[3:0] description. + 24 + 1 + read-write + + + + + TIM8_CCMR2_input + TIM8_CCMR2_input + TIM8 capture/compare mode register 2 [alternate] + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM8_CCMR2_output + TIM8_CCMR2_output + TIM8 capture/compare mode register 2 [alternate] + TIM8_CCMR2_input + 0x1c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M1 + Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M1 + Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M2 + Output compare 3 mode +Refer to OC1M[3:0] description. + 16 + 1 + read-write + + + OC4M2 + Output compare 4 mode +Refer to OC3M[3:0] description. + 24 + 1 + read-write + + + + + TIM8_CCER + TIM8_CCER + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM8_CNT + TIM8_CNT + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM8_PSC + TIM8_PSC + 0x28 + 16 + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). + 0 + 16 + read-write + + + + + TIM8_ARR + TIM8_ARR + 0x2c + 16 + 0x0000FFFF + 0x0000FFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM8_RCR + TIM8_RCR + 0x30 + 16 + 0x00000000 + 0x0000FFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM8_CCR1 + TIM8_CCR1 + 0x34 + 16 + 0x00000000 + 0x0000FFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM8_CCR2 + TIM8_CCR2 + 0x38 + 16 + 0x00000000 + 0x0000FFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM8_CCR3 + TIM8_CCR3 + 0x3c + 16 + 0x00000000 + 0x0000FFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM8_CCR4 + TIM8_CCR4 + 0x40 + 16 + 0x00000000 + 0x0000FFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM8_BDTR + TIM8_BDTR + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup +This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. +DTG[7:5] = 0xx => DT = DTG[7:0] x tDTG with tDTG = tDTS. +DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x tDTG with tDTG = 2 x tDTS. +DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 8 x tDTS. +DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x tDTG with tDTG = 16 x tDTS. +Example if tDTS = 125 ns (8 MHz), dead-time possible values are: +0 to 15875 ns by 125 ns steps, +16 μs to 31750 ns  by 250 ns steps, +32 μs to 63 μs by 1 μs steps, +64 μs to 126 μs by 2 μs steps +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per ). +Note: The BKIN2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM8_DCR + TIM8_DCR + 0x48 + 16 + 0x00000000 + 0x0000FFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM8_DMAR + TIM8_DMAR + 0x4c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM8_CCMR3 + TIM8_CCMR3 + TIM8 capture/compare mode register 3 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M1 + Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M1 + Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M2 + Output compare 5 mode +Refer to OC1M description. + 16 + 1 + read-write + + + OC6M2 + Output compare 6 mode +Refer to OC1M description. + 24 + 1 + read-write + + + + + TIM8_CCR5 + TIM8_CCR5 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM8_CCR6 + TIM8_CCR6 + 0x5c + 16 + 0x00000000 + 0x0000FFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM8_AF1 + TIM8_AF1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKDF1BK2E + BRK dfsdm1_break[2] enable +This bit enables the dfsdm1_break[2] for the timer’s BRK input. dfsdm1_break[2] output is 'ORed’ with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + dfsdm1_break[2] input disabled + 0x0 + + + B_0x1 + dfsdm1_break[2] input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR input is connected to I/O + 0x0 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + ADC2 AWD1 + 0x6 + + + B_0x7 + ADC2 AWD2 + 0x7 + + + B_0x8 + ADC2 AWD3 + 0x8 + + + + + + + TIM8_AF2 + TIM8_AF2 + 0x64 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2DF1BK3E + BRK2 dfsdm1_break[3] enable +This bit enables the dfsdm1_break[3] for the timer’s BRK2 input. dfsdm1_break[3] output is 'ORed’ with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + dfsdm1_break[3] input disabled + 0x0 + + + B_0x1 + dfsdm1_break[3] input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM8_TISEL + TIM8_TISEL + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM8_CH1 input + 0x0 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM8_CH2 input + 0x0 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM8_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM8_CH4 input + 0x0 + + + + + + + + + TIM12 + TIM register block + TIM12 + 0x4C007000 + + 0x0 + 0x400 + registers + + + TIM12 + TIM12 gloabl interrupt + 104 + + + + TIM12_CR1 + TIM12_CR1 + TIM12 control register 1 + 0x0 + 16 + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable +CEN is cleared automatically in one-pulse mode, when an update event occurs. +Note: External clock and gated mode can work only if the CEN bit has been previously set by +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable update event (UEV) generation. +Counter overflow +Setting the UG bit +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. An UEV is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow generates an update interrupt if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped on the update event + 0x0 + + + B_0x1 + Counter stops counting on the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), + 8 + 2 + read-write + + + B_0x0 + tDTS = tCK_INT + 0x0 + + + B_0x1 + tDTS = 2 × tCK_INT + 0x1 + + + B_0x2 + tDTS = 4 × tCK_INT + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM12_CR2 + TIM12_CR2 + TIM12 control register 2 + 0x4 + 16 + 0x00000000 + 0x0000FFFF + + + MMS + Master mode selection +These bits allow to select the information to be sent in master mode to slave timers for +synchronization (TRGO). The combination is as follows: + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO). + 0x5 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIM12_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIM12_CH1, CH2 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + + + TIM12_SMCR + TIM12_SMCR + TIM12 slave mode control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Other codes: reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + B_0x8 + Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. + 0x8 + + + + + TS1 + Trigger selection +This TS[4:0] bitfield selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on the meaning of ITRx for each timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful in order to synchronize several timers on a single external event. + 0x1 + + + + + SMS2 + Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Other codes: reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1’ then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + B_0x8 + Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. + 0x8 + + + + + TS2 + Trigger selection +This TS[4:0] bitfield selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for more details on the meaning of ITRx for each timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + + + + + TIM12_DIER + TIM12_DIER + TIM12 Interrupt enable register + 0xc + 16 + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + + + TIM12_SR + TIM12_SR + TIM12 status register + 0x10 + 16 + 0x00000000 + 0x0000FFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow and if UDIS=’0’ in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +refer to CC1IF description + 2 + 1 + read-write + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag +refer to CC1OF description + 10 + 1 + read-write + + + + + TIM12_EGR + TIM12_EGR + TIM12 event generation register + 0x14 + 16 + 0x00000000 + 0x0000FFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. + 0x1 + + + + + CC1G + Capture/compare 1 generation +This bit is set by software to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +the CC1IF flag is set, the corresponding interrupt is sent if enabled. +If channel CC1 is configured as input: +The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation +refer to CC1G description + 2 + 1 + write-only + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled + 0x1 + + + + + + + TIM12_CCMR1_Output + TIM12_CCMR1_Output + TIM12 capture/compare mode register 1 [alternate] + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bitfield defines the direction of the channel (input/output) as well as the used input. +Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable +Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event + 0x1 + + + + + OC1M1 + Output compare 1 mode (refer to bit 16 for OC1M[3]) +These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas the active level of OC1 depends on the CC1P. +Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high + 0x5 + + + B_0x6 + PWM mode 1 - channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive + 0x6 + + + B_0x7 + PWM mode 2 - channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active + 0x7 + + + B_0x8 + Retrigerrable OPM mode 1 - The channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. + 0x8 + + + B_0x9 + Retrigerrable OPM mode 2 - The channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. + 0x9 + + + B_0xC + Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. + 0xC + + + B_0xD + Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. + 0xD + + + + + CC2S + Capture/Compare 2 selection +This bitfield defines the direction of the channel (input/output) as well as the used input. +Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M1 + Output compare 2 mode +Refer to OC1M[3:0] for bit description. + 12 + 3 + read-write + + + OC1M2 + Output compare 1 mode (refer to bit 16 for OC1M[3]) +These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas the active level of OC1 depends on the CC1P. +Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high + 0x5 + + + B_0x6 + PWM mode 1 - channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive + 0x6 + + + B_0x7 + PWM mode 2 - channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active + 0x7 + + + B_0x8 + Retrigerrable OPM mode 1 - The channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. + 0x8 + + + B_0x9 + Retrigerrable OPM mode 2 - The channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. + 0x9 + + + B_0xC + Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. + 0xC + + + B_0xD + Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. + 0xD + + + + + OC2M2 + Output compare 2 mode +Refer to OC1M[3:0] for bit description. + 24 + 1 + read-write + + + + + TIM12_CCMR1_Input + TIM12_CCMR1_Input + TIM12 capture/compare mode register 1 [alternate] + TIM12_CCMR1_Output + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bitfield defines the direction of the channel (input/output) as well as the used input. +Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). +The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection +This bitfield defines the direction of the channel (input/output) as well as the used input. +Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM12_CCER + TIM12_CCER + TIM12 capture/compare enable register + 0x20 + 16 + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output Polarity +CC1 channel configured as output: CC1NP must be kept cleared +CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity (refer to CC1P description). + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity +Refer to CC1NP description + 7 + 1 + read-write + + + + + TIM12_CNT + TIM12_CNT + TIM12 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit in the TIMx_ISR register. + 31 + 1 + read-write + + + + + TIM12_PSC + TIM12_PSC + TIM12 prescaler + 0x28 + 16 + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +PSC contains the value to be loaded into the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). + 0 + 16 + read-write + + + + + TIM12_ARR + TIM12_ARR + TIM12 auto-reload register + 0x2c + 16 + 0x0000FFFF + 0x0000FFFF + + + ARR + Auto-reload value +ARR is the value to be loaded into the actual auto-reload register. +Refer to the for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM12_CCR1 + TIM12_CCR1 + TIM12 capture/compare register 1 + 0x34 + 16 + 0x00000000 + 0x0000FFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output. +If channel CC1is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + TIM12_CCR2 + TIM12_CCR2 + TIM12 capture/compare register 2 + 0x38 + 16 + 0x00000000 + 0x0000FFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output. +If channel CC2 is configured as input: +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + TIM12_TISEL + TIM12_TISEL + TIM12 timer input selection register + 0x68 + 16 + 0x00000000 + 0x0000FFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Other: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM12_CH1 input + 0x0 + + + B_0x1 + hsi_cal_ck + 0x1 + + + B_0x2 + csi_cal_ck + 0x2 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Other: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM12_CH2 input + 0x0 + + + + + + + + + TIM13 + TIM register block + TIM12 + 0x4C008000 + + 0x0 + 0x400 + registers + + + TIM13 + TIM13 global interrupt + 111 + + + + TIM13_CR1 + TIM13_CR1 + TIM13 control register 1 + 0x0 + 16 + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable +Note: External clock and gated mode can work only if the CEN bit has been previously set by +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. +Counter overflow +Setting the UG bit. +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. An UEV is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the update interrupt (UEV) sources. +Counter overflow +Setting the UG bit + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an UEV if enabled: + 0x0 + + + B_0x1 + Only counter overflow generates an UEV if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped on the update event + 0x0 + + + B_0x1 + Counter stops counting on the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), + 8 + 2 + read-write + + + B_0x0 + tDTS = tCK_INT + 0x0 + + + B_0x1 + tDTS = 2 × tCK_INT + 0x1 + + + B_0x2 + tDTS = 4 × tCK_INT + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM13_DIER + TIM13_DIER + TIM13 Interrupt enable register + 0xc + 16 + 0x00000000 + 0x0000FFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + + + TIM13_SR + TIM13_SR + TIM13 status register + 0x10 + 16 + 0x00000000 + 0x0000FFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow and if UDIS=’0’ in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM13_EGR + TIM13_EGR + TIM13 event generation register + 0x14 + 16 + 0x00000000 + 0x0000FFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. + 0x1 + + + + + CC1G + Capture/compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + + + TIM13_CCMR1_Output + TIM13_CCMR1_Output + TIM13 capture/compare mode register 1 [alternate] + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + + + OC1FE + Output compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable +Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output compare 1 mode (refer to bit 16 for OC1M[3]) +These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. +Others: Reserved +Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active + 0x7 + + + + + OC1M2 + Output compare 1 mode (refer to bit 16 for OC1M[3]) +These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. +Others: Reserved +Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + B_0x0 + Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active + 0x7 + + + + + + + TIM13_CCMR1_Input + TIM13_CCMR1_Input + TIM13 capture/compare mode register 1 [alternate] + TIM13_CCMR1_Output + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). +The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=fCK_INT, N=2 + 0x1 + + + B_0x2 + fSAMPLING=fCK_INT, N=4 + 0x2 + + + B_0x3 + fSAMPLING=fCK_INT, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + + + TIM13_CCER + TIM13_CCER + TIM13 capture/compare enable register + 0x20 + 16 + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output Polarity. +CC1 channel configured as output: CC1NP must be kept cleared. +CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). + 3 + 1 + read-write + + + + + TIM13_CNT + TIM13_CNT + TIM13 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit in the TIMx_ISR register. + 31 + 1 + read-write + + + + + TIM13_PSC + TIM13_PSC + TIM13 prescaler + 0x28 + 16 + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). + 0 + 16 + read-write + + + + + TIM13_ARR + TIM13_ARR + TIM13 auto-reload register + 0x2c + 16 + 0x0000FFFF + 0x0000FFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM13_CCR1 + TIM13_CCR1 + TIM13 capture/compare register 1 + 0x34 + 16 + 0x00000000 + 0x0000FFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + TIM13_TISEL + TIM13_TISEL + TIM13 timer input selection register + 0x68 + 16 + 0x00000000 + 0x0000FFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Other: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM13_CH1 input + 0x0 + + + + + + + + + TIM14 + 0x4C009000 + + TIM14 + TIM14 global interrupt + 112 + + + + TIM15 + TIM15 + TIMER + 0x4C00A000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 101 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 0x10 + read-write + 0x0000 + + + CEN + CEN + 0 + 1 + read-write + + + UDIS + UDIS + 1 + 1 + read-write + + + URS + URS + 2 + 1 + read-write + + + OPM + OPM + 3 + 1 + read-write + + + ARPE + ARPE + 7 + 1 + read-write + + + CKD + CKD + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP + 11 + 1 + read-write + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 0x10 + read-write + 0x0000 + + + CCPC + CCPC + 0 + 1 + read-write + + + CCUS + CCUS + 2 + 1 + read-write + + + CCDS + CCDS + 3 + 1 + read-write + + + MMS + MMS + 4 + 3 + read-write + + + TI1S + TI1S + 7 + 1 + read-write + + + OIS1 + OIS1 + 8 + 1 + read-write + + + OIS1N + OIS1N + 9 + 1 + read-write + + + OIS2 + OIS2 + 10 + 1 + read-write + + + + + TIMx_SMCR + TIMx_SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable + register + 0x0C + 0x10 + read-write + 0x0000 + + + UIE + UIE + 0 + 1 + read-write + + + CC1IE + CC1IE + 1 + 1 + read-write + + + CC2IE + CC2IE + 2 + 1 + read-write + + + COMIE + COMIE + 5 + 1 + read-write + + + TIE + TIE + 6 + 1 + read-write + + + BIE + BIE + 7 + 1 + read-write + + + UDE + UDE + 8 + 1 + read-write + + + CC1DE + CC1DE + 9 + 1 + read-write + + + CC2DE + CC2DE + 10 + 1 + read-write + + + COMDE + COMDE + 13 + 1 + read-write + + + TDE + TDE + 14 + 1 + read-write + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 0x10 + read-write + 0x0000 + + + UIF + UIF + 0 + 1 + read-write + + + CC1IF + CC1IF + 1 + 1 + read-write + + + CC2IF + CC2IF + 2 + 1 + read-write + + + COMIF + COMIF + 5 + 1 + read-write + + + TIF + TIF + 6 + 1 + read-write + + + BIF + BIF + 7 + 1 + read-write + + + CC1OF + CC1OF + 9 + 1 + read-write + + + CC2OF + CC2OF + 10 + 1 + read-write + + + + + TIMx_EGR + TIMx_EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + BG + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + COMG + 5 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + TIMx_CCMR1_Output + TIMx_CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + TIMx_CCMR1_Input + TIMx_CCMR1_Input + capture/compare mode register 1 (input + mode) + TIMx_CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable + register + 0x20 + 0x10 + read-write + 0x0000 + + + CC1E + CC1E + 0 + 1 + read-write + + + CC1P + CC1P + 1 + 1 + read-write + + + CC1NE + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP + 3 + 1 + read-write + + + CC2E + CC2E + 4 + 1 + read-write + + + CC2P + CC2P + 5 + 1 + read-write + + + CC2NP + CC2NP + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + PSC + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 0x10 + read-write + 0xFFFF + + + ARR + ARR + 0 + 16 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter + register + 0x30 + 0x10 + read-write + 0x0000 + + + REP + REP + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register + 1 + 0x34 + 0x10 + read-write + 0x0000 + + + CCR1 + CCR1 + 0 + 16 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register + 2 + 0x38 + 0x10 + read-write + 0x0000 + + + CCR2 + CCR2 + 0 + 16 + read-write + + + + + TIMx_BDTR + TIMx_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, + BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, + OSSR and DTG[7:0] can be write-locked depending on the + LOCK configuration, it can be necessary to configure all + of them during the first write access to the TIMx_BDTR + register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + read-write + + + LOCK + LOCK + 8 + 2 + read-write + + + OSSI + OSSI + 10 + 1 + read-write + + + OSSR + OSSR + 11 + 1 + read-write + + + BKE + BKE + 12 + 1 + read-write + + + BKP + BKP + 13 + 1 + read-write + + + AOE + AOE + 14 + 1 + read-write + + + MOE + MOE + 15 + 1 + read-write + + + BKF + BKF + 16 + 4 + read-write + + + BKDSRM + BKDSRM + 26 + 1 + read-write + + + BKBID + BKBID + 28 + 1 + read-write + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x48 + 0x10 + read-write + 0x0000 + + + DBA + DBA + 0 + 5 + read-write + + + DBL + DBL + 8 + 5 + read-write + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full + transfer + 0x4C + 0x10 + read-write + 0x0000 + + + DMAB + DMAB + 0 + 16 + read-write + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + read-write + + + BKDF1BK0E + BKDF1BK0E + 8 + 1 + read-write + + + BKINP + BKINP + 9 + 1 + read-write + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + read-write + + + TI2SEL + TI2SEL + 8 + 4 + read-write + + + + + + + TIM16 + TIM16 + TIMER + 0x4C00B000 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 102 + + + + TIMx_CR1 + TIMx_CR1 + TIM16/TIM17 control register 1 + 0x00 + 0x10 + read-write + 0x0000 + + + CEN + CEN + 0 + 1 + read-write + + + UDIS + UDIS + 1 + 1 + read-write + + + URS + URS + 2 + 1 + read-write + + + OPM + OPM + 3 + 1 + read-write + + + ARPE + ARPE + 7 + 1 + read-write + + + CKD + CKD + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP + 11 + 1 + read-write + + + + + TIMx_CR2 + TIMx_CR2 + TIM16/TIM17 control register 2 + 0x04 + 0x10 + read-write + 0x0000 + + + CCPC + CCPC + 0 + 1 + read-write + + + CCUS + CCUS + 2 + 1 + read-write + + + CCDS + CCDS + 3 + 1 + read-write + + + OIS1 + OIS1 + 8 + 1 + read-write + + + OIS1N + OIS1N + 9 + 1 + read-write + + + + + TIMx_DIER + TIMx_DIER + TIM16/TIM17 DMA/interrupt enable + register + 0x0C + 0x10 + read-write + 0x0000 + + + UIE + UIE + 0 + 1 + read-write + + + CC1IE + CC1IE + 1 + 1 + read-write + + + COMIE + COMIE + 5 + 1 + read-write + + + BIE + BIE + 7 + 1 + read-write + + + UDE + UDE + 8 + 1 + read-write + + + CC1DE + CC1DE + 9 + 1 + read-write + + + COMDE + COMDE + 13 + 1 + read-write + + + + + TIMx_SR + TIMx_SR + TIM16/TIM17 status register + 0x10 + 0x10 + read-write + 0x0000 + + + UIF + UIF + 0 + 1 + read-write + + + CC1IF + CC1IF + 1 + 1 + read-write + + + COMIF + COMIF + 5 + 1 + read-write + + + BIF + BIF + 7 + 1 + read-write + + + CC1OF + CC1OF + 9 + 1 + read-write + + + + + TIMx_EGR + TIMx_EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + TIMx_CCMR1_Output + TIMx_CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + OC1M2 + Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 16 + 1 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + + + + + TIMx_CCMR1_Input + TIMx_CCMR1_Input + capture/compare mode register 1 (input + mode) + TIMx_CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + + + TIMx_CCER + TIMx_CCER + TIM16/TIM17 capture/compare enable + register + 0x20 + 0x10 + read-write + 0x0000 + + + CC1E + CC1E + 0 + 1 + read-write + + + CC1P + CC1P + 1 + 1 + read-write + + + CC1NE + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP + 3 + 1 + read-write + + + + + TIMx_CNT + TIMx_CNT + TIM16/TIM17 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIMx_PSC + TIMx_PSC + TIM16/TIM17 prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + PSC + 0 + 16 + read-write + + + + + TIMx_ARR + TIMx_ARR + TIM16/TIM17 auto-reload + register + 0x2C + 0x10 + read-write + 0xFFFF + + + ARR + ARR + 0 + 16 + read-write + + + + + TIMx_RCR + TIMx_RCR + TIM16/TIM17 repetition counter + register + 0x30 + 0x10 + read-write + 0x0000 + + + REP + REP + 0 + 8 + read-write + + + + + TIMx_CCR1 + TIMx_CCR1 + TIM16/TIM17 capture/compare register + 1 + 0x34 + 0x10 + read-write + 0x0000 + + + CCR1 + CCR1 + 0 + 16 + read-write + + + + + TIMx_BDTR + TIMx_BDTR + As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, + BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked + depending on the LOCK configuration, it may be necessary + to configure all of them during the first write access to + the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + read-write + + + LOCK + LOCK + 8 + 2 + read-write + + + OSSI + OSSI + 10 + 1 + read-write + + + OSSR + OSSR + 11 + 1 + read-write + + + BKE + BKE + 12 + 1 + read-write + + + BKP + BKP + 13 + 1 + read-write + + + AOE + AOE + 14 + 1 + read-write + + + MOE + MOE + 15 + 1 + read-write + + + BKF + BKF + 16 + 4 + read-write + + + BKDSRM + BKDSRM + 26 + 1 + read-write + + + BKBID + BKBID + 28 + 1 + read-write + + + + + TIMx_DCR + TIMx_DCR + TIM16/TIM17 DMA control + register + 0x48 + 0x10 + read-write + 0x0000 + + + DBA + DBA + 0 + 5 + read-write + + + DBL + DBL + 8 + 5 + read-write + + + + + TIMx_DMAR + TIMx_DMAR + TIM16/TIM17 DMA address for full + transfer + 0x4C + 0x10 + read-write + 0x0000 + + + DMAB + DMAB + 0 + 16 + read-write + + + + + TIMx_AF1 + TIM17_AF1 + TIM17 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + read-write + + + BKDF1BK2E + BKDF1BK2E + 8 + 1 + read-write + + + BKINP + BKINP + 9 + 1 + read-write + + + + + TIMx_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + read-write + + + + + + + TIM17 + 0x4C00C000 + + TIM17 + TIM17 global interrupt + 103 + + + + + + TSC + TSC + TSC + 0x5000B000 + + 0x0 + 0x400 + registers + + + TSC + Touch sensor global interrupt + 0 + + + + TSC_CR + TSC_CR + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSCE + Touch sensing controller enable +This bit is set and cleared by software to enable/disable the touch sensing controller. +Note: When the touch sensing controller is disabled, TSC registers settings have no effect. + 0 + 1 + read-write + + + B_0x0 + Touch sensing controller disabled + 0x0 + + + B_0x1 + Touch sensing controller enabled + 0x1 + + + + + START + Start a new acquisition +This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. + 1 + 1 + read-write + + + B_0x0 + Acquisition not started + 0x0 + + + B_0x1 + Start a new acquisition + 0x1 + + + + + AM + Acquisition mode +This bit is set and cleared by software to select the acquisition mode. +Note: This bit must not be modified when an acquisition is ongoing. + 2 + 1 + read-write + + + B_0x0 + Normal acquisition mode (acquisition starts as soon as START bit is set) + 0x0 + + + B_0x1 + Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) + 0x1 + + + + + SYNCPOL + Synchronization pin polarity +This bit is set and cleared by software to select the polarity of the synchronization input pin. + 3 + 1 + read-write + + + B_0x0 + Falling edge only + 0x0 + + + B_0x1 + Rising edge and high level + 0x1 + + + + + IODEF + I/O Default mode +This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). +Note: This bit must not be modified when an acquisition is ongoing. + 4 + 1 + read-write + + + B_0x0 + I/Os are forced to output push-pull low + 0x0 + + + B_0x1 + I/Os are in input floating + 0x1 + + + + + MCV + Max count value +These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. +Note: These bits must not be modified when an acquisition is ongoing. + 5 + 3 + read-write + + + B_0x0 + 255 + 0x0 + + + B_0x1 + 511 + 0x1 + + + B_0x2 + 1023 + 0x2 + + + B_0x3 + 2047 + 0x3 + + + B_0x4 + 4095 + 0x4 + + + B_0x5 + 8191 + 0x5 + + + B_0x6 + 16383 + 0x6 + + + + + PGPSC + Pulse generator prescaler +These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the acquisition sequence for details. + 12 + 3 + read-write + + + B_0x0 + fHCLK + 0x0 + + + B_0x1 + fHCLK /2 + 0x1 + + + B_0x2 + fHCLK /4 + 0x2 + + + B_0x3 + fHCLK /8 + 0x3 + + + B_0x4 + fHCLK /16 + 0x4 + + + B_0x5 + fHCLK /32 + 0x5 + + + B_0x6 + fHCLK /64 + 0x6 + + + B_0x7 + fHCLK /128 + 0x7 + + + + + SSPSC + Spread spectrum prescaler +This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). +Note: This bit must not be modified when an acquisition is ongoing. + 15 + 1 + read-write + + + B_0x0 + fHCLK + 0x0 + + + B_0x1 + fHCLK /2 + 0x1 + + + + + SSE + Spread spectrum enable +This bit is set and cleared by software to enable/disable the spread spectrum feature. +Note: This bit must not be modified when an acquisition is ongoing. + 16 + 1 + read-write + + + B_0x0 + Spread spectrum disabled + 0x0 + + + B_0x1 + Spread spectrum enabled + 0x1 + + + + + SSD + Spread spectrum deviation +These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. +... +Note: These bits must not be modified when an acquisition is ongoing. + 17 + 7 + read-write + + + B_0x0 + 1x tSSCLK + 0x0 + + + B_0x1 + 2x tSSCLK + 0x1 + + + B_0x7F + 128x tSSCLK + 0x7F + + + + + CTPL + Charge transfer pulse low +These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from CX to CS). +... +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the acquisition sequence for details. + 24 + 4 + read-write + + + B_0x0 + 1x tPGCLK + 0x0 + + + B_0x1 + 2x tPGCLK + 0x1 + + + B_0xF + 16x tPGCLK + 0xF + + + + + CTPH + Charge transfer pulse high +These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of CX). +... +Note: These bits must not be modified when an acquisition is ongoing. + 28 + 4 + read-write + + + B_0x0 + 1x tPGCLK + 0x0 + + + B_0x1 + 2x tPGCLK + 0x1 + + + B_0xF + 16x tPGCLK + 0xF + + + + + + + TSC_IER + TSC_IER + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIE + End of acquisition interrupt enable +This bit is set and cleared by software to enable/disable the end of acquisition interrupt. + 0 + 1 + read-write + + + B_0x0 + End of acquisition interrupt disabled + 0x0 + + + B_0x1 + End of acquisition interrupt enabled + 0x1 + + + + + MCEIE + Max count error interrupt enable +This bit is set and cleared by software to enable/disable the max count error interrupt. + 1 + 1 + read-write + + + B_0x0 + Max count error interrupt disabled + 0x0 + + + B_0x1 + Max count error interrupt enabled + 0x1 + + + + + + + TSC_ICR + TSC_ICR + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIC + End of acquisition interrupt clear +This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a '0’ has no effect. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding EOAF of the TSC_ISR register + 0x1 + + + + + MCEIC + Max count error interrupt clear +This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a '0’ has no effect. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding MCEF of the TSC_ISR register + 0x1 + + + + + + + TSC_ISR + TSC_ISR + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAF + End of acquisition flag +This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. + 0 + 1 + read-only + + + B_0x0 + Acquisition is ongoing or not started + 0x0 + + + B_0x1 + Acquisition is complete + 0x1 + + + + + MCEF + Max count error flag +This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. + 1 + 1 + read-only + + + B_0x0 + No max count error (MCE) detected + 0x0 + + + B_0x1 + Max count error (MCE) detected + 0x1 + + + + + + + TSC_IOHCR + TSC_IOHCR + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + G1_IO1 + 0 + 1 + read-write + + + G1_IO2 + 1 + 1 + read-write + + + G1_IO3 + 2 + 1 + read-write + + + G1_IO4 + 3 + 1 + read-write + + + G2_IO1 + 4 + 1 + read-write + + + G2_IO2 + 5 + 1 + read-write + + + G2_IO3 + 6 + 1 + read-write + + + G2_IO4 + 7 + 1 + read-write + + + G3_IO1 + 8 + 1 + read-write + + + G3_IO2 + 9 + 1 + read-write + + + G3_IO3 + 10 + 1 + read-write + + + G3_IO4 + 11 + 1 + read-write + + + G4_IO1 + 12 + 1 + read-write + + + G4_IO2 + 13 + 1 + read-write + + + G4_IO3 + 14 + 1 + read-write + + + G4_IO4 + 15 + 1 + read-write + + + G5_IO1 + 16 + 1 + read-write + + + G5_IO2 + 17 + 1 + read-write + + + G5_IO3 + 18 + 1 + read-write + + + G5_IO4 + 19 + 1 + read-write + + + + + TSC_IOASCR + TSC_IOASCR + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + 0 + 1 + read-write + + + G1_IO2 + 1 + 1 + read-write + + + G1_IO3 + 2 + 1 + read-write + + + G1_IO4 + 3 + 1 + read-write + + + G2_IO1 + 4 + 1 + read-write + + + G2_IO2 + 5 + 1 + read-write + + + G2_IO3 + 6 + 1 + read-write + + + G2_IO4 + 7 + 1 + read-write + + + G3_IO1 + 8 + 1 + read-write + + + G3_IO2 + 9 + 1 + read-write + + + G3_IO3 + 10 + 1 + read-write + + + G3_IO4 + 11 + 1 + read-write + + + G4_IO1 + 12 + 1 + read-write + + + G4_IO2 + 13 + 1 + read-write + + + G4_IO3 + 14 + 1 + read-write + + + G4_IO4 + 15 + 1 + read-write + + + G5_IO1 + 16 + 1 + read-write + + + G5_IO2 + 17 + 1 + read-write + + + G5_IO3 + 18 + 1 + read-write + + + G5_IO4 + 19 + 1 + read-write + + + + + TSC_IOCCR + TSC_IOCCR + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + 0 + 1 + read-write + + + G1_IO2 + 1 + 1 + read-write + + + G1_IO3 + 2 + 1 + read-write + + + G1_IO4 + 3 + 1 + read-write + + + G2_IO1 + 4 + 1 + read-write + + + G2_IO2 + 5 + 1 + read-write + + + G2_IO3 + 6 + 1 + read-write + + + G2_IO4 + 7 + 1 + read-write + + + G3_IO1 + 8 + 1 + read-write + + + G3_IO2 + 9 + 1 + read-write + + + G3_IO3 + 10 + 1 + read-write + + + G3_IO4 + 11 + 1 + read-write + + + G4_IO1 + 12 + 1 + read-write + + + G4_IO2 + 13 + 1 + read-write + + + G4_IO3 + 14 + 1 + read-write + + + G4_IO4 + 15 + 1 + read-write + + + G5_IO1 + 16 + 1 + read-write + + + G5_IO2 + 17 + 1 + read-write + + + G5_IO3 + 18 + 1 + read-write + + + G5_IO4 + 19 + 1 + read-write + + + + + TSC_IOGCSR + TSC_IOGCSR + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1E + 0 + 1 + read-write + + + G2E + 1 + 1 + read-write + + + G3E + 2 + 1 + read-write + + + G4E + 3 + 1 + read-write + + + G5E + 4 + 1 + read-write + + + G1S + 16 + 1 + read-only + + + G2S + 17 + 1 + read-only + + + G3S + 18 + 1 + read-only + + + G4S + 19 + 1 + read-only + + + G5S + 20 + 1 + read-only + + + + + TSC_IOG1CR + TSC_IOG1CR + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 14 + read-only + + + + + TSC_IOG2CR + TSC_IOG2CR + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 14 + read-only + + + + + TSC_IOG3CR + TSC_IOG3CR + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 14 + read-only + + + + + TSC_IOG4CR + TSC_IOG4CR + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 14 + read-only + + + + + TSC_HWCFGR + TSC_HWCFGR + 0x3f0 + 0x20 + 0x00000025 + 0xFFFFFFFF + + + CFG1 + TSC hardware configuration 1 +These bits return the TSP CFG1[3:0] configuration. +CFG1[3:0] = group_size = 0x5 (group size). + 0 + 4 + read-only + + + CFG2 + TSC hardware configuration 2 +These bits return the TSP CFG2[3:0] configuration. +CFG2[3:0] = dt_duration = 0x2 (dead time duration). + 4 + 4 + read-only + + + + + TSC_VERR + TSC_VERR + 0x3f4 + 0x20 + 0x00000012 + 0xFFFFFFFF + + + MINREV + Minor revision +These bits return the TSC minor revision. +MINREV[3:0] = 0x2 + 0 + 4 + read-only + + + MAJREV + Major revision +These bits return the TSC major revision. +MAJREV[3:0] = 0x1 + 4 + 4 + read-only + + + + + TSC_IDR + TSC_IDR + 0x3f8 + 0x20 + 0x00110041 + 0xFFFFFFFF + + + ID + TSC identifier +These bits return the TSC identifier. +ID[31:0] = 0x00110041 + 0 + 32 + read-only + + + + + TSC_SIDR + TSC_SIDR + 0x3fc + 0x20 + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + TSC size identification +These bits return the size of the memory region allocated to the TSC registers. +SID[31:0] = 0xA3C5DD01 + 0 + 32 + read-only + + + + + + + TZC + TZC + TZC + 0x5C006000 + + 0x0 + 0x1000 + registers + + + TZC_IT + TrustZone DDR address space controller + 4 + + + + TZC_BUILD_CONFIG + TZC_BUILD_CONFIG + TZC configuration register + 0x0 + 0x20 + 0x00001F08 + 0xFFFFFFFF + + + NO_OF_REGIONS + Number fo regions +Others: Reserved + 0 + 5 + read-only + + + B_0x8 + 9 regions + 0x8 + + + + + ADDRESS_WIDTH + Address width +Others: Reserved + 8 + 6 + read-only + + + B_0x1F + 32-bit address width + 0x1F + + + + + NO_OF_FILTERS + Number of filters + 24 + 1 + read-only + + + B_0x0 + 1 filter + 0x0 + + + + + + + TZC_ACTION + TZC_ACTION + TZC action register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REACTION_VALUE + Permission failure reaction +Controls how TZC signals region permission failure. +2: set tzcint high and issue OKAY on the bus +3: set tzcint high and issue DECERR on the bus + 0 + 2 + read-write + + + B_0x0 + set tzcint low and issue OKAY on the bus + 0x0 + + + B_0x1 + set tzcint low and issue DECERR on the bus + 0x1 + + + + + + + TZC_GATE_KEEPER + TZC_GATE_KEEPER + TZC gate keeper register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPENREQ + Gate keeper open request for filter + 0 + 1 + read-write + + + B_0x0 + request filter to open + 0x0 + + + B_0x1 + request filter to close + 0x1 + + + + + OPENSTAT + Gate keeper status for filter + 16 + 1 + read-only + + + B_0x0 + filter is opened + 0x0 + + + B_0x1 + filter is closed + 0x1 + + + + + + + TZC_SPECULATION_CTRL + TZC_SPECULATION_CTRL + TZC speculation control register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + READSPEC_DISABLE + Read access speculation disable + 0 + 1 + read-write + + + B_0x0 + read access speculation enabled + 0x0 + + + B_0x1 + read access speculation disabled + 0x1 + + + + + WRITESPEC_DISABLE + Write access speculation disable + 1 + 1 + read-write + + + B_0x0 + write access speculation enabled + 0x0 + + + B_0x1 + write access speculation disabled + 0x1 + + + + + + + TZC_INT_STATUS + TZC_INT_STATUS + TZC interrupt status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + STATUS + Interrupt status for the filter. + 0 + 1 + read-only + + + B_0x0 + interrupt is not asserted + 0x0 + + + B_0x1 + interrupt asserted and waiting to be cleared + 0x1 + + + + + OVERRUN + Permission failure overrun +Two or more regions permission failures for the filter. + 8 + 1 + read-only + + + B_0x0 + interrupt is not asserted + 0x0 + + + B_0x1 + interrupt asserted and waiting to be cleared + 0x1 + + + + + OVERLAP + Overlap violation for each filter +Bit 17 is for filter 1, bit 16 is for filter 0. + 16 + 2 + read-only + + + B_0x0 + interrupt is not asserted + 0x0 + + + B_0x1 + interrupt asserted and waiting to be cleared + 0x1 + + + + + + + TZC_INT_CLEAR + TZC_INT_CLEAR + TZC interrupt clear register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CLEAR + Filter interrupt clear +Write “1” to clear interrupt for each filter. + 0 + 1 + write-only + + + + + TZC_FAIL_ADDRESS_LOW + TZC_FAIL_ADDRESS_LOW + TZC fail address low register x + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR_STATUS_LOW + Fail address low bits +Low 32 address bits of the first failed access permission check in the filter. + 0 + 32 + read-only + + + + + TZC_FAIL_CONTROL + TZC_FAIL_CONTROL + TZC fail control register x + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRIVILEGE + Privilege access failure + 20 + 1 + read-only + + + B_0x0 + Unprivileged access failure + 0x0 + + + B_0x1 + Privileged access failure + 0x1 + + + + + NON_SECURE + Non-secure access failure + 21 + 1 + read-only + + + B_0x0 + Secure access failure + 0x0 + + + B_0x1 + Non-secure access failure + 0x1 + + + + + DIRECTION + Access failure direction + 24 + 1 + read-only + + + B_0x0 + Read access failure + 0x0 + + + B_0x1 + Write access failure + 0x1 + + + + + + + TZC_FAIL_ID + TZC_FAIL_ID + TZC fail ID register x + 0x2c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ID + AXI fail ID +Return the AXI ID of the first fail. + 0 + 11 + read-only + + + + + TZC_REGION_BASE_LOW0 + TZC_REGION_BASE_LOW0 + TZC region 0 base address low register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + base address bits[31:12] for region 0 +Others: Reserved + 12 + 20 + read-only + + + B_0x0 + fixed value for region 0 + 0x0 + + + + + + + TZC_REGION_TOP_LOW0 + TZC_REGION_TOP_LOW0 + TZC region 0 top address low register + 0x108 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region 0 +Others: Reserved + 12 + 20 + read-only + + + B_0xFFFFF + fixed value for region 0 + 0xFFFFF + + + + + + + TZC_REGION_ATTRIBUTE0 + TZC_REGION_ATTRIBUTE0 + TZC region 0 attribute register + 0x110 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-only + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS0 + TZC_REGION_ID_ACCESS0 + TZC region 0 ID access register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW1 + TZC_REGION_BASE_LOW1 + TZC region 1 base address low register + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW1 + TZC_REGION_TOP_LOW1 + TZC regions 1 top address low register + 0x128 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE1 + TZC_REGION_ATTRIBUTE1 + TZC region 1 attribute register + 0x130 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS1 + TZC_REGION_ID_ACCESS1 + TZC region 1 ID access register + 0x134 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW2 + TZC_REGION_BASE_LOW2 + TZC region 2 base address low register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW2 + TZC_REGION_TOP_LOW2 + TZC regions 2 top address low register + 0x148 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE2 + TZC_REGION_ATTRIBUTE2 + TZC region 2 attribute register + 0x150 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS2 + TZC_REGION_ID_ACCESS2 + TZC region 2 ID access register + 0x154 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW3 + TZC_REGION_BASE_LOW3 + TZC region 3 base address low register + 0x160 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW3 + TZC_REGION_TOP_LOW3 + TZC regions 3 top address low register + 0x168 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE3 + TZC_REGION_ATTRIBUTE3 + TZC region 3 attribute register + 0x170 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS3 + TZC_REGION_ID_ACCESS3 + TZC region 3 ID access register + 0x174 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW4 + TZC_REGION_BASE_LOW4 + TZC region 4 base address low register + 0x180 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW4 + TZC_REGION_TOP_LOW4 + TZC regions 4 top address low register + 0x188 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE4 + TZC_REGION_ATTRIBUTE4 + TZC region 4 attribute register + 0x190 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS4 + TZC_REGION_ID_ACCESS4 + TZC region 4 ID access register + 0x194 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW5 + TZC_REGION_BASE_LOW5 + TZC region 5 base address low register + 0x1a0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW5 + TZC_REGION_TOP_LOW5 + TZC regions 5 top address low register + 0x1a8 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE5 + TZC_REGION_ATTRIBUTE5 + TZC region 5 attribute register + 0x1b0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS5 + TZC_REGION_ID_ACCESS5 + TZC region 5 ID access register + 0x1b4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW6 + TZC_REGION_BASE_LOW6 + TZC region 6 base address low register + 0x1c0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW6 + TZC_REGION_TOP_LOW6 + TZC regions 6 top address low register + 0x1c8 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE6 + TZC_REGION_ATTRIBUTE6 + TZC region 6 attribute register + 0x1d0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS6 + TZC_REGION_ID_ACCESS6 + TZC region 6 ID access register + 0x1d4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW7 + TZC_REGION_BASE_LOW7 + TZC region 7 base address low register + 0x1e0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW7 + TZC_REGION_TOP_LOW7 + TZC regions 7 top address low register + 0x1e8 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE7 + TZC_REGION_ATTRIBUTE7 + TZC region 7 attribute register + 0x1f0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + B_0x0 + secure read to the region are not allowed + 0x0 + + + B_0x1 + permit secure read into the region + 0x1 + + + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS7 + TZC_REGION_ID_ACCESS7 + TZC region 7 ID access register + 0x1f4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_REGION_BASE_LOW8 + TZC_REGION_BASE_LOW8 + TZC region 8 base address low register + 0x200 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BASE_ADDRESS_LOW + Base address bits[31:12] for region x + 12 + 20 + read-write + + + + + TZC_REGION_TOP_LOW8 + TZC_REGION_TOP_LOW8 + TZC regions 8 top address low register + 0x208 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + Top address bits [31:12] of region x + 12 + 20 + read-write + + + + + TZC_REGION_ATTRIBUTE8 + TZC_REGION_ATTRIBUTE8 + TZC region 8 attribute register + 0x210 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FILTER_EN + Region enable for the filter + 0 + 1 + read-write + + + B_0x0 + disable filter for the region + 0x0 + + + B_0x1 + enable filter for the region + 0x1 + + + + + S_RD_EN + Secure global read enable + 30 + 1 + read-write + + + S_WR_EN + Secure global write enable + 31 + 1 + read-write + + + B_0x0 + secure write to the region are not allowed + 0x0 + + + B_0x1 + permit secure write into the region + 0x1 + + + + + + + TZC_REGION_ID_ACCESS8 + TZC_REGION_ID_ACCESS8 + TZC region 8 ID access register + 0x214 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NSAID_RD_EN + Region read enable for each NSAID +Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15. + 0 + 16 + read-write + + + B_0x0 + forbids read non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits read non-secure to the region for this NSAID + 0x1 + + + + + NSAID_WR_EN + Region write enable for each NSAID +Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15 + 16 + 16 + read-write + + + B_0x0 + forbids write non-secure to the region for this NSAID + 0x0 + + + B_0x1 + permits write non-secure to the region for this NSAID + 0x1 + + + + + + + TZC_PID4 + TZC_PID4 + TZC peripheral ID 4 register + 0xfd0 + 0x20 + 0x00000004 + 0xFFFFFFFF + + + PER_ID_4 + Peripheral ID 4 + 0 + 8 + read-only + + + + + TZC_PID5 + TZC_PID5 + TZC peripheral ID 5 register + 0xfd4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PER_ID_5 + Peripheral ID 5 + 0 + 8 + read-only + + + + + TZC_PID6 + TZC_PID6 + TZC peripheral ID 6 register + 0xfd8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PER_ID_6 + Peripheral ID 6 + 0 + 8 + read-only + + + + + TZC_PID7 + TZC_PID7 + TZC peripheral ID 7 register + 0xfdc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PER_ID_7 + Peripheral ID 7 + 0 + 8 + read-only + + + + + TZC_PID0 + TZC_PID0 + TZC peripheral ID 0 register + 0xfe0 + 0x20 + 0x00000060 + 0xFFFFFFFF + + + PER_ID_0 + Peripheral ID 0 + 0 + 8 + read-only + + + + + TZC_PID1 + TZC_PID1 + TZC peripheral ID 1 register + 0xfe4 + 0x20 + 0x000000B4 + 0xFFFFFFFF + + + PER_ID_1 + Peripheral ID 1 + 0 + 8 + read-only + + + + + TZC_PID2 + TZC_PID2 + TZC peripheral ID 2 register + 0xfe8 + 0x20 + 0x0000002B + 0xFFFFFFFF + + + PER_ID_2 + Peripheral ID 2 + 0 + 8 + read-only + + + + + TZC_PID3 + TZC_PID3 + TZC peripheral ID 3 register + 0xfec + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PER_ID_3 + Peripheral ID 3 + 0 + 8 + read-only + + + + + TZC_CID0 + TZC_CID0 + TZC component ID 0 register + 0xff0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + COMP_ID_0 + Component ID 0 + 0 + 8 + read-only + + + + + TZC_CID1 + TZC_CID1 + TZC component ID 1 register + 0xff4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + COMP_ID_1 + Component ID 0 + 0 + 8 + read-only + + + + + TZC_CID2 + TZC_CID2 + TZC component ID 2 register + 0xff8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + COMP_ID_2 + Component ID 2 + 0 + 8 + read-only + + + + + TZC_CID3 + TZC_CID3 + TZC component ID 3 register + 0xffc + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + COMP_ID_3 + Component ID 3 + 0 + 8 + read-only + + + + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x4C000000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 38 + + + + CR1_FIFO_enabled + CR1_FIFO_enabled + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR1_FIFO_disabled + CR1_FIFO_disabled + Control register 1 + CR1_FIFO_enabled + 0x0 + 0x20 + read-write + 0x0000 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD + Auto baud rate mode + 21 + 2 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + When the DSI_NSS bit is set, the NSS pin input will be ignored + 3 + 1 + + + SLVEN + Synchronous Slave mode enable + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold configuration + 25 + 3 + + + TCBGTIE + Tr Complete before guard time, interrupt enable + 24 + 1 + + + TXFTIE + threshold interrupt enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR_4_15 + BRR_4_15 + 4 + 12 + + + BRR_0_3 + BRR_0_3 + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR_FIFO_enabled + ISR_FIFO_enabled + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ISR_FIFO_disabled + ISR_FIFO_disabled + USART interrupt and status register + ISR_FIFO_enabled + 0x1C + 0x20 + read-only + 0x00C0 + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + SPI slave underrun clear flag + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + Transmission complete before Guard time clear flag + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFIFO empty clear flag + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + HWCFGR2 + HWCFGR2 + USART Hardware Configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000014 + + + CFG1 + CFG1 + 0 + 4 + + + CFG2 + CFG2 + 4 + 4 + + + + + HWCFGR1 + HWCFGR1 + USART Hardware Configuration register 1 + 0x3F0 + 0x20 + read-only + 0x00000014 + + + CFG1 + CFG1 + 0 + 4 + + + CFG2 + CFG2 + 4 + 4 + + + CFG3 + CFG3 + 8 + 4 + + + CFG4 + CFG4 + 12 + 4 + + + CFG5 + CFG5 + 16 + 4 + + + CFG6 + CFG6 + 20 + 4 + + + CFG7 + CFG7 + 24 + 4 + + + CFG8 + CFG8 + 28 + 4 + + + + + VERR + VERR + EXTI IP Version register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + MINREV + Minor Revision number + 0 + 4 + + + MAJREV + Major Revision number + 4 + 4 + + + + + IPIDR + IPIDR + EXTI Identification register + 0x3F8 + 0x20 + read-only + 0x00130003 + + + IPID + IP Identification + 0 + 32 + + + + + SIDR + SIDR + EXTI Size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size Identification + 0 + 32 + + + + + + + USART2 + 0x4C001000 + + USART2 + USART2 global interrupt + 39 + + + + USART3 + 0x4000F000 + + USART3 + USART3 global interrupt + 40 + + + + USART4 + 0x40010000 + + USART4 + USART4 global interrupt + 53 + + + + USART5 + 0x40011000 + + USART5 + USART5 global interrupt + 54 + + + + USART6 + 0x44003000 + + USART6 + USART6 global interrupt + 72 + + + + USART7 + 0x40018000 + + USART7 + USART7 global interrupt + 83 + + + + USART8 + 0x40019000 + + USART8 + USART8 global interrupt + 84 + + + + USBPHYC + USBPHYC + USBPHYC + 0x5A006000 + + 0x0 + 0x1000 + registers + + + + USBPHYC_PLL + USBPHYC_PLL + USBPHYC PLL control register + 0x0 + 0x20 + 0xC0000000 + 0xFFFFFFFF + + + PLLNDIV + Loop division factor of PLL (integer part) + 0 + 7 + read-write + + + PLLODF + PLL output division factor + 7 + 3 + read-write + + + PLLFRACIN + PLL fractional input +PLLFRACIN is the fractional input of the PLL divider. + 10 + 16 + read-write + + + PLLEN + PLL enable +This bit enables the PLL. + 26 + 1 + read-write + + + B_0x0 + PLL disabled + 0x0 + + + B_0x1 + PLL enabled + 0x1 + + + + + PLLSTRB + PLL strobe +This bit allows to control an asynchronous strobe signal provided as an input to the fractional controller. A rising edge of PLLSTRB signal indicates to the fractional controller that a new fractional word is to be loaded. + 27 + 1 + read-write + + + B_0x0 + Strobe set to 0 + 0x0 + + + B_0x1 + Strobe set to 1 + 0x1 + + + + + PLLSTRBYP + PLL strobe bypass +Bypass the strobe signal. If set to 1 before setting PLLEN=1, then the PLL will start up in fractional mode depending on the setting of PLLFRACCTL. + 28 + 1 + read-write + + + B_0x0 + Do not bypass the strobe signal + 0x0 + + + B_0x1 + Bypass the strobe signal + 0x1 + + + + + PLLFRACCTL + PLL fractional mode control + 29 + 1 + read-write + + + B_0x0 + Fractional mode off + 0x0 + + + B_0x1 + Fractional mode on + 0x1 + + + + + PLLDITHEN0 + PLL dither 2 (triangular) +This bit enables the triangular dither for the PLL. + 30 + 1 + read-write + + + B_0x0 + Enables the triangular PDF dither input to SDM of PLL (not recommended) + 0x0 + + + B_0x1 + Disables the triangular PDF dither input to SDM of PLL + 0x1 + + + + + PLLDITHEN1 + PLL dither 1 (rectangular) +This bit enables the rectangular dither for the PLL. + 31 + 1 + read-write + + + B_0x0 + Enables the rectangular PDF dither input to SDM of PLL (not recommended) + 0x0 + + + B_0x1 + Disables the rectangular PDF dither input to SDM of PLL + 0x1 + + + + + + + USBPHYC_MISC + USBPHYC_MISC + USBPHYC misc control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWITHOST + Switch host +Controls main switch connecting USB PHY 2nd port between USB host controller and USB OTG controller. This register is static. + 0 + 1 + read-write + + + B_0x0 + Select OTG controller for 2nd PHY port + 0x0 + + + B_0x1 + Select Host controller for 2nd PHY port + 0x1 + + + + + PPCKDIS + Intelligent per HS PHY port clock gating control +This register is static. + 1 + 2 + read-write + + + B_0x0 + No clock gating. PHY dedicated 60 MHz Port1/Port2 clocks are always delivered to target controller. PHY 48 MHz output clock is always delivered to target controller. + 0x0 + + + B_0x1 + Intelligent clock gating for Port1. Port1 60 MHz input clock gated (Port1 is unused). Port2 dedicated 60 MHz is delivered in case of parallel data comm is requested on target controller (Host or OTG). PHY 48 MHz is delivered in case serial comm is requested on target controller (Host if SWITHOST = 1 else OTG). + 0x1 + + + B_0x2 + Intelligent clock gating for Port2. Port2 60 MHz input clock gated (Port2 is unused). Port1 dedicated 60 MHz is delivered in case of parallel data comm is requested on target controller (Host). PHY 48 MHz is delivered in case serial comm is requested on target controller (Host if SWITHOST = 1 else OTG). + 0x2 + + + B_0x3 + Intelligent clock gating for Port1 and Port2. Port1 dedicated 60 MHz is delivered in case of parallel data comm is requested on target (Host). Port2 dedicated 60 MHz is delivered in case of parallel data comm is requested on target (Host if SWITHOST = 1 else OTG). PHY 48 MHz output clock is delivered in case serial comm is requested on target controller (Host or OTG). + 0x3 + + + + + + + USBPHYC_TUNE1 + USBPHYC_TUNE1 + USBPHYC PHY 1 TUNE register + 0x10c + 0x20 + 0x04070004 + 0xFFFFFFFF + + + INCURREN + The bit enables the current boosting function. + 0 + 1 + read-write + + + B_0x0 + Disables the current boosting + 0x0 + + + B_0x1 + Enables the current boosting + 0x1 + + + + + INCURRINT + Current boosting value +This bit controls the PHY current boosting value. + 1 + 1 + read-write + + + B_0x0 + Provides a current boosting of 1mA if INCURREN = '1' + 0x0 + + + B_0x1 + Provides a current boosting of 2mA if INCURREN = '1' + 0x1 + + + + + LFSCAPEN + Low full speed enable +This bit enables the low full speed feedback capacitor. + 2 + 1 + read-write + + + B_0x0 + Disables the feedback capacitor. + 0x0 + + + B_0x1 + Enables the feedback capacitor. + 0x1 + + + + + HSDRVSLEW + HS driver slew rate +This bit controls the HS driver slew rate. + 3 + 1 + read-write + + + B_0x0 + Keeps the normal slew rate + 0x0 + + + B_0x1 + Slows the driver slew rate by 10% + 0x1 + + + + + HSDRVDCCUR + HS driver DC level +This bit allows to decrease the HS driver DC level. + 4 + 1 + read-write + + + B_0x0 + Keeps the normal HS driver DC level + 0x0 + + + B_0x1 + Decreases the HS driver DC level by 5 to 7 mV + 0x1 + + + + + HSDRVDCLEV + HS driver DC level +This bit allows to increase the HS driver DC level. I is not applicable during the HS test J and test K data transfer. + 5 + 1 + read-write + + + B_0x0 + Increases the HS driver DC level by 5 to 7 mV if HSDRVCURINCR = '1' + 0x0 + + + B_0x1 + Increases the HS driver DC level by 10 to 14 mV if HSDRVCURINCR = '1' + 0x1 + + + + + HSDRVCURINCR + Enable the HS driver current increase feature + 6 + 1 + read-write + + + B_0x0 + Disables the HSDRVDCLEV feature + 0x0 + + + B_0x1 + Enables the HSDRVDCLEV feature + 0x1 + + + + + FSDRVRFADJ + Tuning pin to adjust the full speed rise/fall time + 7 + 1 + read-write + + + B_0x0 + Disables the full speed rise/fall tuning option + 0x0 + + + B_0x1 + Enables the full speed rise/fall tuning option + 0x1 + + + + + HSDRVRFRED + High-speed rise-fall reduction enable + 8 + 1 + read-write + + + B_0x0 + Default rise/fall time + 0x0 + + + B_0x1 + Increases the rise/fall time by 20% + 0x1 + + + + + HSDRVCHKITRM + HS driver choke current trim +This bitfield controls the HS driver current trimming pins for choke compensation. + 9 + 4 + read-write + + + B_0x0 + 18.87 mA target current / nominal + 0% + 0x0 + + + B_0x1 + 19.165 mA target current / nominal + 1.56% + 0x1 + + + B_0x2 + 19.46 mA target current / nominal + 3.12% + 0x2 + + + B_0x3 + 19.755 mA target current / nominal + 4.68% + 0x3 + + + B_0x4 + 20.05 mA target current / nominal + 6.24% + 0x4 + + + B_0x5 + 20.345 mA target current / nominal + 7.8% + 0x5 + + + B_0x6 + 20.64 mA target current / nominal + 9.36% + 0x6 + + + B_0x7 + 20.935 mA target current / nominal + 10.92% + 0x7 + + + B_0x8 + 21.23 mA target current / nominal + 12.48% + 0x8 + + + B_0x9 + 21.525 mA target current / nominal + 14.04% + 0x9 + + + B_0xA + 21.82 mA target current / nominal + 15.6% + 0xA + + + B_0xB + 22.115 mA target current / nominal + 17.16% + 0xB + + + B_0xC + 22.458 mA target current / nominal + 19.01% + 0xC + + + B_0xD + 22.755 mA target current / nominal + 20.58% + 0xD + + + B_0xE + 23.052 mA target current / nominal + 22.16% + 0xE + + + B_0xF + 23.348 mA target current / nominal + 23.73% + 0xF + + + + + HSDRVCHKZTRM + HS driver choke impedance trim +This bitfield controls the PHY bus HS driver impedance tuning for choke compensation. + 13 + 2 + read-write + + + B_0x0 + No impedance offset + 0x0 + + + B_0x1 + Reduce the impedance by 2 Ω + 0x1 + + + B_0x2 + Reduce the impedance by 4 Ω + 0x2 + + + B_0x3 + Reduce the impedance by 6 Ω + 0x3 + + + + + OTPCOMP + OTP compensation code + 15 + 5 + read-write + + + SQLCHCTL + Squelch control +This bitfield adjusts the squelch DC threshold value. + 20 + 2 + read-write + + + B_0x0 + No shift in threshold + 0x0 + + + B_0x1 + Squelch DC threshold shift by +7 mV + 0x1 + + + B_0x2 + Squelch DC threshold shift by -5 mV + 0x2 + + + B_0x3 + Squelch DC threshold shift by +14 mV + 0x3 + + + + + HDRXGNEQEN + Enable HS Rx gain equalizer + 22 + 1 + read-write + + + B_0x0 + Disable the gain equalizer + 0x0 + + + B_0x1 + Enable the gain equalizer + 0x1 + + + + + HSRXOFF + HS receiver offset adjustment + 23 + 2 + read-write + + + B_0x0 + No offset + 0x0 + + + B_0x1 + Offset +5 mV + 0x1 + + + B_0x2 + Offset +10 mV + 0x2 + + + B_0x3 + Offset -5 mV + 0x3 + + + + + HSFALLPREEM + HS fall time pre-emphasis +This bit enables the HS fall time control of single ended signals during pre-emphasis: + 25 + 1 + read-write + + + B_0x0 + Control On + 0x0 + + + B_0x1 + Control Off + 0x1 + + + + + SHTCCTCTLPROT + Short circuit control protection +This bit enables the short circuit protection circuitry in LS/FS driver. + 26 + 1 + read-write + + + B_0x0 + Short circuit protection disabled + 0x0 + + + B_0x1 + Short circuit protection enabled + 0x1 + + + + + STAGSEL + Staggering selection +This bit enables the HS Tx staggering. + 27 + 1 + read-write + + + B_0x0 + Disable the basic staggering in HS Tx mode + 0x0 + + + B_0x1 + Enable the basic staggering in HS Tx mode + 0x1 + + + + + + + USBPHYC_TUNE2 + USBPHYC_TUNE2 + USBPHYC PHY 2 TUNE register + 0x20c + 0x20 + 0x04070004 + 0xFFFFFFFF + + + INCURREN + The bit enables the current boosting function. + 0 + 1 + read-write + + + B_0x0 + Disables the current boosting + 0x0 + + + B_0x1 + Enables the current boosting + 0x1 + + + + + INCURRINT + Current boosting value +This bit controls the PHY current boosting value. + 1 + 1 + read-write + + + B_0x0 + Provides a current boosting of 1mA if INCURREN = '1' + 0x0 + + + B_0x1 + Provides a current boosting of 2mA if INCURREN = '1' + 0x1 + + + + + LFSCAPEN + Low full speed enable +This bit enables the low full speed feedback capacitor. + 2 + 1 + read-write + + + B_0x0 + Disables the feedback capacitor. + 0x0 + + + B_0x1 + Enables the feedback capacitor. + 0x1 + + + + + HSDRVSLEW + HS driver slew rate +This bit controls the HS driver slew rate. + 3 + 1 + read-write + + + B_0x0 + Keeps the normal slew rate + 0x0 + + + B_0x1 + Slows the driver slew rate by 10% + 0x1 + + + + + HSDRVDCCUR + HS driver DC level +This bit allows to decrease the HS driver DC level. + 4 + 1 + read-write + + + B_0x0 + Keeps the normal HS driver DC level + 0x0 + + + B_0x1 + Decreases the HS driver DC level by 5 to 7 mV + 0x1 + + + + + HSDRVDCLEV + HS driver DC level +This bit allows to increase the HS driver DC level. I is not applicable during the HS test J and test K data transfer. + 5 + 1 + read-write + + + B_0x0 + Increases the HS driver DC level by 5 to 7 mV if HSDRVCURINCR = '1' + 0x0 + + + B_0x1 + Increases the HS driver DC level by 10 to 14 mV if HSDRVCURINCR = '1' + 0x1 + + + + + HSDRVCURINCR + Enable the HS driver current increase feature + 6 + 1 + read-write + + + B_0x0 + Disables the HSDRVDCLEV feature + 0x0 + + + B_0x1 + Enables the HSDRVDCLEV feature + 0x1 + + + + + FSDRVRFADJ + Tuning pin to adjust the full speed rise/fall time + 7 + 1 + read-write + + + B_0x0 + Disables the full speed rise/fall tuning option + 0x0 + + + B_0x1 + Enables the full speed rise/fall tuning option + 0x1 + + + + + HSDRVRFRED + High-speed rise-fall reduction enable + 8 + 1 + read-write + + + B_0x0 + Default rise/fall time + 0x0 + + + B_0x1 + Increases the rise/fall time by 20% + 0x1 + + + + + HSDRVCHKITRM + HS driver choke current trim +This bitfield controls the HS driver current trimming pins for choke compensation. + 9 + 4 + read-write + + + B_0x0 + 18.87 mA target current / nominal + 0% + 0x0 + + + B_0x1 + 19.165 mA target current / nominal + 1.56% + 0x1 + + + B_0x2 + 19.46 mA target current / nominal + 3.12% + 0x2 + + + B_0x3 + 19.755 mA target current / nominal + 4.68% + 0x3 + + + B_0x4 + 20.05 mA target current / nominal + 6.24% + 0x4 + + + B_0x5 + 20.345 mA target current / nominal + 7.8% + 0x5 + + + B_0x6 + 20.64 mA target current / nominal + 9.36% + 0x6 + + + B_0x7 + 20.935 mA target current / nominal + 10.92% + 0x7 + + + B_0x8 + 21.23 mA target current / nominal + 12.48% + 0x8 + + + B_0x9 + 21.525 mA target current / nominal + 14.04% + 0x9 + + + B_0xA + 21.82 mA target current / nominal + 15.6% + 0xA + + + B_0xB + 22.115 mA target current / nominal + 17.16% + 0xB + + + B_0xC + 22.458 mA target current / nominal + 19.01% + 0xC + + + B_0xD + 22.755 mA target current / nominal + 20.58% + 0xD + + + B_0xE + 23.052 mA target current / nominal + 22.16% + 0xE + + + B_0xF + 23.348 mA target current / nominal + 23.73% + 0xF + + + + + HSDRVCHKZTRM + HS driver choke impedance trim +This bitfield controls the PHY bus HS driver impedance tuning for choke compensation. + 13 + 2 + read-write + + + B_0x0 + No impedance offset + 0x0 + + + B_0x1 + Reduce the impedance by 2 Ω + 0x1 + + + B_0x2 + Reduce the impedance by 4 Ω + 0x2 + + + B_0x3 + Reduce the impedance by 6 Ω + 0x3 + + + + + OTPCOMP + OTP compensation code + 15 + 5 + read-write + + + SQLCHCTL + Squelch control +This bitfield adjusts the squelch DC threshold value. + 20 + 2 + read-write + + + B_0x0 + No shift in threshold + 0x0 + + + B_0x1 + Squelch DC threshold shift by +7 mV + 0x1 + + + B_0x2 + Squelch DC threshold shift by -5 mV + 0x2 + + + B_0x3 + Squelch DC threshold shift by +14 mV + 0x3 + + + + + HDRXGNEQEN + Enable HS Rx gain equalizer + 22 + 1 + read-write + + + B_0x0 + Disable the gain equalizer + 0x0 + + + B_0x1 + Enable the gain equalizer + 0x1 + + + + + HSRXOFF + HS receiver offset adjustment + 23 + 2 + read-write + + + B_0x0 + No offset + 0x0 + + + B_0x1 + Offset +5 mV + 0x1 + + + B_0x2 + Offset +10 mV + 0x2 + + + B_0x3 + Offset -5 mV + 0x3 + + + + + HSFALLPREEM + HS fall time pre-emphasis +This bit enables the HS fall time control of single ended signals during pre-emphasis: + 25 + 1 + read-write + + + B_0x0 + Control On + 0x0 + + + B_0x1 + Control Off + 0x1 + + + + + SHTCCTCTLPROT + Short circuit control protection +This bit enables the short circuit protection circuitry in LS/FS driver. + 26 + 1 + read-write + + + B_0x0 + Short circuit protection disabled + 0x0 + + + B_0x1 + Short circuit protection enabled + 0x1 + + + + + STAGSEL + Staggering selection +This bit enables the HS Tx staggering. + 27 + 1 + read-write + + + B_0x0 + Disable the basic staggering in HS Tx mode + 0x0 + + + B_0x1 + Enable the basic staggering in HS Tx mode + 0x1 + + + + + + + USBPHYC_VERR + USBPHYC_VERR + USBPHYC VERSION register + 0xffc + 0x20 + 0x00000010 + 0xFFFFFFFF + + + MINREV + Minor revision + 0 + 4 + read-only + + + MAJREV + Major revision + 4 + 4 + read-only + + + + + + + VREFBUF + VREFBUF + VREFBUF + 0x50025000 + + 0x0 + 0x400 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x0 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable +This bit is used to enable the voltage reference buffer mode. + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode +This bit controls the analog switch to connect or not the VREF+ pin. +Refer to for the mode descriptions depending on ENVR bit configuration. + 1 + 1 + read-write + + + B_0x0 + VREF+ pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + VREF+ pin is high impedance. + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + VRS + Voltage reference scale +These bits select the value generated by the voltage reference buffer. +VRS = 000: VREFBUF0 voltage selected. +VRS = 001: VREFBUF1 voltage selected. +VRS = 010: VREFBUF2 voltage selected. +VRS = 011: VREFBUF3 voltage selected. +Others: Reserved +Note: Refer to the product datasheet for each VREFBUFx voltage setting value. +The software can program this bitfield only when the VREFBUF is disabled (ENVR=0). + 4 + 3 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + TRIM + Trimming code +The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. +Reset: +TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. +VRS change: +TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. +Write in TRIM[5:0]: +User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). +Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order. + 0 + 6 + read-write + + + + + + + diff --git a/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP15xxx.svd b/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP15xxx.svd new file mode 100644 index 0000000..1fe06e9 --- /dev/null +++ b/recipes-devtools/cmsis-svd/cmsis-svd/STM32MP15xxx.svd @@ -0,0 +1,149424 @@ + + + STM32MP15xxx + 1.2 + STM32MP15xxx + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC2 + ADC2 + ADC2 + 0x48003100 + + 0x0 + 0x100 + registers + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + ADRDY + ADRDY + 0 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + EOC + EOC + 2 + 1 + + + EOS + EOS + 3 + 1 + + + OVR + OVR + 4 + 1 + + + JEOC + JEOC + 5 + 1 + + + JEOS + JEOS + 6 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + JQOVF + JQOVF + 10 + 1 + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + + + ADC_CR + ADC_CR + ADC control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADEN + ADEN + 0 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + BOOST + BOOST + 8 + 1 + + + ADCALLIN + ADCALLIN + 16 + 1 + + + LINCALRDYW1 + LINCALRDYW1 + 22 + 1 + + + LINCALRDYW2 + LINCALRDYW2 + 23 + 1 + + + LINCALRDYW3 + LINCALRDYW3 + 24 + 1 + + + LINCALRDYW4 + LINCALRDYW4 + 25 + 1 + + + LINCALRDYW5 + LINCALRDYW5 + 26 + 1 + + + LINCALRDYW6 + LINCALRDYW6 + 27 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + ADCAL + ADCAL + 31 + 1 + + + + + ADC_CFGR + ADC_CFGR + ADC configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + DMNGT + DMNGT + 0 + 2 + + + RES + RES + 2 + 3 + + + EXTSEL + EXTSEL + 5 + 5 + + + EXTEN + EXTEN + 10 + 2 + + + OVRMOD + OVRMOD + 12 + 1 + + + CONT + CONT + 13 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + DISCEN + DISCEN + 16 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + JDISCEN + JDISCEN + 20 + 1 + + + JQM + JQM + 21 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + JAUTO + JAUTO + 25 + 1 + + + AWD1CH + AWD1CH + 26 + 5 + + + JQDIS + JQDIS + 31 + 1 + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSE + ROVSE + 0 + 1 + + + JOVSE + JOVSE + 1 + 1 + + + OVSS + OVSS + 5 + 4 + + + TROVS + TROVS + 9 + 1 + + + ROVSM + ROVSM + 10 + 1 + + + RSHIFT1 + RSHIFT1 + 11 + 1 + + + RSHIFT2 + RSHIFT2 + 12 + 1 + + + RSHIFT3 + RSHIFT3 + 13 + 1 + + + RSHIFT4 + RSHIFT4 + 14 + 1 + + + OSVR + OSVR + 16 + 10 + + + LSHIFT + LSHIFT + 28 + 4 + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP0 + SMP0 + 0 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP9 + SMP9 + 27 + 3 + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP10 + SMP10 + 0 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP18 + SMP18 + 24 + 3 + + + SMP19 + SMP19 + 27 + 3 + + + + + ADC_PCSEL + ADC_PCSEL + ADC channel preselection register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL0 + PCSEL0 + 0 + 1 + + + PCSEL1 + PCSEL1 + 1 + 1 + + + PCSEL2 + PCSEL2 + 2 + 1 + + + PCSEL3 + PCSEL3 + 3 + 1 + + + PCSEL4 + PCSEL4 + 4 + 1 + + + PCSEL5 + PCSEL5 + 5 + 1 + + + PCSEL6 + PCSEL6 + 6 + 1 + + + PCSEL7 + PCSEL7 + 7 + 1 + + + PCSEL8 + PCSEL8 + 8 + 1 + + + PCSEL9 + PCSEL9 + 9 + 1 + + + PCSEL10 + PCSEL10 + 10 + 1 + + + PCSEL11 + PCSEL11 + 11 + 1 + + + PCSEL12 + PCSEL12 + 12 + 1 + + + PCSEL13 + PCSEL13 + 13 + 1 + + + PCSEL14 + PCSEL14 + 14 + 1 + + + PCSEL15 + PCSEL15 + 15 + 1 + + + PCSEL16 + PCSEL16 + 16 + 1 + + + PCSEL17 + PCSEL17 + 17 + 1 + + + PCSEL18 + PCSEL18 + 18 + 1 + + + PCSEL19 + PCSEL19 + 19 + 1 + + + + + ADC_LTR1 + ADC_LTR1 + ADC watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + LTR1 + LTR1 + 0 + 26 + + + + + ADC_HTR1 + ADC_HTR1 + ADC watchdog threshold register 1 + 0x24 + 0x20 + read-write + 0x03FFFFFF + + + HTR1 + HTR1 + 0 + 26 + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + L + L + 0 + 4 + + + SQ1 + SQ1 + 6 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ4 + SQ4 + 24 + 5 + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ5 + SQ5 + 0 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ9 + SQ9 + 24 + 5 + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ10 + SQ10 + 0 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ14 + SQ14 + 24 + 5 + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ15 + SQ15 + 0 + 5 + + + SQ16 + SQ16 + 6 + 5 + + + + + ADC_DR + ADC_DR + ADC regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 32 + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JL + JL + 0 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JSQ1 + JSQ1 + 9 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ4 + JSQ4 + 27 + 5 + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset register + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1 + OFFSET1 + 0 + 26 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset register + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET2 + OFFSET2 + 0 + 26 + + + OFFSET2_CH + OFFSET2_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset register + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3 + OFFSET3 + 0 + 26 + + + OFFSET3_CH + OFFSET3_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset register + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4 + OFFSET4 + 0 + 26 + + + OFFSET4_CH + OFFSET4_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected data register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected data register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected data register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected data register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 20 + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 20 + + + + + ADC_LTR2 + ADC_LTR2 + ADC watchdog lower threshold register 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + LTR2 + 0 + 26 + + + + + ADC_HTR2 + ADC_HTR2 + ADC watchdog higher threshold register 2 + 0xB4 + 0x20 + read-write + 0x03FFFFFF + + + HTR2 + HTR2 + 0 + 26 + + + + + ADC_LTR3 + ADC_LTR3 + ADC watchdog lower threshold register 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + LTR3 + 0 + 26 + + + + + ADC_HTR3 + ADC_HTR3 + ADC watchdog higher threshold register 3 + 0xBC + 0x20 + read-write + 0x03FFFFFF + + + HTR3 + HTR3 + 0 + 26 + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC differential mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + DIFSEL + 0 + 20 + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factors register + 0xC4 + 0x20 + read-write + 0x00000000 + + + CALFACT_S + CALFACT_S + 0 + 11 + + + CALFACT_D + CALFACT_D + 16 + 11 + + + + + ADC_CALFACT2 + ADC_CALFACT2 + ADC calibration factor register 2 + 0xC8 + 0x20 + read-write + 0x00000000 + + + LINCALFACT + LINCALFACT + 0 + 30 + + + + + ADC2_OR + ADC2_OR + ADC2 option register + 0xD0 + 0x20 + read-write + 0x00000000 + + + VDDCOREEN + VDDCOREEN + 0 + 1 + + + + + + + ADC + ADC + ADC + 0x48003000 + + 0x0 + 0x100 + registers + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + ADRDY + ADRDY + 0 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + EOC + EOC + 2 + 1 + + + EOS + EOS + 3 + 1 + + + OVR + OVR + 4 + 1 + + + JEOC + JEOC + 5 + 1 + + + JEOS + JEOS + 6 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + JQOVF + JQOVF + 10 + 1 + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + + + ADC_CR + ADC_CR + ADC control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADEN + ADEN + 0 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + BOOST + BOOST + 8 + 1 + + + ADCALLIN + ADCALLIN + 16 + 1 + + + LINCALRDYW1 + LINCALRDYW1 + 22 + 1 + + + LINCALRDYW2 + LINCALRDYW2 + 23 + 1 + + + LINCALRDYW3 + LINCALRDYW3 + 24 + 1 + + + LINCALRDYW4 + LINCALRDYW4 + 25 + 1 + + + LINCALRDYW5 + LINCALRDYW5 + 26 + 1 + + + LINCALRDYW6 + LINCALRDYW6 + 27 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + ADCAL + ADCAL + 31 + 1 + + + + + ADC_CFGR + ADC_CFGR + ADC configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + DMNGT + DMNGT + 0 + 2 + + + RES + RES + 2 + 3 + + + EXTSEL + EXTSEL + 5 + 5 + + + EXTEN + EXTEN + 10 + 2 + + + OVRMOD + OVRMOD + 12 + 1 + + + CONT + CONT + 13 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + DISCEN + DISCEN + 16 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + JDISCEN + JDISCEN + 20 + 1 + + + JQM + JQM + 21 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + JAUTO + JAUTO + 25 + 1 + + + AWD1CH + AWD1CH + 26 + 5 + + + JQDIS + JQDIS + 31 + 1 + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSE + ROVSE + 0 + 1 + + + JOVSE + JOVSE + 1 + 1 + + + OVSS + OVSS + 5 + 4 + + + TROVS + TROVS + 9 + 1 + + + ROVSM + ROVSM + 10 + 1 + + + RSHIFT1 + RSHIFT1 + 11 + 1 + + + RSHIFT2 + RSHIFT2 + 12 + 1 + + + RSHIFT3 + RSHIFT3 + 13 + 1 + + + RSHIFT4 + RSHIFT4 + 14 + 1 + + + OSVR + OSVR + 16 + 10 + + + LSHIFT + LSHIFT + 28 + 4 + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP0 + SMP0 + 0 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP9 + SMP9 + 27 + 3 + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP10 + SMP10 + 0 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP18 + SMP18 + 24 + 3 + + + SMP19 + SMP19 + 27 + 3 + + + + + ADC_PCSEL + ADC_PCSEL + ADC channel preselection register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCSEL0 + PCSEL0 + 0 + 1 + + + PCSEL1 + PCSEL1 + 1 + 1 + + + PCSEL2 + PCSEL2 + 2 + 1 + + + PCSEL3 + PCSEL3 + 3 + 1 + + + PCSEL4 + PCSEL4 + 4 + 1 + + + PCSEL5 + PCSEL5 + 5 + 1 + + + PCSEL6 + PCSEL6 + 6 + 1 + + + PCSEL7 + PCSEL7 + 7 + 1 + + + PCSEL8 + PCSEL8 + 8 + 1 + + + PCSEL9 + PCSEL9 + 9 + 1 + + + PCSEL10 + PCSEL10 + 10 + 1 + + + PCSEL11 + PCSEL11 + 11 + 1 + + + PCSEL12 + PCSEL12 + 12 + 1 + + + PCSEL13 + PCSEL13 + 13 + 1 + + + PCSEL14 + PCSEL14 + 14 + 1 + + + PCSEL15 + PCSEL15 + 15 + 1 + + + PCSEL16 + PCSEL16 + 16 + 1 + + + PCSEL17 + PCSEL17 + 17 + 1 + + + PCSEL18 + PCSEL18 + 18 + 1 + + + PCSEL19 + PCSEL19 + 19 + 1 + + + + + ADC_LTR1 + ADC_LTR1 + ADC watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + LTR1 + LTR1 + 0 + 26 + + + + + ADC_HTR1 + ADC_HTR1 + ADC watchdog threshold register 1 + 0x24 + 0x20 + read-write + 0x03FFFFFF + + + HTR1 + HTR1 + 0 + 26 + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + L + L + 0 + 4 + + + SQ1 + SQ1 + 6 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ4 + SQ4 + 24 + 5 + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ5 + SQ5 + 0 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ9 + SQ9 + 24 + 5 + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ10 + SQ10 + 0 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ14 + SQ14 + 24 + 5 + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ15 + SQ15 + 0 + 5 + + + SQ16 + SQ16 + 6 + 5 + + + + + ADC_DR + ADC_DR + ADC regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 32 + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JL + JL + 0 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JSQ1 + JSQ1 + 9 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ4 + JSQ4 + 27 + 5 + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset register + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1 + OFFSET1 + 0 + 26 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset register + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET2 + OFFSET2 + 0 + 26 + + + OFFSET2_CH + OFFSET2_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset register + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3 + OFFSET3 + 0 + 26 + + + OFFSET3_CH + OFFSET3_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset register + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4 + OFFSET4 + 0 + 26 + + + OFFSET4_CH + OFFSET4_CH + 26 + 5 + + + SSATE + SSATE + 31 + 1 + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected data register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected data register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected data register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected data register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA + JDATA + 0 + 32 + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 20 + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 20 + + + + + ADC_LTR2 + ADC_LTR2 + ADC watchdog lower threshold register 2 + 0xB0 + 0x20 + read-write + 0x00000000 + + + LTR2 + LTR2 + 0 + 26 + + + + + ADC_HTR2 + ADC_HTR2 + ADC watchdog higher threshold register 2 + 0xB4 + 0x20 + read-write + 0x03FFFFFF + + + HTR2 + HTR2 + 0 + 26 + + + + + ADC_LTR3 + ADC_LTR3 + ADC watchdog lower threshold register 3 + 0xB8 + 0x20 + read-write + 0x00000000 + + + LTR3 + LTR3 + 0 + 26 + + + + + ADC_HTR3 + ADC_HTR3 + ADC watchdog higher threshold register 3 + 0xBC + 0x20 + read-write + 0x03FFFFFF + + + HTR3 + HTR3 + 0 + 26 + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC differential mode selection register + 0xC0 + 0x20 + read-write + 0x00000000 + + + DIFSEL + DIFSEL + 0 + 20 + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factors register + 0xC4 + 0x20 + read-write + 0x00000000 + + + CALFACT_S + CALFACT_S + 0 + 11 + + + CALFACT_D + CALFACT_D + 16 + 11 + + + + + ADC_CALFACT2 + ADC_CALFACT2 + ADC calibration factor register 2 + 0xC8 + 0x20 + read-write + 0x00000000 + + + LINCALFACT + LINCALFACT + 0 + 30 + + + + + + + ADC_common + Analog-to-Digital Converter + ADC + 0x48003300 + + 0x0 + 0x100 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + EOC_SLV + 18 + 1 + + + EOS_SLV + EOS_SLV + 19 + 1 + + + OVR_SLV + OVR_SLV + 20 + 1 + + + JEOC_SLV + JEOC_SLV + 21 + 1 + + + JEOS_SLV + JEOS_SLV + 22 + 1 + + + AWD1_SLV + AWD1_SLV + 23 + 1 + + + AWD2_SLV + AWD2_SLV + 24 + 1 + + + AWD3_SLV + AWD3_SLV + 25 + 1 + + + JQOVF_SLV + JQOVF_SLV + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 16 + 2 + + + PRESC + ADC prescaler + 18 + 4 + + + VREFEN + VREFINT enable + 22 + 1 + + + CH17SEL + CH17SEL + 23 + 1 + + + CH18SEL + CH18SEL + 24 + 1 + + + MDMA + MDMA + 14 + 2 + + + DMACFG + DMACFG + 13 + 1 + + + DELAY + DELAY + 8 + 3 + + + DUAL + DUAL + 0 + 5 + + + + + CDR + CDR + Common regular data register for dual mode + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_MST + RDATA_MST + 0 + 16 + + + RDATA_SLV + RDATA_SLV + 16 + 16 + + + + + CDR2 + CDR2 + Common regular data register for dual mode + 0x10 + 0x20 + read-only + 0x00000000 + + + RDATA_ALT + RDATA_ALT + 0 + 32 + + + + + + + BSEC + BSEC2 + BSEC2 + 0x5C005000 + + 0x0 + 0x1000 + registers + + + + BSEC_OTP_CONFIG + BSEC_OTP_CONFIG + BSEC OTP configuration register + 0x0 + 0x20 + read-write + 0x0000000E + + + PWRUP + PWRUP + 0 + 1 + + + FRC + FRC + 1 + 2 + + + PRGWIDTH + PRGWIDTH + 3 + 4 + + + TREAD + TREAD + 7 + 2 + + + + + BSEC_OTP_CONTROL + BSEC_OTP_CONTROL + BSEC OTP control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDR + ADDR + 0 + 7 + + + PROG + PROG + 8 + 1 + + + LOCK + LOCK + 9 + 1 + + + + + BSEC_OTP_WRDATA + BSEC_OTP_WRDATA + BSEC OTP write data register + 0x8 + 0x20 + read-write + 0x00000000 + + + WRDATA + WRDATA + 0 + 32 + + + + + BSEC_OTP_STATUS + BSEC_OTP_STATUS + BSEC OTP status register + 0xC + 0x20 + read-only + 0x00000000 + + + SECURE + SECURE + 0 + 1 + + + FULLDBG + FULLDBG + 1 + 1 + + + INVALID + INVALID + 2 + 1 + + + BUSY + BUSY + 3 + 1 + + + PROGFAIL + PROGFAIL + 4 + 1 + + + PWRON + PWRON + 5 + 1 + + + BIST1LOCK + BIST1LOCK + 6 + 1 + + + BIST2LOCK + BIST2LOCK + 7 + 1 + + + + + BSEC_OTP_LOCK + BSEC_OTP_LOCK + BSEC OTP lock configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTP + OTP + 0 + 1 + + + ROMLOCK + ROMLOCK + 1 + 1 + + + DENREG + DENREG + 2 + 1 + + + GPLOCK + GPLOCK + 4 + 1 + + + + + BSEC_DENABLE + BSEC_DENABLE + reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181. + 0x14 + 0x20 + read-write + 0x00000000 + + + DFTEN + DFTEN + 0 + 1 + + + DBGEN + DBGEN + 1 + 1 + + + NIDEN + NIDEN + 2 + 1 + + + DEVICEEN + DEVICEEN + 3 + 1 + + + HDPEN + HDPEN + 4 + 1 + + + SPIDEN + SPIDEN + 5 + 1 + + + SPNIDEN + SPNIDEN + 6 + 1 + + + CP15SDISABLE + CP15SDISABLE + 7 + 2 + + + CFGSDISABLE + CFGSDISABLE + 9 + 1 + + + DBGSWENABLE + DBGSWENABLE + 10 + 1 + + + + + BSEC_OTP_DISTURBED0 + BSEC_OTP_DISTURBED0 + BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. + 0x1C + 0x20 + read-only + 0x00000000 + + + DIS + DIS + 0 + 32 + + + + + BSEC_OTP_DISTURBED1 + BSEC_OTP_DISTURBED1 + BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. + 0x20 + 0x20 + read-only + 0x00000000 + + + DIS + DIS + 0 + 32 + + + + + BSEC_OTP_DISTURBED2 + BSEC_OTP_DISTURBED2 + BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. + 0x24 + 0x20 + read-only + 0x00000000 + + + DIS + DIS + 0 + 32 + + + + + BSEC_OTP_ERROR0 + BSEC_OTP_ERROR0 + BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. + 0x34 + 0x20 + read-only + 0x00000000 + + + ERR + ERR + 0 + 32 + + + + + BSEC_OTP_ERROR1 + BSEC_OTP_ERROR1 + BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. + 0x38 + 0x20 + read-only + 0x00000000 + + + ERR + ERR + 0 + 32 + + + + + BSEC_OTP_ERROR2 + BSEC_OTP_ERROR2 + BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. + 0x3C + 0x20 + read-only + 0x00000000 + + + ERR + ERR + 0 + 32 + + + + + BSEC_OTP_WRLOCK0 + BSEC_OTP_WRLOCK0 + BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). + 0x4C + 0x20 + read-only + 0x00000000 + + + WRLOCK + WRLOCK + 0 + 32 + + + + + BSEC_OTP_WRLOCK1 + BSEC_OTP_WRLOCK1 + BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). + 0x50 + 0x20 + read-only + 0x00000000 + + + WRLOCK + WRLOCK + 0 + 32 + + + + + BSEC_OTP_WRLOCK2 + BSEC_OTP_WRLOCK2 + BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). + 0x54 + 0x20 + read-only + 0x00000000 + + + WRLOCK + WRLOCK + 0 + 32 + + + + + BSEC_OTP_SPLOCK0 + BSEC_OTP_SPLOCK0 + BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. + 0x64 + 0x20 + read-write + 0x00000000 + + + SPLOCK + SPLOCK + 0 + 32 + + + + + BSEC_OTP_SPLOCK1 + BSEC_OTP_SPLOCK1 + BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. + 0x68 + 0x20 + read-write + 0x00000000 + + + SPLOCK + SPLOCK + 0 + 32 + + + + + BSEC_OTP_SPLOCK2 + BSEC_OTP_SPLOCK2 + BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. + 0x6C + 0x20 + read-write + 0x00000000 + + + SPLOCK + SPLOCK + 0 + 32 + + + + + BSEC_OTP_SWLOCK0 + BSEC_OTP_SWLOCK0 + BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. + 0x7C + 0x20 + read-write + 0x00000001 + + + SWLOCK + SWLOCK + 0 + 32 + + + + + BSEC_OTP_SWLOCK1 + BSEC_OTP_SWLOCK1 + BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. + 0x80 + 0x20 + read-write + 0x00000001 + + + SWLOCK + SWLOCK + 0 + 32 + + + + + BSEC_OTP_SWLOCK2 + BSEC_OTP_SWLOCK2 + BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. + 0x84 + 0x20 + read-write + 0x00000001 + + + SWLOCK + SWLOCK + 0 + 32 + + + + + BSEC_OTP_SRLOCK0 + BSEC_OTP_SRLOCK0 + BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. + 0x94 + 0x20 + read-write + 0x00000000 + + + SRLOCK + SRLOCK + 0 + 32 + + + + + BSEC_OTP_SRLOCK1 + BSEC_OTP_SRLOCK1 + BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. + 0x98 + 0x20 + read-write + 0x00000000 + + + SRLOCK + SRLOCK + 0 + 32 + + + + + BSEC_OTP_SRLOCK2 + BSEC_OTP_SRLOCK2 + BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. + 0x9C + 0x20 + read-write + 0x00000000 + + + SRLOCK + SRLOCK + 0 + 32 + + + + + BSEC_JTAGIN + BSEC_JTAGIN + BSEC JTAG input register + 0xAC + 0x20 + read-only + 0x00000000 + + + DATA + DATA + 0 + 16 + + + + + BSEC_JTAGOUT + BSEC_JTAGOUT + BSEC JTAG output register + 0xB0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 16 + + + + + BSEC_SCRATCH + BSEC_SCRATCH + BSEC scratch register + 0xB4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA0 + BSEC_OTP_DATA0 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x200 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA1 + BSEC_OTP_DATA1 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x204 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA2 + BSEC_OTP_DATA2 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x208 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA3 + BSEC_OTP_DATA3 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x20C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA4 + BSEC_OTP_DATA4 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x210 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA5 + BSEC_OTP_DATA5 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x214 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA6 + BSEC_OTP_DATA6 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x218 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA7 + BSEC_OTP_DATA7 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x21C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA8 + BSEC_OTP_DATA8 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x220 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA9 + BSEC_OTP_DATA9 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x224 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA10 + BSEC_OTP_DATA10 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x228 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA11 + BSEC_OTP_DATA11 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x22C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA12 + BSEC_OTP_DATA12 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x230 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA13 + BSEC_OTP_DATA13 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x234 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA14 + BSEC_OTP_DATA14 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x238 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA15 + BSEC_OTP_DATA15 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x23C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA16 + BSEC_OTP_DATA16 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x240 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA17 + BSEC_OTP_DATA17 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x244 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA18 + BSEC_OTP_DATA18 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x248 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA19 + BSEC_OTP_DATA19 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x24C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA20 + BSEC_OTP_DATA20 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x250 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA21 + BSEC_OTP_DATA21 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x254 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA22 + BSEC_OTP_DATA22 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x258 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA23 + BSEC_OTP_DATA23 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x25C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA24 + BSEC_OTP_DATA24 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x260 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA25 + BSEC_OTP_DATA25 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x264 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA26 + BSEC_OTP_DATA26 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x268 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA27 + BSEC_OTP_DATA27 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x26C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA28 + BSEC_OTP_DATA28 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x270 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA29 + BSEC_OTP_DATA29 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x274 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA30 + BSEC_OTP_DATA30 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x278 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA31 + BSEC_OTP_DATA31 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x27C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA32 + BSEC_OTP_DATA32 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x280 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA33 + BSEC_OTP_DATA33 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x284 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA34 + BSEC_OTP_DATA34 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x288 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA35 + BSEC_OTP_DATA35 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x28C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA36 + BSEC_OTP_DATA36 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x290 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA37 + BSEC_OTP_DATA37 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x294 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA38 + BSEC_OTP_DATA38 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x298 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA39 + BSEC_OTP_DATA39 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x29C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA40 + BSEC_OTP_DATA40 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2A0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA41 + BSEC_OTP_DATA41 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2A4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA42 + BSEC_OTP_DATA42 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2A8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA43 + BSEC_OTP_DATA43 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2AC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA44 + BSEC_OTP_DATA44 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2B0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA45 + BSEC_OTP_DATA45 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2B4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA46 + BSEC_OTP_DATA46 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2B8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA47 + BSEC_OTP_DATA47 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2BC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA48 + BSEC_OTP_DATA48 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2C0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA49 + BSEC_OTP_DATA49 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2C4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA50 + BSEC_OTP_DATA50 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2C8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA51 + BSEC_OTP_DATA51 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2CC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA52 + BSEC_OTP_DATA52 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2D0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA53 + BSEC_OTP_DATA53 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2D4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA54 + BSEC_OTP_DATA54 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2D8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA55 + BSEC_OTP_DATA55 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2DC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA56 + BSEC_OTP_DATA56 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2E0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA57 + BSEC_OTP_DATA57 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2E4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA58 + BSEC_OTP_DATA58 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2E8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA59 + BSEC_OTP_DATA59 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2EC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA60 + BSEC_OTP_DATA60 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2F0 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA61 + BSEC_OTP_DATA61 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2F4 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA62 + BSEC_OTP_DATA62 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2F8 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA63 + BSEC_OTP_DATA63 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x2FC + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA64 + BSEC_OTP_DATA64 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x300 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA65 + BSEC_OTP_DATA65 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x304 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA66 + BSEC_OTP_DATA66 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x308 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA67 + BSEC_OTP_DATA67 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x30C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA68 + BSEC_OTP_DATA68 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x310 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA69 + BSEC_OTP_DATA69 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x314 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA70 + BSEC_OTP_DATA70 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x318 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA71 + BSEC_OTP_DATA71 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x31C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA72 + BSEC_OTP_DATA72 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x320 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA73 + BSEC_OTP_DATA73 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x324 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA74 + BSEC_OTP_DATA74 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x328 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA75 + BSEC_OTP_DATA75 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x32C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA76 + BSEC_OTP_DATA76 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x330 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA77 + BSEC_OTP_DATA77 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x334 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA78 + BSEC_OTP_DATA78 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x338 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA79 + BSEC_OTP_DATA79 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x33C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA80 + BSEC_OTP_DATA80 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x340 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA81 + BSEC_OTP_DATA81 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x344 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA82 + BSEC_OTP_DATA82 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x348 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA83 + BSEC_OTP_DATA83 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x34C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA84 + BSEC_OTP_DATA84 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x350 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA85 + BSEC_OTP_DATA85 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x354 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA86 + BSEC_OTP_DATA86 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x358 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA87 + BSEC_OTP_DATA87 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x35C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA88 + BSEC_OTP_DATA88 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x360 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA89 + BSEC_OTP_DATA89 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x364 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA90 + BSEC_OTP_DATA90 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x368 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA91 + BSEC_OTP_DATA91 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x36C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA92 + BSEC_OTP_DATA92 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x370 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA93 + BSEC_OTP_DATA93 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x374 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA94 + BSEC_OTP_DATA94 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x378 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_OTP_DATA95 + BSEC_OTP_DATA95 + Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. + 0x37C + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + BSEC_HWCFGR + BSEC_HWCFGR + BSEC hardware configuration register + 0xFF0 + 0x20 + read-only + 0x00000014 + + + SIZE + SIZE + 0 + 4 + + + ECC_USE + ECC_USE + 4 + 4 + + + + + BSEC_VERR + BSEC_VERR + BSEC version register + 0xFF4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + BSEC_IPIDR + BSEC_IPIDR + BSEC identification register + 0xFF8 + 0x20 + read-only + 0x00100032 + + + ID + ID + 0 + 32 + + + + + BSEC_SIDR + BSEC_SIDR + BSEC size identification register + 0xFFC + 0x20 + read-only + 0xA3C5DD04 + + + SID + SID + 0 + 32 + + + + + + + DCMI + DCMI + DCMI + 0x4C006000 + + 0x0 + 0x400 + registers + + + + DCMI_CR + DCMI_CR + DCMI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CAPTURE + CAPTURE + 0 + 1 + + + CM + CM + 1 + 1 + + + CROP + CROP + 2 + 1 + + + JPEG + JPEG + 3 + 1 + + + ESS + ESS + 4 + 1 + + + PCKPOL + PCKPOL + 5 + 1 + + + HSPOL + HSPOL + 6 + 1 + + + VSPOL + VSPOL + 7 + 1 + + + FCRC + FCRC + 8 + 2 + + + EDM + EDM + 10 + 2 + + + ENABLE + ENABLE + 14 + 1 + + + BSM + BSM + 16 + 2 + + + OEBS + OEBS + 18 + 1 + + + LSM + LSM + 19 + 1 + + + OELS + OELS + 20 + 1 + + + + + DCMI_SR + DCMI_SR + DCMI status register + 0x4 + 0x20 + read-only + 0x00000000 + + + HSYNC + HSYNC + 0 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + FNE + FNE + 2 + 1 + + + + + DCMI_RIS + DCMI_RIS + DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. + 0x8 + 0x20 + read-only + 0x00000000 + + + FRAME_RIS + FRAME_RIS + 0 + 1 + + + OVR_RIS + OVR_RIS + 1 + 1 + + + ERR_RIS + ERR_RIS + 2 + 1 + + + VSYNC_RIS + VSYNC_RIS + 3 + 1 + + + LINE_RIS + LINE_RIS + 4 + 1 + + + + + DCMI_IER + DCMI_IER + The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. + 0xC + 0x20 + read-write + 0x00000000 + + + FRAME_IE + FRAME_IE + 0 + 1 + + + OVR_IE + OVR_IE + 1 + 1 + + + ERR_IE + ERR_IE + 2 + 1 + + + VSYNC_IE + VSYNC_IE + 3 + 1 + + + LINE_IE + LINE_IE + 4 + 1 + + + + + DCMI_MIS + DCMI_MIS + This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. + 0x10 + 0x20 + read-only + 0x00000000 + + + FRAME_MIS + FRAME_MIS + 0 + 1 + + + OVR_MIS + OVR_MIS + 1 + 1 + + + ERR_MIS + ERR_MIS + 2 + 1 + + + VSYNC_MIS + VSYNC_MIS + 3 + 1 + + + LINE_MIS + LINE_MIS + 4 + 1 + + + + + DCMI_ICR + DCMI_ICR + The DCMI_ICR register is write-only. + 0x14 + 0x20 + write-only + 0x00000000 + + + FRAME_ISC + FRAME_ISC + 0 + 1 + + + OVR_ISC + OVR_ISC + 1 + 1 + + + ERR_ISC + ERR_ISC + 2 + 1 + + + VSYNC_ISC + VSYNC_ISC + 3 + 1 + + + LINE_ISC + LINE_ISC + 4 + 1 + + + + + DCMI_ESCR + DCMI_ESCR + DCMI embedded synchronization code register + 0x18 + 0x20 + read-write + 0x00000000 + + + FSC + FSC + 0 + 8 + + + LSC + LSC + 8 + 8 + + + LEC + LEC + 16 + 8 + + + FEC + FEC + 24 + 8 + + + + + DCMI_ESUR + DCMI_ESUR + DCMI embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x00000000 + + + FSU + FSU + 0 + 8 + + + LSU + LSU + 8 + 8 + + + LEU + LEU + 16 + 8 + + + FEU + FEU + 24 + 8 + + + + + DCMI_CWSTRT + DCMI_CWSTRT + DCMI crop window start + 0x20 + 0x20 + read-write + 0x00000000 + + + HOFFCNT + HOFFCNT + 0 + 14 + + + VST + VST + 16 + 13 + + + + + DCMI_CWSIZE + DCMI_CWSIZE + DCMI crop window size + 0x24 + 0x20 + read-write + 0x00000000 + + + CAPCNT + CAPCNT + 0 + 14 + + + VLINE + VLINE + 16 + 14 + + + + + DCMI_DR + DCMI_DR + DCMI data register + 0x28 + 0x20 + read-only + 0x00000000 + + + Byte0 + Byte0 + 0 + 8 + + + Byte1 + Byte1 + 8 + 8 + + + Byte2 + Byte2 + 16 + 8 + + + Byte3 + Byte3 + 24 + 8 + + + + + + + CRYP1 + CRYP1 + CRYP1 + 0x54001000 + + 0x0 + 0x400 + registers + + + + CRYP_CR + CRYP_CR + CRYP control register + 0x0 + 0x20 + 0x00000000 + + + ALGODIR + ALGODIR + 2 + 1 + read-write + + + ALGOMODE + ALGOMODE + 3 + 3 + read-write + + + DATATYPE + DATATYPE + 6 + 2 + read-write + + + KEYSIZE + KEYSIZE + 8 + 2 + read-write + + + FFLUSH + FFLUSH + 14 + 1 + write-only + + + CRYPEN + CRYPEN + 15 + 1 + read-write + + + GCM_CCMPH + GCM_CCMPH + 16 + 2 + read-write + + + ALGOMODE3 + ALGOMODE3 + 19 + 1 + read-write + + + NPBLB + NPBLB + 20 + 4 + read-write + + + + + CRYP_SR + CRYP_SR + CRYP status register + 0x4 + 0x20 + read-only + 0x00000003 + + + IFEM + IFEM + 0 + 1 + + + IFNF + IFNF + 1 + 1 + + + OFNE + OFNE + 2 + 1 + + + OFFU + OFFU + 3 + 1 + + + BUSY + BUSY + 4 + 1 + + + + + CRYP_DIN + CRYP_DIN + The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. + 0x8 + 0x20 + read-write + 0x00000000 + + + DATAIN + DATAIN + 0 + 32 + + + + + CRYP_DOUT + CRYP_DOUT + The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. + 0xC + 0x20 + read-only + 0x00000000 + + + DATAOUT + DATAOUT + 0 + 32 + + + + + CRYP_DMACR + CRYP_DMACR + CRYP DMA control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DIEN + DIEN + 0 + 1 + + + DOEN + DOEN + 1 + 1 + + + + + CRYP_IMSCR + CRYP_IMSCR + The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. + 0x14 + 0x20 + read-write + 0x00000000 + + + INIM + INIM + 0 + 1 + + + OUTIM + OUTIM + 1 + 1 + + + + + CRYP_RISR + CRYP_RISR + The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. + 0x18 + 0x20 + read-only + 0x00000001 + + + INRIS + INRIS + 0 + 1 + + + OUTRIS + OUTRIS + 1 + 1 + + + + + CRYP_MISR + CRYP_MISR + The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. + 0x1C + 0x20 + read-only + 0x00000000 + + + INMIS + INMIS + 0 + 1 + + + OUTMIS + OUTMIS + 1 + 1 + + + + + CRYP_K0LR + CRYP_K0LR + CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) + 0x20 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K0RR + CRYP_K0RR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x24 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K1LR + CRYP_K1LR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x28 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K1RR + CRYP_K1RR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x2C + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K2LR + CRYP_K2LR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x30 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K2RR + CRYP_K2RR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x34 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K3LR + CRYP_K3LR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x38 + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_K3RR + CRYP_K3RR + Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. + 0x3C + 0x20 + write-only + 0x00000000 + + + K + K + 0 + 32 + + + + + CRYP_IV0LR + CRYP_IV0LR + The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). + 0x40 + 0x20 + read-write + 0x00000000 + + + IV31 + IV31 + 0 + 1 + + + IV30 + IV30 + 1 + 1 + + + IV29 + IV29 + 2 + 1 + + + IV28 + IV28 + 3 + 1 + + + IV27 + IV27 + 4 + 1 + + + IV26 + IV26 + 5 + 1 + + + IV25 + IV25 + 6 + 1 + + + IV24 + IV24 + 7 + 1 + + + IV23 + IV23 + 8 + 1 + + + IV22 + IV22 + 9 + 1 + + + IV21 + IV21 + 10 + 1 + + + IV20 + IV20 + 11 + 1 + + + IV19 + IV19 + 12 + 1 + + + IV18 + IV18 + 13 + 1 + + + IV17 + IV17 + 14 + 1 + + + IV16 + IV16 + 15 + 1 + + + IV15 + IV15 + 16 + 1 + + + IV14 + IV14 + 17 + 1 + + + IV13 + IV13 + 18 + 1 + + + IV12 + IV12 + 19 + 1 + + + IV11 + IV11 + 20 + 1 + + + IV10 + IV10 + 21 + 1 + + + IV9 + IV9 + 22 + 1 + + + IV8 + IV8 + 23 + 1 + + + IV7 + IV7 + 24 + 1 + + + IV6 + IV6 + 25 + 1 + + + IV5 + IV5 + 26 + 1 + + + IV4 + IV4 + 27 + 1 + + + IV3 + IV3 + 28 + 1 + + + IV2 + IV2 + 29 + 1 + + + IV1 + IV1 + 30 + 1 + + + IV0 + IV0 + 31 + 1 + + + + + CRYP_IV0RR + CRYP_IV0RR + Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. + 0x44 + 0x20 + read-write + 0x00000000 + + + IV63 + IV63 + 0 + 1 + + + IV62 + IV62 + 1 + 1 + + + IV61 + IV61 + 2 + 1 + + + IV60 + IV60 + 3 + 1 + + + IV59 + IV59 + 4 + 1 + + + IV58 + IV58 + 5 + 1 + + + IV57 + IV57 + 6 + 1 + + + IV56 + IV56 + 7 + 1 + + + IV55 + IV55 + 8 + 1 + + + IV54 + IV54 + 9 + 1 + + + IV53 + IV53 + 10 + 1 + + + IV52 + IV52 + 11 + 1 + + + IV51 + IV51 + 12 + 1 + + + IV50 + IV50 + 13 + 1 + + + IV49 + IV49 + 14 + 1 + + + IV48 + IV48 + 15 + 1 + + + IV47 + IV47 + 16 + 1 + + + IV46 + IV46 + 17 + 1 + + + IV45 + IV45 + 18 + 1 + + + IV44 + IV44 + 19 + 1 + + + IV43 + IV43 + 20 + 1 + + + IV42 + IV42 + 21 + 1 + + + IV41 + IV41 + 22 + 1 + + + IV40 + IV40 + 23 + 1 + + + IV39 + IV39 + 24 + 1 + + + IV38 + IV38 + 25 + 1 + + + IV37 + IV37 + 26 + 1 + + + IV36 + IV36 + 27 + 1 + + + IV35 + IV35 + 28 + 1 + + + IV34 + IV34 + 29 + 1 + + + IV33 + IV33 + 30 + 1 + + + IV32 + IV32 + 31 + 1 + + + + + CRYP_IV1LR + CRYP_IV1LR + Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. + 0x48 + 0x20 + read-write + 0x00000000 + + + IV95 + IV95 + 0 + 1 + + + IV94 + IV94 + 1 + 1 + + + IV93 + IV93 + 2 + 1 + + + IV92 + IV92 + 3 + 1 + + + IV91 + IV91 + 4 + 1 + + + IV90 + IV90 + 5 + 1 + + + IV89 + IV89 + 6 + 1 + + + IV88 + IV88 + 7 + 1 + + + IV87 + IV87 + 8 + 1 + + + IV86 + IV86 + 9 + 1 + + + IV85 + IV85 + 10 + 1 + + + IV84 + IV84 + 11 + 1 + + + IV83 + IV83 + 12 + 1 + + + IV82 + IV82 + 13 + 1 + + + IV81 + IV81 + 14 + 1 + + + IV80 + IV80 + 15 + 1 + + + IV79 + IV79 + 16 + 1 + + + IV78 + IV78 + 17 + 1 + + + IV77 + IV77 + 18 + 1 + + + IV76 + IV76 + 19 + 1 + + + IV75 + IV75 + 20 + 1 + + + IV74 + IV74 + 21 + 1 + + + IV73 + IV73 + 22 + 1 + + + IV72 + IV72 + 23 + 1 + + + IV71 + IV71 + 24 + 1 + + + IV70 + IV70 + 25 + 1 + + + IV69 + IV69 + 26 + 1 + + + IV68 + IV68 + 27 + 1 + + + IV67 + IV67 + 28 + 1 + + + IV66 + IV66 + 29 + 1 + + + IV65 + IV65 + 30 + 1 + + + IV64 + IV64 + 31 + 1 + + + + + CRYP_IV1RR + CRYP_IV1RR + Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. + 0x4C + 0x20 + read-write + 0x00000000 + + + IV127 + IV127 + 0 + 1 + + + IV126 + IV126 + 1 + 1 + + + IV125 + IV125 + 2 + 1 + + + IV124 + IV124 + 3 + 1 + + + IV123 + IV123 + 4 + 1 + + + IV122 + IV122 + 5 + 1 + + + IV121 + IV121 + 6 + 1 + + + IV120 + IV120 + 7 + 1 + + + IV119 + IV119 + 8 + 1 + + + IV118 + IV118 + 9 + 1 + + + IV117 + IV117 + 10 + 1 + + + IV116 + IV116 + 11 + 1 + + + IV115 + IV115 + 12 + 1 + + + IV114 + IV114 + 13 + 1 + + + IV113 + IV113 + 14 + 1 + + + IV112 + IV112 + 15 + 1 + + + IV111 + IV111 + 16 + 1 + + + IV110 + IV110 + 17 + 1 + + + IV109 + IV109 + 18 + 1 + + + IV108 + IV108 + 19 + 1 + + + IV107 + IV107 + 20 + 1 + + + IV106 + IV106 + 21 + 1 + + + IV105 + IV105 + 22 + 1 + + + IV104 + IV104 + 23 + 1 + + + IV103 + IV103 + 24 + 1 + + + IV102 + IV102 + 25 + 1 + + + IV101 + IV101 + 26 + 1 + + + IV100 + IV100 + 27 + 1 + + + IV99 + IV99 + 28 + 1 + + + IV98 + IV98 + 29 + 1 + + + IV97 + IV97 + 30 + 1 + + + IV96 + IV96 + 31 + 1 + + + + + CRYP_CSGCMCCM0R + CRYP_CSGCMCCM0R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x50 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM0 + CSGCMCCM0 + 0 + 32 + + + + + CRYP_CSGCMCCM1R + CRYP_CSGCMCCM1R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x54 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM1 + CSGCMCCM1 + 0 + 32 + + + + + CRYP_CSGCMCCM2R + CRYP_CSGCMCCM2R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x58 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM2 + CSGCMCCM2 + 0 + 32 + + + + + CRYP_CSGCMCCM3R + CRYP_CSGCMCCM3R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x5C + 0x20 + read-write + 0x00000000 + + + CSGCMCCM3 + CSGCMCCM3 + 0 + 32 + + + + + CRYP_CSGCMCCM4R + CRYP_CSGCMCCM4R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x60 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM4 + CSGCMCCM4 + 0 + 32 + + + + + CRYP_CSGCMCCM5R + CRYP_CSGCMCCM5R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x64 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM5 + CSGCMCCM5 + 0 + 32 + + + + + CRYP_CSGCMCCM6R + CRYP_CSGCMCCM6R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x68 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM6 + CSGCMCCM6 + 0 + 32 + + + + + CRYP_CSGCMCCM7R + CRYP_CSGCMCCM7R + These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. + 0x6C + 0x20 + read-write + 0x00000000 + + + CSGCMCCM7 + CSGCMCCM7 + 0 + 32 + + + + + CRYP_CSGCM0R + CRYP_CSGCM0R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x70 + 0x20 + read-write + 0x00000000 + + + CSGCM0 + CSGCM0 + 0 + 32 + + + + + CRYP_CSGCM1R + CRYP_CSGCM1R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x74 + 0x20 + read-write + 0x00000000 + + + CSGCM1 + CSGCM1 + 0 + 32 + + + + + CRYP_CSGCM2R + CRYP_CSGCM2R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x78 + 0x20 + read-write + 0x00000000 + + + CSGCM2 + CSGCM2 + 0 + 32 + + + + + CRYP_CSGCM3R + CRYP_CSGCM3R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x7C + 0x20 + read-write + 0x00000000 + + + CSGCM3 + CSGCM3 + 0 + 32 + + + + + CRYP_CSGCM4R + CRYP_CSGCM4R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x80 + 0x20 + read-write + 0x00000000 + + + CSGCM4 + CSGCM4 + 0 + 32 + + + + + CRYP_CSGCM5R + CRYP_CSGCM5R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x84 + 0x20 + read-write + 0x00000000 + + + CSGCM5 + CSGCM5 + 0 + 32 + + + + + CRYP_CSGCM6R + CRYP_CSGCM6R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x88 + 0x20 + read-write + 0x00000000 + + + CSGCM6 + CSGCM6 + 0 + 32 + + + + + CRYP_CSGCM7R + CRYP_CSGCM7R + Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. + 0x8C + 0x20 + read-write + 0x00000000 + + + CSGCM7 + CSGCM7 + 0 + 32 + + + + + CRYP_HWCFGR + CRYP_HWCFGR + CRYP hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000131 + + + CFG1 + CFG1 + 0 + 4 + + + CFG2 + CFG2 + 4 + 4 + + + CFG3 + CFG3 + 8 + 4 + + + CFG4 + CFG4 + 12 + 4 + + + + + CRYP_VERR + CRYP_VERR + CRYP HW Version Register + 0x3F4 + 0x20 + read-only + 0x00000022 + + + VER + VER + 0 + 8 + + + + + CRYP_IPIDR + CRYP_IPIDR + CRYP Identification + 0x3F8 + 0x20 + read-only + 0x00170011 + + + ID + ID + 0 + 32 + + + + + CRYP_MID + CRYP_MID + CRYP HW Magic ID + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + MID + MID + 0 + 32 + + + + + + + CRYP2 + 0x4C005000 + + + DAC1 + DAC1 + DAC1 + 0x40017000 + + 0x0 + 0x400 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + EN1 + 0 + 1 + + + TEN1 + TEN1 + 1 + 1 + + + TSEL10 + TSEL10 + 2 + 1 + + + TSEL11 + TSEL11 + 3 + 1 + + + TSEL12 + TSEL12 + 4 + 1 + + + TSEL13 + TSEL13 + 5 + 1 + + + WAVE1 + WAVE1 + 6 + 2 + + + MAMP1 + MAMP1 + 8 + 4 + + + DMAEN1 + DMAEN1 + 12 + 1 + + + DMAUDRIE1 + DMAUDRIE1 + 13 + 1 + + + CEN1 + CEN1 + 14 + 1 + + + HFSEL + HFSEL + 15 + 1 + + + EN2 + EN2 + 16 + 1 + + + TEN2 + TEN2 + 17 + 1 + + + TSEL20 + TSEL20 + 18 + 1 + + + TSEL21 + TSEL21 + 19 + 1 + + + TSEL22 + TSEL22 + 20 + 1 + + + TSEL23 + TSEL23 + 21 + 1 + + + WAVE2 + WAVE2 + 22 + 2 + + + MAMP2 + MAMP2 + 24 + 4 + + + DMAEN2 + DMAEN2 + 28 + 1 + + + DMAUDRIE2 + DMAUDRIE2 + 29 + 1 + + + CEN2 + CEN2 + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + SWTRIG1 + 0 + 1 + + + SWTRIG2 + SWTRIG2 + 1 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 0 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 4 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 0 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DACC2DHR + 0 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DACC2DHR + 4 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DACC2DHR + 0 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 0 + 12 + + + DACC2DHR + DACC2DHR + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + Dual DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 4 + 12 + + + DACC2DHR + DACC2DHR + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + Dual DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DACC1DHR + 0 + 8 + + + DACC2DHR + DACC2DHR + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DACC1DOR + 0 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DACC2DOR + 0 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DMAUDR1 + 13 + 1 + read-write + + + CAL_FLAG1 + CAL_FLAG1 + 14 + 1 + read-only + + + BWST1 + BWST1 + 15 + 1 + read-only + + + DMAUDR2 + DMAUDR2 + 29 + 1 + read-write + + + CAL_FLAG2 + CAL_FLAG2 + 30 + 1 + read-only + + + BWST2 + BWST2 + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + OTRIM1 + 0 + 5 + + + OTRIM2 + OTRIM2 + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + MODE1 + 0 + 3 + + + MODE2 + MODE2 + 16 + 3 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel 1 sample and hold sample time register + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + TSAMPLE1 + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + TSAMPLE2 + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + THOLD1 + 0 + 10 + + + THOLD2 + THOLD2 + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + TREFRESH1 + 0 + 8 + + + TREFRESH2 + TREFRESH2 + 16 + 8 + + + + + DAC_HWCFGR0 + DAC_HWCFGR0 + DAC IP hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00001111 + + + DUAL + DUAL + 0 + 4 + + + LFSR + LFSR + 4 + 4 + + + TRIANGLE + TRIANGLE + 8 + 4 + + + SAMPLE + SAMPLE + 12 + 4 + + + OR_CFG + OR_CFG + 16 + 8 + + + + + DAC_VERR + DAC_VERR + No + 0x3F4 + 0x20 + read-only + 0x00000031 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DAC_IPIDR + DAC_IPIDR + No + 0x3F8 + 0x20 + read-only + 0x00110011 + + + ID + ID + 0 + 32 + + + + + DAC_SIDR + DAC_SIDR + No + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DDRCTRL + DDRCTRL + DDRCTRL + 0x5A003000 + + 0x0 + 0x1000 + registers + + + + DDRCTRL_MSTR + DDRCTRL_MSTR + DDRCTRL master register 0 + 0x0 + 0x20 + read-write + 0x00040001 + + + DDR3 + DDR3 + 0 + 1 + + + LPDDR2 + LPDDR2 + 2 + 1 + + + LPDDR3 + LPDDR3 + 3 + 1 + + + BURSTCHOP + BURSTCHOP + 9 + 1 + + + EN_2T_TIMING_MODE + EN_2T_TIMING_MODE + 10 + 1 + + + DATA_BUS_WIDTH + DATA_BUS_WIDTH + 12 + 2 + + + DLL_OFF_MODE + DLL_OFF_MODE + 15 + 1 + + + BURST_RDWR + BURST_RDWR + 16 + 4 + + + + + DDRCTRL_STAT + DDRCTRL_STAT + DDRCTRL operating mode status register + 0x4 + 0x20 + read-only + 0x00000000 + + + OPERATING_MODE + OPERATING_MODE + 0 + 3 + + + SELFREF_TYPE + SELFREF_TYPE + 4 + 2 + + + SELFREF_CAM_NOT_EMPTY + SELFREF_CAM_NOT_EMPTY + 12 + 1 + + + + + DDRCTRL_MRCTRL0 + DDRCTRL_MRCTRL0 + Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en + 0x10 + 0x20 + read-write + 0x00000010 + + + MR_TYPE + MR_TYPE + 0 + 1 + + + MR_RANK + MR_RANK + 4 + 1 + + + MR_ADDR + MR_ADDR + 12 + 4 + + + MR_WR + MR_WR + 31 + 1 + + + + + DDRCTRL_MRCTRL1 + DDRCTRL_MRCTRL1 + DDRCTRL mode register read/write control register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + MR_DATA + MR_DATA + 0 + 16 + + + + + DDRCTRL_MRSTAT + DDRCTRL_MRSTAT + DDRCTRL mode register read/write status register + 0x18 + 0x20 + read-only + 0x00000000 + + + MR_WR_BUSY + MR_WR_BUSY + 0 + 1 + + + + + DDRCTRL_DERATEEN + DDRCTRL_DERATEEN + DDRCTRL temperature derate enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DERATE_ENABLE + DERATE_ENABLE + 0 + 1 + + + DERATE_VALUE + DERATE_VALUE + 1 + 2 + + + DERATE_BYTE + DERATE_BYTE + 4 + 4 + + + + + DDRCTRL_DERATEINT + DDRCTRL_DERATEINT + DDRCTRL temperature derate interval register + 0x24 + 0x20 + read-write + 0x00800000 + + + MR4_READ_INTERVAL + MR4_READ_INTERVAL + 0 + 32 + + + + + DDRCTRL_PWRCTL + DDRCTRL_PWRCTL + DDRCTRL low power control register + 0x30 + 0x20 + read-write + 0x00000000 + + + SELFREF_EN + SELFREF_EN + 0 + 1 + + + POWERDOWN_EN + POWERDOWN_EN + 1 + 1 + + + DEEPPOWERDOWN_EN + DEEPPOWERDOWN_EN + 2 + 1 + + + EN_DFI_DRAM_CLK_DISABLE + EN_DFI_DRAM_CLK_DISABLE + 3 + 1 + + + SELFREF_SW + SELFREF_SW + 5 + 1 + + + DIS_CAM_DRAIN_SELFREF + DIS_CAM_DRAIN_SELFREF + 7 + 1 + + + + + DDRCTRL_PWRTMG + DDRCTRL_PWRTMG + DDRCTRL low power timing register + 0x34 + 0x20 + read-write + 0x00402010 + + + POWERDOWN_TO_X32 + POWERDOWN_TO_X32 + 0 + 5 + + + T_DPD_X4096 + T_DPD_X4096 + 8 + 8 + + + SELFREF_TO_X32 + SELFREF_TO_X32 + 16 + 8 + + + + + DDRCTRL_HWLPCTL + DDRCTRL_HWLPCTL + DDRCTRL hardware low power control register + 0x38 + 0x20 + read-write + 0x00000003 + + + HW_LP_EN + HW_LP_EN + 0 + 1 + + + HW_LP_EXIT_IDLE_EN + HW_LP_EXIT_IDLE_EN + 1 + 1 + + + HW_LP_IDLE_X32 + HW_LP_IDLE_X32 + 16 + 12 + + + + + DDRCTRL_RFSHCTL0 + DDRCTRL_RFSHCTL0 + DDRCTRL refresh control register 0 + 0x50 + 0x20 + read-write + 0x00210000 + + + PER_BANK_REFRESH + PER_BANK_REFRESH + 2 + 1 + + + REFRESH_BURST + REFRESH_BURST + 4 + 5 + + + REFRESH_TO_X32 + REFRESH_TO_X32 + 12 + 5 + + + REFRESH_MARGIN + REFRESH_MARGIN + 20 + 4 + + + + + DDRCTRL_RFSHCTL3 + DDRCTRL_RFSHCTL3 + DDRCTRL refresh control register 3 + 0x60 + 0x20 + read-write + 0x00000000 + + + DIS_AUTO_REFRESH + DIS_AUTO_REFRESH + 0 + 1 + + + REFRESH_UPDATE_LEVEL + REFRESH_UPDATE_LEVEL + 1 + 1 + + + + + DDRCTRL_RFSHTMG + DDRCTRL_RFSHTMG + DDRCTRL refresh timing register + 0x64 + 0x20 + read-write + 0x0062008C + + + T_RFC_MIN + T_RFC_MIN + 0 + 10 + + + LPDDR3_TREFBW_EN + LPDDR3_TREFBW_EN + 15 + 1 + + + T_RFC_NOM_X1_X32 + T_RFC_NOM_X1_X32 + 16 + 12 + + + T_RFC_NOM_X1_SEL + T_RFC_NOM_X1_SEL + 31 + 1 + + + + + DDRCTRL_CRCPARCTL0 + DDRCTRL_CRCPARCTL0 + DDRCTRL CRC parity control register 0 + 0xC0 + 0x20 + read-write + 0x00000000 + + + DFI_ALERT_ERR_INT_EN + DFI_ALERT_ERR_INT_EN + 0 + 1 + + + DFI_ALERT_ERR_INT_CLR + DFI_ALERT_ERR_INT_CLR + 1 + 1 + + + DFI_ALERT_ERR_CNT_CLR + DFI_ALERT_ERR_CNT_CLR + 2 + 1 + + + + + DDRCTRL_CRCPARSTAT + DDRCTRL_CRCPARSTAT + DDRCTRL CRC parity status register + 0xCC + 0x20 + read-only + 0x00000000 + + + DFI_ALERT_ERR_CNT + DFI_ALERT_ERR_CNT + 0 + 16 + + + DFI_ALERT_ERR_INT + DFI_ALERT_ERR_INT + 16 + 1 + + + + + DDRCTRL_INIT0 + DDRCTRL_INIT0 + DDRCTRL SDRAM initialization register 0 + 0xD0 + 0x20 + read-write + 0x0002004E + + + PRE_CKE_X1024 + PRE_CKE_X1024 + 0 + 12 + + + POST_CKE_X1024 + POST_CKE_X1024 + 16 + 10 + + + SKIP_DRAM_INIT + SKIP_DRAM_INIT + 30 + 2 + + + + + DDRCTRL_INIT1 + DDRCTRL_INIT1 + DDRCTRL SDRAM initialization register 1 + 0xD4 + 0x20 + read-write + 0x00000000 + + + PRE_OCD_X32 + PRE_OCD_X32 + 0 + 4 + + + DRAM_RSTN_X1024 + DRAM_RSTN_X1024 + 16 + 9 + + + + + DDRCTRL_INIT2 + DDRCTRL_INIT2 + DDRCTRL SDRAM initialization register 2 + 0xD8 + 0x20 + read-write + 0x00000D05 + + + MIN_STABLE_CLOCK_X1 + MIN_STABLE_CLOCK_X1 + 0 + 4 + + + IDLE_AFTER_RESET_X32 + IDLE_AFTER_RESET_X32 + 8 + 8 + + + + + DDRCTRL_INIT3 + DDRCTRL_INIT3 + DDRCTRL SDRAM initialization register 3 + 0xDC + 0x20 + read-write + 0x00000510 + + + EMR + EMR + 0 + 16 + + + MR + MR + 16 + 16 + + + + + DDRCTRL_INIT4 + DDRCTRL_INIT4 + DDRCTRL SDRAM initialization register 4 + 0xE0 + 0x20 + read-write + 0x00000000 + + + EMR3 + EMR3 + 0 + 16 + + + EMR2 + EMR2 + 16 + 16 + + + + + DDRCTRL_INIT5 + DDRCTRL_INIT5 + DDRCTRL SDRAM initialization register 5 + 0xE4 + 0x20 + read-write + 0x00100004 + + + MAX_AUTO_INIT_X1024 + MAX_AUTO_INIT_X1024 + 0 + 10 + + + DEV_ZQINIT_X32 + DEV_ZQINIT_X32 + 16 + 8 + + + + + DDRCTRL_DIMMCTL + DDRCTRL_DIMMCTL + DDRCTRL DIMM control register + 0xF0 + 0x20 + read-write + 0x00000000 + + + DIMM_STAGGER_CS_EN + DIMM_STAGGER_CS_EN + 0 + 1 + + + DIMM_ADDR_MIRR_EN + DIMM_ADDR_MIRR_EN + 1 + 1 + + + + + DDRCTRL_DRAMTMG0 + DDRCTRL_DRAMTMG0 + DDRCTRL SDRAM timing register 0 + 0x100 + 0x20 + read-write + 0x0F101B0F + + + T_RAS_MIN + T_RAS_MIN + 0 + 6 + + + T_RAS_MAX + T_RAS_MAX + 8 + 7 + + + T_FAW + T_FAW + 16 + 6 + + + WR2PRE + WR2PRE + 24 + 7 + + + + + DDRCTRL_DRAMTMG1 + DDRCTRL_DRAMTMG1 + DDRCTRL SDRAM timing register 1 + 0x104 + 0x20 + read-write + 0x00080414 + + + T_RC + T_RC + 0 + 7 + + + RD2PRE + RD2PRE + 8 + 6 + + + T_XP + T_XP + 16 + 5 + + + + + DDRCTRL_DRAMTMG2 + DDRCTRL_DRAMTMG2 + DDRCTRL SDRAM timing register 2 + 0x108 + 0x20 + read-write + 0x0305060D + + + WR2RD + WR2RD + 0 + 6 + + + RD2WR + RD2WR + 8 + 6 + + + READ_LATENCY + READ_LATENCY + 16 + 6 + + + WRITE_LATENCY + WRITE_LATENCY + 24 + 6 + + + + + DDRCTRL_DRAMTMG3 + DDRCTRL_DRAMTMG3 + DDRCTRL SDRAM timing register 3 + 0x10C + 0x20 + read-write + 0x0050400C + + + T_MOD + T_MOD + 0 + 10 + + + T_MRD + T_MRD + 12 + 6 + + + T_MRW + T_MRW + 20 + 10 + + + + + DDRCTRL_DRAMTMG4 + DDRCTRL_DRAMTMG4 + DDRCTRL SDRAM timing register 4 + 0x110 + 0x20 + read-write + 0x05040405 + + + T_RP + T_RP + 0 + 5 + + + T_RRD + T_RRD + 8 + 4 + + + T_CCD + T_CCD + 16 + 4 + + + T_RCD + T_RCD + 24 + 5 + + + + + DDRCTRL_DRAMTMG5 + DDRCTRL_DRAMTMG5 + DDRCTRL SDRAM timing register 5 + 0x114 + 0x20 + read-write + 0x05050403 + + + T_CKE + T_CKE + 0 + 5 + + + T_CKESR + T_CKESR + 8 + 6 + + + T_CKSRE + T_CKSRE + 16 + 4 + + + T_CKSRX + T_CKSRX + 24 + 4 + + + + + DDRCTRL_DRAMTMG6 + DDRCTRL_DRAMTMG6 + DDRCTRL SDRAM timing register 6 + 0x118 + 0x20 + read-write + 0x02020005 + + + T_CKCSX + T_CKCSX + 0 + 4 + + + T_CKDPDX + T_CKDPDX + 16 + 4 + + + T_CKDPDE + T_CKDPDE + 24 + 4 + + + + + DDRCTRL_DRAMTMG7 + DDRCTRL_DRAMTMG7 + DDRCTRL SDRAM timing register 7 + 0x11C + 0x20 + read-write + 0x00000202 + + + T_CKPDX + T_CKPDX + 0 + 4 + + + T_CKPDE + T_CKPDE + 8 + 4 + + + + + DDRCTRL_DRAMTMG8 + DDRCTRL_DRAMTMG8 + DDRCTRL SDRAM timing register 8 + 0x120 + 0x20 + read-write + 0x00004405 + + + T_XS_X32 + T_XS_X32 + 0 + 7 + + + T_XS_DLL_X32 + T_XS_DLL_X32 + 8 + 7 + + + + + DDRCTRL_DRAMTMG14 + DDRCTRL_DRAMTMG14 + DDRCTRL SDRAM timing register 14 + 0x138 + 0x20 + read-write + 0x000000A0 + + + T_XSR + T_XSR + 0 + 12 + + + + + DDRCTRL_DRAMTMG15 + DDRCTRL_DRAMTMG15 + DDRCTRL SDRAM timing register 15 + 0x13C + 0x20 + read-write + 0x00000000 + + + T_STAB_X32 + T_STAB_X32 + 0 + 8 + + + EN_DFI_LP_T_STAB + EN_DFI_LP_T_STAB + 31 + 1 + + + + + DDRCTRL_ZQCTL0 + DDRCTRL_ZQCTL0 + DDRCTRL ZQ control register 0 + 0x180 + 0x20 + read-write + 0x02000040 + + + T_ZQ_SHORT_NOP + T_ZQ_SHORT_NOP + 0 + 10 + + + T_ZQ_LONG_NOP + T_ZQ_LONG_NOP + 16 + 11 + + + ZQ_RESISTOR_SHARED + ZQ_RESISTOR_SHARED + 29 + 1 + + + DIS_SRX_ZQCL + DIS_SRX_ZQCL + 30 + 1 + + + DIS_AUTO_ZQ + DIS_AUTO_ZQ + 31 + 1 + + + + + DDRCTRL_ZQCTL1 + DDRCTRL_ZQCTL1 + DDRCTRL ZQ control register 1 + 0x184 + 0x20 + read-write + 0x02000100 + + + T_ZQ_SHORT_INTERVAL_X1024 + T_ZQ_SHORT_INTERVAL_X1024 + 0 + 20 + + + T_ZQ_RESET_NOP + T_ZQ_RESET_NOP + 20 + 10 + + + + + DDRCTRL_ZQCTL2 + DDRCTRL_ZQCTL2 + DDRCTRL ZQ control register 2 + 0x188 + 0x20 + read-write + 0x00000000 + + + ZQ_RESET + ZQ_RESET + 0 + 1 + + + + + DDRCTRL_ZQSTAT + DDRCTRL_ZQSTAT + DDRCTRL ZQ status register + 0x18C + 0x20 + read-only + 0x00000000 + + + ZQ_RESET_BUSY + ZQ_RESET_BUSY + 0 + 1 + + + + + DDRCTRL_DFITMG0 + DDRCTRL_DFITMG0 + DDRCTRL DFI timing register 0 + 0x190 + 0x20 + read-write + 0x07020002 + + + DFI_TPHY_WRLAT + DFI_TPHY_WRLAT + 0 + 6 + + + DFI_TPHY_WRDATA + DFI_TPHY_WRDATA + 8 + 6 + + + DFI_T_RDDATA_EN + DFI_T_RDDATA_EN + 16 + 7 + + + DFI_T_CTRL_DELAY + DFI_T_CTRL_DELAY + 24 + 5 + + + + + DDRCTRL_DFITMG1 + DDRCTRL_DFITMG1 + DDRCTRL DFI timing register 1 + 0x194 + 0x20 + read-write + 0x00000404 + + + DFI_T_DRAM_CLK_ENABLE + DFI_T_DRAM_CLK_ENABLE + 0 + 5 + + + DFI_T_DRAM_CLK_DISABLE + DFI_T_DRAM_CLK_DISABLE + 8 + 5 + + + DFI_T_WRDATA_DELAY + DFI_T_WRDATA_DELAY + 16 + 5 + + + + + DDRCTRL_DFILPCFG0 + DDRCTRL_DFILPCFG0 + DDRCTRL low power configuration register 0 + 0x198 + 0x20 + read-write + 0x07000000 + + + DFI_LP_EN_PD + DFI_LP_EN_PD + 0 + 1 + + + DFI_LP_WAKEUP_PD + DFI_LP_WAKEUP_PD + 4 + 4 + + + DFI_LP_EN_SR + DFI_LP_EN_SR + 8 + 1 + + + DFI_LP_WAKEUP_SR + DFI_LP_WAKEUP_SR + 12 + 4 + + + DFI_LP_EN_DPD + DFI_LP_EN_DPD + 16 + 1 + + + DFI_LP_WAKEUP_DPD + DFI_LP_WAKEUP_DPD + 20 + 4 + + + DFI_TLP_RESP + DFI_TLP_RESP + 24 + 5 + + + + + DDRCTRL_DFIUPD0 + DDRCTRL_DFIUPD0 + DDRCTRL DFI update register 0 + 0x1A0 + 0x20 + read-write + 0x00400003 + + + DFI_T_CTRLUP_MIN + DFI_T_CTRLUP_MIN + 0 + 10 + + + DFI_T_CTRLUP_MAX + DFI_T_CTRLUP_MAX + 16 + 10 + + + CTRLUPD_PRE_SRX + CTRLUPD_PRE_SRX + 29 + 1 + + + DIS_AUTO_CTRLUPD_SRX + DIS_AUTO_CTRLUPD_SRX + 30 + 1 + + + DIS_AUTO_CTRLUPD + DIS_AUTO_CTRLUPD + 31 + 1 + + + + + DDRCTRL_DFIUPD1 + DDRCTRL_DFIUPD1 + DDRCTRL DFI update register 1 + 0x1A4 + 0x20 + read-write + 0x00010001 + + + DFI_T_CTRLUPD_INTERVAL_MAX_X1024 + DFI_T_CTRLUPD_INTERVAL_MAX_X1024 + 0 + 8 + + + DFI_T_CTRLUPD_INTERVAL_MIN_X1024 + DFI_T_CTRLUPD_INTERVAL_MIN_X1024 + 16 + 8 + + + + + DDRCTRL_DFIUPD2 + DDRCTRL_DFIUPD2 + DDRCTRL DFI update register 2 + 0x1A8 + 0x20 + read-write + 0x80000000 + + + DFI_PHYUPD_EN + DFI_PHYUPD_EN + 31 + 1 + + + + + DDRCTRL_DFIMISC + DDRCTRL_DFIMISC + DDRCTRL DFI miscellaneous control register + 0x1B0 + 0x20 + read-write + 0x00000001 + + + DFI_INIT_COMPLETE_EN + DFI_INIT_COMPLETE_EN + 0 + 1 + + + CTL_IDLE_EN + CTL_IDLE_EN + 4 + 1 + + + DFI_INIT_START + DFI_INIT_START + 5 + 1 + + + DFI_FREQUENCY + DFI_FREQUENCY + 8 + 5 + + + + + DDRCTRL_DFISTAT + DDRCTRL_DFISTAT + DDRCTRL DFI status register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DFI_INIT_COMPLETE + DFI_INIT_COMPLETE + 0 + 1 + + + DFI_LP_ACK + DFI_LP_ACK + 1 + 1 + + + + + DDRCTRL_DFIPHYMSTR + DDRCTRL_DFIPHYMSTR + DDRCTRL DFI PHY master register + 0x1C4 + 0x20 + read-write + 0x00000001 + + + DFI_PHYMSTR_EN + DFI_PHYMSTR_EN + 0 + 1 + + + + + DDRCTRL_ADDRMAP1 + DDRCTRL_ADDRMAP1 + DDRCTRL address map register 1 + 0x204 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_BANK_B0 + ADDRMAP_BANK_B0 + 0 + 6 + + + ADDRMAP_BANK_B1 + ADDRMAP_BANK_B1 + 8 + 6 + + + ADDRMAP_BANK_B2 + ADDRMAP_BANK_B2 + 16 + 6 + + + + + DDRCTRL_ADDRMAP2 + DDRCTRL_ADDRMAP2 + DDRCTRL address map register 2 + 0x208 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_COL_B2 + ADDRMAP_COL_B2 + 0 + 4 + + + ADDRMAP_COL_B3 + ADDRMAP_COL_B3 + 8 + 4 + + + ADDRMAP_COL_B4 + ADDRMAP_COL_B4 + 16 + 4 + + + ADDRMAP_COL_B5 + ADDRMAP_COL_B5 + 24 + 4 + + + + + DDRCTRL_ADDRMAP3 + DDRCTRL_ADDRMAP3 + DDRCTRL address map register 3 + 0x20C + 0x20 + read-write + 0x00000000 + + + ADDRMAP_COL_B6 + ADDRMAP_COL_B6 + 0 + 4 + + + ADDRMAP_COL_B7 + ADDRMAP_COL_B7 + 8 + 5 + + + ADDRMAP_COL_B8 + ADDRMAP_COL_B8 + 16 + 5 + + + ADDRMAP_COL_B9 + ADDRMAP_COL_B9 + 24 + 5 + + + + + DDRCTRL_ADDRMAP4 + DDRCTRL_ADDRMAP4 + DDRCTRL address map register 4 + 0x210 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_COL_B10 + ADDRMAP_COL_B10 + 0 + 5 + + + ADDRMAP_COL_B11 + ADDRMAP_COL_B11 + 8 + 5 + + + + + DDRCTRL_ADDRMAP5 + DDRCTRL_ADDRMAP5 + DDRCTRL address map register 5 + 0x214 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_ROW_B0 + ADDRMAP_ROW_B0 + 0 + 4 + + + ADDRMAP_ROW_B1 + ADDRMAP_ROW_B1 + 8 + 4 + + + ADDRMAP_ROW_B2_10 + ADDRMAP_ROW_B2_10 + 16 + 4 + + + ADDRMAP_ROW_B11 + ADDRMAP_ROW_B11 + 24 + 4 + + + + + DDRCTRL_ADDRMAP6 + DDRCTRL_ADDRMAP6 + DDRCTRL address register 6 + 0x218 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_ROW_B12 + ADDRMAP_ROW_B12 + 0 + 4 + + + ADDRMAP_ROW_B13 + ADDRMAP_ROW_B13 + 8 + 4 + + + ADDRMAP_ROW_B14 + ADDRMAP_ROW_B14 + 16 + 4 + + + ADDRMAP_ROW_B15 + ADDRMAP_ROW_B15 + 24 + 4 + + + LPDDR3_6GB_12GB + LPDDR3_6GB_12GB + 31 + 1 + + + + + DDRCTRL_ADDRMAP9 + DDRCTRL_ADDRMAP9 + DDRCTRL address map register 9 + 0x224 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_ROW_B2 + ADDRMAP_ROW_B2 + 0 + 4 + + + ADDRMAP_ROW_B3 + ADDRMAP_ROW_B3 + 8 + 4 + + + ADDRMAP_ROW_B4 + ADDRMAP_ROW_B4 + 16 + 4 + + + ADDRMAP_ROW_B5 + ADDRMAP_ROW_B5 + 24 + 4 + + + + + DDRCTRL_ADDRMAP10 + DDRCTRL_ADDRMAP10 + DDRCTRL address map register 10 + 0x228 + 0x20 + read-write + 0x00000000 + + + ADDRMAP_ROW_B6 + ADDRMAP_ROW_B6 + 0 + 4 + + + ADDRMAP_ROW_B7 + ADDRMAP_ROW_B7 + 8 + 4 + + + ADDRMAP_ROW_B8 + ADDRMAP_ROW_B8 + 16 + 4 + + + ADDRMAP_ROW_B9 + ADDRMAP_ROW_B9 + 24 + 4 + + + + + DDRCTRL_ADDRMAP11 + DDRCTRL_ADDRMAP11 + DDRCTRL address map register 11 + 0x22C + 0x20 + read-write + 0x00000000 + + + ADDRMAP_ROW_B10 + ADDRMAP_ROW_B10 + 0 + 4 + + + + + DDRCTRL_ODTCFG + DDRCTRL_ODTCFG + DDRCTRL ODT configuration register + 0x240 + 0x20 + read-write + 0x04000400 + + + RD_ODT_DELAY + RD_ODT_DELAY + 2 + 5 + + + RD_ODT_HOLD + RD_ODT_HOLD + 8 + 4 + + + WR_ODT_DELAY + WR_ODT_DELAY + 16 + 5 + + + WR_ODT_HOLD + WR_ODT_HOLD + 24 + 4 + + + + + DDRCTRL_ODTMAP + DDRCTRL_ODTMAP + DDRCTRL ODT/Rank map register + 0x244 + 0x20 + read-write + 0x00000011 + + + RANK0_WR_ODT + RANK0_WR_ODT + 0 + 1 + + + RANK0_RD_ODT + RANK0_RD_ODT + 4 + 1 + + + + + DDRCTRL_SCHED + DDRCTRL_SCHED + DDRCTRL scheduler control register + 0x250 + 0x20 + read-write + 0x00000805 + + + FORCE_LOW_PRI_N + FORCE_LOW_PRI_N + 0 + 1 + + + PREFER_WRITE + PREFER_WRITE + 1 + 1 + + + PAGECLOSE + PAGECLOSE + 2 + 1 + + + LPR_NUM_ENTRIES + LPR_NUM_ENTRIES + 8 + 4 + + + GO2CRITICAL_HYSTERESIS + GO2CRITICAL_HYSTERESIS + 16 + 8 + + + RDWR_IDLE_GAP + RDWR_IDLE_GAP + 24 + 7 + + + + + DDRCTRL_SCHED1 + DDRCTRL_SCHED1 + DDRCTRL scheduler control register 1 + 0x254 + 0x20 + read-write + 0x00000000 + + + PAGECLOSE_TIMER + PAGECLOSE_TIMER + 0 + 8 + + + + + DDRCTRL_PERFHPR1 + DDRCTRL_PERFHPR1 + DDRCTRL high priority read CAM register 1 + 0x25C + 0x20 + read-write + 0x0F000001 + + + HPR_MAX_STARVE + HPR_MAX_STARVE + 0 + 16 + + + HPR_XACT_RUN_LENGTH + HPR_XACT_RUN_LENGTH + 24 + 8 + + + + + DDRCTRL_PERFLPR1 + DDRCTRL_PERFLPR1 + DDRCTRL low priority read CAM register 1 + 0x264 + 0x20 + read-write + 0x0F00007F + + + LPR_MAX_STARVE + LPR_MAX_STARVE + 0 + 16 + + + LPR_XACT_RUN_LENGTH + LPR_XACT_RUN_LENGTH + 24 + 8 + + + + + DDRCTRL_PERFWR1 + DDRCTRL_PERFWR1 + DDRCTRL write CAM register 1 + 0x26C + 0x20 + read-write + 0x0F00007F + + + W_MAX_STARVE + W_MAX_STARVE + 0 + 16 + + + W_XACT_RUN_LENGTH + W_XACT_RUN_LENGTH + 24 + 8 + + + + + DDRCTRL_DBG0 + DDRCTRL_DBG0 + DDRCTRL debug register 0 + 0x300 + 0x20 + read-write + 0x00000000 + + + DIS_WC + DIS_WC + 0 + 1 + + + DIS_COLLISION_PAGE_OPT + DIS_COLLISION_PAGE_OPT + 4 + 1 + + + + + DDRCTRL_DBG1 + DDRCTRL_DBG1 + DDRCTRL debug register 1 + 0x304 + 0x20 + read-write + 0x00000000 + + + DIS_DQ + DIS_DQ + 0 + 1 + + + DIS_HIF + DIS_HIF + 1 + 1 + + + + + DDRCTRL_DBGCAM + DDRCTRL_DBGCAM + DDRCTRL CAM debug register + 0x308 + 0x20 + read-only + 0x00000000 + + + DBG_HPR_Q_DEPTH + DBG_HPR_Q_DEPTH + 0 + 5 + + + DBG_LPR_Q_DEPTH + DBG_LPR_Q_DEPTH + 8 + 5 + + + DBG_W_Q_DEPTH + DBG_W_Q_DEPTH + 16 + 5 + + + DBG_STALL + DBG_STALL + 24 + 1 + + + DBG_RD_Q_EMPTY + DBG_RD_Q_EMPTY + 25 + 1 + + + DBG_WR_Q_EMPTY + DBG_WR_Q_EMPTY + 26 + 1 + + + RD_DATA_PIPELINE_EMPTY + RD_DATA_PIPELINE_EMPTY + 28 + 1 + + + WR_DATA_PIPELINE_EMPTY + WR_DATA_PIPELINE_EMPTY + 29 + 1 + + + + + DDRCTRL_DBGCMD + DDRCTRL_DBGCMD + DDRCTRL command debug register + 0x30C + 0x20 + read-write + 0x00000000 + + + RANK0_REFRESH + RANK0_REFRESH + 0 + 1 + + + ZQ_CALIB_SHORT + ZQ_CALIB_SHORT + 4 + 1 + + + CTRLUPD + CTRLUPD + 5 + 1 + + + + + DDRCTRL_DBGSTAT + DDRCTRL_DBGSTAT + DDRCTRL status debug register + 0x310 + 0x20 + read-only + 0x00000000 + + + RANK0_REFRESH_BUSY + RANK0_REFRESH_BUSY + 0 + 1 + + + ZQ_CALIB_SHORT_BUSY + ZQ_CALIB_SHORT_BUSY + 4 + 1 + + + CTRLUPD_BUSY + CTRLUPD_BUSY + 5 + 1 + + + + + DDRCTRL_SWCTL + DDRCTRL_SWCTL + DDRCTRL software register programming control enable + 0x320 + 0x20 + read-write + 0x00000001 + + + SW_DONE + SW_DONE + 0 + 1 + + + + + DDRCTRL_SWSTAT + DDRCTRL_SWSTAT + DDRCTRL software register programming control status + 0x324 + 0x20 + read-only + 0x00000001 + + + SW_DONE_ACK + SW_DONE_ACK + 0 + 1 + + + + + DDRCTRL_POISONCFG + DDRCTRL_POISONCFG + AXI Poison configuration register common for all AXI ports. + 0x36C + 0x20 + read-write + 0x00110011 + + + WR_POISON_SLVERR_EN + WR_POISON_SLVERR_EN + 0 + 1 + + + WR_POISON_INTR_EN + WR_POISON_INTR_EN + 4 + 1 + + + WR_POISON_INTR_CLR + WR_POISON_INTR_CLR + 8 + 1 + + + RD_POISON_SLVERR_EN + RD_POISON_SLVERR_EN + 16 + 1 + + + RD_POISON_INTR_EN + RD_POISON_INTR_EN + 20 + 1 + + + RD_POISON_INTR_CLR + RD_POISON_INTR_CLR + 24 + 1 + + + + + DDRCTRL_POISONSTAT + DDRCTRL_POISONSTAT + DDRCTRL AXI Poison status register + 0x370 + 0x20 + read-only + 0x00000000 + + + WR_POISON_INTR_0 + WR_POISON_INTR_0 + 0 + 1 + + + WR_POISON_INTR_1 + WR_POISON_INTR_1 + 1 + 1 + + + RD_POISON_INTR_0 + RD_POISON_INTR_0 + 16 + 1 + + + RD_POISON_INTR_1 + RD_POISON_INTR_1 + 17 + 1 + + + + + DDRCTRL_PSTAT + DDRCTRL_PSTAT + DDRCTRL port status register + 0x3FC + 0x20 + read-only + 0x00000000 + + + RD_PORT_BUSY_0 + RD_PORT_BUSY_0 + 0 + 1 + + + RD_PORT_BUSY_1 + RD_PORT_BUSY_1 + 1 + 1 + + + WR_PORT_BUSY_0 + WR_PORT_BUSY_0 + 16 + 1 + + + WR_PORT_BUSY_1 + WR_PORT_BUSY_1 + 17 + 1 + + + + + DDRCTRL_PCCFG + DDRCTRL_PCCFG + DDRCTRL port common configuration register + 0x400 + 0x20 + read-write + 0x00000000 + + + GO2CRITICAL_EN + GO2CRITICAL_EN + 0 + 1 + + + PAGEMATCH_LIMIT + PAGEMATCH_LIMIT + 4 + 1 + + + BL_EXP_MODE + BL_EXP_MODE + 8 + 1 + + + + + DDRCTRL_PCFGR_0 + DDRCTRL_PCFGR_0 + DDRCTRL port 0 configuration read register + 0x404 + 0x20 + read-write + 0x00004000 + + + RD_PORT_PRIORITY + RD_PORT_PRIORITY + 0 + 10 + + + RD_PORT_AGING_EN + RD_PORT_AGING_EN + 12 + 1 + + + RD_PORT_URGENT_EN + RD_PORT_URGENT_EN + 13 + 1 + + + RD_PORT_PAGEMATCH_EN + RD_PORT_PAGEMATCH_EN + 14 + 1 + + + RDWR_ORDERED_EN + RDWR_ORDERED_EN + 16 + 1 + + + + + DDRCTRL_PCFGW_0 + DDRCTRL_PCFGW_0 + DDRCTRL port 0 configuration write register + 0x408 + 0x20 + read-write + 0x00004000 + + + WR_PORT_PRIORITY + WR_PORT_PRIORITY + 0 + 10 + + + WR_PORT_AGING_EN + WR_PORT_AGING_EN + 12 + 1 + + + WR_PORT_URGENT_EN + WR_PORT_URGENT_EN + 13 + 1 + + + WR_PORT_PAGEMATCH_EN + WR_PORT_PAGEMATCH_EN + 14 + 1 + + + + + DDRCTRL_PCTRL_0 + DDRCTRL_PCTRL_0 + DDRCTRL port 0 control register + 0x490 + 0x20 + read-write + 0x00000000 + + + PORT_EN + PORT_EN + 0 + 1 + + + + + DDRCTRL_PCFGQOS0_0 + DDRCTRL_PCFGQOS0_0 + DDRCTRL port 0 read Q0S configuration register 0 + 0x494 + 0x20 + read-write + 0x02000E00 + + + RQOS_MAP_LEVEL1 + RQOS_MAP_LEVEL1 + 0 + 4 + + + RQOS_MAP_LEVEL2 + RQOS_MAP_LEVEL2 + 8 + 4 + + + RQOS_MAP_REGION0 + RQOS_MAP_REGION0 + 16 + 2 + + + RQOS_MAP_REGION1 + RQOS_MAP_REGION1 + 20 + 2 + + + RQOS_MAP_REGION2 + RQOS_MAP_REGION2 + 24 + 2 + + + + + DDRCTRL_PCFGQOS1_0 + DDRCTRL_PCFGQOS1_0 + DDRCTRL port 0 read Q0S configuration register 1 + 0x498 + 0x20 + read-write + 0x00000000 + + + RQOS_MAP_TIMEOUTB + RQOS_MAP_TIMEOUTB + 0 + 11 + + + RQOS_MAP_TIMEOUTR + RQOS_MAP_TIMEOUTR + 16 + 11 + + + + + DDRCTRL_PCFGWQOS0_0 + DDRCTRL_PCFGWQOS0_0 + DDRCTRL port 0 write Q0S configuration register 0 + 0x49C + 0x20 + read-write + 0x00000E00 + + + WQOS_MAP_LEVEL1 + WQOS_MAP_LEVEL1 + 0 + 4 + + + WQOS_MAP_LEVEL2 + WQOS_MAP_LEVEL2 + 8 + 4 + + + WQOS_MAP_REGION0 + WQOS_MAP_REGION0 + 16 + 2 + + + WQOS_MAP_REGION1 + WQOS_MAP_REGION1 + 20 + 2 + + + WQOS_MAP_REGION2 + WQOS_MAP_REGION2 + 24 + 2 + + + + + DDRCTRL_PCFGWQOS1_0 + DDRCTRL_PCFGWQOS1_0 + DDRCTRL port 0 write Q0S configuration register 1 + 0x4A0 + 0x20 + read-write + 0x00000000 + + + WQOS_MAP_TIMEOUT1 + WQOS_MAP_TIMEOUT1 + 0 + 11 + + + WQOS_MAP_TIMEOUT2 + WQOS_MAP_TIMEOUT2 + 16 + 11 + + + + + DDRCTRL_PCFGR_1 + DDRCTRL_PCFGR_1 + DDRCTRL port 1 configuration read register + 0x4B4 + 0x20 + read-write + 0x00004000 + + + RD_PORT_PRIORITY + RD_PORT_PRIORITY + 0 + 10 + + + RD_PORT_AGING_EN + RD_PORT_AGING_EN + 12 + 1 + + + RD_PORT_URGENT_EN + RD_PORT_URGENT_EN + 13 + 1 + + + RD_PORT_PAGEMATCH_EN + RD_PORT_PAGEMATCH_EN + 14 + 1 + + + RDWR_ORDERED_EN + RDWR_ORDERED_EN + 16 + 1 + + + + + DDRCTRL_PCFGW_1 + DDRCTRL_PCFGW_1 + DDRCTRL port 1 configuration write register + 0x4B8 + 0x20 + read-write + 0x00004000 + + + WR_PORT_PRIORITY + WR_PORT_PRIORITY + 0 + 10 + + + WR_PORT_AGING_EN + WR_PORT_AGING_EN + 12 + 1 + + + WR_PORT_URGENT_EN + WR_PORT_URGENT_EN + 13 + 1 + + + WR_PORT_PAGEMATCH_EN + WR_PORT_PAGEMATCH_EN + 14 + 1 + + + + + DDRCTRL_PCTRL_1 + DDRCTRL_PCTRL_1 + DDRCTRL port 1 control register + 0x540 + 0x20 + read-write + 0x00000000 + + + PORT_EN + PORT_EN + 0 + 1 + + + + + DDRCTRL_PCFGQOS0_1 + DDRCTRL_PCFGQOS0_1 + DDRCTRL port 1 read Q0S configuration register 0 + 0x544 + 0x20 + read-write + 0x02000E00 + + + RQOS_MAP_LEVEL1 + RQOS_MAP_LEVEL1 + 0 + 4 + + + RQOS_MAP_LEVEL2 + RQOS_MAP_LEVEL2 + 8 + 4 + + + RQOS_MAP_REGION0 + RQOS_MAP_REGION0 + 16 + 2 + + + RQOS_MAP_REGION1 + RQOS_MAP_REGION1 + 20 + 2 + + + RQOS_MAP_REGION2 + RQOS_MAP_REGION2 + 24 + 2 + + + + + DDRCTRL_PCFGQOS1_1 + DDRCTRL_PCFGQOS1_1 + DDRCTRL port 1 read Q0S configuration register 1 + 0x548 + 0x20 + read-write + 0x00000000 + + + RQOS_MAP_TIMEOUTB + RQOS_MAP_TIMEOUTB + 0 + 11 + + + RQOS_MAP_TIMEOUTR + RQOS_MAP_TIMEOUTR + 16 + 11 + + + + + DDRCTRL_PCFGWQOS0_1 + DDRCTRL_PCFGWQOS0_1 + DDRCTRL port 1 write Q0S configuration register 0 + 0x54C + 0x20 + read-write + 0x00000E00 + + + WQOS_MAP_LEVEL1 + WQOS_MAP_LEVEL1 + 0 + 4 + + + WQOS_MAP_LEVEL2 + WQOS_MAP_LEVEL2 + 8 + 4 + + + WQOS_MAP_REGION0 + WQOS_MAP_REGION0 + 16 + 2 + + + WQOS_MAP_REGION1 + WQOS_MAP_REGION1 + 20 + 2 + + + WQOS_MAP_REGION2 + WQOS_MAP_REGION2 + 24 + 2 + + + + + DDRCTRL_PCFGWQOS1_1 + DDRCTRL_PCFGWQOS1_1 + DDRCTRL port 1 write Q0S configuration register 1 + 0x550 + 0x20 + read-write + 0x00000000 + + + WQOS_MAP_TIMEOUT1 + WQOS_MAP_TIMEOUT1 + 0 + 11 + + + WQOS_MAP_TIMEOUT2 + WQOS_MAP_TIMEOUT2 + 16 + 11 + + + + + + + DDRPERFM + DDRPERFM + DDRPERFM + 0x5A007000 + + 0x0 + 0x400 + registers + + + + DDRPERFM_CTL + DDRPERFM_CTL + Write-only register. A read request returns all zeros. + 0x0 + 0x20 + write-only + 0x00000000 + + + START + START + 0 + 1 + + + STOP + STOP + 1 + 1 + + + + + DDRPERFM_CFG + DDRPERFM_CFG + DDRPERFM configurationl register + 0x4 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 4 + + + SEL + SEL + 16 + 2 + + + + + DDRPERFM_STATUS + DDRPERFM_STATUS + DDRPERFM status register + 0x8 + 0x20 + read-only + 0x00000000 + + + COVF + COVF + 0 + 4 + + + BUSY + BUSY + 16 + 1 + + + TOVF + TOVF + 31 + 1 + + + + + DDRPERFM_CCR + DDRPERFM_CCR + Write-only register. A read request returns all zeros + 0xC + 0x20 + write-only + 0x00000000 + + + CCLR + CCLR + 0 + 4 + + + TCLR + TCLR + 31 + 1 + + + + + DDRPERFM_IER + DDRPERFM_IER + DDRPERFM interrupt enable register + 0x10 + 0x20 + read-write + 0x00000000 + + + OVFIE + OVFIE + 0 + 1 + + + + + DDRPERFM_ISR + DDRPERFM_ISR + DDRPERFM interrupt status register + 0x14 + 0x20 + read-only + 0x00000000 + + + OVFF + OVFF + 0 + 1 + + + + + DDRPERFM_ICR + DDRPERFM_ICR + Write-only register. A read request returns all zeros + 0x18 + 0x20 + write-only + 0x00000000 + + + OVF + OVF + 0 + 1 + + + + + DDRPERFM_TCNT + DDRPERFM_TCNT + DDRPERFM time counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + DDRPERFM_CNT0 + DDRPERFM_CNT0 + DDRPERFM event counter 0 register + 0x60 + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + DDRPERFM_CNT1 + DDRPERFM_CNT1 + DDRPERFM event counter 1 register + 0x68 + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + DDRPERFM_CNT2 + DDRPERFM_CNT2 + DDRPERFM event counter 2 register + 0x70 + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + DDRPERFM_CNT3 + DDRPERFM_CNT3 + DDRPERFM event counter 3 register + 0x78 + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 32 + + + + + DDRPERFM_HWCFG + DDRPERFM_HWCFG + DDRPERFM hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000004 + + + NCNT + NCNT + 0 + 4 + + + + + DDRPERFM_VER + DDRPERFM_VER + DDRPERFM version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DDRPERFM_ID + DDRPERFM_ID + DDRPERFM ID register + 0x3F8 + 0x20 + read-only + 0x00140061 + + + ID + ID + 0 + 32 + + + + + DDRPERFM_SID + DDRPERFM_SID + DDRPERFM magic ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DDRPHYC + DDRPHYC + DDRPHYC + 0x5A004000 + + 0x0 + 0x1000 + registers + + + + DDRPHYC_RIDR + DDRPHYC_RIDR + DDRPHYC revision ID register + 0x0 + 0x20 + read-only + 0x00410010 + + + PUBMNR + PUBMNR + 0 + 4 + + + PUBMDR + PUBMDR + 4 + 4 + + + PUBMJR + PUBMJR + 8 + 4 + + + PHYMNR + PHYMNR + 12 + 4 + + + PHYMDR + PHYMDR + 16 + 4 + + + PHYMJR + PHYMJR + 20 + 4 + + + UDRID + UDRID + 24 + 8 + + + + + DDRPHYC_PIR + DDRPHYC_PIR + DDRPHYC PHY initialization register + 0x4 + 0x20 + write-only + 0x00000000 + + + INIT + INIT + 0 + 1 + + + DLLSRST + DLLSRST + 1 + 1 + + + DLLLOCK + DLLLOCK + 2 + 1 + + + ZCAL + ZCAL + 3 + 1 + + + ITMSRST + ITMSRST + 4 + 1 + + + DRAMRST + DRAMRST + 5 + 1 + + + DRAMINIT + DRAMINIT + 6 + 1 + + + QSTRN + QSTRN + 7 + 1 + + + RVTRN + RVTRN + 8 + 1 + + + ICPC + ICPC + 16 + 1 + + + DLLBYP + DLLBYP + 17 + 1 + + + CTLDINIT + CTLDINIT + 18 + 1 + + + CLRSR + CLRSR + 28 + 1 + + + LOCKBYP + LOCKBYP + 29 + 1 + + + ZCALBYP + ZCALBYP + 30 + 1 + + + INITBYP + INITBYP + 31 + 1 + + + + + DDRPHYC_PGCR + DDRPHYC_PGCR + DDRPHYC PHY global control register + 0x8 + 0x20 + read-write + 0x01BC2E04 + + + ITMDMD + ITMDMD + 0 + 1 + + + DQSCFG + DQSCFG + 1 + 1 + + + DFTCMP + DFTCMP + 2 + 1 + + + DFTLMT + DFTLMT + 3 + 2 + + + DTOSEL + DTOSEL + 5 + 4 + + + CKEN + CKEN + 9 + 3 + + + CKDV + CKDV + 12 + 2 + + + CKINV + CKINV + 14 + 1 + + + IOLB + IOLB + 15 + 1 + + + IODDRM + IODDRM + 16 + 2 + + + RANKEN + RANKEN + 18 + 4 + + + ZKSEL + ZKSEL + 22 + 2 + + + PDDISDX + PDDISDX + 24 + 1 + + + RFSHDT + RFSHDT + 25 + 4 + + + LBDQSS + LBDQSS + 29 + 1 + + + LBGDQS + LBGDQS + 30 + 1 + + + LBMODE + LBMODE + 31 + 1 + + + + + DDRPHYC_PGSR + DDRPHYC_PGSR + DDRPHYC PHY global status register + 0xC + 0x20 + read-only + 0x00000000 + + + IDONE + IDONE + 0 + 1 + + + DLDONE + DLDONE + 1 + 1 + + + ZCDDONE + ZCDDONE + 2 + 1 + + + DIDONE + DIDONE + 3 + 1 + + + DTDONE + DTDONE + 4 + 1 + + + DTERR + DTERR + 5 + 1 + + + DTIERR + DTIERR + 6 + 1 + + + DFTERR + DFTERR + 7 + 1 + + + RVERR + RVERR + 8 + 1 + + + RVEIRR + RVEIRR + 9 + 1 + + + TQ + TQ + 31 + 1 + + + + + DDRPHYC_DLLGCR + DDRPHYC_DLLGCR + DDRPHYC DDR global control register + 0x10 + 0x20 + read-write + 0x03737000 + + + DRES + DRES + 0 + 2 + + + IPUMP + IPUMP + 2 + 3 + + + TESTEN + TESTEN + 5 + 1 + + + DTC + DTC + 6 + 3 + + + ATC + ATC + 9 + 2 + + + TESTSW + TESTSW + 11 + 1 + + + MBIAS + MBIAS + 12 + 8 + + + SBIAS2_0 + SBIAS2_0 + 20 + 3 + + + BPS200 + BPS200 + 23 + 1 + + + SBIAS5_3 + SBIAS5_3 + 24 + 3 + + + FDTRMSL + FDTRMSL + 27 + 2 + + + LOCKDET + LOCKDET + 29 + 1 + + + DLLRSVD2 + DLLRSVD2 + 30 + 2 + + + + + DDRPHYC_ACDLLCR + DDRPHYC_ACDLLCR + DDRPHYC AC DLL control register + 0x14 + 0x20 + read-write + 0x40000000 + + + MFBDLY + MFBDLY + 6 + 3 + + + MFWDLY + MFWDLY + 9 + 3 + + + ATESTEN + ATESTEN + 18 + 1 + + + DLLSRST + DLLSRST + 30 + 1 + + + DLLDIS + DLLDIS + 31 + 1 + + + + + DDRPHYC_PTR0 + DDRPHYC_PTR0 + DDRPHYC PT register 0 + 0x18 + 0x20 + read-write + 0x0022AF9B + + + TDLLSRST + TDLLSRST + 0 + 6 + + + TDLLLOCK + TDLLLOCK + 6 + 12 + + + TITMSRST + TITMSRST + 18 + 4 + + + + + DDRPHYC_PTR1 + DDRPHYC_PTR1 + DDRPHYC PT register 1 + 0x1C + 0x20 + read-write + 0x0604111D + + + TDINIT0 + TDINIT0 + 0 + 19 + + + TDINIT1 + TDINIT1 + 19 + 8 + + + + + DDRPHYC_PTR2 + DDRPHYC_PTR2 + DDRPHYC PT register 2 + 0x20 + 0x20 + read-write + 0x042DA072 + + + TDINIT2 + TDINIT2 + 0 + 17 + + + TDINIT3 + TDINIT3 + 17 + 10 + + + + + DDRPHYC_ACIOCR + DDRPHYC_ACIOCR + DDRPHYC ACIOC register + 0x24 + 0x20 + read-write + 0x33C03812 + + + ACIOM + ACIOM + 0 + 1 + + + ACOE + ACOE + 1 + 1 + + + ACODT + ACODT + 2 + 1 + + + ACPDD + ACPDD + 3 + 1 + + + ACPDR + ACPDR + 4 + 1 + + + CKODT + CKODT + 5 + 3 + + + CKPDD + CKPDD + 8 + 3 + + + CKPDR + CKPDR + 11 + 3 + + + RANKODT + RANKODT + 14 + 1 + + + CSPDD + CSPDD + 18 + 1 + + + RANKPDR + RANKPDR + 22 + 1 + + + RSTODT + RSTODT + 26 + 1 + + + RSTPDD + RSTPDD + 27 + 1 + + + RSTPDR + RSTPDR + 28 + 1 + + + RSTIOM + RSTIOM + 29 + 1 + + + ACSR + ACSR + 30 + 2 + + + + + DDRPHYC_DXCCR + DDRPHYC_DXCCR + DDRPHYC DXCC register + 0x28 + 0x20 + read-write + 0x00000800 + + + DXODT + DXODT + 0 + 1 + + + DXIOM + DXIOM + 1 + 1 + + + DXPDD + DXPDD + 2 + 1 + + + DXPDR + DXPDR + 3 + 1 + + + DQSRES + DQSRES + 4 + 4 + + + DQSNRES + DQSNRES + 8 + 4 + + + DQSNRST + DQSNRST + 14 + 1 + + + RVSEL + RVSEL + 15 + 1 + + + AWDT + AWDT + 16 + 1 + + + + + DDRPHYC_DSGCR + DDRPHYC_DSGCR + DDRPHYC DSGC register + 0x2C + 0x20 + read-write + 0xFA00001F + + + PUREN + PUREN + 0 + 1 + + + BDISEN + BDISEN + 1 + 1 + + + ZUEN + ZUEN + 2 + 1 + + + LPIOPD + LPIOPD + 3 + 1 + + + LPDLLPD + LPDLLPD + 4 + 1 + + + DQSGX + DQSGX + 5 + 3 + + + DQSGE + DQSGE + 8 + 3 + + + NOBUB + NOBUB + 11 + 1 + + + FXDLAT + FXDLAT + 12 + 1 + + + CKEPDD + CKEPDD + 16 + 1 + + + ODTPDD + ODTPDD + 20 + 1 + + + NL2PD + NL2PD + 24 + 1 + + + NL2OE + NL2OE + 25 + 1 + + + TPDPD + TPDPD + 26 + 1 + + + TPDOE + TPDOE + 27 + 1 + + + CKOE + CKOE + 28 + 1 + + + ODTOE + ODTOE + 29 + 1 + + + RSTOE + RSTOE + 30 + 1 + + + CKEOE + CKEOE + 31 + 1 + + + + + DDRPHYC_DCR + DDRPHYC_DCR + DDRPHYC DC register + 0x30 + 0x20 + read-write + 0x0000000B + + + DDRMD + DDRMD + 0 + 3 + + + DDR8BNK + DDR8BNK + 3 + 1 + + + PDQ + PDQ + 4 + 3 + + + MPRDQ + MPRDQ + 7 + 1 + + + DDRTYPE + DDRTYPE + 8 + 2 + + + NOSRA + NOSRA + 27 + 1 + + + DDR2T + DDR2T + 28 + 1 + + + UDIMM + UDIMM + 29 + 1 + + + RDIMM + RDIMM + 30 + 1 + + + TPD + TPD + 31 + 1 + + + + + DDRPHYC_DTPR0 + DDRPHYC_DTPR0 + DDRPHYC DTP register 0 + 0x34 + 0x20 + read-write + 0x3012666E + + + TMRD + TMRD + 0 + 2 + + + TRTP + TRTP + 2 + 3 + + + TWTR + TWTR + 5 + 3 + + + TRP + TRP + 8 + 4 + + + TRCD + TRCD + 12 + 4 + + + TRAS + TRAS + 16 + 5 + + + TRRD + TRRD + 21 + 4 + + + TRC + TRC + 25 + 6 + + + TCCD + TCCD + 31 + 1 + + + + + DDRPHYC_DTPR1 + DDRPHYC_DTPR1 + DDRPHYC DTP register 1 + 0x38 + 0x20 + read-write + 0x0A030090 + + + TAOND + TAOND + 0 + 2 + + + TRTW + TRTW + 2 + 1 + + + TFAW + TFAW + 3 + 6 + + + TMOD + TMOD + 9 + 2 + + + TRTODT + TRTODT + 11 + 1 + + + TRFC + TRFC + 16 + 8 + + + TDQSCKMIN + TDQSCKMIN + 24 + 3 + + + TDQSCKMAX + TDQSCKMAX + 27 + 3 + + + + + DDRPHYC_DTPR2 + DDRPHYC_DTPR2 + DDRPHYC DTP register 2 + 0x3C + 0x20 + read-write + 0x20040D84 + + + TXS + TXS + 0 + 10 + + + TXP + TXP + 10 + 5 + + + TCKE + TCKE + 15 + 4 + + + TDLLK + TDLLK + 19 + 10 + + + + + DDRPHYC_DDR3_MR0 + DDRPHYC_DDR3_MR0 + DDRPHYC MR0 register for DDR3 + 0x40 + 0x10 + read-write + 0x00000A52 + + + BL + BL + 0 + 2 + + + CL0 + CL0 + 2 + 1 + + + BT + BT + 3 + 1 + + + CL + CL + 4 + 3 + + + TM + TM + 7 + 1 + + + DR + DR + 8 + 1 + + + WR + WR + 9 + 3 + + + PD + PD + 12 + 1 + + + RSVD + RSVD + 13 + 3 + + + + + DDRPHYC_DDR3_MR1 + DDRPHYC_DDR3_MR1 + DDRPHYC MR1 register for DDR3 + 0x44 + 0x10 + read-write + 0x00000000 + + + DE + DE + 0 + 1 + + + DIC0 + DIC0 + 1 + 1 + + + RTT0 + RTT0 + 2 + 1 + + + AL + AL + 3 + 2 + + + DIC1 + DIC1 + 5 + 1 + + + RTT1 + RTT1 + 6 + 1 + + + LEVEL + LEVEL + 7 + 1 + + + RTT2 + RTT2 + 9 + 1 + + + TDQS + TDQS + 11 + 1 + + + QOFF + QOFF + 12 + 1 + + + + + DDRPHYC_DDR3_MR2 + DDRPHYC_DDR3_MR2 + DDRPHYC MR2 register for DDR3 + 0x48 + 0x10 + read-write + 0x00000000 + + + PASR + PASR + 0 + 3 + + + CWL + CWL + 3 + 3 + + + ASR + ASR + 6 + 1 + + + SRT + SRT + 7 + 1 + + + RTTWR + RTTWR + 9 + 2 + + + + + DDRPHYC_DDR3_MR3 + DDRPHYC_DDR3_MR3 + DDRPHYC MR3 register for DDR3 + 0x4C + 0x8 + read-write + 0x00000000 + + + MPRLOC + MPRLOC + 0 + 2 + + + MPR + MPR + 2 + 1 + + + + + DDRPHYC_ODTCR + DDRPHYC_ODTCR + DDRPHYC ODTC register + 0x50 + 0x20 + read-write + 0x84210000 + + + RDODT + RDODT + 0 + 1 + + + WRODT + WRODT + 16 + 1 + + + + + DDRPHYC_DTAR + DDRPHYC_DTAR + DDRPHYC DTA register + 0x54 + 0x20 + read-write + 0x00000000 + + + DTCOL + DTCOL + 0 + 12 + + + DTROW + DTROW + 12 + 16 + + + DTBANK + DTBANK + 28 + 3 + + + DTMPR + DTMPR + 31 + 1 + + + + + DDRPHYC_DTDR0 + DDRPHYC_DTDR0 + DDRPHYC DTD register 0 + 0x58 + 0x20 + read-write + 0xDD22EE11 + + + DTBYTE0 + DTBYTE0 + 0 + 8 + + + DTBYTE1 + DTBYTE1 + 8 + 8 + + + DTBYTE2 + DTBYTE2 + 16 + 8 + + + DTBYTE3 + DTBYTE3 + 24 + 8 + + + + + DDRPHYC_DTDR1 + DDRPHYC_DTDR1 + DDRPHYC DTD register 1 + 0x5C + 0x20 + read-write + 0x7788BB44 + + + DTBYTE4 + DTBYTE4 + 0 + 8 + + + DTBYTE5 + DTBYTE5 + 8 + 8 + + + DTBYTE6 + DTBYTE6 + 16 + 8 + + + DTBYTE7 + DTBYTE7 + 24 + 8 + + + + + DDRPHYC_GPR0 + DDRPHYC_GPR0 + DDRPHYC general purpose register 0 + 0x178 + 0x20 + read-write + 0x00000000 + + + GPR0 + GPR0 + 0 + 32 + + + + + DDRPHYC_GPR1 + DDRPHYC_GPR1 + DDRPHYC general purpose register 1 + 0x17C + 0x20 + read-write + 0x00000000 + + + GPR1 + GPR1 + 0 + 32 + + + + + DDRPHYC_ZQ0CR0 + DDRPHYC_ZQ0CR0 + DDRPHYC ZQ0C register 0 + 0x180 + 0x20 + read-write + 0x0000014A + + + ZDATA + ZDATA + 0 + 20 + + + ZDEN + ZDEN + 28 + 1 + + + ZCALBYP + ZCALBYP + 29 + 1 + + + ZCAL + ZCAL + 30 + 1 + + + ZQPD + ZQPD + 31 + 1 + + + + + DDRPHYC_ZQ0CR1 + DDRPHYC_ZQ0CR1 + DDRPHYC ZQ0CR1 register + 0x184 + 0x8 + read-write + 0x0000007B + + + ZPROG + ZPROG + 0 + 8 + + + + + DDRPHYC_ZQ0SR0 + DDRPHYC_ZQ0SR0 + DDRPHYC ZQ0S register 0 + 0x188 + 0x20 + read-only + 0x0000014A + + + ZCTRL + ZCTRL + 0 + 20 + + + ZERR + ZERR + 30 + 1 + + + ZDONE + ZDONE + 31 + 1 + + + + + DDRPHYC_ZQ0SR1 + DDRPHYC_ZQ0SR1 + DDRPHYC ZQ0S register 1 + 0x18C + 0x8 + read-only + 0x00000000 + + + ZPD + ZPD + 0 + 2 + + + ZPU + ZPU + 2 + 2 + + + OPD + OPD + 4 + 2 + + + OPU + OPU + 6 + 2 + + + + + DDRPHYC_DX0GCR + DDRPHYC_DX0GCR + DDRPHYC byte lane 0 GC register + 0x1C0 + 0x20 + read-write + 0x0000EE81 + + + DXEN + DXEN + 0 + 1 + + + DQSODT + DQSODT + 1 + 1 + + + DQODT + DQODT + 2 + 1 + + + DXIOM + DXIOM + 3 + 1 + + + DXPDD + DXPDD + 4 + 1 + + + DXPDR + DXPDR + 5 + 1 + + + DQSRPD + DQSRPD + 6 + 1 + + + DSEN + DSEN + 7 + 2 + + + DQSRTT + DQSRTT + 9 + 1 + + + DQRTT + DQRTT + 10 + 1 + + + RTTOH + RTTOH + 11 + 2 + + + RTTOAL + RTTOAL + 13 + 1 + + + R0RVSL + R0RVSL + 14 + 3 + + + + + DDRPHYC_DX0GSR0 + DDRPHYC_DX0GSR0 + DDRPHYC byte lane 0 GS register 0 + 0x1C4 + 0x10 + read-only + 0x00000000 + + + DTDONE + DTDONE + 0 + 1 + + + DTERR + DTERR + 4 + 1 + + + DTIERR + DTIERR + 8 + 1 + + + DTPASS + DTPASS + 13 + 3 + + + + + DDRPHYC_DX0GSR1 + DDRPHYC_DX0GSR1 + DDRPHYC byte lane 0 GS register 1 + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DFTERR + DFTERR + 0 + 1 + + + DQSDFT + DQSDFT + 4 + 2 + + + RVERR + RVERR + 12 + 1 + + + RVIERR + RVIERR + 16 + 1 + + + RVPASS + RVPASS + 20 + 3 + + + + + DDRPHYC_DX0DLLCR + DDRPHYC_DX0DLLCR + DDRPHYC byte lane 0 DLLC register + 0x1CC + 0x20 + read-write + 0x40000000 + + + SFBDLY + SFBDLY + 0 + 3 + + + SFWDLY + SFWDLY + 3 + 3 + + + MFBDLY + MFBDLY + 6 + 3 + + + MFWDLY + MFWDLY + 9 + 3 + + + SSTART + SSTART + 12 + 2 + + + SDPHASE + SDPHASE + 14 + 4 + + + ATESTEN + ATESTEN + 18 + 1 + + + SDLBMODE + SDLBMODE + 19 + 1 + + + DLLSRST + DLLSRST + 30 + 1 + + + DLLDIS + DLLDIS + 31 + 1 + + + + + DDRPHYC_DX0DQTR + DDRPHYC_DX0DQTR + DDRPHYC byte lane 0 DQT register + 0x1D0 + 0x20 + read-write + 0xFFFFFFFF + + + DQDLY0 + DQDLY0 + 0 + 4 + + + DQDLY1 + DQDLY1 + 4 + 4 + + + DQDLY2 + DQDLY2 + 8 + 4 + + + DQDLY3 + DQDLY3 + 12 + 4 + + + DQDLY4 + DQDLY4 + 16 + 4 + + + DQDLY5 + DQDLY5 + 20 + 4 + + + DQDLY6 + DQDLY6 + 24 + 4 + + + DQDLY7 + DQDLY7 + 28 + 4 + + + + + DDRPHYC_DX0DQSTR + DDRPHYC_DX0DQSTR + DDRPHYC byte lane 0 DQST register + 0x1D4 + 0x20 + read-write + 0x3DB02000 + + + R0DGSL + R0DGSL + 0 + 3 + + + R0DGPS + R0DGPS + 12 + 2 + + + DQSDLY + DQSDLY + 20 + 3 + + + DQSNDLY + DQSNDLY + 23 + 3 + + + DMDLY + DMDLY + 26 + 4 + + + + + DDRPHYC_DX1GCR + DDRPHYC_DX1GCR + DDRPHYC byte lane 1 GC register + 0x200 + 0x20 + read-write + 0x0000EE81 + + + DXEN + DXEN + 0 + 1 + + + DQSODT + DQSODT + 1 + 1 + + + DQODT + DQODT + 2 + 1 + + + DXIOM + DXIOM + 3 + 1 + + + DXPDD + DXPDD + 4 + 1 + + + DXPDR + DXPDR + 5 + 1 + + + DQSRPD + DQSRPD + 6 + 1 + + + DSEN + DSEN + 7 + 2 + + + DQSRTT + DQSRTT + 9 + 1 + + + DQRTT + DQRTT + 10 + 1 + + + RTTOH + RTTOH + 11 + 2 + + + RTTOAL + RTTOAL + 13 + 1 + + + R0RVSL + R0RVSL + 14 + 3 + + + + + DDRPHYC_DX1GSR0 + DDRPHYC_DX1GSR0 + DDRPHYC byte lane 1 GS register 0 + 0x204 + 0x10 + read-only + 0x00000000 + + + DTDONE + DTDONE + 0 + 1 + + + DTERR + DTERR + 4 + 1 + + + DTIERR + DTIERR + 8 + 1 + + + DTPASS + DTPASS + 13 + 3 + + + + + DDRPHYC_DX1GSR1 + DDRPHYC_DX1GSR1 + DDRPHYC byte lane 1 GS register 1 + 0x208 + 0x20 + read-only + 0x00000000 + + + DFTERR + DFTERR + 0 + 1 + + + DQSDFT + DQSDFT + 4 + 2 + + + RVERR + RVERR + 12 + 1 + + + RVIERR + RVIERR + 16 + 1 + + + RVPASS + RVPASS + 20 + 3 + + + + + DDRPHYC_DX1DLLCR + DDRPHYC_DX1DLLCR + DDRPHYC byte lane 1 DLLC register + 0x20C + 0x20 + read-write + 0x40000000 + + + SFBDLY + SFBDLY + 0 + 3 + + + SFWDLY + SFWDLY + 3 + 3 + + + MFBDLY + MFBDLY + 6 + 3 + + + MFWDLY + MFWDLY + 9 + 3 + + + SSTART + SSTART + 12 + 2 + + + SDPHASE + SDPHASE + 14 + 4 + + + ATESTEN + ATESTEN + 18 + 1 + + + SDLBMODE + SDLBMODE + 19 + 1 + + + DLLSRST + DLLSRST + 30 + 1 + + + DLLDIS + DLLDIS + 31 + 1 + + + + + DDRPHYC_DX1DQTR + DDRPHYC_DX1DQTR + DDRPHYC byte lane 1 DQT register + 0x210 + 0x20 + read-write + 0xFFFFFFFF + + + DQDLY0 + DQDLY0 + 0 + 4 + + + DQDLY1 + DQDLY1 + 4 + 4 + + + DQDLY2 + DQDLY2 + 8 + 4 + + + DQDLY3 + DQDLY3 + 12 + 4 + + + DQDLY4 + DQDLY4 + 16 + 4 + + + DQDLY5 + DQDLY5 + 20 + 4 + + + DQDLY6 + DQDLY6 + 24 + 4 + + + DQDLY7 + DQDLY7 + 28 + 4 + + + + + DDRPHYC_DX1DQSTR + DDRPHYC_DX1DQSTR + DDRPHYC byte lane 1 DQST register + 0x214 + 0x20 + read-write + 0x3DB02000 + + + R0DGSL + R0DGSL + 0 + 3 + + + R0DGPS + R0DGPS + 12 + 2 + + + DQSDLY + DQSDLY + 20 + 3 + + + DQSNDLY + DQSNDLY + 23 + 3 + + + DMDLY + DMDLY + 26 + 4 + + + + + DDRPHYC_DX2GCR + DDRPHYC_DX2GCR + DDRPHYC byte lane 2 GC register + 0x240 + 0x20 + read-write + 0x0000EE81 + + + DXEN + DXEN + 0 + 1 + + + DQSODT + DQSODT + 1 + 1 + + + DQODT + DQODT + 2 + 1 + + + DXIOM + DXIOM + 3 + 1 + + + DXPDD + DXPDD + 4 + 1 + + + DXPDR + DXPDR + 5 + 1 + + + DQSRPD + DQSRPD + 6 + 1 + + + DSEN + DSEN + 7 + 2 + + + DQSRTT + DQSRTT + 9 + 1 + + + DQRTT + DQRTT + 10 + 1 + + + RTTOH + RTTOH + 11 + 2 + + + RTTOAL + RTTOAL + 13 + 1 + + + R0RVSL + R0RVSL + 14 + 3 + + + + + DDRPHYC_DX2GSR0 + DDRPHYC_DX2GSR0 + DDRPHYC byte lane 2 GS register 0 + 0x244 + 0x10 + read-only + 0x00000000 + + + DTDONE + DTDONE + 0 + 1 + + + DTERR + DTERR + 4 + 1 + + + DTIERR + DTIERR + 8 + 1 + + + DTPASS + DTPASS + 13 + 3 + + + + + DDRPHYC_DX2GSR1 + DDRPHYC_DX2GSR1 + DDRPHYC byte lane 2 GS register 1 + 0x248 + 0x20 + read-only + 0x00000000 + + + DFTERR + DFTERR + 0 + 1 + + + DQSDFT + DQSDFT + 4 + 2 + + + RVERR + RVERR + 12 + 1 + + + RVIERR + RVIERR + 16 + 1 + + + RVPASS + RVPASS + 20 + 3 + + + + + DDRPHYC_DX2DLLCR + DDRPHYC_DX2DLLCR + DDRPHYC byte lane 2 DLLC register + 0x24C + 0x20 + read-write + 0x40000000 + + + SFBDLY + SFBDLY + 0 + 3 + + + SFWDLY + SFWDLY + 3 + 3 + + + MFBDLY + MFBDLY + 6 + 3 + + + MFWDLY + MFWDLY + 9 + 3 + + + SSTART + SSTART + 12 + 2 + + + SDPHASE + SDPHASE + 14 + 4 + + + ATESTEN + ATESTEN + 18 + 1 + + + SDLBMODE + SDLBMODE + 19 + 1 + + + DLLSRST + DLLSRST + 30 + 1 + + + DLLDIS + DLLDIS + 31 + 1 + + + + + DDRPHYC_DX2DQTR + DDRPHYC_DX2DQTR + DDRPHYC byte lane 2 DQT register + 0x250 + 0x20 + read-write + 0xFFFFFFFF + + + DQDLY0 + DQDLY0 + 0 + 4 + + + DQDLY1 + DQDLY1 + 4 + 4 + + + DQDLY2 + DQDLY2 + 8 + 4 + + + DQDLY3 + DQDLY3 + 12 + 4 + + + DQDLY4 + DQDLY4 + 16 + 4 + + + DQDLY5 + DQDLY5 + 20 + 4 + + + DQDLY6 + DQDLY6 + 24 + 4 + + + DQDLY7 + DQDLY7 + 28 + 4 + + + + + DDRPHYC_DX2DQSTR + DDRPHYC_DX2DQSTR + DDRPHYC byte lane 2 DQST register + 0x254 + 0x20 + read-write + 0x3DB02000 + + + R0DGSL + R0DGSL + 0 + 3 + + + R0DGPS + R0DGPS + 12 + 2 + + + DQSDLY + DQSDLY + 20 + 3 + + + DQSNDLY + DQSNDLY + 23 + 3 + + + DMDLY + DMDLY + 26 + 4 + + + + + DDRPHYC_DX3GCR + DDRPHYC_DX3GCR + DDRPHYC byte lane 3 GC register + 0x280 + 0x20 + read-write + 0x0000EE81 + + + DXEN + DXEN + 0 + 1 + + + DQSODT + DQSODT + 1 + 1 + + + DQODT + DQODT + 2 + 1 + + + DXIOM + DXIOM + 3 + 1 + + + DXPDD + DXPDD + 4 + 1 + + + DXPDR + DXPDR + 5 + 1 + + + DQSRPD + DQSRPD + 6 + 1 + + + DSEN + DSEN + 7 + 2 + + + DQSRTT + DQSRTT + 9 + 1 + + + DQRTT + DQRTT + 10 + 1 + + + RTTOH + RTTOH + 11 + 2 + + + RTTOAL + RTTOAL + 13 + 1 + + + R0RVSL + R0RVSL + 14 + 3 + + + + + DDRPHYC_DX3GSR0 + DDRPHYC_DX3GSR0 + DDRPHYC byte lane 3 GS register 0 + 0x284 + 0x10 + read-only + 0x00000000 + + + DTDONE + DTDONE + 0 + 1 + + + DTERR + DTERR + 4 + 1 + + + DTIERR + DTIERR + 8 + 1 + + + DTPASS + DTPASS + 13 + 3 + + + + + DDRPHYC_DX3GSR1 + DDRPHYC_DX3GSR1 + DDRPHYC byte lane 3 GS register 1 + 0x288 + 0x20 + read-only + 0x00000000 + + + DFTERR + DFTERR + 0 + 1 + + + DQSDFT + DQSDFT + 4 + 2 + + + RVERR + RVERR + 12 + 1 + + + RVIERR + RVIERR + 16 + 1 + + + RVPASS + RVPASS + 20 + 3 + + + + + DDRPHYC_DX3DLLCR + DDRPHYC_DX3DLLCR + DDRPHYC byte lane 3 DLLC register + 0x28C + 0x20 + read-write + 0x40000000 + + + SFBDLY + SFBDLY + 0 + 3 + + + SFWDLY + SFWDLY + 3 + 3 + + + MFBDLY + MFBDLY + 6 + 3 + + + MFWDLY + MFWDLY + 9 + 3 + + + SSTART + SSTART + 12 + 2 + + + SDPHASE + SDPHASE + 14 + 4 + + + ATESTEN + ATESTEN + 18 + 1 + + + SDLBMODE + SDLBMODE + 19 + 1 + + + DLLSRST + DLLSRST + 30 + 1 + + + DLLDIS + DLLDIS + 31 + 1 + + + + + DDRPHYC_DX3DQTR + DDRPHYC_DX3DQTR + DDRPHYC byte lane 3 DQT register + 0x290 + 0x20 + read-write + 0xFFFFFFFF + + + DQDLY0 + DQDLY0 + 0 + 4 + + + DQDLY1 + DQDLY1 + 4 + 4 + + + DQDLY2 + DQDLY2 + 8 + 4 + + + DQDLY3 + DQDLY3 + 12 + 4 + + + DQDLY4 + DQDLY4 + 16 + 4 + + + DQDLY5 + DQDLY5 + 20 + 4 + + + DQDLY6 + DQDLY6 + 24 + 4 + + + DQDLY7 + DQDLY7 + 28 + 4 + + + + + DDRPHYC_DX3DQSTR + DDRPHYC_DX3DQSTR + DDRPHYC byte lane 3 DQST register + 0x294 + 0x20 + read-write + 0x3DB02000 + + + R0DGSL + R0DGSL + 0 + 3 + + + R0DGPS + R0DGPS + 12 + 2 + + + DQSDLY + DQSDLY + 20 + 3 + + + DQSNDLY + DQSNDLY + 23 + 3 + + + DMDLY + DMDLY + 26 + 4 + + + + + + + DLYBSD1 + DLYBSD1 + DLYBSD1 + 0x58006000 + + 0x0 + 0x1000 + registers + + + + DLYB_CR + DLYB_CR + DLYB control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN + DEN + 0 + 1 + + + SEN + SEN + 1 + 1 + + + + + DLYB_CFGR + DLYB_CFGR + DLYB configuration register + 0x4 + 0x20 + 0x00000000 + + + SEL + SEL + 0 + 4 + read-write + + + UNIT + UNIT + 8 + 7 + read-write + + + LNG + LNG + 16 + 12 + read-only + + + LNGF + LNGF + 31 + 1 + read-only + + + + + DLYB_VERR + DLYB_VERR + DLYB IP version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DLYB_IPIDR + DLYB_IPIDR + DLYB IP identification register + 0x3F8 + 0x20 + read-only + 0x00140051 + + + ID + ID + 0 + 32 + + + + + DLYB_SIDR + DLYB_SIDR + DLYB size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DLYBSD2 + 0x58008000 + + + DLYBSD3 + 0x48005000 + + + DFSDM1 + DFSDM1 + DFSDM1 + 0x4400D000 + + 0x0 + 0x800 + registers + + + + DFSDM_CH0CFGR1 + DFSDM_CH0CFGR1 + This register specifies the parameters used by channel y. + 0x0 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH0CFGR2 + DFSDM_CH0CFGR2 + This register specifies the parameters used by channel y. + 0x4 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH0AWSCDR + DFSDM_CH0AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0x8 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH0WDATR + DFSDM_CH0WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0xC + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH0DATINR + DFSDM_CH0DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0x10 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH0DLYR + DFSDM_CH0DLYR + DFSDM channel 0 delay register + 0x14 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH1CFGR1 + DFSDM_CH1CFGR1 + This register specifies the parameters used by channel y. + 0x20 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH1CFGR2 + DFSDM_CH1CFGR2 + This register specifies the parameters used by channel y. + 0x24 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH1AWSCDR + DFSDM_CH1AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0x28 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH1WDATR + DFSDM_CH1WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0x2C + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH1DATINR + DFSDM_CH1DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0x30 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH1DLYR + DFSDM_CH1DLYR + DFSDM channel 1 delay register + 0x34 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH2CFGR1 + DFSDM_CH2CFGR1 + This register specifies the parameters used by channel y. + 0x40 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH2CFGR2 + DFSDM_CH2CFGR2 + This register specifies the parameters used by channel y. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH2AWSCDR + DFSDM_CH2AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0x48 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH2WDATR + DFSDM_CH2WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0x4C + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH2DATINR + DFSDM_CH2DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0x50 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH2DLYR + DFSDM_CH2DLYR + DFSDM channel 2 delay register + 0x54 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH3CFGR1 + DFSDM_CH3CFGR1 + This register specifies the parameters used by channel y. + 0x60 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH3CFGR2 + DFSDM_CH3CFGR2 + This register specifies the parameters used by channel y. + 0x64 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH3AWSCDR + DFSDM_CH3AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0x68 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH3WDATR + DFSDM_CH3WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0x6C + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH3DATINR + DFSDM_CH3DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0x70 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH3DLYR + DFSDM_CH3DLYR + DFSDM channel 3 delay register + 0x74 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH4CFGR1 + DFSDM_CH4CFGR1 + This register specifies the parameters used by channel y. + 0x80 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH4CFGR2 + DFSDM_CH4CFGR2 + This register specifies the parameters used by channel y. + 0x84 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH4AWSCDR + DFSDM_CH4AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0x88 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH4WDATR + DFSDM_CH4WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0x8C + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH4DATINR + DFSDM_CH4DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0x90 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH4DLYR + DFSDM_CH4DLYR + DFSDM channel 4 delay register + 0x94 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH5CFGR1 + DFSDM_CH5CFGR1 + This register specifies the parameters used by channel y. + 0xA0 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH5CFGR2 + DFSDM_CH5CFGR2 + This register specifies the parameters used by channel y. + 0xA4 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH5AWSCDR + DFSDM_CH5AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0xA8 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH5WDATR + DFSDM_CH5WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0xAC + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH5DATINR + DFSDM_CH5DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0xB0 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH5DLYR + DFSDM_CH5DLYR + DFSDM channel 5 delay register + 0xB4 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH6CFGR1 + DFSDM_CH6CFGR1 + This register specifies the parameters used by channel y. + 0xC0 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH6CFGR2 + DFSDM_CH6CFGR2 + This register specifies the parameters used by channel y. + 0xC4 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH6AWSCDR + DFSDM_CH6AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0xC8 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH6WDATR + DFSDM_CH6WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0xCC + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH6DATINR + DFSDM_CH6DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0xD0 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH6DLYR + DFSDM_CH6DLYR + DFSDM channel 6 delay register + 0xD4 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_CH7CFGR1 + DFSDM_CH7CFGR1 + This register specifies the parameters used by channel y. + 0xE0 + 0x20 + read-write + 0x00000000 + + + SITP + SITP + 0 + 2 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SCDEN + SCDEN + 5 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + CHEN + CHEN + 7 + 1 + + + CHINSEL + CHINSEL + 8 + 1 + + + DATMPX + DATMPX + 12 + 2 + + + DATPACK + DATPACK + 14 + 2 + + + CKOUTDIV + CKOUTDIV + 16 + 8 + + + CKOUTSRC + CKOUTSRC + 30 + 1 + + + DFSDMEN + DFSDMEN + 31 + 1 + + + + + DFSDM_CH7CFGR2 + DFSDM_CH7CFGR2 + This register specifies the parameters used by channel y. + 0xE4 + 0x20 + read-write + 0x00000000 + + + DTRBS + DTRBS + 3 + 5 + + + OFFSET + OFFSET + 8 + 24 + + + + + DFSDM_CH7AWSCDR + DFSDM_CH7AWSCDR + Short-circuit detector and analog watchdog settings for channel y. + 0xE8 + 0x20 + read-write + 0x00000000 + + + SCDT + SCDT + 0 + 8 + + + BKSCD + BKSCD + 12 + 4 + + + AWFOSR + AWFOSR + 16 + 5 + + + AWFORD + AWFORD + 22 + 2 + + + + + DFSDM_CH7WDATR + DFSDM_CH7WDATR + This register contains the data resulting from the analog watchdog filter associated to the input channel y. + 0xEC + 0x20 + read-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + DFSDM_CH7DATINR + DFSDM_CH7DATINR + This register contains 16-bit input data to be processed by DFSDM filter module. + 0xF0 + 0x20 + read-write + 0x00000000 + + + INDAT0 + INDAT0 + 0 + 16 + + + INDAT1 + INDAT1 + 16 + 16 + + + + + DFSDM_CH7DLYR + DFSDM_CH7DLYR + DFSDM channel 7 delay register + 0xF4 + 0x20 + read-write + 0x00000000 + + + PLSSKP + PLSSKP + 0 + 6 + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + DFSDM filter 0 control register 1 + 0x100 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + DFSDM filter 0 control register 2 + 0x104 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + DFSDM filter 0 interrupt and status register + 0x108 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + DFSDM filter 0 interrupt flag clear register + 0x10C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + DFSDM filter 0 injected channel group selection register + 0x110 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT0FCR + DFSDM_FLT0FCR + DFSDM filter 0 control register + 0x114 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + DFSDM filter 0 data register for injected group + 0x118 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + DFSDM filter 0 data register for the regular channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + DFSDM filter 0 analog watchdog high threshold register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + DFSDM filter 0 analog watchdog low threshold register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + DFSDM filter 0 analog watchdog status register + 0x128 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + DFSDM filter 0 analog watchdog clear flag register + 0x12C + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + DFSDM filter 0 extremes detector maximum register + 0x130 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + DFSDM filter 0 extremes detector minimum register + 0x134 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + DFSDM filter 0 conversion timer register + 0x138 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + DFSDM filter 1 control register 1 + 0x180 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + DFSDM filter 1 control register 2 + 0x184 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + DFSDM filter 1 interrupt and status register + 0x188 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT1ICR + DFSDM_FLT1ICR + DFSDM filter 1 interrupt flag clear register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT1JCHGR + DFSDM_FLT1JCHGR + DFSDM filter 1 injected channel group selection register + 0x190 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT1FCR + DFSDM_FLT1FCR + DFSDM filter 1 control register + 0x194 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + DFSDM filter 1 data register for injected group + 0x198 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + DFSDM filter 1 data register for the regular channel + 0x19C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + DFSDM filter 1 analog watchdog high threshold register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + DFSDM filter 1 analog watchdog low threshold register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + DFSDM filter 1 analog watchdog status register + 0x1A8 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + DFSDM filter 1 analog watchdog clear flag register + 0x1AC + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + DFSDM filter 1 extremes detector maximum register + 0x1B0 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + DFSDM filter 1 extremes detector minimum register + 0x1B4 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + DFSDM filter 1 conversion timer register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_FLT2CR1 + DFSDM_FLT2CR1 + DFSDM filter 2 control register 1 + 0x200 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT2CR2 + DFSDM_FLT2CR2 + DFSDM filter 2 control register 2 + 0x204 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT2ISR + DFSDM_FLT2ISR + DFSDM filter 2 interrupt and status register + 0x208 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT2ICR + DFSDM_FLT2ICR + DFSDM filter 2 interrupt flag clear register + 0x20C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT2JCHGR + DFSDM_FLT2JCHGR + DFSDM filter 2 injected channel group selection register + 0x210 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT2FCR + DFSDM_FLT2FCR + DFSDM filter 2 control register + 0x214 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT2JDATAR + DFSDM_FLT2JDATAR + DFSDM filter 2 data register for injected group + 0x218 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT2RDATAR + DFSDM_FLT2RDATAR + DFSDM filter 2 data register for the regular channel + 0x21C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT2AWHTR + DFSDM_FLT2AWHTR + DFSDM filter 2 analog watchdog high threshold register + 0x220 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT2AWLTR + DFSDM_FLT2AWLTR + DFSDM filter 2 analog watchdog low threshold register + 0x224 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT2AWSR + DFSDM_FLT2AWSR + DFSDM filter 2 analog watchdog status register + 0x228 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT2AWCFR + DFSDM_FLT2AWCFR + DFSDM filter 2 analog watchdog clear flag register + 0x22C + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT2EXMAX + DFSDM_FLT2EXMAX + DFSDM filter 2 extremes detector maximum register + 0x230 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT2EXMIN + DFSDM_FLT2EXMIN + DFSDM filter 2 extremes detector minimum register + 0x234 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT2CNVTIMR + DFSDM_FLT2CNVTIMR + DFSDM filter 2 conversion timer register + 0x238 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_FLT3CR1 + DFSDM_FLT3CR1 + DFSDM filter 3 control register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT3CR2 + DFSDM_FLT3CR2 + DFSDM filter 3 control register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT3ISR + DFSDM_FLT3ISR + DFSDM filter 3 interrupt and status register + 0x288 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT3ICR + DFSDM_FLT3ICR + DFSDM filter 3 interrupt flag clear register + 0x28C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT3JCHGR + DFSDM_FLT3JCHGR + DFSDM filter 3 injected channel group selection register + 0x290 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT3FCR + DFSDM_FLT3FCR + DFSDM filter 3 control register + 0x294 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT3JDATAR + DFSDM_FLT3JDATAR + DFSDM filter 3 data register for injected group + 0x298 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT3RDATAR + DFSDM_FLT3RDATAR + DFSDM filter 3 data register for the regular channel + 0x29C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT3AWHTR + DFSDM_FLT3AWHTR + DFSDM filter 3 analog watchdog high threshold register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT3AWLTR + DFSDM_FLT3AWLTR + DFSDM filter 3 analog watchdog low threshold register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT3AWSR + DFSDM_FLT3AWSR + DFSDM filter 3 analog watchdog status register + 0x2A8 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT3AWCFR + DFSDM_FLT3AWCFR + DFSDM filter 3 analog watchdog clear flag register + 0x2AC + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT3EXMAX + DFSDM_FLT3EXMAX + DFSDM filter 3 extremes detector maximum register + 0x2B0 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT3EXMIN + DFSDM_FLT3EXMIN + DFSDM filter 3 extremes detector minimum register + 0x2B4 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT3CNVTIMR + DFSDM_FLT3CNVTIMR + DFSDM filter 3 conversion timer register + 0x2B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_FLT4CR1 + DFSDM_FLT4CR1 + DFSDM filter 4 control register 1 + 0x300 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT4CR2 + DFSDM_FLT4CR2 + DFSDM filter 4 control register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT4ISR + DFSDM_FLT4ISR + DFSDM filter 4 interrupt and status register + 0x308 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT4ICR + DFSDM_FLT4ICR + DFSDM filter 4 interrupt flag clear register + 0x30C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT4JCHGR + DFSDM_FLT4JCHGR + DFSDM filter 4 injected channel group selection register + 0x310 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT4FCR + DFSDM_FLT4FCR + DFSDM filter 4 control register + 0x314 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT4JDATAR + DFSDM_FLT4JDATAR + DFSDM filter 4 data register for injected group + 0x318 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT4RDATAR + DFSDM_FLT4RDATAR + DFSDM filter 4 data register for the regular channel + 0x31C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT4AWHTR + DFSDM_FLT4AWHTR + DFSDM filter 4 analog watchdog high threshold register + 0x320 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT4AWLTR + DFSDM_FLT4AWLTR + DFSDM filter 4 analog watchdog low threshold register + 0x324 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT4AWSR + DFSDM_FLT4AWSR + DFSDM filter 4 analog watchdog status register + 0x328 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT4AWCFR + DFSDM_FLT4AWCFR + DFSDM filter 4 analog watchdog clear flag register + 0x32C + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT4EXMAX + DFSDM_FLT4EXMAX + DFSDM filter 4 extremes detector maximum register + 0x330 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT4EXMIN + DFSDM_FLT4EXMIN + DFSDM filter 4 extremes detector minimum register + 0x334 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT4CNVTIMR + DFSDM_FLT4CNVTIMR + DFSDM filter 4 conversion timer register + 0x338 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_FLT5CR1 + DFSDM_FLT5CR1 + DFSDM filter 5 control register 1 + 0x380 + 0x20 + read-write + 0x00000000 + + + DFEN + DFEN + 0 + 1 + + + JSWSTART + JSWSTART + 1 + 1 + + + JSYNC + JSYNC + 3 + 1 + + + JSCAN + JSCAN + 4 + 1 + + + JDMAEN + JDMAEN + 5 + 1 + + + JEXTSEL + JEXTSEL + 8 + 5 + + + JEXTEN + JEXTEN + 13 + 2 + + + RSWSTART + RSWSTART + 17 + 1 + + + RCONT + RCONT + 18 + 1 + + + RSYNC + RSYNC + 19 + 1 + + + RDMAEN + RDMAEN + 21 + 1 + + + RCH + RCH + 24 + 3 + + + FAST + FAST + 29 + 1 + + + AWFSEL + AWFSEL + 30 + 1 + + + + + DFSDM_FLT5CR2 + DFSDM_FLT5CR2 + DFSDM filter 5 control register 2 + 0x384 + 0x20 + read-write + 0x00000000 + + + JEOCIE + JEOCIE + 0 + 1 + + + REOCIE + REOCIE + 1 + 1 + + + JOVRIE + JOVRIE + 2 + 1 + + + ROVRIE + ROVRIE + 3 + 1 + + + AWDIE + AWDIE + 4 + 1 + + + SCDIE + SCDIE + 5 + 1 + + + CKABIE + CKABIE + 6 + 1 + + + EXCH + EXCH + 8 + 8 + + + AWDCH + AWDCH + 16 + 8 + + + + + DFSDM_FLT5ISR + DFSDM_FLT5ISR + DFSDM filter 5 interrupt and status register + 0x388 + 0x20 + read-only + 0x00FF0000 + + + JEOCF + JEOCF + 0 + 1 + + + REOCF + REOCF + 1 + 1 + + + JOVRF + JOVRF + 2 + 1 + + + ROVRF + ROVRF + 3 + 1 + + + AWDF + AWDF + 4 + 1 + + + JCIP + JCIP + 13 + 1 + + + RCIP + RCIP + 14 + 1 + + + CKABF + CKABF + 16 + 8 + + + SCDF + SCDF + 24 + 8 + + + + + DFSDM_FLT5ICR + DFSDM_FLT5ICR + DFSDM filter 5 interrupt flag clear register + 0x38C + 0x20 + read-write + 0x00000000 + + + CLRJOVRF + CLRJOVRF + 2 + 1 + + + CLRROVRF + CLRROVRF + 3 + 1 + + + CLRCKABF + CLRCKABF + 16 + 8 + + + CLRSCDF + CLRSCDF + 24 + 8 + + + + + DFSDM_FLT5JCHGR + DFSDM_FLT5JCHGR + DFSDM filter 5 injected channel group selection register + 0x390 + 0x20 + read-write + 0x00000001 + + + JCHG + JCHG + 0 + 8 + + + + + DFSDM_FLT5FCR + DFSDM_FLT5FCR + DFSDM filter 5 control register + 0x394 + 0x20 + read-write + 0x00000000 + + + IOSR + IOSR + 0 + 8 + + + FOSR + FOSR + 16 + 10 + + + FORD + FORD + 29 + 3 + + + + + DFSDM_FLT5JDATAR + DFSDM_FLT5JDATAR + DFSDM filter 5 data register for injected group + 0x398 + 0x20 + read-only + 0x00000000 + + + JDATACH + JDATACH + 0 + 3 + + + JDATA + JDATA + 8 + 24 + + + + + DFSDM_FLT5RDATAR + DFSDM_FLT5RDATAR + DFSDM filter 5 data register for the regular channel + 0x39C + 0x20 + read-only + 0x00000000 + + + RDATACH + RDATACH + 0 + 3 + + + RPEND + RPEND + 4 + 1 + + + RDATA + RDATA + 8 + 24 + + + + + DFSDM_FLT5AWHTR + DFSDM_FLT5AWHTR + DFSDM filter 5 analog watchdog high threshold register + 0x3A0 + 0x20 + read-write + 0x00000000 + + + BKAWH + BKAWH + 0 + 4 + + + AWHT + AWHT + 8 + 24 + + + + + DFSDM_FLT5AWLTR + DFSDM_FLT5AWLTR + DFSDM filter 5 analog watchdog low threshold register + 0x3A4 + 0x20 + read-write + 0x00000000 + + + BKAWL + BKAWL + 0 + 4 + + + AWLT + AWLT + 8 + 24 + + + + + DFSDM_FLT5AWSR + DFSDM_FLT5AWSR + DFSDM filter 5 analog watchdog status register + 0x3A8 + 0x20 + read-only + 0x00000000 + + + AWLTF + AWLTF + 0 + 8 + + + AWHTF + AWHTF + 8 + 8 + + + + + DFSDM_FLT5AWCFR + DFSDM_FLT5AWCFR + DFSDM filter 5 analog watchdog clear flag register + 0x3AC + 0x20 + read-write + 0x00000000 + + + CLRAWLTF + CLRAWLTF + 0 + 8 + + + CLRAWHTF + CLRAWHTF + 8 + 8 + + + + + DFSDM_FLT5EXMAX + DFSDM_FLT5EXMAX + DFSDM filter 5 extremes detector maximum register + 0x3B0 + 0x20 + read-only + 0x80000000 + + + EXMAXCH + EXMAXCH + 0 + 3 + + + EXMAX + EXMAX + 8 + 24 + + + + + DFSDM_FLT5EXMIN + DFSDM_FLT5EXMIN + DFSDM filter 5 extremes detector minimum register + 0x3B4 + 0x20 + 0x7FFFFF00 + + + EXMINCH + EXMINCH + 0 + 3 + read-only + + + EXMIN + EXMIN + 8 + 24 + read-write + + + + + DFSDM_FLT5CNVTIMR + DFSDM_FLT5CNVTIMR + DFSDM filter 5 conversion timer register + 0x3B8 + 0x20 + read-only + 0x00000000 + + + CNVCNT + CNVCNT + 4 + 28 + + + + + DFSDM_HWCFGR + DFSDM_HWCFGR + This register specifies the hardware configuration of DFSDM peripheral. + 0x7F0 + 0x20 + read-only + 0x00000608 + + + NBT + NBT + 0 + 8 + + + NBF + NBF + 8 + 8 + + + + + DFSDM_VERR + DFSDM_VERR + This register specifies the version of DFSDM peripheral. + 0x7F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DFSDM_IPIDR + DFSDM_IPIDR + This register specifies the identification of DFSDM peripheral. + 0x7F8 + 0x20 + read-only + 0x00110031 + + + ID + ID + 0 + 32 + + + + + DFSDM_SIDR + DFSDM_SIDR + This register specifies the size allocated to DFSDM registers. + 0x7FC + 0x20 + read-only + 0xA3C5DD02 + + + SID + SID + 0 + 32 + + + + + + + DMA1 + DMA1 + DMA1 + 0x48000000 + + 0x0 + 0x400 + registers + + + + DMA_LISR + DMA_LISR + DMA low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + FEIF0 + FEIF0 + 0 + 1 + + + DMEIF0 + DMEIF0 + 2 + 1 + + + TEIF0 + TEIF0 + 3 + 1 + + + HTIF0 + HTIF0 + 4 + 1 + + + TCIF0 + TCIF0 + 5 + 1 + + + FEIF1 + FEIF1 + 6 + 1 + + + DMEIF1 + DMEIF1 + 8 + 1 + + + TEIF1 + TEIF1 + 9 + 1 + + + HTIF1 + HTIF1 + 10 + 1 + + + TCIF1 + TCIF1 + 11 + 1 + + + FEIF2 + FEIF2 + 16 + 1 + + + DMEIF2 + DMEIF2 + 18 + 1 + + + TEIF2 + TEIF2 + 19 + 1 + + + HTIF2 + HTIF2 + 20 + 1 + + + TCIF2 + TCIF2 + 21 + 1 + + + FEIF3 + FEIF3 + 22 + 1 + + + DMEIF3 + DMEIF3 + 24 + 1 + + + TEIF3 + TEIF3 + 25 + 1 + + + HTIF3 + HTIF3 + 26 + 1 + + + TCIF3 + TCIF3 + 27 + 1 + + + + + DMA_HISR + DMA_HISR + DMA high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + FEIF4 + FEIF4 + 0 + 1 + + + DMEIF4 + DMEIF4 + 2 + 1 + + + TEIF4 + TEIF4 + 3 + 1 + + + HTIF4 + HTIF4 + 4 + 1 + + + TCIF4 + TCIF4 + 5 + 1 + + + FEIF5 + FEIF5 + 6 + 1 + + + DMEIF5 + DMEIF5 + 8 + 1 + + + TEIF5 + TEIF5 + 9 + 1 + + + HTIF5 + HTIF5 + 10 + 1 + + + TCIF5 + TCIF5 + 11 + 1 + + + FEIF6 + FEIF6 + 16 + 1 + + + DMEIF6 + DMEIF6 + 18 + 1 + + + TEIF6 + TEIF6 + 19 + 1 + + + HTIF6 + HTIF6 + 20 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + FEIF7 + FEIF7 + 22 + 1 + + + DMEIF7 + DMEIF7 + 24 + 1 + + + TEIF7 + TEIF7 + 25 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 27 + 1 + + + + + DMA_LIFCR + DMA_LIFCR + DMA low interrupt flag clear register + 0x8 + 0x20 + write-only + 0x00000000 + + + CFEIF0 + CFEIF0 + 0 + 1 + + + CDMEIF0 + CDMEIF0 + 2 + 1 + + + CTEIF0 + CTEIF0 + 3 + 1 + + + CHTIF0 + CHTIF0 + 4 + 1 + + + CTCIF0 + CTCIF0 + 5 + 1 + + + CFEIF1 + CFEIF1 + 6 + 1 + + + CDMEIF1 + CDMEIF1 + 8 + 1 + + + CTEIF1 + CTEIF1 + 9 + 1 + + + CHTIF1 + CHTIF1 + 10 + 1 + + + CTCIF1 + CTCIF1 + 11 + 1 + + + CFEIF2 + CFEIF2 + 16 + 1 + + + CDMEIF2 + CDMEIF2 + 18 + 1 + + + CTEIF2 + CTEIF2 + 19 + 1 + + + CHTIF2 + CHTIF2 + 20 + 1 + + + CTCIF2 + CTCIF2 + 21 + 1 + + + CFEIF3 + CFEIF3 + 22 + 1 + + + CDMEIF3 + CDMEIF3 + 24 + 1 + + + CTEIF3 + CTEIF3 + 25 + 1 + + + CHTIF3 + CHTIF3 + 26 + 1 + + + CTCIF3 + CTCIF3 + 27 + 1 + + + + + DMA_HIFCR + DMA_HIFCR + DMA high interrupt flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CFEIF4 + CFEIF4 + 0 + 1 + + + CDMEIF4 + CDMEIF4 + 2 + 1 + + + CTEIF4 + CTEIF4 + 3 + 1 + + + CHTIF4 + CHTIF4 + 4 + 1 + + + CTCIF4 + CTCIF4 + 5 + 1 + + + CFEIF5 + CFEIF5 + 6 + 1 + + + CDMEIF5 + CDMEIF5 + 8 + 1 + + + CTEIF5 + CTEIF5 + 9 + 1 + + + CHTIF5 + CHTIF5 + 10 + 1 + + + CTCIF5 + CTCIF5 + 11 + 1 + + + CFEIF6 + CFEIF6 + 16 + 1 + + + CDMEIF6 + CDMEIF6 + 18 + 1 + + + CTEIF6 + CTEIF6 + 19 + 1 + + + CHTIF6 + CHTIF6 + 20 + 1 + + + CTCIF6 + CTCIF6 + 21 + 1 + + + CFEIF7 + CFEIF7 + 22 + 1 + + + CDMEIF7 + CDMEIF7 + 24 + 1 + + + CTEIF7 + CTEIF7 + 25 + 1 + + + CHTIF7 + CHTIF7 + 26 + 1 + + + CTCIF7 + CTCIF7 + 27 + 1 + + + + + DMA_S0CR + DMA_S0CR + This register is used to configure the concerned stream. + 0x10 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S0NDTR + DMA_S0NDTR + DMA stream 0 number of data register + 0x14 + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S0PAR + DMA_S0PAR + DMA stream 0 peripheral address register + 0x18 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S0M0AR + DMA_S0M0AR + DMA stream 0 memory 0 address register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S0M1AR + DMA_S0M1AR + DMA stream 0 memory 1 address register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S0FCR + DMA_S0FCR + DMA stream 0 FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S1CR + DMA_S1CR + This register is used to configure the concerned stream. + 0x28 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S1NDTR + DMA_S1NDTR + DMA stream 1 number of data register + 0x2C + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S1PAR + DMA_S1PAR + DMA stream 1 peripheral address register + 0x30 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S1M0AR + DMA_S1M0AR + DMA stream 1 memory 0 address register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S1M1AR + DMA_S1M1AR + DMA stream 1 memory 1 address register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S1FCR + DMA_S1FCR + DMA stream 1 FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S2CR + DMA_S2CR + This register is used to configure the concerned stream. + 0x40 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S2NDTR + DMA_S2NDTR + DMA stream 2 number of data register + 0x44 + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S2PAR + DMA_S2PAR + DMA stream 2 peripheral address register + 0x48 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S2M0AR + DMA_S2M0AR + DMA stream 2 memory 0 address register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S2M1AR + DMA_S2M1AR + DMA stream 2 memory 1 address register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S2FCR + DMA_S2FCR + DMA stream 2 FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S3CR + DMA_S3CR + This register is used to configure the concerned stream. + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S3NDTR + DMA_S3NDTR + DMA stream 3 number of data register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S3PAR + DMA_S3PAR + DMA stream 3 peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S3M0AR + DMA_S3M0AR + DMA stream 3 memory 0 address register + 0x64 + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S3M1AR + DMA_S3M1AR + DMA stream 3 memory 1 address register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S3FCR + DMA_S3FCR + DMA stream 3 FIFO control register + 0x6C + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S4CR + DMA_S4CR + This register is used to configure the concerned stream. + 0x70 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S4NDTR + DMA_S4NDTR + DMA stream 4 number of data register + 0x74 + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S4PAR + DMA_S4PAR + DMA stream 4 peripheral address register + 0x78 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S4M0AR + DMA_S4M0AR + DMA stream 4 memory 0 address register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S4M1AR + DMA_S4M1AR + DMA stream 4 memory 1 address register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S4FCR + DMA_S4FCR + DMA stream 4 FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S5CR + DMA_S5CR + This register is used to configure the concerned stream. + 0x88 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S5NDTR + DMA_S5NDTR + DMA stream 5 number of data register + 0x8C + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S5PAR + DMA_S5PAR + DMA stream 5 peripheral address register + 0x90 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S5M0AR + DMA_S5M0AR + DMA stream 5 memory 0 address register + 0x94 + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S5M1AR + DMA_S5M1AR + DMA stream 5 memory 1 address register + 0x98 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S5FCR + DMA_S5FCR + DMA stream 5 FIFO control register + 0x9C + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S6CR + DMA_S6CR + This register is used to configure the concerned stream. + 0xA0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S6NDTR + DMA_S6NDTR + DMA stream 6 number of data register + 0xA4 + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S6PAR + DMA_S6PAR + DMA stream 6 peripheral address register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S6M0AR + DMA_S6M0AR + DMA stream 6 memory 0 address register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S6M1AR + DMA_S6M1AR + DMA stream 6 memory 1 address register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S6FCR + DMA_S6FCR + DMA stream 6 FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_S7CR + DMA_S7CR + This register is used to configure the concerned stream. + 0xB8 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + DMEIE + DMEIE + 1 + 1 + + + TEIE + TEIE + 2 + 1 + + + HTIE + HTIE + 3 + 1 + + + TCIE + TCIE + 4 + 1 + + + PFCTRL + PFCTRL + 5 + 1 + + + DIR + DIR + 6 + 2 + + + CIRC + CIRC + 8 + 1 + + + PINC + PINC + 9 + 1 + + + MINC + MINC + 10 + 1 + + + PSIZE + PSIZE + 11 + 2 + + + MSIZE + MSIZE + 13 + 2 + + + PINCOS + PINCOS + 15 + 1 + + + PL + PL + 16 + 2 + + + DBM + DBM + 18 + 1 + + + CT + CT + 19 + 1 + + + PBURST + PBURST + 21 + 2 + + + MBURST + MBURST + 23 + 2 + + + + + DMA_S7NDTR + DMA_S7NDTR + DMA stream 7 number of data register + 0xBC + 0x20 + read-write + 0x00000000 + + + NDT + NDT + 0 + 16 + + + + + DMA_S7PAR + DMA_S7PAR + DMA stream 7 peripheral address register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PAR + PAR + 0 + 32 + + + + + DMA_S7M0AR + DMA_S7M0AR + DMA stream 7 memory 0 address register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0A + M0A + 0 + 32 + + + + + DMA_S7M1AR + DMA_S7M1AR + DMA stream 7 memory 1 address register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1A + M1A + 0 + 32 + + + + + DMA_S7FCR + DMA_S7FCR + DMA stream 7 FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FTH + FTH + 0 + 2 + read-write + + + DMDIS + DMDIS + 2 + 1 + read-write + + + FS + FS + 3 + 3 + read-only + + + FEIE + FEIE + 7 + 1 + read-write + + + + + DMA_HWCFGR2 + DMA_HWCFGR2 + DMA hardware configuration 2register + 0x3EC + 0x20 + read-only + 0x00000001 + + + FIFO_SIZE + FIFO_SIZE + 0 + 2 + + + WRITE_BUFFERABLE + WRITE_BUFFERABLE + 4 + 1 + + + CHSEL_WIDTH + CHSEL_WIDTH + 8 + 3 + + + + + DMA_HWCFGR1 + DMA_HWCFGR1 + DMA hardware configuration 1 register + 0x3F0 + 0x20 + read-only + 0x22222222 + + + DMA_DEF0 + DMA_DEF0 + 0 + 2 + + + DMA_DEF1 + DMA_DEF1 + 4 + 2 + + + DMA_DEF2 + DMA_DEF2 + 8 + 2 + + + DMA_DEF3 + DMA_DEF3 + 12 + 2 + + + DMA_DEF4 + DMA_DEF4 + 16 + 2 + + + DMA_DEF5 + DMA_DEF5 + 20 + 2 + + + DMA_DEF6 + DMA_DEF6 + 24 + 2 + + + DMA_DEF7 + DMA_DEF7 + 28 + 2 + + + + + DMA_VERR + DMA_VERR + This register identifies the version of the IP. + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DMA_IPDR + DMA_IPDR + DMA IP identification register + 0x3F8 + 0x20 + read-only + 0x00100002 + + + ID + ID + 0 + 32 + + + + + DMA_SIDR + DMA_SIDR + DMA size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DMA2 + 0x48001000 + + + DMAMUX1 + DMAMUX1 + DMAMUX1 + 0x48002000 + + 0x0 + 0x400 + registers + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C8CR + DMAMUX_C8CR + DMAMUX request line multiplexer channel 8 configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C9CR + DMAMUX_C9CR + DMAMUX request line multiplexer channel 9 configuration register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C10CR + DMAMUX_C10CR + DMAMUX request line multiplexer channel 10 configuration register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C11CR + DMAMUX_C11CR + DMAMUX request line multiplexer channel 11 configuration register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C12CR + DMAMUX_C12CR + DMAMUX request line multiplexer channel 12 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C13CR + DMAMUX_C13CR + DMAMUX request line multiplexer channel 13 configuration register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C14CR + DMAMUX_C14CR + DMAMUX request line multiplexer channel 14 configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_C15CR + DMAMUX_C15CR + DMAMUX request line multiplexer channel 15 configuration register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + DMAREQ_ID + 0 + 7 + + + SOIE + SOIE + 8 + 1 + + + EGE + EGE + 9 + 1 + + + SE + SE + 16 + 1 + + + SPOL + SPOL + 17 + 2 + + + NBREQ + NBREQ + 19 + 5 + + + SYNC_ID + SYNC_ID + 24 + 3 + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF0 + SOF0 + 0 + 1 + + + SOF1 + SOF1 + 1 + 1 + + + SOF2 + SOF2 + 2 + 1 + + + SOF3 + SOF3 + 3 + 1 + + + SOF4 + SOF4 + 4 + 1 + + + SOF5 + SOF5 + 5 + 1 + + + SOF6 + SOF6 + 6 + 1 + + + SOF7 + SOF7 + 7 + 1 + + + SOF8 + SOF8 + 8 + 1 + + + SOF9 + SOF9 + 9 + 1 + + + SOF10 + SOF10 + 10 + 1 + + + SOF11 + SOF11 + 11 + 1 + + + SOF12 + SOF12 + 12 + 1 + + + SOF13 + SOF13 + 13 + 1 + + + SOF14 + SOF14 + 14 + 1 + + + SOF15 + SOF15 + 15 + 1 + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF0 + CSOF0 + 0 + 1 + + + CSOF1 + CSOF1 + 1 + 1 + + + CSOF2 + CSOF2 + 2 + 1 + + + CSOF3 + CSOF3 + 3 + 1 + + + CSOF4 + CSOF4 + 4 + 1 + + + CSOF5 + CSOF5 + 5 + 1 + + + CSOF6 + CSOF6 + 6 + 1 + + + CSOF7 + CSOF7 + 7 + 1 + + + CSOF8 + CSOF8 + 8 + 1 + + + CSOF9 + CSOF9 + 9 + 1 + + + CSOF10 + CSOF10 + 10 + 1 + + + CSOF11 + CSOF11 + 11 + 1 + + + CSOF12 + CSOF12 + 12 + 1 + + + CSOF13 + CSOF13 + 13 + 1 + + + CSOF14 + CSOF14 + 14 + 1 + + + CSOF15 + CSOF15 + 15 + 1 + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG4CR + DMAMUX_RG4CR + DMAMUX request generator channel 4 configuration register + 0x110 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG5CR + DMAMUX_RG5CR + DMAMUX request generator channel 5 configuration register + 0x114 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG6CR + DMAMUX_RG6CR + DMAMUX request generator channel 6 configuration register + 0x118 + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RG7CR + DMAMUX_RG7CR + DMAMUX request generator channel 7 configuration register + 0x11C + 0x20 + read-write + 0x00000000 + + + SIG_ID + SIG_ID + 0 + 3 + + + OIE + OIE + 8 + 1 + + + GE + GE + 16 + 1 + + + GPOL + GPOL + 17 + 2 + + + GNBREQ + GNBREQ + 19 + 5 + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF0 + OF0 + 0 + 1 + + + OF1 + OF1 + 1 + 1 + + + OF2 + OF2 + 2 + 1 + + + OF3 + OF3 + 3 + 1 + + + OF4 + OF4 + 4 + 1 + + + OF5 + OF5 + 5 + 1 + + + OF6 + OF6 + 6 + 1 + + + OF7 + OF7 + 7 + 1 + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF0 + COF0 + 0 + 1 + + + COF1 + COF1 + 1 + 1 + + + COF2 + COF2 + 2 + 1 + + + COF3 + COF3 + 3 + 1 + + + COF4 + COF4 + 4 + 1 + + + COF5 + COF5 + 5 + 1 + + + COF6 + COF6 + 6 + 1 + + + COF7 + COF7 + 7 + 1 + + + + + DMAMUX_HWCFGR2 + DMAMUX_HWCFGR2 + DMAMUX hardware configuration 2 register + 0x3EC + 0x20 + read-only + 0x00000008 + + + NUM_DMA_EXT_REQ + NUM_DMA_EXT_REQ + 0 + 8 + + + + + DMAMUX_HWCFGR1 + DMAMUX_HWCFGR1 + DMAMUX hardware configuration 1 register + 0x3F0 + 0x20 + read-only + 0x08086C10 + + + NUM_DMA_STREAMS + NUM_DMA_STREAMS + 0 + 8 + + + NUM_DMA_PERIPH_REQ + NUM_DMA_PERIPH_REQ + 8 + 8 + + + NUM_DMA_TRIG + NUM_DMA_TRIG + 16 + 8 + + + NUM_DMA_REQGEN + NUM_DMA_REQGEN + 24 + 8 + + + + + DMAMUX_VERR + DMAMUX_VERR + This register identifies the IP version. + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DMAMUX_IPIDR + DMAMUX_IPIDR + This register identifies the IP. + 0x3F8 + 0x20 + read-only + 0x00100011 + + + ID + ID + 0 + 32 + + + + + DMAMUX_SIDR + DMAMUX_SIDR + DMAMUX size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + DSIHOST1 + DSIHOST1 + DSIHOST1 + 0x5A000000 + + 0x0 + 0x800 + registers + + + + DSI_VR + DSI_VR + DSI Host version register + 0x0 + 0x20 + read-only + 0x3133312A + + + VERSION + VERSION + 0 + 32 + + + + + DSI_CR + DSI_CR + DSI Host control register + 0x4 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + + + DSI_CCR + DSI_CCR + DSI Host clock control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TXECKDIV + TXECKDIV + 0 + 8 + + + TOCKDIV + TOCKDIV + 8 + 8 + + + + + DSI_LVCIDR + DSI_LVCIDR + DSI Host LTDC VCID register + 0xC + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCOLCR + DSI_LCOLCR + DSI Host LTDC color coding register + 0x10 + 0x20 + read-write + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPCR + DSI_LPCR + DSI Host LTDC polarity configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DEP + DEP + 0 + 1 + + + VSP + VSP + 1 + 1 + + + HSP + HSP + 2 + 1 + + + + + DSI_LPMCR + DSI_LPMCR + DSI Host low-power mode configuration register + 0x18 + 0x20 + read-write + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_PCR + DSI_PCR + DSI Host protocol configuration register + 0x2C + 0x20 + read-write + 0x00000000 + + + ETTXE + ETTXE + 0 + 1 + + + ETRXE + ETRXE + 1 + 1 + + + BTAE + BTAE + 2 + 1 + + + ECCRXE + ECCRXE + 3 + 1 + + + CRCRXE + CRCRXE + 4 + 1 + + + + + DSI_GVCIDR + DSI_GVCIDR + DSI Host generic VCID register + 0x30 + 0x20 + read-only + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_MCR + DSI_MCR + DSI Host mode configuration register + 0x34 + 0x20 + read-write + 0x00000001 + + + CMDM + CMDM + 0 + 1 + + + + + DSI_VMCR + DSI_VMCR + DSI Host video mode configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 8 + 1 + + + LPVBPE + LPVBPE + 9 + 1 + + + LPVFPE + LPVFPE + 10 + 1 + + + LPVAE + LPVAE + 11 + 1 + + + LPHBPE + LPHBPE + 12 + 1 + + + LPHFPE + LPHFPE + 13 + 1 + + + FBTAAE + FBTAAE + 14 + 1 + + + LPCE + LPCE + 15 + 1 + + + PGE + PGE + 16 + 1 + + + PGM + PGM + 20 + 1 + + + PGO + PGO + 24 + 1 + + + + + DSI_VPCR + DSI_VPCR + DSI Host video packet configuration register + 0x3C + 0x20 + read-write + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCR + DSI_VCCR + DSI Host video chunks configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCR + DSI_VNPCR + DSI Host video null packet configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACR + DSI_VHSACR + DSI Host video HSA configuration register + 0x48 + 0x20 + read-write + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCR + DSI_VHBPCR + DSI Host video HBP configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCR + DSI_VLCR + DSI Host video line configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACR + DSI_VVSACR + DSI Host video VSA configuration register + 0x54 + 0x20 + read-write + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCR + DSI_VVBPCR + DSI Host video VBP configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCR + DSI_VVFPCR + DSI Host video VFP configuration register + 0x5C + 0x20 + read-write + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACR + DSI_VVACR + DSI Host video VA configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_LCCR + DSI_LCCR + DSI Host LTDC command configuration register + 0x64 + 0x20 + read-write + 0x00000000 + + + CMDSIZE + CMDSIZE + 0 + 16 + + + + + DSI_CMCR + DSI_CMCR + DSI Host command mode configuration register + 0x68 + 0x20 + read-write + 0x00000000 + + + TEARE + TEARE + 0 + 1 + + + ARE + ARE + 1 + 1 + + + GSW0TX + GSW0TX + 8 + 1 + + + GSW1TX + GSW1TX + 9 + 1 + + + GSW2TX + GSW2TX + 10 + 1 + + + GSR0TX + GSR0TX + 11 + 1 + + + GSR1TX + GSR1TX + 12 + 1 + + + GSR2TX + GSR2TX + 13 + 1 + + + GLWTX + GLWTX + 14 + 1 + + + DSW0TX + DSW0TX + 16 + 1 + + + DSW1TX + DSW1TX + 17 + 1 + + + DSR0TX + DSR0TX + 18 + 1 + + + DLWTX + DLWTX + 19 + 1 + + + MRDPS + MRDPS + 24 + 1 + + + + + DSI_GHCR + DSI_GHCR + DSI Host generic header configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + DT + 0 + 6 + + + VCID + VCID + 6 + 2 + + + WCLSB + WCLSB + 8 + 8 + + + WCMSB + WCMSB + 16 + 8 + + + + + DSI_GPDR + DSI_GPDR + DSI Host generic payload data register + 0x70 + 0x20 + read-write + 0x00000000 + + + DATA1 + DATA1 + 0 + 8 + + + DATA2 + DATA2 + 8 + 8 + + + DATA3 + DATA3 + 16 + 8 + + + DATA4 + DATA4 + 24 + 8 + + + + + DSI_GPSR + DSI_GPSR + DSI Host generic packet status register + 0x74 + 0x20 + read-only + 0x00000015 + + + CMDFE + CMDFE + 0 + 1 + + + CMDFF + CMDFF + 1 + 1 + + + PWRFE + PWRFE + 2 + 1 + + + PWRFF + PWRFF + 3 + 1 + + + PRDFE + PRDFE + 4 + 1 + + + PRDFF + PRDFF + 5 + 1 + + + RCB + RCB + 6 + 1 + + + + + DSI_TCCR0 + DSI_TCCR0 + DSI Host timeout counter configuration register 0 + 0x78 + 0x20 + read-write + 0x00000000 + + + LPRX_TOCNT + LPRX_TOCNT + 0 + 16 + + + HSTX_TOCNT + HSTX_TOCNT + 16 + 16 + + + + + DSI_TCCR1 + DSI_TCCR1 + DSI Host timeout counter configuration register 1 + 0x7C + 0x20 + read-write + 0x00000000 + + + HSRD_TOCNT + HSRD_TOCNT + 0 + 16 + + + + + DSI_TCCR2 + DSI_TCCR2 + DSI Host timeout counter configuration register 2 + 0x80 + 0x20 + read-write + 0x00000000 + + + LPRD_TOCNT + LPRD_TOCNT + 0 + 16 + + + + + DSI_TCCR3 + DSI_TCCR3 + DSI Host timeout counter configuration register 3 + 0x84 + 0x20 + read-write + 0x00000000 + + + HSWR_TOCNT + HSWR_TOCNT + 0 + 16 + + + PM + PM + 24 + 1 + + + + + DSI_TCCR4 + DSI_TCCR4 + DSI Host timeout counter configuration register 4 + 0x88 + 0x20 + read-write + 0x00000000 + + + LPWR_TOCNT + LPWR_TOCNT + 0 + 16 + + + + + DSI_TCCR5 + DSI_TCCR5 + DSI Host timeout counter configuration register 5 + 0x8C + 0x20 + read-write + 0x00000000 + + + BTA_TOCNT + BTA_TOCNT + 0 + 16 + + + + + DSI_CLCR + DSI_CLCR + DSI Host clock lane configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + DPCC + DPCC + 0 + 1 + + + ACR + ACR + 1 + 1 + + + + + DSI_CLTCR + DSI_CLTCR + DSI Host clock lane timer configuration register + 0x98 + 0x20 + read-write + 0x00000000 + + + LP2HS_TIME + LP2HS_TIME + 0 + 10 + + + HS2LP_TIME + HS2LP_TIME + 16 + 10 + + + + + DSI_DLTCR + DSI_DLTCR + DSI Host data lane timer configuration register + 0x9C + 0x20 + read-write + 0x00000000 + + + LP2HS_TIME + LP2HS_TIME + 0 + 10 + + + HS2LP_TIME + HS2LP_TIME + 16 + 10 + + + + + DSI_PCTLR + DSI_PCTLR + DSI Host PHY control register + 0xA0 + 0x20 + read-write + 0x00000000 + + + DEN + DEN + 1 + 1 + + + CKE + CKE + 2 + 1 + + + + + DSI_PCONFR + DSI_PCONFR + DSI Host PHY configuration register + 0xA4 + 0x20 + read-write + 0x00000001 + + + NL + NL + 0 + 2 + + + SW_TIME + SW_TIME + 8 + 8 + + + + + DSI_PUCR + DSI_PUCR + DSI Host PHY ULPS control register + 0xA8 + 0x20 + read-write + 0x00000000 + + + URCL + URCL + 0 + 1 + + + UECL + UECL + 1 + 1 + + + URDL + URDL + 2 + 1 + + + UEDL + UEDL + 3 + 1 + + + + + DSI_PTTCR + DSI_PTTCR + DSI Host PHY TX triggers configuration register + 0xAC + 0x20 + read-write + 0x00000000 + + + TX_TRIG + TX_TRIG + 0 + 4 + + + + + DSI_PSR + DSI_PSR + DSI Host PHY status register + 0xB0 + 0x20 + read-only + 0x00001528 + + + PD + PD + 1 + 1 + + + PSSC + PSSC + 2 + 1 + + + UANC + UANC + 3 + 1 + + + PSS0 + PSS0 + 4 + 1 + + + UAN0 + UAN0 + 5 + 1 + + + RUE0 + RUE0 + 6 + 1 + + + PSS1 + PSS1 + 7 + 1 + + + UAN1 + UAN1 + 8 + 1 + + + + + DSI_ISR0 + DSI_ISR0 + DSI Host interrupt and status register 0 + 0xBC + 0x20 + read-only + 0x00000000 + + + AE0 + AE0 + 0 + 1 + + + AE1 + AE1 + 1 + 1 + + + AE2 + AE2 + 2 + 1 + + + AE3 + AE3 + 3 + 1 + + + AE4 + AE4 + 4 + 1 + + + AE5 + AE5 + 5 + 1 + + + AE6 + AE6 + 6 + 1 + + + AE7 + AE7 + 7 + 1 + + + AE8 + AE8 + 8 + 1 + + + AE9 + AE9 + 9 + 1 + + + AE10 + AE10 + 10 + 1 + + + AE11 + AE11 + 11 + 1 + + + AE12 + AE12 + 12 + 1 + + + AE13 + AE13 + 13 + 1 + + + AE14 + AE14 + 14 + 1 + + + AE15 + AE15 + 15 + 1 + + + PE0 + PE0 + 16 + 1 + + + PE1 + PE1 + 17 + 1 + + + PE2 + PE2 + 18 + 1 + + + PE3 + PE3 + 19 + 1 + + + PE4 + PE4 + 20 + 1 + + + + + DSI_ISR1 + DSI_ISR1 + DSI Host interrupt and status register 1 + 0xC0 + 0x20 + read-only + 0x00000000 + + + TOHSTX + TOHSTX + 0 + 1 + + + TOLPRX + TOLPRX + 1 + 1 + + + ECCSE + ECCSE + 2 + 1 + + + ECCME + ECCME + 3 + 1 + + + CRCE + CRCE + 4 + 1 + + + PSE + PSE + 5 + 1 + + + EOTPE + EOTPE + 6 + 1 + + + LPWRE + LPWRE + 7 + 1 + + + GCWRE + GCWRE + 8 + 1 + + + GPWRE + GPWRE + 9 + 1 + + + GPTXE + GPTXE + 10 + 1 + + + GPRDE + GPRDE + 11 + 1 + + + GPRXE + GPRXE + 12 + 1 + + + + + DSI_IER0 + DSI_IER0 + DSI Host interrupt enable register 0 + 0xC4 + 0x20 + read-write + 0x00000000 + + + AE0IE + AE0IE + 0 + 1 + + + AE1IE + AE1IE + 1 + 1 + + + AE2IE + AE2IE + 2 + 1 + + + AE3IE + AE3IE + 3 + 1 + + + AE4IE + AE4IE + 4 + 1 + + + AE5IE + AE5IE + 5 + 1 + + + AE6IE + AE6IE + 6 + 1 + + + AE7IE + AE7IE + 7 + 1 + + + AE8IE + AE8IE + 8 + 1 + + + AE9IE + AE9IE + 9 + 1 + + + AE10IE + AE10IE + 10 + 1 + + + AE11IE + AE11IE + 11 + 1 + + + AE12IE + AE12IE + 12 + 1 + + + AE13IE + AE13IE + 13 + 1 + + + AE14IE + AE14IE + 14 + 1 + + + AE15IE + AE15IE + 15 + 1 + + + PE0IE + PE0IE + 16 + 1 + + + PE1IE + PE1IE + 17 + 1 + + + PE2IE + PE2IE + 18 + 1 + + + PE3IE + PE3IE + 19 + 1 + + + PE4IE + PE4IE + 20 + 1 + + + + + DSI_IER1 + DSI_IER1 + DSI Host interrupt enable register 1 + 0xC8 + 0x20 + read-write + 0x00000000 + + + TOHSTXIE + TOHSTXIE + 0 + 1 + + + TOLPRXIE + TOLPRXIE + 1 + 1 + + + ECCSEIE + ECCSEIE + 2 + 1 + + + ECCMEIE + ECCMEIE + 3 + 1 + + + CRCEIE + CRCEIE + 4 + 1 + + + PSEIE + PSEIE + 5 + 1 + + + EOTPEIE + EOTPEIE + 6 + 1 + + + LPWREIE + LPWREIE + 7 + 1 + + + GCWREIE + GCWREIE + 8 + 1 + + + GPWREIE + GPWREIE + 9 + 1 + + + GPTXEIE + GPTXEIE + 10 + 1 + + + GPRDEIE + GPRDEIE + 11 + 1 + + + GPRXEIE + GPRXEIE + 12 + 1 + + + + + DSI_FIR0 + DSI_FIR0 + DSI Host force interrupt register 0 + 0xD8 + 0x20 + write-only + 0x00000000 + + + FAE0 + FAE0 + 0 + 1 + + + FAE1 + FAE1 + 1 + 1 + + + FAE2 + FAE2 + 2 + 1 + + + FAE3 + FAE3 + 3 + 1 + + + FAE4 + FAE4 + 4 + 1 + + + FAE5 + FAE5 + 5 + 1 + + + FAE6 + FAE6 + 6 + 1 + + + FAE7 + FAE7 + 7 + 1 + + + FAE8 + FAE8 + 8 + 1 + + + FAE9 + FAE9 + 9 + 1 + + + FAE10 + FAE10 + 10 + 1 + + + FAE11 + FAE11 + 11 + 1 + + + FAE12 + FAE12 + 12 + 1 + + + FAE13 + FAE13 + 13 + 1 + + + FAE14 + FAE14 + 14 + 1 + + + FAE15 + FAE15 + 15 + 1 + + + FPE0 + FPE0 + 16 + 1 + + + FPE1 + FPE1 + 17 + 1 + + + FPE2 + FPE2 + 18 + 1 + + + FPE3 + FPE3 + 19 + 1 + + + FPE4 + FPE4 + 20 + 1 + + + + + DSI_FIR1 + DSI_FIR1 + DSI Host force interrupt register 1 + 0xDC + 0x20 + write-only + 0x00000000 + + + FTOHSTX + FTOHSTX + 0 + 1 + + + FTOLPRX + FTOLPRX + 1 + 1 + + + FECCSE + FECCSE + 2 + 1 + + + FECCME + FECCME + 3 + 1 + + + FCRCE + FCRCE + 4 + 1 + + + FPSE + FPSE + 5 + 1 + + + FEOTPE + FEOTPE + 6 + 1 + + + FLPWRE + FLPWRE + 7 + 1 + + + FGCWRE + FGCWRE + 8 + 1 + + + FGPWRE + FGPWRE + 9 + 1 + + + FGPTXE + FGPTXE + 10 + 1 + + + FGPRDE + FGPRDE + 11 + 1 + + + FGPRXE + FGPRXE + 12 + 1 + + + + + DSI_DLTRCR + DSI_DLTRCR + DSI Host data lane timer read configuration register + 0xF4 + 0x20 + read-write + 0x00000000 + + + MRD_TIME + MRD_TIME + 0 + 15 + + + + + DSI_VSCR + DSI_VSCR + DSI Host video shadow control register + 0x100 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + UR + UR + 8 + 1 + + + + + DSI_LCVCIDR + DSI_LCVCIDR + DSI Host LTDC current VCID register + 0x10C + 0x20 + read-write + 0x00000000 + + + VCID + VCID + 0 + 2 + + + + + DSI_LCCCR + DSI_LCCCR + DSI Host LTDC current color coding register + 0x110 + 0x20 + read-only + 0x00000000 + + + COLC + COLC + 0 + 4 + + + LPE + LPE + 8 + 1 + + + + + DSI_LPMCCR + DSI_LPMCCR + DSI Host low-power mode current configuration register + 0x118 + 0x20 + read-only + 0x00000000 + + + VLPSIZE + VLPSIZE + 0 + 8 + + + LPSIZE + LPSIZE + 16 + 8 + + + + + DSI_VMCCR + DSI_VMCCR + DSI Host video mode current configuration register + 0x138 + 0x20 + read-only + 0x00000000 + + + VMT + VMT + 0 + 2 + + + LPVSAE + LPVSAE + 2 + 1 + + + LPVBPE + LPVBPE + 3 + 1 + + + LPVFPE + LPVFPE + 4 + 1 + + + LPVAE + LPVAE + 5 + 1 + + + LPHBPE + LPHBPE + 6 + 1 + + + LPHFE + LPHFE + 7 + 1 + + + FBTAAE + FBTAAE + 8 + 1 + + + LPCE + LPCE + 9 + 1 + + + + + DSI_VPCCR + DSI_VPCCR + DSI Host video packet current configuration register + 0x13C + 0x20 + read-only + 0x00000000 + + + VPSIZE + VPSIZE + 0 + 14 + + + + + DSI_VCCCR + DSI_VCCCR + DSI Host video chunks current configuration register + 0x140 + 0x20 + read-only + 0x00000000 + + + NUMC + NUMC + 0 + 13 + + + + + DSI_VNPCCR + DSI_VNPCCR + DSI Host video null packet current configuration register + 0x144 + 0x20 + read-only + 0x00000000 + + + NPSIZE + NPSIZE + 0 + 13 + + + + + DSI_VHSACCR + DSI_VHSACCR + DSI Host video HSA current configuration register + 0x148 + 0x20 + read-only + 0x00000000 + + + HSA + HSA + 0 + 12 + + + + + DSI_VHBPCCR + DSI_VHBPCCR + DSI Host video HBP current configuration register + 0x14C + 0x20 + read-only + 0x00000000 + + + HBP + HBP + 0 + 12 + + + + + DSI_VLCCR + DSI_VLCCR + DSI Host video line current configuration register + 0x150 + 0x20 + read-only + 0x00000000 + + + HLINE + HLINE + 0 + 15 + + + + + DSI_VVSACCR + DSI_VVSACCR + DSI Host video VSA current configuration register + 0x154 + 0x20 + read-only + 0x00000000 + + + VSA + VSA + 0 + 10 + + + + + DSI_VVBPCCR + DSI_VVBPCCR + DSI Host video VBP current configuration register + 0x158 + 0x20 + read-only + 0x00000000 + + + VBP + VBP + 0 + 10 + + + + + DSI_VVFPCCR + DSI_VVFPCCR + DSI Host video VFP current configuration register + 0x15C + 0x20 + read-only + 0x00000000 + + + VFP + VFP + 0 + 10 + + + + + DSI_VVACCR + DSI_VVACCR + DSI Host video VA current configuration register + 0x160 + 0x20 + read-only + 0x00000000 + + + VA + VA + 0 + 14 + + + + + DSI_WCFGR + DSI_WCFGR + DSI wrapper configuration register + 0x400 + 0x20 + read-write + 0x00000000 + + + DSIM + DSIM + 0 + 1 + + + COLMUX + COLMUX + 1 + 3 + + + TESRC + TESRC + 4 + 1 + + + TEPOL + TEPOL + 5 + 1 + + + AR + AR + 6 + 1 + + + VSPOL + VSPOL + 7 + 1 + + + + + DSI_WCR + DSI_WCR + DSI wrapper control register + 0x404 + 0x20 + read-write + 0x00000000 + + + COLM + COLM + 0 + 1 + + + SHTDN + SHTDN + 1 + 1 + + + LTDCEN + LTDCEN + 2 + 1 + + + DSIEN + DSIEN + 3 + 1 + + + + + DSI_WIER + DSI_WIER + DSI wrapper interrupt enable register + 0x408 + 0x20 + read-write + 0x00000000 + + + TEIE + TEIE + 0 + 1 + + + ERIE + ERIE + 1 + 1 + + + PLLLIE + PLLLIE + 9 + 1 + + + PLLUIE + PLLUIE + 10 + 1 + + + RRIE + RRIE + 13 + 1 + + + + + DSI_WISR + DSI_WISR + DSI wrapper interrupt and status register + 0x40C + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + ERIF + ERIF + 1 + 1 + + + BUSY + BUSY + 2 + 1 + + + PLLLS + PLLLS + 8 + 1 + + + PLLLIF + PLLLIF + 9 + 1 + + + PLLUIF + PLLUIF + 10 + 1 + + + RRS + RRS + 12 + 1 + + + RRIF + RRIF + 13 + 1 + + + + + DSI_WIFCR + DSI_WIFCR + DSI wrapper interrupt flag clear register + 0x410 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CERIF + CERIF + 1 + 1 + + + CPLLLIF + CPLLLIF + 9 + 1 + + + CPLLUIF + CPLLUIF + 10 + 1 + + + CRRIF + CRRIF + 13 + 1 + + + + + DSI_WPCR0 + DSI_WPCR0 + DSI wrapper PHY configuration register 0 + 0x418 + 0x20 + read-write + 0x00000000 + + + UIX4 + UIX4 + 0 + 6 + + + SWCL + SWCL + 6 + 1 + + + SWDL0 + SWDL0 + 7 + 1 + + + SWDL1 + SWDL1 + 8 + 1 + + + HSICL + HSICL + 9 + 1 + + + HSIDL0 + HSIDL0 + 10 + 1 + + + HSIDL1 + HSIDL1 + 11 + 1 + + + FTXSMCL + FTXSMCL + 12 + 1 + + + FTXSMDL + FTXSMDL + 13 + 1 + + + CDOFFDL + CDOFFDL + 14 + 1 + + + TDDL + TDDL + 16 + 1 + + + + + DSI_WPCR1 + DSI_WPCR1 + This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + 0x41C + 0x20 + read-write + 0x00000000 + + + SKEWCL + SKEWCL + 0 + 2 + + + SKEWDL + SKEWDL + 2 + 2 + + + LPTXSRCL + LPTXSRCL + 6 + 2 + + + LPTXSRDL + LPTXSRDL + 8 + 2 + + + SDDCCL + SDDCCL + 12 + 1 + + + SDDCDL + SDDCDL + 13 + 1 + + + HSTXSRUCL + HSTXSRUCL + 16 + 1 + + + HSTXSRDCL + HSTXSRDCL + 17 + 1 + + + HSTXSRUDL + HSTXSRUDL + 18 + 1 + + + HSTXSRDDL + HSTXSRDDL + 19 + 1 + + + + + DSI_WRPCR + DSI_WRPCR + DSI wrapper regulator and PLL control register + 0x430 + 0x20 + read-write + 0x00000000 + + + PLLEN + PLLEN + 0 + 1 + + + NDIV + NDIV + 2 + 7 + + + IDF + IDF + 11 + 4 + + + ODF + ODF + 16 + 2 + + + REGEN + REGEN + 24 + 1 + + + BGREN + BGREN + 28 + 1 + + + + + DSI_HWCFGR + DSI_HWCFGR + DSI Host hardware configuration register + 0x7F0 + 0x20 + read-only + 0x00005A01 + + + TECHNO + TECHNO + 0 + 4 + + + FIFOSIZE + FIFOSIZE + 4 + 12 + + + + + DSI_VERR + DSI_VERR + DSI Host version register + 0x7F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + DSI_IPIDR + DSI_IPIDR + DSI Host identification register + 0x7F8 + 0x20 + read-only + 0x00160071 + + + ID + ID + 0 + 32 + + + + + DSI_SIDR + DSI_SIDR + DSI Host size identification register + 0x7FC + 0x20 + read-only + 0xA3C5DD02 + + + SID + SID + 0 + 32 + + + + + + + DTS + DTS register block + DTS + 0x50028000 + + 0x0 + 0x400 + registers + + + + DTS_CFGR1 + DTS_CFGR1 + DTS_CFGR1 is the configuration register for temperature sensor 1. + 0x0 + 0x20 + read-write + 0x00000000 + + + TS1_EN + TS1_EN + 0 + 1 + + + TS1_START + TS1_START + 4 + 1 + + + TS1_INTRIG_SEL + TS1_INTRIG_SEL + 8 + 4 + + + TS1_SMP_TIME + TS1_SMP_TIME + 16 + 4 + + + REFCLK_SEL + REFCLK_SEL + 20 + 1 + + + Q_MEAS_opt + Q_MEAS_opt + 21 + 1 + + + HSREF_CLK_DIV + HSREF_CLK_DIV + 24 + 7 + + + + + DTS_T0VALR1 + DTS_T0VALR1 + DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. + 0x8 + 0x20 + read-only + 0x00000000 + + + TS1_FMT0 + TS1_FMT0 + 0 + 16 + + + TS1_T0 + TS1_T0 + 16 + 2 + + + + + DTS_RAMPVALR + DTS_RAMPVALR + The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. + 0x10 + 0x20 + read-only + 0x00000000 + + + TS1_RAMP_COEFF + TS1_RAMP_COEFF + 0 + 16 + + + + + DTS_ITR1 + DTS_ITR1 + DTS_ITR1 contains the threshold values for sensor 1. + 0x14 + 0x20 + read-write + 0x00000000 + + + TS1_LITTHD + TS1_LITTHD + 0 + 16 + + + TS1_HITTHD + TS1_HITTHD + 16 + 16 + + + + + DTS_DR + DTS_DR + The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. + 0x1C + 0x20 + read-write + 0x00000000 + + + TS1_MFREQ + TS1_MFREQ + 0 + 16 + + + + + DTS_SR + DTS_SR + Temperature sensor status register + 0x20 + 0x20 + read-only + 0x00000000 + + + TS1_ITEF + TS1_ITEF + 0 + 1 + + + TS1_ITLF + TS1_ITLF + 1 + 1 + + + TS1_ITHF + TS1_ITHF + 2 + 1 + + + TS1_AITEF + TS1_AITEF + 4 + 1 + + + TS1_AITLF + TS1_AITLF + 5 + 1 + + + TS1_AITHF + TS1_AITHF + 6 + 1 + + + TS1_RDY + TS1_RDY + 15 + 1 + + + + + DTS_ITENR + DTS_ITENR + Temperature sensor interrupt enable register + 0x24 + 0x20 + read-write + 0x00000000 + + + TS1_ITEEN + TS1_ITEEN + 0 + 1 + + + TS1_ITLEN + TS1_ITLEN + 1 + 1 + + + TS1_ITHEN + TS1_ITHEN + 2 + 1 + + + TS1_AITEEN + TS1_AITEEN + 4 + 1 + + + TS1_AITLEN + TS1_AITLEN + 5 + 1 + + + TS1_AITHEN + TS1_AITHEN + 6 + 1 + + + + + DTS_ICIFR + DTS_ICIFR + DTS_ICIFR is the control register for the interrupt flags. + 0x28 + 0x20 + read-write + 0x00000000 + + + TS1_CITEF + TS1_CITEF + 0 + 1 + + + TS1_CITLF + TS1_CITLF + 1 + 1 + + + TS1_CITHF + TS1_CITHF + 2 + 1 + + + TS1_CAITEF + TS1_CAITEF + 4 + 1 + + + TS1_CAITLF + TS1_CAITLF + 5 + 1 + + + TS1_CAITHF + TS1_CAITHF + 6 + 1 + + + + + DTS_OR + DTS_OR + The DTS_OR contains general-purpose option bits. + 0x2C + 0x20 + read-write + 0x00000000 + + + TS_Op0 + TS_Op0 + 0 + 1 + + + TS_Op1 + TS_Op1 + 1 + 1 + + + TS_Op2 + TS_Op2 + 2 + 1 + + + TS_Op3 + TS_Op3 + 3 + 1 + + + TS_Op4 + TS_Op4 + 4 + 1 + + + TS_Op5 + TS_Op5 + 5 + 1 + + + TS_Op6 + TS_Op6 + 6 + 1 + + + TS_Op7 + TS_Op7 + 7 + 1 + + + TS_Op8 + TS_Op8 + 8 + 1 + + + TS_Op9 + TS_Op9 + 9 + 1 + + + TS_Op10 + TS_Op10 + 10 + 1 + + + TS_Op11 + TS_Op11 + 11 + 1 + + + TS_Op12 + TS_Op12 + 12 + 1 + + + TS_Op13 + TS_Op13 + 13 + 1 + + + TS_Op14 + TS_Op14 + 14 + 1 + + + TS_Op15 + TS_Op15 + 15 + 1 + + + TS_Op16 + TS_Op16 + 16 + 1 + + + TS_Op17 + TS_Op17 + 17 + 1 + + + TS_Op18 + TS_Op18 + 18 + 1 + + + TS_Op19 + TS_Op19 + 19 + 1 + + + TS_Op20 + TS_Op20 + 20 + 1 + + + TS_Op21 + TS_Op21 + 21 + 1 + + + TS_Op22 + TS_Op22 + 22 + 1 + + + TS_Op23 + TS_Op23 + 23 + 1 + + + TS_Op24 + TS_Op24 + 24 + 1 + + + TS_Op25 + TS_Op25 + 25 + 1 + + + TS_Op26 + TS_Op26 + 26 + 1 + + + TS_Op27 + TS_Op27 + 27 + 1 + + + TS_Op28 + TS_Op28 + 28 + 1 + + + TS_Op29 + TS_Op29 + 29 + 1 + + + TS_Op30 + TS_Op30 + 30 + 1 + + + TS_Op31 + TS_Op31 + 31 + 1 + + + + + + + ETH_MAC_MMC + ETH_MAC_MMC + Ethernet + 0x5800A000 + + 0x0 + 0xBD4 + registers + + + + ETH_MACCR + ETH_MACCR + The MAC Configuration Register establishes + the operating mode of the MAC. + 0x00 + 0x20 + read-write + 0x00008000 + + + RE + RE + 0 + 1 + read-write + + + TE + TE + 1 + 1 + read-write + + + PRELEN + PRELEN + 2 + 2 + read-write + + + DC + DC + 4 + 1 + read-write + + + BL + BL + 5 + 2 + read-write + + + DR + DR + 8 + 1 + read-write + + + DCRS + DCRS + 9 + 1 + read-write + + + DO + DO + 10 + 1 + read-write + + + ECRSFD + ECRSFD + 11 + 1 + read-write + + + LM + LM + 12 + 1 + read-write + + + DM + DM + 13 + 1 + read-write + + + FES + FES + 14 + 1 + read-write + + + PS + PS + 15 + 1 + read-write + + + JE + JE + 16 + 1 + read-write + + + JD + JD + 17 + 1 + read-write + + + BE + BE + 18 + 1 + read-write + + + WD + WD + 19 + 1 + read-write + + + ACS + ACS + 20 + 1 + read-write + + + CST + CST + 21 + 1 + read-write + + + S2KP + S2KP + 22 + 1 + read-write + + + GPSLCE + GPSLCE + 23 + 1 + read-write + + + IPG + IPG + 24 + 3 + read-write + + + IPC + IPC + 27 + 1 + read-write + + + SARC + SARC + 28 + 3 + read-write + + + ARPEN + ARPEN + 31 + 1 + read-write + + + + + ETH_MACECR + ETH_MACECR + The MAC Extended Configuration Register + establishes the operating mode of the MAC. + 0x04 + 0x20 + read-write + 0x00000000 + + + GPSL + GPSL + 0 + 14 + read-write + + + DCRCC + DCRCC + 16 + 1 + read-write + + + SPEN + SPEN + 17 + 1 + read-write + + + USP + USP + 18 + 1 + read-write + + + EIPGEN + EIPGEN + 24 + 1 + read-write + + + EIPG + EIPG + 25 + 5 + read-write + + + + + ETH_MACPFR + ETH_MACPFR + The MAC Packet Filter register contains the + filter controls for receiving packets. Some of the + controls from this register go to the address check block + of the MAC which performs the first level of address + filtering. The second level of filtering is performed on + the incoming packet based on other controls such as Pass + Bad Packets and Pass Control Packets. + 0x08 + 0x20 + read-write + 0x00000000 + + + PR + PR + 0 + 1 + read-write + + + HUC + HUC + 1 + 1 + read-write + + + HMC + HMC + 2 + 1 + read-write + + + DAIF + DAIF + 3 + 1 + read-write + + + PM + PM + 4 + 1 + read-write + + + DBF + DBF + 5 + 1 + read-write + + + PCF + PCF + 6 + 2 + read-write + + + SAIF + SAIF + 8 + 1 + read-write + + + SAF + SAF + 9 + 1 + read-write + + + HPF + HPF + 10 + 1 + read-write + + + VTFE + VTFE + 16 + 1 + read-write + + + IPFE + IPFE + 20 + 1 + read-write + + + DNTU + DNTU + 21 + 1 + read-write + + + RA + RA + 31 + 1 + read-write + + + + + ETH_MACWTR + ETH_MACWTR + The Watchdog Timeout register controls the + watchdog timeout for received packets. + 0x0C + 0x20 + read-write + 0x00000000 + + + WTO + WTO + 0 + 4 + read-write + + + PWE + PWE + 8 + 1 + read-write + + + + + ETH_MACHT0R + ETH_MACHT0R + The Hash Table Register 0 contains the first + 32 bits of the Hash table (64 bits). For Hash filtering, + the content of the destination address in the incoming + packet is passed through the CRC logic and the upper six + bits of the CRC register are used to index the content of + the Hash table. The most significant bits determines the + register to be used (Hash Table Register 0 or 1). The + Hash value of the destination address is calculated in + the following way: Calculate the 32-bit CRC for the DA + (See IEEE 802.3, Section 3.2.8 for the steps to calculate + CRC32). Perform bitwise reversal for the value obtained + in Step 1. Take the upper 7 or 8 bits from the value + obtained in Step 2. If the corresponding bit value of the + register is 1, the packet is accepted. Otherwise, it is + rejected. If the PM bit is set in ETH_MACPFR, all + multicast packets are accepted regardless of the + multicast Hash values. If the Hash Table register is + configured to be double-synchronized to the GMII clock + domain, the synchronization is triggered only when + Bits[31:24] (in little-endian mode) or Bits[7:0] (in + big-endian mode) of the Hash Table Register X registers + are written. + 0x10 + 0x20 + read-write + 0x00000000 + + + HT31T0 + HT31T0 + 0 + 32 + read-write + + + + + ETH_MACHT1R + ETH_MACHT1R + The Hash Table Register 1contains the last + 32 bits of the Hash table (64 bits). For Hash filtering, + the content of the destination address in the incoming + packet is passed through the CRC logic and the upper six + bits of the CRC register are used to index the content of + the Hash table. The most significant bits determines the + register to be used (Hash Table Register 0 or 1). The + Hash value of the destination address is calculated in + the following way: Calculate the 32-bit CRC for the DA + (See IEEE 802.3, Section 3.2.8 for the steps to calculate + CRC32). Perform bitwise reversal for the value obtained + in Step 1. Take the upper 7 or 8 bits from the value + obtained in Step 2. If the corresponding bit value of the + register is 1, the packet is accepted. Otherwise, it is + rejected. If the PM bit is set in ETH_MACPFR, all + multicast packets are accepted regardless of the + multicast Hash values. If the Hash Table register is + configured to be double-synchronized to the GMII clock + domain, the synchronization is triggered only when + Bits[31:24] (in little-endian mode) or Bits[7:0] (in + big-endian mode) of the Hash Table Register X registers + are written. + 0x14 + 0x20 + read-write + 0x00000000 + + + HT63T32 + HT63T32 + 0 + 32 + read-write + + + + + ETH_MACVTR + ETH_MACVTR + The VLAN Tag register identifies the IEEE + 802.1Q VLAN type packets. + 0x50 + 0x20 + read-write + 0x00000000 + + + VL + VL + 0 + 16 + read-write + + + ETV + ETV + 16 + 1 + read-write + + + VTIM + VTIM + 17 + 1 + read-write + + + ESVL + ESVL + 18 + 1 + read-write + + + ERSVLM + ERSVLM + 19 + 1 + read-write + + + DOVLTC + DOVLTC + 20 + 1 + read-write + + + EVLS + EVLS + 21 + 2 + read-write + + + EVLRXS + EVLRXS + 24 + 1 + read-write + + + VTHM + VTHM + 25 + 1 + read-write + + + EDVLP + EDVLP + 26 + 1 + read-write + + + ERIVLT + ERIVLT + 27 + 1 + read-write + + + EIVLS + EIVLS + 28 + 2 + read-write + + + EIVLRXS + EIVLRXS + 31 + 1 + read-write + + + + + ETH_MACVHTR + ETH_MACVHTR + When the ERSVLM bit of ETH_MACHT1R register + is set, the 16-bit VLAN Hash Table register is used for + group address filtering based on the VLAN tag. For Hash + filtering, the content of the 16-bit VLAN tag or 12-bit + VLAN ID (based on the ETV bit of ETH_MACVTR register) in + the incoming packet is passed through the CRC logic. The + upper four bits of the calculated CRC are used to index + the contents of the VLAN Hash table. For example, a Hash + value of 1000 selects Bit 8 of the VLAN Hash table. The + Hash value of the destination address is calculated in + the following way: Calculate the 32-bit CRC for the VLAN + tag or ID (For steps to calculate CRC32, see Section + 3.2.8 of IEEE 802.3). Perform bitwise reversal for the + value obtained in step 1. Take the upper four bits from + the value obtained in step 2. If the VLAN Hash Table + register is configured to be double-synchronized to the + GMII clock domain, the synchronization is triggered only + when Bits[15:8] (in little-endian mode) or Bits[7:0] (in + big-endian mode) of this register are + written. + 0x58 + 0x20 + read-write + 0x00000000 + + + VLHT + VLHT + 0 + 16 + read-write + + + + + ETH_MACVIR + ETH_MACVIR + The VLAN Tag Inclusion or Replacement + register contains the VLAN tag for insertion or + replacement in the Transmit packets. It also contains the + VLAN tag insertion controls. + 0x60 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + read-write + + + VLC + VLC + 16 + 2 + read-write + + + VLP + VLP + 18 + 1 + read-write + + + CSVL + CSVL + 19 + 1 + read-write + + + VLTI + VLTI + 20 + 1 + read-write + + + + + ETH_MACIVIR + ETH_MACIVIR + The Inner VLAN Tag Inclusion or Replacement + register contains the inner VLAN tag to be inserted or + replaced in the Transmit packet. It also contains the + inner VLAN tag insertion controls. + 0x64 + 0x20 + read-write + 0x00000000 + + + VLT + VLT + 0 + 16 + read-write + + + VLC + VLC + 16 + 2 + read-write + + + VLP + VLP + 18 + 1 + read-write + + + CSVL + CSVL + 19 + 1 + read-write + + + VLTI + VLTI + 20 + 1 + read-write + + + + + ETH_MACQ0TxFCR + ETH_MACQ0TxFCR + The Flow Control register controls the + generation and reception of the Control (Pause Command) + packets by the Flow control module of the MAC. A Write to + a register with the Busy bit set to 1 triggers the Flow + Control block to generate a Pause packet. The fields of + the control packet are selected as specified in the + 802.3x specification, and the Pause Time value from this + register is used in the Pause Time field of the control + packet. The Busy bit remains set until the control packet + is transferred onto the cable. The application must make + sure that the Busy bit is cleared before writing to the + register. + 0x70 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + FCB_BPA + 0 + 1 + read-write + + + TFE + TFE + 1 + 1 + read-write + + + PLT + PLT + 4 + 3 + read-write + + + DZPQ + DZPQ + 7 + 1 + read-write + + + PT + PT + 16 + 16 + read-write + + + + + ETH_MACRxFCR + ETH_MACRxFCR + The Receive Flow Control register controls + the pausing of MAC Transmit based on the received Pause + packet. + 0x90 + 0x20 + read-write + 0x00000000 + + + RFE + RFE + 0 + 1 + read-write + + + UP + UP + 1 + 1 + read-write + + + + + ETH_MACTxQPMR + ETH_MACTxQPMR + The transmit queue priority mapping 0 + register contains the priority values assigned to Tx + queue 0 and tx queue 1. + 0x98 + 0x20 + read-only + 0x00000000 + + + PSTQ0 + PSTQ0 + 0 + 8 + read-only + + + PSTQ1 + PSTQ1 + 8 + 8 + read-only + + + + + ETH_MACRxQC0R + ETH_MACRxQC0R + The Receive Queue Control 0 register + controls the queue management in the MAC + Receiver. + 0xA0 + 0x20 + read-write + 0x00000000 + + + RXQ0EN + RXQ0EN + 0 + 2 + read-write + + + RXQ1EN + RXQ1EN + 2 + 2 + read-write + + + + + ETH_MACRxQC1R + ETH_MACRxQC1R + The Receive Queue Control 1 register + controls queue 1 management in the MAC + receiver. + 0xA4 + 0x20 + read-write + 0x00000000 + + + AVCPQ + AVCPQ + 0 + 3 + read-write + + + AVPTPQ + AVPTPQ + 4 + 3 + read-write + + + UPQ + UPQ + 12 + 3 + read-write + + + MCBCQ + MCBCQ + 16 + 3 + read-write + + + MCBCQEN + MCBCQEN + 20 + 1 + read-write + + + TACPQE + TACPQE + 21 + 1 + read-write + + + + + ETH_MACRxQC2R + ETH_MACRxQC2R + This register controls the routing of tagged + packets based on the USP (user priority) field of the + received packets to the Rx queue 0 and 1. + 0xA8 + 0x20 + read-write + 0x00000000 + + + PSRQ0 + PSRQ0 + 0 + 8 + read-write + + + PSRQ1 + PSRQ1 + 8 + 8 + read-write + + + + + ETH_MACISR + ETH_MACISR + The Interrupt Status register contains the + status of interrupts. + 0xB0 + 0x20 + read-only + 0x00000000 + + + RGSMIIIS + RGSMIIIS + 0 + 1 + read-only + + + PHYIS + PHYIS + 3 + 1 + read-only + + + PMTIS + PMTIS + 4 + 1 + read-only + + + LPIIS + LPIIS + 5 + 1 + read-only + + + MMCIS + MMCIS + 8 + 1 + read-only + + + MMCRXIS + MMCRXIS + 9 + 1 + read-only + + + MMCTXIS + MMCTXIS + 10 + 1 + read-only + + + TSIS + TSIS + 12 + 1 + read-only + + + TXSTSIS + TXSTSIS + 13 + 1 + read-only + + + RXSTSIS + RXSTSIS + 14 + 1 + read-only + + + + + ETH_MACIER + ETH_MACIER + The Interrupt Enable register contains the + masks for generating the interrupts. + 0xB4 + 0x20 + read-write + 0x00000000 + + + RGSMIIIE + RGSMIIIE + 0 + 1 + read-write + + + PHYIE + PHYIE + 3 + 1 + read-write + + + PMTIE + PMTIE + 4 + 1 + read-write + + + LPIIE + LPIIE + 5 + 1 + read-write + + + TSIE + TSIE + 12 + 1 + read-write + + + TXSTSIE + TXSTSIE + 13 + 1 + read-write + + + RXSTSIE + RXSTSIE + 14 + 1 + read-write + + + + + ETH_MACRxTxSR + ETH_MACRxTxSR + The Receive Transmit Status register + contains the Receive and Transmit Error + status. + 0xB8 + 0x20 + read-only + 0x00000000 + + + TJT + TJT + 0 + 1 + read-only + + + NCARR + NCARR + 1 + 1 + read-only + + + LCARR + LCARR + 2 + 1 + read-only + + + EXDEF + EXDEF + 3 + 1 + read-only + + + LCOL + LCOL + 4 + 1 + read-only + + + EXCOL + EXCOL + 5 + 1 + read-only + + + RWT + RWT + 8 + 1 + read-only + + + + + ETH_MACPCSR + ETH_MACPCSR + The PMT Control and Status Register is + present only when you select the PMT module in + coreConsultant. + 0xC0 + 0x20 + read-write + 0x00000000 + + + PWRDWN + PWRDWN + 0 + 1 + read-write + + + MGKPKTEN + MGKPKTEN + 1 + 1 + read-write + + + RWKPKTEN + RWKPKTEN + 2 + 1 + read-write + + + MGKPRCVD + MGKPRCVD + 5 + 1 + read-only + + + RWKPRCVD + RWKPRCVD + 6 + 1 + read-only + + + GLBLUCAST + GLBLUCAST + 9 + 1 + read-write + + + RWKPFE + RWKPFE + 10 + 1 + read-write + + + RWKPTR + RWKPTR + 24 + 5 + read-only + + + RWKFILTRST + RWKFILTRST + 31 + 1 + read-write + + + + + ETH_MACRWKPFR + ETH_MACRWKPFR + The LPI Control and Status Register controls + the LPI functions and provides the LPI interrupt status. + The status bits are cleared when this register is + read. + 0xC4 + 0x20 + read-write + 0x00000000 + + + TLPIEN + TLPIEN + 0 + 1 + read-only + + + TLPIEX + TLPIEX + 1 + 1 + read-only + + + RLPIEN + RLPIEN + 2 + 1 + read-only + + + RLPIEX + RLPIEX + 3 + 1 + read-only + + + TLPIST + TLPIST + 8 + 1 + read-only + + + RLPIST + RLPIST + 9 + 1 + read-only + + + LPIEN + LPIEN + 16 + 1 + read-write + + + PLS + PLS + 17 + 1 + read-write + + + PLSEN + PLSEN + 18 + 1 + read-write + + + LPITXA + LPITXA + 19 + 1 + read-write + + + LPITE + LPITE + 20 + 1 + read-write + + + + + ETH_MACLCSR + ETH_MACLCSR + The LPI Control and Status Register controls + the LPI functions and provides the LPI interrupt status. + The status bits are cleared when this register is + read. + 0xD0 + 0x20 + read-write + 0x00000000 + + + TLPIEN + TLPIEN + 0 + 1 + read-only + + + TLPIEX + TLPIEX + 1 + 1 + read-only + + + RLPIEN + RLPIEN + 2 + 1 + read-only + + + RLPIEX + RLPIEX + 3 + 1 + read-only + + + TLPIST + TLPIST + 8 + 1 + read-only + + + RLPIST + RLPIST + 9 + 1 + read-only + + + LPIEN + LPIEN + 16 + 1 + read-write + + + PLS + PLS + 17 + 1 + read-write + + + PLSEN + PLSEN + 18 + 1 + read-write + + + LPITXA + LPITXA + 19 + 1 + read-write + + + LPITE + LPITE + 20 + 1 + read-write + + + + + ETH_MACLTCR + ETH_MACLTCR + The LPI Timers Control register controls the + timeout values in the LPI states. It specifies the time + for which the MAC transmits the LPI pattern and also the + time for which the MAC waits before resuming the normal + transmission. + 0xD4 + 0x20 + read-write + 0x03E80000 + + + TWT + TWT + 0 + 16 + read-write + + + LST + LST + 16 + 10 + read-write + + + + + ETH_MACLETR + ETH_MACLETR + The LPI Entry Timer Register is used to + store the LPI Idle Timer Value in + Micro-Seconds. + 0xD8 + 0x20 + read-write + 0x00000000 + + + LPIET + LPIET + 3 + 17 + read-write + + + + + ETH_MAC1USTCR + ETH_MAC1USTCR + This register controls the generation of the + Reference time (1-microsecond tick) for all the LPI + timers. This timer has to be programmed by the software + initially. + 0xDC + 0x20 + read-write + 0x00000000 + + + TIC_1US_CNTR + TIC_1US_CNTR + 0 + 12 + read-write + + + + + ETH_MACPHYCSR + ETH_MACPHYCSR + The PHY Interface Control and Status + register indicates the status signals received by the, + RGMII interface from the PHY. + 0xF8 + 0x20 + read-write + 0x00000000 + + + TC + TC + 0 + 1 + read-write + + + LUD + LUD + 1 + 1 + read-write + + + LNKMOD + LNKMOD + 16 + 1 + read-only + + + LNKSPEED + LNKSPEED + 17 + 2 + read-only + + + LNKSTS + LNKSTS + 19 + 1 + read-only + + + JABTO + JABTO + 20 + 1 + read-only + + + FALSCARDET + FALSCARDET + 21 + 1 + read-only + + + + + ETH_MACVR + ETH_MACVR + The version register identifies the version + of the Ethernet peripheral. + 0x110 + 0x20 + read-only + 0x00004042 + + + SNPSVER + SNPSVER + 0 + 8 + read-only + + + USERVER + USERVER + 8 + 8 + read-only + + + + + ETH_MACDR + ETH_MACDR + The Debug register provides the debug status + of various MAC blocks. + 0x114 + 0x20 + read-only + 0x00000000 + + + RPESTS + RPESTS + 0 + 1 + read-only + + + RFCFCSTS + RFCFCSTS + 1 + 2 + read-only + + + TPESTS + TPESTS + 16 + 1 + read-only + + + TFCSTS + TFCSTS + 17 + 2 + read-only + + + + + ETH_MACHWF1R + ETH_MACHWF1R + This register indicates the presence of + second set of the optional features or functions of the + Ethernet peripheral. The software driver can use this + register to dynamically enable or disable the programs + related to the optional blocks. + 0x120 + 0x20 + read-only + 0x11141945 + + + RXFIFOSIZE + RXFIFOSIZE + 0 + 5 + read-only + + + TXFIFOSIZE + TXFIFOSIZE + 6 + 5 + read-only + + + OSTEN + OSTEN + 11 + 1 + read-only + + + PTOEN + PTOEN + 12 + 1 + read-only + + + ADVTHWORD + ADVTHWORD + 13 + 1 + read-only + + + ADDR64 + ADDR64 + 14 + 2 + read-only + + + DCBEN + DCBEN + 16 + 1 + read-only + + + SPHEN + SPHEN + 17 + 1 + read-only + + + TSOEN + TSOEN + 18 + 1 + read-only + + + DBGMEMA + DBGMEMA + 19 + 1 + read-only + + + AVSEL + AVSEL + 20 + 1 + read-only + + + HASHTBLSZ + HASHTBLSZ + 24 + 2 + read-only + + + L3L4FNUM + L3L4FNUM + 27 + 4 + read-only + + + + + ETH_MACHWF2R + ETH_MACHWF2R + This register indicates the presence of + third set of the optional features or functions of the + Ethernet peripheral. The software driver can use this + register to dynamically enable or disable the programs + related to the optional blocks. + 0x124 + 0x20 + read-only + 0x41040041 + + + RXQCNT + RXQCNT + 0 + 4 + read-only + + + TXQCNT + TXQCNT + 6 + 4 + read-only + + + RXCHCNT + RXCHCNT + 12 + 4 + read-only + + + TXCHCNT + TXCHCNT + 18 + 4 + read-only + + + PPSOUTNUM + PPSOUTNUM + 24 + 3 + read-only + + + AUXSNAPNUM + AUXSNAPNUM + 28 + 3 + read-only + + + + + ETH_MACMDIOAR + ETH_MACMDIOAR + The MDIO Address register controls the + management cycles to external PHY through a management + interface. + 0x200 + 0x20 + read-write + 0x00000000 + + + GB + GB + 0 + 1 + read-write + + + C45E + C45E + 1 + 1 + read-write + + + GOC + GOC + 2 + 2 + read-write + + + SKAP + SKAP + 4 + 1 + read-write + + + CR + CR + 8 + 4 + read-write + + + NTC + NTC + 12 + 3 + read-write + + + RDA + RDA + 16 + 5 + read-write + + + PA + PA + 21 + 5 + read-write + + + BTB + BTB + 26 + 1 + read-write + + + PSE + PSE + 27 + 1 + read-write + + + + + ETH_MACMDIODR + ETH_MACMDIODR + The MDIO Data register stores the Write data + to be written to the PHY register located at the address + specified in ETH_MACMDIOAR. This register also stores the + Read data from the PHY register located at the address + specified by MDIO Address register. + 0x204 + 0x20 + read-write + 0x00000000 + + + GD + GD + 0 + 16 + read-write + + + RA + RA + 16 + 16 + read-write + + + + + ETH_MACA0HR + ETH_MACA0HR + The MAC Address0 High register holds the + upper 16 bits of the first 6-byte MAC address of the + station. The first DA byte that is received on the GMII + interface corresponds to the LS byte (Bits [7:0]) of the + MAC Address Low register. For example, if 0x112233445566 + is received (0x11 in lane 0 of the first column) on the + GMII as the destination address, then the MacAddress0 + Register [47:0] is compared with 0x665544332211. If the + MAC address registers are configured to be + double-synchronized to the GMII clock domains, then the + synchronization is triggered only when Bits[31:24] (in + little-endian mode) or Bits[7:0] (in big-endian mode) of + the MAC Address0 Low Register are written. For proper + synchronization updates, the consecutive writes to this + Address Low Register should be performed after at least + four clock cycles in the destination clock + domain. + 0x300 + 0x20 + read-write + 0x8000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + AE + AE + 31 + 1 + read-only + + + + + ETH_MACA0LR + ETH_MACA0LR + The MAC Address x Low register holds the + lower 32 bits of the 6-byte first MAC address of the + station. + 0x304 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + read-write + + + + + ETH_MACA1HR + ETH_MACA1HR + The MAC Address x High register holds the + upper 16 bits of the second 6-byte MAC address of the + station. + 0x308 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + MBC + MBC + 24 + 6 + read-write + + + SA + SA + 30 + 1 + read-write + + + AE + AE + 31 + 1 + read-write + + + + + ETH_MACA1LR + ETH_MACA1LR + The MAC Address x Low register holds the + lower 32 bits of the 6-byte first MAC address of the + station. + 0x30C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + read-write + + + + + ETH_MACA2HR + ETH_MACA2HR + The MAC Address x High register holds the + upper 16 bits of the second 6-byte MAC address of the + station. + 0x310 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + MBC + MBC + 24 + 6 + read-write + + + SA + SA + 30 + 1 + read-write + + + AE + AE + 31 + 1 + read-write + + + + + ETH_MACA2LR + ETH_MACA2LR + The MAC Address x Low register holds the + lower 32 bits of the 6-byte first MAC address of the + station. + 0x314 + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + read-write + + + + + ETH_MACA3HR + ETH_MACA3HR + The MAC Address x High register holds the + upper 16 bits of the second 6-byte MAC address of the + station. + 0x318 + 0x20 + read-write + 0x0000FFFF + + + ADDRHI + ADDRHI + 0 + 16 + read-write + + + MBC + MBC + 24 + 6 + read-write + + + SA + SA + 30 + 1 + read-write + + + AE + AE + 31 + 1 + read-write + + + + + ETH_MACA3LR + ETH_MACA3LR + The MAC Address x Low register holds the + lower 32 bits of the 6-byte first MAC address of the + station. + 0x31C + 0x20 + read-write + 0xFFFFFFFF + + + ADDRLO + ADDRLO + 0 + 32 + read-write + + + + + MMC_CONTROL + MMC_CONTROL + This register configures the MMC operating + mode. + 0x700 + 0x20 + read-write + 0x00000000 + + + CNTRST + CNTRST + 0 + 1 + read-write + + + CNTSTOPRO + CNTSTOPRO + 1 + 1 + read-write + + + RSTONRD + RSTONRD + 2 + 1 + read-write + + + CNTFREEZ + CNTFREEZ + 3 + 1 + read-write + + + CNTPRST + CNTPRST + 4 + 1 + read-write + + + CNTPRSTLVL + CNTPRSTLVL + 5 + 1 + read-write + + + UCDBC + UCDBC + 8 + 1 + read-write + + + + + MMC_RX_INTERRUPT + MMC_RX_INTERRUPT + This register maintains the interrupts + generated from all Receive statistics counters. The MMC + Receive Interrupt register maintains the interrupts that + are generated when the following occur: Receive statistic + counters reach half of their maximum values (0x8000_0000 + for 32 bit counter and 0x8000 for 16 bit counter). + Receive statistic counters cross their maximum values + (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit + counter). When the Counter Stop Rollover is set, + interrupts are set but the counter remains at all-ones. + The MMC Receive Interrupt register is a 32 bit register. + An interrupt bit is cleared when the respective MMC + counter that caused the interrupt is read. The least + significant byte lane (Bits[7:0]) of the respective + counter must be read to clear the interrupt + bit. + 0x704 + 0x20 + read-only + 0x00000000 + + + RXCRCERPIS + RXCRCERPIS + 5 + 1 + read-only + + + RXALGNERPIS + RXALGNERPIS + 6 + 1 + read-only + + + RXUCGPIS + RXUCGPIS + 17 + 1 + read-only + + + RXLPIUSCIS + RXLPIUSCIS + 26 + 1 + read-only + + + RXLPITRCIS + RXLPITRCIS + 27 + 1 + read-only + + + + + MMC_TX_INTERRUPT + MMC_TX_INTERRUPT + This register maintains the interrupts + generated from all Transmit statistics counters. The MMC + Transmit Interrupt register maintains the interrupts + generated when transmit statistic counters reach half + their maximum values (0x8000_0000 for 32 bit counter and + 0x8000 for 16 bit counter), and when they cross their + maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF + for 16-bit counter). When Counter Stop Rollover is set, + the interrupts are set but the counter remains at + all-ones. The MMC Transmit Interrupt register is a 32 bit + register. An interrupt bit is cleared when the respective + MMC counter that caused the interrupt is read. The least + significant byte lane (Bits[7:0]) of the respective + counter must be read to clear the interrupt + bit. + 0x708 + 0x20 + read-only + 0x00000000 + + + TXSCOLGPIS + TXSCOLGPIS + 14 + 1 + read-only + + + TXMCOLGPIS + TXMCOLGPIS + 15 + 1 + read-only + + + TXGPKTIS + TXGPKTIS + 21 + 1 + read-only + + + TXLPIUSCIS + TXLPIUSCIS + 26 + 1 + read-only + + + TXLPITRCIS + TXLPITRCIS + 27 + 1 + read-only + + + + + MMC_RX_INTERRUPT_MASK + MMC_RX_INTERRUPT_MASK + The MMC Receive Interrupt Mask register + maintains the masks for the interrupts generated when + receive statistic counters reach half of their maximum + value or the maximum values. + 0x70C + 0x20 + read-write + 0x00000000 + + + RXCRCERPIM + RXCRCERPIM + 5 + 1 + read-write + + + RXALGNERPIM + RXALGNERPIM + 6 + 1 + read-write + + + RXUCGPIM + RXUCGPIM + 17 + 1 + read-write + + + RXLPIUSCIM + RXLPIUSCIM + 26 + 1 + read-write + + + RXLPITRCIM + RXLPITRCIM + 27 + 1 + read-only + + + + + MMC_TX_INTERRUPT_MASK + MMC_TX_INTERRUPT_MASK + This register maintains the masks for + interrupts generated from all Transmit statistics + counters. The MMC Transmit Interrupt Mask register + maintains the masks for the interrupts generated when the + transmit statistic counters reach half of their maximum + value or the maximum values. This register is 32 bit + wide. This register is present only when any one of the + MMC Transmit Counters is selected during core + configuration. + 0x710 + 0x20 + read-write + 0x00000000 + + + TXSCOLGPIM + TXSCOLGPIM + 14 + 1 + read-write + + + TXMCOLGPIM + TXMCOLGPIM + 15 + 1 + read-write + + + TXGPKTIM + TXGPKTIM + 21 + 1 + read-write + + + TXLPIUSCIM + TXLPIUSCIM + 26 + 1 + read-write + + + TXLPITRCIM + TXLPITRCIM + 27 + 1 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_PACKETS + + TX_SINGLE_COLLISION_GOOD_PACKETS + This register provides the number of + successfully transmitted packets by Ethernet peripheral + after a single collision in the half-duplex + mode. + 0x74C + 0x20 + read-only + 0x00000000 + + + TXSNGLCOLG + TXSNGLCOLG + 0 + 32 + read-only + + + + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + + TX_MULTIPLE_COLLISION_GOOD_PACKETS + This register provides the number of + successfully transmitted packets by Ethernet peripheral + after multiple collisions in the half-duplex + mode. + 0x750 + 0x20 + read-only + 0x00000000 + + + TXMULTCOLG + TXMULTCOLG + 0 + 32 + read-only + + + + + TX_PACKET_COUNT_GOOD + TX_PACKET_COUNT_GOOD + This register provides the number of good + packets transmitted by Ethernet peripheral. + 0x768 + 0x20 + read-only + 0x00000000 + + + TXPKTG + TXPKTG + 0 + 32 + read-only + + + + + RX_CRC_ERROR_PACKETS + RX_CRC_ERROR_PACKETS + This register provides the number of packets + received by Ethernet peripheral with CRC + error. + 0x794 + 0x20 + read-only + 0x00000000 + + + RXCRCERR + RXCRCERR + 0 + 32 + read-only + + + + + RX_ALIGNMENT_ERROR_PACKETS + RX_ALIGNMENT_ERROR_PACKETS + This register provides the number of packets + received by Ethernet peripheral with alignment (dribble) + error. It is valid only in 10/100 mode. + 0x798 + 0x20 + read-only + 0x00000000 + + + RXALGNERR + RXALGNERR + 0 + 32 + read-only + + + + + RX_UNICAST_PACKETS_GOOD + RX_UNICAST_PACKETS_GOOD + This register provides the number of good + unicast packets received by Ethernet + peripheral. + 0x7C4 + 0x20 + read-only + 0x00000000 + + + RXUCASTG + RXUCASTG + 0 + 32 + read-only + + + + + TX_LPI_USEC_CNTR + TX_LPI_USEC_CNTR + This register provides the number of + microseconds Tx LPI is asserted by Ethernet + peripheral. + 0x7EC + 0x20 + read-only + 0x00000000 + + + TXLPIUSC + TXLPIUSC + 0 + 32 + read-only + + + + + TX_LPI_TRAN_CNTR + TX_LPI_TRAN_CNTR + This register provides the number of times + Ethernet peripheral has entered Tx LPI. + 0x7F0 + 0x20 + read-only + 0x00000000 + + + TXLPITRC + TXLPITRC + 0 + 32 + read-only + + + + + RX_LPI_USEC_CNTR + RX_LPI_USEC_CNTR + This register provides the number of + microseconds Rx LPI is sampled by Ethernet + peripheral. + 0x7F4 + 0x20 + read-only + 0x00000000 + + + RXLPIUSC + RXLPIUSC + 0 + 32 + read-only + + + + + RX_LPI_TRAN_CNTR + RX_LPI_TRAN_CNTR + This register provides the number of times + Ethernet peripheral has entered Rx LPI. + 0x7F8 + 0x20 + read-only + 0x00000000 + + + RXLPITRC + RXLPITRC + 0 + 32 + read-only + + + + + ETH_MACL3L4C0R + ETH_MACL3L4C0R + The Layer 3 and Layer 4 Control register + controls the operations of filter 0 of Layer 3 and Layer + 4. This register is reserved if the Layer 3 and Layer 4 + Filtering feature is not selected during core + configuration. + 0x900 + 0x20 + read-write + 0x00000000 + + + L3PEN0 + L3PEN0 + 0 + 1 + read-write + + + L3SAM0 + L3SAM0 + 2 + 1 + read-write + + + L3SAIM0 + L3SAIM0 + 3 + 1 + read-write + + + L3DAM0 + L3DAM0 + 4 + 1 + read-write + + + L3DAIM0 + L3DAIM0 + 5 + 1 + read-write + + + L3HSBM0 + L3HSBM0 + 6 + 5 + read-write + + + L3HDBM0 + L3HDBM0 + 11 + 5 + read-write + + + L4PEN0 + L4PEN0 + 16 + 1 + read-write + + + L4SPM0 + L4SPM0 + 18 + 1 + read-write + + + L4SPIM0 + L4SPIM0 + 19 + 1 + read-write + + + L4DPM0 + L4DPM0 + 20 + 1 + read-write + + + L4DPIM0 + L4DPIM0 + 21 + 1 + read-write + + + + + ETH_MACL4A0R + ETH_MACL4A0R + Layer4 address filter 0 + register + 0x904 + 0x20 + read-write + 0x00000000 + + + L4SP0 + L4SP0 + 0 + 16 + read-write + + + L4DP0 + L4DP0 + 16 + 16 + read-write + + + + + ETH_MACL3A00R + ETH_MACL3A00R + For IPv4 packets, the Layer 3 Address 0 + Register 0 register contains the 32-bit IP Source Address + field. For IPv6 packets, it contains Bits[31:0] of the + 128-bit IP Source Address or Destination Address + field. + 0x910 + 0x20 + read-write + 0x00000000 + + + L3A00 + L3A00 + 0 + 32 + read-write + + + + + ETH_MACL3A10R + ETH_MACL3A10R + For IPv4 packets, the Layer 3 Address 1 + Register 0 register contains the 32-bit IP Destination + Address field. For IPv6 packets, it contains Bits[63:32] + of the 128-bit IP Source Address or Destination Address + field. + 0x914 + 0x20 + read-write + 0x00000000 + + + L3A10 + L3A10 + 0 + 32 + read-write + + + + + ETH_MACL3A20 + ETH_MACL3A20 + The Layer 3 Address 2 Register 0 register is + reserved for IPv4 packets. For IPv6 packets, it contains + Bits[95:64] of 128-bit IP Source Address or Destination + Address field. + 0x918 + 0x20 + read-write + 0x00000000 + + + L3A20 + L3A20 + 0 + 32 + read-write + + + + + ETH_MACL3A30 + ETH_MACL3A30 + The Layer 3 Address 3 Register 0 register is + reserved for IPv4 packets. For IPv6 packets, it contains + Bits[127:96] of 128-bit IP Source Address or Destination + Address field. + 0x91C + 0x20 + read-write + 0x00000000 + + + L3A30 + L3A30 + 0 + 32 + read-write + + + + + ETH_MACL3L4C1R + ETH_MACL3L4C1R + The Layer 3 and Layer 4 Control register + controls the operations of filter 0 of Layer 3 and Layer + 4. + 0x930 + 0x20 + read-write + 0x00000000 + + + L3PEN1 + L3PEN1 + 0 + 1 + read-write + + + L3SAM1 + L3SAM1 + 2 + 1 + read-write + + + L3SAIM1 + L3SAIM1 + 3 + 1 + read-write + + + L3DAM1 + L3DAM1 + 4 + 1 + read-write + + + L3DAIM1 + L3DAIM1 + 5 + 1 + read-write + + + L3HSBM1 + L3HSBM1 + 6 + 5 + read-write + + + L3HDBM1 + L3HDBM1 + 11 + 5 + read-write + + + L4PEN1 + L4PEN1 + 16 + 1 + read-write + + + L4SPM1 + L4SPM1 + 18 + 1 + read-write + + + L4SPIM1 + L4SPIM1 + 19 + 1 + read-write + + + L4DPM1 + L4DPM1 + 20 + 1 + read-write + + + L4DPIM1 + L4DPIM1 + 21 + 1 + read-write + + + + + ETH_MACL4A1R + ETH_MACL4A1R + The Layer 4 Address 0 register and registers + 580 through 667 are reserved (RO with default value) if + Enable Layer 3 and Layer 4 Packet Filter option is not + selected while configuring the core. You can configure + the Layer 3 and Layer 4 Address Registers to be + double-synchronized by selecting the Synchronize Layer 3 + and Layer 4 Address Registers to Rx Clock Domain option + while configuring the core. When you select this option, + the synchronization is triggered only when Bits[31:24] + (in little-endian mode) or Bits[7:0] (in big-endian mode) + of the Layer 3 and Layer 4 Address Registers are written. + For proper synchronization updates, you should perform + consecutive writes to same Layer 3 and Layer 4 Address + Registers after at least four clock cycles delay of the + destination clock. + 0x934 + 0x20 + read-write + 0x00000000 + + + L4SP1 + L4SP1 + 0 + 16 + read-write + + + L4DP1 + L4DP1 + 16 + 16 + read-write + + + + + ETH_MACL3A01R + ETH_MACL3A01R + For IPv4 packets, the Layer 3 Address 0 + Register 0 register contains the 32-bit IP Source Address + field. For IPv6 packets, it contains Bits[31:0] of the + 128-bit IP Source Address or Destination Address + field. + 0x940 + 0x20 + read-write + 0x00000000 + + + L3A01 + L3A01 + 0 + 32 + read-write + + + + + ETH_MACL3A11R + ETH_MACL3A11R + For IPv4 packets, the Layer 3 Address 1 + Register 0 register contains the 32-bit IP Destination + Address field. For IPv6 packets, it contains Bits[63:32] + of the 128-bit IP Source Address or Destination Address + field. + 0x944 + 0x20 + read-write + 0x00000000 + + + L3A11 + L3A11 + 0 + 32 + read-write + + + + + ETH_MACL3A21R + ETH_MACL3A21R + The Layer 3 Address 2 Register 0 register is + reserved for IPv4 packets. For IPv6 packets, it contains + Bits[95:64] of 128-bit IP Source Address or Destination + Address field. + 0x948 + 0x20 + read-write + 0x00000000 + + + L3A21 + L3A21 + 0 + 32 + read-write + + + + + ETH_MACL3A31R + ETH_MACL3A31R + The Layer 3 Address 3 Register 0 register is + reserved for IPv4 packets. For IPv6 packets, it contains + Bits[127:96] of 128-bit IP Source Address or Destination + Address field. + 0x94C + 0x20 + read-write + 0x00000000 + + + L3A31 + L3A31 + 0 + 32 + read-write + + + + + ETH_MACARPAR + ETH_MACARPAR + The ARP Address register contains the IPv4 + Destination Address of the MAC. + 0xAE0 + 0x20 + read-write + 0x00000000 + + + ARPPA + ARPPA + 0 + 32 + read-write + + + + + ETH_MACTSCR + ETH_MACTSCR + This register controls the operation of the + System Time generator and processing of PTP packets for + timestamping in the Receiver. + 0xB00 + 0x20 + read-write + 0x00002000 + + + TSENA + TSENA + 0 + 1 + read-write + + + TSCFUPDT + TSCFUPDT + 1 + 1 + read-write + + + TSINIT + TSINIT + 2 + 1 + read-write + + + TSUPDT + TSUPDT + 3 + 1 + read-write + + + TSADDREG + TSADDREG + 5 + 1 + read-write + + + TSENALL + TSENALL + 8 + 1 + read-write + + + TSCTRLSSR + TSCTRLSSR + 9 + 1 + read-write + + + TSVER2ENA + TSVER2ENA + 10 + 1 + read-write + + + TSIPENA + TSIPENA + 11 + 1 + read-write + + + TSIPV6ENA + TSIPV6ENA + 12 + 1 + read-write + + + TSIPV4ENA + TSIPV4ENA + 13 + 1 + read-write + + + TSEVNTENA + TSEVNTENA + 14 + 1 + read-write + + + TSMSTRENA + TSMSTRENA + 15 + 1 + read-write + + + SNAPTYPSEL + SNAPTYPSEL + 16 + 2 + read-write + + + TSENMACADDR + TSENMACADDR + 18 + 1 + read-write + + + CSC + CSC + 19 + 1 + read-only + + + TXTSSTSM + TXTSSTSM + 24 + 1 + read-write + + + AV8021ASMEN + AV8021ASMEN + 28 + 1 + read-write + + + + + ETH_MACSSIR + ETH_MACSSIR + The Sub-second Increment register is present + only when the IEEE 1588 timestamp feature is selected + without an external timestamp input. In Coarse Update + mode [Bit 1 in ETH_MACTSCR register, the value in this + register is added to the system time every clock cycle of + HCLK. In Fine Update mode, the value in this register is + added to the system time whenever the Accumulator gets an + overflow. + 0xB04 + 0x20 + read-write + 0x00000000 + + + SNSINC + SNSINC + 8 + 8 + read-write + + + SSINC + SSINC + 16 + 8 + read-write + + + + + ETH_MACSTSR + ETH_MACSTSR + The System Time Seconds register, along with + System Time Nanoseconds register, indicates the current + value of the system time maintained by the MAC. Though it + is updated on a continuous basis, there is some delay + from the actual time because of clock domain transfer + latencies (from HCLK to CSR clock). This register is + present only when the IEEE 1588 Timestamp feature is + selected without external timestamp input. + 0xB08 + 0x20 + read-only + 0x00000000 + + + TSS + TSS + 0 + 32 + read-only + + + + + ETH_MACSTNR + ETH_MACSTNR + The System Time Nanoseconds register, along + with System Time Seconds register, indicates the current + value of the system time maintained by the MAC. This + register is present only when the IEEE 1588 Timestamp + feature is selected without external timestamp + input. + 0xB0C + 0x20 + read-only + 0x00000000 + + + TSSS + TSSS + 0 + 31 + read-only + + + + + ETH_MACSTSUR + ETH_MACSTSUR + The System Time Seconds Update register, + along with the System Time Nanoseconds Update register, + initializes or updates the system time maintained by the + MAC. You must write both registers before setting the + TSINIT or TSUPDT bits in ETH_MACTSCR register. This + register is present only when the IEEE 1588 Timestamp + feature is selected without external timestamp + input. + 0xB10 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 32 + read-write + + + + + ETH_MACSTNUR + ETH_MACSTNUR + This register is present only when the IEEE + 1588 timestamp feature is selected without external + timestamp input. + 0xB14 + 0x20 + read-write + 0x00000000 + + + TSSS + TSSS + 0 + 31 + read-write + + + ADDSUB + ADDSUB + 31 + 1 + read-write + + + + + ETH_MACTSAR + ETH_MACTSAR + The Timestamp Addend register is present + only when the IEEE 1588 Timestamp feature is selected + without external timestamp input. This register value is + used only when the system time is configured for Fine + Update mode (TSCFUPDT bit in the ETH_MACTSCR register). + The content of this register is added to a 32-bit + accumulator in every clock cycle (of HCLK) and the system + time is updated whenever the accumulator + overflows. + 0xB18 + 0x20 + read-write + 0x00000000 + + + TSAR + TSAR + 0 + 32 + read-write + + + + + ETH_MACTSSR + ETH_MACTSSR + The Timestamp Status register is present + only when the IEEE 1588 Timestamp feature is selected. + All bits except Bits[27:25] gets cleared when the + application reads this register. + 0xB20 + 0x20 + read-only + 0x00000000 + + + TSSOVF + TSSOVF + 0 + 1 + read-only + + + TSTARGT0 + TSTARGT0 + 1 + 1 + read-only + + + AUXTSTRIG + AUXTSTRIG + 2 + 1 + read-only + + + TSTRGTERR0 + TSTRGTERR0 + 3 + 1 + read-only + + + TXTSSIS + TXTSSIS + 15 + 1 + read-only + + + ATSSTN + ATSSTN + 16 + 4 + read-only + + + ATSSTM + ATSSTM + 24 + 1 + read-only + + + ATSNS + ATSNS + 25 + 5 + read-only + + + + + ETH_MACTxTSSNR + ETH_MACTxTSSNR + This register contains the nanosecond part + of timestamp captured for Transmit packets when Tx status + is disabled. + 0xB30 + 0x20 + read-only + 0x00000000 + + + TXTSSLO + TXTSSLO + 0 + 31 + read-only + + + TXTSSMIS + TXTSSMIS + 31 + 1 + read-only + + + + + ETH_MACTxTSSSR + ETH_MACTxTSSSR + The register contains the higher 32 bits of + the timestamp (in seconds) captured when a PTP packet is + transmitted. + 0xB34 + 0x20 + read-only + 0x00000000 + + + TXTSSHI + TXTSSHI + 0 + 32 + read-only + + + + + ETH_MACACR + ETH_MACACR + The Auxiliary Timestamp Control register + controls the Auxiliary Timestamp snapshot. + 0xB40 + 0x20 + read-write + 0x00000000 + + + ATSFC + ATSFC + 0 + 1 + read-write + + + ATSEN0 + ATSEN0 + 4 + 1 + read-write + + + ATSEN1 + ATSEN1 + 5 + 1 + read-write + + + ATSEN2 + ATSEN2 + 6 + 1 + read-write + + + ATSEN3 + ATSEN3 + 7 + 1 + read-write + + + + + ETH_MACATSNR + ETH_MACATSNR + The Auxiliary Timestamp Nanoseconds + register, along with ETH_MACATSSR, gives the 64-bit + timestamp stored as auxiliary snapshot. These two + registers form the read port of a 64-bit wide FIFO with a + depth of 4 words. You can store multiple snapshots in + this FIFO. Bits[29:25] in ETH_MACTSSR indicate the + fill-level of the FIFO. The top of the FIFO is removed + only when the last byte of MAC Register 91 (Auxiliary + Timestamp - Seconds Register) is read. In the + little-endian mode, this means when Bits[31:24] are read + and in big-endian mode, Bits[7:0] are read. + 0xB48 + 0x20 + read-only + 0x00000000 + + + AUXTSLO + AUXTSLO + 0 + 31 + read-only + + + + + ETH_MACATSSR + ETH_MACATSSR + The Auxiliary Timestamp - Seconds register + contains the lower 32 bits of the Seconds field of the + auxiliary timestamp register. + 0xB4C + 0x20 + read-only + 0x00000000 + + + AUXTSHI + AUXTSHI + 0 + 32 + read-only + + + + + ETH_MACTSIACR + ETH_MACTSIACR + The MAC Timestamp Ingress Asymmetry + Correction register contains the Ingress Asymmetry + Correction value to be used while updating correction + field in PDelay_Resp PTP messages. + 0xB50 + 0x20 + read-write + 0x00000000 + + + OSTIAC + OSTIAC + 0 + 32 + read-write + + + + + ETH_MACTSEACR + ETH_MACTSEACR + The MAC Timestamp Egress Asymmetry + Correction register contains the Egress Asymmetry + Correction value to be used while updating the correction + field in PDelay_Req PTP messages. + 0xB54 + 0x20 + read-write + 0x00000000 + + + OSTEAC + OSTEAC + 0 + 32 + read-write + + + + + ETH_MACTSICNR + ETH_MACTSICNR + This register contains the correction value + in nanoseconds to be used with the captured timestamp + value in the ingress path. + 0xB58 + 0x20 + read-write + 0x00000000 + + + TSIC + TSIC + 0 + 32 + read-write + + + + + ETH_MACTSECNR + ETH_MACTSECNR + This register contains the correction value + in nanoseconds to be used with the captured timestamp + value in the egress path. + 0xB5C + 0x20 + read-write + 0x00000000 + + + TSEC + TSEC + 0 + 32 + read-write + + + + + ETH_MACPPSCR + ETH_MACPPSCR + The PPS Control register is present only + when the Timestamp feature is selected and External + Timestamp is not enabled. Bits[30:24] of this register + are valid only when four Flexible PPS outputs are + selected. Bits[22:16] are valid only when three or more + Flexible PPS outputs are selected. Bits[14:8] are valid + only when two or more Flexible PPS outputs are selected. + Bits[6:4] are valid only when Flexible PPS feature is + selected. + 0xB70 + 0x20 + read-write + 0x00000000 + + + PPSCTRL + PPSCTRL + 0 + 4 + read-write + + + PPSEN0 + PPSEN0 + 4 + 1 + read-write + + + TRGTMODSEL0 + TRGTMODSEL0 + 5 + 2 + read-write + + + + + ETH_MACPPSTTSR + ETH_MACPPSTTSR + The PPS Target Time Seconds register, along + with PPS Target Time Nanoseconds register, is used to + schedule an interrupt event [Bit 1 of ETH_MACTSSR] when + the system time exceeds the value programmed in these + registers. + 0xB80 + 0x20 + read-write + 0x00000000 + + + TSTRH0 + TSTRH0 + 0 + 32 + read-write + + + + + ETH_MACPPSTTNR + ETH_MACPPSTTNR + The PPS Target Time Nanoseconds register is + present only when more than one Flexible PPS output is + selected. + 0xB84 + 0x20 + read-write + 0x00000000 + + + TTSL0 + TTSL0 + 0 + 31 + read-write + + + TRGTBUSY0 + TRGTBUSY0 + 31 + 1 + read-write + + + + + ETH_MACPPSIR + ETH_MACPPSIR + The PPS Interval register contains the + number of units of sub-second increment value between the + rising edges of PPS signal output + (ptp_pps_o[0]). + 0xB88 + 0x20 + read-write + 0x00000000 + + + PPSINT0 + PPSINT0 + 0 + 32 + read-write + + + + + ETH_MACPPSWR + ETH_MACPPSWR + The PPS Width register contains the number + of units of sub-second increment value between the rising + and corresponding falling edges of PPS signal output + (ptp_pps_o). + 0xB8C + 0x20 + read-write + 0x00000000 + + + PPSWIDTH0 + PPSWIDTH0 + 0 + 32 + read-write + + + + + ETH_MACPOCR + ETH_MACPOCR + This register controls the PTP Offload + Engine operation. This register is available only when + the Enable PTP Timestamp Offload feature is + selected. + 0xBC0 + 0x20 + read-write + 0x00000000 + + + PTOEN + PTOEN + 0 + 1 + read-write + + + ASYNCEN + ASYNCEN + 1 + 1 + read-write + + + APDREQEN + APDREQEN + 2 + 1 + read-write + + + ASYNCTRIG + ASYNCTRIG + 4 + 1 + read-write + + + APDREQTRIG + APDREQTRIG + 5 + 1 + read-write + + + DRRDIS + DRRDIS + 6 + 1 + read-write + + + DN + DN + 8 + 8 + read-write + + + + + ETH_MACSPI0R + ETH_MACSPI0R + This register contains Bits[31:0] of the + 80-bit Source Port Identity of the PTP node. This + register is available only when the Enable PTP Timestamp + Offload feature is selected. + 0xBC4 + 0x20 + read-write + 0x00000000 + + + SPI0 + SPI0 + 0 + 32 + read-write + + + + + ETH_MACSPI1R + ETH_MACSPI1R + This register contains Bits[63:32] of the + 80-bit Source Port Identity of the PTP node. This + register is available only when the Enable PTP Timestamp + Offload feature is selected. + 0xBC8 + 0x20 + read-write + 0x00000000 + + + SPI1 + SPI1 + 0 + 32 + read-write + + + + + ETH_MACSPI2R + ETH_MACSPI2R + This register contains Bits[79:64] of the + 80-bit Source Port Identity of the PTP + node. + 0xBCC + 0x20 + read-write + 0x00000000 + + + SPI2 + SPI2 + 0 + 16 + read-write + + + + + ETH_MACLMIR + ETH_MACLMIR + This register contains the periodic + intervals for automatic PTP packet + generation. + 0xBD0 + 0x20 + read-write + 0x00000000 + + + LSI + LSI + 0 + 8 + read-write + + + DRSYNCR + DRSYNCR + 8 + 3 + read-write + + + LMPDRI + LMPDRI + 24 + 8 + read-write + + + + + + + ETH_MTL + ETH_MTL + Ethernet + 0x5800AC00 + + 0x0 + 0x400 + registers + + + + ETH_MTLOMR + ETH_MTLOMR + The Operating Mode register establishes the + Transmit and Receive operating modes and + commands. + 0x000 + 0x20 + read-write + 0x00000000 + + + DTXSTS + DTXSTS + 1 + 1 + read-write + + + RAA + RAA + 2 + 1 + read-write + + + SCHALG + SCHALG + 5 + 2 + read-write + + + CNTPRST + CNTPRST + 8 + 1 + read-write + + + CNTCLR + CNTCLR + 9 + 1 + read-write + + + + + ETH_MTLISR + ETH_MTLISR + The software driver (application) reads this + register during interrupt service routine or polling to + determine the interrupt status of MTL queues and the + MAC. + 0x020 + 0x20 + read-only + 0x00000000 + + + Q0IS + Q0IS + 0 + 1 + read-only + + + Q1IS + Q1IS + 1 + 1 + read-only + + + + + ETH_MTLTxQ0OMR + ETH_MTLTxQ0OMR + Tx queue 0 operating mode + Register + 0x0100 + 0x20 + read-write + 0x00000000 + + + FTQ + FTQ + 0 + 1 + read-write + + + TSF + TSF + 1 + 1 + read-write + + + TXQEN + TXQEN + 2 + 2 + read-write + + + TTC + TTC + 4 + 2 + read-write + + + TQS + TQS + 16 + 9 + read-write + + + + + ETH_MTLTxQ1OMR + ETH_MTLTxQ1OMR + Tx queue 1 operating mode + Register + 0x0140 + 0x20 + read-write + 0x00000000 + + + FTQ + FTQ + 0 + 1 + read-write + + + TSF + TSF + 1 + 1 + read-write + + + TXQEN + TXQEN + 2 + 2 + read-write + + + TTC + TTC + 4 + 2 + read-write + + + TQS + TQS + 16 + 9 + read-write + + + + + ETH_MTLTxQ0UR + ETH_MTLTxQ0UR + Tx queue 0 underflow register + 0x0104 + 0x20 + read-only + 0x00000000 + + + UFFRMCNT + UFFRMCNT + 0 + 11 + read-only + + + UFCNTOVF + UFCNTOVF + 11 + 1 + read-only + + + + + ETH_MTLTxQ1UR + ETH_MTLTxQ1UR + Tx queue 1 underflow register + 0x0144 + 0x20 + read-only + 0x00000000 + + + UFFRMCNT + UFFRMCNT + 0 + 11 + read-only + + + UFCNTOVF + UFCNTOVF + 11 + 1 + read-only + + + + + ETH_MTLTxQ0DR + ETH_MTLTxQ0DR + Tx queue 0 underflow register + 0x0108 + 0x20 + read-only + 0x00000000 + + + TXQPAUSED + TXQPAUSED + 0 + 1 + read-only + + + TRCSTS + TRCSTS + 1 + 2 + read-only + + + TWCSTS + TWCSTS + 3 + 1 + read-only + + + TXQSTS + TXQSTS + 4 + 1 + read-only + + + TXSTSFSTS + TXSTSFSTS + 5 + 1 + read-only + + + PTXQ + PTXQ + 16 + 3 + read-only + + + STXSTSF + STXSTSF + 20 + 3 + read-only + + + + + ETH_MTLTxQ1DR + ETH_MTLTxQ1DR + Tx queue 1 underflow register + 0x0148 + 0x20 + read-only + 0x00000000 + + + TXQPAUSED + TXQPAUSED + 0 + 1 + read-only + + + TRCSTS + TRCSTS + 1 + 2 + read-only + + + TWCSTS + TWCSTS + 3 + 1 + read-only + + + TXQSTS + TXQSTS + 4 + 1 + read-only + + + TXSTSFSTS + TXSTSFSTS + 5 + 1 + read-only + + + PTXQ + PTXQ + 16 + 3 + read-only + + + STXSTSF + STXSTSF + 20 + 3 + read-only + + + + + ETH_MTLTxQ0ESR + ETH_MTLTxQ0ESR + Tx queue x ETS status Register + 0x0114 + 0x20 + read-only + 0x00000000 + + + ABS + ABS + 0 + 24 + read-only + + + + + ETH_MTLTxQ1ESR + ETH_MTLTxQ1ESR + Tx queue x ETS status Register + 0x0154 + 0x20 + read-only + 0x00000000 + + + ABS + ABS + 0 + 24 + read-only + + + + + ETH_MTLQ0ICSR + ETH_MTLQ0ICSR + Queue 0 interrupt control status + Register + 0x012C + 0x20 + read-write + 0x00000000 + + + TXUNFIS + TXUNFIS + 0 + 1 + read-only + + + ABPSIS + ABPSIS + 1 + 1 + read-write + + + TXUIE + TXUIE + 8 + 1 + read-write + + + ABPSIE + ABPSIE + 9 + 1 + read-write + + + RXOVFIS + RXOVFIS + 16 + 1 + read-write + + + RXOIE + RXOIE + 24 + 1 + read-write + + + + + ETH_MTLQ1ICSR + ETH_MTLQ1ICSR + Queue 1 interrupt control status + Register + 0x016C + 0x20 + read-write + 0x00000000 + + + TXUNFIS + TXUNFIS + 0 + 1 + read-only + + + ABPSIS + ABPSIS + 1 + 1 + read-write + + + TXUIE + TXUIE + 8 + 1 + read-write + + + ABPSIE + ABPSIE + 9 + 1 + read-write + + + RXOVFIS + RXOVFIS + 16 + 1 + read-write + + + RXOIE + RXOIE + 24 + 1 + read-write + + + + + ETH_MTLRxQ0OMR + ETH_MTLRxQ0OMR + Rx queue 0 operating mode + register + 0x0130 + 0x20 + read-write + 0x00700000 + + + RTC + RTC + 0 + 2 + read-write + + + FUP + FUP + 3 + 1 + read-write + + + FEP + FEP + 4 + 1 + read-write + + + RSF + RSF + 5 + 1 + read-write + + + DIS_TCP_EF + DIS_TCP_EF + 6 + 1 + read-write + + + EHFC + EHFC + 7 + 1 + read-write + + + RFA + RFA + 8 + 3 + read-write + + + RFD + RFD + 14 + 3 + read-write + + + RQS + RQS + 20 + 4 + read-only + + + + + ETH_MTLRxQ1OMR + ETH_MTLRxQ1OMR + Rx queue 1 operating mode + register + 0x0170 + 0x20 + read-write + 0x00700000 + + + RTC + RTC + 0 + 2 + read-write + + + FUP + FUP + 3 + 1 + read-write + + + FEP + FEP + 4 + 1 + read-write + + + RSF + RSF + 5 + 1 + read-write + + + DIS_TCP_EF + DIS_TCP_EF + 6 + 1 + read-write + + + EHFC + EHFC + 7 + 1 + read-write + + + RFA + RFA + 8 + 3 + read-write + + + RFD + RFD + 14 + 3 + read-write + + + RQS + RQS + 20 + 4 + read-only + + + + + ETH_MTLRxQ0MPOCR + ETH_MTLRxQ0MPOCR + Rx queue 0 missed packet and overflow + counter register + 0x0134 + 0x20 + read-only + 0x00000000 + + + OVFPKTCNT + OVFPKTCNT + 0 + 11 + read-only + + + OVFCNTOVF + OVFCNTOVF + 11 + 1 + read-only + + + MISPKTCNT + MISPKTCNT + 16 + 11 + read-only + + + MISCNTOVF + MISCNTOVF + 27 + 1 + read-only + + + + + ETH_MTLRxQ1MPOCR + ETH_MTLRxQ1MPOCR + Rx queue 1 missed packet and overflow + counter register + 0x0174 + 0x20 + read-only + 0x00000000 + + + OVFPKTCNT + OVFPKTCNT + 0 + 11 + read-only + + + OVFCNTOVF + OVFCNTOVF + 11 + 1 + read-only + + + MISPKTCNT + MISPKTCNT + 16 + 11 + read-only + + + MISCNTOVF + MISCNTOVF + 27 + 1 + read-only + + + + + ETH_MTLRxQ0DR + ETH_MTLRxQ0DR + Rx queue i debug register + 0x0138 + 0x20 + read-only + 0x00000000 + + + RWCSTS + RWCSTS + 0 + 1 + read-only + + + RRCSTS + RRCSTS + 1 + 2 + read-only + + + RXQSTS + RXQSTS + 4 + 2 + read-only + + + PRXQ + PRXQ + 16 + 14 + read-only + + + + + ETH_MTLRxQ1DR + ETH_MTLRxQ1DR + Rx queue i debug register + 0x0178 + 0x20 + read-only + 0x00000000 + + + RWCSTS + RWCSTS + 0 + 1 + read-only + + + RRCSTS + RRCSTS + 1 + 2 + read-only + + + RXQSTS + RXQSTS + 4 + 2 + read-only + + + PRXQ + PRXQ + 16 + 14 + read-only + + + + + ETH_MTLRxQ0CR + ETH_MTLRxQ0CR + Rx queue 0 control register + 0x013C + 0x20 + read-write + 0x00000000 + + + RXQ_WEGT + RXQ_WEGT + 0 + 3 + read-only + + + RXQ_FRM_ARBIT + RXQ_FRM_ARBIT + 3 + 1 + read-only + + + + + ETH_MTLRxQ1CR + ETH_MTLRxQ1CR + Rx queue 1 control register + 0x017C + 0x20 + read-write + 0x00000000 + + + RXQ_WEGT + RXQ_WEGT + 0 + 3 + read-only + + + RXQ_FRM_ARBIT + RXQ_FRM_ARBIT + 3 + 1 + read-only + + + + + ETH_MTLTxQ1ECR + ETH_MTLTxQ1ECR + The Queue ETS Control register controls the + enhanced transmission selection operation. + 0x150 + 0x20 + read-write + 0x00000000 + + + AVALG + AVALG + 2 + 1 + read-write + + + CC + CC + 3 + 1 + read-write + + + SLC + SLC + 4 + 3 + read-write + + + + + ETH_MTLTxQ1QWR + ETH_MTLTxQ1QWR + This register provides the average traffic + transmitted on queue 1. + 0x158 + 0x20 + read-write + 0x00000000 + + + ISCQW + ISCQW + 0 + 21 + read-write + + + + + ETH_MTLTxQ1SSCR + ETH_MTLTxQ1SSCR + The sendSlopeCredit register contains the + sendSlope credit value required for the credit-based + shaper algorithm for the Queue. + 0x15C + 0x20 + read-write + 0x00000000 + + + SSC + SSC + 0 + 14 + read-write + + + + + ETH_MTLTxQ1HCR + ETH_MTLTxQ1HCR + The hiCredit register contains the hiCredit + value required for the credit-based shaper algorithm for + the Queue. + 0x160 + 0x20 + read-write + 0x00000000 + + + HC + HC + 0 + 29 + read-write + + + + + ETH_MTLTxQ1LCR + ETH_MTLTxQ1LCR + The loCredit register contains the loCredit + value required for the credit-based shaper algorithm for + the Queue. + 0x164 + 0x20 + read-write + 0x00000000 + + + LC + LC + 0 + 29 + read-write + + + + + + + ETH_DMA + ETH_DMA + Ethernet + 0x5800B000 + + 0x0 + 0x400 + registers + + + + ETH_DMAMR + ETH_DMAMR + DMA mode register + 0x0000 + 0x20 + read-write + 0x0008000 + + + SWR + Software Reset + 0 + 1 + + + TAA + TAA + 2 + 3 + + + TXPR + Transmit priority + 11 + 1 + + + PR + Priority ratio + 12 + 3 + + + INTM + Interrupt Mode + 16 + 2 + + + + + ETH_DMASBMR + ETH_DMASBMR + System bus mode register + 0x0004 + 0x20 + read-write + 0x0008000 + + + FB + Fixed Burst Length + 0 + 1 + + + BLEN4 + BLEN4 + 1 + 1 + + + BLEN8 + BLEN8 + 2 + 1 + + + BLEN16 + BLEN16 + 3 + 1 + + + BLEN32 + BLEN32 + 4 + 1 + + + BLEN64 + BLEN64 + 5 + 1 + + + BLEN128 + BLEN128 + 6 + 1 + + + BLEN256 + BLEN256 + 7 + 1 + + + AAL + Address-Aligned Beats + 12 + 1 + + + ONEKBBE + ONEKBBE + 13 + 1 + + + RD_OSR_LMT + RD_OSR_LMT + 16 + 2 + + + WR_OSR_LMT + WR_OSR_LMT + 24 + 2 + + + LPI_XIT_PKT + LPI_XIT_PKT + 30 + 1 + + + EN_LPI + EN_LPI + 31 + 1 + + + + + ETH_DMAISR + ETH_DMAISR + Interrupt status register + 0x0008 + 0x20 + read-only + 0x0008000 + + + DC0IS + DMA Channel Interrupt + Status + 0 + 1 + + + DC1IS + DC1IS + 1 + 1 + + + MTLIS + MTL Interrupt Status + 16 + 1 + + + MACIS + MAC Interrupt Status + 17 + 1 + + + + + ETH_DMADSR + ETH_DMADSR + Debug status register + 0x000C + 0x20 + read-only + 0x00000000 + + + AXWHSTS + AHB Master Write Channel + 0 + 1 + + + AXRHSTS + AXRHSTS + 1 + 1 + + + RPS0 + RPS0 + 8 + 4 + + + TPS0 + TPS0 + 12 + 4 + + + RPS1 + RPS1 + 16 + 4 + + + TPS1 + TPS1 + 20 + 4 + + + + + ETH_DMAA4TxACR + ETH_DMAA4TxACR + AXI4 transmit channel ACE control + register + 0x0020 + 0x20 + read-write + 0x00000000 + + + TDRC + TDRC + 0 + 4 + + + TEC + TEC + 8 + 4 + + + THC + THC + 16 + 4 + + + + + ETH_DMAA4RxACR + ETH_DMAA4RxACR + AXI4 receive channel ACE control + register + 0x0024 + 0x20 + read-write + 0x00000000 + + + RDWC + RDWC + 0 + 4 + + + RPC + RPC + 8 + 4 + + + RHC + RHC + 16 + 4 + + + RDC + RDC + 24 + 2 + + + + + ETH_DMAA4DACR + ETH_DMAA4DACR + AXI4 descriptor ACE control + register + 0x0028 + 0x20 + read-write + 0x00000000 + + + TDWC + TDWC + 0 + 4 + + + TDWD + TDWD + 4 + 2 + + + RDRC + RDRC + 8 + 4 + + + RDP + RDP + 16 + 3 + + + WRP + WRP + 20 + 3 + + + + + ETH_DMAC0CR + ETH_DMAC0CR + Channel 0 control register + 0x0100 + 0x20 + read-write + 0x00000000 + + + MSS + MSS + 0 + 14 + + + PBLX8 + PBLX8 + 16 + 1 + + + DSL + DSL + 18 + 3 + + + + + ETH_DMAC1CR + ETH_DMAC1CR + Channel 1 control register + 0x0180 + 0x20 + read-write + 0x00000000 + + + MSS + MSS + 0 + 14 + + + PBLX8 + PBLX8 + 16 + 1 + + + DSL + DSL + 18 + 3 + + + + + ETH_DMAC0TxCR + ETH_DMAC0TxCR + Channel 0 transmit control + register + 0x0104 + 0x20 + read-write + 0x00000000 + + + ST + ST + 0 + 1 + + + TCW + TCW + 1 + 3 + + + OSF + OSF + 4 + 1 + + + TSE + TSE + 12 + 1 + + + TXPBL + TXPBL + 16 + 6 + + + TQOS + TQOS + 24 + 4 + + + + + ETH_DMAC1TxCR + ETH_DMAC1TxCR + Channel 1 transmit control + register + 0x0184 + 0x20 + read-write + 0x00000000 + + + ST + ST + 0 + 1 + + + TCW + TCW + 1 + 3 + + + OSF + OSF + 4 + 1 + + + TSE + TSE + 12 + 1 + + + TXPBL + TXPBL + 16 + 6 + + + TQOS + TQOS + 24 + 4 + + + + + ETH_DMAC0RxCR + ETH_DMAC0RxCR + Channel receive control + register + 0x0108 + 0x20 + read-write + 0x0008000 + + + SR + Start or Stop Receive + Command + 0 + 1 + + + RBSZ + Receive Buffer size + 1 + 14 + + + RXPBL + RXPBL + 16 + 6 + + + RQOS + RQOS + 24 + 4 + + + RPF + DMA Rx Channel Packet + Flush + 31 + 1 + + + + + ETH_DMAC0TxDLAR + ETH_DMAC0TxDLAR + Channel i Tx descriptor list address + register + 0x0114 + 0x20 + read-write + 0x0000000 + + + TDESLA + Start of Transmit List + 3 + 29 + + + + + ETH_DMAC1TxDLAR + ETH_DMAC1TxDLAR + Channel i Tx descriptor list address + register + 0x0194 + 0x20 + read-write + 0x0000000 + + + TDESLA + Start of Transmit List + 3 + 29 + + + + + ETH_DMAC0RxDLAR + ETH_DMAC0RxDLAR + Channel Rx descriptor list address + register + 0x011C + 0x20 + read-write + 0x0008000 + + + RDESLA + Start of Receive List + 3 + 29 + + + + + ETH_DMAC0TxDTPR + ETH_DMAC0TxDTPR + Channel Tx descriptor tail pointer + register + 0x0120 + 0x20 + read-write + 0x0000000 + + + TDT + Transmit Descriptor Tail + Pointer + 3 + 29 + + + + + ETH_DMAC1TxDTPR + ETH_DMAC1TxDTPR + Channel Tx descriptor tail pointer + register + 0x01A0 + 0x20 + read-write + 0x0000000 + + + TDT + Transmit Descriptor Tail + Pointer + 3 + 29 + + + + + ETH_DMAC0RxDTPR + ETH_DMAC0RxDTPR + Channel Rx descriptor tail pointer + register + 0x0128 + 0x20 + read-write + 0x0000000 + + + RDT + Receive Descriptor Tail + Pointer + 3 + 29 + + + + + ETH_DMAC0TxRLR + ETH_DMAC0TxRLR + Channel Tx descriptor ring length + register + 0x012C + 0x20 + read-write + 0x0000000 + + + TDRL + Transmit Descriptor Ring + Length + 0 + 10 + + + + + ETH_DMAC1TxRLR + ETH_DMAC1TxRLR + Channel Tx descriptor ring length + register + 0x01AC + 0x20 + read-write + 0x0000000 + + + TDRL + Transmit Descriptor Ring + Length + 0 + 10 + + + + + ETH_DMAC0RxRLR + ETH_DMAC0RxRLR + Channel Rx descriptor ring length + register + 0x0130 + 0x20 + read-write + 0x0008000 + + + RDRL + Receive Descriptor Ring + Length + 0 + 10 + + + + + ETH_DMAC0IER + ETH_DMACIER + Channel interrupt enable + register + 0x0134 + 0x20 + read-write + 0x0008000 + + + TIE + Transmit Interrupt Enable + 0 + 1 + + + TXSE + Transmit Stopped Enable + 1 + 1 + + + TBUE + Transmit Buffer Unavailable + Enable + 2 + 1 + + + RIE + Receive Interrupt Enable + 6 + 1 + + + RBUE + Receive Buffer Unavailable + Enable + 7 + 1 + + + RSE + Receive Stopped Enable + 8 + 1 + + + RWTE + Receive Watchdog Timeout + Enable + 9 + 1 + + + ETIE + Early Transmit Interrupt + Enable + 10 + 1 + + + ERIE + Early Receive Interrupt + Enable + 11 + 1 + + + FBEE + Fatal Bus Error Enable + 12 + 1 + + + CDEE + Context Descriptor Error + Enable + 13 + 1 + + + AIE + Abnormal Interrupt Summary + Enable + 14 + 1 + + + NIE + Normal Interrupt Summary + Enable + 15 + 1 + + + + + ETH_DMAC1IER + ETH_DMAC1IER + Channel interrupt enable + register + 0x01B4 + 0x20 + read-write + 0x0008000 + + + TIE + Transmit Interrupt Enable + 0 + 1 + + + TXSE + Transmit Stopped Enable + 1 + 1 + + + TBUE + Transmit Buffer Unavailable + Enable + 2 + 1 + + + RIE + Receive Interrupt Enable + 6 + 1 + + + RBUE + Receive Buffer Unavailable + Enable + 7 + 1 + + + RSE + Receive Stopped Enable + 8 + 1 + + + RWTE + Receive Watchdog Timeout + Enable + 9 + 1 + + + ETIE + Early Transmit Interrupt + Enable + 10 + 1 + + + ERIE + Early Receive Interrupt + Enable + 11 + 1 + + + FBEE + Fatal Bus Error Enable + 12 + 1 + + + CDEE + Context Descriptor Error + Enable + 13 + 1 + + + AIE + Abnormal Interrupt Summary + Enable + 14 + 1 + + + NIE + Normal Interrupt Summary + Enable + 15 + 1 + + + + + ETH_DMAC0RxIWTR + ETH_DMAC0RxIWTR + Channel Rx interrupt watchdog timer + register + 0x0138 + 0x20 + read-write + 0x0000000 + + + RWT + Receive Interrupt Watchdog Timer + Count + 0 + 8 + + + + + ETH_DMAC0SFCSR + ETH_DMAC0SFCSR + Channel i slot function control status + register + 0x013C + 0x20 + read-write + 0x0000000 + + + ESC + ESC + 0 + 1 + + + ASC + ASC + 1 + 1 + + + RSN + RSN + 16 + 4 + + + + + ETH_DMAC1SFCSR + ETH_DMAC1SFCSR + Channel i slot function control status + register + 0x01BC + 0x20 + read-write + 0x0000000 + + + ESC + ESC + 0 + 1 + + + ASC + ASC + 1 + 1 + + + RSN + RSN + 16 + 4 + + + + + ETH_DMAC0CATxDR + ETH_DMAC0CATxDR + Channel current application transmit + descriptor register + 0x0144 + 0x20 + read-only + 0x0000000 + + + CURTDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + ETH_DMAC1CATxDR + ETH_DMAC1CATxDR + Channel current application transmit + descriptor register + 0x01C4 + 0x20 + read-only + 0x0000000 + + + CURTDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + ETH_DMAC0CARxDR + ETH_DMAC0CARxDR + Channel 0 current application receive + descriptor register + DMAC1CATxDR + 0x014C + 0x20 + read-only + 0x0000000 + + + CURRDESAPTR + Application Transmit Descriptor Address + Pointer + 0 + 32 + + + + + ETH_DMAC0CATxBR + ETH_DMAC0CATxBR + Channel 0 current application transmit + buffer register + 0x0154 + 0x20 + read-only + 0x0000000 + + + CURTBUFAPTR + Application Transmit Buffer Address + Pointer + 0 + 32 + + + + + ETH_DMAC1CATxBR + ETH_DMAC1CATxBR + Channel 0 current application transmit + buffer register + 0x01D4 + 0x20 + read-only + 0x0000000 + + + CURTBUFAPTR + Application Transmit Buffer Address + Pointer + 0 + 32 + + + + + ETH_DMAC0CARxBR + ETH_DMACCARxBR + Channel current application receive buffer + register + 0x015C + 0x20 + read-only + 0x0000000 + + + CURRBUFAPTR + Application Receive Buffer Address + Pointer + 0 + 32 + + + + + ETH_DMAC0SR + ETH_DMAC0SR + Channel status register + 0x0160 + 0x20 + read-write + 0x0000000 + + + TI + Transmit Interrupt + 0 + 1 + + + TPS + Transmit Process Stopped + 1 + 1 + + + TBU + Transmit Buffer + Unavailable + 2 + 1 + + + RI + Receive Interrupt + 6 + 1 + + + RBU + Receive Buffer Unavailable + 7 + 1 + + + RPS + Receive Process Stopped + 8 + 1 + + + RWT + Receive Watchdog Timeout + 9 + 1 + + + ETI + Early Transmit Interrupt + 10 + 1 + + + ERI + Early Receive Interrupt + 11 + 1 + + + FBE + Fatal Bus Error + 12 + 1 + + + CDE + Context Descriptor Error + 13 + 1 + + + AIS + Abnormal Interrupt Summary + 14 + 1 + + + NIS + Normal Interrupt Summary + 15 + 1 + + + TEB + Tx DMA Error Bits + 16 + 3 + + + REB + Rx DMA Error Bits + 19 + 3 + + + + + ETH_DMAC1SR + ETH_DMAC1SR + Channel status register + 0x01E0 + 0x20 + read-write + 0x0000000 + + + TI + Transmit Interrupt + 0 + 1 + + + TPS + Transmit Process Stopped + 1 + 1 + + + TBU + Transmit Buffer + Unavailable + 2 + 1 + + + RI + Receive Interrupt + 6 + 1 + + + RBU + Receive Buffer Unavailable + 7 + 1 + + + RPS + Receive Process Stopped + 8 + 1 + + + RWT + Receive Watchdog Timeout + 9 + 1 + + + ETI + Early Transmit Interrupt + 10 + 1 + + + ERI + Early Receive Interrupt + 11 + 1 + + + FBE + Fatal Bus Error + 12 + 1 + + + CDE + Context Descriptor Error + 13 + 1 + + + AIS + Abnormal Interrupt Summary + 14 + 1 + + + NIS + Normal Interrupt Summary + 15 + 1 + + + TEB + Tx DMA Error Bits + 16 + 3 + + + REB + Rx DMA Error Bits + 19 + 3 + + + + + ETH_DMAC0MFCR + ETH_DMAC0MFCR + Channel missed frame count + register + 0x016C + 0x20 + read-only + 0x0000000 + + + MFC + Dropped Packet Counters + 0 + 11 + + + MFCO + Overflow status of the MFC + Counter + 15 + 1 + + + + + ETH_DMAC1MFCR + ETH_DMAC1MFCR + Channel missed frame count + register + 0x01EC + 0x20 + read-only + 0x0000000 + + + MFC + Dropped Packet Counters + 0 + 11 + + + MFCO + Overflow status of the MFC + Counter + 15 + 1 + + + + + + + EXTI + EXTI + EXTI + 0x5000D000 + + 0x0 + 0x400 + registers + + + PVD_AVD + PVD AND AVD detector through EXTI + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI4 + EXTI Line 4 interrupt + 10 + + + EXTI5 + EXTI line 5 interrupt + 23 + + + EXTI10 + EXTI line 10 interrupt + 40 + + + EXTI11 + EXTI line 11 interrupt + 42 + + + EXTI11 + EXTI line 11 interrupt + 42 + + + EXTI6 + EXTI line 6 interrupt + 64 + + + EXTI7 + EXTI line 7 interrupt + 65 + + + EXTI8 + EXTI line 8 interrupt + 66 + + + EXTI9 + EXTI line 9 interrupt + 67 + + + EXTI12 + EXTI line 12 interrupt + 76 + + + EXTI13 + EXTI line 13 interrupt + 77 + + + EXTI14 + EXTI line 14 interrupt + 121 + + + EXTI15 + EXTI line 15 interrupt + 127 + + + + EXTI_RTSR1 + EXTI_RTSR1 + Contains only register bits for configurable events. + 0x0 + 0x20 + read-write + 0x00000000 + + + RT0 + RT0 + 0 + 1 + + + RT1 + RT1 + 1 + 1 + + + RT2 + RT2 + 2 + 1 + + + RT3 + RT3 + 3 + 1 + + + RT4 + RT4 + 4 + 1 + + + RT5 + RT5 + 5 + 1 + + + RT6 + RT6 + 6 + 1 + + + RT7 + RT7 + 7 + 1 + + + RT8 + RT8 + 8 + 1 + + + RT9 + RT9 + 9 + 1 + + + RT10 + RT10 + 10 + 1 + + + RT11 + RT11 + 11 + 1 + + + RT12 + RT12 + 12 + 1 + + + RT13 + RT13 + 13 + 1 + + + RT14 + RT14 + 14 + 1 + + + RT15 + RT15 + 15 + 1 + + + RT16 + RT16 + 16 + 1 + + + + + EXTI_FTSR1 + EXTI_FTSR1 + Contains only register bits for configurable events. + 0x4 + 0x20 + read-write + 0x00000000 + + + FT0 + FT0 + 0 + 1 + + + FT1 + FT1 + 1 + 1 + + + FT2 + FT2 + 2 + 1 + + + FT3 + FT3 + 3 + 1 + + + FT4 + FT4 + 4 + 1 + + + FT5 + FT5 + 5 + 1 + + + FT6 + FT6 + 6 + 1 + + + FT7 + FT7 + 7 + 1 + + + FT8 + FT8 + 8 + 1 + + + FT9 + FT9 + 9 + 1 + + + FT10 + FT10 + 10 + 1 + + + FT11 + FT11 + 11 + 1 + + + FT12 + FT12 + 12 + 1 + + + FT13 + FT13 + 13 + 1 + + + FT14 + FT14 + 14 + 1 + + + FT15 + FT15 + 15 + 1 + + + FT16 + FT16 + 16 + 1 + + + + + EXTI_SWIER1 + EXTI_SWIER1 + Contains only register bits for configurable events. + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI0 + SWI0 + 0 + 1 + + + SWI1 + SWI1 + 1 + 1 + + + SWI2 + SWI2 + 2 + 1 + + + SWI3 + SWI3 + 3 + 1 + + + SWI4 + SWI4 + 4 + 1 + + + SWI5 + SWI5 + 5 + 1 + + + SWI6 + SWI6 + 6 + 1 + + + SWI7 + SWI7 + 7 + 1 + + + SWI8 + SWI8 + 8 + 1 + + + SWI9 + SWI9 + 9 + 1 + + + SWI10 + SWI10 + 10 + 1 + + + SWI11 + SWI11 + 11 + 1 + + + SWI12 + SWI12 + 12 + 1 + + + SWI13 + SWI13 + 13 + 1 + + + SWI14 + SWI14 + 14 + 1 + + + SWI15 + SWI15 + 15 + 1 + + + SWI16 + SWI16 + 16 + 1 + + + + + EXTI_RPR1 + EXTI_RPR1 + Contains only register bits for configurable events. + 0xC + 0x20 + read-write + 0x00000000 + + + RPIF0 + RPIF0 + 0 + 1 + + + RPIF1 + RPIF1 + 1 + 1 + + + RPIF2 + RPIF2 + 2 + 1 + + + RPIF3 + RPIF3 + 3 + 1 + + + RPIF4 + RPIF4 + 4 + 1 + + + RPIF5 + RPIF5 + 5 + 1 + + + RPIF6 + RPIF6 + 6 + 1 + + + RPIF7 + RPIF7 + 7 + 1 + + + RPIF8 + RPIF8 + 8 + 1 + + + RPIF9 + RPIF9 + 9 + 1 + + + RPIF10 + RPIF10 + 10 + 1 + + + RPIF11 + RPIF11 + 11 + 1 + + + RPIF12 + RPIF12 + 12 + 1 + + + RPIF13 + RPIF13 + 13 + 1 + + + RPIF14 + RPIF14 + 14 + 1 + + + RPIF15 + RPIF15 + 15 + 1 + + + RPIF16 + RPIF16 + 16 + 1 + + + + + EXTI_FPR1 + EXTI_FPR1 + Contains only register bits for configurable events. + 0x10 + 0x20 + read-write + 0x00000000 + + + FPIF0 + FPIF0 + 0 + 1 + + + FPIF1 + FPIF1 + 1 + 1 + + + FPIF2 + FPIF2 + 2 + 1 + + + FPIF3 + FPIF3 + 3 + 1 + + + FPIF4 + FPIF4 + 4 + 1 + + + FPIF5 + FPIF5 + 5 + 1 + + + FPIF6 + FPIF6 + 6 + 1 + + + FPIF7 + FPIF7 + 7 + 1 + + + FPIF8 + FPIF8 + 8 + 1 + + + FPIF9 + FPIF9 + 9 + 1 + + + FPIF10 + FPIF10 + 10 + 1 + + + FPIF11 + FPIF11 + 11 + 1 + + + FPIF12 + FPIF12 + 12 + 1 + + + FPIF13 + FPIF13 + 13 + 1 + + + FPIF14 + FPIF14 + 14 + 1 + + + FPIF15 + FPIF15 + 15 + 1 + + + FPIF16 + FPIF16 + 16 + 1 + + + + + EXTI_TZENR1 + EXTI_TZENR1 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x14 + 0x20 + read-write + 0x00000000 + + + TZEN0 + TZEN0 + 0 + 1 + + + TZEN1 + TZEN1 + 1 + 1 + + + TZEN2 + TZEN2 + 2 + 1 + + + TZEN3 + TZEN3 + 3 + 1 + + + TZEN4 + TZEN4 + 4 + 1 + + + TZEN5 + TZEN5 + 5 + 1 + + + TZEN6 + TZEN6 + 6 + 1 + + + TZEN7 + TZEN7 + 7 + 1 + + + TZEN8 + TZEN8 + 8 + 1 + + + TZEN9 + TZEN9 + 9 + 1 + + + TZEN10 + TZEN10 + 10 + 1 + + + TZEN11 + TZEN11 + 11 + 1 + + + TZEN12 + TZEN12 + 12 + 1 + + + TZEN13 + TZEN13 + 13 + 1 + + + TZEN14 + TZEN14 + 14 + 1 + + + TZEN15 + TZEN15 + 15 + 1 + + + TZEN17 + TZEN17 + 17 + 1 + + + TZEN18 + TZEN18 + 18 + 1 + + + TZEN19 + TZEN19 + 19 + 1 + + + TZEN24 + TZEN24 + 24 + 1 + + + TZEN26 + TZEN26 + 26 + 1 + + + + + EXTI_RTSR2 + EXTI_RTSR2 + Contains only register bits for configurable events. + 0x20 + 0x20 + read-write + 0x00000000 + + + EXTI_FTSR2 + EXTI_FTSR2 + Contains only register bits for configurable events. + 0x24 + 0x20 + read-write + 0x00000000 + + + EXTI_SWIER2 + EXTI_SWIER2 + Contains only register bits for configurable events. + 0x28 + 0x20 + read-write + 0x00000000 + + + EXTI_RPR2 + EXTI_RPR2 + Contains only register bits for configurable events. + 0x2C + 0x20 + read-write + 0x00000000 + + + EXTI_FPR2 + EXTI_FPR2 + Contains only register bits for configurable events. + 0x30 + 0x20 + read-write + 0x00000000 + + + EXTI_TZENR2 + EXTI_TZENR2 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x34 + 0x20 + read-write + 0x00000000 + + + TZEN41 + TZEN41 + 9 + 1 + + + TZEN54 + TZEN54 + 22 + 1 + + + TZEN55 + TZEN55 + 23 + 1 + + + TZEN56 + TZEN56 + 24 + 1 + + + TZEN57 + TZEN57 + 25 + 1 + + + TZEN58 + TZEN58 + 26 + 1 + + + TZEN59 + TZEN59 + 27 + 1 + + + TZEN60 + TZEN60 + 28 + 1 + + + + + EXTI_RTSR3 + EXTI_RTSR3 + Contains only register bits for configurable events. + 0x40 + 0x20 + read-write + 0x00000000 + + + RT65 + RT65 + 1 + 1 + + + RT66 + RT66 + 2 + 1 + + + RT68 + RT68 + 4 + 1 + + + RT73 + RT73 + 9 + 1 + + + RT74 + RT74 + 10 + 1 + + + + + EXTI_FTSR3 + EXTI_FTSR3 + Contains only register bits for configurable events. + 0x44 + 0x20 + read-write + 0x00000000 + + + FT65 + FT65 + 1 + 1 + + + FT66 + FT66 + 2 + 1 + + + FT68 + FT68 + 4 + 1 + + + FT73 + FT73 + 9 + 1 + + + FT74 + FT74 + 10 + 1 + + + + + EXTI_SWIER3 + EXTI_SWIER3 + Contains only register bits for configurable events. + 0x48 + 0x20 + read-write + 0x00000000 + + + SWI65 + SWI65 + 1 + 1 + + + SWI66 + SWI66 + 2 + 1 + + + SWI68 + SWI68 + 4 + 1 + + + SWI73 + SWI73 + 9 + 1 + + + SWI74 + SWI74 + 10 + 1 + + + + + EXTI_RPR3 + EXTI_RPR3 + Contains only register bits for configurable events. + 0x4C + 0x20 + read-write + 0x00000000 + + + RPIF65 + RPIF65 + 1 + 1 + + + RPIF66 + RPIF66 + 2 + 1 + + + RPIF68 + RPIF68 + 4 + 1 + + + RPIF73 + RPIF73 + 9 + 1 + + + RPIF74 + RPIF74 + 10 + 1 + + + + + EXTI_FPR3 + EXTI_FPR3 + Contains only register bits for configurable events. + 0x50 + 0x20 + read-write + 0x00000000 + + + FPIF65 + FPIF65 + 1 + 1 + + + FPIF66 + FPIF66 + 2 + 1 + + + FPIF68 + FPIF68 + 4 + 1 + + + FPIF73 + FPIF73 + 9 + 1 + + + FPIF74 + FPIF74 + 10 + 1 + + + + + EXTI_TZENR3 + EXTI_TZENR3 + This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. + 0x54 + 0x20 + read-write + 0x00000000 + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x60 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 + 0 + 8 + + + EXTI1 + EXTI1 + 8 + 8 + + + EXTI2 + EXTI2 + 16 + 8 + + + EXTI3 + EXTI3 + 24 + 8 + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x64 + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 + 0 + 8 + + + EXTI5 + EXTI5 + 8 + 8 + + + EXTI6 + EXTI6 + 16 + 8 + + + EXTI7 + EXTI7 + 24 + 8 + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x68 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 + 0 + 8 + + + EXTI9 + EXTI9 + 8 + 8 + + + EXTI10 + EXTI10 + 16 + 8 + + + EXTI11 + EXTI11 + 24 + 8 + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTIm fields contain only the number of bits in line with the nb_ioport configuration. + 0x6C + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 + 0 + 8 + + + EXTI13 + EXTI13 + 8 + 8 + + + EXTI14 + EXTI14 + 16 + 8 + + + EXTI15 + EXTI15 + 24 + 8 + + + + + EXTI_IMR1 + EXTI_IMR1 + Contains register bits for configurable events and Direct events. + 0x80 + 0x20 + read-write + 0xFFFE0000 + + + IM0 + IM0 + 0 + 1 + + + IM1 + IM1 + 1 + 1 + + + IM2 + IM2 + 2 + 1 + + + IM3 + IM3 + 3 + 1 + + + IM4 + IM4 + 4 + 1 + + + IM5 + IM5 + 5 + 1 + + + IM6 + IM6 + 6 + 1 + + + IM7 + IM7 + 7 + 1 + + + IM8 + IM8 + 8 + 1 + + + IM9 + IM9 + 9 + 1 + + + IM10 + IM10 + 10 + 1 + + + IM11 + IM11 + 11 + 1 + + + IM12 + IM12 + 12 + 1 + + + IM13 + IM13 + 13 + 1 + + + IM14 + IM14 + 14 + 1 + + + IM15 + IM15 + 15 + 1 + + + IM16 + IM16 + 16 + 1 + + + IM17 + IM17 + 17 + 1 + + + IM18 + IM18 + 18 + 1 + + + IM19 + IM19 + 19 + 1 + + + IM20 + IM20 + 20 + 1 + + + IM21 + IM21 + 21 + 1 + + + IM22 + IM22 + 22 + 1 + + + IM23 + IM23 + 23 + 1 + + + IM24 + IM24 + 24 + 1 + + + IM25 + IM25 + 25 + 1 + + + IM26 + IM26 + 26 + 1 + + + IM27 + IM27 + 27 + 1 + + + IM28 + IM28 + 28 + 1 + + + IM29 + IM29 + 29 + 1 + + + IM30 + IM30 + 30 + 1 + + + IM31 + IM31 + 31 + 1 + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wakeup with event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + EM0 + EM0 + 0 + 1 + + + EM1 + EM1 + 1 + 1 + + + EM2 + EM2 + 2 + 1 + + + EM3 + EM3 + 3 + 1 + + + EM4 + EM4 + 4 + 1 + + + EM5 + EM5 + 5 + 1 + + + EM6 + EM6 + 6 + 1 + + + EM7 + EM7 + 7 + 1 + + + EM8 + EM8 + 8 + 1 + + + EM9 + EM9 + 9 + 1 + + + EM10 + EM10 + 10 + 1 + + + EM11 + EM11 + 11 + 1 + + + EM12 + EM12 + 12 + 1 + + + EM13 + EM13 + 13 + 1 + + + EM14 + EM14 + 14 + 1 + + + EM15 + EM15 + 15 + 1 + + + EM17 + EM17 + 17 + 1 + + + EM18 + EM18 + 18 + 1 + + + EM19 + EM19 + 19 + 1 + + + + + EXTI_IMR2 + EXTI_IMR2 + Contains register bits for configurable events and direct events. + 0x90 + 0x20 + read-write + 0xFFFFFFFF + + + IM32 + IM32 + 0 + 1 + + + IM33 + IM33 + 1 + 1 + + + IM34 + IM34 + 2 + 1 + + + IM35 + IM35 + 3 + 1 + + + IM36 + IM36 + 4 + 1 + + + IM37 + IM37 + 5 + 1 + + + IM38 + IM38 + 6 + 1 + + + IM39 + IM39 + 7 + 1 + + + IM40 + IM40 + 8 + 1 + + + IM41 + IM41 + 9 + 1 + + + IM42 + IM42 + 10 + 1 + + + IM43 + IM43 + 11 + 1 + + + IM44 + IM44 + 12 + 1 + + + IM45 + IM45 + 13 + 1 + + + IM46 + IM46 + 14 + 1 + + + IM47 + IM47 + 15 + 1 + + + IM48 + IM48 + 16 + 1 + + + IM49 + IM49 + 17 + 1 + + + IM50 + IM50 + 18 + 1 + + + IM51 + IM51 + 19 + 1 + + + IM52 + IM52 + 20 + 1 + + + IM53 + IM53 + 21 + 1 + + + IM54 + IM54 + 22 + 1 + + + IM55 + IM55 + 23 + 1 + + + IM56 + IM56 + 24 + 1 + + + IM57 + IM57 + 25 + 1 + + + IM58 + IM58 + 26 + 1 + + + IM59 + IM59 + 27 + 1 + + + IM60 + IM60 + 28 + 1 + + + IM61 + IM61 + 29 + 1 + + + IM62 + IM62 + 30 + 1 + + + IM63 + IM63 + 31 + 1 + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wakeup with event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + EXTI_IMR3 + EXTI_IMR3 + Contains register bits for configurable events and direct events. + 0xA0 + 0x20 + read-write + 0x00000DE9 + + + IM64 + IM64 + 0 + 1 + + + IM65 + IM65 + 1 + 1 + + + IM66 + IM66 + 2 + 1 + + + IM67 + IM67 + 3 + 1 + + + IM68 + IM68 + 4 + 1 + + + IM69 + IM69 + 5 + 1 + + + IM70 + IM70 + 6 + 1 + + + IM71 + IM71 + 7 + 1 + + + IM72 + IM72 + 8 + 1 + + + IM73 + IM73 + 9 + 1 + + + IM74 + IM74 + 10 + 1 + + + IM75 + IM75 + 11 + 1 + + + + + EXTI_EMR3 + EXTI_EMR3 + EXTI CPU wakeup with event mask register + 0xA4 + 0x20 + read-write + 0x00000000 + + + EM66 + EM66 + 2 + 1 + + + + + EXTI_C2IMR1 + EXTI_C2IMR1 + Contains register bits for configurable events and Direct events. + 0xC0 + 0x20 + read-write + 0xFFFE0000 + + + IM0 + IM0 + 0 + 1 + + + IM1 + IM1 + 1 + 1 + + + IM2 + IM2 + 2 + 1 + + + IM3 + IM3 + 3 + 1 + + + IM4 + IM4 + 4 + 1 + + + IM5 + IM5 + 5 + 1 + + + IM6 + IM6 + 6 + 1 + + + IM7 + IM7 + 7 + 1 + + + IM8 + IM8 + 8 + 1 + + + IM9 + IM9 + 9 + 1 + + + IM10 + IM10 + 10 + 1 + + + IM11 + IM11 + 11 + 1 + + + IM12 + IM12 + 12 + 1 + + + IM13 + IM13 + 13 + 1 + + + IM14 + IM14 + 14 + 1 + + + IM15 + IM15 + 15 + 1 + + + IM16 + IM16 + 16 + 1 + + + IM17 + IM17 + 17 + 1 + + + IM18 + IM18 + 18 + 1 + + + IM19 + IM19 + 19 + 1 + + + IM20 + IM20 + 20 + 1 + + + IM21 + IM21 + 21 + 1 + + + IM22 + IM22 + 22 + 1 + + + IM23 + IM23 + 23 + 1 + + + IM24 + IM24 + 24 + 1 + + + IM25 + IM25 + 25 + 1 + + + IM26 + IM26 + 26 + 1 + + + IM27 + IM27 + 27 + 1 + + + IM28 + IM28 + 28 + 1 + + + IM29 + IM29 + 29 + 1 + + + IM30 + IM30 + 30 + 1 + + + IM31 + IM31 + 31 + 1 + + + + + EXTI_C2EMR1 + EXTI_C2EMR1 + EXTI CPU2 wakeup with event mask register + 0xC4 + 0x20 + read-write + 0x00000000 + + + EM0 + EM0 + 0 + 1 + + + EM1 + EM1 + 1 + 1 + + + EM2 + EM2 + 2 + 1 + + + EM3 + EM3 + 3 + 1 + + + EM4 + EM4 + 4 + 1 + + + EM5 + EM5 + 5 + 1 + + + EM6 + EM6 + 6 + 1 + + + EM7 + EM7 + 7 + 1 + + + EM8 + EM8 + 8 + 1 + + + EM9 + EM9 + 9 + 1 + + + EM10 + EM10 + 10 + 1 + + + EM11 + EM11 + 11 + 1 + + + EM12 + EM12 + 12 + 1 + + + EM13 + EM13 + 13 + 1 + + + EM14 + EM14 + 14 + 1 + + + EM15 + EM15 + 15 + 1 + + + EM17 + EM17 + 17 + 1 + + + EM18 + EM18 + 18 + 1 + + + EM19 + EM19 + 19 + 1 + + + + + EXTI_C2IMR2 + EXTI_C2IMR2 + Contains register bits for configurable events and direct events. + 0xD0 + 0x20 + read-write + 0xFFFFFFFF + + + IM32 + IM32 + 0 + 1 + + + IM33 + IM33 + 1 + 1 + + + IM34 + IM34 + 2 + 1 + + + IM35 + IM35 + 3 + 1 + + + IM36 + IM36 + 4 + 1 + + + IM37 + IM37 + 5 + 1 + + + IM38 + IM38 + 6 + 1 + + + IM39 + IM39 + 7 + 1 + + + IM40 + IM40 + 8 + 1 + + + IM41 + IM41 + 9 + 1 + + + IM42 + IM42 + 10 + 1 + + + IM43 + IM43 + 11 + 1 + + + IM44 + IM44 + 12 + 1 + + + IM45 + IM45 + 13 + 1 + + + IM46 + IM46 + 14 + 1 + + + IM47 + IM47 + 15 + 1 + + + IM48 + IM48 + 16 + 1 + + + IM49 + IM49 + 17 + 1 + + + IM50 + IM50 + 18 + 1 + + + IM51 + IM51 + 19 + 1 + + + IM52 + IM52 + 20 + 1 + + + IM53 + IM53 + 21 + 1 + + + IM54 + IM54 + 22 + 1 + + + IM55 + IM55 + 23 + 1 + + + IM56 + IM56 + 24 + 1 + + + IM57 + IM57 + 25 + 1 + + + IM58 + IM58 + 26 + 1 + + + IM59 + IM59 + 27 + 1 + + + IM60 + IM60 + 28 + 1 + + + IM61 + IM61 + 29 + 1 + + + IM62 + IM62 + 30 + 1 + + + IM63 + IM63 + 31 + 1 + + + + + EXTI_C2EMR2 + EXTI_C2EMR2 + EXTI CPU2 wakeup with event mask register + 0xD4 + 0x20 + read-write + 0x00000000 + + + EXTI_C2IMR3 + EXTI_C2IMR3 + Contains register bits for configurable events and direct events. + 0xE0 + 0x20 + read-write + 0x00000DE9 + + + IM64 + IM64 + 0 + 1 + + + IM65 + IM65 + 1 + 1 + + + IM66 + IM66 + 2 + 1 + + + IM67 + IM67 + 3 + 1 + + + IM68 + IM68 + 4 + 1 + + + IM69 + IM69 + 5 + 1 + + + IM70 + IM70 + 6 + 1 + + + IM71 + IM71 + 7 + 1 + + + IM72 + IM72 + 8 + 1 + + + IM73 + IM73 + 9 + 1 + + + IM74 + IM74 + 10 + 1 + + + IM75 + IM75 + 11 + 1 + + + + + EXTI_C2EMR3 + EXTI_C2EMR3 + EXTI CPU2 wakeup with event mask register + 0xE4 + 0x20 + read-write + 0x00000000 + + + EM66 + EM66 + 2 + 1 + + + + + EXTI_HWCFGR13 + EXTI_HWCFGR13 + EXTI hardware configuration register 13 + 0x3C0 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR12 + EXTI_HWCFGR12 + EXTI hardware configuration register 12 + 0x3C4 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR11 + EXTI_HWCFGR11 + EXTI hardware configuration register 11 + 0x3C8 + 0x20 + read-only + 0x050EFFFF + + + TZ + TZ + 0 + 32 + + + + + EXTI_HWCFGR10 + EXTI_HWCFGR10 + EXTI hardware configuration register 10 + 0x3CC + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR9 + EXTI_HWCFGR9 + EXTI hardware configuration register 9 + 0x3D0 + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR8 + EXTI_HWCFGR8 + EXTI hardware configuration register 8 + 0x3D4 + 0x20 + read-only + 0x00000000 + + + EXTI_HWCFGR7 + EXTI_HWCFGR7 + EXTI hardware configuration register 7 + 0x3D8 + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR6 + EXTI_HWCFGR6 + EXTI hardware configuration register 6 + 0x3DC + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR5 + EXTI_HWCFGR5 + EXTI hardware configuration register 5 + 0x3E0 + 0x20 + read-only + 0x000EFFFF + + + CPUEVENT + CPUEVENT + 0 + 32 + + + + + EXTI_HWCFGR4 + EXTI_HWCFGR4 + EXTI hardware configuration register 4 + 0x3E4 + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR3 + EXTI_HWCFGR3 + EXTI hardware configuration register 3 + 0x3E8 + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR2 + EXTI_HWCFGR2 + EXTI hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x0001FFFF + + + EVENT_TRG + EVENT_TRG + 0 + 32 + + + + + EXTI_HWCFGR1 + EXTI_HWCFGR1 + EXTI hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x000B214B + + + NBEVENTS + NBEVENTS + 0 + 8 + + + NBCPUS + NBCPUS + 8 + 4 + + + CPUEVTEN + CPUEVTEN + 12 + 4 + + + NBIOPORT + NBIOPORT + 16 + 8 + + + + + EXTI_VERR + EXTI_VERR + EXTI IP version register + 0x3F4 + 0x20 + read-only + 0x00000030 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + EXTI_IPIDR + EXTI_IPIDR + EXTI identification register + 0x3F8 + 0x20 + read-only + 0x000E0001 + + + IPID + IPID + 0 + 32 + + + + + EXTI_SIDR + EXTI_SIDR + EXTI size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + FDCAN1 + FDCAN1 + FDCAN1 + 0x4400E000 + + 0x0 + 0x400 + registers + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0 + 0x20 + read-only + 0x32141218 + + + DAY + DAY + 0 + 8 + + + MON + MON + 8 + 8 + + + YEAR + YEAR + 16 + 4 + + + SUBSTEP + SUBSTEP + 20 + 4 + + + STEP + STEP + 24 + 4 + + + REL + REL + 28 + 4 + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN Endian register + 0x4 + 0x20 + read-only + 0x87654321 + + + ETV + ETV + 0 + 32 + + + + + FDCAN_DBTP + FDCAN_DBTP + This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. + 0xC + 0x20 + read-write + 0x00000A33 + + + DSJW + DSJW + 0 + 4 + + + DTSEG2 + DTSEG2 + 4 + 4 + + + DTSEG1 + DTSEG1 + 8 + 5 + + + DBRP + DBRP + 16 + 5 + + + TDC + TDC + 23 + 1 + + + + + FDCAN_TEST + FDCAN_TEST + Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. + 0x10 + 0x20 + 0x00000000 + + + LBCK + LBCK + 4 + 1 + read-write + + + TX + TX + 5 + 2 + read-write + + + RX + RX + 7 + 1 + read-only + + + + + FDCAN_RWD + FDCAN_RWD + The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. + 0x14 + 0x20 + 0x00000000 + + + WDC + WDC + 0 + 8 + read-write + + + WDV + WDV + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + For details about setting and resetting of single bits see Software initialization. + 0x18 + 0x20 + 0x00000001 + + + INIT + INIT + 0 + 1 + read-write + + + CCE + CCE + 1 + 1 + read-write + + + ASM + ASM + 2 + 1 + read-write + + + CSA + CSA + 3 + 1 + read-only + + + CSR + CSR + 4 + 1 + read-write + + + MON + MON + 5 + 1 + read-write + + + DAR + DAR + 6 + 1 + read-write + + + TEST + TEST + 7 + 1 + read-write + + + FDOE + FDOE + 8 + 1 + read-write + + + BRSE + BRSE + 9 + 1 + read-write + + + PXHD + PXHD + 12 + 1 + read-write + + + EFBI + EFBI + 13 + 1 + read-write + + + TXP + TXP + 14 + 1 + read-write + + + NISO + NISO + 15 + 1 + read-write + + + + + FDCAN_NBTP + FDCAN_NBTP + This register is dedicated to the nominal bit timing used during the arbitration phase. + 0x1C + 0x20 + read-write + 0x00000A33 + + + NTSEG2 + NTSEG2 + 0 + 7 + + + NTSEG1 + NTSEG1 + 8 + 8 + + + NBRP + NBRP + 16 + 9 + + + NSJW + NSJW + 25 + 7 + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x20 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 2 + + + TCP + TCP + 16 + 4 + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x24 + 0x20 + read-write + 0x00000000 + + + TSC + TSC + 0 + 16 + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x28 + 0x20 + read-write + 0xFFFF0000 + + + ETOC + ETOC + 0 + 1 + + + TOS + TOS + 1 + 2 + + + TOP + TOP + 16 + 16 + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + TOC + TOC + 0 + 16 + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x40 + 0x20 + 0x00000000 + + + TEC + TEC + 0 + 8 + read-only + + + TREC + TREC + 8 + 7 + read-only + + + RP + RP + 15 + 1 + read-only + + + CEL + CEL + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x44 + 0x20 + 0x00000707 + + + LEC + LEC + 0 + 3 + read-only + + + ACT + ACT + 3 + 2 + read-only + + + EP + EP + 5 + 1 + read-only + + + EW + EW + 6 + 1 + read-only + + + BO + BO + 7 + 1 + read-only + + + DLEC + DLEC + 8 + 3 + read-only + + + RESI + RESI + 11 + 1 + read-write + + + RBRS + RBRS + 12 + 1 + read-write + + + REDL + REDL + 13 + 1 + read-write + + + PXE + PXE + 14 + 1 + read-write + + + TDCV + TDCV + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x48 + 0x20 + read-write + 0x00000000 + + + TDCF + TDCF + 0 + 7 + + + TDCO + TDCO + 8 + 7 + + + + + FDCAN_IR + FDCAN_IR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. + 0x50 + 0x20 + read-write + 0x00000000 + + + RF0N + RF0N + 0 + 1 + + + RF0W + RF0W + 1 + 1 + + + RF0F + RF0F + 2 + 1 + + + RF0L + RF0L + 3 + 1 + + + RF1N + RF1N + 4 + 1 + + + RF1W + RF1W + 5 + 1 + + + RF1F + RF1F + 6 + 1 + + + RF1L + RF1L + 7 + 1 + + + HPM + HPM + 8 + 1 + + + TC + TC + 9 + 1 + + + TCF + TCF + 10 + 1 + + + TFE + TFE + 11 + 1 + + + TEFN + TEFN + 12 + 1 + + + TEFW + TEFW + 13 + 1 + + + TEFF + TEFF + 14 + 1 + + + TEFL + TEFL + 15 + 1 + + + TSW + TSW + 16 + 1 + + + MRAF + MRAF + 17 + 1 + + + TOO + TOO + 18 + 1 + + + DRX + DRX + 19 + 1 + + + ELO + ELO + 22 + 1 + + + EP + EP + 23 + 1 + + + EW + EW + 24 + 1 + + + BO + BO + 25 + 1 + + + WDI + WDI + 26 + 1 + + + PEA + PEA + 27 + 1 + + + PED + PED + 28 + 1 + + + ARA + ARA + 29 + 1 + + + + + FDCAN_IE + FDCAN_IE + The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. + 0x54 + 0x20 + read-write + 0x00000000 + + + RF0NE + RF0NE + 0 + 1 + + + RF0WE + RF0WE + 1 + 1 + + + RF0FE + RF0FE + 2 + 1 + + + RF0LE + RF0LE + 3 + 1 + + + RF1NE + RF1NE + 4 + 1 + + + RF1WE + RF1WE + 5 + 1 + + + RF1FE + RF1FE + 6 + 1 + + + RF1LE + RF1LE + 7 + 1 + + + HPME + HPME + 8 + 1 + + + TCE + TCE + 9 + 1 + + + TCFE + TCFE + 10 + 1 + + + TFEE + TFEE + 11 + 1 + + + TEFNE + TEFNE + 12 + 1 + + + TEFWE + TEFWE + 13 + 1 + + + TEFFE + TEFFE + 14 + 1 + + + TEFLE + TEFLE + 15 + 1 + + + TSWE + TSWE + 16 + 1 + + + MRAFE + MRAFE + 17 + 1 + + + TOOE + TOOE + 18 + 1 + + + DRXE + DRXE + 19 + 1 + + + BECE + BECE + 20 + 1 + + + BEUE + BEUE + 21 + 1 + + + ELOE + ELOE + 22 + 1 + + + EPE + EPE + 23 + 1 + + + EWE + EWE + 24 + 1 + + + BOE + BOE + 25 + 1 + + + WDIE + WDIE + 26 + 1 + + + PEAE + PEAE + 27 + 1 + + + PEDE + PEDE + 28 + 1 + + + ARAE + ARAE + 29 + 1 + + + + + FDCAN_ILS + FDCAN_ILS + This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. + 0x58 + 0x20 + read-write + 0x00000000 + + + RF0NL + RF0NL + 0 + 1 + + + RF0WL + RF0WL + 1 + 1 + + + RF0FL + RF0FL + 2 + 1 + + + RF0LL + RF0LL + 3 + 1 + + + RF1NL + RF1NL + 4 + 1 + + + RF1WL + RF1WL + 5 + 1 + + + RF1FL + RF1FL + 6 + 1 + + + RF1LL + RF1LL + 7 + 1 + + + HPML + HPML + 8 + 1 + + + TCL + TCL + 9 + 1 + + + TCFL + TCFL + 10 + 1 + + + TFEL + TFEL + 11 + 1 + + + TEFNL + TEFNL + 12 + 1 + + + TEFWL + TEFWL + 13 + 1 + + + TEFFL + TEFFL + 14 + 1 + + + TEFLL + TEFLL + 15 + 1 + + + TSWL + TSWL + 16 + 1 + + + MRAFL + MRAFL + 17 + 1 + + + TOOL + TOOL + 18 + 1 + + + DRXL + DRXL + 19 + 1 + + + BECL + BECL + 20 + 1 + + + BEUL + BEUL + 21 + 1 + + + ELOL + ELOL + 22 + 1 + + + EPL + EPL + 23 + 1 + + + EWL + EWL + 24 + 1 + + + BOL + BOL + 25 + 1 + + + WDIL + WDIL + 26 + 1 + + + PEAL + PEAL + 27 + 1 + + + PEDL + PEDL + 28 + 1 + + + ARAL + ARAL + 29 + 1 + + + + + FDCAN_ILE + FDCAN_ILE + Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. + 0x5C + 0x20 + read-write + 0x00000000 + + + EINT0 + EINT0 + 0 + 1 + + + EINT1 + EINT1 + 1 + 1 + + + + + FDCAN_GFC + FDCAN_GFC + Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. + 0x80 + 0x20 + read-write + 0x00000000 + + + RRFE + RRFE + 0 + 1 + + + RRFS + RRFS + 1 + 1 + + + ANFE + ANFE + 2 + 2 + + + ANFS + ANFS + 4 + 2 + + + + + FDCAN_SIDFC + FDCAN_SIDFC + Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. + 0x84 + 0x20 + read-write + 0x00000000 + + + FLSSA + FLSSA + 2 + 14 + + + LSS + LSS + 16 + 8 + + + + + FDCAN_XIDFC + FDCAN_XIDFC + Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. + 0x88 + 0x20 + read-write + 0x00000000 + + + FLESA + FLESA + 2 + 14 + + + LSE + LSE + 16 + 8 + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x90 + 0x20 + read-write + 0x1FFFFFFF + + + EIDM + EIDM + 0 + 29 + + + + + FDCAN_HPMS + FDCAN_HPMS + This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. + 0x94 + 0x20 + read-only + 0x00000000 + + + BIDX + BIDX + 0 + 6 + + + MSI + MSI + 6 + 2 + + + FIDX + FIDX + 8 + 7 + + + FLST + FLST + 15 + 1 + + + + + FDCAN_NDAT1 + FDCAN_NDAT1 + FDCAN new data 1 register + 0x98 + 0x20 + read-write + 0x00000000 + + + ND0 + ND0 + 0 + 1 + + + ND1 + ND1 + 1 + 1 + + + ND2 + ND2 + 2 + 1 + + + ND3 + ND3 + 3 + 1 + + + ND4 + ND4 + 4 + 1 + + + ND5 + ND5 + 5 + 1 + + + ND6 + ND6 + 6 + 1 + + + ND7 + ND7 + 7 + 1 + + + ND8 + ND8 + 8 + 1 + + + ND9 + ND9 + 9 + 1 + + + ND10 + ND10 + 10 + 1 + + + ND11 + ND11 + 11 + 1 + + + ND12 + ND12 + 12 + 1 + + + ND13 + ND13 + 13 + 1 + + + ND14 + ND14 + 14 + 1 + + + ND15 + ND15 + 15 + 1 + + + ND16 + ND16 + 16 + 1 + + + ND17 + ND17 + 17 + 1 + + + ND18 + ND18 + 18 + 1 + + + ND19 + ND19 + 19 + 1 + + + ND20 + ND20 + 20 + 1 + + + ND21 + ND21 + 21 + 1 + + + ND22 + ND22 + 22 + 1 + + + ND23 + ND23 + 23 + 1 + + + ND24 + ND24 + 24 + 1 + + + ND25 + ND25 + 25 + 1 + + + ND26 + ND26 + 26 + 1 + + + ND27 + ND27 + 27 + 1 + + + ND28 + ND28 + 28 + 1 + + + ND29 + ND29 + 29 + 1 + + + ND30 + ND30 + 30 + 1 + + + ND31 + ND31 + 31 + 1 + + + + + FDCAN_NDAT2 + FDCAN_NDAT2 + FDCAN new data 2 register + 0x9C + 0x20 + read-write + 0x00000000 + + + ND32 + ND32 + 0 + 1 + + + ND33 + ND33 + 1 + 1 + + + ND34 + ND34 + 2 + 1 + + + ND35 + ND35 + 3 + 1 + + + ND36 + ND36 + 4 + 1 + + + ND37 + ND37 + 5 + 1 + + + ND38 + ND38 + 6 + 1 + + + ND39 + ND39 + 7 + 1 + + + ND40 + ND40 + 8 + 1 + + + ND41 + ND41 + 9 + 1 + + + ND42 + ND42 + 10 + 1 + + + ND43 + ND43 + 11 + 1 + + + ND44 + ND44 + 12 + 1 + + + ND45 + ND45 + 13 + 1 + + + ND46 + ND46 + 14 + 1 + + + ND47 + ND47 + 15 + 1 + + + ND48 + ND48 + 16 + 1 + + + ND49 + ND49 + 17 + 1 + + + ND50 + ND50 + 18 + 1 + + + ND51 + ND51 + 19 + 1 + + + ND52 + ND52 + 20 + 1 + + + ND53 + ND53 + 21 + 1 + + + ND54 + ND54 + 22 + 1 + + + ND55 + ND55 + 23 + 1 + + + ND56 + ND56 + 24 + 1 + + + ND57 + ND57 + 25 + 1 + + + ND58 + ND58 + 26 + 1 + + + ND59 + ND59 + 27 + 1 + + + ND60 + ND60 + 28 + 1 + + + ND61 + ND61 + 29 + 1 + + + ND62 + ND62 + 30 + 1 + + + ND63 + ND63 + 31 + 1 + + + + + FDCAN_RXF0C + FDCAN_RXF0C + FDCAN Rx FIFO 0 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + F0SA + F0SA + 2 + 14 + + + F0S + F0S + 16 + 7 + + + F0WM + F0WM + 24 + 7 + + + F0OM + F0OM + 31 + 1 + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0xA4 + 0x20 + read-write + 0x00000000 + + + F0FL + F0FL + 0 + 7 + + + F0GI + F0GI + 8 + 6 + + + F0PI + F0PI + 16 + 6 + + + F0F + F0F + 24 + 1 + + + RF0L + RF0L + 25 + 1 + + + + + FDCAN_RXF0A + FDCAN_RXF0A + FDCAN Rx FIFO 0 acknowledge register + 0xA8 + 0x20 + read-write + 0x00000000 + + + F0AI + F0AI + 0 + 6 + + + + + FDCAN_RXBC + FDCAN_RXBC + FDCAN Rx buffer configuration register + 0xAC + 0x20 + read-write + 0x00000000 + + + RBSA + RBSA + 2 + 14 + + + + + FDCAN_RXF1C + FDCAN_RXF1C + FDCAN Rx FIFO 1 configuration register + 0xB0 + 0x20 + read-write + 0x00000000 + + + F1SA + F1SA + 2 + 14 + + + F1S + F1S + 16 + 7 + + + F1WM + F1WM + 24 + 7 + + + F1OM + F1OM + 31 + 1 + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0xB4 + 0x20 + read-only + 0x00000000 + + + F1FL + F1FL + 0 + 7 + + + F1GI + F1GI + 8 + 6 + + + F1PI + F1PI + 16 + 6 + + + F1F + F1F + 24 + 1 + + + RF1L + RF1L + 25 + 1 + + + DMS + DMS + 30 + 2 + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0xB8 + 0x20 + read-write + 0x00000000 + + + F1AI + F1AI + 0 + 6 + + + + + FDCAN_RXESC + FDCAN_RXESC + Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. + 0xBC + 0x20 + read-only + 0x00000000 + + + F0DS + F0DS + 0 + 3 + + + F1DS + F1DS + 4 + 3 + + + RBDS + RBDS + 8 + 3 + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0xC0 + 0x20 + read-write + 0x00000000 + + + TBSA + TBSA + 2 + 14 + + + NDTB + NDTB + 16 + 6 + + + TFQS + TFQS + 24 + 6 + + + TFQM + TFQM + 30 + 1 + + + + + FDCAN_TXFQS + FDCAN_TXFQS + The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). + 0xC4 + 0x20 + read-only + 0x00000000 + + + TFFL + TFFL + 0 + 6 + + + TFGI + TFGI + 8 + 5 + + + TFQPI + TFQPI + 16 + 5 + + + TFQF + TFQF + 21 + 1 + + + + + FDCAN_TXESC + FDCAN_TXESC + Configures the number of data bytes belonging to a Tx buffer element. Data field sizes &gt;8 bytes are intended for CAN FD operation only. + 0xC8 + 0x20 + read-only + 0x00000000 + + + TBDS + TBDS + 0 + 3 + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0xD0 + 0x20 + read-write + 0x00000000 + + + AR + AR + 0 + 32 + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0xD4 + 0x20 + read-write + 0x00000000 + + + CR + CR + 0 + 32 + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0xD8 + 0x20 + read-only + 0x00000000 + + + TO + TO + 0 + 32 + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0xDC + 0x20 + read-only + 0x00000000 + + + CF + CF + 0 + 32 + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0xE0 + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 32 + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0xE4 + 0x20 + read-write + 0x00000000 + + + CFIE + CFIE + 0 + 32 + + + + + FDCAN_TXEFC + FDCAN_TXEFC + FDCAN Tx event FIFO configuration register + 0xF0 + 0x20 + read-write + 0x00000000 + + + EFSA + EFSA + 2 + 14 + + + EFS + EFS + 16 + 6 + + + EFWM + EFWM + 24 + 6 + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0xF4 + 0x20 + read-only + 0x00000000 + + + EFFL + EFFL + 0 + 6 + + + EFGI + EFGI + 8 + 5 + + + EFPI + EFPI + 16 + 5 + + + EFF + EFF + 24 + 1 + + + TEFL + TEFL + 25 + 1 + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0xF8 + 0x20 + read-write + 0x00000000 + + + EFAI + EFAI + 0 + 5 + + + + + FDCAN_TTTMC + FDCAN_TTTMC + FDCAN TT trigger memory configuration register + 0x100 + 0x20 + read-write + 0x00000000 + + + TMSA + TMSA + 2 + 14 + + + TME + TME + 16 + 7 + + + + + FDCAN_TTRMC + FDCAN_TTRMC + FDCAN TT reference message configuration register + 0x104 + 0x20 + read-write + 0x00000000 + + + RID + RID + 0 + 29 + + + XTD + XTD + 30 + 1 + + + RMPS + RMPS + 31 + 1 + + + + + FDCAN_TTOCF + FDCAN_TTOCF + FDCAN TT operation configuration register + 0x108 + 0x20 + read-write + 0x00010000 + + + OM + OM + 0 + 2 + + + GEN + GEN + 3 + 1 + + + TM + TM + 4 + 1 + + + LDSDL + LDSDL + 5 + 3 + + + IRTO + IRTO + 8 + 7 + + + EECS + EECS + 15 + 1 + + + AWL + AWL + 16 + 8 + + + EGTF + EGTF + 24 + 1 + + + ECC + ECC + 25 + 1 + + + EVTP + EVTP + 26 + 1 + + + + + FDCAN_TTMLM + FDCAN_TTMLM + FDCAN TT matrix limits register + 0x10C + 0x20 + read-write + 0x00000000 + + + CCM + CCM + 0 + 6 + + + CSS + CSS + 6 + 2 + + + TXEW + TXEW + 8 + 4 + + + ENTT + ENTT + 16 + 12 + + + + + FDCAN_TURCF + FDCAN_TURCF + The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. + 0x110 + 0x20 + read-write + 0x00000000 + + + NCL + NCL + 0 + 16 + + + DC + DC + 16 + 14 + + + ELT + ELT + 31 + 1 + + + + + FDCAN_TTOCN + FDCAN_TTOCN + FDCAN TT operation control register + 0x114 + 0x20 + 0x00000000 + + + SGT + SGT + 0 + 1 + read-write + + + ECS + ECS + 1 + 1 + read-write + + + SWP + SWP + 2 + 1 + read-write + + + SWS + SWS + 3 + 2 + read-write + + + RTIE + RTIE + 5 + 1 + read-write + + + TMC + TMC + 6 + 2 + read-write + + + TTIE + TTIE + 8 + 1 + read-write + + + GCS + GCS + 9 + 1 + read-write + + + FGP + FGP + 10 + 1 + read-write + + + TMG + TMG + 11 + 1 + read-write + + + NIG + NIG + 12 + 1 + read-write + + + ESCN + ESCN + 13 + 1 + read-write + + + LCKC + LCKC + 15 + 1 + read-only + + + + + FDCAN_TTGTP + FDCAN_TTGTP + If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. + 0x118 + 0x20 + read-write + 0x00000000 + + + TP + TP + 0 + 16 + + + CTP + CTP + 16 + 16 + + + + + FDCAN_TTTMK + FDCAN_TTTMK + A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. + 0x11C + 0x20 + 0x00000000 + + + TM + TM + 0 + 16 + read-write + + + TICC + TICC + 16 + 7 + read-write + + + LCKM + LCKM + 31 + 1 + read-only + + + + + FDCAN_TTIR + FDCAN_TTIR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. + 0x120 + 0x20 + read-write + 0x00000000 + + + SBC + SBC + 0 + 1 + + + SMC + SMC + 1 + 1 + + + CSM + CSM + 2 + 1 + + + SOG + SOG + 3 + 1 + + + RTMI + RTMI + 4 + 1 + + + TTMI + TTMI + 5 + 1 + + + SWE + SWE + 6 + 1 + + + GTW + GTW + 7 + 1 + + + GTD + GTD + 8 + 1 + + + GTE + GTE + 9 + 1 + + + TXU + TXU + 10 + 1 + + + TXO + TXO + 11 + 1 + + + SE1 + SE1 + 12 + 1 + + + SE2 + SE2 + 13 + 1 + + + ELC + ELC + 14 + 1 + + + IWTG + IWTG + 15 + 1 + + + WT + WT + 16 + 1 + + + AW + AW + 17 + 1 + + + CER + CER + 18 + 1 + + + + + FDCAN_TTIE + FDCAN_TTIE + The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. + 0x124 + 0x20 + read-write + 0x00000000 + + + SBCE + SBCE + 0 + 1 + + + SMCE + SMCE + 1 + 1 + + + CSME + CSME + 2 + 1 + + + SOGE + SOGE + 3 + 1 + + + RTMIE + RTMIE + 4 + 1 + + + TTMIE + TTMIE + 5 + 1 + + + SWEE + SWEE + 6 + 1 + + + GTWE + GTWE + 7 + 1 + + + GTDE + GTDE + 8 + 1 + + + GTEE + GTEE + 9 + 1 + + + TXUE + TXUE + 10 + 1 + + + TXOE + TXOE + 11 + 1 + + + SE1E + SE1E + 12 + 1 + + + SE2E + SE2E + 13 + 1 + + + ELCE + ELCE + 14 + 1 + + + IWTE + IWTE + 15 + 1 + + + WTE + WTE + 16 + 1 + + + AWE + AWE + 17 + 1 + + + CERE + CERE + 18 + 1 + + + + + FDCAN_TTILS + FDCAN_TTILS + The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. + 0x128 + 0x20 + read-write + 0x00000000 + + + SBCL + SBCL + 0 + 1 + + + SMCL + SMCL + 1 + 1 + + + CSML + CSML + 2 + 1 + + + SOGL + SOGL + 3 + 1 + + + RTMIL + RTMIL + 4 + 1 + + + TTMIL + TTMIL + 5 + 1 + + + SWEL + SWEL + 6 + 1 + + + GTWL + GTWL + 7 + 1 + + + GTDL + GTDL + 8 + 1 + + + GTEL + GTEL + 9 + 1 + + + TXUL + TXUL + 10 + 1 + + + TXOL + TXOL + 11 + 1 + + + SE1L + SE1L + 12 + 1 + + + SE2L + SE2L + 13 + 1 + + + ELCL + ELCL + 14 + 1 + + + IWTL + IWTL + 15 + 1 + + + WTL + WTL + 16 + 1 + + + AWL + AWL + 17 + 1 + + + CERL + CERL + 18 + 1 + + + + + FDCAN_TTOST + FDCAN_TTOST + FDCAN TT operation status register + 0x12C + 0x20 + read-only + 0x00000080 + + + EL + EL + 0 + 2 + + + MS + MS + 2 + 2 + + + SYS + SYS + 4 + 2 + + + QGTP + QGTP + 6 + 1 + + + QCS + QCS + 7 + 1 + + + RTO + RTO + 8 + 8 + + + WGTD + WGTD + 22 + 1 + + + GFI + GFI + 23 + 1 + + + TMP + TMP + 24 + 3 + + + GSI + GSI + 27 + 1 + + + WFE + WFE + 28 + 1 + + + AWE + AWE + 29 + 1 + + + WECS + WECS + 30 + 1 + + + SPL + SPL + 31 + 1 + + + + + FDCAN_TURNA + FDCAN_TURNA + There is no drift compensation in TTCAN level 1. + 0x130 + 0x20 + read-only + 0x00000000 + + + NAV + NAV + 0 + 18 + + + + + FDCAN_TTLGT + FDCAN_TTLGT + FDCAN TT local and global time register + 0x134 + 0x20 + read-only + 0x00000000 + + + LT + LT + 0 + 16 + + + GT + GT + 16 + 16 + + + + + FDCAN_TTCTC + FDCAN_TTCTC + FDCAN TT cycle time and count register + 0x138 + 0x20 + read-only + 0x003F0000 + + + CT + CT + 0 + 16 + + + CC + CC + 16 + 6 + + + + + FDCAN_TTCPT + FDCAN_TTCPT + FDCAN TT capture time register + 0x13C + 0x20 + read-only + 0x00000000 + + + CCV + CCV + 0 + 6 + + + SWV + SWV + 16 + 16 + + + + + FDCAN_TTCSM + FDCAN_TTCSM + FDCAN TT cycle sync mark register + 0x140 + 0x20 + read-only + 0x00000000 + + + CSM + CSM + 0 + 16 + + + + + FDCAN_TTTS + FDCAN_TTTS + The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. + 0x300 + 0x20 + read-write + 0x00000000 + + + SWTDEL + SWTDEL + 0 + 2 + + + EVTSEL + EVTSEL + 4 + 2 + + + + + + + FDCAN2 + 0x4400F000 + + + CCU + CCU + CCU + 0x44010000 + + 0x0 + 0x400 + registers + + + + FCCAN_CCU_CREL + FCCAN_CCU_CREL + Clock calibration unit core release register + 0x0 + 0x20 + read-only + 0x11141218 + + + DAY + DAY + 0 + 8 + + + MON + MON + 8 + 8 + + + YEAR + YEAR + 16 + 4 + + + SUBSTEP + SUBSTEP + 20 + 4 + + + STEP + STEP + 24 + 4 + + + REL + REL + 28 + 4 + + + + + FCCAN_CCU_CCFG + FCCAN_CCU_CCFG + Calibration configuration register + 0x4 + 0x20 + read-write + 0x00000004 + + + TQBT + TQBT + 0 + 5 + + + BCC + BCC + 6 + 1 + + + CFL + CFL + 7 + 1 + + + OCPM + OCPM + 8 + 8 + + + CDIV + CDIV + 16 + 4 + + + SWR + SWR + 31 + 1 + + + + + FCCAN_CCU_CSTAT + FCCAN_CCU_CSTAT + Calibration status register + 0x8 + 0x20 + read-only + 0x0203FFFF + + + OCPC + OCPC + 0 + 18 + + + TQC + TQC + 18 + 11 + + + CALS + CALS + 30 + 2 + + + + + FCCAN_CCU_CWD + FCCAN_CCU_CWD + The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset. + 0xC + 0x20 + 0x00000000 + + + WDC + WDC + 0 + 16 + read-write + + + WDV + WDV + 16 + 16 + read-only + + + + + FCCAN_CCU_IR + FCCAN_CCU_IR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not. + 0x10 + 0x20 + read-write + 0x00000000 + + + CWE + CWE + 0 + 1 + + + CSC + CSC + 1 + 1 + + + + + FCCAN_CCU_IE + FCCAN_CCU_IE + The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line. + 0x14 + 0x20 + read-write + 0x00000000 + + + CWEE + CWEE + 0 + 1 + + + CSCE + CSCE + 1 + 1 + + + + + + + FMC + FMC register block + FMC + 0x58002000 + + 0x0 + 0x1000 + registers + + + + FMC_BCR1 + FMC_BCR1 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR1 + FMC_BTR1 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR2 + FMC_BCR2 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR2 + FMC_BTR2 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR3 + FMC_BCR3 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR3 + FMC_BTR3 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BCR4 + FMC_BCR4 + This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030DB + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + FMCEN + FMCEN + 31 + 1 + + + + + FMC_BTR4 + FMC_BTR4 + This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATLAT + DATLAT + 24 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_PCSCNTR + FMC_PCSCNTR + This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h + 0x20 + 0x20 + read-write + 0x00000000 + + + CSCOUNT + CSCOUNT + 0 + 16 + + + CNTB1EN + CNTB1EN + 16 + 1 + + + CNTB2EN + CNTB2EN + 17 + 1 + + + CNTB3EN + CNTB3EN + 18 + 1 + + + CNTB4EN + CNTB4EN + 19 + 1 + + + + + FMC_PCR + FMC_PCR + NAND Flash Programmable control register + 0x80 + 0x20 + read-write + 0x0007FE08 + + + PWAITEN + PWAITEN + 1 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWID + PWID + 4 + 2 + + + ECCEN + ECCEN + 6 + 1 + + + ECCALG + ECCALG + 8 + 1 + + + TCLR + TCLR + 9 + 4 + + + TAR + TAR + 13 + 4 + + + ECCSS + ECCSS + 17 + 3 + + + TCEH + TCEH + 20 + 4 + + + BCHECC + BCHECC + 24 + 1 + + + WEN + WEN + 25 + 1 + + + + + FMC_SR + FMC_SR + This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits. + 0x84 + 0x20 + read-only + 0x00000040 + + + ISOST + ISOST + 0 + 2 + + + PEF + PEF + 4 + 1 + + + NWRF + NWRF + 6 + 1 + + + + + FMC_PMEM + FMC_PMEM + The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses. + 0x88 + 0x20 + read-write + 0x0A0A0A0A + + + MEMSET + MEMSET + 0 + 8 + + + MEMWAIT + MEMWAIT + 8 + 8 + + + MEMHOLD + MEMHOLD + 16 + 8 + + + MEMHIZ + MEMHIZ + 24 + 8 + + + + + FMC_PATT + FMC_PATT + The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function). + 0x8C + 0x20 + read-write + 0x0A0A0A0A + + + ATTSET + ATTSET + 0 + 8 + + + ATTWAIT + ATTWAIT + 8 + 8 + + + ATTHOLD + ATTHOLD + 16 + 8 + + + ATTHIZ + ATTHIZ + 24 + 8 + + + + + FMC_HPR + FMC_HPR + This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. + 0x90 + 0x20 + read-only + 0x00000000 + + + HPR + HPR + 0 + 32 + + + + + FMC_HECCR + FMC_HECCR + This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. + 0x94 + 0x20 + read-only + 0x00000000 + + + HECC + HECC + 0 + 32 + + + + + FMC_BWTR1 + FMC_BWTR1 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x104 + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR2 + FMC_BWTR2 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x10C + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR3 + FMC_BWTR3 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x114 + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_BWTR4 + FMC_BWTR4 + This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. + 0x11C + 0x20 + read-write + 0x000FFFFF + + + ADDSET + ADDSET + 0 + 4 + + + ADDHLD + ADDHLD + 4 + 4 + + + DATAST + DATAST + 8 + 8 + + + BUSTURN + BUSTURN + 16 + 4 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATAHLD + DATAHLD + 30 + 2 + + + + + FMC_CSQCR + FMC_CSQCR + FMC NAND Command Sequencer Control Register + 0x200 + 0x20 + write-only + 0x00000000 + + + CSQSTART + CSQSTART + 0 + 1 + + + + + FMC_CSQCFGR1 + FMC_CSQCFGR1 + FMC NAND Command Sequencer Configuration Register 1 + 0x204 + 0x20 + read-write + 0x00000000 + + + CMD2EN + CMD2EN + 1 + 1 + + + DMADEN + DMADEN + 2 + 1 + + + ACYNBR + ACYNBR + 4 + 3 + + + CMD1 + CMD1 + 8 + 8 + + + CMD2 + CMD2 + 16 + 8 + + + CMD1T + CMD1T + 24 + 1 + + + CMD2T + CMD2T + 25 + 1 + + + + + FMC_CSQCFGR2 + FMC_CSQCFGR2 + This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. . + 0x208 + 0x20 + read-write + 0x00000000 + + + SQSDTEN + SQSDTEN + 0 + 1 + + + RCMD2EN + RCMD2EN + 1 + 1 + + + DMASEN + DMASEN + 2 + 1 + + + RCMD1 + RCMD1 + 8 + 8 + + + RCMD2 + RCMD2 + 16 + 8 + + + RCMD1T + RCMD1T + 24 + 1 + + + RCMD2T + RCMD2T + 25 + 1 + + + + + FMC_CSQCFGR3 + FMC_CSQCFGR3 + FMC NAND sequencer configuration register 3 + 0x20C + 0x20 + read-write + 0x00000000 + + + SNBR + SNBR + 8 + 6 + + + AC1T + AC1T + 16 + 1 + + + AC2T + AC2T + 17 + 1 + + + AC3T + AC3T + 18 + 1 + + + AC4T + AC4T + 19 + 1 + + + AC5T + AC5T + 20 + 1 + + + SDT + SDT + 21 + 1 + + + RAC1T + RAC1T + 22 + 1 + + + RAC2T + RAC2T + 23 + 1 + + + + + FMC_CSQAR1 + FMC_CSQAR1 + This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer. + 0x210 + 0x20 + read-write + 0x00000000 + + + ADDC1 + ADDC1 + 0 + 8 + + + ADDC2 + ADDC2 + 8 + 8 + + + ADDC3 + ADDC3 + 16 + 8 + + + ADDC4 + ADDC4 + 24 + 8 + + + + + FMC_CSQAR2 + FMC_CSQAR2 + This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable. + 0x214 + 0x20 + read-write + 0x00020000 + + + ADDC5 + ADDC5 + 0 + 8 + + + NANDCEN0 + NANDCEN0 + 10 + 1 + + + NANDCEN1 + NANDCEN1 + 11 + 1 + + + SAO + SAO + 16 + 16 + + + + + FMC_CSQIER + FMC_CSQIER + FMC NAND Command Sequencer Interrupt Enable Register + 0x220 + 0x20 + read-write + 0x00000000 + + + TCIE + TCIE + 0 + 1 + + + SCIE + SCIE + 1 + 1 + + + SEIE + SEIE + 2 + 1 + + + SUEIE + SUEIE + 3 + 1 + + + CMDTCIE + CMDTCIE + 4 + 1 + + + + + FMC_CSQISR + FMC_CSQISR + FMC NAND Command Sequencer Interrupt Status Register + 0x224 + 0x20 + read-write + 0x00000000 + + + TCF + TCF + 0 + 1 + + + SCF + SCF + 1 + 1 + + + SEF + SEF + 2 + 1 + + + SUEF + SUEF + 3 + 1 + + + CMDTCF + CMDTCF + 4 + 1 + + + + + FMC_CSQICR + FMC_CSQICR + FMC NAND Command Sequencer Interrupt Clear Register + 0x228 + 0x20 + write-only + 0x00000000 + + + CTCF + CTCF + 0 + 1 + + + CSCF + CSCF + 1 + 1 + + + CSEF + CSEF + 2 + 1 + + + CSUEF + CSUEF + 3 + 1 + + + CCMDTCF + CCMDTCF + 4 + 1 + + + + + FMC_CSQEMSR + FMC_CSQEMSR + This register holds a sector error mapping status when the whole transfer is complete. + 0x230 + 0x20 + read-only + 0x00000000 + + + SEM + SEM + 0 + 16 + + + + + FMC_BCHIER + FMC_BCHIER + FMC BCH Interrupt enable register + 0x250 + 0x20 + read-write + 0x00000000 + + + DUEIE + DUEIE + 0 + 1 + + + DERIE + DERIE + 1 + 1 + + + DEFIE + DEFIE + 2 + 1 + + + DSRIE + DSRIE + 3 + 1 + + + EPBRIE + EPBRIE + 4 + 1 + + + + + FMC_BCHISR + FMC_BCHISR + This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared. + 0x254 + 0x20 + read-only + 0x00000000 + + + DUEF + DUEF + 0 + 1 + + + DERF + DERF + 1 + 1 + + + DEFF + DEFF + 2 + 1 + + + DSRF + DSRF + 3 + 1 + + + EPBRF + EPBRF + 4 + 1 + + + + + FMC_BCHICR + FMC_BCHICR + FMC BCH Interrupt Clear Register + 0x258 + 0x20 + write-only + 0x00000000 + + + CDUEF + CDUEF + 0 + 1 + + + CDERF + CDERF + 1 + 1 + + + CDEFF + CDEFF + 2 + 1 + + + CDSRF + CDSRF + 3 + 1 + + + CEPBRF + CEPBRF + 4 + 1 + + + + + FMC_BCHPBR1 + FMC_BCHPBR1 + These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant. + 0x260 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR2 + FMC_BCHPBR2 + FMC BCH Parity Bits Register 2 + 0x264 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR3 + FMC_BCHPBR3 + FMC BCH Parity Bits Register 3 + 0x268 + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 32 + + + + + FMC_BCHPBR4 + FMC_BCHPBR4 + FMC BCH Parity Bits Register 4 + 0x26C + 0x20 + read-only + 0x00000000 + + + BCHPB + BCHPB + 0 + 8 + + + + + FMC_BCHDSR0 + FMC_BCHDSR0 + This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. . + 0x27C + 0x20 + read-only + 0x00000000 + + + DUE + DUE + 0 + 1 + + + DEF + DEF + 1 + 1 + + + DEN + DEN + 4 + 4 + + + + + FMC_BCHDSR1 + FMC_BCHDSR1 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors + 0x280 + 0x20 + read-only + 0x00000000 + + + EBP1 + EBP1 + 0 + 13 + + + EBP2 + EBP2 + 16 + 13 + + + + + FMC_BCHDSR2 + FMC_BCHDSR2 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively. + 0x284 + 0x20 + read-only + 0x00000000 + + + EBP3 + EBP3 + 0 + 13 + + + EBP4 + EBP4 + 16 + 13 + + + + + FMC_BCHDSR3 + FMC_BCHDSR3 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. + 0x288 + 0x20 + read-only + 0x00000000 + + + EBP5 + EBP5 + 0 + 13 + + + EBP6 + EBP6 + 16 + 13 + + + + + FMC_BCHDSR4 + FMC_BCHDSR4 + The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. . + 0x28C + 0x20 + read-only + 0x00000000 + + + EBP7 + EBP7 + 0 + 13 + + + EBP8 + EBP8 + 16 + 13 + + + + + FMC_HWCFGR2 + FMC_HWCFGR2 + FMC Hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00DC8762 + + + RD_LN2DPTH + RD_LN2DPTH + 0 + 4 + + + NOR_BASE + NOR_BASE + 4 + 4 + + + SDRAM_RBASE + SDRAM_RBASE + 8 + 4 + + + NAND_BASE + NAND_BASE + 12 + 4 + + + SDRAM1_BASE + SDRAM1_BASE + 16 + 4 + + + SDRAM2_BASE + SDRAM2_BASE + 20 + 4 + + + + + FMC_HWCFGR1 + FMC_HWCFGR1 + FMC Hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x2232B011 + + + NAND_SEL + NAND_SEL + 0 + 1 + + + NAND_ECC + NAND_ECC + 4 + 1 + + + SDRAM_SEL + SDRAM_SEL + 8 + 1 + + + ID_SIZE + ID_SIZE + 12 + 4 + + + WA_LN2DPTH + WA_LN2DPTH + 16 + 4 + + + WD_LN2DPTH + WD_LN2DPTH + 20 + 4 + + + WR_LN2DPTH + WR_LN2DPTH + 24 + 4 + + + RA_LN2DPTH + RA_LN2DPTH + 28 + 4 + + + + + FMC_VERR + FMC_VERR + FMC Version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + FMC_IPIDR + FMC_IPIDR + FMC Identification register + 0x3F8 + 0x20 + read-only + 0x00140001 + + + ID + ID + 0 + 32 + + + + + FMC_SIDR + FMC_SIDR + FMC Size Identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + GICD + GICD + GICD + 0xA0021000 + + 0x0 + 0x1000 + registers + + + + GICD_CTLR + GICD_CTLR + GICD control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLEGRP0 + ENABLEGRP0 + 0 + 1 + + + ENABLEGRP1 + ENABLEGRP1 + 1 + 1 + + + + + GICD_TYPER + GICD_TYPER + GICD interrupt controller type register + 0x4 + 0x20 + read-only + 0x0000FC28 + + + ITLINESNUMBER + ITLINESNUMBER + 0 + 5 + + + CPUNUMBER + CPUNUMBER + 5 + 3 + + + SECURITYEXTN + SECURITYEXTN + 10 + 1 + + + LSPI + LSPI + 11 + 5 + + + + + GICD_IIDR + GICD_IIDR + GICD implementer identification register + 0x8 + 0x20 + read-only + 0x0100143B + + + IMPLEMENTER + IMPLEMENTER + 0 + 12 + + + VARIANT + VARIANT + 12 + 4 + + + REVISION + REVISION + 16 + 4 + + + PRODUCTID + PRODUCTID + 24 + 8 + + + + + GICD_IGROUPR0 + GICD_IGROUPR0 + For interrupts ID + 0x80 + 0x20 + read-write + 0x00000000 + + + IGROUPR0 + IGROUPR0 + 0 + 32 + + + + + GICD_IGROUPR1 + GICD_IGROUPR1 + For interrupts ID + 0x84 + 0x20 + read-write + 0x00000000 + + + IGROUPR1 + IGROUPR1 + 0 + 32 + + + + + GICD_IGROUPR2 + GICD_IGROUPR2 + For interrupts ID + 0x88 + 0x20 + read-write + 0x00000000 + + + IGROUPR2 + IGROUPR2 + 0 + 32 + + + + + GICD_IGROUPR3 + GICD_IGROUPR3 + For interrupts ID = x*32 to ID = x*32+31 + 0x8C + 0x20 + read-write + 0x00000000 + + + IGROUPR3 + IGROUPR3 + 0 + 32 + + + + + GICD_IGROUPR4 + GICD_IGROUPR4 + For interrupts ID = x*32 to ID = x*32+31 + 0x90 + 0x20 + read-write + 0x00000000 + + + IGROUPR4 + IGROUPR4 + 0 + 32 + + + + + GICD_IGROUPR5 + GICD_IGROUPR5 + For interrupts ID + 0x94 + 0x20 + read-write + 0x00000000 + + + IGROUPR5 + IGROUPR5 + 0 + 32 + + + + + GICD_IGROUPR6 + GICD_IGROUPR6 + For interrupts ID + 0x98 + 0x20 + read-write + 0x00000000 + + + IGROUPR6 + IGROUPR6 + 0 + 32 + + + + + GICD_IGROUPR7 + GICD_IGROUPR7 + For interrupts ID + 0x9C + 0x20 + read-write + 0x00000000 + + + IGROUPR7 + IGROUPR7 + 0 + 32 + + + + + GICD_IGROUPR8 + GICD_IGROUPR8 + For interrupts ID + 0xA0 + 0x20 + read-write + 0x00000000 + + + IGROUPR8 + IGROUPR8 + 0 + 32 + + + + + GICD_ISENABLER0 + GICD_ISENABLER0 + For interrupts ID = 0 to ID = 31 + 0x100 + 0x20 + read-write + 0x0000FFFF + + + ISENABLER0 + ISENABLER0 + 0 + 32 + + + + + GICD_ISENABLER1 + GICD_ISENABLER1 + For interrupts ID + 0x104 + 0x20 + read-write + 0x00000000 + + + ISENABLER1 + ISENABLER1 + 0 + 32 + + + + + GICD_ISENABLER2 + GICD_ISENABLER2 + For interrupts ID + 0x108 + 0x20 + read-write + 0x00000000 + + + ISENABLER2 + ISENABLER2 + 0 + 32 + + + + + GICD_ISENABLER3 + GICD_ISENABLER3 + For interrupts ID + 0x10C + 0x20 + read-write + 0x00000000 + + + ISENABLER3 + ISENABLER3 + 0 + 32 + + + + + GICD_ISENABLER4 + GICD_ISENABLER4 + For interrupts ID + 0x110 + 0x20 + read-write + 0x00000000 + + + ISENABLER4 + ISENABLER4 + 0 + 32 + + + + + GICD_ISENABLER5 + GICD_ISENABLER5 + For interrupts ID + 0x114 + 0x20 + read-write + 0x00000000 + + + ISENABLER5 + ISENABLER5 + 0 + 32 + + + + + GICD_ISENABLER6 + GICD_ISENABLER6 + For interrupts ID + 0x118 + 0x20 + read-write + 0x00000000 + + + ISENABLER6 + ISENABLER6 + 0 + 32 + + + + + GICD_ISENABLER7 + GICD_ISENABLER7 + For interrupts ID + 0x11C + 0x20 + read-write + 0x00000000 + + + ISENABLER7 + ISENABLER7 + 0 + 32 + + + + + GICD_ISENABLER8 + GICD_ISENABLER8 + For interrupts ID + 0x120 + 0x20 + read-write + 0x00000000 + + + ISENABLER8 + ISENABLER8 + 0 + 32 + + + + + GICD_ICENABLER0 + GICD_ICENABLER0 + For interrupts ID = 0 to ID = 31 + 0x180 + 0x20 + read-write + 0x0000FFFF + + + ICENABLER0 + ICENABLER0 + 0 + 32 + + + + + GICD_ICENABLER1 + GICD_ICENABLER1 + For interrupts ID + 0x184 + 0x20 + read-write + 0x00000000 + + + ICENABLER1 + ICENABLER1 + 0 + 32 + + + + + GICD_ICENABLER2 + GICD_ICENABLER2 + For interrupts ID + 0x188 + 0x20 + read-write + 0x00000000 + + + ICENABLER2 + ICENABLER2 + 0 + 32 + + + + + GICD_ICENABLER3 + GICD_ICENABLER3 + For interrupts ID + 0x18C + 0x20 + read-write + 0x00000000 + + + ICENABLER3 + ICENABLER3 + 0 + 32 + + + + + GICD_ICENABLER4 + GICD_ICENABLER4 + For interrupts ID + 0x190 + 0x20 + read-write + 0x00000000 + + + ICENABLER4 + ICENABLER4 + 0 + 32 + + + + + GICD_ICENABLER5 + GICD_ICENABLER5 + For interrupts ID + 0x194 + 0x20 + read-write + 0x00000000 + + + ICENABLER5 + ICENABLER5 + 0 + 32 + + + + + GICD_ICENABLER6 + GICD_ICENABLER6 + For interrupts ID + 0x198 + 0x20 + read-write + 0x00000000 + + + ICENABLER6 + ICENABLER6 + 0 + 32 + + + + + GICD_ICENABLER7 + GICD_ICENABLER7 + For interrupts ID + 0x19C + 0x20 + read-write + 0x00000000 + + + ICENABLER7 + ICENABLER7 + 0 + 32 + + + + + GICD_ICENABLER8 + GICD_ICENABLER8 + For interrupts ID + 0x1A0 + 0x20 + read-write + 0x00000000 + + + ICENABLER8 + ICENABLER8 + 0 + 32 + + + + + GICD_ISPENDR0 + GICD_ISPENDR0 + For interrupts ID + 0x200 + 0x20 + read-write + 0x00000000 + + + ISPENDR0 + ISPENDR0 + 0 + 32 + + + + + GICD_ISPENDR1 + GICD_ISPENDR1 + For interrupts ID + 0x204 + 0x20 + read-write + 0x00000000 + + + ISPENDR1 + ISPENDR1 + 0 + 32 + + + + + GICD_ISPENDR2 + GICD_ISPENDR2 + For interrupts ID + 0x208 + 0x20 + read-write + 0x00000000 + + + ISPENDR2 + ISPENDR2 + 0 + 32 + + + + + GICD_ISPENDR3 + GICD_ISPENDR3 + For interrupts ID + 0x20C + 0x20 + read-write + 0x00000000 + + + ISPENDR3 + ISPENDR3 + 0 + 32 + + + + + GICD_ISPENDR4 + GICD_ISPENDR4 + For interrupts ID + 0x210 + 0x20 + read-write + 0x00000000 + + + ISPENDR4 + ISPENDR4 + 0 + 32 + + + + + GICD_ISPENDR5 + GICD_ISPENDR5 + For interrupts ID + 0x214 + 0x20 + read-write + 0x00000000 + + + ISPENDR5 + ISPENDR5 + 0 + 32 + + + + + GICD_ISPENDR6 + GICD_ISPENDR6 + For interrupts ID + 0x218 + 0x20 + read-write + 0x00000000 + + + ISPENDR6 + ISPENDR6 + 0 + 32 + + + + + GICD_ISPENDR7 + GICD_ISPENDR7 + For interrupts ID + 0x21C + 0x20 + read-write + 0x00000000 + + + ISPENDR7 + ISPENDR7 + 0 + 32 + + + + + GICD_ISPENDR8 + GICD_ISPENDR8 + For interrupts ID + 0x220 + 0x20 + read-write + 0x00000000 + + + ISPENDR8 + ISPENDR8 + 0 + 32 + + + + + GICD_ICPENDR0 + GICD_ICPENDR0 + For interrupts ID + 0x280 + 0x20 + read-write + 0x00000000 + + + ICPENDR0 + ICPENDR0 + 0 + 32 + + + + + GICD_ICPENDR1 + GICD_ICPENDR1 + For interrupts ID + 0x284 + 0x20 + read-write + 0x00000000 + + + ICPENDR1 + ICPENDR1 + 0 + 32 + + + + + GICD_ICPENDR2 + GICD_ICPENDR2 + For interrupts ID + 0x288 + 0x20 + read-write + 0x00000000 + + + ICPENDR2 + ICPENDR2 + 0 + 32 + + + + + GICD_ICPENDR3 + GICD_ICPENDR3 + For interrupts ID + 0x28C + 0x20 + read-write + 0x00000000 + + + ICPENDR3 + ICPENDR3 + 0 + 32 + + + + + GICD_ICPENDR4 + GICD_ICPENDR4 + For interrupts ID + 0x290 + 0x20 + read-write + 0x00000000 + + + ICPENDR4 + ICPENDR4 + 0 + 32 + + + + + GICD_ICPENDR5 + GICD_ICPENDR5 + For interrupts ID + 0x294 + 0x20 + read-write + 0x00000000 + + + ICPENDR5 + ICPENDR5 + 0 + 32 + + + + + GICD_ICPENDR6 + GICD_ICPENDR6 + For interrupts ID + 0x298 + 0x20 + read-write + 0x00000000 + + + ICPENDR6 + ICPENDR6 + 0 + 32 + + + + + GICD_ICPENDR7 + GICD_ICPENDR7 + For interrupts ID + 0x29C + 0x20 + read-write + 0x00000000 + + + ICPENDR7 + ICPENDR7 + 0 + 32 + + + + + GICD_ICPENDR8 + GICD_ICPENDR8 + For interrupts ID + 0x2A0 + 0x20 + read-write + 0x00000000 + + + ICPENDR8 + ICPENDR8 + 0 + 32 + + + + + GICD_ISACTIVER0 + GICD_ISACTIVER0 + For interrupts ID + 0x300 + 0x20 + read-write + 0x00000000 + + + ISACTIVER0 + ISACTIVER0 + 0 + 32 + + + + + GICD_ISACTIVER1 + GICD_ISACTIVER1 + For interrupts ID + 0x304 + 0x20 + read-write + 0x00000000 + + + ISACTIVER1 + ISACTIVER1 + 0 + 32 + + + + + GICD_ISACTIVER2 + GICD_ISACTIVER2 + For interrupts ID + 0x308 + 0x20 + read-write + 0x00000000 + + + ISACTIVER2 + ISACTIVER2 + 0 + 32 + + + + + GICD_ISACTIVER3 + GICD_ISACTIVER3 + For interrupts ID + 0x30C + 0x20 + read-write + 0x00000000 + + + ISACTIVER3 + ISACTIVER3 + 0 + 32 + + + + + GICD_ISACTIVER4 + GICD_ISACTIVER4 + For interrupts ID + 0x310 + 0x20 + read-write + 0x00000000 + + + ISACTIVER4 + ISACTIVER4 + 0 + 32 + + + + + GICD_ISACTIVER5 + GICD_ISACTIVER5 + For interrupts ID + 0x314 + 0x20 + read-write + 0x00000000 + + + ISACTIVER5 + ISACTIVER5 + 0 + 32 + + + + + GICD_ISACTIVER6 + GICD_ISACTIVER6 + For interrupts ID + 0x318 + 0x20 + read-write + 0x00000000 + + + ISACTIVER6 + ISACTIVER6 + 0 + 32 + + + + + GICD_ISACTIVER7 + GICD_ISACTIVER7 + For interrupts ID + 0x31C + 0x20 + read-write + 0x00000000 + + + ISACTIVER7 + ISACTIVER7 + 0 + 32 + + + + + GICD_ISACTIVER8 + GICD_ISACTIVER8 + For interrupts ID + 0x320 + 0x20 + read-write + 0x00000000 + + + ISACTIVER8 + ISACTIVER8 + 0 + 32 + + + + + GICD_ICACTIVER0 + GICD_ICACTIVER0 + For interrupts ID + 0x380 + 0x20 + read-write + 0x00000000 + + + ICACTIVER0 + ICACTIVER0 + 0 + 32 + + + + + GICD_ICACTIVER1 + GICD_ICACTIVER1 + For interrupts ID + 0x384 + 0x20 + read-write + 0x00000000 + + + ICACTIVER1 + ICACTIVER1 + 0 + 32 + + + + + GICD_ICACTIVER2 + GICD_ICACTIVER2 + For interrupts ID + 0x388 + 0x20 + read-write + 0x00000000 + + + ICACTIVER2 + ICACTIVER2 + 0 + 32 + + + + + GICD_ICACTIVER3 + GICD_ICACTIVER3 + For interrupts ID + 0x38C + 0x20 + read-write + 0x00000000 + + + ICACTIVER3 + ICACTIVER3 + 0 + 32 + + + + + GICD_ICACTIVER4 + GICD_ICACTIVER4 + For interrupts ID + 0x390 + 0x20 + read-write + 0x00000000 + + + ICACTIVER4 + ICACTIVER4 + 0 + 32 + + + + + GICD_ICACTIVER5 + GICD_ICACTIVER5 + For interrupts ID + 0x394 + 0x20 + read-write + 0x00000000 + + + ICACTIVER5 + ICACTIVER5 + 0 + 32 + + + + + GICD_ICACTIVER6 + GICD_ICACTIVER6 + For interrupts ID + 0x398 + 0x20 + read-write + 0x00000000 + + + ICACTIVER6 + ICACTIVER6 + 0 + 32 + + + + + GICD_ICACTIVER7 + GICD_ICACTIVER7 + For interrupts ID + 0x39C + 0x20 + read-write + 0x00000000 + + + ICACTIVER7 + ICACTIVER7 + 0 + 32 + + + + + GICD_ICACTIVER8 + GICD_ICACTIVER8 + For interrupts ID + 0x3A0 + 0x20 + read-write + 0x00000000 + + + ICACTIVER8 + ICACTIVER8 + 0 + 32 + + + + + GICD_IPRIORITYR0 + GICD_IPRIORITYR0 + GICD interrupt priority register 0 + 0x400 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR1 + GICD_IPRIORITYR1 + GICD interrupt priority register 1 + 0x404 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR2 + GICD_IPRIORITYR2 + GICD interrupt priority register 2 + 0x408 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR3 + GICD_IPRIORITYR3 + GICD interrupt priority register 3 + 0x40C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR4 + GICD_IPRIORITYR4 + GICD interrupt priority register 4 + 0x410 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR5 + GICD_IPRIORITYR5 + GICD interrupt priority register 5 + 0x414 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR6 + GICD_IPRIORITYR6 + GICD interrupt priority register 6 + 0x418 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR7 + GICD_IPRIORITYR7 + GICD interrupt priority register 7 + 0x41C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR8 + GICD_IPRIORITYR8 + GICD interrupt priority register 8 + 0x420 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR9 + GICD_IPRIORITYR9 + GICD interrupt priority register 9 + 0x424 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR10 + GICD_IPRIORITYR10 + GICD interrupt priority register 10 + 0x428 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR11 + GICD_IPRIORITYR11 + GICD interrupt priority register 11 + 0x42C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR12 + GICD_IPRIORITYR12 + GICD interrupt priority register 12 + 0x430 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR13 + GICD_IPRIORITYR13 + GICD interrupt priority register 13 + 0x434 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR14 + GICD_IPRIORITYR14 + GICD interrupt priority register 14 + 0x438 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR15 + GICD_IPRIORITYR15 + GICD interrupt priority register 15 + 0x43C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR16 + GICD_IPRIORITYR16 + GICD interrupt priority register 16 + 0x440 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR17 + GICD_IPRIORITYR17 + GICD interrupt priority register 17 + 0x444 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR18 + GICD_IPRIORITYR18 + GICD interrupt priority register 18 + 0x448 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR19 + GICD_IPRIORITYR19 + GICD interrupt priority register 19 + 0x44C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR20 + GICD_IPRIORITYR20 + GICD interrupt priority register 20 + 0x450 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR21 + GICD_IPRIORITYR21 + GICD interrupt priority register 21 + 0x454 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR22 + GICD_IPRIORITYR22 + GICD interrupt priority register 22 + 0x458 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR23 + GICD_IPRIORITYR23 + GICD interrupt priority register 23 + 0x45C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR24 + GICD_IPRIORITYR24 + GICD interrupt priority register 24 + 0x460 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR25 + GICD_IPRIORITYR25 + GICD interrupt priority register 25 + 0x464 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR26 + GICD_IPRIORITYR26 + GICD interrupt priority register 26 + 0x468 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR27 + GICD_IPRIORITYR27 + GICD interrupt priority register 27 + 0x46C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR28 + GICD_IPRIORITYR28 + GICD interrupt priority register 28 + 0x470 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR29 + GICD_IPRIORITYR29 + GICD interrupt priority register 29 + 0x474 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR30 + GICD_IPRIORITYR30 + GICD interrupt priority register 30 + 0x478 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR31 + GICD_IPRIORITYR31 + GICD interrupt priority register 31 + 0x47C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR32 + GICD_IPRIORITYR32 + GICD interrupt priority register 32 + 0x480 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR33 + GICD_IPRIORITYR33 + GICD interrupt priority register 33 + 0x484 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR34 + GICD_IPRIORITYR34 + GICD interrupt priority register 34 + 0x488 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR35 + GICD_IPRIORITYR35 + GICD interrupt priority register 35 + 0x48C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR36 + GICD_IPRIORITYR36 + GICD interrupt priority register 36 + 0x490 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR37 + GICD_IPRIORITYR37 + GICD interrupt priority register 37 + 0x494 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR38 + GICD_IPRIORITYR38 + GICD interrupt priority register 38 + 0x498 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR39 + GICD_IPRIORITYR39 + GICD interrupt priority register 39 + 0x49C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR40 + GICD_IPRIORITYR40 + GICD interrupt priority register 40 + 0x4A0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR41 + GICD_IPRIORITYR41 + GICD interrupt priority register 41 + 0x4A4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR42 + GICD_IPRIORITYR42 + GICD interrupt priority register 42 + 0x4A8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR43 + GICD_IPRIORITYR43 + GICD interrupt priority register 43 + 0x4AC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR44 + GICD_IPRIORITYR44 + GICD interrupt priority register 44 + 0x4B0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR45 + GICD_IPRIORITYR45 + GICD interrupt priority register 45 + 0x4B4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR46 + GICD_IPRIORITYR46 + GICD interrupt priority register 46 + 0x4B8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR47 + GICD_IPRIORITYR47 + GICD interrupt priority register 47 + 0x4BC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR48 + GICD_IPRIORITYR48 + GICD interrupt priority register 48 + 0x4C0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR49 + GICD_IPRIORITYR49 + GICD interrupt priority register 49 + 0x4C4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR50 + GICD_IPRIORITYR50 + GICD interrupt priority register 50 + 0x4C8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR51 + GICD_IPRIORITYR51 + GICD interrupt priority register 51 + 0x4CC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR52 + GICD_IPRIORITYR52 + GICD interrupt priority register 52 + 0x4D0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR53 + GICD_IPRIORITYR53 + GICD interrupt priority register 53 + 0x4D4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR54 + GICD_IPRIORITYR54 + GICD interrupt priority register 54 + 0x4D8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR55 + GICD_IPRIORITYR55 + GICD interrupt priority register 55 + 0x4DC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR56 + GICD_IPRIORITYR56 + GICD interrupt priority register 56 + 0x4E0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR57 + GICD_IPRIORITYR57 + GICD interrupt priority register 57 + 0x4E4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR58 + GICD_IPRIORITYR58 + GICD interrupt priority register 58 + 0x4E8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR59 + GICD_IPRIORITYR59 + GICD interrupt priority register 59 + 0x4EC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR60 + GICD_IPRIORITYR60 + GICD interrupt priority register 60 + 0x4F0 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR61 + GICD_IPRIORITYR61 + GICD interrupt priority register 61 + 0x4F4 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR62 + GICD_IPRIORITYR62 + GICD interrupt priority register 62 + 0x4F8 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR63 + GICD_IPRIORITYR63 + GICD interrupt priority register 63 + 0x4FC + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR64 + GICD_IPRIORITYR64 + GICD interrupt priority register 64 + 0x500 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR65 + GICD_IPRIORITYR65 + GICD interrupt priority register 65 + 0x504 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR66 + GICD_IPRIORITYR66 + GICD interrupt priority register 66 + 0x508 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR67 + GICD_IPRIORITYR67 + GICD interrupt priority register 67 + 0x50C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR68 + GICD_IPRIORITYR68 + GICD interrupt priority register 68 + 0x510 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR69 + GICD_IPRIORITYR69 + GICD interrupt priority register 69 + 0x514 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR70 + GICD_IPRIORITYR70 + GICD interrupt priority register 70 + 0x518 + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_IPRIORITYR71 + GICD_IPRIORITYR71 + GICD interrupt priority register 71 + 0x51C + 0x20 + read-write + 0x00000000 + + + PRIORITY0 + PRIORITY0 + 3 + 5 + + + PRIORITY1 + PRIORITY1 + 11 + 5 + + + PRIORITY2 + PRIORITY2 + 19 + 5 + + + PRIORITY3 + PRIORITY3 + 27 + 5 + + + + + GICD_ITARGETSR0 + GICD_ITARGETSR0 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x800 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR1 + GICD_ITARGETSR1 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x804 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR2 + GICD_ITARGETSR2 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x808 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR3 + GICD_ITARGETSR3 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x80C + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR4 + GICD_ITARGETSR4 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x810 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR5 + GICD_ITARGETSR5 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x814 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR6 + GICD_ITARGETSR6 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x818 + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR7 + GICD_ITARGETSR7 + For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. + 0x81C + 0x20 + read-only + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR8 + GICD_ITARGETSR8 + GICD interrupt processor target register 8 + 0x820 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR9 + GICD_ITARGETSR9 + GICD interrupt processor target register 9 + 0x824 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR10 + GICD_ITARGETSR10 + GICD interrupt processor target register 10 + 0x828 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR11 + GICD_ITARGETSR11 + GICD interrupt processor target register 11 + 0x82C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR12 + GICD_ITARGETSR12 + GICD interrupt processor target register 12 + 0x830 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR13 + GICD_ITARGETSR13 + GICD interrupt processor target register 13 + 0x834 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR14 + GICD_ITARGETSR14 + GICD interrupt processor target register 14 + 0x838 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR15 + GICD_ITARGETSR15 + GICD interrupt processor target register 15 + 0x83C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR16 + GICD_ITARGETSR16 + GICD interrupt processor target register 16 + 0x840 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR17 + GICD_ITARGETSR17 + GICD interrupt processor target register 17 + 0x844 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR18 + GICD_ITARGETSR18 + GICD interrupt processor target register 18 + 0x848 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR19 + GICD_ITARGETSR19 + GICD interrupt processor target register 19 + 0x84C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR20 + GICD_ITARGETSR20 + GICD interrupt processor target register 20 + 0x850 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR21 + GICD_ITARGETSR21 + GICD interrupt processor target register 21 + 0x854 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR22 + GICD_ITARGETSR22 + GICD interrupt processor target register 22 + 0x858 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR23 + GICD_ITARGETSR23 + GICD interrupt processor target register 23 + 0x85C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR24 + GICD_ITARGETSR24 + GICD interrupt processor target register 24 + 0x860 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR25 + GICD_ITARGETSR25 + GICD interrupt processor target register 25 + 0x864 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR26 + GICD_ITARGETSR26 + GICD interrupt processor target register 26 + 0x868 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR27 + GICD_ITARGETSR27 + GICD interrupt processor target register 27 + 0x86C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR28 + GICD_ITARGETSR28 + GICD interrupt processor target register 28 + 0x870 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR29 + GICD_ITARGETSR29 + GICD interrupt processor target register 29 + 0x874 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR30 + GICD_ITARGETSR30 + GICD interrupt processor target register 30 + 0x878 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR31 + GICD_ITARGETSR31 + GICD interrupt processor target register 31 + 0x87C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR32 + GICD_ITARGETSR32 + GICD interrupt processor target register 32 + 0x880 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR33 + GICD_ITARGETSR33 + GICD interrupt processor target register 33 + 0x884 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR34 + GICD_ITARGETSR34 + GICD interrupt processor target register 34 + 0x888 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR35 + GICD_ITARGETSR35 + GICD interrupt processor target register 35 + 0x88C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR36 + GICD_ITARGETSR36 + GICD interrupt processor target register 36 + 0x890 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR37 + GICD_ITARGETSR37 + GICD interrupt processor target register 37 + 0x894 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR38 + GICD_ITARGETSR38 + GICD interrupt processor target register 38 + 0x898 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR39 + GICD_ITARGETSR39 + GICD interrupt processor target register 39 + 0x89C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR40 + GICD_ITARGETSR40 + GICD interrupt processor target register 40 + 0x8A0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR41 + GICD_ITARGETSR41 + GICD interrupt processor target register 41 + 0x8A4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR42 + GICD_ITARGETSR42 + GICD interrupt processor target register 42 + 0x8A8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR43 + GICD_ITARGETSR43 + GICD interrupt processor target register 43 + 0x8AC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR44 + GICD_ITARGETSR44 + GICD interrupt processor target register 44 + 0x8B0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR45 + GICD_ITARGETSR45 + GICD interrupt processor target register 45 + 0x8B4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR46 + GICD_ITARGETSR46 + GICD interrupt processor target register 46 + 0x8B8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR47 + GICD_ITARGETSR47 + GICD interrupt processor target register 47 + 0x8BC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR48 + GICD_ITARGETSR48 + GICD interrupt processor target register 48 + 0x8C0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR49 + GICD_ITARGETSR49 + GICD interrupt processor target register 49 + 0x8C4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR50 + GICD_ITARGETSR50 + GICD interrupt processor target register 50 + 0x8C8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR51 + GICD_ITARGETSR51 + GICD interrupt processor target register 51 + 0x8CC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR52 + GICD_ITARGETSR52 + GICD interrupt processor target register 52 + 0x8D0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR53 + GICD_ITARGETSR53 + GICD interrupt processor target register 53 + 0x8D4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR54 + GICD_ITARGETSR54 + GICD interrupt processor target register 54 + 0x8D8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR55 + GICD_ITARGETSR55 + GICD interrupt processor target register 55 + 0x8DC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR56 + GICD_ITARGETSR56 + GICD interrupt processor target register 56 + 0x8E0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR57 + GICD_ITARGETSR57 + GICD interrupt processor target register 57 + 0x8E4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR58 + GICD_ITARGETSR58 + GICD interrupt processor target register 58 + 0x8E8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR59 + GICD_ITARGETSR59 + GICD interrupt processor target register 59 + 0x8EC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR60 + GICD_ITARGETSR60 + GICD interrupt processor target register 60 + 0x8F0 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR61 + GICD_ITARGETSR61 + GICD interrupt processor target register 61 + 0x8F4 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR62 + GICD_ITARGETSR62 + GICD interrupt processor target register 62 + 0x8F8 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR63 + GICD_ITARGETSR63 + GICD interrupt processor target register 63 + 0x8FC + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR64 + GICD_ITARGETSR64 + GICD interrupt processor target register 64 + 0x900 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR65 + GICD_ITARGETSR65 + GICD interrupt processor target register 65 + 0x904 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR66 + GICD_ITARGETSR66 + GICD interrupt processor target register 66 + 0x908 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR67 + GICD_ITARGETSR67 + GICD interrupt processor target register 67 + 0x90C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR68 + GICD_ITARGETSR68 + GICD interrupt processor target register 68 + 0x910 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR69 + GICD_ITARGETSR69 + GICD interrupt processor target register 69 + 0x914 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR70 + GICD_ITARGETSR70 + GICD interrupt processor target register 70 + 0x918 + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ITARGETSR71 + GICD_ITARGETSR71 + GICD interrupt processor target register 71 + 0x91C + 0x20 + read-write + 0x00000000 + + + CPU_TARGETS0 + CPU_TARGETS0 + 0 + 2 + + + CPU_TARGETS1 + CPU_TARGETS1 + 8 + 2 + + + CPU_TARGETS2 + CPU_TARGETS2 + 16 + 2 + + + CPU_TARGETS3 + CPU_TARGETS3 + 24 + 2 + + + + + GICD_ICFGR0 + GICD_ICFGR0 + GICD interrupt configuration register + 0xC00 + 0x20 + read-write + 0xAAAAAAAA + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR1 + GICD_ICFGR1 + GICD interrupt configuration register + 0xC04 + 0x20 + read-write + 0x55540000 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR2 + GICD_ICFGR2 + GICD interrupt configuration register 2 + 0xC08 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR3 + GICD_ICFGR3 + GICD interrupt configuration register 3 + 0xC0C + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR4 + GICD_ICFGR4 + GICD interrupt configuration register 4 + 0xC10 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR5 + GICD_ICFGR5 + GICD interrupt configuration register 5 + 0xC14 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR6 + GICD_ICFGR6 + GICD interrupt configuration register 6 + 0xC18 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR7 + GICD_ICFGR7 + GICD interrupt configuration register 7 + 0xC1C + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR8 + GICD_ICFGR8 + GICD interrupt configuration register 8 + 0xC20 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR9 + GICD_ICFGR9 + GICD interrupt configuration register 9 + 0xC24 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR10 + GICD_ICFGR10 + GICD interrupt configuration register 10 + 0xC28 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR11 + GICD_ICFGR11 + GICD interrupt configuration register 11 + 0xC2C + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR12 + GICD_ICFGR12 + GICD interrupt configuration register 12 + 0xC30 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR13 + GICD_ICFGR13 + GICD interrupt configuration register 13 + 0xC34 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR14 + GICD_ICFGR14 + GICD interrupt configuration register 14 + 0xC38 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR15 + GICD_ICFGR15 + GICD interrupt configuration register 15 + 0xC3C + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR16 + GICD_ICFGR16 + GICD interrupt configuration register 16 + 0xC40 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_ICFGR17 + GICD_ICFGR17 + GICD interrupt configuration register 17 + 0xC44 + 0x20 + read-write + 0x55555555 + + + INT_CONFIG0 + INT_CONFIG0 + 0 + 2 + + + INT_CONFIG1 + INT_CONFIG1 + 2 + 2 + + + INT_CONFIG2 + INT_CONFIG2 + 4 + 2 + + + INT_CONFIG3 + INT_CONFIG3 + 6 + 2 + + + INT_CONFIG4 + INT_CONFIG4 + 8 + 2 + + + INT_CONFIG5 + INT_CONFIG5 + 10 + 2 + + + INT_CONFIG6 + INT_CONFIG6 + 12 + 2 + + + INT_CONFIG7 + INT_CONFIG7 + 14 + 2 + + + INT_CONFIG8 + INT_CONFIG8 + 16 + 2 + + + INT_CONFIG9 + INT_CONFIG9 + 18 + 2 + + + INT_CONFIG10 + INT_CONFIG10 + 20 + 2 + + + INT_CONFIG11 + INT_CONFIG11 + 22 + 2 + + + INT_CONFIG12 + INT_CONFIG12 + 24 + 2 + + + INT_CONFIG13 + INT_CONFIG13 + 26 + 2 + + + INT_CONFIG14 + INT_CONFIG14 + 28 + 2 + + + INT_CONFIG15 + INT_CONFIG15 + 30 + 2 + + + + + GICD_PPISR + GICD_PPISR + GICD private peripheral interrupt status register + 0xD00 + 0x20 + read-only + 0x00000000 + + + PPI6 + PPI6 + 9 + 1 + + + PPI5 + PPI5 + 10 + 1 + + + PPI4 + PPI4 + 11 + 1 + + + PPI0 + PPI0 + 12 + 1 + + + PPI1 + PPI1 + 13 + 1 + + + PPI2 + PPI2 + 14 + 1 + + + PPI3 + PPI3 + 15 + 1 + + + + + GICD_SPISR1 + GICD_SPISR1 + For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32] + 0xD08 + 0x20 + read-only + 0x00000000 + + + SPISR1 + SPISR1 + 0 + 32 + + + + + GICD_SPISR2 + GICD_SPISR2 + For interrupts ID + 0xD0C + 0x20 + read-only + 0x00000000 + + + SPISR2 + SPISR2 + 0 + 32 + + + + + GICD_SPISR3 + GICD_SPISR3 + For interrupts ID + 0xD10 + 0x20 + read-only + 0x00000000 + + + SPISR3 + SPISR3 + 0 + 32 + + + + + GICD_SPISR4 + GICD_SPISR4 + For interrupts ID + 0xD14 + 0x20 + read-only + 0x00000000 + + + SPISR4 + SPISR4 + 0 + 32 + + + + + GICD_SPISR5 + GICD_SPISR5 + For interrupts ID + 0xD18 + 0x20 + read-only + 0x00000000 + + + SPISR5 + SPISR5 + 0 + 32 + + + + + GICD_SPISR6 + GICD_SPISR6 + For interrupts ID + 0xD1C + 0x20 + read-only + 0x00000000 + + + SPISR6 + SPISR6 + 0 + 32 + + + + + GICD_SPISR7 + GICD_SPISR7 + For interrupts ID + 0xD20 + 0x20 + read-only + 0x00000000 + + + SPISR7 + SPISR7 + 0 + 32 + + + + + GICD_SGIR + GICD_SGIR + GICD software generated interrupt register + 0xF00 + 0x20 + write-only + 0x00000000 + + + SGIINTID + SGIINTID + 0 + 4 + + + NSATT + NSATT + 15 + 1 + + + CPUTARGETLIST + CPUTARGETLIST + 16 + 2 + + + TARGETLISTFILTER + TARGETLISTFILTER + 24 + 2 + + + + + GICD_CPENDSGIR0 + GICD_CPENDSGIR0 + For SGI x*4 to SGI x*4+3 + 0xF10 + 0x20 + read-write + 0x00000000 + + + SGI_CLEAR_PENDING0 + SGI_CLEAR_PENDING0 + 0 + 2 + + + SGI_CLEAR_PENDING1 + SGI_CLEAR_PENDING1 + 8 + 2 + + + SGI_CLEAR_PENDING2 + SGI_CLEAR_PENDING2 + 16 + 2 + + + SGI_CLEAR_PENDING3 + SGI_CLEAR_PENDING3 + 24 + 2 + + + + + GICD_CPENDSGIR1 + GICD_CPENDSGIR1 + For SGI x*4 to SGI x*4+3 + 0xF14 + 0x20 + read-write + 0x00000000 + + + SGI_CLEAR_PENDING0 + SGI_CLEAR_PENDING0 + 0 + 2 + + + SGI_CLEAR_PENDING1 + SGI_CLEAR_PENDING1 + 8 + 2 + + + SGI_CLEAR_PENDING2 + SGI_CLEAR_PENDING2 + 16 + 2 + + + SGI_CLEAR_PENDING3 + SGI_CLEAR_PENDING3 + 24 + 2 + + + + + GICD_CPENDSGIR2 + GICD_CPENDSGIR2 + For SGI x*4 to SGI x*4+3 + 0xF18 + 0x20 + read-write + 0x00000000 + + + SGI_CLEAR_PENDING0 + SGI_CLEAR_PENDING0 + 0 + 2 + + + SGI_CLEAR_PENDING1 + SGI_CLEAR_PENDING1 + 8 + 2 + + + SGI_CLEAR_PENDING2 + SGI_CLEAR_PENDING2 + 16 + 2 + + + SGI_CLEAR_PENDING3 + SGI_CLEAR_PENDING3 + 24 + 2 + + + + + GICD_CPENDSGIR3 + GICD_CPENDSGIR3 + For SGI x*4 to SGI x*4+3 + 0xF1C + 0x20 + read-write + 0x00000000 + + + SGI_CLEAR_PENDING0 + SGI_CLEAR_PENDING0 + 0 + 2 + + + SGI_CLEAR_PENDING1 + SGI_CLEAR_PENDING1 + 8 + 2 + + + SGI_CLEAR_PENDING2 + SGI_CLEAR_PENDING2 + 16 + 2 + + + SGI_CLEAR_PENDING3 + SGI_CLEAR_PENDING3 + 24 + 2 + + + + + GICD_SPENDSGIR0 + GICD_SPENDSGIR0 + For SGI x*4 to SGI x*4+3 + 0xF20 + 0x20 + read-write + 0x00000000 + + + SGI_SET_PENDING0 + SGI_SET_PENDING0 + 0 + 2 + + + SGI_SET_PENDING1 + SGI_SET_PENDING1 + 8 + 2 + + + SGI_SET_PENDING2 + SGI_SET_PENDING2 + 16 + 2 + + + SGI_SET_PENDING3 + SGI_SET_PENDING3 + 24 + 2 + + + + + GICD_SPENDSGIR1 + GICD_SPENDSGIR1 + For SGI x*4 to SGI x*4+3 + 0xF24 + 0x20 + read-write + 0x00000000 + + + SGI_SET_PENDING0 + SGI_SET_PENDING0 + 0 + 2 + + + SGI_SET_PENDING1 + SGI_SET_PENDING1 + 8 + 2 + + + SGI_SET_PENDING2 + SGI_SET_PENDING2 + 16 + 2 + + + SGI_SET_PENDING3 + SGI_SET_PENDING3 + 24 + 2 + + + + + GICD_SPENDSGIR2 + GICD_SPENDSGIR2 + For SGI x*4 to SGI x*4+3 + 0xF28 + 0x20 + read-write + 0x00000000 + + + SGI_SET_PENDING0 + SGI_SET_PENDING0 + 0 + 2 + + + SGI_SET_PENDING1 + SGI_SET_PENDING1 + 8 + 2 + + + SGI_SET_PENDING2 + SGI_SET_PENDING2 + 16 + 2 + + + SGI_SET_PENDING3 + SGI_SET_PENDING3 + 24 + 2 + + + + + GICD_SPENDSGIR3 + GICD_SPENDSGIR3 + For SGI x*4 to SGI x*4+3 + 0xF2C + 0x20 + read-write + 0x00000000 + + + SGI_SET_PENDING0 + SGI_SET_PENDING0 + 0 + 2 + + + SGI_SET_PENDING1 + SGI_SET_PENDING1 + 8 + 2 + + + SGI_SET_PENDING2 + SGI_SET_PENDING2 + 16 + 2 + + + SGI_SET_PENDING3 + SGI_SET_PENDING3 + 24 + 2 + + + + + GICD_PIDR4 + GICD_PIDR4 + GICD peripheral ID4 register + 0xFD0 + 0x20 + read-only + 0x00000004 + + + PIDR4 + PIDR4 + 0 + 32 + + + + + GICD_PIDR5 + GICD_PIDR5 + GICD peripheral ID5 to ID7 register 5 + 0xFD4 + 0x20 + read-only + 0x00000000 + + + PIDR5 + PIDR5 + 0 + 32 + + + + + GICD_PIDR6 + GICD_PIDR6 + GICD peripheral ID5 to ID7 register 6 + 0xFD8 + 0x20 + read-only + 0x00000000 + + + PIDR6 + PIDR6 + 0 + 32 + + + + + GICD_PIDR7 + GICD_PIDR7 + GICD peripheral ID5 to ID7 register 7 + 0xFDC + 0x20 + read-only + 0x00000000 + + + PIDR7 + PIDR7 + 0 + 32 + + + + + GICD_PIDR0 + GICD_PIDR0 + GICD peripheral ID0 register + 0xFE0 + 0x20 + read-only + 0x00000090 + + + PIDR0 + PIDR0 + 0 + 32 + + + + + GICD_PIDR1 + GICD_PIDR1 + GICD peripheral ID1 register + 0xFE4 + 0x20 + read-only + 0x000000B4 + + + PIDR1 + PIDR1 + 0 + 32 + + + + + GICD_PIDR2 + GICD_PIDR2 + GICD peripheral ID2 register + 0xFE8 + 0x20 + read-only + 0x0000002B + + + PIDR2 + PIDR2 + 0 + 32 + + + + + GICD_PIDR3 + GICD_PIDR3 + GICD peripheral ID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + PIDR3 + PIDR3 + 0 + 32 + + + + + GICD_CIDR0 + GICD_CIDR0 + GICD component ID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + CIDR0 + CIDR0 + 0 + 32 + + + + + GICD_CIDR1 + GICD_CIDR1 + GICD component ID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + CIDR1 + CIDR1 + 0 + 32 + + + + + GICD_CIDR2 + GICD_CIDR2 + GICD component ID2 register + 0xFF8 + 0x20 + read-only + 0x00000005 + + + CIDR2 + CIDR2 + 0 + 32 + + + + + GICD_CIDR3 + GICD_CIDR3 + GICD component ID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + CIDR3 + CIDR3 + 0 + 32 + + + + + + + GICC + GICC + GICC + 0xA0022000 + + 0x0 + 0x2000 + registers + + + + GICC_CTLR + GICC_CTLR + GICC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLEGRP0 + ENABLEGRP0 + 0 + 1 + + + ENABLEGRP1 + ENABLEGRP1 + 1 + 1 + + + ACKCTL + ACKCTL + 2 + 1 + + + FIQEN + FIQEN + 3 + 1 + + + CBPR + CBPR + 4 + 1 + + + FIQBYPDISGRP0 + FIQBYPDISGRP0 + 5 + 1 + + + IRQBYPDISGRP0 + IRQBYPDISGRP0 + 6 + 1 + + + FIQBYPDISGRP1 + FIQBYPDISGRP1 + 7 + 1 + + + IRQBYPDISGRP1 + IRQBYPDISGRP1 + 8 + 1 + + + EOIMODES + EOIMODES + 9 + 1 + + + EOIMODENS + EOIMODENS + 10 + 1 + + + + + GICC_PMR + GICC_PMR + GICC input priority mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRIORITY + PRIORITY + 3 + 5 + + + + + GICC_BPR + GICC_BPR + GICC binary point register + 0x8 + 0x20 + read-write + 0x00000002 + + + BINARY_POINT + BINARY_POINT + 0 + 3 + + + + + GICC_IAR + GICC_IAR + GICC interrupt acknowledge register + 0xC + 0x20 + read-only + 0x000003FF + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_EOIR + GICC_EOIR + GICC end of interrupt register + 0x10 + 0x20 + write-only + 0x00000000 + + + EOIINTID + EOIINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_RPR + GICC_RPR + GICC running priority register + 0x14 + 0x20 + read-only + 0x000000FF + + + PRIORITY + PRIORITY + 3 + 5 + + + + + GICC_HPPIR + GICC_HPPIR + GICC highest priority pending interrupt register + 0x18 + 0x20 + read-only + 0x000003FF + + + PENDINTID + PENDINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_ABPR + GICC_ABPR + GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR. + 0x1C + 0x20 + read-write + 0x00000003 + + + BINARY_POINT + BINARY_POINT + 0 + 3 + + + + + GICC_AIAR + GICC_AIAR + GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR. + 0x20 + 0x20 + read-only + 0x000003FF + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_AEOIR + GICC_AEOIR + GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used. + 0x24 + 0x20 + write-only + 0x00000000 + + + EOIINTID + EOIINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_AHPPIR + GICC_AHPPIR + ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR. + 0x28 + 0x20 + read-only + 0x000003FF + + + PENDINTID + PENDINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICC_APR0 + GICC_APR0 + GICC active priority register + 0xD0 + 0x20 + read-write + 0x00000000 + + + APR0 + APR0 + 0 + 32 + + + + + GICC_NSAPR0 + GICC_NSAPR0 + GICC non-secure active priority register + 0xE0 + 0x20 + read-write + 0x00000000 + + + NSAPR0 + NSAPR0 + 0 + 32 + + + + + GICC_IIDR + GICC_IIDR + GICC interface identification register + 0xFC + 0x20 + read-only + 0x0102143B + + + IMPLEMENTER + IMPLEMENTER + 0 + 12 + + + REVISION + REVISION + 12 + 4 + + + ARCH + ARCH + 16 + 4 + + + PRODUCTID + PRODUCTID + 20 + 12 + + + + + GICC_DIR + GICC_DIR + GICC deactivate interrupt register + 0x1000 + 0x20 + write-only + 0x00000000 + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + + + GICH + GICH + GICH + 0xA0024000 + + 0x0 + 0x2000 + registers + + + + GICH_HCR + GICH_HCR + GICH hypervisor control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + UIE + UIE + 1 + 1 + + + LRENPIE + LRENPIE + 2 + 1 + + + NPIE + NPIE + 3 + 1 + + + VGRP0EIE + VGRP0EIE + 4 + 1 + + + VGRP0DIE + VGRP0DIE + 5 + 1 + + + VGRP1EIE + VGRP1EIE + 6 + 1 + + + VGRP1DIE + VGRP1DIE + 7 + 1 + + + EOICOUNT + EOICOUNT + 27 + 5 + + + + + GICH_VTR + GICH_VTR + GICH VGIC type register + 0x4 + 0x20 + read-only + 0x90000003 + + + LISTREGS + LISTREGS + 0 + 5 + + + PREBITS + PREBITS + 26 + 3 + + + PRIBITS + PRIBITS + 29 + 3 + + + + + GICH_VMCR + GICH_VMCR + GICH virtual machine control register + 0x8 + 0x20 + read-write + 0x004D0000 + + + VMGRP0EN + VMGRP0EN + 0 + 1 + + + VMGRP1EN + VMGRP1EN + 1 + 1 + + + VMACKCTL + VMACKCTL + 2 + 1 + + + VMFIQEN + VMFIQEN + 3 + 1 + + + VMCBPR + VMCBPR + 4 + 1 + + + VEM + VEM + 9 + 1 + + + VMABP + VMABP + 18 + 3 + + + VMBP + VMBP + 21 + 3 + + + VMPRIMASK + VMPRIMASK + 27 + 5 + + + + + GICH_MISR + GICH_MISR + GICH maintenance interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + EOI + EOI + 0 + 1 + + + U + U + 1 + 1 + + + LRENP + LRENP + 2 + 1 + + + NP + NP + 3 + 1 + + + VGRP0E + VGRP0E + 4 + 1 + + + VGRP0D + VGRP0D + 5 + 1 + + + VGRP1E + VGRP1E + 6 + 1 + + + VGRP1D + VGRP1D + 7 + 1 + + + + + GICH_EISR0 + GICH_EISR0 + GICH end of interrupt status register + 0x20 + 0x20 + read-only + 0x00000000 + + + EISR0 + EISR0 + 0 + 32 + + + + + GICH_ELSR0 + GICH_ELSR0 + GICH empty list status register + 0x30 + 0x20 + read-only + 0x0000000F + + + ELSR0 + ELSR0 + 0 + 32 + + + + + GICH_APR0 + GICH_APR0 + GICH active priority register + 0xF0 + 0x20 + read-write + 0x00000000 + + + APR0 + APR0 + 0 + 32 + + + + + GICH_LR0 + GICH_LR0 + GICH list register 0 + 0x100 + 0x20 + read-write + 0x00000000 + + + VIRTUALID + VIRTUALID + 0 + 10 + + + PHYSICALID + PHYSICALID + 10 + 10 + + + PRIORITY + PRIORITY + 23 + 5 + + + STATE + STATE + 28 + 2 + + + GRP1 + GRP1 + 30 + 1 + + + HW + HW + 31 + 1 + + + + + GICH_LR1 + GICH_LR1 + GICH list register 1 + 0x104 + 0x20 + read-write + 0x00000000 + + + VIRTUALID + VIRTUALID + 0 + 10 + + + PHYSICALID + PHYSICALID + 10 + 10 + + + PRIORITY + PRIORITY + 23 + 5 + + + STATE + STATE + 28 + 2 + + + GRP1 + GRP1 + 30 + 1 + + + HW + HW + 31 + 1 + + + + + GICH_LR2 + GICH_LR2 + GICH list register 2 + 0x108 + 0x20 + read-write + 0x00000000 + + + VIRTUALID + VIRTUALID + 0 + 10 + + + PHYSICALID + PHYSICALID + 10 + 10 + + + PRIORITY + PRIORITY + 23 + 5 + + + STATE + STATE + 28 + 2 + + + GRP1 + GRP1 + 30 + 1 + + + HW + HW + 31 + 1 + + + + + GICH_LR3 + GICH_LR3 + GICH list register 3 + 0x10C + 0x20 + read-write + 0x00000000 + + + VIRTUALID + VIRTUALID + 0 + 10 + + + PHYSICALID + PHYSICALID + 10 + 10 + + + PRIORITY + PRIORITY + 23 + 5 + + + STATE + STATE + 28 + 2 + + + GRP1 + GRP1 + 30 + 1 + + + HW + HW + 31 + 1 + + + + + + + GICV + GICV + GICV + 0xA0026000 + + 0x0 + 0x2000 + registers + + + + GICV_CTLR + GICV_CTLR + GICV virtual machine control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLEGRP0 + ENABLEGRP0 + 0 + 1 + + + ENABLEGRP1 + ENABLEGRP1 + 1 + 1 + + + ACKCTL + ACKCTL + 2 + 1 + + + FIQEN + FIQEN + 3 + 1 + + + CBPR + CBPR + 4 + 1 + + + EOIMODE + EOIMODE + 9 + 1 + + + + + GICV_PMR + GICV_PMR + GICV VM priority mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRIORITY + PRIORITY + 3 + 5 + + + + + GICV_BPR + GICV_BPR + GICV VM binary point register + 0x8 + 0x20 + read-write + 0x00000002 + + + BINARY_POINT + BINARY_POINT + 0 + 3 + + + + + GICV_IAR + GICV_IAR + GICV VM interrupt acknowledge register + 0xC + 0x20 + read-only + 0x000003FF + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_EOIR + GICV_EOIR + GICV VM end of interrupt register + 0x10 + 0x20 + write-only + 0x00000000 + + + EOIINTID + EOIINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_RPR + GICV_RPR + GICV VM running priority register + 0x14 + 0x20 + read-only + 0x000000FF + + + PRIORITY + PRIORITY + 3 + 5 + + + + + GICV_HPPIR + GICV_HPPIR + GICV VM highest priority pending interrupt register + 0x18 + 0x20 + read-only + 0x000003FF + + + PENDINTID + PENDINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_ABPR + GICV_ABPR + GICV VM aliased binary point register + 0x1C + 0x20 + read-write + 0x00000003 + + + BINARY_POINT + BINARY_POINT + 0 + 3 + + + + + GICV_AIAR + GICV_AIAR + GICV VM aliased interrupt register + 0x20 + 0x20 + read-only + 0x000003FF + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_AEOIR + GICV_AEOIR + GICV VM aliased end of interrupt register + 0x24 + 0x20 + write-only + 0x00000000 + + + EOIINTID + EOIINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_AHPPIR + GICV_AHPPIR + GICV VM aliased highest priority pending interrupt register + 0x28 + 0x20 + read-only + 0x000003FF + + + PENDINTID + PENDINTID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + GICV_APR0 + GICV_APR0 + The GICV_APR0 is an alias of GICH_APR. + 0xD0 + 0x20 + read-write + 0x00000000 + + + APR0 + APR0 + 0 + 32 + + + + + GICV_IIDR + GICV_IIDR + The GICV_IIDR is an alias of GICC_IIDR. + 0xFC + 0x20 + read-only + 0x0102143B + + + IIDR + IIDR + 0 + 32 + + + + + GICV_DIR + GICV_DIR + GICV VM deactivate interrupt register + 0x1000 + 0x20 + write-only + 0x00000000 + + + INTERRUPT_ID + INTERRUPT_ID + 0 + 10 + + + CPUID + CPUID + 10 + 1 + + + + + + + TIM1 + TIM1 + TIM1 + 0x44000000 + + 0x0 + 0x400 + registers + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM1_CCMR1ALTERNATE1 + TIM1_CCMR1ALTERNATE1 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM1_CCMR2ALTERNATE17 + TIM1_CCMR2ALTERNATE17 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM1_BDTR + TIM1_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM1_CCMR3 + TIM1_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + + + BKDF1BK0E + BKDF1BK0E + 8 + 1 + + + BKINP + BKINP + 9 + 1 + + + ETRSEL + ETRSEL + 14 + 4 + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 Alternate function register 2 + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BK2INE + 0 + 1 + + + BK2DF1BK1E + BK2DF1BK1E + 8 + 1 + + + BK2INP + BK2INP + 9 + 1 + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + + + TI2SEL + TI2SEL + 8 + 4 + + + TI3SEL + TI3SEL + 16 + 4 + + + TI4SEL + TI4SEL + 24 + 4 + + + + + + + TIM2 + TIM2 + TIM2 + 0x40000000 + + 0x0 + 0x400 + registers + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM2_CCMR1ALTERNATE2 + TIM2_CCMR1ALTERNATE2 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM2_CCMR2ALTERNATE18 + TIM2_CCMR2ALTERNATE18 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM2_RCR + TIM2_RCR + TIM2 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM2_BDTR + TIM2_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM2_CCMR3 + TIM2_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM2_CCR5 + TIM2_CCR5 + TIM2 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM2_CCR6 + TIM2_CCR6 + TIM2 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM3 + TIM3 + TIM3 + 0x40001000 + + 0x0 + 0x400 + registers + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM3_CCMR1ALTERNATE3 + TIM3_CCMR1ALTERNATE3 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM3_CCMR2ALTERNATE19 + TIM3_CCMR2ALTERNATE19 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM3_RCR + TIM3_RCR + TIM3 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM3_BDTR + TIM3_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM3_CCMR3 + TIM3_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM3_CCR5 + TIM3_CCR5 + TIM3 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM3_CCR6 + TIM3_CCR6 + TIM3 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM4 + TIM4 + TIM4 + 0x40002000 + + 0x0 + 0x400 + registers + + + + TIM4_CR1 + TIM4_CR1 + TIM4 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM4_CR2 + TIM4_CR2 + TIM4 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM4_SMCR + TIM4_SMCR + TIM4 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM4_DIER + TIM4_DIER + TIM4 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM4_SR + TIM4_SR + TIM4 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM4_EGR + TIM4_EGR + TIM4 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM4_CCMR1ALTERNATE4 + TIM4_CCMR1ALTERNATE4 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM4_CCMR2ALTERNATE20 + TIM4_CCMR2ALTERNATE20 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM4_CCER + TIM4_CCER + TIM4 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM4_CNT + TIM4_CNT + TIM4 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM4_PSC + TIM4_PSC + TIM4 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM4_ARR + TIM4_ARR + TIM4 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM4_RCR + TIM4_RCR + TIM4 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM4_CCR1 + TIM4_CCR1 + TIM4 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM4_CCR2 + TIM4_CCR2 + TIM4 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM4_CCR3 + TIM4_CCR3 + TIM4 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM4_CCR4 + TIM4_CCR4 + TIM4 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM4_BDTR + TIM4_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM4_DCR + TIM4_DCR + TIM4 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM4_DMAR + TIM4_DMAR + TIM4 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM4_CCMR3 + TIM4_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM4_CCR5 + TIM4_CCR5 + TIM4 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM4_CCR6 + TIM4_CCR6 + TIM4 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM5 + TIM5 + TIM5 + 0x40003000 + + 0x0 + 0x400 + registers + + + + TIM5_CR1 + TIM5_CR1 + TIM5 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM5_CR2 + TIM5_CR2 + TIM5 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM5_SMCR + TIM5_SMCR + TIM5 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM5_DIER + TIM5_DIER + TIM5 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM5_SR + TIM5_SR + TIM5 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM5_EGR + TIM5_EGR + TIM5 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM5_CCMR1ALTERNATE5 + TIM5_CCMR1ALTERNATE5 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM5_CCMR2ALTERNATE21 + TIM5_CCMR2ALTERNATE21 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM5_CCER + TIM5_CCER + TIM5 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM5_CNT + TIM5_CNT + TIM5 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM5_PSC + TIM5_PSC + TIM5 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM5_ARR + TIM5_ARR + TIM5 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM5_RCR + TIM5_RCR + TIM5 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM5_CCR1 + TIM5_CCR1 + TIM5 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM5_CCR2 + TIM5_CCR2 + TIM5 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM5_CCR3 + TIM5_CCR3 + TIM5 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM5_CCR4 + TIM5_CCR4 + TIM5 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM5_BDTR + TIM5_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM5_DCR + TIM5_DCR + TIM5 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM5_DMAR + TIM5_DMAR + TIM5 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM5_CCMR3 + TIM5_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM5_CCR5 + TIM5_CCR5 + TIM5 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM5_CCR6 + TIM5_CCR6 + TIM5 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM6 + TIM6 + TIM6 + 0x40004000 + + 0x0 + 0x400 + registers + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM6_SMCR + TIM6_SMCR + TIM6 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM6_CCMR1ALTERNATE6 + TIM6_CCMR1ALTERNATE6 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM6_CCMR2ALTERNATE22 + TIM6_CCMR2ALTERNATE22 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM6_CCER + TIM6_CCER + TIM6 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM6_RCR + TIM6_RCR + TIM6 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM6_CCR1 + TIM6_CCR1 + TIM6 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM6_CCR2 + TIM6_CCR2 + TIM6 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM6_CCR3 + TIM6_CCR3 + TIM6 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM6_CCR4 + TIM6_CCR4 + TIM6 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM6_BDTR + TIM6_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM6_DCR + TIM6_DCR + TIM6 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM6_DMAR + TIM6_DMAR + TIM6 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM6_CCMR3 + TIM6_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM6_CCR5 + TIM6_CCR5 + TIM6 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM6_CCR6 + TIM6_CCR6 + TIM6 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM7 + TIM7 + TIM7 + 0x40005000 + + 0x0 + 0x400 + registers + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM7_SMCR + TIM7_SMCR + TIM7 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM7_CCMR1ALTERNATE7 + TIM7_CCMR1ALTERNATE7 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM7_CCMR2ALTERNATE23 + TIM7_CCMR2ALTERNATE23 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM7_CCER + TIM7_CCER + TIM7 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM7_RCR + TIM7_RCR + TIM7 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM7_CCR1 + TIM7_CCR1 + TIM7 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM7_CCR2 + TIM7_CCR2 + TIM7 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM7_CCR3 + TIM7_CCR3 + TIM7 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM7_CCR4 + TIM7_CCR4 + TIM7 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM7_BDTR + TIM7_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM7_DCR + TIM7_DCR + TIM7 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM7_DMAR + TIM7_DMAR + TIM7 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM7_CCMR3 + TIM7_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM7_CCR5 + TIM7_CCR5 + TIM7 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM7_CCR6 + TIM7_CCR6 + TIM7 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + + + TIM8 + TIM8 + TIM8 + 0x44001000 + + 0x0 + 0x400 + registers + + + + TIM8_CR1 + TIM8_CR1 + TIM8 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CMS + CMS + 5 + 2 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM8_CR2 + TIM8_CR2 + TIM8 control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC + 0 + 1 + + + CCUS + CCUS + 2 + 1 + + + CCDS + CCDS + 3 + 1 + + + MMS + MMS + 4 + 3 + + + TI1S + TI1S + 7 + 1 + + + OIS1 + OIS1 + 8 + 1 + + + OIS1N + OIS1N + 9 + 1 + + + OIS2 + OIS2 + 10 + 1 + + + OIS2N + OIS2N + 11 + 1 + + + OIS3 + OIS3 + 12 + 1 + + + OIS3N + OIS3N + 13 + 1 + + + OIS4 + OIS4 + 14 + 1 + + + OIS5 + OIS5 + 16 + 1 + + + OIS6 + OIS6 + 18 + 1 + + + MMS2 + MMS2 + 20 + 4 + + + + + TIM8_SMCR + TIM8_SMCR + TIM8 slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + SMS + 0 + 3 + + + TS + TS + 4 + 3 + + + MSM + MSM + 7 + 1 + + + ETF + ETF + 8 + 4 + + + ETPS + ETPS + 12 + 2 + + + ECE + ECE + 14 + 1 + + + ETP + ETP + 15 + 1 + + + SMS3 + SMS3 + 16 + 1 + + + TS3 + TS3 + 20 + 1 + + + TS4 + TS4 + 21 + 1 + + + + + TIM8_DIER + TIM8_DIER + TIM8 DMA/interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + CC2IE + CC2IE + 2 + 1 + + + CC3IE + CC3IE + 3 + 1 + + + CC4IE + CC4IE + 4 + 1 + + + COMIE + COMIE + 5 + 1 + + + TIE + TIE + 6 + 1 + + + BIE + BIE + 7 + 1 + + + UDE + UDE + 8 + 1 + + + CC1DE + CC1DE + 9 + 1 + + + CC2DE + CC2DE + 10 + 1 + + + CC3DE + CC3DE + 11 + 1 + + + CC4DE + CC4DE + 12 + 1 + + + COMDE + COMDE + 13 + 1 + + + TDE + TDE + 14 + 1 + + + + + TIM8_SR + TIM8_SR + TIM8 status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC2IF + CC2IF + 2 + 1 + + + CC3IF + CC3IF + 3 + 1 + + + CC4IF + CC4IF + 4 + 1 + + + COMIF + COMIF + 5 + 1 + + + TIF + TIF + 6 + 1 + + + BIF + BIF + 7 + 1 + + + B2IF + B2IF + 8 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + CC2OF + CC2OF + 10 + 1 + + + CC3OF + CC3OF + 11 + 1 + + + CC4OF + CC4OF + 12 + 1 + + + SBIF + SBIF + 13 + 1 + + + CC5IF + CC5IF + 16 + 1 + + + CC6IF + CC6IF + 17 + 1 + + + + + TIM8_EGR + TIM8_EGR + TIM8 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + CC2G + CC2G + 2 + 1 + + + CC3G + CC3G + 3 + 1 + + + CC4G + CC4G + 4 + 1 + + + COMG + COMG + 5 + 1 + + + TG + TG + 6 + 1 + + + BG + BG + 7 + 1 + + + B2G + B2G + 8 + 1 + + + + + TIM8_CCMR1ALTERNATE8 + TIM8_CCMR1ALTERNATE8 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + IC1PSC + IC1PSC + 2 + 2 + + + IC1F + IC1F + 4 + 4 + + + CC2S + CC2S + 8 + 2 + + + IC2PSC + IC2PSC + 10 + 2 + + + IC2F + IC2F + 12 + 4 + + + + + TIM8_CCMR2ALTERNATE24 + TIM8_CCMR2ALTERNATE24 + The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + CC3S + 0 + 2 + + + IC3PSC + IC3PSC + 2 + 2 + + + IC3F + IC3F + 4 + 4 + + + CC4S + CC4S + 8 + 2 + + + IC4PSC + IC4PSC + 10 + 2 + + + IC4F + IC4F + 12 + 4 + + + + + TIM8_CCER + TIM8_CCER + TIM8 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NE + CC1NE + 2 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + CC2E + CC2E + 4 + 1 + + + CC2P + CC2P + 5 + 1 + + + CC2NE + CC2NE + 6 + 1 + + + CC2NP + CC2NP + 7 + 1 + + + CC3E + CC3E + 8 + 1 + + + CC3P + CC3P + 9 + 1 + + + CC3NE + CC3NE + 10 + 1 + + + CC3NP + CC3NP + 11 + 1 + + + CC4E + CC4E + 12 + 1 + + + CC4P + CC4P + 13 + 1 + + + CC4NP + CC4NP + 15 + 1 + + + CC5E + CC5E + 16 + 1 + + + CC5P + CC5P + 17 + 1 + + + CC6E + CC6E + 20 + 1 + + + CC6P + CC6P + 21 + 1 + + + + + TIM8_CNT + TIM8_CNT + TIM8 counter + 0x24 + 0x20 + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM8_PSC + TIM8_PSC + TIM8 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM8_ARR + TIM8_ARR + TIM8 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM8_RCR + TIM8_RCR + TIM8 repetition counter register + 0x30 + 0x10 + read-write + 0x00000000 + + + REP + REP + 0 + 16 + + + + + TIM8_CCR1 + TIM8_CCR1 + TIM8 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM8_CCR2 + TIM8_CCR2 + TIM8 capture/compare register 2 + 0x38 + 0x10 + read-write + 0x00000000 + + + CCR2 + CCR2 + 0 + 16 + + + + + TIM8_CCR3 + TIM8_CCR3 + TIM8 capture/compare register 3 + 0x3C + 0x10 + read-write + 0x00000000 + + + CCR3 + CCR3 + 0 + 16 + + + + + TIM8_CCR4 + TIM8_CCR4 + TIM8 capture/compare register 4 + 0x40 + 0x10 + read-write + 0x00000000 + + + CCR4 + CCR4 + 0 + 16 + + + + + TIM8_BDTR + TIM8_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + + + LOCK + LOCK + 8 + 2 + + + OSSI + OSSI + 10 + 1 + + + OSSR + OSSR + 11 + 1 + + + BKE + BKE + 12 + 1 + + + BKP + BKP + 13 + 1 + + + AOE + AOE + 14 + 1 + + + MOE + MOE + 15 + 1 + + + BKF + BKF + 16 + 4 + + + BK2F + BK2F + 20 + 4 + + + BK2E + BK2E + 24 + 1 + + + BK2P + BK2P + 25 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2BID + BK2BID + 29 + 1 + + + + + TIM8_DCR + TIM8_DCR + TIM8 DMA control register + 0x48 + 0x10 + read-write + 0x00000000 + + + DBA + DBA + 0 + 5 + + + DBL + DBL + 8 + 5 + + + + + TIM8_DMAR + TIM8_DMAR + TIM8 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB + 0 + 32 + + + + + TIM8_CCMR3 + TIM8_CCMR3 + The channels 5 and 6 can only be configured in output. Output compare mode: + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + OC5FE + 2 + 1 + + + OC5PE + OC5PE + 3 + 1 + + + OC5M + OC5M + 4 + 3 + + + OC5CE + OC5CE + 7 + 1 + + + OC6FE + OC6FE + 10 + 1 + + + OC6PE + OC6PE + 11 + 1 + + + OC6M + OC6M + 12 + 3 + + + OC6CE + OC6CE + 15 + 1 + + + OC5M3 + OC5M3 + 16 + 1 + + + OC6M3 + OC6M3 + 24 + 1 + + + + + TIM8_CCR5 + TIM8_CCR5 + TIM8 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + CCR5 + 0 + 16 + + + GC5C1 + GC5C1 + 29 + 1 + + + GC5C2 + GC5C2 + 30 + 1 + + + GC5C3 + GC5C3 + 31 + 1 + + + + + TIM8_CCR6 + TIM8_CCR6 + TIM8 capture/compare register 6 + 0x5C + 0x10 + read-write + 0x00000000 + + + CCR6 + CCR6 + 0 + 16 + + + + + TIM8_AF1 + TIM8_AF1 + TIM8 Alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + + + BKDF1BK2E + BKDF1BK2E + 8 + 1 + + + BKINP + BKINP + 9 + 1 + + + ETRSEL + ETRSEL + 14 + 4 + + + + + TIM8_AF2 + TIM8_AF2 + TIM8 Alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BK2INE + 0 + 1 + + + BK2DF1BK3E + BK2DF1BK3E + 8 + 1 + + + BK2INP + BK2INP + 9 + 1 + + + + + TIM8_TISEL + TIM8_TISEL + TIM8 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + + + TI2SEL + TI2SEL + 8 + 4 + + + TI3SEL + TI3SEL + 16 + 4 + + + TI4SEL + TI4SEL + 24 + 4 + + + + + + + TIM13 + TIM13 + TIM13 + 0x40007000 + + 0x0 + 0x400 + registers + + + + TIM13_CR1 + TIM13_CR1 + TIM13 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM13_DIER + TIM13_DIER + TIM13 Interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + + + TIM13_SR + TIM13_SR + TIM13 status register + 0x10 + 0x10 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + + + TIM13_EGR + TIM13_EGR + TIM13 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + + + TIM13_CCMR1 + TIM13_CCMR1 + The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + OC1FE + OC1FE + 2 + 1 + + + OC1PE + OC1PE + 3 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1M3 + OC1M3 + 16 + 1 + + + + + TIM13_CCER + TIM13_CCER + TIM13 capture/compare enable register + 0x20 + 0x10 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + + + TIM13_CNT + TIM13_CNT + TIM13 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + + + UIFCPY + UIFCPY + 31 + 1 + + + + + TIM13_PSC + TIM13_PSC + TIM13 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM13_ARR + TIM13_ARR + TIM13 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM13_CCR1 + TIM13_CCR1 + TIM13 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM13_TISEL + TIM13_TISEL + TIM13 timer input selection register + 0x68 + 0x10 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + + + + + + + TIM14 + TIM14 + TIM14 + 0x40008000 + + 0x0 + 0x400 + registers + + + + TIM14_CR1 + TIM14_CR1 + TIM14 control register 1 + 0x0 + 0x10 + read-write + 0x00000000 + + + CEN + CEN + 0 + 1 + + + UDIS + UDIS + 1 + 1 + + + URS + URS + 2 + 1 + + + OPM + OPM + 3 + 1 + + + ARPE + ARPE + 7 + 1 + + + CKD + CKD + 8 + 2 + + + UIFREMAP + UIFREMAP + 11 + 1 + + + + + TIM14_DIER + TIM14_DIER + TIM14 Interrupt enable register + 0xC + 0x10 + read-write + 0x00000000 + + + UIE + UIE + 0 + 1 + + + CC1IE + CC1IE + 1 + 1 + + + + + TIM14_SR + TIM14_SR + TIM14 status register + 0x10 + 0x10 + read-write + 0x00000000 + + + UIF + UIF + 0 + 1 + + + CC1IF + CC1IF + 1 + 1 + + + CC1OF + CC1OF + 9 + 1 + + + + + TIM14_EGR + TIM14_EGR + TIM14 event generation register + 0x14 + 0x10 + write-only + 0x00000000 + + + UG + UG + 0 + 1 + + + CC1G + CC1G + 1 + 1 + + + + + TIM14_CCMR1 + TIM14_CCMR1 + The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S + 0 + 2 + + + OC1FE + OC1FE + 2 + 1 + + + OC1PE + OC1PE + 3 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1M3 + OC1M3 + 16 + 1 + + + + + TIM14_CCER + TIM14_CCER + TIM14 capture/compare enable register + 0x20 + 0x10 + read-write + 0x00000000 + + + CC1E + CC1E + 0 + 1 + + + CC1P + CC1P + 1 + 1 + + + CC1NP + CC1NP + 3 + 1 + + + + + TIM14_CNT + TIM14_CNT + TIM14 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + + + UIFCPY + UIFCPY + 31 + 1 + + + + + TIM14_PSC + TIM14_PSC + TIM14 prescaler + 0x28 + 0x10 + read-write + 0x00000000 + + + PSC + PSC + 0 + 16 + + + + + TIM14_ARR + TIM14_ARR + TIM14 auto-reload register + 0x2C + 0x10 + read-write + 0x0000FFFF + + + ARR + ARR + 0 + 16 + + + + + TIM14_CCR1 + TIM14_CCR1 + TIM14 capture/compare register 1 + 0x34 + 0x10 + read-write + 0x00000000 + + + CCR1 + CCR1 + 0 + 16 + + + + + TIM14_TISEL + TIM14_TISEL + TIM14 timer input selection register + 0x68 + 0x10 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + + + + + + + I2C2 + I2C2 + I2C2_IPXACT + 0x40013000 + + 0x0 + 0x400 + registers + + + + I2C_CR1 + I2C_CR1 + Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + PE + 0 + 1 + + + TXIE + TXIE + 1 + 1 + + + RXIE + RXIE + 2 + 1 + + + ADDRIE + ADDRIE + 3 + 1 + + + NACKIE + NACKIE + 4 + 1 + + + STOPIE + STOPIE + 5 + 1 + + + TCIE + TCIE + 6 + 1 + + + ERRIE + ERRIE + 7 + 1 + + + DNF + DNF + 8 + 4 + + + ANFOFF + ANFOFF + 12 + 1 + + + TXDMAEN + TXDMAEN + 14 + 1 + + + RXDMAEN + RXDMAEN + 15 + 1 + + + SBC + SBC + 16 + 1 + + + NOSTRETCH + NOSTRETCH + 17 + 1 + + + WUPEN + WUPEN + 18 + 1 + + + GCEN + GCEN + 19 + 1 + + + SMBHEN + SMBHEN + 20 + 1 + + + SMBDEN + SMBDEN + 21 + 1 + + + ALERTEN + ALERTEN + 22 + 1 + + + PECEN + PECEN + 23 + 1 + + + + + I2C_CR2 + I2C_CR2 + Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. + 0x4 + 0x20 + read-write + 0x00000000 + + + SADD + SADD + 0 + 10 + + + RD_WRN + RD_WRN + 10 + 1 + + + ADD10 + ADD10 + 11 + 1 + + + HEAD10R + HEAD10R + 12 + 1 + + + START + START + 13 + 1 + + + STOP + STOP + 14 + 1 + + + NACK + NACK + 15 + 1 + + + NBYTES + NBYTES + 16 + 8 + + + RELOAD + RELOAD + 24 + 1 + + + AUTOEND + AUTOEND + 25 + 1 + + + PECBYTE + PECBYTE + 26 + 1 + + + + + I2C_OAR1 + I2C_OAR1 + Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + OA1 + 0 + 10 + + + OA1MODE + OA1MODE + 10 + 1 + + + OA1EN + OA1EN + 15 + 1 + + + + + I2C_OAR2 + I2C_OAR2 + Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + OA2 + 1 + 7 + + + OA2MSK + OA2MSK + 8 + 3 + + + OA2EN + OA2EN + 15 + 1 + + + + + I2C_TIMINGR + I2C_TIMINGR + Access: No wait states + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCLL + 0 + 8 + + + SCLH + SCLH + 8 + 8 + + + SDADEL + SDADEL + 16 + 4 + + + SCLDEL + SCLDEL + 20 + 4 + + + PRESC + PRESC + 28 + 4 + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + TIMEOUTA + 0 + 12 + + + TIDLE + TIDLE + 12 + 1 + + + TIMOUTEN + TIMOUTEN + 15 + 1 + + + TIMEOUTB + TIMEOUTB + 16 + 12 + + + TEXTEN + TEXTEN + 31 + 1 + + + + + I2C_ISR + I2C_ISR + Access: No wait states + 0x18 + 0x20 + 0x00000001 + + + TXE + TXE + 0 + 1 + read-write + + + TXIS + TXIS + 1 + 1 + read-write + + + RXNE + RXNE + 2 + 1 + read-only + + + ADDR + ADDR + 3 + 1 + read-only + + + NACKF + NACKF + 4 + 1 + read-only + + + STOPF + STOPF + 5 + 1 + read-only + + + TC + TC + 6 + 1 + read-only + + + TCR + TCR + 7 + 1 + read-only + + + BERR + BERR + 8 + 1 + read-only + + + ARLO + ARLO + 9 + 1 + read-only + + + OVR + OVR + 10 + 1 + read-only + + + PECERR + PECERR + 11 + 1 + read-only + + + TIMEOUT + TIMEOUT + 12 + 1 + read-only + + + ALERT + ALERT + 13 + 1 + read-only + + + BUSY + BUSY + 15 + 1 + read-only + + + DIR + DIR + 16 + 1 + read-only + + + ADDCODE + ADDCODE + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + Access: No wait states + 0x1C + 0x20 + write-only + 0x00000000 + + + ADDRCF + ADDRCF + 3 + 1 + + + NACKCF + NACKCF + 4 + 1 + + + STOPCF + STOPCF + 5 + 1 + + + BERRCF + BERRCF + 8 + 1 + + + ARLOCF + ARLOCF + 9 + 1 + + + OVRCF + OVRCF + 10 + 1 + + + PECCF + PECCF + 11 + 1 + + + TIMOUTCF + TIMOUTCF + 12 + 1 + + + ALERTCF + ALERTCF + 13 + 1 + + + + + I2C_PECR + I2C_PECR + Access: No wait states + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + PEC + 0 + 8 + + + + + I2C_RXDR + I2C_RXDR + Access: No wait states + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + I2C_TXDR + I2C_TXDR + Access: No wait states + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + I2C_HWCFGR + I2C_HWCFGR + I2C hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000111 + + + SMBUS + SMBUS + 0 + 4 + + + ASYN + ASYN + 4 + 4 + + + WKP + WKP + 8 + 4 + + + + + I2C_VERR + I2C_VERR + I2C version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + I2C_IPIDR + I2C_IPIDR + I2C identification register + 0x3F8 + 0x20 + read-only + 0x00130012 + + + ID + ID + 0 + 32 + + + + + I2C_SIDR + I2C_SIDR + I2C size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + I2C1 + 0x40012000 + + + I2C3 + 0x40014000 + + + I2C4 + 0x5C002000 + + + I2C5 + 0x40015000 + + + I2C6 + 0x5C009000 + + + RTC + RTC + RTC + 0x5C004000 + + 0x0 + 0x400 + registers + + + RTC_WKUP_ALARM + RTC Tamper or TimeStamp + 3 + + + RTC_WKUP_ALARM_S + RTC wakeup timer and alarms (A and B) secure interrupt + 198 + + + RTC_TS + RTC timestamp interrupt + 41 + + + RTC_TS_S + RTC timestamp secure interrupt + 199 + + + + RTC_TR + RTC_TR + The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x0 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + + + RTC_DR + RTC_DR + The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x4 + 0x20 + read-write + 0x00002101 + + + DU + DU + 0 + 4 + + + DT + DT + 4 + 2 + + + MU + MU + 8 + 4 + + + MT + MT + 12 + 1 + + + WDU + WDU + 13 + 3 + + + YU + YU + 16 + 4 + + + YT + YT + 20 + 4 + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + SS + 0 + 16 + + + + + RTC_ICSR + RTC_ICSR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0xC + 0x20 + 0x00000007 + + + ALRAWF + ALRAWF + 0 + 1 + read-only + + + ALRBWF + ALRBWF + 1 + 1 + read-only + + + WUTWF + WUTWF + 2 + 1 + read-only + + + SHPF + SHPF + 3 + 1 + read-only + + + INITS + INITS + 4 + 1 + read-only + + + RSF + RSF + 5 + 1 + read-write + + + INITF + INITF + 6 + 1 + read-only + + + INIT + INIT + 7 + 1 + read-write + + + RECALPF + RECALPF + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + PREDIV_S + 0 + 15 + + + PREDIV_A + PREDIV_A + 16 + 7 + + + + + RTC_WUTR + RTC_WUTR + This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + WUT + 0 + 16 + + + + + RTC_CR + RTC_CR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x18 + 0x20 + 0x00000000 + + + WUCKSEL + WUCKSEL + 0 + 3 + read-write + + + TSEDGE + TSEDGE + 3 + 1 + read-write + + + REFCKON + REFCKON + 4 + 1 + read-write + + + BYPSHAD + BYPSHAD + 5 + 1 + read-write + + + FMT + FMT + 6 + 1 + read-write + + + ALRAE + ALRAE + 8 + 1 + read-write + + + ALRBE + ALRBE + 9 + 1 + read-write + + + WUTE + WUTE + 10 + 1 + read-write + + + TSE + TSE + 11 + 1 + read-write + + + ALRAIE + ALRAIE + 12 + 1 + read-write + + + ALRBIE + ALRBIE + 13 + 1 + read-write + + + WUTIE + WUTIE + 14 + 1 + read-write + + + TSIE + TSIE + 15 + 1 + read-write + + + ADD1H + ADD1H + 16 + 1 + write-only + + + SUB1H + SUB1H + 17 + 1 + write-only + + + BKP + BKP + 18 + 1 + read-write + + + COSEL + COSEL + 19 + 1 + read-write + + + POL + POL + 20 + 1 + read-write + + + OSEL + OSEL + 21 + 2 + read-write + + + COE + COE + 23 + 1 + read-write + + + ITSE + ITSE + 24 + 1 + read-write + + + TAMPTS + TAMPTS + 25 + 1 + read-write + + + TAMPOE + TAMPOE + 26 + 1 + read-write + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + read-write + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + read-write + + + OUT2EN + OUT2EN + 31 + 1 + read-write + + + + + RTC_SMCR + RTC_SMCR + This register can be written only when the APB access is secure. + 0x20 + 0x20 + read-write + 0x0000E00F + + + ALRADPROT + ALRADPROT + 0 + 1 + + + ALRBDPROT + ALRBDPROT + 1 + 1 + + + WUTDPROT + WUTDPROT + 2 + 1 + + + TSDPROT + TSDPROT + 3 + 1 + + + CALDPROT + CALDPROT + 13 + 1 + + + INITDPROT + INITDPROT + 14 + 1 + + + DECPROT + DECPROT + 15 + 1 + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + KEY + 0 + 8 + + + + + RTC_CALR + RTC_CALR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x28 + 0x20 + read-write + 0x00000000 + + + CALM + CALM + 0 + 9 + + + CALW16 + CALW16 + 13 + 1 + + + CALW8 + CALW8 + 14 + 1 + + + CALP + CALP + 15 + 1 + + + + + RTC_SHIFTR + RTC_SHIFTR + This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x2C + 0x20 + write-only + 0x00000000 + + + SUBFS + SUBFS + 0 + 15 + + + ADD1S + ADD1S + 31 + 1 + + + + + RTC_TSTR + RTC_TSTR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + + + RTC_TSDR + RTC_TSDR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x34 + 0x20 + read-only + 0x00000000 + + + DU + DU + 0 + 4 + + + DT + DT + 4 + 2 + + + MU + MU + 8 + 4 + + + MT + MT + 12 + 1 + + + WDU + WDU + 13 + 3 + + + + + RTC_TSSSR + RTC_TSSSR + The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + SS + 0 + 16 + + + + + RTC_ALRMAR + RTC_ALRMAR + This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x40 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MSK1 + MSK1 + 7 + 1 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + MSK2 + MSK2 + 15 + 1 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + MSK3 + MSK3 + 23 + 1 + + + DU + DU + 24 + 4 + + + DT + DT + 28 + 2 + + + WDSEL + WDSEL + 30 + 1 + + + MSK4 + MSK4 + 31 + 1 + + + + + RTC_ALRMASSR + RTC_ALRMASSR + This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + SS + 0 + 15 + + + MASKSS + MASKSS + 24 + 4 + + + + + RTC_ALRMBR + RTC_ALRMBR + This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x48 + 0x20 + read-write + 0x00000000 + + + SU + SU + 0 + 4 + + + ST + ST + 4 + 3 + + + MSK1 + MSK1 + 7 + 1 + + + MNU + MNU + 8 + 4 + + + MNT + MNT + 12 + 3 + + + MSK2 + MSK2 + 15 + 1 + + + HU + HU + 16 + 4 + + + HT + HT + 20 + 2 + + + PM + PM + 22 + 1 + + + MSK3 + MSK3 + 23 + 1 + + + DU + DU + 24 + 4 + + + DT + DT + 28 + 2 + + + WDSEL + WDSEL + 30 + 1 + + + MSK4 + MSK4 + 31 + 1 + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x4C + 0x20 + read-write + 0x00000000 + + + SS + SS + 0 + 15 + + + MASKSS + MASKSS + 24 + 4 + + + + + RTC_SR + RTC_SR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + RTC_MISR + RTC_MISR + RTC non-secure masked interrupt status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + RTC_SMISR + RTC_SMISR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x58 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + RTC_SCR + RTC_SCR + This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + RTC_CFGR + RTC_CFGR + RTC configuration register + 0x60 + 0x20 + read-write + 0x00000000 + + + OUT2_RMP + OUT2_RMP + 0 + 1 + + + LSCOEN + LSCOEN + 1 + 2 + + + + + RTC_HWCFGR + RTC_HWCFGR + RTC hardware configuration register + 0x3F0 + 0x20 + read-only + 0x01031111 + + + ALARMB + ALARMB + 0 + 4 + + + WAKEUP + WAKEUP + 4 + 4 + + + SMOOTH_CALIB + SMOOTH_CALIB + 8 + 4 + + + TIMESTAMP + TIMESTAMP + 12 + 4 + + + OPTIONREG_OUT + OPTIONREG_OUT + 16 + 8 + + + TRUST_ZONE + TRUST_ZONE + 24 + 4 + + + + + RTC_VERR + RTC_VERR + RTC version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + RTC_IPIDR + RTC_IPIDR + RTC identification register + 0x3F8 + 0x20 + read-only + 0x00120033 + + + ID + ID + 0 + 32 + + + + + RTC_SIDR + RTC_SIDR + RTC size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + TAMP + TAMP + TAMP + 0x5C00A000 + + 0x0 + 0x400 + registers + + + TAMP + Tamper interrupt (include LSECSS interrupts) + 2 + + + TAMP_S + TAMP tamper secure interrupt + 197 + + + + TAMP_CR1 + TAMP_CR1 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP3E + 2 + 1 + + + ITAMP1E + ITAMP1E + 16 + 1 + + + ITAMP2E + ITAMP2E + 17 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP8E + ITAMP8E + 23 + 1 + + + + + TAMP_CR2 + TAMP_CR2 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + TAMP_FLTCR + TAMP_FLTCR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + TAMP_ATCR1 + TAMP_ATCR1 + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x10 + 0x20 + read-write + 0x00070000 + + + TAMP1AM + TAMP1AM + 0 + 1 + + + TAMP2AM + TAMP2AM + 1 + 1 + + + TAMP3AM + TAMP3AM + 2 + 1 + + + ATOSEL1 + ATOSEL1 + 8 + 2 + + + ATOSEL2 + ATOSEL2 + 10 + 2 + + + ATOSEL3 + ATOSEL3 + 12 + 2 + + + ATCKSEL + ATCKSEL + 16 + 3 + + + ATPER + ATPER + 24 + 3 + + + ATOSHARE + ATOSHARE + 30 + 1 + + + FLTEN + FLTEN + 31 + 1 + + + + + TAMP_ATSEEDR + TAMP_ATSEEDR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x14 + 0x20 + write-only + 0x00000000 + + + SEED + SEED + 0 + 32 + + + + + TAMP_ATOR + TAMP_ATOR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x18 + 0x20 + read-only + 0x00000000 + + + PRNG + PRNG + 0 + 8 + + + SEEDF + SEEDF + 14 + 1 + + + INITS + INITS + 15 + 1 + + + + + TAMP_SMCR + TAMP_SMCR + This register can be written only when the APB access is secure. + 0x20 + 0x20 + read-write + 0x80000000 + + + BKPRWDPROT + BKPRWDPROT + 0 + 8 + + + BKPWDPROT + BKPWDPROT + 16 + 8 + + + TAMPDPROT + TAMPDPROT + 31 + 1 + + + + + TAMP_IER + TAMP_IER + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP1IE + ITAMP1IE + 16 + 1 + + + ITAMP2IE + ITAMP2IE + 17 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP8IE + ITAMP8IE + 23 + 1 + + + + + TAMP_SR + TAMP_SR + This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP1F + ITAMP1F + 16 + 1 + + + ITAMP2F + ITAMP2F + 17 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP8F + ITAMP8F + 23 + 1 + + + + + TAMP_MISR + TAMP_MISR + TAMP non-secure masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP1MF + ITAMP1MF + 16 + 1 + + + ITAMP2MF + ITAMP2MF + 17 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP8MF + ITAMP8MF + 23 + 1 + + + + + TAMP_SMISR + TAMP_SMISR + TAMP secure masked interrupt status register + 0x38 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP1MF + ITAMP1MF + 16 + 1 + + + ITAMP2MF + ITAMP2MF + 17 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP8MF + ITAMP8MF + 23 + 1 + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + write-only + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP1F + CITAMP1F + 16 + 1 + + + CITAMP2F + CITAMP2F + 17 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP8F + CITAMP8F + 23 + 1 + + + + + TAMP_COUNTR + TAMP_COUNTR + TAMP monotonic counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + COUNT + COUNT + 0 + 32 + + + + + TAMP_CFGR + TAMP_CFGR + TAMP configuration register + 0x50 + 0x20 + read-write + 0x00000000 + + + OUT3_RMP + OUT3_RMP + 0 + 1 + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP9R + TAMP_BKP9R + TAMP backup 9 register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP10R + TAMP_BKP10R + TAMP backup 10 register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP11R + TAMP_BKP11R + TAMP backup 11 register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP12R + TAMP_BKP12R + TAMP backup 12 register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP13R + TAMP_BKP13R + TAMP backup 13 register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP14R + TAMP_BKP14R + TAMP backup 14 register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP15R + TAMP_BKP15R + TAMP backup 15 register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP16R + TAMP_BKP16R + TAMP backup 16 register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP17R + TAMP_BKP17R + TAMP backup 17 register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP18R + TAMP_BKP18R + TAMP backup 18 register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP19R + TAMP_BKP19R + TAMP backup 19 register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP20R + TAMP_BKP20R + TAMP backup 20 register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP21R + TAMP_BKP21R + TAMP backup 21 register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP22R + TAMP_BKP22R + TAMP backup 22 register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP23R + TAMP_BKP23R + TAMP backup 23 register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP24R + TAMP_BKP24R + TAMP backup 24 register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP25R + TAMP_BKP25R + TAMP backup 25 register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP26R + TAMP_BKP26R + TAMP backup 26 register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP27R + TAMP_BKP27R + TAMP backup 27 register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP28R + TAMP_BKP28R + TAMP backup 28 register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP29R + TAMP_BKP29R + TAMP backup 29 register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP30R + TAMP_BKP30R + TAMP backup 30 register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_BKP31R + TAMP_BKP31R + TAMP backup 31 register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + TAMP_HWCFGR2 + TAMP_HWCFGR2 + TAMP hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000101 + + + OPTIONREG_OUT + OPTIONREG_OUT + 0 + 8 + + + TRUST_ZONE + TRUST_ZONE + 8 + 4 + + + + + TAMP_HWCFGR1 + TAMP_HWCFGR1 + TAMP hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x009D1320 + + + BACKUP_REGS + BACKUP_REGS + 0 + 8 + + + TAMPER + TAMPER + 8 + 4 + + + ACTIVE_TAMPER + ACTIVE_TAMPER + 12 + 4 + + + INT_TAMPER + INT_TAMPER + 16 + 16 + + + + + TAMP_VERR + TAMP_VERR + TAMP version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + TAMP_IPIDR + TAMP_IPIDR + TAMP identification register + 0x3F8 + 0x20 + read-only + 0x00121033 + + + ID + ID + 0 + 32 + + + + + TAMP_SIDR + TAMP_SIDR + TAMP size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + STGENC + STGENC + STGENC + 0x5C008000 + + 0x0 + 0x1000 + registers + + + + STGENC_CNTCR + STGENC_CNTCR + STGENC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + HLTDBG + HLTDBG + 1 + 1 + + + + + STGENC_CNTSR + STGENC_CNTSR + STGENC status register + 0x4 + 0x20 + read-only + 0x00000000 + + + EN + EN + 0 + 1 + + + HLTDBG + HLTDBG + 1 + 1 + + + + + STGENC_CNTCVL + STGENC_CNTCVL + the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. + 0x8 + 0x20 + read-write + 0x00000000 + + + CNTCVL_L_32 + CNTCVL_L_32 + 0 + 32 + + + + + STGENC_CNTCVU + STGENC_CNTCVU + the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. + 0xC + 0x20 + read-write + 0x00000000 + + + CNTCVU_U_32 + CNTCVU_U_32 + 0 + 32 + + + + + STGENC_CNTFID0 + STGENC_CNTFID0 + the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. + 0x20 + 0x20 + read-write + 0x00000000 + + + FREQ + FREQ + 0 + 32 + + + + + STGENC_PIDR4 + STGENC_PIDR4 + STGENC peripheral ID4 register + 0xFD0 + 0x20 + read-only + 0x00000004 + + + DES_2 + DES_2 + 0 + 4 + + + SIZE + SIZE + 4 + 4 + + + + + STGENC_PIDR5 + STGENC_PIDR5 + STGENC peripheral ID5 register + 0xFD4 + 0x20 + read-only + 0x00000000 + + + PIDR5 + PIDR5 + 0 + 32 + + + + + STGENC_PIDR6 + STGENC_PIDR6 + STGENC peripheral ID6 register + 0xFD8 + 0x20 + read-only + 0x00000000 + + + PIDR6 + PIDR6 + 0 + 32 + + + + + STGENC_PIDR7 + STGENC_PIDR7 + STGENC peripheral ID7 register + 0xFDC + 0x20 + read-only + 0x00000000 + + + PIDR7 + PIDR7 + 0 + 32 + + + + + STGENC_PIDR0 + STGENC_PIDR0 + STGENC peripheral ID0 register + 0xFE0 + 0x20 + read-only + 0x00000001 + + + PART_0 + PART_0 + 0 + 8 + + + + + STGENC_PIDR1 + STGENC_PIDR1 + STGENC peripheral ID1 register + 0xFE4 + 0x20 + read-only + 0x000000B1 + + + PART_1 + PART_1 + 0 + 4 + + + DES_0 + DES_0 + 4 + 4 + + + + + STGENC_PIDR2 + STGENC_PIDR2 + STGENC peripheral ID2 register + 0xFE8 + 0x20 + read-only + 0x0000001B + + + DES_1 + DES_1 + 0 + 3 + + + JEDEC + JEDEC + 3 + 1 + + + REVISION + REVISION + 4 + 4 + + + + + STGENC_PIDR3 + STGENC_PIDR3 + STGENC peripheral ID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + CMOD + CMOD + 0 + 4 + + + REVAND + REVAND + 4 + 4 + + + + + STGENC_CIDR0 + STGENC_CIDR0 + STGENC component ID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + PRMBL_0 + PRMBL_0 + 0 + 8 + + + + + STGENC_CIDR1 + STGENC_CIDR1 + STGENC component ID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + PRMBL_1 + PRMBL_1 + 0 + 4 + + + CLASS + CLASS + 4 + 4 + + + + + STGENC_CIDR2 + STGENC_CIDR2 + STGENC component ID2 register + 0xFF8 + 0x20 + read-only + 0x00000050 + + + PRMBL_2 + PRMBL_2 + 0 + 8 + + + + + STGENC_CIDR3 + STGENC_CIDR3 + STGENC component ID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + PRMBL_3 + PRMBL_3 + 0 + 8 + + + + + + + STGENR + STGENR + STGENR + 0x5A005000 + + 0x0 + 0x1000 + registers + + + + STGENR_CNTCVL + STGENR_CNTCVL + the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. + 0x0 + 0x20 + read-only + 0x00000000 + + + CNTCVL_L_32 + CNTCVL_L_32 + 0 + 32 + + + + + STGENR_CNTCVU + STGENR_CNTCVU + the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. + 0x4 + 0x20 + read-only + 0x00000000 + + + CNTCVU_U_32 + CNTCVU_U_32 + 0 + 32 + + + + + STGENR_PIDR4 + STGENR_PIDR4 + STGENR peripheral ID4 register + 0xFD0 + 0x20 + read-only + 0x00000004 + + + DES_2 + DES_2 + 0 + 4 + + + SIZE + SIZE + 4 + 4 + + + + + STGENR_PIDR5 + STGENR_PIDR5 + STGENR peripheral ID5 register + 0xFD4 + 0x20 + read-only + 0x00000000 + + + PIDR5 + PIDR5 + 0 + 32 + + + + + STGENR_PIDR6 + STGENR_PIDR6 + STGENR peripheral ID6 register + 0xFD8 + 0x20 + read-only + 0x00000000 + + + PIDR6 + PIDR6 + 0 + 32 + + + + + STGENR_PIDR7 + STGENR_PIDR7 + STGENR peripheral ID7 register + 0xFDC + 0x20 + read-only + 0x00000000 + + + PIDR7 + PIDR7 + 0 + 32 + + + + + STGENR_PIDR0 + STGENR_PIDR0 + STGENR peripheral ID0 register + 0xFE0 + 0x20 + read-only + 0x00000001 + + + PART_0 + PART_0 + 0 + 8 + + + + + STGENR_PIDR1 + STGENR_PIDR1 + STGENR peripheral ID1 register + 0xFE4 + 0x20 + read-only + 0x000000B1 + + + PART_1 + PART_1 + 0 + 4 + + + DES_0 + DES_0 + 4 + 4 + + + + + STGENR_PIDR2 + STGENR_PIDR2 + STGENR peripheral ID2 register + 0xFE8 + 0x20 + read-only + 0x0000001B + + + DES_1 + DES_1 + 0 + 3 + + + JEDEC + JEDEC + 3 + 1 + + + REVISION + REVISION + 4 + 4 + + + + + STGENR_PIDR3 + STGENR_PIDR3 + STGENR peripheral ID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + CMOD + CMOD + 0 + 4 + + + REVAND + REVAND + 4 + 4 + + + + + STGENR_CIDR0 + STGENR_CIDR0 + STGENR component ID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + PRMBL_0 + PRMBL_0 + 0 + 8 + + + + + STGENR_CIDR1 + STGENR_CIDR1 + STGENR component ID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + PRMBL_1 + PRMBL_1 + 0 + 4 + + + CLASS + CLASS + 4 + 4 + + + + + STGENR_CIDR2 + STGENR_CIDR2 + STGENR component ID2 register + 0xFF8 + 0x20 + read-only + 0x00000050 + + + PRMBL_2 + PRMBL_2 + 0 + 8 + + + + + STGENR_CIDR3 + STGENR_CIDR3 + STGENR component ID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + PRMBL_3 + PRMBL_3 + 0 + 8 + + + + + + + ETZPC + ETZPC + ETZPC + 0x5C007000 + + 0x0 + 0x400 + registers + + + + ETZPC_TZMA0_SIZE + ETZPC_TZMA0_SIZE + ETZPC ROM secure size definition + 0x0 + 0x20 + read-write + 0x000003FF + + + R0SIZE + R0SIZE + 0 + 10 + + + LOCK + LOCK + 31 + 1 + + + + + ETZPC_TZMA1_SIZE + ETZPC_TZMA1_SIZE + ETZPC RAM secure size definition + 0x4 + 0x20 + read-write + 0x000003FF + + + R0SIZE + R0SIZE + 0 + 10 + + + LOCK + LOCK + 31 + 1 + + + + + ETZPC_DECPROT0 + ETZPC_DECPROT0 + Register reset values + 0x10 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT1 + ETZPC_DECPROT1 + Register reset values + 0x14 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT2 + ETZPC_DECPROT2 + Register reset values + 0x18 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT3 + ETZPC_DECPROT3 + Register reset values + 0x1C + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT4 + ETZPC_DECPROT4 + Register reset values + 0x20 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT5 + ETZPC_DECPROT5 + Register reset values + 0x24 + 0x20 + read-write + 0x00000000 + + + DECPROT0 + DECPROT0 + 0 + 2 + + + DECPROT1 + DECPROT1 + 2 + 2 + + + DECPROT2 + DECPROT2 + 4 + 2 + + + DECPROT3 + DECPROT3 + 6 + 2 + + + DECPROT4 + DECPROT4 + 8 + 2 + + + DECPROT5 + DECPROT5 + 10 + 2 + + + DECPROT6 + DECPROT6 + 12 + 2 + + + DECPROT7 + DECPROT7 + 14 + 2 + + + DECPROT8 + DECPROT8 + 16 + 2 + + + DECPROT9 + DECPROT9 + 18 + 2 + + + DECPROT10 + DECPROT10 + 20 + 2 + + + DECPROT11 + DECPROT11 + 22 + 2 + + + DECPROT12 + DECPROT12 + 24 + 2 + + + DECPROT13 + DECPROT13 + 26 + 2 + + + DECPROT14 + DECPROT14 + 28 + 2 + + + DECPROT15 + DECPROT15 + 30 + 2 + + + + + ETZPC_DECPROT_LOCK0 + ETZPC_DECPROT_LOCK0 + ETZPC decprot lock 0 register + 0x30 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_DECPROT_LOCK1 + ETZPC_DECPROT_LOCK1 + ETZPC decprot lock 1 register + 0x34 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_DECPROT_LOCK2 + ETZPC_DECPROT_LOCK2 + ETZPC decprot lock 2 register + 0x38 + 0x20 + read-write + 0x00000000 + + + LOCK0 + LOCK0 + 0 + 1 + + + LOCK1 + LOCK1 + 1 + 1 + + + LOCK2 + LOCK2 + 2 + 1 + + + LOCK3 + LOCK3 + 3 + 1 + + + LOCK4 + LOCK4 + 4 + 1 + + + LOCK5 + LOCK5 + 5 + 1 + + + LOCK6 + LOCK6 + 6 + 1 + + + LOCK7 + LOCK7 + 7 + 1 + + + LOCK8 + LOCK8 + 8 + 1 + + + LOCK9 + LOCK9 + 9 + 1 + + + LOCK10 + LOCK10 + 10 + 1 + + + LOCK11 + LOCK11 + 11 + 1 + + + LOCK12 + LOCK12 + 12 + 1 + + + LOCK13 + LOCK13 + 13 + 1 + + + LOCK14 + LOCK14 + 14 + 1 + + + LOCK15 + LOCK15 + 15 + 1 + + + LOCK16 + LOCK16 + 16 + 1 + + + LOCK17 + LOCK17 + 17 + 1 + + + LOCK18 + LOCK18 + 18 + 1 + + + LOCK19 + LOCK19 + 19 + 1 + + + LOCK20 + LOCK20 + 20 + 1 + + + LOCK21 + LOCK21 + 21 + 1 + + + LOCK22 + LOCK22 + 22 + 1 + + + LOCK23 + LOCK23 + 23 + 1 + + + LOCK24 + LOCK24 + 24 + 1 + + + LOCK25 + LOCK25 + 25 + 1 + + + LOCK26 + LOCK26 + 26 + 1 + + + LOCK27 + LOCK27 + 27 + 1 + + + LOCK28 + LOCK28 + 28 + 1 + + + LOCK29 + LOCK29 + 29 + 1 + + + LOCK30 + LOCK30 + 30 + 1 + + + LOCK31 + LOCK31 + 31 + 1 + + + + + ETZPC_HWCFGR + ETZPC_HWCFGR + ETZPC IP HW configuration register + 0x3F0 + 0x20 + read-only + 0x00006002 + + + NUM_TZMA + NUM_TZMA + 0 + 8 + + + NUM_PER_SEC + NUM_PER_SEC + 8 + 8 + + + NUM_AHB_SEC + NUM_AHB_SEC + 16 + 8 + + + CHUNKS1N4 + CHUNKS1N4 + 24 + 8 + + + + + ETZPC_VERR + ETZPC_VERR + ETZPC IP version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + ETZPC_IDR + ETZPC_IDR + ETZPC IP version register + 0x3F8 + 0x20 + read-only + 0x00100061 + + + ID + ID + 0 + 32 + + + + + ETZPC_SIDR + ETZPC_SIDR + ETZPC IP version register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + IWDG1 + IWDG1 + IWDG1 + 0x5C003000 + + 0x0 + 0x400 + registers + + + + IWDG_KR + IWDG_KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + KEY + 0 + 16 + + + + + IWDG_PR + IWDG_PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000007 + + + PR + PR + 0 + 3 + + + + + IWDG_RLR + IWDG_RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + RL + 0 + 12 + + + + + IWDG_SR + IWDG_SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + PVU + 0 + 1 + + + RVU + RVU + 1 + 1 + + + WVU + WVU + 2 + 1 + + + + + IWDG_WINR + IWDG_WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + WIN + 0 + 12 + + + + + IWDG_HWCFGR + IWDG_HWCFGR + IWDG hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000071 + + + WINDOW + WINDOW + 0 + 4 + + + PR_DEFAULT + PR_DEFAULT + 4 + 4 + + + + + IWDG_VERR + IWDG_VERR + IWDG version register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + IWDG_IDR + IWDG_IDR + IWDG identification register + 0x3F8 + 0x20 + read-only + 0x00120041 + + + ID + ID + 0 + 32 + + + + + IWDG_SIDR + IWDG_SIDR + IWDG size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + IWDG2 + 0x5A002000 + + + SPI1 + SPI1 + SPI1 + 0x44004000 + + 0x0 + 0x400 + registers + + + + SPI2S_CR1 + SPI2S_CR1 + SPI/I2S control register 1 + 0x0 + 0x20 + 0x00000000 + + + SPE + SPE + 0 + 1 + read-write + + + MASRX + MASRX + 8 + 1 + read-write + + + CSTART + CSTART + 9 + 1 + read-write + + + CSUSP + CSUSP + 10 + 1 + write-only + + + HDDIR + HDDIR + 11 + 1 + read-write + + + SSI + SSI + 12 + 1 + read-write + + + CRC33_17 + CRC33_17 + 13 + 1 + read-write + + + RCRCINI + RCRCINI + 14 + 1 + read-write + + + TCRCINI + TCRCINI + 15 + 1 + read-write + + + IOLOCK + IOLOCK + 16 + 1 + read-write + + + + + SPI2S_IER + SPI2S_IER + SPI/I2S interrupt enable register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXPIE + RXPIE + 0 + 1 + + + TXPIE + TXPIE + 1 + 1 + + + DXPIE + DXPIE + 2 + 1 + + + EOTIE + EOTIE + 3 + 1 + + + TXTFIE + TXTFIE + 4 + 1 + + + UDRIE + UDRIE + 5 + 1 + + + OVRIE + OVRIE + 6 + 1 + + + CRCEIE + CRCEIE + 7 + 1 + + + TIFREIE + TIFREIE + 8 + 1 + + + MODFIE + MODFIE + 9 + 1 + + + TSERFIE + TSERFIE + 10 + 1 + + + + + SPI2S_SR + SPI2S_SR + SPI/I2S status register + 0x14 + 0x20 + read-only + 0x00001002 + + + RXP + RXP + 0 + 1 + + + TXP + TXP + 1 + 1 + + + DXP + DXP + 2 + 1 + + + EOT + EOT + 3 + 1 + + + TXTF + TXTF + 4 + 1 + + + UDR + UDR + 5 + 1 + + + OVR + OVR + 6 + 1 + + + CRCE + CRCE + 7 + 1 + + + TIFRE + TIFRE + 8 + 1 + + + MODF + MODF + 9 + 1 + + + TSERF + TSERF + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + TXC + TXC + 12 + 1 + + + RXPLVL + RXPLVL + 13 + 2 + + + RXWNE + RXWNE + 15 + 1 + + + CTSIZE + CTSIZE + 16 + 16 + + + + + SPI2S_IFCR + SPI2S_IFCR + SPI/I2S interrupt/status flags clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + EOTC + EOTC + 3 + 1 + + + TXTFC + TXTFC + 4 + 1 + + + UDRC + UDRC + 5 + 1 + + + OVRC + OVRC + 6 + 1 + + + CRCEC + CRCEC + 7 + 1 + + + TIFREC + TIFREC + 8 + 1 + + + MODFC + MODFC + 9 + 1 + + + TSERFC + TSERFC + 10 + 1 + + + SUSPC + SUSPC + 11 + 1 + + + + + SPI2S_TXDR + SPI2S_TXDR + SPI/I2S transmit data register + 0x20 + 0x20 + write-only + 0x00000000 + + + TXDR + TXDR + 0 + 32 + + + + + SPI2S_RXDR + SPI2S_RXDR + SPI/I2S receive data register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDR + RXDR + 0 + 32 + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TSIZE + TSIZE + 0 + 16 + + + TSER + TSER + 16 + 16 + + + + + SPI_CFG1 + SPI_CFG1 + Content of this register is write protected when SPI is enabled + 0x8 + 0x20 + read-write + 0x00070007 + + + DSIZE + DSIZE + 0 + 5 + + + FTHLV + FTHLV + 5 + 4 + + + UDRCFG + UDRCFG + 9 + 2 + + + UDRDET + UDRDET + 11 + 2 + + + RXDMAEN + RXDMAEN + 14 + 1 + + + TXDMAEN + TXDMAEN + 15 + 1 + + + CRCSIZE + CRCSIZE + 16 + 5 + + + CRCEN + CRCEN + 22 + 1 + + + MBR + MBR + 28 + 3 + + + + + SPI_CFG2 + SPI_CFG2 + The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. + 0xC + 0x20 + read-write + 0x00000000 + + + MSSI + MSSI + 0 + 4 + + + MIDI + MIDI + 4 + 4 + + + IOSWP + IOSWP + 15 + 1 + + + COMM + COMM + 17 + 2 + + + SP + SP + 19 + 3 + + + MASTER + MASTER + 22 + 1 + + + LSBFRST + LSBFRST + 23 + 1 + + + CPHA + CPHA + 24 + 1 + + + CPOL + CPOL + 25 + 1 + + + SSM + SSM + 26 + 1 + + + SSIOP + SSIOP + 28 + 1 + + + SSOE + SSOE + 29 + 1 + + + SSOM + SSOM + 30 + 1 + + + AFCNTR + AFCNTR + 31 + 1 + + + + + SPI_CRCPOLY + SPI_CRCPOLY + SPI polynomial register + 0x40 + 0x20 + read-write + 0x00000107 + + + CRCPOLY + CRCPOLY + 0 + 32 + + + + + SPI_TXCRC + SPI_TXCRC + SPI transmitter CRC register + 0x44 + 0x20 + read-only + 0x00000000 + + + TXCRC + TXCRC + 0 + 32 + + + + + SPI_RXCRC + SPI_RXCRC + SPI receiver CRC register + 0x48 + 0x20 + read-only + 0x00000000 + + + RXCRC + RXCRC + 0 + 32 + + + + + SPI_UDRDR + SPI_UDRDR + SPI underrun data register + 0x4C + 0x20 + read-write + 0x00000000 + + + UDRDR + UDRDR + 0 + 32 + + + + + SPI_I2SCFGR + SPI_I2SCFGR + All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. + 0x50 + 0x20 + read-write + 0x00000000 + + + I2SMOD + I2SMOD + 0 + 1 + + + I2SCFG + I2SCFG + 1 + 3 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + DATLEN + DATLEN + 8 + 2 + + + CHLEN + CHLEN + 10 + 1 + + + CKPOL + CKPOL + 11 + 1 + + + FIXCH + FIXCH + 12 + 1 + + + WSINV + WSINV + 13 + 1 + + + DATFMT + DATFMT + 14 + 1 + + + I2SDIV + I2SDIV + 16 + 8 + + + ODD + ODD + 24 + 1 + + + MCKOE + MCKOE + 25 + 1 + + + + + SPI_I2S_HWCFGR + SPI_I2S_HWCFGR + SPI/I2S hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000000 + + + TXFCFG + TXFCFG + 0 + 4 + + + RXFCFG + RXFCFG + 4 + 4 + + + CRCCFG + CRCCFG + 8 + 4 + + + I2SCFG + I2SCFG + 12 + 4 + + + DSCFG + DSCFG + 16 + 4 + + + + + SPI_VERR + SPI_VERR + SPI/I2S version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SPI_IPIDR + SPI_IPIDR + SPI/I2S identification register + 0x3F8 + 0x20 + read-only + 0x00130022 + + + ID + ID + 0 + 32 + + + + + SPI_SIDR + SPI_SIDR + SPI/I2S size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + + SPI2 + SPI2 + SPI2 + 0x4000B000 + + 0x0 + 0x400 + registers + + + + SPI2S_CR1 + SPI2S_CR1 + SPI/I2S control register 1 + 0x0 + 0x20 + 0x00000000 + + + SPE + SPE + 0 + 1 + read-write + + + MASRX + MASRX + 8 + 1 + read-write + + + CSTART + CSTART + 9 + 1 + read-write + + + CSUSP + CSUSP + 10 + 1 + write-only + + + HDDIR + HDDIR + 11 + 1 + read-write + + + SSI + SSI + 12 + 1 + read-write + + + CRC33_17 + CRC33_17 + 13 + 1 + read-write + + + RCRCINI + RCRCINI + 14 + 1 + read-write + + + TCRCINI + TCRCINI + 15 + 1 + read-write + + + IOLOCK + IOLOCK + 16 + 1 + read-write + + + + + SPI2S_IER + SPI2S_IER + SPI/I2S interrupt enable register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXPIE + RXPIE + 0 + 1 + + + TXPIE + TXPIE + 1 + 1 + + + DXPIE + DXPIE + 2 + 1 + + + EOTIE + EOTIE + 3 + 1 + + + TXTFIE + TXTFIE + 4 + 1 + + + UDRIE + UDRIE + 5 + 1 + + + OVRIE + OVRIE + 6 + 1 + + + CRCEIE + CRCEIE + 7 + 1 + + + TIFREIE + TIFREIE + 8 + 1 + + + MODFIE + MODFIE + 9 + 1 + + + TSERFIE + TSERFIE + 10 + 1 + + + + + SPI2S_SR + SPI2S_SR + SPI/I2S status register + 0x14 + 0x20 + read-only + 0x00001002 + + + RXP + RXP + 0 + 1 + + + TXP + TXP + 1 + 1 + + + DXP + DXP + 2 + 1 + + + EOT + EOT + 3 + 1 + + + TXTF + TXTF + 4 + 1 + + + UDR + UDR + 5 + 1 + + + OVR + OVR + 6 + 1 + + + CRCE + CRCE + 7 + 1 + + + TIFRE + TIFRE + 8 + 1 + + + MODF + MODF + 9 + 1 + + + TSERF + TSERF + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + TXC + TXC + 12 + 1 + + + RXPLVL + RXPLVL + 13 + 2 + + + RXWNE + RXWNE + 15 + 1 + + + CTSIZE + CTSIZE + 16 + 16 + + + + + SPI2S_IFCR + SPI2S_IFCR + SPI/I2S interrupt/status flags clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + EOTC + EOTC + 3 + 1 + + + TXTFC + TXTFC + 4 + 1 + + + UDRC + UDRC + 5 + 1 + + + OVRC + OVRC + 6 + 1 + + + CRCEC + CRCEC + 7 + 1 + + + TIFREC + TIFREC + 8 + 1 + + + MODFC + MODFC + 9 + 1 + + + TSERFC + TSERFC + 10 + 1 + + + SUSPC + SUSPC + 11 + 1 + + + + + SPI2S_TXDR + SPI2S_TXDR + SPI/I2S transmit data register + 0x20 + 0x20 + write-only + 0x00000000 + + + TXDR + TXDR + 0 + 32 + + + + + SPI2S_RXDR + SPI2S_RXDR + SPI/I2S receive data register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDR + RXDR + 0 + 32 + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TSIZE + TSIZE + 0 + 16 + + + TSER + TSER + 16 + 16 + + + + + SPI_CFG1 + SPI_CFG1 + Content of this register is write protected when SPI is enabled + 0x8 + 0x20 + read-write + 0x00070007 + + + DSIZE + DSIZE + 0 + 5 + + + FTHLV + FTHLV + 5 + 4 + + + UDRCFG + UDRCFG + 9 + 2 + + + UDRDET + UDRDET + 11 + 2 + + + RXDMAEN + RXDMAEN + 14 + 1 + + + TXDMAEN + TXDMAEN + 15 + 1 + + + CRCSIZE + CRCSIZE + 16 + 5 + + + CRCEN + CRCEN + 22 + 1 + + + MBR + MBR + 28 + 3 + + + + + SPI_CFG2 + SPI_CFG2 + The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. + 0xC + 0x20 + read-write + 0x00000000 + + + MSSI + MSSI + 0 + 4 + + + MIDI + MIDI + 4 + 4 + + + IOSWP + IOSWP + 15 + 1 + + + COMM + COMM + 17 + 2 + + + SP + SP + 19 + 3 + + + MASTER + MASTER + 22 + 1 + + + LSBFRST + LSBFRST + 23 + 1 + + + CPHA + CPHA + 24 + 1 + + + CPOL + CPOL + 25 + 1 + + + SSM + SSM + 26 + 1 + + + SSIOP + SSIOP + 28 + 1 + + + SSOE + SSOE + 29 + 1 + + + SSOM + SSOM + 30 + 1 + + + AFCNTR + AFCNTR + 31 + 1 + + + + + SPI_CRCPOLY + SPI_CRCPOLY + SPI polynomial register + 0x40 + 0x20 + read-write + 0x00000107 + + + CRCPOLY + CRCPOLY + 0 + 32 + + + + + SPI_TXCRC + SPI_TXCRC + SPI transmitter CRC register + 0x44 + 0x20 + read-only + 0x00000000 + + + TXCRC + TXCRC + 0 + 32 + + + + + SPI_RXCRC + SPI_RXCRC + SPI receiver CRC register + 0x48 + 0x20 + read-only + 0x00000000 + + + RXCRC + RXCRC + 0 + 32 + + + + + SPI_UDRDR + SPI_UDRDR + SPI underrun data register + 0x4C + 0x20 + read-write + 0x00000000 + + + UDRDR + UDRDR + 0 + 32 + + + + + SPI_I2SCFGR + SPI_I2SCFGR + All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. + 0x50 + 0x20 + read-write + 0x00000000 + + + I2SMOD + I2SMOD + 0 + 1 + + + I2SCFG + I2SCFG + 1 + 3 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + DATLEN + DATLEN + 8 + 2 + + + CHLEN + CHLEN + 10 + 1 + + + CKPOL + CKPOL + 11 + 1 + + + FIXCH + FIXCH + 12 + 1 + + + WSINV + WSINV + 13 + 1 + + + DATFMT + DATFMT + 14 + 1 + + + I2SDIV + I2SDIV + 16 + 8 + + + ODD + ODD + 24 + 1 + + + MCKOE + MCKOE + 25 + 1 + + + + + SPI_I2S_HWCFGR + SPI_I2S_HWCFGR + SPI/I2S hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000000 + + + TXFCFG + TXFCFG + 0 + 4 + + + RXFCFG + RXFCFG + 4 + 4 + + + CRCCFG + CRCCFG + 8 + 4 + + + I2SCFG + I2SCFG + 12 + 4 + + + DSCFG + DSCFG + 16 + 4 + + + + + SPI_VERR + SPI_VERR + SPI/I2S version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SPI_IPIDR + SPI_IPIDR + SPI/I2S identification register + 0x3F8 + 0x20 + read-only + 0x00130022 + + + ID + ID + 0 + 32 + + + + + SPI_SIDR + SPI_SIDR + SPI/I2S size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + + SPI3 + 0x4000C000 + + + SPI4 + 0x44005000 + + + SPI5 + 0x44009000 + + + SPI6 + 0x5C001000 + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x5C000000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT + DEAT + 21 + 5 + + + DEDT + DEDT + 16 + 5 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD + Auto baud rate mode + 21 + 2 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + When the DSI_NSS bit is set, the NSS pin input will be ignored + 3 + 1 + + + SLVEN + Synchronous Slave mode enable + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold configuration + 25 + 3 + + + TCBGTIE + Tr Complete before guard time, interrupt enable + 24 + 1 + + + TXFTIE + threshold interrupt enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR_4_15 + BRR_4_15 + 4 + 12 + + + BRR_0_3 + BRR_0_3 + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + SPI slave underrun clear flag + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + Transmission complete before Guard time clear flag + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFIFO empty clear flag + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + HWCFGR2 + HWCFGR2 + USART Hardware Configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000014 + + + CFG1 + CFG1 + 0 + 4 + + + CFG2 + CFG2 + 4 + 4 + + + + + HWCFGR1 + HWCFGR1 + USART Hardware Configuration register 1 + 0x3F0 + 0x20 + read-only + 0x00000014 + + + CFG1 + CFG1 + 0 + 4 + + + CFG2 + CFG2 + 4 + 4 + + + CFG3 + CFG3 + 8 + 4 + + + CFG4 + CFG4 + 12 + 4 + + + CFG5 + CFG5 + 16 + 4 + + + CFG6 + CFG6 + 20 + 4 + + + CFG7 + CFG7 + 24 + 4 + + + CFG8 + CFG8 + 28 + 4 + + + + + VERR + VERR + EXTI IP Version register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + MINREV + Minor Revision number + 0 + 4 + + + MAJREV + Major Revision number + 4 + 4 + + + + + IPIDR + IPIDR + EXTI Identification register + 0x3F8 + 0x20 + read-only + 0x00130003 + + + IPID + IP Identification + 0 + 32 + + + + + SIDR + SIDR + EXTI Size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size Identification + 0 + 32 + + + + + + + USART2 + 0x4000E000 + + + USART3 + 0x4000F000 + + + UART4 + 0x40010000 + + + UART5 + 0x40011000 + + + USART6 + 0x44003000 + + + UART7 + 0x40018000 + + + UART8 + 0x40019000 + + + LTDC + LTDC + LTDC + 0x5A001000 + + 0x0 + 0x400 + registers + + + + LTDC_IDR + LTDC_IDR + LTDC identification register + 0x0 + 0x20 + read-only + 0x00010300 + + + REV + REV + 0 + 8 + + + MINVER + MINVER + 8 + 8 + + + MAJVER + MAJVER + 16 + 8 + + + + + LTDC_LCR + LTDC_LCR + LDTC layer count register + 0x4 + 0x20 + read-only + 0x00000002 + + + LNBR + LNBR + 0 + 8 + + + + + LTDC_SSCR + LTDC_SSCR + This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. + 0x8 + 0x20 + read-write + 0x00000000 + + + VSH + VSH + 0 + 12 + + + HSW + HSW + 16 + 12 + + + + + LTDC_BPCR + LTDC_BPCR + This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. + 0xC + 0x20 + read-write + 0x00000000 + + + AVBP + AVBP + 0 + 12 + + + AHBP + AHBP + 16 + 12 + + + + + LTDC_AWCR + LTDC_AWCR + This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. + 0x10 + 0x20 + read-write + 0x00000000 + + + AAH + AAH + 0 + 12 + + + AAW + AAW + 16 + 12 + + + + + LTDC_TWCR + LTDC_TWCR + This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALH + TOTALH + 0 + 12 + + + TOTALW + TOTALW + 16 + 12 + + + + + LTDC_GCR + LTDC_GCR + This register defines the global configuration of the LCD-TFT controller. + 0x18 + 0x20 + 0x00002220 + + + LTDCEN + LTDCEN + 0 + 1 + read-write + + + DBW + DBW + 4 + 3 + read-only + + + DGW + DGW + 8 + 3 + read-only + + + DRW + DRW + 12 + 3 + read-only + + + DEN + DEN + 16 + 1 + read-write + + + PCPOL + PCPOL + 28 + 1 + read-write + + + DEPOL + DEPOL + 29 + 1 + read-write + + + VSPOL + VSPOL + 30 + 1 + read-write + + + HSPOL + HSPOL + 31 + 1 + read-write + + + + + LTDC_GC1R + LTDC_GC1R + LTDC global configuration 1 register + 0x1C + 0x20 + read-only + 0x6BE2D888 + + + WBCH + WBCH + 0 + 4 + + + WGCH + WGCH + 4 + 4 + + + WRCH + WRCH + 8 + 4 + + + PRBEN + PRBEN + 12 + 1 + + + DT + DT + 14 + 2 + + + GCT + GCT + 17 + 3 + + + SHREN + SHREN + 21 + 1 + + + BCP + BCP + 22 + 1 + + + BBEN + BBEN + 23 + 1 + + + LNIP + LNIP + 24 + 1 + + + TP + TP + 25 + 1 + + + IPP + IPP + 26 + 1 + + + SPP + SPP + 27 + 1 + + + DWP + DWP + 28 + 1 + + + STREN + STREN + 29 + 1 + + + BMEN + BMEN + 31 + 1 + + + + + LTDC_GC2R + LTDC_GC2R + LTDC global configuration 2 register + 0x20 + 0x20 + read-only + 0x00000030 + + + EDCEN + EDCEN + 0 + 1 + + + STSAEN + STSAEN + 1 + 1 + + + DVAEN + DVAEN + 2 + 1 + + + DPAEN + DPAEN + 3 + 1 + + + BW + BW + 4 + 3 + + + EDCA + EDCA + 7 + 1 + + + + + LTDC_SRCR + LTDC_SRCR + This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. + 0x24 + 0x20 + read-write + 0x00000000 + + + IMR + IMR + 0 + 1 + + + VBR + VBR + 1 + 1 + + + + + LTDC_BCCR + LTDC_BCCR + This register defines the background color (RGB888). + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + BCBLUE + 0 + 8 + + + BCGREEN + BCGREEN + 8 + 8 + + + BCRED + BCRED + 16 + 8 + + + + + LTDC_IER + LTDC_IER + This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. + 0x34 + 0x20 + read-write + 0x00000000 + + + LIE + LIE + 0 + 1 + + + FUIE + FUIE + 1 + 1 + + + TERRIE + TERRIE + 2 + 1 + + + RRIE + RRIE + 3 + 1 + + + + + LTDC_ISR + LTDC_ISR + This register returns the interrupt status flag. + 0x38 + 0x20 + read-only + 0x00000000 + + + LIF + LIF + 0 + 1 + + + FUIF + FUIF + 1 + 1 + + + TERRIF + TERRIF + 2 + 1 + + + RRIF + RRIF + 3 + 1 + + + + + LTDC_ICR + LTDC_ICR + LTDC Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CLIF + CLIF + 0 + 1 + + + CFUIF + CFUIF + 1 + 1 + + + CTERRIF + CTERRIF + 2 + 1 + + + CRRIF + CRRIF + 3 + 1 + + + + + LTDC_LIPCR + LTDC_LIPCR + This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274. + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + LIPOS + 0 + 12 + + + + + LTDC_CPSR + LTDC_CPSR + LTDC current position status register + 0x44 + 0x20 + read-only + 0x00000000 + + + CYPOS + CYPOS + 0 + 16 + + + CXPOS + CXPOS + 16 + 16 + + + + + LTDC_CDSR + LTDC_CDSR + This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. + 0x48 + 0x20 + read-only + 0x0000000F + + + VDES + VDES + 0 + 1 + + + HDES + HDES + 1 + 1 + + + VSYNCS + VSYNCS + 2 + 1 + + + HSYNCS + HSYNCS + 3 + 1 + + + + + LTDC_L1CR + LTDC_L1CR + LTDC layer 1 control register + 0x84 + 0x20 + read-write + 0x00000000 + + + LEN + LEN + 0 + 1 + + + COLKEN + COLKEN + 1 + 1 + + + CLUTEN + CLUTEN + 4 + 1 + + + + + LTDC_L1WHPCR + LTDC_L1WHPCR + This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. + 0x88 + 0x20 + read-write + 0x00000000 + + + WHSTPOS + WHSTPOS + 0 + 12 + + + WHSPPOS + WHSPPOS + 16 + 12 + + + + + LTDC_L1WVPCR + LTDC_L1WVPCR + This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. + 0x8C + 0x20 + read-write + 0x00000000 + + + WVSTPOS + WVSTPOS + 0 + 12 + + + WVSPPOS + WVSPPOS + 16 + 12 + + + + + LTDC_L1CKCR + LTDC_L1CKCR + This register defines the color key value (RGB), that is used by the color keying. + 0x90 + 0x20 + read-write + 0x00000000 + + + CKBLUE + CKBLUE + 0 + 8 + + + CKGREEN + CKGREEN + 8 + 8 + + + CKRED + CKRED + 16 + 8 + + + + + LTDC_L1PFCR + LTDC_L1PFCR + This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). + 0x94 + 0x20 + read-write + 0x00000000 + + + PF + PF + 0 + 3 + + + + + LTDC_L1CACR + LTDC_L1CACR + This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. + 0x98 + 0x20 + read-write + 0x000000FF + + + CONSTA + CONSTA + 0 + 8 + + + + + LTDC_L1DCCR + LTDC_L1DCCR + This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. + 0x9C + 0x20 + read-write + 0x00000000 + + + DCBLUE + DCBLUE + 0 + 8 + + + DCGREEN + DCGREEN + 8 + 8 + + + DCRED + DCRED + 16 + 8 + + + DCALPHA + DCALPHA + 24 + 8 + + + + + LTDC_L1BFCR + LTDC_L1BFCR + This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color + 0xA0 + 0x20 + read-write + 0x00000607 + + + BF2 + BF2 + 0 + 3 + + + BF1 + BF1 + 8 + 3 + + + + + LTDC_L1CFBAR + LTDC_L1CFBAR + This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. + 0xAC + 0x20 + read-write + 0x00000000 + + + CFBADD + CFBADD + 0 + 32 + + + + + LTDC_L1CFBLR + LTDC_L1CFBLR + This register defines the color frame buffer line length and pitch. + 0xB0 + 0x20 + read-write + 0x00000000 + + + CFBLL + CFBLL + 0 + 14 + + + CFBP + CFBP + 16 + 14 + + + + + LTDC_L1CFBLNR + LTDC_L1CFBLNR + This register defines the number of lines in the color frame buffer. + 0xB4 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + CFBLNBR + 0 + 12 + + + + + LTDC_L1CLUTWR + LTDC_L1CLUTWR + This register defines the CLUT address and the RGB value. + 0xC4 + 0x20 + write-only + 0x00000000 + + + BLUE + BLUE + 0 + 8 + + + GREEN + GREEN + 8 + 8 + + + RED + RED + 16 + 8 + + + CLUTADD + CLUTADD + 24 + 8 + + + + + LTDC_L2CR + LTDC_L2CR + LTDC layer 2 control register + 0x104 + 0x20 + read-write + 0x00000000 + + + LEN + LEN + 0 + 1 + + + COLKEN + COLKEN + 1 + 1 + + + CLUTEN + CLUTEN + 4 + 1 + + + + + LTDC_L2WHPCR + LTDC_L2WHPCR + This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. + 0x108 + 0x20 + read-write + 0x00000000 + + + WHSTPOS + WHSTPOS + 0 + 12 + + + WHSPPOS + WHSPPOS + 16 + 12 + + + + + LTDC_L2WVPCR + LTDC_L2WVPCR + This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. + 0x10C + 0x20 + read-write + 0x00000000 + + + WVSTPOS + WVSTPOS + 0 + 12 + + + WVSPPOS + WVSPPOS + 16 + 12 + + + + + LTDC_L2CKCR + LTDC_L2CKCR + This register defines the color key value (RGB), that is used by the color keying. + 0x110 + 0x20 + read-write + 0x00000000 + + + CKBLUE + CKBLUE + 0 + 8 + + + CKGREEN + CKGREEN + 8 + 8 + + + CKRED + CKRED + 16 + 8 + + + + + LTDC_L2PFCR + LTDC_L2PFCR + This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). + 0x114 + 0x20 + read-write + 0x00000000 + + + PF + PF + 0 + 3 + + + + + LTDC_L2CACR + LTDC_L2CACR + This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. + 0x118 + 0x20 + read-write + 0x000000FF + + + CONSTA + CONSTA + 0 + 8 + + + + + LTDC_L2DCCR + LTDC_L2DCCR + This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. + 0x11C + 0x20 + read-write + 0x00000000 + + + DCBLUE + DCBLUE + 0 + 8 + + + DCGREEN + DCGREEN + 8 + 8 + + + DCRED + DCRED + 16 + 8 + + + DCALPHA + DCALPHA + 24 + 8 + + + + + LTDC_L2BFCR + LTDC_L2BFCR + This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color + 0x120 + 0x20 + read-write + 0x00000607 + + + BF2 + BF2 + 0 + 3 + + + BF1 + BF1 + 8 + 3 + + + + + LTDC_L2CFBAR + LTDC_L2CFBAR + This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. + 0x12C + 0x20 + read-write + 0x00000000 + + + CFBADD + CFBADD + 0 + 32 + + + + + LTDC_L2CFBLR + LTDC_L2CFBLR + This register defines the color frame buffer line length and pitch. + 0x130 + 0x20 + read-write + 0x00000000 + + + CFBLL + CFBLL + 0 + 14 + + + CFBP + CFBP + 16 + 14 + + + + + LTDC_L2CFBLNR + LTDC_L2CFBLNR + This register defines the number of lines in the color frame buffer. + 0x134 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + CFBLNBR + 0 + 12 + + + + + LTDC_L2CLUTWR + LTDC_L2CLUTWR + This register defines the CLUT address and the RGB value. + 0x144 + 0x20 + write-only + 0x00000000 + + + BLUE + BLUE + 0 + 8 + + + GREEN + GREEN + 8 + 8 + + + RED + RED + 16 + 8 + + + CLUTADD + CLUTADD + 24 + 8 + + + + + + + USBPHYC + USBPHYC + USBPHYC + 0x5A006000 + + 0x0 + 0x1000 + registers + + + + USBPHYC_PLL + USBPHYC_PLL + This register is used to control the PLL of the HS PHY. + 0x0 + 0x20 + read-write + 0xC0000000 + + + PLLNDIV + PLLNDIV + 0 + 7 + + + PLLODF + PLLODF + 7 + 3 + + + PLLFRACIN + PLLFRACIN + 10 + 16 + + + PLLEN + PLLEN + 26 + 1 + + + PLLSTRB + PLLSTRB + 27 + 1 + + + PLLSTRBYP + PLLSTRBYP + 28 + 1 + + + PLLFRACCTL + PLLFRACCTL + 29 + 1 + + + PLLDITHEN0 + PLLDITHEN0 + 30 + 1 + + + PLLDITHEN1 + PLLDITHEN1 + 31 + 1 + + + + + USBPHYC_MISC + USBPHYC_MISC + This register is used to control the switch between controllers for the HS PHY. + 0x8 + 0x20 + read-write + 0x00000000 + + + SWITHOST + SWITHOST + 0 + 1 + + + PPCKDIS + PPCKDIS + 1 + 2 + + + + + USBPHYC_TUNE1 + USBPHYC_TUNE1 + This register is used to control the tune interface of the HS PHY, port #x. + 0x10C + 0x20 + read-write + 0x04070004 + + + INCURREN + INCURREN + 0 + 1 + + + INCURRINT + INCURRINT + 1 + 1 + + + LFSCAPEN + LFSCAPEN + 2 + 1 + + + HSDRVSLEW + HSDRVSLEW + 3 + 1 + + + HSDRVDCCUR + HSDRVDCCUR + 4 + 1 + + + HSDRVDCLEV + HSDRVDCLEV + 5 + 1 + + + HSDRVCURINCR + HSDRVCURINCR + 6 + 1 + + + FSDRVRFADJ + FSDRVRFADJ + 7 + 1 + + + HSDRVRFRED + HSDRVRFRED + 8 + 1 + + + HSDRVCHKITRM + HSDRVCHKITRM + 9 + 4 + + + HSDRVCHKZTRM + HSDRVCHKZTRM + 13 + 2 + + + OTPCOMP + OTPCOMP + 15 + 5 + + + SQLCHCTL + SQLCHCTL + 20 + 2 + + + HDRXGNEQEN + HDRXGNEQEN + 22 + 1 + + + HSRXOFF + HSRXOFF + 23 + 2 + + + HSFALLPREEM + HSFALLPREEM + 25 + 1 + + + SHTCCTCTLPROT + SHTCCTCTLPROT + 26 + 1 + + + STAGSEL + STAGSEL + 27 + 1 + + + + + USBPHYC_TUNE2 + USBPHYC_TUNE2 + This register is used to control the tune interface of the HS PHY, port #x. + 0x20C + 0x20 + read-write + 0x04070004 + + + INCURREN + INCURREN + 0 + 1 + + + INCURRINT + INCURRINT + 1 + 1 + + + LFSCAPEN + LFSCAPEN + 2 + 1 + + + HSDRVSLEW + HSDRVSLEW + 3 + 1 + + + HSDRVDCCUR + HSDRVDCCUR + 4 + 1 + + + HSDRVDCLEV + HSDRVDCLEV + 5 + 1 + + + HSDRVCURINCR + HSDRVCURINCR + 6 + 1 + + + FSDRVRFADJ + FSDRVRFADJ + 7 + 1 + + + HSDRVRFRED + HSDRVRFRED + 8 + 1 + + + HSDRVCHKITRM + HSDRVCHKITRM + 9 + 4 + + + HSDRVCHKZTRM + HSDRVCHKZTRM + 13 + 2 + + + OTPCOMP + OTPCOMP + 15 + 5 + + + SQLCHCTL + SQLCHCTL + 20 + 2 + + + HDRXGNEQEN + HDRXGNEQEN + 22 + 1 + + + HSRXOFF + HSRXOFF + 23 + 2 + + + HSFALLPREEM + HSFALLPREEM + 25 + 1 + + + SHTCCTCTLPROT + SHTCCTCTLPROT + 26 + 1 + + + STAGSEL + STAGSEL + 27 + 1 + + + + + USBPHYC_VERR + USBPHYC_VERR + This register defines the version of this IP. + 0xFFC + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + + + CRC1 + CRC1 + CRC1 + 0x58009000 + + 0x0 + 0x1000 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + DR + 0 + 32 + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + IDR + 0 + 32 + + + + + CRC_CR + CRC_CR + CRC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RESET + RESET + 0 + 1 + + + POLYSIZE + POLYSIZE + 3 + 2 + + + REV_IN + REV_IN + 5 + 2 + + + REV_OUT + REV_OUT + 7 + 1 + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + CRC_INIT + 0 + 32 + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + POL + 0 + 32 + + + + + + + CRC2 + 0x4C004000 + + + SDMMC1 + SDMMC1 + SDMMC2 + 0x58005000 + + 0x0 + 0x1000 + registers + + + + SDMMC_POWER + SDMMC_POWER + SDMMC power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + VSWITCH + VSWITCH + 2 + 1 + + + VSWITCHEN + VSWITCHEN + 3 + 1 + + + DIRPOL + DIRPOL + 4 + 1 + + + + + SDMMC_CLKCR + SDMMC_CLKCR + The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + CLKDIV + 0 + 10 + + + PWRSAV + PWRSAV + 12 + 1 + + + WIDBUS + WIDBUS + 14 + 2 + + + NEGEDGE + NEGEDGE + 16 + 1 + + + HWFC_EN + HWFC_EN + 17 + 1 + + + DDR + DDR + 18 + 1 + + + BUSSPEED + BUSSPEED + 19 + 1 + + + SELCLKRX + SELCLKRX + 20 + 2 + + + + + SDMMC_ARGR + SDMMC_ARGR + The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + CMDARG + 0 + 32 + + + + + SDMMC_CMDR + SDMMC_CMDR + The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + CMDINDEX + 0 + 6 + + + CMDTRANS + CMDTRANS + 6 + 1 + + + CMDSTOP + CMDSTOP + 7 + 1 + + + WAITRESP + WAITRESP + 8 + 2 + + + WAITINT + WAITINT + 10 + 1 + + + WAITPEND + WAITPEND + 11 + 1 + + + CPSMEN + CPSMEN + 12 + 1 + + + DTHOLD + DTHOLD + 13 + 1 + + + BOOTMODE + BOOTMODE + 14 + 1 + + + BOOTEN + BOOTEN + 15 + 1 + + + CMDSUSPEND + CMDSUSPEND + 16 + 1 + + + + + SDMMC_RESPCMDR + SDMMC_RESPCMDR + The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + RESPCMD + 0 + 6 + + + + + SDMMC_RESP1R + SDMMC_RESP1R + The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + CARDSTATUS1 + 0 + 32 + + + + + SDMMC_RESP2R + SDMMC_RESP2R + The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + CARDSTATUS2 + 0 + 32 + + + + + SDMMC_RESP3R + SDMMC_RESP3R + The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + CARDSTATUS3 + 0 + 32 + + + + + SDMMC_RESP4R + SDMMC_RESP4R + The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + CARDSTATUS4 + 0 + 32 + + + + + SDMMC_DTIMER + SDMMC_DTIMER + The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + DATATIME + 0 + 32 + + + + + SDMMC_DLENR + SDMMC_DLENR + The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + DATALENGTH + 0 + 25 + + + + + SDMMC_DCTRL + SDMMC_DCTRL + The SDMMC_DCTRL register control the data path state machine (DPSM). + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + DTEN + 0 + 1 + + + DTDIR + DTDIR + 1 + 1 + + + DTMODE + DTMODE + 2 + 2 + + + DBLOCKSIZE + DBLOCKSIZE + 4 + 4 + + + RWSTART + RWSTART + 8 + 1 + + + RWSTOP + RWSTOP + 9 + 1 + + + RWMOD + RWMOD + 10 + 1 + + + SDIOEN + SDIOEN + 11 + 1 + + + BOOTACKEN + BOOTACKEN + 12 + 1 + + + FIFORST + FIFORST + 13 + 1 + + + + + SDMMC_DCNTR + SDMMC_DCNTR + The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + DATACOUNT + 0 + 25 + + + + + SDMMC_STAR + SDMMC_STAR + The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + CCRCFAIL + 0 + 1 + + + DCRCFAIL + DCRCFAIL + 1 + 1 + + + CTIMEOUT + CTIMEOUT + 2 + 1 + + + DTIMEOUT + DTIMEOUT + 3 + 1 + + + TXUNDERR + TXUNDERR + 4 + 1 + + + RXOVERR + RXOVERR + 5 + 1 + + + CMDREND + CMDREND + 6 + 1 + + + CMDSENT + CMDSENT + 7 + 1 + + + DATAEND + DATAEND + 8 + 1 + + + DHOLD + DHOLD + 9 + 1 + + + DBCKEND + DBCKEND + 10 + 1 + + + DABORT + DABORT + 11 + 1 + + + DPSMACT + DPSMACT + 12 + 1 + + + CPSMACT + CPSMACT + 13 + 1 + + + TXFIFOHE + TXFIFOHE + 14 + 1 + + + RXFIFOHF + RXFIFOHF + 15 + 1 + + + TXFIFOF + TXFIFOF + 16 + 1 + + + RXFIFOF + RXFIFOF + 17 + 1 + + + TXFIFOE + TXFIFOE + 18 + 1 + + + RXFIFOE + RXFIFOE + 19 + 1 + + + BUSYD0 + BUSYD0 + 20 + 1 + + + BUSYD0END + BUSYD0END + 21 + 1 + + + SDIOIT + SDIOIT + 22 + 1 + + + ACKFAIL + ACKFAIL + 23 + 1 + + + ACKTIMEOUT + ACKTIMEOUT + 24 + 1 + + + VSWEND + VSWEND + 25 + 1 + + + CKSTOP + CKSTOP + 26 + 1 + + + IDMATE + IDMATE + 27 + 1 + + + IDMABTC + IDMABTC + 28 + 1 + + + + + SDMMC_ICR + SDMMC_ICR + The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAILC + 0 + 1 + + + DCRCFAILC + DCRCFAILC + 1 + 1 + + + CTIMEOUTC + CTIMEOUTC + 2 + 1 + + + DTIMEOUTC + DTIMEOUTC + 3 + 1 + + + TXUNDERRC + TXUNDERRC + 4 + 1 + + + RXOVERRC + RXOVERRC + 5 + 1 + + + CMDRENDC + CMDRENDC + 6 + 1 + + + CMDSENTC + CMDSENTC + 7 + 1 + + + DATAENDC + DATAENDC + 8 + 1 + + + DHOLDC + DHOLDC + 9 + 1 + + + DBCKENDC + DBCKENDC + 10 + 1 + + + DABORTC + DABORTC + 11 + 1 + + + BUSYD0ENDC + BUSYD0ENDC + 21 + 1 + + + SDIOITC + SDIOITC + 22 + 1 + + + ACKFAILC + ACKFAILC + 23 + 1 + + + ACKTIMEOUTC + ACKTIMEOUTC + 24 + 1 + + + VSWENDC + VSWENDC + 25 + 1 + + + CKSTOPC + CKSTOPC + 26 + 1 + + + IDMATEC + IDMATEC + 27 + 1 + + + IDMABTCC + IDMABTCC + 28 + 1 + + + + + SDMMC_MASKR + SDMMC_MASKR + The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + CCRCFAILIE + 0 + 1 + + + DCRCFAILIE + DCRCFAILIE + 1 + 1 + + + CTIMEOUTIE + CTIMEOUTIE + 2 + 1 + + + DTIMEOUTIE + DTIMEOUTIE + 3 + 1 + + + TXUNDERRIE + TXUNDERRIE + 4 + 1 + + + RXOVERRIE + RXOVERRIE + 5 + 1 + + + CMDRENDIE + CMDRENDIE + 6 + 1 + + + CMDSENTIE + CMDSENTIE + 7 + 1 + + + DATAENDIE + DATAENDIE + 8 + 1 + + + DHOLDIE + DHOLDIE + 9 + 1 + + + DBCKENDIE + DBCKENDIE + 10 + 1 + + + DABORTIE + DABORTIE + 11 + 1 + + + TXFIFOHEIE + TXFIFOHEIE + 14 + 1 + + + RXFIFOHFIE + RXFIFOHFIE + 15 + 1 + + + RXFIFOFIE + RXFIFOFIE + 17 + 1 + + + TXFIFOEIE + TXFIFOEIE + 18 + 1 + + + BUSYD0ENDIE + BUSYD0ENDIE + 21 + 1 + + + SDIOITIE + SDIOITIE + 22 + 1 + + + ACKFAILIE + ACKFAILIE + 23 + 1 + + + ACKTIMEOUTIE + ACKTIMEOUTIE + 24 + 1 + + + VSWENDIE + VSWENDIE + 25 + 1 + + + CKSTOPIE + CKSTOPIE + 26 + 1 + + + IDMABTCIE + IDMABTCIE + 28 + 1 + + + + + SDMMC_ACKTIMER + SDMMC_ACKTIMER + The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. + 0x40 + 0x20 + read-write + 0x00000000 + + + ACKTIME + ACKTIME + 0 + 25 + + + + + SDMMC_IDMACTRLR + SDMMC_IDMACTRLR + The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. + 0x50 + 0x20 + read-write + 0x00000000 + + + IDMAEN + IDMAEN + 0 + 1 + + + IDMABMODE + IDMABMODE + 1 + 1 + + + + + SDMMC_IDMABSIZER + SDMMC_IDMABSIZER + The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. + 0x54 + 0x20 + read-write + 0x00000000 + + + IDMABNDT + IDMABNDT + 5 + 12 + + + + + SDMMC_IDMABASER + SDMMC_IDMABASER + The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. + 0x58 + 0x20 + read-write + 0x00000000 + + + IDMABASE + IDMABASE + 0 + 32 + + + + + SDMMC_IDMALAR + SDMMC_IDMALAR + SDMMC IDMA linked list address register + 0x64 + 0x20 + read-write + 0x00000000 + + + IDMALA + IDMALA + 2 + 14 + + + ABR + ABR + 29 + 1 + + + ULS + ULS + 30 + 1 + + + ULA + ULA + 31 + 1 + + + + + SDMMC_IDMABAR + SDMMC_IDMABAR + SDMMC IDMA linked list memory base register + 0x68 + 0x20 + read-write + 0x00000000 + + + IDMABA + IDMABA + 2 + 30 + + + + + SDMMC_FIFOR0 + SDMMC_FIFOR0 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR1 + SDMMC_FIFOR1 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x84 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR2 + SDMMC_FIFOR2 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x88 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR3 + SDMMC_FIFOR3 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x8C + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR4 + SDMMC_FIFOR4 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x90 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR5 + SDMMC_FIFOR5 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x94 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR6 + SDMMC_FIFOR6 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x98 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR7 + SDMMC_FIFOR7 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0x9C + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR8 + SDMMC_FIFOR8 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xA0 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR9 + SDMMC_FIFOR9 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xA4 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR10 + SDMMC_FIFOR10 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xA8 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR11 + SDMMC_FIFOR11 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xAC + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR12 + SDMMC_FIFOR12 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xB0 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR13 + SDMMC_FIFOR13 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xB4 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR14 + SDMMC_FIFOR14 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xB8 + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_FIFOR15 + SDMMC_FIFOR15 + The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. + 0xBC + 0x20 + read-write + 0x00000000 + + + FIFODATA + FIFODATA + 0 + 32 + + + + + SDMMC_VERR + SDMMC_VERR + SDMMC version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SDMMC_IPIDR + SDMMC_IPIDR + SDMMC identification register + 0x3F8 + 0x20 + read-only + 0x00140022 + + + IP_ID + IP_ID + 0 + 32 + + + + + SDMMC_SIDR + SDMMC_SIDR + SDMMC size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + SDMMC2 + 0x58007000 + + + SDMMC3 + 0x48004000 + + + QUADSPI + QUADSPI1 + QUADSPI1 + 0x58003000 + + 0x0 + 0x1000 + registers + + + + QUADSPI_CR + QUADSPI_CR + QUADSPI control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + ABORT + ABORT + 1 + 1 + + + DMAEN + DMAEN + 2 + 1 + + + TCEN + TCEN + 3 + 1 + + + SSHIFT + SSHIFT + 4 + 1 + + + DFM + DFM + 6 + 1 + + + FSEL + FSEL + 7 + 1 + + + FTHRES + FTHRES + 8 + 4 + + + TEIE + TEIE + 16 + 1 + + + TCIE + TCIE + 17 + 1 + + + FTIE + FTIE + 18 + 1 + + + SMIE + SMIE + 19 + 1 + + + TOIE + TOIE + 20 + 1 + + + APMS + APMS + 22 + 1 + + + PMM + PMM + 23 + 1 + + + PRESCALER + PRESCALER + 24 + 8 + + + + + QUADSPI_DCR + QUADSPI_DCR + QUADSPI device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + CKMODE + 0 + 1 + + + CSHT + CSHT + 8 + 3 + + + FSIZE + FSIZE + 16 + 5 + + + + + QUADSPI_SR + QUADSPI_SR + QUADSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + TEF + 0 + 1 + + + TCF + TCF + 1 + 1 + + + FTF + FTF + 2 + 1 + + + SMF + SMF + 3 + 1 + + + TOF + TOF + 4 + 1 + + + BUSY + BUSY + 5 + 1 + + + FLEVEL + FLEVEL + 8 + 5 + + + + + QUADSPI_FCR + QUADSPI_FCR + QUADSPI flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CTEF + CTEF + 0 + 1 + + + CTCF + CTCF + 1 + 1 + + + CSMF + CSMF + 3 + 1 + + + CTOF + CTOF + 4 + 1 + + + + + QUADSPI_DLR + QUADSPI_DLR + QUADSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + DL + 0 + 32 + + + + + QUADSPI_CCR + QUADSPI_CCR + QUADSPI communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + INSTRUCTION + 0 + 8 + + + IMODE + IMODE + 8 + 2 + + + ADMODE + ADMODE + 10 + 2 + + + ADSIZE + ADSIZE + 12 + 2 + + + ABMODE + ABMODE + 14 + 2 + + + ABSIZE + ABSIZE + 16 + 2 + + + DCYC + DCYC + 18 + 5 + + + DMODE + DMODE + 24 + 2 + + + FMODE + FMODE + 26 + 2 + + + SIOO + SIOO + 28 + 1 + + + FRCM + FRCM + 29 + 1 + + + DHHC + DHHC + 30 + 1 + + + DDRM + DDRM + 31 + 1 + + + + + QUADSPI_AR + QUADSPI_AR + QUADSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + ADDRESS + 0 + 32 + + + + + QUADSPI_ABR + QUADSPI_ABR + QUADSPI alternate bytes registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + QUADSPI_DR + QUADSPI_DR + QUADSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + QUADSPI_PSMKR + QUADSPI_PSMKR + QUADSPI polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + MASK + 0 + 32 + + + + + QUADSPI_PSMAR + QUADSPI_PSMAR + QUADSPI polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + MATCH + 0 + 32 + + + + + QUADSPI_PIR + QUADSPI_PIR + QUADSPI polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + INTERVAL + 0 + 16 + + + + + QUADSPI_LPTR + QUADSPI_LPTR + QUADSPI low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + TIMEOUT + 0 + 16 + + + + + QUADSPI_HWCFGR + QUADSPI_HWCFGR + QUADSPI HW configuration register + 0x3F0 + 0x20 + read-only + 0x0000B058 + + + FIFOSIZE + FIFOSIZE + 0 + 4 + + + FIFOPTR + FIFOPTR + 4 + 4 + + + PRESCVAL + PRESCVAL + 8 + 4 + + + IDLENGTH + IDLENGTH + 12 + 4 + + + + + QUADSPI_VERR + QUADSPI_VERR + QUADSPI version register + 0x3F4 + 0x20 + read-only + 0x00000041 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + QUADSPI_IPIDR + QUADSPI_IPIDR + QUADSPI identification register + 0x3F8 + 0x20 + read-only + 0x00140031 + + + ID + ID + 0 + 32 + + + + + QUADSPI_SIDR + QUADSPI_SIDR + QUADSPI size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + MDMA + MDMA1 + MDMA1 + 0x58000000 + + 0x0 + 0x1000 + registers + + + + MDMA_GISR0 + MDMA_GISR0 + MDMA global interrupt/status register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + GIF0 + 0 + 1 + + + GIF1 + GIF1 + 1 + 1 + + + GIF2 + GIF2 + 2 + 1 + + + GIF3 + GIF3 + 3 + 1 + + + GIF4 + GIF4 + 4 + 1 + + + GIF5 + GIF5 + 5 + 1 + + + GIF6 + GIF6 + 6 + 1 + + + GIF7 + GIF7 + 7 + 1 + + + GIF8 + GIF8 + 8 + 1 + + + GIF9 + GIF9 + 9 + 1 + + + GIF10 + GIF10 + 10 + 1 + + + GIF11 + GIF11 + 11 + 1 + + + GIF12 + GIF12 + 12 + 1 + + + GIF13 + GIF13 + 13 + 1 + + + GIF14 + GIF14 + 14 + 1 + + + GIF15 + GIF15 + 15 + 1 + + + GIF16 + GIF16 + 16 + 1 + + + GIF17 + GIF17 + 17 + 1 + + + GIF18 + GIF18 + 18 + 1 + + + GIF19 + GIF19 + 19 + 1 + + + GIF20 + GIF20 + 20 + 1 + + + GIF21 + GIF21 + 21 + 1 + + + GIF22 + GIF22 + 22 + 1 + + + GIF23 + GIF23 + 23 + 1 + + + GIF24 + GIF24 + 24 + 1 + + + GIF25 + GIF25 + 25 + 1 + + + GIF26 + GIF26 + 26 + 1 + + + GIF27 + GIF27 + 27 + 1 + + + GIF28 + GIF28 + 28 + 1 + + + GIF29 + GIF29 + 29 + 1 + + + GIF30 + GIF30 + 30 + 1 + + + GIF31 + GIF31 + 31 + 1 + + + + + MDMA_SGISR0 + MDMA_SGISR0 + MDMA secure global interrupt/status register + 0x8 + 0x20 + read-only + 0x00000000 + + + GIF0 + GIF0 + 0 + 1 + + + GIF1 + GIF1 + 1 + 1 + + + GIF2 + GIF2 + 2 + 1 + + + GIF3 + GIF3 + 3 + 1 + + + GIF4 + GIF4 + 4 + 1 + + + GIF5 + GIF5 + 5 + 1 + + + GIF6 + GIF6 + 6 + 1 + + + GIF7 + GIF7 + 7 + 1 + + + GIF8 + GIF8 + 8 + 1 + + + GIF9 + GIF9 + 9 + 1 + + + GIF10 + GIF10 + 10 + 1 + + + GIF11 + GIF11 + 11 + 1 + + + GIF12 + GIF12 + 12 + 1 + + + GIF13 + GIF13 + 13 + 1 + + + GIF14 + GIF14 + 14 + 1 + + + GIF15 + GIF15 + 15 + 1 + + + GIF16 + GIF16 + 16 + 1 + + + GIF17 + GIF17 + 17 + 1 + + + GIF18 + GIF18 + 18 + 1 + + + GIF19 + GIF19 + 19 + 1 + + + GIF20 + GIF20 + 20 + 1 + + + GIF21 + GIF21 + 21 + 1 + + + GIF22 + GIF22 + 22 + 1 + + + GIF23 + GIF23 + 23 + 1 + + + GIF24 + GIF24 + 24 + 1 + + + GIF25 + GIF25 + 25 + 1 + + + GIF26 + GIF26 + 26 + 1 + + + GIF27 + GIF27 + 27 + 1 + + + GIF28 + GIF28 + 28 + 1 + + + GIF29 + GIF29 + 29 + 1 + + + GIF30 + GIF30 + 30 + 1 + + + GIF31 + GIF31 + 31 + 1 + + + + + MDMA_C0ISR + MDMA_C0ISR + MDMA channel 0 interrupt/status register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C0IFCR + MDMA_C0IFCR + MDMA channel 0 interrupt flag clear register + 0x44 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C0ESR + MDMA_C0ESR + MDMA channel 0 error status register + 0x48 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C0CR + MDMA_C0CR + This register is used to control the concerned channel. + 0x4C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C0TCR + MDMA_C0TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x50 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C0BNDTR + MDMA_C0BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x54 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C0SAR + MDMA_C0SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x58 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C0DAR + MDMA_C0DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x5C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C0BRUR + MDMA_C0BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x60 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C0LAR + MDMA_C0LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x64 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C0TBR + MDMA_C0TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x68 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C0MAR + MDMA_C0MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x70 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C0MDR + MDMA_C0MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x74 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C1ISR + MDMA_C1ISR + MDMA channel 1 interrupt/status register + 0x80 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C1IFCR + MDMA_C1IFCR + MDMA channel 1 interrupt flag clear register + 0x84 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C1ESR + MDMA_C1ESR + MDMA channel 1 error status register + 0x88 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C1CR + MDMA_C1CR + This register is used to control the concerned channel. + 0x8C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C1TCR + MDMA_C1TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x90 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C1BNDTR + MDMA_C1BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x94 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C1SAR + MDMA_C1SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x98 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C1DAR + MDMA_C1DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x9C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C1BRUR + MDMA_C1BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0xA0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C1LAR + MDMA_C1LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0xA4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C1TBR + MDMA_C1TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0xA8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C1MAR + MDMA_C1MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0xB0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C1MDR + MDMA_C1MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0xB4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C2ISR + MDMA_C2ISR + MDMA channel 2 interrupt/status register + 0xC0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C2IFCR + MDMA_C2IFCR + MDMA channel 2 interrupt flag clear register + 0xC4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C2ESR + MDMA_C2ESR + MDMA channel 2 error status register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C2CR + MDMA_C2CR + This register is used to control the concerned channel. + 0xCC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C2TCR + MDMA_C2TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0xD0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C2BNDTR + MDMA_C2BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0xD4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C2SAR + MDMA_C2SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0xD8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C2DAR + MDMA_C2DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0xDC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C2BRUR + MDMA_C2BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0xE0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C2LAR + MDMA_C2LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0xE4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C2TBR + MDMA_C2TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0xE8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C2MAR + MDMA_C2MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0xF0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C2MDR + MDMA_C2MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0xF4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C3ISR + MDMA_C3ISR + MDMA channel 3 interrupt/status register + 0x100 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C3IFCR + MDMA_C3IFCR + MDMA channel 3 interrupt flag clear register + 0x104 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C3ESR + MDMA_C3ESR + MDMA channel 3 error status register + 0x108 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C3CR + MDMA_C3CR + This register is used to control the concerned channel. + 0x10C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C3TCR + MDMA_C3TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x110 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C3BNDTR + MDMA_C3BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x114 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C3SAR + MDMA_C3SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x118 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C3DAR + MDMA_C3DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x11C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C3BRUR + MDMA_C3BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x120 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C3LAR + MDMA_C3LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x124 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C3TBR + MDMA_C3TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x128 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C3MAR + MDMA_C3MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x130 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C3MDR + MDMA_C3MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x134 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C4ISR + MDMA_C4ISR + MDMA channel 4 interrupt/status register + 0x140 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C4IFCR + MDMA_C4IFCR + MDMA channel 4 interrupt flag clear register + 0x144 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C4ESR + MDMA_C4ESR + MDMA channel 4 error status register + 0x148 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C4CR + MDMA_C4CR + This register is used to control the concerned channel. + 0x14C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C4TCR + MDMA_C4TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x150 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C4BNDTR + MDMA_C4BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x154 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C4SAR + MDMA_C4SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x158 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C4DAR + MDMA_C4DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x15C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C4BRUR + MDMA_C4BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x160 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C4LAR + MDMA_C4LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x164 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C4TBR + MDMA_C4TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x168 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C4MAR + MDMA_C4MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x170 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C4MDR + MDMA_C4MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x174 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C5ISR + MDMA_C5ISR + MDMA channel 5 interrupt/status register + 0x180 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C5IFCR + MDMA_C5IFCR + MDMA channel 5 interrupt flag clear register + 0x184 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C5ESR + MDMA_C5ESR + MDMA channel 5 error status register + 0x188 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C5CR + MDMA_C5CR + This register is used to control the concerned channel. + 0x18C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C5TCR + MDMA_C5TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x190 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C5BNDTR + MDMA_C5BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x194 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C5SAR + MDMA_C5SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x198 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C5DAR + MDMA_C5DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x19C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C5BRUR + MDMA_C5BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C5LAR + MDMA_C5LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x1A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C5TBR + MDMA_C5TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C5MAR + MDMA_C5MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x1B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C5MDR + MDMA_C5MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x1B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C6ISR + MDMA_C6ISR + MDMA channel 6 interrupt/status register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C6IFCR + MDMA_C6IFCR + MDMA channel 6 interrupt flag clear register + 0x1C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C6ESR + MDMA_C6ESR + MDMA channel 6 error status register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C6CR + MDMA_C6CR + This register is used to control the concerned channel. + 0x1CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C6TCR + MDMA_C6TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x1D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C6BNDTR + MDMA_C6BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x1D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C6SAR + MDMA_C6SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x1D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C6DAR + MDMA_C6DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x1DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C6BRUR + MDMA_C6BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x1E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C6LAR + MDMA_C6LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x1E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C6TBR + MDMA_C6TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C6MAR + MDMA_C6MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x1F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C6MDR + MDMA_C6MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x1F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C7ISR + MDMA_C7ISR + MDMA channel 7 interrupt/status register + 0x200 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C7IFCR + MDMA_C7IFCR + MDMA channel 7 interrupt flag clear register + 0x204 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C7ESR + MDMA_C7ESR + MDMA channel 7 error status register + 0x208 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C7CR + MDMA_C7CR + This register is used to control the concerned channel. + 0x20C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C7TCR + MDMA_C7TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x210 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C7BNDTR + MDMA_C7BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x214 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C7SAR + MDMA_C7SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x218 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C7DAR + MDMA_C7DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x21C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C7BRUR + MDMA_C7BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x220 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C7LAR + MDMA_C7LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x224 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C7TBR + MDMA_C7TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x228 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C7MAR + MDMA_C7MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x230 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C7MDR + MDMA_C7MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x234 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C8ISR + MDMA_C8ISR + MDMA channel 8 interrupt/status register + 0x240 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C8IFCR + MDMA_C8IFCR + MDMA channel 8 interrupt flag clear register + 0x244 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C8ESR + MDMA_C8ESR + MDMA channel 8 error status register + 0x248 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C8CR + MDMA_C8CR + This register is used to control the concerned channel. + 0x24C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C8TCR + MDMA_C8TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x250 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C8BNDTR + MDMA_C8BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x254 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C8SAR + MDMA_C8SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x258 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C8DAR + MDMA_C8DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x25C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C8BRUR + MDMA_C8BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x260 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C8LAR + MDMA_C8LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x264 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C8TBR + MDMA_C8TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x268 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C8MAR + MDMA_C8MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x270 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C8MDR + MDMA_C8MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x274 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C9ISR + MDMA_C9ISR + MDMA channel 9 interrupt/status register + 0x280 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C9IFCR + MDMA_C9IFCR + MDMA channel 9 interrupt flag clear register + 0x284 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C9ESR + MDMA_C9ESR + MDMA channel 9 error status register + 0x288 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C9CR + MDMA_C9CR + This register is used to control the concerned channel. + 0x28C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C9TCR + MDMA_C9TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x290 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C9BNDTR + MDMA_C9BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x294 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C9SAR + MDMA_C9SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x298 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C9DAR + MDMA_C9DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x29C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C9BRUR + MDMA_C9BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x2A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C9LAR + MDMA_C9LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x2A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C9TBR + MDMA_C9TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x2A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C9MAR + MDMA_C9MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x2B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C9MDR + MDMA_C9MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x2B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C10ISR + MDMA_C10ISR + MDMA channel 10 interrupt/status register + 0x2C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C10IFCR + MDMA_C10IFCR + MDMA channel 10 interrupt flag clear register + 0x2C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C10ESR + MDMA_C10ESR + MDMA channel 10 error status register + 0x2C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C10CR + MDMA_C10CR + This register is used to control the concerned channel. + 0x2CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C10TCR + MDMA_C10TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x2D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C10BNDTR + MDMA_C10BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x2D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C10SAR + MDMA_C10SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x2D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C10DAR + MDMA_C10DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x2DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C10BRUR + MDMA_C10BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x2E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C10LAR + MDMA_C10LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x2E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C10TBR + MDMA_C10TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x2E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C10MAR + MDMA_C10MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x2F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C10MDR + MDMA_C10MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x2F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C11ISR + MDMA_C11ISR + MDMA channel 11 interrupt/status register + 0x300 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C11IFCR + MDMA_C11IFCR + MDMA channel 11 interrupt flag clear register + 0x304 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C11ESR + MDMA_C11ESR + MDMA channel 11 error status register + 0x308 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C11CR + MDMA_C11CR + This register is used to control the concerned channel. + 0x30C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C11TCR + MDMA_C11TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x310 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C11BNDTR + MDMA_C11BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x314 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C11SAR + MDMA_C11SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x318 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C11DAR + MDMA_C11DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x31C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C11BRUR + MDMA_C11BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x320 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C11LAR + MDMA_C11LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x324 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C11TBR + MDMA_C11TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x328 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C11MAR + MDMA_C11MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x330 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C11MDR + MDMA_C11MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x334 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C12ISR + MDMA_C12ISR + MDMA channel 12 interrupt/status register + 0x340 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C12IFCR + MDMA_C12IFCR + MDMA channel 12 interrupt flag clear register + 0x344 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C12ESR + MDMA_C12ESR + MDMA channel 12 error status register + 0x348 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C12CR + MDMA_C12CR + This register is used to control the concerned channel. + 0x34C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C12TCR + MDMA_C12TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x350 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C12BNDTR + MDMA_C12BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x354 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C12SAR + MDMA_C12SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x358 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C12DAR + MDMA_C12DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x35C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C12BRUR + MDMA_C12BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x360 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C12LAR + MDMA_C12LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x364 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C12TBR + MDMA_C12TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x368 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C12MAR + MDMA_C12MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x370 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C12MDR + MDMA_C12MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x374 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C13ISR + MDMA_C13ISR + MDMA channel 13 interrupt/status register + 0x380 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C13IFCR + MDMA_C13IFCR + MDMA channel 13 interrupt flag clear register + 0x384 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C13ESR + MDMA_C13ESR + MDMA channel 13 error status register + 0x388 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C13CR + MDMA_C13CR + This register is used to control the concerned channel. + 0x38C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C13TCR + MDMA_C13TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x390 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C13BNDTR + MDMA_C13BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x394 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C13SAR + MDMA_C13SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x398 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C13DAR + MDMA_C13DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x39C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C13BRUR + MDMA_C13BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x3A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C13LAR + MDMA_C13LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x3A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C13TBR + MDMA_C13TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x3A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C13MAR + MDMA_C13MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x3B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C13MDR + MDMA_C13MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x3B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C14ISR + MDMA_C14ISR + MDMA channel 14 interrupt/status register + 0x3C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C14IFCR + MDMA_C14IFCR + MDMA channel 14 interrupt flag clear register + 0x3C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C14ESR + MDMA_C14ESR + MDMA channel 14 error status register + 0x3C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C14CR + MDMA_C14CR + This register is used to control the concerned channel. + 0x3CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C14TCR + MDMA_C14TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x3D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C14BNDTR + MDMA_C14BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x3D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C14SAR + MDMA_C14SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x3D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C14DAR + MDMA_C14DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x3DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C14BRUR + MDMA_C14BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x3E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C14LAR + MDMA_C14LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x3E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C14TBR + MDMA_C14TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x3E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C14MAR + MDMA_C14MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x3F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C14MDR + MDMA_C14MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x3F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C15ISR + MDMA_C15ISR + MDMA channel 15 interrupt/status register + 0x400 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C15IFCR + MDMA_C15IFCR + MDMA channel 15 interrupt flag clear register + 0x404 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C15ESR + MDMA_C15ESR + MDMA channel 15 error status register + 0x408 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C15CR + MDMA_C15CR + This register is used to control the concerned channel. + 0x40C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C15TCR + MDMA_C15TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x410 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C15BNDTR + MDMA_C15BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x414 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C15SAR + MDMA_C15SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x418 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C15DAR + MDMA_C15DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x41C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C15BRUR + MDMA_C15BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x420 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C15LAR + MDMA_C15LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x424 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C15TBR + MDMA_C15TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x428 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C15MAR + MDMA_C15MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x430 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C15MDR + MDMA_C15MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x434 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C16ISR + MDMA_C16ISR + MDMA channel 16 interrupt/status register + 0x440 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C16IFCR + MDMA_C16IFCR + MDMA channel 16 interrupt flag clear register + 0x444 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C16ESR + MDMA_C16ESR + MDMA channel 16 error status register + 0x448 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C16CR + MDMA_C16CR + This register is used to control the concerned channel. + 0x44C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C16TCR + MDMA_C16TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x450 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C16BNDTR + MDMA_C16BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x454 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C16SAR + MDMA_C16SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x458 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C16DAR + MDMA_C16DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x45C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C16BRUR + MDMA_C16BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x460 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C16LAR + MDMA_C16LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x464 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C16TBR + MDMA_C16TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x468 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C16MAR + MDMA_C16MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x470 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C16MDR + MDMA_C16MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x474 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C17ISR + MDMA_C17ISR + MDMA channel 17 interrupt/status register + 0x480 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C17IFCR + MDMA_C17IFCR + MDMA channel 17 interrupt flag clear register + 0x484 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C17ESR + MDMA_C17ESR + MDMA channel 17 error status register + 0x488 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C17CR + MDMA_C17CR + This register is used to control the concerned channel. + 0x48C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C17TCR + MDMA_C17TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x490 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C17BNDTR + MDMA_C17BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x494 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C17SAR + MDMA_C17SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x498 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C17DAR + MDMA_C17DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x49C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C17BRUR + MDMA_C17BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x4A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C17LAR + MDMA_C17LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x4A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C17TBR + MDMA_C17TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x4A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C17MAR + MDMA_C17MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x4B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C17MDR + MDMA_C17MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x4B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C18ISR + MDMA_C18ISR + MDMA channel 18 interrupt/status register + 0x4C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C18IFCR + MDMA_C18IFCR + MDMA channel 18 interrupt flag clear register + 0x4C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C18ESR + MDMA_C18ESR + MDMA channel 18 error status register + 0x4C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C18CR + MDMA_C18CR + This register is used to control the concerned channel. + 0x4CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C18TCR + MDMA_C18TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x4D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C18BNDTR + MDMA_C18BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x4D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C18SAR + MDMA_C18SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x4D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C18DAR + MDMA_C18DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x4DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C18BRUR + MDMA_C18BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x4E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C18LAR + MDMA_C18LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x4E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C18TBR + MDMA_C18TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x4E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C18MAR + MDMA_C18MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x4F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C18MDR + MDMA_C18MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x4F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C19ISR + MDMA_C19ISR + MDMA channel 19 interrupt/status register + 0x500 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C19IFCR + MDMA_C19IFCR + MDMA channel 19 interrupt flag clear register + 0x504 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C19ESR + MDMA_C19ESR + MDMA channel 19 error status register + 0x508 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C19CR + MDMA_C19CR + This register is used to control the concerned channel. + 0x50C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C19TCR + MDMA_C19TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x510 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C19BNDTR + MDMA_C19BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x514 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C19SAR + MDMA_C19SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x518 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C19DAR + MDMA_C19DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x51C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C19BRUR + MDMA_C19BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x520 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C19LAR + MDMA_C19LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x524 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C19TBR + MDMA_C19TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x528 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C19MAR + MDMA_C19MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x530 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C19MDR + MDMA_C19MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x534 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C20ISR + MDMA_C20ISR + MDMA channel 20 interrupt/status register + 0x540 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C20IFCR + MDMA_C20IFCR + MDMA channel 20 interrupt flag clear register + 0x544 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C20ESR + MDMA_C20ESR + MDMA channel 20 error status register + 0x548 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C20CR + MDMA_C20CR + This register is used to control the concerned channel. + 0x54C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C20TCR + MDMA_C20TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x550 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C20BNDTR + MDMA_C20BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x554 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C20SAR + MDMA_C20SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x558 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C20DAR + MDMA_C20DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x55C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C20BRUR + MDMA_C20BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x560 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C20LAR + MDMA_C20LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x564 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C20TBR + MDMA_C20TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x568 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C20MAR + MDMA_C20MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x570 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C20MDR + MDMA_C20MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x574 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C21ISR + MDMA_C21ISR + MDMA channel 21 interrupt/status register + 0x580 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C21IFCR + MDMA_C21IFCR + MDMA channel 21 interrupt flag clear register + 0x584 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C21ESR + MDMA_C21ESR + MDMA channel 21 error status register + 0x588 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C21CR + MDMA_C21CR + This register is used to control the concerned channel. + 0x58C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C21TCR + MDMA_C21TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x590 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C21BNDTR + MDMA_C21BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x594 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C21SAR + MDMA_C21SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x598 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C21DAR + MDMA_C21DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x59C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C21BRUR + MDMA_C21BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x5A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C21LAR + MDMA_C21LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x5A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C21TBR + MDMA_C21TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x5A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C21MAR + MDMA_C21MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x5B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C21MDR + MDMA_C21MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x5B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C22ISR + MDMA_C22ISR + MDMA channel 22 interrupt/status register + 0x5C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C22IFCR + MDMA_C22IFCR + MDMA channel 22 interrupt flag clear register + 0x5C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C22ESR + MDMA_C22ESR + MDMA channel 22 error status register + 0x5C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C22CR + MDMA_C22CR + This register is used to control the concerned channel. + 0x5CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C22TCR + MDMA_C22TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x5D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C22BNDTR + MDMA_C22BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x5D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C22SAR + MDMA_C22SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x5D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C22DAR + MDMA_C22DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x5DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C22BRUR + MDMA_C22BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x5E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C22LAR + MDMA_C22LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x5E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C22TBR + MDMA_C22TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x5E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C22MAR + MDMA_C22MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x5F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C22MDR + MDMA_C22MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x5F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C23ISR + MDMA_C23ISR + MDMA channel 23 interrupt/status register + 0x600 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C23IFCR + MDMA_C23IFCR + MDMA channel 23 interrupt flag clear register + 0x604 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C23ESR + MDMA_C23ESR + MDMA channel 23 error status register + 0x608 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C23CR + MDMA_C23CR + This register is used to control the concerned channel. + 0x60C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C23TCR + MDMA_C23TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x610 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C23BNDTR + MDMA_C23BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x614 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C23SAR + MDMA_C23SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x618 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C23DAR + MDMA_C23DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x61C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C23BRUR + MDMA_C23BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x620 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C23LAR + MDMA_C23LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x624 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C23TBR + MDMA_C23TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x628 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C23MAR + MDMA_C23MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x630 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C23MDR + MDMA_C23MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x634 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C24ISR + MDMA_C24ISR + MDMA channel 24 interrupt/status register + 0x640 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C24IFCR + MDMA_C24IFCR + MDMA channel 24 interrupt flag clear register + 0x644 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C24ESR + MDMA_C24ESR + MDMA channel 24 error status register + 0x648 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C24CR + MDMA_C24CR + This register is used to control the concerned channel. + 0x64C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C24TCR + MDMA_C24TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x650 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C24BNDTR + MDMA_C24BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x654 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C24SAR + MDMA_C24SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x658 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C24DAR + MDMA_C24DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x65C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C24BRUR + MDMA_C24BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x660 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C24LAR + MDMA_C24LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x664 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C24TBR + MDMA_C24TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x668 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C24MAR + MDMA_C24MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x670 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C24MDR + MDMA_C24MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x674 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C25ISR + MDMA_C25ISR + MDMA channel 25 interrupt/status register + 0x680 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C25IFCR + MDMA_C25IFCR + MDMA channel 25 interrupt flag clear register + 0x684 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C25ESR + MDMA_C25ESR + MDMA channel 25 error status register + 0x688 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C25CR + MDMA_C25CR + This register is used to control the concerned channel. + 0x68C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C25TCR + MDMA_C25TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x690 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C25BNDTR + MDMA_C25BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x694 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C25SAR + MDMA_C25SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x698 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C25DAR + MDMA_C25DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x69C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C25BRUR + MDMA_C25BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x6A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C25LAR + MDMA_C25LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x6A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C25TBR + MDMA_C25TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x6A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C25MAR + MDMA_C25MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x6B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C25MDR + MDMA_C25MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x6B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C26ISR + MDMA_C26ISR + MDMA channel 26 interrupt/status register + 0x6C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C26IFCR + MDMA_C26IFCR + MDMA channel 26 interrupt flag clear register + 0x6C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C26ESR + MDMA_C26ESR + MDMA channel 26 error status register + 0x6C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C26CR + MDMA_C26CR + This register is used to control the concerned channel. + 0x6CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C26TCR + MDMA_C26TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x6D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C26BNDTR + MDMA_C26BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x6D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C26SAR + MDMA_C26SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x6D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C26DAR + MDMA_C26DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x6DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C26BRUR + MDMA_C26BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x6E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C26LAR + MDMA_C26LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x6E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C26TBR + MDMA_C26TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x6E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C26MAR + MDMA_C26MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x6F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C26MDR + MDMA_C26MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x6F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C27ISR + MDMA_C27ISR + MDMA channel 27 interrupt/status register + 0x700 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C27IFCR + MDMA_C27IFCR + MDMA channel 27 interrupt flag clear register + 0x704 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C27ESR + MDMA_C27ESR + MDMA channel 27 error status register + 0x708 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C27CR + MDMA_C27CR + This register is used to control the concerned channel. + 0x70C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C27TCR + MDMA_C27TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x710 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C27BNDTR + MDMA_C27BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x714 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C27SAR + MDMA_C27SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x718 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C27DAR + MDMA_C27DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x71C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C27BRUR + MDMA_C27BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x720 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C27LAR + MDMA_C27LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x724 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C27TBR + MDMA_C27TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x728 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C27MAR + MDMA_C27MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x730 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C27MDR + MDMA_C27MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x734 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C28ISR + MDMA_C28ISR + MDMA channel 28 interrupt/status register + 0x740 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C28IFCR + MDMA_C28IFCR + MDMA channel 28 interrupt flag clear register + 0x744 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C28ESR + MDMA_C28ESR + MDMA channel 28 error status register + 0x748 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C28CR + MDMA_C28CR + This register is used to control the concerned channel. + 0x74C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C28TCR + MDMA_C28TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x750 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C28BNDTR + MDMA_C28BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x754 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C28SAR + MDMA_C28SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x758 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C28DAR + MDMA_C28DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x75C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C28BRUR + MDMA_C28BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x760 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C28LAR + MDMA_C28LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x764 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C28TBR + MDMA_C28TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x768 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C28MAR + MDMA_C28MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x770 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C28MDR + MDMA_C28MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x774 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C29ISR + MDMA_C29ISR + MDMA channel 29 interrupt/status register + 0x780 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C29IFCR + MDMA_C29IFCR + MDMA channel 29 interrupt flag clear register + 0x784 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C29ESR + MDMA_C29ESR + MDMA channel 29 error status register + 0x788 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C29CR + MDMA_C29CR + This register is used to control the concerned channel. + 0x78C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C29TCR + MDMA_C29TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x790 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C29BNDTR + MDMA_C29BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x794 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C29SAR + MDMA_C29SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x798 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C29DAR + MDMA_C29DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x79C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C29BRUR + MDMA_C29BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x7A0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C29LAR + MDMA_C29LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x7A4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C29TBR + MDMA_C29TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x7A8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C29MAR + MDMA_C29MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x7B0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C29MDR + MDMA_C29MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x7B4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C30ISR + MDMA_C30ISR + MDMA channel 30 interrupt/status register + 0x7C0 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C30IFCR + MDMA_C30IFCR + MDMA channel 30 interrupt flag clear register + 0x7C4 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C30ESR + MDMA_C30ESR + MDMA channel 30 error status register + 0x7C8 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C30CR + MDMA_C30CR + This register is used to control the concerned channel. + 0x7CC + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C30TCR + MDMA_C30TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x7D0 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C30BNDTR + MDMA_C30BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x7D4 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C30SAR + MDMA_C30SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x7D8 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C30DAR + MDMA_C30DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x7DC + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C30BRUR + MDMA_C30BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x7E0 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C30LAR + MDMA_C30LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x7E4 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C30TBR + MDMA_C30TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x7E8 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C30MAR + MDMA_C30MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x7F0 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C30MDR + MDMA_C30MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x7F4 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + MDMA_C31ISR + MDMA_C31ISR + MDMA channel 31 interrupt/status register + 0x800 + 0x20 + read-only + 0x00000000 + + + TEIF + TEIF + 0 + 1 + + + CTCIF + CTCIF + 1 + 1 + + + BRTIF + BRTIF + 2 + 1 + + + BTIF + BTIF + 3 + 1 + + + TCIF + TCIF + 4 + 1 + + + CRQA + CRQA + 16 + 1 + + + + + MDMA_C31IFCR + MDMA_C31IFCR + MDMA channel 31 interrupt flag clear register + 0x804 + 0x20 + write-only + 0x00000000 + + + CTEIF + CTEIF + 0 + 1 + + + CCTCIF + CCTCIF + 1 + 1 + + + CBRTIF + CBRTIF + 2 + 1 + + + CBTIF + CBTIF + 3 + 1 + + + CLTCIF + CLTCIF + 4 + 1 + + + + + MDMA_C31ESR + MDMA_C31ESR + MDMA channel 31 error status register + 0x808 + 0x20 + read-only + 0x00000000 + + + TEA + TEA + 0 + 7 + + + TED + TED + 7 + 1 + + + TELD + TELD + 8 + 1 + + + TEMD + TEMD + 9 + 1 + + + ASE + ASE + 10 + 1 + + + BSE + BSE + 11 + 1 + + + + + MDMA_C31CR + MDMA_C31CR + This register is used to control the concerned channel. + 0x80C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + TEIE + TEIE + 1 + 1 + read-write + + + CTCIE + CTCIE + 2 + 1 + read-write + + + BRTIE + BRTIE + 3 + 1 + read-write + + + BTIE + BTIE + 4 + 1 + read-write + + + TCIE + TCIE + 5 + 1 + read-write + + + PL + PL + 6 + 2 + read-write + + + BEX + BEX + 12 + 1 + read-write + + + HEX + HEX + 13 + 1 + read-write + + + WEX + WEX + 14 + 1 + read-write + + + SWRQ + SWRQ + 16 + 1 + write-only + + + + + MDMA_C31TCR + MDMA_C31TCR + This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). + 0x810 + 0x20 + read-write + 0x00000000 + + + SINC + SINC + 0 + 2 + + + DINC + DINC + 2 + 2 + + + SSIZE + SSIZE + 4 + 2 + + + DSIZE + DSIZE + 6 + 2 + + + SINCOS + SINCOS + 8 + 2 + + + DINCOS + DINCOS + 10 + 2 + + + SBURST + SBURST + 12 + 3 + + + DBURST + DBURST + 15 + 3 + + + TLEN + TLEN + 18 + 7 + + + PKE + PKE + 25 + 1 + + + PAM + PAM + 26 + 2 + + + TRGM + TRGM + 28 + 2 + + + SWRM + SWRM + 30 + 1 + + + BWM + BWM + 31 + 1 + + + + + MDMA_C31BNDTR + MDMA_C31BNDTR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). + 0x814 + 0x20 + read-write + 0x00000000 + + + BNDT + BNDT + 0 + 17 + + + BRSUM + BRSUM + 18 + 1 + + + BRDUM + BRDUM + 19 + 1 + + + BRC + BRC + 20 + 12 + + + + + MDMA_C31SAR + MDMA_C31SAR + In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). + 0x818 + 0x20 + read-write + 0x00000000 + + + SAR + SAR + 0 + 32 + + + + + MDMA_C31DAR + MDMA_C31DAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M + 0x81C + 0x20 + read-write + 0x00000000 + + + DAR + DAR + 0 + 32 + + + + + MDMA_C31BRUR + MDMA_C31BRUR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). + 0x820 + 0x20 + read-write + 0x00000000 + + + SUV + SUV + 0 + 16 + + + DUV + DUV + 16 + 16 + + + + + MDMA_C31LAR + MDMA_C31LAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. + 0x824 + 0x20 + read-write + 0x00000000 + + + LAR + LAR + 0 + 32 + + + + + MDMA_C31TBR + MDMA_C31TBR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). + 0x828 + 0x20 + read-write + 0x00000000 + + + TSEL + TSEL + 0 + 6 + + + SBUS + SBUS + 16 + 1 + + + DBUS + DBUS + 17 + 1 + + + + + MDMA_C31MAR + MDMA_C31MAR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). + 0x830 + 0x20 + read-write + 0x00000000 + + + MAR + MAR + 0 + 32 + + + + + MDMA_C31MDR + MDMA_C31MDR + In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). + 0x834 + 0x20 + read-write + 0x00000000 + + + MDR + MDR + 0 + 32 + + + + + + + GPIOA + GPIOA + GPIOA + 0x50002000 + + 0x0 + 0x400 + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOA_LCKR + GPIOA_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOA_HWCFGR10 + GPIOA_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOA_HWCFGR9 + GPIOA_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOA_HWCFGR8 + GPIOA_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOA_HWCFGR7 + GPIOA_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOA_HWCFGR6 + GPIOA_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOA_HWCFGR5 + GPIOA_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOA_HWCFGR4 + GPIOA_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOA_HWCFGR3 + GPIOA_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOA_HWCFGR2 + GPIOA_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOA_HWCFGR1 + GPIOA_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOA_HWCFGR0 + GPIOA_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOA_VERR + GPIOA_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOA_IPIDR + GPIOA_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOA_SIDR + GPIOA_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOB + GPIOB + GPIOB + 0x50003000 + + 0x0 + 0x400 + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOB_LCKR + GPIOB_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOB_HWCFGR10 + GPIOB_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOB_HWCFGR9 + GPIOB_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOB_HWCFGR8 + GPIOB_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOB_HWCFGR7 + GPIOB_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOB_HWCFGR6 + GPIOB_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOB_HWCFGR5 + GPIOB_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOB_HWCFGR4 + GPIOB_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOB_HWCFGR3 + GPIOB_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOB_HWCFGR2 + GPIOB_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOB_HWCFGR1 + GPIOB_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOB_HWCFGR0 + GPIOB_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOB_VERR + GPIOB_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOB_IPIDR + GPIOB_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOB_SIDR + GPIOB_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOC + GPIOC + GPIOC + 0x50004000 + + 0x0 + 0x400 + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOC_LCKR + GPIOC_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOC_HWCFGR10 + GPIOC_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOC_HWCFGR9 + GPIOC_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOC_HWCFGR8 + GPIOC_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOC_HWCFGR7 + GPIOC_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOC_HWCFGR6 + GPIOC_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOC_HWCFGR5 + GPIOC_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOC_HWCFGR4 + GPIOC_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOC_HWCFGR3 + GPIOC_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOC_HWCFGR2 + GPIOC_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOC_HWCFGR1 + GPIOC_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOC_HWCFGR0 + GPIOC_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOC_VERR + GPIOC_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOC_IPIDR + GPIOC_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOC_SIDR + GPIOC_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOD + GPIOD + GPIOD + 0x50005000 + + 0x0 + 0x400 + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOD_LCKR + GPIOD_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOD_HWCFGR10 + GPIOD_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOD_HWCFGR9 + GPIOD_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOD_HWCFGR8 + GPIOD_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOD_HWCFGR7 + GPIOD_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOD_HWCFGR6 + GPIOD_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOD_HWCFGR5 + GPIOD_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOD_HWCFGR4 + GPIOD_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOD_HWCFGR3 + GPIOD_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOD_HWCFGR2 + GPIOD_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOD_HWCFGR1 + GPIOD_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOD_HWCFGR0 + GPIOD_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOD_VERR + GPIOD_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOD_IPIDR + GPIOD_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOD_SIDR + GPIOD_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOE + GPIOE + GPIOE + 0x50006000 + + 0x0 + 0x400 + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOE_LCKR + GPIOE_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOE_HWCFGR10 + GPIOE_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOE_HWCFGR9 + GPIOE_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOE_HWCFGR8 + GPIOE_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOE_HWCFGR7 + GPIOE_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOE_HWCFGR6 + GPIOE_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOE_HWCFGR5 + GPIOE_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOE_HWCFGR4 + GPIOE_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOE_HWCFGR3 + GPIOE_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOE_HWCFGR2 + GPIOE_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOE_HWCFGR1 + GPIOE_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOE_HWCFGR0 + GPIOE_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOE_VERR + GPIOE_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOE_IPIDR + GPIOE_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOE_SIDR + GPIOE_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOF + GPIOF + GPIOF + 0x50007000 + + 0x0 + 0x400 + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOF_LCKR + GPIOF_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOF_HWCFGR10 + GPIOF_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOF_HWCFGR9 + GPIOF_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOF_HWCFGR8 + GPIOF_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOF_HWCFGR7 + GPIOF_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOF_HWCFGR6 + GPIOF_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOF_HWCFGR5 + GPIOF_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOF_HWCFGR4 + GPIOF_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOF_HWCFGR3 + GPIOF_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOF_HWCFGR2 + GPIOF_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOF_HWCFGR1 + GPIOF_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOF_HWCFGR0 + GPIOF_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOF_VERR + GPIOF_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOF_IPIDR + GPIOF_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOF_SIDR + GPIOF_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOG + GPIOG + GPIOG + 0x50008000 + + 0x0 + 0x400 + registers + + + + GPIOG_MODER + GPIOG_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOG_OTYPER + GPIOG_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOG_OSPEEDR + GPIOG_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOG_PUPDR + GPIOG_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOG_IDR + GPIOG_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOG_ODR + GPIOG_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOG_BSRR + GPIOG_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOG_LCKR + GPIOG_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOG_AFRL + GPIOG_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOG_AFRH + GPIOG_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOG_BRR + GPIOG_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOG_HWCFGR10 + GPIOG_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOG_HWCFGR9 + GPIOG_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOG_HWCFGR8 + GPIOG_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOG_HWCFGR7 + GPIOG_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOG_HWCFGR6 + GPIOG_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOG_HWCFGR5 + GPIOG_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOG_HWCFGR4 + GPIOG_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOG_HWCFGR3 + GPIOG_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOG_HWCFGR2 + GPIOG_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOG_HWCFGR1 + GPIOG_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOG_HWCFGR0 + GPIOG_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOG_VERR + GPIOG_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOG_IPIDR + GPIOG_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOG_SIDR + GPIOG_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOH + GPIOH + GPIOH + 0x50009000 + + 0x0 + 0x400 + registers + + + + GPIOH_MODER + GPIOH_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOH_OTYPER + GPIOH_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOH_OSPEEDR + GPIOH_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOH_PUPDR + GPIOH_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOH_IDR + GPIOH_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOH_ODR + GPIOH_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOH_BSRR + GPIOH_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOH_LCKR + GPIOH_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOH_AFRL + GPIOH_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOH_AFRH + GPIOH_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOH_BRR + GPIOH_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOH_HWCFGR10 + GPIOH_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOH_HWCFGR9 + GPIOH_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOH_HWCFGR8 + GPIOH_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOH_HWCFGR7 + GPIOH_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOH_HWCFGR6 + GPIOH_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOH_HWCFGR5 + GPIOH_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOH_HWCFGR4 + GPIOH_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOH_HWCFGR3 + GPIOH_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOH_HWCFGR2 + GPIOH_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOH_HWCFGR1 + GPIOH_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOH_HWCFGR0 + GPIOH_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOH_VERR + GPIOH_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOH_IPIDR + GPIOH_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOH_SIDR + GPIOH_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOI + GPIOI + GPIOI + 0x5000A000 + + 0x0 + 0x400 + registers + + + + GPIOI_MODER + GPIOI_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOI_OTYPER + GPIOI_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOI_OSPEEDR + GPIOI_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOI_PUPDR + GPIOI_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOI_IDR + GPIOI_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOI_ODR + GPIOI_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOI_BSRR + GPIOI_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOI_LCKR + GPIOI_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOI_AFRL + GPIOI_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOI_AFRH + GPIOI_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOI_BRR + GPIOI_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOI_HWCFGR10 + GPIOI_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOI_HWCFGR9 + GPIOI_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOI_HWCFGR8 + GPIOI_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOI_HWCFGR7 + GPIOI_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOI_HWCFGR6 + GPIOI_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOI_HWCFGR5 + GPIOI_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOI_HWCFGR4 + GPIOI_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOI_HWCFGR3 + GPIOI_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOI_HWCFGR2 + GPIOI_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOI_HWCFGR1 + GPIOI_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOI_HWCFGR0 + GPIOI_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOI_VERR + GPIOI_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOI_IPIDR + GPIOI_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOI_SIDR + GPIOI_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOJ + GPIOJ + GPIOJ + 0x5000B000 + + 0x0 + 0x400 + registers + + + + GPIOJ_MODER + GPIOJ_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOJ_OTYPER + GPIOJ_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOJ_OSPEEDR + GPIOJ_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOJ_PUPDR + GPIOJ_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOJ_IDR + GPIOJ_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOJ_ODR + GPIOJ_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOJ_BSRR + GPIOJ_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOJ_LCKR + GPIOJ_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOJ_AFRL + GPIOJ_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOJ_AFRH + GPIOJ_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOJ_BRR + GPIOJ_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOJ_HWCFGR10 + GPIOJ_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOJ_HWCFGR9 + GPIOJ_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOJ_HWCFGR8 + GPIOJ_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOJ_HWCFGR7 + GPIOJ_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOJ_HWCFGR6 + GPIOJ_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOJ_HWCFGR5 + GPIOJ_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOJ_HWCFGR4 + GPIOJ_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOJ_HWCFGR3 + GPIOJ_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOJ_HWCFGR2 + GPIOJ_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOJ_HWCFGR1 + GPIOJ_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOJ_HWCFGR0 + GPIOJ_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOJ_VERR + GPIOJ_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOJ_IPIDR + GPIOJ_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOJ_SIDR + GPIOJ_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOK + GPIOK + GPIOK + 0x5000C000 + + 0x0 + 0x400 + registers + + + + GPIOK_MODER + GPIOK_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOK_OTYPER + GPIOK_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOK_OSPEEDR + GPIOK_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOK_PUPDR + GPIOK_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOK_IDR + GPIOK_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOK_ODR + GPIOK_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOK_BSRR + GPIOK_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOK_LCKR + GPIOK_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOK_AFRL + GPIOK_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOK_AFRH + GPIOK_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOK_BRR + GPIOK_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOK_HWCFGR10 + GPIOK_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOK_HWCFGR9 + GPIOK_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOK_HWCFGR8 + GPIOK_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOK_HWCFGR7 + GPIOK_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOK_HWCFGR6 + GPIOK_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOK_HWCFGR5 + GPIOK_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOK_HWCFGR4 + GPIOK_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOK_HWCFGR3 + GPIOK_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOK_HWCFGR2 + GPIOK_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOK_HWCFGR1 + GPIOK_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOK_HWCFGR0 + GPIOK_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOK_VERR + GPIOK_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOK_IPIDR + GPIOK_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOK_SIDR + GPIOK_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + GPIOZ + GPIOZ + GPIOZ + 0x54004000 + + 0x0 + 0x400 + registers + + + + GPIOZ_MODER + GPIOZ_MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER0 + MODER0 + 0 + 2 + + + MODER1 + MODER1 + 2 + 2 + + + MODER2 + MODER2 + 4 + 2 + + + MODER3 + MODER3 + 6 + 2 + + + MODER4 + MODER4 + 8 + 2 + + + MODER5 + MODER5 + 10 + 2 + + + MODER6 + MODER6 + 12 + 2 + + + MODER7 + MODER7 + 14 + 2 + + + MODER8 + MODER8 + 16 + 2 + + + MODER9 + MODER9 + 18 + 2 + + + MODER10 + MODER10 + 20 + 2 + + + MODER11 + MODER11 + 22 + 2 + + + MODER12 + MODER12 + 24 + 2 + + + MODER13 + MODER13 + 26 + 2 + + + MODER14 + MODER14 + 28 + 2 + + + MODER15 + MODER15 + 30 + 2 + + + + + GPIOZ_OTYPER + GPIOZ_OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0 + 0 + 1 + + + OT1 + OT1 + 1 + 1 + + + OT2 + OT2 + 2 + 1 + + + OT3 + OT3 + 3 + 1 + + + OT4 + OT4 + 4 + 1 + + + OT5 + OT5 + 5 + 1 + + + OT6 + OT6 + 6 + 1 + + + OT7 + OT7 + 7 + 1 + + + OT8 + OT8 + 8 + 1 + + + OT9 + OT9 + 9 + 1 + + + OT10 + OT10 + 10 + 1 + + + OT11 + OT11 + 11 + 1 + + + OT12 + OT12 + 12 + 1 + + + OT13 + OT13 + 13 + 1 + + + OT14 + OT14 + 14 + 1 + + + OT15 + OT15 + 15 + 1 + + + + + GPIOZ_OSPEEDR + GPIOZ_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR0 + OSPEEDR0 + 0 + 2 + + + OSPEEDR1 + OSPEEDR1 + 2 + 2 + + + OSPEEDR2 + OSPEEDR2 + 4 + 2 + + + OSPEEDR3 + OSPEEDR3 + 6 + 2 + + + OSPEEDR4 + OSPEEDR4 + 8 + 2 + + + OSPEEDR5 + OSPEEDR5 + 10 + 2 + + + OSPEEDR6 + OSPEEDR6 + 12 + 2 + + + OSPEEDR7 + OSPEEDR7 + 14 + 2 + + + OSPEEDR8 + OSPEEDR8 + 16 + 2 + + + OSPEEDR9 + OSPEEDR9 + 18 + 2 + + + OSPEEDR10 + OSPEEDR10 + 20 + 2 + + + OSPEEDR11 + OSPEEDR11 + 22 + 2 + + + OSPEEDR12 + OSPEEDR12 + 24 + 2 + + + OSPEEDR13 + OSPEEDR13 + 26 + 2 + + + OSPEEDR14 + OSPEEDR14 + 28 + 2 + + + OSPEEDR15 + OSPEEDR15 + 30 + 2 + + + + + GPIOZ_PUPDR + GPIOZ_PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR0 + PUPDR0 + 0 + 2 + + + PUPDR1 + PUPDR1 + 2 + 2 + + + PUPDR2 + PUPDR2 + 4 + 2 + + + PUPDR3 + PUPDR3 + 6 + 2 + + + PUPDR4 + PUPDR4 + 8 + 2 + + + PUPDR5 + PUPDR5 + 10 + 2 + + + PUPDR6 + PUPDR6 + 12 + 2 + + + PUPDR7 + PUPDR7 + 14 + 2 + + + PUPDR8 + PUPDR8 + 16 + 2 + + + PUPDR9 + PUPDR9 + 18 + 2 + + + PUPDR10 + PUPDR10 + 20 + 2 + + + PUPDR11 + PUPDR11 + 22 + 2 + + + PUPDR12 + PUPDR12 + 24 + 2 + + + PUPDR13 + PUPDR13 + 26 + 2 + + + PUPDR14 + PUPDR14 + 28 + 2 + + + PUPDR15 + PUPDR15 + 30 + 2 + + + + + GPIOZ_IDR + GPIOZ_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR0 + IDR0 + 0 + 1 + + + IDR1 + IDR1 + 1 + 1 + + + IDR2 + IDR2 + 2 + 1 + + + IDR3 + IDR3 + 3 + 1 + + + IDR4 + IDR4 + 4 + 1 + + + IDR5 + IDR5 + 5 + 1 + + + IDR6 + IDR6 + 6 + 1 + + + IDR7 + IDR7 + 7 + 1 + + + IDR8 + IDR8 + 8 + 1 + + + IDR9 + IDR9 + 9 + 1 + + + IDR10 + IDR10 + 10 + 1 + + + IDR11 + IDR11 + 11 + 1 + + + IDR12 + IDR12 + 12 + 1 + + + IDR13 + IDR13 + 13 + 1 + + + IDR14 + IDR14 + 14 + 1 + + + IDR15 + IDR15 + 15 + 1 + + + + + GPIOZ_ODR + GPIOZ_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR0 + ODR0 + 0 + 1 + + + ODR1 + ODR1 + 1 + 1 + + + ODR2 + ODR2 + 2 + 1 + + + ODR3 + ODR3 + 3 + 1 + + + ODR4 + ODR4 + 4 + 1 + + + ODR5 + ODR5 + 5 + 1 + + + ODR6 + ODR6 + 6 + 1 + + + ODR7 + ODR7 + 7 + 1 + + + ODR8 + ODR8 + 8 + 1 + + + ODR9 + ODR9 + 9 + 1 + + + ODR10 + ODR10 + 10 + 1 + + + ODR11 + ODR11 + 11 + 1 + + + ODR12 + ODR12 + 12 + 1 + + + ODR13 + ODR13 + 13 + 1 + + + ODR14 + ODR14 + 14 + 1 + + + ODR15 + ODR15 + 15 + 1 + + + + + GPIOZ_BSRR + GPIOZ_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0 + 0 + 1 + + + BS1 + BS1 + 1 + 1 + + + BS2 + BS2 + 2 + 1 + + + BS3 + BS3 + 3 + 1 + + + BS4 + BS4 + 4 + 1 + + + BS5 + BS5 + 5 + 1 + + + BS6 + BS6 + 6 + 1 + + + BS7 + BS7 + 7 + 1 + + + BS8 + BS8 + 8 + 1 + + + BS9 + BS9 + 9 + 1 + + + BS10 + BS10 + 10 + 1 + + + BS11 + BS11 + 11 + 1 + + + BS12 + BS12 + 12 + 1 + + + BS13 + BS13 + 13 + 1 + + + BS14 + BS14 + 14 + 1 + + + BS15 + BS15 + 15 + 1 + + + BR0 + BR0 + 16 + 1 + + + BR1 + BR1 + 17 + 1 + + + BR2 + BR2 + 18 + 1 + + + BR3 + BR3 + 19 + 1 + + + BR4 + BR4 + 20 + 1 + + + BR5 + BR5 + 21 + 1 + + + BR6 + BR6 + 22 + 1 + + + BR7 + BR7 + 23 + 1 + + + BR8 + BR8 + 24 + 1 + + + BR9 + BR9 + 25 + 1 + + + BR10 + BR10 + 26 + 1 + + + BR11 + BR11 + 27 + 1 + + + BR12 + BR12 + 28 + 1 + + + BR13 + BR13 + 29 + 1 + + + BR14 + BR14 + 30 + 1 + + + BR15 + BR15 + 31 + 1 + + + + + GPIOZ_LCKR + GPIOZ_LCKR + This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0 + 0 + 1 + + + LCK1 + LCK1 + 1 + 1 + + + LCK2 + LCK2 + 2 + 1 + + + LCK3 + LCK3 + 3 + 1 + + + LCK4 + LCK4 + 4 + 1 + + + LCK5 + LCK5 + 5 + 1 + + + LCK6 + LCK6 + 6 + 1 + + + LCK7 + LCK7 + 7 + 1 + + + LCK8 + LCK8 + 8 + 1 + + + LCK9 + LCK9 + 9 + 1 + + + LCK10 + LCK10 + 10 + 1 + + + LCK11 + LCK11 + 11 + 1 + + + LCK12 + LCK12 + 12 + 1 + + + LCK13 + LCK13 + 13 + 1 + + + LCK14 + LCK14 + 14 + 1 + + + LCK15 + LCK15 + 15 + 1 + + + LCKK + LCKK + 16 + 1 + + + + + GPIOZ_AFRL + GPIOZ_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFR0 + AFR0 + 0 + 4 + + + AFR1 + AFR1 + 4 + 4 + + + AFR2 + AFR2 + 8 + 4 + + + AFR3 + AFR3 + 12 + 4 + + + AFR4 + AFR4 + 16 + 4 + + + AFR5 + AFR5 + 20 + 4 + + + AFR6 + AFR6 + 24 + 4 + + + AFR7 + AFR7 + 28 + 4 + + + + + GPIOZ_AFRH + GPIOZ_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFR8 + AFR8 + 0 + 4 + + + AFR9 + AFR9 + 4 + 4 + + + AFR10 + AFR10 + 8 + 4 + + + AFR11 + AFR11 + 12 + 4 + + + AFR12 + AFR12 + 16 + 4 + + + AFR13 + AFR13 + 20 + 4 + + + AFR14 + AFR14 + 24 + 4 + + + AFR15 + AFR15 + 28 + 4 + + + + + GPIOZ_BRR + GPIOZ_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + BR0 + 0 + 1 + + + BR1 + BR1 + 1 + 1 + + + BR2 + BR2 + 2 + 1 + + + BR3 + BR3 + 3 + 1 + + + BR4 + BR4 + 4 + 1 + + + BR5 + BR5 + 5 + 1 + + + BR6 + BR6 + 6 + 1 + + + BR7 + BR7 + 7 + 1 + + + BR8 + BR8 + 8 + 1 + + + BR9 + BR9 + 9 + 1 + + + BR10 + BR10 + 10 + 1 + + + BR11 + BR11 + 11 + 1 + + + BR12 + BR12 + 12 + 1 + + + BR13 + BR13 + 13 + 1 + + + BR14 + BR14 + 14 + 1 + + + BR15 + BR15 + 15 + 1 + + + + + GPIOZ_SECCFGR + GPIOZ_SECCFGR + This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded. + 0x30 + 0x20 + write-only + 0x000000FF + + + SEC0 + SEC0 + 0 + 1 + + + SEC1 + SEC1 + 1 + 1 + + + SEC2 + SEC2 + 2 + 1 + + + SEC3 + SEC3 + 3 + 1 + + + SEC4 + SEC4 + 4 + 1 + + + SEC5 + SEC5 + 5 + 1 + + + SEC6 + SEC6 + 6 + 1 + + + SEC7 + SEC7 + 7 + 1 + + + + + GPIOZ_HWCFGR10 + GPIOZ_HWCFGR10 + For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: + 0x3C8 + 0x20 + read-only + 0x00011240 + + + AHB_IOP + AHB_IOP + 0 + 4 + + + AF_SIZE + AF_SIZE + 4 + 4 + + + SPEED_CFG + SPEED_CFG + 8 + 4 + + + LOCK_CFG + LOCK_CFG + 12 + 4 + + + SEC_CFG + SEC_CFG + 16 + 4 + + + OR_CFG + OR_CFG + 20 + 4 + + + + + GPIOZ_HWCFGR9 + GPIOZ_HWCFGR9 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3CC + 0x20 + read-only + 0x000000FF + + + EN_IO + EN_IO + 0 + 16 + + + + + GPIOZ_HWCFGR8 + GPIOZ_HWCFGR8 + For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: + 0x3D0 + 0x20 + read-only + 0x00000000 + + + AF_PRIO8 + AF_PRIO8 + 0 + 4 + + + AF_PRIO9 + AF_PRIO9 + 4 + 4 + + + AF_PRIO10 + AF_PRIO10 + 8 + 4 + + + AF_PRIO11 + AF_PRIO11 + 12 + 4 + + + AF_PRIO12 + AF_PRIO12 + 16 + 4 + + + AF_PRIO13 + AF_PRIO13 + 20 + 4 + + + AF_PRIO14 + AF_PRIO14 + 24 + 4 + + + AF_PRIO15 + AF_PRIO15 + 28 + 4 + + + + + GPIOZ_HWCFGR7 + GPIOZ_HWCFGR7 + GPIO hardware configuration register 7 + 0x3D4 + 0x20 + read-only + 0xFFFFFFFF + + + AF_PRIO0 + AF_PRIO0 + 0 + 4 + + + AF_PRIO1 + AF_PRIO1 + 4 + 4 + + + AF_PRIO2 + AF_PRIO2 + 8 + 4 + + + AF_PRIO3 + AF_PRIO3 + 12 + 4 + + + AF_PRIO4 + AF_PRIO4 + 16 + 4 + + + AF_PRIO5 + AF_PRIO5 + 20 + 4 + + + AF_PRIO6 + AF_PRIO6 + 24 + 4 + + + AF_PRIO7 + AF_PRIO7 + 28 + 4 + + + + + GPIOZ_HWCFGR6 + GPIOZ_HWCFGR6 + GPIO hardware configuration register 6 + 0x3D8 + 0x20 + read-only + 0xFFFFFFFF + + + MODER_RES + MODER_RES + 0 + 32 + + + + + GPIOZ_HWCFGR5 + GPIOZ_HWCFGR5 + GPIO hardware configuration register 5 + 0x3DC + 0x20 + read-only + 0x00000000 + + + PUPDR_RES + PUPDR_RES + 0 + 32 + + + + + GPIOZ_HWCFGR4 + GPIOZ_HWCFGR4 + GPIO hardware configuration register 4 + 0x3E0 + 0x20 + read-only + 0x00000000 + + + OSPEED_RES + OSPEED_RES + 0 + 32 + + + + + GPIOZ_HWCFGR3 + GPIOZ_HWCFGR3 + GPIO hardware configuration register 3 + 0x3E4 + 0x20 + read-only + 0x00000000 + + + ODR_RES + ODR_RES + 0 + 16 + + + OTYPER_RES + OTYPER_RES + 16 + 16 + + + + + GPIOZ_HWCFGR2 + GPIOZ_HWCFGR2 + GPIO hardware configuration register 2 + 0x3E8 + 0x20 + read-only + 0x00000000 + + + AFRL_RES + AFRL_RES + 0 + 32 + + + + + GPIOZ_HWCFGR1 + GPIOZ_HWCFGR1 + GPIO hardware configuration register 1 + 0x3EC + 0x20 + read-only + 0x00000000 + + + AFRH_RES + AFRH_RES + 0 + 32 + + + + + GPIOZ_HWCFGR0 + GPIOZ_HWCFGR0 + GPIO hardware configuration register 0 + 0x3F0 + 0x20 + read-only + 0x00000000 + + + OR_RES + OR_RES + 0 + 16 + + + + + GPIOZ_VERR + GPIOZ_VERR + GPIO version register + 0x3F4 + 0x20 + read-only + 0x00000040 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + GPIOZ_IPIDR + GPIOZ_IPIDR + GPIO identification register + 0x3F8 + 0x20 + read-only + 0x000F0002 + + + IPIDR + IPIDR + 0 + 32 + + + + + GPIOZ_SIDR + GPIOZ_SIDR + GPIO size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SIDR + SIDR + 0 + 32 + + + + + + + RNG1 + RNG1 + RNG1 + 0x54003000 + + 0x0 + 0x400 + registers + + + + RNG_CR + RNG_CR + RNG control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + RNGEN + 2 + 1 + + + IE + IE + 3 + 1 + + + CED + CED + 5 + 1 + + + + + RNG_SR + RNG_SR + RNG status register + 0x4 + 0x20 + 0x00000000 + + + DRDY + DRDY + 0 + 1 + read-only + + + CECS + CECS + 1 + 1 + read-only + + + SECS + SECS + 2 + 1 + read-only + + + CEIS + CEIS + 5 + 1 + read-write + + + SEIS + SEIS + 6 + 1 + read-write + + + + + RNG_DR + RNG_DR + The RNG_DR register is a read-only register. + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + RNDATA + 0 + 32 + + + + + RNG_HWCFGR + RNG_HWCFGR + RNG hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000006 + + + RNG_VERR + RNG_VERR + RNG version register + 0x3F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + RNG_IPIDR + RNG_IPIDR + RNG identification register + 0x3F8 + 0x20 + read-only + 0x00170041 + + + ID + ID + 0 + 32 + + + + + RNG_SIDR + RNG_SIDR + RNG size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + RNG2 + RNG2 + RNG2 + 0x4C003000 + + 0x0 + 0x400 + registers + + + + RNG_CR + RNG_CR + RNG control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + RNGEN + 2 + 1 + + + IE + IE + 3 + 1 + + + CED + CED + 5 + 1 + + + + + RNG_SR + RNG_SR + RNG status register + 0x4 + 0x20 + 0x00000000 + + + DRDY + DRDY + 0 + 1 + read-only + + + CECS + CECS + 1 + 1 + read-only + + + SECS + SECS + 2 + 1 + read-only + + + CEIS + CEIS + 5 + 1 + read-write + + + SEIS + SEIS + 6 + 1 + read-write + + + + + RNG_DR + RNG_DR + The RNG_DR register is a read-only register. + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + RNDATA + 0 + 32 + + + + + RNG_HWCFGR + RNG_HWCFGR + RNG hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000006 + + + RNG_VERR + RNG_VERR + RNG version register + 0x3F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + RNG_IPIDR + RNG_IPIDR + RNG identification register + 0x3F8 + 0x20 + read-only + 0x00170041 + + + ID + ID + 0 + 32 + + + + + RNG_SIDR + RNG_SIDR + RNG size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + HASH1 + HASH register block + HASH + 0x54002000 + + 0x0 + 0x400 + registers + + + + HASH_CR + HASH_CR + HASH control register + 0x0 + 0x20 + 0x00000000 + + + INIT + INIT + 2 + 1 + write-only + + + DMAE + DMAE + 3 + 1 + read-write + + + DATATYPE + DATATYPE + 4 + 2 + read-write + + + MODE + MODE + 6 + 1 + read-write + + + ALGO0 + ALGO0 + 7 + 1 + read-write + + + NBW + NBW + 8 + 4 + read-only + + + DINNE + DINNE + 12 + 1 + read-only + + + MDMAT + MDMAT + 13 + 1 + read-write + + + DMAA + DMAA + 14 + 1 + write-only + + + LKEY + LKEY + 16 + 1 + read-write + + + ALGO1 + ALGO1 + 18 + 1 + read-write + + + + + HASH_DIN + HASH_DIN + HASH_DIN is the data input register. + 0x4 + 0x20 + read-write + 0x00000000 + + + DATAIN + DATAIN + 0 + 32 + + + + + HASH_STR + HASH_STR + The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 + 0x8 + 0x20 + 0x00000000 + + + NBLW + NBLW + 0 + 5 + read-write + + + DCAL + DCAL + 8 + 1 + write-only + + + + + HASH_HR0 + HASH_HR0 + HASH digest register 0 + 0xC + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HASH_HR1 + HASH_HR1 + HASH digest register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HASH_HR2 + HASH_HR2 + HASH digest register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HASH_HR3 + HASH_HR3 + HASH digest register 3 + 0x18 + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HASH_HR4 + HASH_HR4 + HASH digest register 4 + 0x1C + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + HASH_IMR + HASH_IMR + HASH interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DINIE + DINIE + 0 + 1 + + + DCIE + DCIE + 1 + 1 + + + + + HASH_SR + HASH_SR + HASH status register + 0x24 + 0x20 + 0x00000001 + + + DINIS + DINIS + 0 + 1 + read-write + + + DCIS + DCIS + 1 + 1 + read-write + + + DMAS + DMAS + 2 + 1 + read-only + + + BUSY + BUSY + 3 + 1 + read-only + + + + + HASH_CSR0 + HASH_CSR0 + These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. + 0xF8 + 0x20 + read-write + 0x00000002 + + + CS0 + CS0 + 0 + 32 + + + + + HASH_CSR1 + HASH_CSR1 + HASH context swap registers + 0xFC + 0x20 + read-write + 0x00000000 + + + CS1 + CS1 + 0 + 32 + + + + + HASH_CSR2 + HASH_CSR2 + HASH context swap registers + 0x100 + 0x20 + read-write + 0x00000000 + + + CS2 + CS2 + 0 + 32 + + + + + HASH_CSR3 + HASH_CSR3 + HASH context swap registers + 0x104 + 0x20 + read-write + 0x00000000 + + + CS3 + CS3 + 0 + 32 + + + + + HASH_CSR4 + HASH_CSR4 + HASH context swap registers + 0x108 + 0x20 + read-write + 0x00000000 + + + CS4 + CS4 + 0 + 32 + + + + + HASH_CSR5 + HASH_CSR5 + HASH context swap registers + 0x10C + 0x20 + read-write + 0x00000000 + + + CS5 + CS5 + 0 + 32 + + + + + HASH_CSR6 + HASH_CSR6 + HASH context swap registers + 0x110 + 0x20 + read-write + 0x00000000 + + + CS6 + CS6 + 0 + 32 + + + + + HASH_CSR7 + HASH_CSR7 + HASH context swap registers + 0x114 + 0x20 + read-write + 0x00000000 + + + CS7 + CS7 + 0 + 32 + + + + + HASH_CSR8 + HASH_CSR8 + HASH context swap registers + 0x118 + 0x20 + read-write + 0x00000000 + + + CS8 + CS8 + 0 + 32 + + + + + HASH_CSR9 + HASH_CSR9 + HASH context swap registers + 0x11C + 0x20 + read-write + 0x00000000 + + + CS9 + CS9 + 0 + 32 + + + + + HASH_CSR10 + HASH_CSR10 + HASH context swap registers + 0x120 + 0x20 + read-write + 0x00000000 + + + CS10 + CS10 + 0 + 32 + + + + + HASH_CSR11 + HASH_CSR11 + HASH context swap registers + 0x124 + 0x20 + read-write + 0x00000000 + + + CS11 + CS11 + 0 + 32 + + + + + HASH_CSR12 + HASH_CSR12 + HASH context swap registers + 0x128 + 0x20 + read-write + 0x00000000 + + + CS12 + CS12 + 0 + 32 + + + + + HASH_CSR13 + HASH_CSR13 + HASH context swap registers + 0x12C + 0x20 + read-write + 0x00000000 + + + CS13 + CS13 + 0 + 32 + + + + + HASH_CSR14 + HASH_CSR14 + HASH context swap registers + 0x130 + 0x20 + read-write + 0x00000000 + + + CS14 + CS14 + 0 + 32 + + + + + HASH_CSR15 + HASH_CSR15 + HASH context swap registers + 0x134 + 0x20 + read-write + 0x00000000 + + + CS15 + CS15 + 0 + 32 + + + + + HASH_CSR16 + HASH_CSR16 + HASH context swap registers + 0x138 + 0x20 + read-write + 0x00000000 + + + CS16 + CS16 + 0 + 32 + + + + + HASH_CSR17 + HASH_CSR17 + HASH context swap registers + 0x13C + 0x20 + read-write + 0x00000000 + + + CS17 + CS17 + 0 + 32 + + + + + HASH_CSR18 + HASH_CSR18 + HASH context swap registers + 0x140 + 0x20 + read-write + 0x00000000 + + + CS18 + CS18 + 0 + 32 + + + + + HASH_CSR19 + HASH_CSR19 + HASH context swap registers + 0x144 + 0x20 + read-write + 0x00000000 + + + CS19 + CS19 + 0 + 32 + + + + + HASH_CSR20 + HASH_CSR20 + HASH context swap registers + 0x148 + 0x20 + read-write + 0x00000000 + + + CS20 + CS20 + 0 + 32 + + + + + HASH_CSR21 + HASH_CSR21 + HASH context swap registers + 0x14C + 0x20 + read-write + 0x00000000 + + + CS21 + CS21 + 0 + 32 + + + + + HASH_CSR22 + HASH_CSR22 + HASH context swap registers + 0x150 + 0x20 + read-write + 0x00000000 + + + CS22 + CS22 + 0 + 32 + + + + + HASH_CSR23 + HASH_CSR23 + HASH context swap registers + 0x154 + 0x20 + read-write + 0x00000000 + + + CS23 + CS23 + 0 + 32 + + + + + HASH_CSR24 + HASH_CSR24 + HASH context swap registers + 0x158 + 0x20 + read-write + 0x00000000 + + + CS24 + CS24 + 0 + 32 + + + + + HASH_CSR25 + HASH_CSR25 + HASH context swap registers + 0x15C + 0x20 + read-write + 0x00000000 + + + CS25 + CS25 + 0 + 32 + + + + + HASH_CSR26 + HASH_CSR26 + HASH context swap registers + 0x160 + 0x20 + read-write + 0x00000000 + + + CS26 + CS26 + 0 + 32 + + + + + HASH_CSR27 + HASH_CSR27 + HASH context swap registers + 0x164 + 0x20 + read-write + 0x00000000 + + + CS27 + CS27 + 0 + 32 + + + + + HASH_CSR28 + HASH_CSR28 + HASH context swap registers + 0x168 + 0x20 + read-write + 0x00000000 + + + CS28 + CS28 + 0 + 32 + + + + + HASH_CSR29 + HASH_CSR29 + HASH context swap registers + 0x16C + 0x20 + read-write + 0x00000000 + + + CS29 + CS29 + 0 + 32 + + + + + HASH_CSR30 + HASH_CSR30 + HASH context swap registers + 0x170 + 0x20 + read-write + 0x00000000 + + + CS30 + CS30 + 0 + 32 + + + + + HASH_CSR31 + HASH_CSR31 + HASH context swap registers + 0x174 + 0x20 + read-write + 0x00000000 + + + CS31 + CS31 + 0 + 32 + + + + + HASH_CSR32 + HASH_CSR32 + HASH context swap registers + 0x178 + 0x20 + read-write + 0x00000000 + + + CS32 + CS32 + 0 + 32 + + + + + HASH_CSR33 + HASH_CSR33 + HASH context swap registers + 0x17C + 0x20 + read-write + 0x00000000 + + + CS33 + CS33 + 0 + 32 + + + + + HASH_CSR34 + HASH_CSR34 + HASH context swap registers + 0x180 + 0x20 + read-write + 0x00000000 + + + CS34 + CS34 + 0 + 32 + + + + + HASH_CSR35 + HASH_CSR35 + HASH context swap registers + 0x184 + 0x20 + read-write + 0x00000000 + + + CS35 + CS35 + 0 + 32 + + + + + HASH_CSR36 + HASH_CSR36 + HASH context swap registers + 0x188 + 0x20 + read-write + 0x00000000 + + + CS36 + CS36 + 0 + 32 + + + + + HASH_CSR37 + HASH_CSR37 + HASH context swap registers + 0x18C + 0x20 + read-write + 0x00000000 + + + CS37 + CS37 + 0 + 32 + + + + + HASH_CSR38 + HASH_CSR38 + HASH context swap registers + 0x190 + 0x20 + read-write + 0x00000000 + + + CS38 + CS38 + 0 + 32 + + + + + HASH_CSR39 + HASH_CSR39 + HASH context swap registers + 0x194 + 0x20 + read-write + 0x00000000 + + + CS39 + CS39 + 0 + 32 + + + + + HASH_CSR40 + HASH_CSR40 + HASH context swap registers + 0x198 + 0x20 + read-write + 0x00000000 + + + CS40 + CS40 + 0 + 32 + + + + + HASH_CSR41 + HASH_CSR41 + HASH context swap registers + 0x19C + 0x20 + read-write + 0x00000000 + + + CS41 + CS41 + 0 + 32 + + + + + HASH_CSR42 + HASH_CSR42 + HASH context swap registers + 0x1A0 + 0x20 + read-write + 0x00000000 + + + CS42 + CS42 + 0 + 32 + + + + + HASH_CSR43 + HASH_CSR43 + HASH context swap registers + 0x1A4 + 0x20 + read-write + 0x00000000 + + + CS43 + CS43 + 0 + 32 + + + + + HASH_CSR44 + HASH_CSR44 + HASH context swap registers + 0x1A8 + 0x20 + read-write + 0x00000000 + + + CS44 + CS44 + 0 + 32 + + + + + HASH_CSR45 + HASH_CSR45 + HASH context swap registers + 0x1AC + 0x20 + read-write + 0x00000000 + + + CS45 + CS45 + 0 + 32 + + + + + HASH_CSR46 + HASH_CSR46 + HASH context swap registers + 0x1B0 + 0x20 + read-write + 0x00000000 + + + CS46 + CS46 + 0 + 32 + + + + + HASH_CSR47 + HASH_CSR47 + HASH context swap registers + 0x1B4 + 0x20 + read-write + 0x00000000 + + + CS47 + CS47 + 0 + 32 + + + + + HASH_CSR48 + HASH_CSR48 + HASH context swap registers + 0x1B8 + 0x20 + read-write + 0x00000000 + + + CS48 + CS48 + 0 + 32 + + + + + HASH_CSR49 + HASH_CSR49 + HASH context swap registers + 0x1BC + 0x20 + read-write + 0x00000000 + + + CS49 + CS49 + 0 + 32 + + + + + HASH_CSR50 + HASH_CSR50 + HASH context swap registers + 0x1C0 + 0x20 + read-write + 0x00000000 + + + CS50 + CS50 + 0 + 32 + + + + + HASH_CSR51 + HASH_CSR51 + HASH context swap registers + 0x1C4 + 0x20 + read-write + 0x00000000 + + + CS51 + CS51 + 0 + 32 + + + + + HASH_CSR52 + HASH_CSR52 + HASH context swap registers + 0x1C8 + 0x20 + read-write + 0x00000000 + + + CS52 + CS52 + 0 + 32 + + + + + HASH_CSR53 + HASH_CSR53 + HASH context swap registers + 0x1CC + 0x20 + read-write + 0x00000000 + + + CS53 + CS53 + 0 + 32 + + + + + HASH_HR5 + HASH_HR5 + HASH digest register 5 + 0x324 + 0x20 + read-only + 0x00000000 + + + H5 + H5 + 0 + 32 + + + + + HASH_HR6 + HASH_HR6 + HASH digest register 6 + 0x328 + 0x20 + read-only + 0x00000000 + + + H6 + H6 + 0 + 32 + + + + + HASH_HR7 + HASH_HR7 + HASH digest register 7 + 0x32C + 0x20 + read-only + 0x00000000 + + + H7 + H7 + 0 + 32 + + + + + HASH_HWCFGR + HASH_HWCFGR + HASH Hardware Configuration Register + 0x3F0 + 0x20 + read-only + 0x00000001 + + + CFG1 + CFG1 + 0 + 4 + + + + + HASH_VERR + HASH_VERR + HASH Version Register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + VER + VER + 0 + 8 + + + + + HASH_IPIDR + HASH_IPIDR + HASH Identification + 0x3F8 + 0x20 + read-only + 0x00170031 + + + ID + ID + 0 + 32 + + + + + HASH_MID + HASH_MID + HASH Hardware Magic ID + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + MID + MID + 0 + 32 + + + + + + + HASH2 + HASH register block + HASH + 0x4C002000 + + 0x0 + 0x400 + registers + + + + HASH_CR + HASH_CR + HASH control register + 0x0 + 0x20 + 0x00000000 + + + INIT + INIT + 2 + 1 + write-only + + + DMAE + DMAE + 3 + 1 + read-write + + + DATATYPE + DATATYPE + 4 + 2 + read-write + + + MODE + MODE + 6 + 1 + read-write + + + ALGO0 + ALGO0 + 7 + 1 + read-write + + + NBW + NBW + 8 + 4 + read-only + + + DINNE + DINNE + 12 + 1 + read-only + + + MDMAT + MDMAT + 13 + 1 + read-write + + + DMAA + DMAA + 14 + 1 + write-only + + + LKEY + LKEY + 16 + 1 + read-write + + + ALGO1 + ALGO1 + 18 + 1 + read-write + + + + + HASH_DIN + HASH_DIN + HASH_DIN is the data input register. + 0x4 + 0x20 + read-write + 0x00000000 + + + DATAIN + DATAIN + 0 + 32 + + + + + HASH_STR + HASH_STR + The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 + 0x8 + 0x20 + 0x00000000 + + + NBLW + NBLW + 0 + 5 + read-write + + + DCAL + DCAL + 8 + 1 + write-only + + + + + HASH_HR0 + HASH_HR0 + HASH digest register 0 + 0xC + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HASH_HR1 + HASH_HR1 + HASH digest register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HASH_HR2 + HASH_HR2 + HASH digest register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HASH_HR3 + HASH_HR3 + HASH digest register 3 + 0x18 + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HASH_HR4 + HASH_HR4 + HASH digest register 4 + 0x1C + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + HASH_IMR + HASH_IMR + HASH interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DINIE + DINIE + 0 + 1 + + + DCIE + DCIE + 1 + 1 + + + + + HASH_SR + HASH_SR + HASH status register + 0x24 + 0x20 + 0x00000001 + + + DINIS + DINIS + 0 + 1 + read-write + + + DCIS + DCIS + 1 + 1 + read-write + + + DMAS + DMAS + 2 + 1 + read-only + + + BUSY + BUSY + 3 + 1 + read-only + + + + + HASH_CSR0 + HASH_CSR0 + These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. + 0xF8 + 0x20 + read-write + 0x00000002 + + + CS0 + CS0 + 0 + 32 + + + + + HASH_CSR1 + HASH_CSR1 + HASH context swap registers + 0xFC + 0x20 + read-write + 0x00000000 + + + CS1 + CS1 + 0 + 32 + + + + + HASH_CSR2 + HASH_CSR2 + HASH context swap registers + 0x100 + 0x20 + read-write + 0x00000000 + + + CS2 + CS2 + 0 + 32 + + + + + HASH_CSR3 + HASH_CSR3 + HASH context swap registers + 0x104 + 0x20 + read-write + 0x00000000 + + + CS3 + CS3 + 0 + 32 + + + + + HASH_CSR4 + HASH_CSR4 + HASH context swap registers + 0x108 + 0x20 + read-write + 0x00000000 + + + CS4 + CS4 + 0 + 32 + + + + + HASH_CSR5 + HASH_CSR5 + HASH context swap registers + 0x10C + 0x20 + read-write + 0x00000000 + + + CS5 + CS5 + 0 + 32 + + + + + HASH_CSR6 + HASH_CSR6 + HASH context swap registers + 0x110 + 0x20 + read-write + 0x00000000 + + + CS6 + CS6 + 0 + 32 + + + + + HASH_CSR7 + HASH_CSR7 + HASH context swap registers + 0x114 + 0x20 + read-write + 0x00000000 + + + CS7 + CS7 + 0 + 32 + + + + + HASH_CSR8 + HASH_CSR8 + HASH context swap registers + 0x118 + 0x20 + read-write + 0x00000000 + + + CS8 + CS8 + 0 + 32 + + + + + HASH_CSR9 + HASH_CSR9 + HASH context swap registers + 0x11C + 0x20 + read-write + 0x00000000 + + + CS9 + CS9 + 0 + 32 + + + + + HASH_CSR10 + HASH_CSR10 + HASH context swap registers + 0x120 + 0x20 + read-write + 0x00000000 + + + CS10 + CS10 + 0 + 32 + + + + + HASH_CSR11 + HASH_CSR11 + HASH context swap registers + 0x124 + 0x20 + read-write + 0x00000000 + + + CS11 + CS11 + 0 + 32 + + + + + HASH_CSR12 + HASH_CSR12 + HASH context swap registers + 0x128 + 0x20 + read-write + 0x00000000 + + + CS12 + CS12 + 0 + 32 + + + + + HASH_CSR13 + HASH_CSR13 + HASH context swap registers + 0x12C + 0x20 + read-write + 0x00000000 + + + CS13 + CS13 + 0 + 32 + + + + + HASH_CSR14 + HASH_CSR14 + HASH context swap registers + 0x130 + 0x20 + read-write + 0x00000000 + + + CS14 + CS14 + 0 + 32 + + + + + HASH_CSR15 + HASH_CSR15 + HASH context swap registers + 0x134 + 0x20 + read-write + 0x00000000 + + + CS15 + CS15 + 0 + 32 + + + + + HASH_CSR16 + HASH_CSR16 + HASH context swap registers + 0x138 + 0x20 + read-write + 0x00000000 + + + CS16 + CS16 + 0 + 32 + + + + + HASH_CSR17 + HASH_CSR17 + HASH context swap registers + 0x13C + 0x20 + read-write + 0x00000000 + + + CS17 + CS17 + 0 + 32 + + + + + HASH_CSR18 + HASH_CSR18 + HASH context swap registers + 0x140 + 0x20 + read-write + 0x00000000 + + + CS18 + CS18 + 0 + 32 + + + + + HASH_CSR19 + HASH_CSR19 + HASH context swap registers + 0x144 + 0x20 + read-write + 0x00000000 + + + CS19 + CS19 + 0 + 32 + + + + + HASH_CSR20 + HASH_CSR20 + HASH context swap registers + 0x148 + 0x20 + read-write + 0x00000000 + + + CS20 + CS20 + 0 + 32 + + + + + HASH_CSR21 + HASH_CSR21 + HASH context swap registers + 0x14C + 0x20 + read-write + 0x00000000 + + + CS21 + CS21 + 0 + 32 + + + + + HASH_CSR22 + HASH_CSR22 + HASH context swap registers + 0x150 + 0x20 + read-write + 0x00000000 + + + CS22 + CS22 + 0 + 32 + + + + + HASH_CSR23 + HASH_CSR23 + HASH context swap registers + 0x154 + 0x20 + read-write + 0x00000000 + + + CS23 + CS23 + 0 + 32 + + + + + HASH_CSR24 + HASH_CSR24 + HASH context swap registers + 0x158 + 0x20 + read-write + 0x00000000 + + + CS24 + CS24 + 0 + 32 + + + + + HASH_CSR25 + HASH_CSR25 + HASH context swap registers + 0x15C + 0x20 + read-write + 0x00000000 + + + CS25 + CS25 + 0 + 32 + + + + + HASH_CSR26 + HASH_CSR26 + HASH context swap registers + 0x160 + 0x20 + read-write + 0x00000000 + + + CS26 + CS26 + 0 + 32 + + + + + HASH_CSR27 + HASH_CSR27 + HASH context swap registers + 0x164 + 0x20 + read-write + 0x00000000 + + + CS27 + CS27 + 0 + 32 + + + + + HASH_CSR28 + HASH_CSR28 + HASH context swap registers + 0x168 + 0x20 + read-write + 0x00000000 + + + CS28 + CS28 + 0 + 32 + + + + + HASH_CSR29 + HASH_CSR29 + HASH context swap registers + 0x16C + 0x20 + read-write + 0x00000000 + + + CS29 + CS29 + 0 + 32 + + + + + HASH_CSR30 + HASH_CSR30 + HASH context swap registers + 0x170 + 0x20 + read-write + 0x00000000 + + + CS30 + CS30 + 0 + 32 + + + + + HASH_CSR31 + HASH_CSR31 + HASH context swap registers + 0x174 + 0x20 + read-write + 0x00000000 + + + CS31 + CS31 + 0 + 32 + + + + + HASH_CSR32 + HASH_CSR32 + HASH context swap registers + 0x178 + 0x20 + read-write + 0x00000000 + + + CS32 + CS32 + 0 + 32 + + + + + HASH_CSR33 + HASH_CSR33 + HASH context swap registers + 0x17C + 0x20 + read-write + 0x00000000 + + + CS33 + CS33 + 0 + 32 + + + + + HASH_CSR34 + HASH_CSR34 + HASH context swap registers + 0x180 + 0x20 + read-write + 0x00000000 + + + CS34 + CS34 + 0 + 32 + + + + + HASH_CSR35 + HASH_CSR35 + HASH context swap registers + 0x184 + 0x20 + read-write + 0x00000000 + + + CS35 + CS35 + 0 + 32 + + + + + HASH_CSR36 + HASH_CSR36 + HASH context swap registers + 0x188 + 0x20 + read-write + 0x00000000 + + + CS36 + CS36 + 0 + 32 + + + + + HASH_CSR37 + HASH_CSR37 + HASH context swap registers + 0x18C + 0x20 + read-write + 0x00000000 + + + CS37 + CS37 + 0 + 32 + + + + + HASH_CSR38 + HASH_CSR38 + HASH context swap registers + 0x190 + 0x20 + read-write + 0x00000000 + + + CS38 + CS38 + 0 + 32 + + + + + HASH_CSR39 + HASH_CSR39 + HASH context swap registers + 0x194 + 0x20 + read-write + 0x00000000 + + + CS39 + CS39 + 0 + 32 + + + + + HASH_CSR40 + HASH_CSR40 + HASH context swap registers + 0x198 + 0x20 + read-write + 0x00000000 + + + CS40 + CS40 + 0 + 32 + + + + + HASH_CSR41 + HASH_CSR41 + HASH context swap registers + 0x19C + 0x20 + read-write + 0x00000000 + + + CS41 + CS41 + 0 + 32 + + + + + HASH_CSR42 + HASH_CSR42 + HASH context swap registers + 0x1A0 + 0x20 + read-write + 0x00000000 + + + CS42 + CS42 + 0 + 32 + + + + + HASH_CSR43 + HASH_CSR43 + HASH context swap registers + 0x1A4 + 0x20 + read-write + 0x00000000 + + + CS43 + CS43 + 0 + 32 + + + + + HASH_CSR44 + HASH_CSR44 + HASH context swap registers + 0x1A8 + 0x20 + read-write + 0x00000000 + + + CS44 + CS44 + 0 + 32 + + + + + HASH_CSR45 + HASH_CSR45 + HASH context swap registers + 0x1AC + 0x20 + read-write + 0x00000000 + + + CS45 + CS45 + 0 + 32 + + + + + HASH_CSR46 + HASH_CSR46 + HASH context swap registers + 0x1B0 + 0x20 + read-write + 0x00000000 + + + CS46 + CS46 + 0 + 32 + + + + + HASH_CSR47 + HASH_CSR47 + HASH context swap registers + 0x1B4 + 0x20 + read-write + 0x00000000 + + + CS47 + CS47 + 0 + 32 + + + + + HASH_CSR48 + HASH_CSR48 + HASH context swap registers + 0x1B8 + 0x20 + read-write + 0x00000000 + + + CS48 + CS48 + 0 + 32 + + + + + HASH_CSR49 + HASH_CSR49 + HASH context swap registers + 0x1BC + 0x20 + read-write + 0x00000000 + + + CS49 + CS49 + 0 + 32 + + + + + HASH_CSR50 + HASH_CSR50 + HASH context swap registers + 0x1C0 + 0x20 + read-write + 0x00000000 + + + CS50 + CS50 + 0 + 32 + + + + + HASH_CSR51 + HASH_CSR51 + HASH context swap registers + 0x1C4 + 0x20 + read-write + 0x00000000 + + + CS51 + CS51 + 0 + 32 + + + + + HASH_CSR52 + HASH_CSR52 + HASH context swap registers + 0x1C8 + 0x20 + read-write + 0x00000000 + + + CS52 + CS52 + 0 + 32 + + + + + HASH_CSR53 + HASH_CSR53 + HASH context swap registers + 0x1CC + 0x20 + read-write + 0x00000000 + + + CS53 + CS53 + 0 + 32 + + + + + HASH_HR5 + HASH_HR5 + HASH digest register 5 + 0x324 + 0x20 + read-only + 0x00000000 + + + H5 + H5 + 0 + 32 + + + + + HASH_HR6 + HASH_HR6 + HASH digest register 6 + 0x328 + 0x20 + read-only + 0x00000000 + + + H6 + H6 + 0 + 32 + + + + + HASH_HR7 + HASH_HR7 + HASH digest register 7 + 0x32C + 0x20 + read-only + 0x00000000 + + + H7 + H7 + 0 + 32 + + + + + HASH_HWCFGR + HASH_HWCFGR + HASH Hardware Configuration Register + 0x3F0 + 0x20 + read-only + 0x00000001 + + + CFG1 + CFG1 + 0 + 4 + + + + + HASH_VERR + HASH_VERR + HASH Version Register + 0x3F4 + 0x20 + read-only + 0x00000023 + + + VER + VER + 0 + 8 + + + + + HASH_IPIDR + HASH_IPIDR + HASH Identification + 0x3F8 + 0x20 + read-only + 0x00170031 + + + ID + ID + 0 + 32 + + + + + HASH_MID + HASH_MID + HASH Hardware Magic ID + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + MID + MID + 0 + 32 + + + + + + + HSEM + HSEM + HSEM_IPXACT + 0x4C000000 + + 0x0 + 0x400 + registers + + + + HSEM_R0 + HSEM_R0 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x0 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R1 + HSEM_R1 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x4 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R2 + HSEM_R2 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x8 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R3 + HSEM_R3 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0xC + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R4 + HSEM_R4 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x10 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R5 + HSEM_R5 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x14 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R6 + HSEM_R6 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x18 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R7 + HSEM_R7 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x1C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R8 + HSEM_R8 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x20 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R9 + HSEM_R9 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x24 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R10 + HSEM_R10 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x28 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R11 + HSEM_R11 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x2C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R12 + HSEM_R12 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x30 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R13 + HSEM_R13 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x34 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R14 + HSEM_R14 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x38 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R15 + HSEM_R15 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x3C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R16 + HSEM_R16 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x40 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R17 + HSEM_R17 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x44 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R18 + HSEM_R18 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x48 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R19 + HSEM_R19 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x4C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R20 + HSEM_R20 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x50 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R21 + HSEM_R21 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x54 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R22 + HSEM_R22 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x58 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R23 + HSEM_R23 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x5C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R24 + HSEM_R24 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x60 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R25 + HSEM_R25 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x64 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R26 + HSEM_R26 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x68 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R27 + HSEM_R27 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x6C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R28 + HSEM_R28 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x70 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R29 + HSEM_R29 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x74 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R30 + HSEM_R30 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x78 + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_R31 + HSEM_R31 + The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x7C + 0x20 + read-write + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR0 + HSEM_RLR0 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x80 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR1 + HSEM_RLR1 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x84 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR2 + HSEM_RLR2 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x88 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR3 + HSEM_RLR3 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x8C + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR4 + HSEM_RLR4 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x90 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR5 + HSEM_RLR5 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x94 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR6 + HSEM_RLR6 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x98 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR7 + HSEM_RLR7 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0x9C + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR8 + HSEM_RLR8 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xA0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR9 + HSEM_RLR9 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xA4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR10 + HSEM_RLR10 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xA8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR11 + HSEM_RLR11 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xAC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR12 + HSEM_RLR12 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xB0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR13 + HSEM_RLR13 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xB4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR14 + HSEM_RLR14 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xB8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR15 + HSEM_RLR15 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xBC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR16 + HSEM_RLR16 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xC0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR17 + HSEM_RLR17 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xC4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR18 + HSEM_RLR18 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xC8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR19 + HSEM_RLR19 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xCC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR20 + HSEM_RLR20 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xD0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR21 + HSEM_RLR21 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xD4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR22 + HSEM_RLR22 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xD8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR23 + HSEM_RLR23 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xDC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR24 + HSEM_RLR24 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xE0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR25 + HSEM_RLR25 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xE4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR26 + HSEM_RLR26 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xE8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR27 + HSEM_RLR27 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xEC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR28 + HSEM_RLR28 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xF0 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR29 + HSEM_RLR29 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xF4 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR30 + HSEM_RLR30 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xF8 + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_RLR31 + HSEM_RLR31 + Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. + 0xFC + 0x20 + read-only + 0x00000000 + + + PROCID + PROCID + 0 + 8 + + + COREID + COREID + 8 + 4 + + + LOCK + LOCK + 31 + 1 + + + + + HSEM_C1IER + HSEM_C1IER + HSEM i1terrupt enable register + 0x100 + 0x20 + read-write + 0x00000000 + + + ISE + ISE + 0 + 32 + + + + + HSEM_C1ICR + HSEM_C1ICR + HSEM i1terrupt clear register + 0x104 + 0x20 + read-write + 0x00000000 + + + ISC + ISC + 0 + 32 + + + + + HSEM_C1ISR + HSEM_C1ISR + HSEM i1terrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + + + ISF + ISF + 0 + 32 + + + + + HSEM_C1MISR + HSEM_C1MISR + HSEM i1terrupt status register + 0x10C + 0x20 + read-only + 0x00000000 + + + MISF + MISF + 0 + 32 + + + + + HSEM_C2IER + HSEM_C2IER + HSEM i2terrupt enable register + 0x110 + 0x20 + read-write + 0x00000000 + + + ISE + ISE + 0 + 32 + + + + + HSEM_C2ICR + HSEM_C2ICR + HSEM i2terrupt clear register + 0x114 + 0x20 + read-write + 0x00000000 + + + ISC + ISC + 0 + 32 + + + + + HSEM_C2ISR + HSEM_C2ISR + HSEM i2terrupt status register + 0x118 + 0x20 + read-only + 0x00000000 + + + ISF + ISF + 0 + 32 + + + + + HSEM_C2MISR + HSEM_C2MISR + HSEM i2terrupt status register + 0x11C + 0x20 + read-only + 0x00000000 + + + MISF + MISF + 0 + 32 + + + + + HSEM_CR + HSEM_CR + Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. + 0x140 + 0x20 + write-only + 0x00000000 + + + COREID + COREID + 8 + 4 + + + KEY + KEY + 16 + 16 + + + + + HSEM_KEYR + HSEM_KEYR + HSEM interrupt clear register + 0x144 + 0x20 + read-write + 0x00000000 + + + KEY + KEY + 16 + 16 + + + + + HSEM_HWCFGR2 + HSEM_HWCFGR2 + HSEM hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000021 + + + MASTERID1 + MASTERID1 + 0 + 4 + + + MASTERID2 + MASTERID2 + 4 + 4 + + + MASTERID3 + MASTERID3 + 8 + 4 + + + MASTERID4 + MASTERID4 + 12 + 4 + + + + + HSEM_HWCFGR1 + HSEM_HWCFGR1 + HSEM hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x00000220 + + + NBSEM + NBSEM + 0 + 8 + + + NBINT + NBINT + 8 + 4 + + + + + HSEM_VERR + HSEM_VERR + HSEM IP version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + HSEM_IPIDR + HSEM_IPIDR + HSEM IP identification register + 0x3F8 + 0x20 + read-only + 0x00100072 + + + IPID + IPID + 0 + 32 + + + + + HSEM_SIDR + HSEM_SIDR + HSEM size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + HDP + HDP + HDP + 0x5002A000 + + 0x0 + 0x400 + registers + + + + HDP_CTRL + HDP_CTRL + HDP Control + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + + + HDP_MUX + HDP_MUX + HDP multiplexing + 0x4 + 0x20 + read-write + 0x00000000 + + + MUX0 + MUX0 + 0 + 4 + + + MUX1 + MUX1 + 4 + 4 + + + MUX2 + MUX2 + 8 + 4 + + + MUX3 + MUX3 + 12 + 4 + + + MUX4 + MUX4 + 16 + 4 + + + MUX5 + MUX5 + 20 + 4 + + + MUX6 + MUX6 + 24 + 4 + + + MUX7 + MUX7 + 28 + 4 + + + + + HDP_VAL + HDP_VAL + HDP value + 0x10 + 0x20 + read-only + 0x00000000 + + + HDPVAL + HDPVAL + 0 + 8 + + + + + HDP_GPOSET + HDP_GPOSET + HDP GPO set + 0x14 + 0x20 + write-only + 0x00000000 + + + HDPGPOSET + HDPGPOSET + 0 + 8 + + + + + HDP_GPOCLR + HDP_GPOCLR + HDP GPO clear + 0x18 + 0x20 + write-only + 0x00000000 + + + HDPGPOCLR + HDPGPOCLR + 0 + 8 + + + + + HDP_GPOVAL + HDP_GPOVAL + HDP GPO value + 0x1C + 0x20 + read-write + 0x00000000 + + + HDPGPOVAL + HDPGPOVAL + 0 + 8 + + + + + HDP_VERR + HDP_VERR + HDP version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + HDP_IPIDR + HDP_IPIDR + HDP IP identification register + 0x3F8 + 0x20 + read-only + 0x00030002 + + + ID + ID + 0 + 32 + + + + + HDP_SIDR + HDP_SIDR + HDP size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + SAI1 + SAI1 register block + SAI + 0x4400A000 + + 0x0 + 0x400 + registers + + + + SAI_GCR + SAI_GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + SYNCIN + 0 + 2 + + + SYNCOUT + SYNCOUT + 4 + 2 + + + + + SAI_ACR1 + SAI_ACR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + MODE + 0 + 2 + + + PRTCFG + PRTCFG + 2 + 2 + + + DS + DS + 5 + 3 + + + LSBFIRST + LSBFIRST + 8 + 1 + + + CKSTR + CKSTR + 9 + 1 + + + SYNCEN + SYNCEN + 10 + 2 + + + MONO + MONO + 12 + 1 + + + OUTDRIV + OUTDRIV + 13 + 1 + + + SAIEN + SAIEN + 16 + 1 + + + DMAEN + DMAEN + 17 + 1 + + + NODIV + NODIV + 19 + 1 + + + MCKDIV + MCKDIV + 20 + 6 + + + OSR + OSR + 26 + 1 + + + MCKEN + MCKEN + 27 + 1 + + + + + SAI_ACR2 + SAI_ACR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FTH + 0 + 3 + read-write + + + FFLUSH + FFLUSH + 3 + 1 + write-only + + + TRIS + TRIS + 4 + 1 + read-write + + + MUTE + MUTE + 5 + 1 + read-write + + + MUTEVAL + MUTEVAL + 6 + 1 + read-write + + + MUTECNT + MUTECNT + 7 + 6 + read-write + + + CPL + CPL + 13 + 1 + read-write + + + COMP + COMP + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in and SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + FRL + 0 + 8 + read-write + + + FSALL + FSALL + 8 + 7 + read-write + + + FSDEF + FSDEF + 16 + 1 + read-only + + + FSPOL + FSPOL + 17 + 1 + read-write + + + FSOFF + FSOFF + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in and SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + FBOFF + 0 + 5 + + + SLOTSZ + SLOTSZ + 6 + 2 + + + NBSLOT + NBSLOT + 8 + 4 + + + SLOTEN + SLOTEN + 16 + 16 + + + + + SAI_AIM + SAI_AIM + Interrupt mask register + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + OVRUDRIE + 0 + 1 + + + MUTEDETIE + MUTEDETIE + 1 + 1 + + + WCKCFGIE + WCKCFGIE + 2 + 1 + + + FREQIE + FREQIE + 3 + 1 + + + CNRDYIE + CNRDYIE + 4 + 1 + + + AFSDETIE + AFSDETIE + 5 + 1 + + + LFSDETIE + LFSDETIE + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + OVRUDR + 0 + 1 + + + MUTEDET + MUTEDET + 1 + 1 + + + WCKCFG + WCKCFG + 2 + 1 + + + FREQ + FREQ + 3 + 1 + + + CNRDY + CNRDY + 4 + 1 + + + AFSDET + AFSDET + 5 + 1 + + + LFSDET + LFSDET + 6 + 1 + + + FLVL + FLVL + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + Clear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + COVRUDR + COVRUDR + 0 + 1 + + + CMUTEDET + CMUTEDET + 1 + 1 + + + CWCKCFG + CWCKCFG + 2 + 1 + + + CCNRDY + CCNRDY + 4 + 1 + + + CAFSDET + CAFSDET + 5 + 1 + + + CLFSDET + CLFSDET + 6 + 1 + + + + + SAI_ADR + SAI_ADR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + SAI_BCR1 + SAI_BCR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + MODE + 0 + 2 + + + PRTCFG + PRTCFG + 2 + 2 + + + DS + DS + 5 + 3 + + + LSBFIRST + LSBFIRST + 8 + 1 + + + CKSTR + CKSTR + 9 + 1 + + + SYNCEN + SYNCEN + 10 + 2 + + + MONO + MONO + 12 + 1 + + + OUTDRIV + OUTDRIV + 13 + 1 + + + SAIEN + SAIEN + 16 + 1 + + + DMAEN + DMAEN + 17 + 1 + + + NODIV + NODIV + 19 + 1 + + + MCKDIV + MCKDIV + 20 + 6 + + + OSR + OSR + 26 + 1 + + + MCKEN + MCKEN + 27 + 1 + + + + + SAI_BCR2 + SAI_BCR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FTH + 0 + 3 + read-write + + + FFLUSH + FFLUSH + 3 + 1 + write-only + + + TRIS + TRIS + 4 + 1 + read-write + + + MUTE + MUTE + 5 + 1 + read-write + + + MUTEVAL + MUTEVAL + 6 + 1 + read-write + + + MUTECNT + MUTECNT + 7 + 6 + read-write + + + CPL + CPL + 13 + 1 + read-write + + + COMP + COMP + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in and SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + FRL + 0 + 8 + read-write + + + FSALL + FSALL + 8 + 7 + read-write + + + FSDEF + FSDEF + 16 + 1 + read-only + + + FSPOL + FSPOL + 17 + 1 + read-write + + + FSOFF + FSOFF + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in and SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + FBOFF + 0 + 5 + + + SLOTSZ + SLOTSZ + 6 + 2 + + + NBSLOT + NBSLOT + 8 + 4 + + + SLOTEN + SLOTEN + 16 + 16 + + + + + SAI_BIM + SAI_BIM + Interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + OVRUDRIE + 0 + 1 + + + MUTEDETIE + MUTEDETIE + 1 + 1 + + + WCKCFGIE + WCKCFGIE + 2 + 1 + + + FREQIE + FREQIE + 3 + 1 + + + CNRDYIE + CNRDYIE + 4 + 1 + + + AFSDETIE + AFSDETIE + 5 + 1 + + + LFSDETIE + LFSDETIE + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + OVRUDR + 0 + 1 + + + MUTEDET + MUTEDET + 1 + 1 + + + WCKCFG + WCKCFG + 2 + 1 + + + FREQ + FREQ + 3 + 1 + + + CNRDY + CNRDY + 4 + 1 + + + AFSDET + AFSDET + 5 + 1 + + + LFSDET + LFSDET + 6 + 1 + + + FLVL + FLVL + 16 + 3 + + + + + SAI_BCLRFR + SAI_BCLRFR + Clear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + COVRUDR + COVRUDR + 0 + 1 + + + CMUTEDET + CMUTEDET + 1 + 1 + + + CWCKCFG + CWCKCFG + 2 + 1 + + + CCNRDY + CCNRDY + 4 + 1 + + + CAFSDET + CAFSDET + 5 + 1 + + + CLFSDET + CLFSDET + 6 + 1 + + + + + SAI_BDR + SAI_BDR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + DATA + 0 + 32 + + + + + SAI_PDMCR + SAI_PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + SAI_PDMDLY + SAI_PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + SAI_HWCFGR + SAI_HWCFGR + SAI hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000108 + + + FIFO_SIZE + FIFO_SIZE + 0 + 8 + + + SPDIF_PDM + SPDIF_PDM + 8 + 4 + + + OPTION_REGOUT + OPTION_REGOUT + 12 + 8 + + + + + SAI_VERR + SAI_VERR + SAI version register + 0x3F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SAI_IPIDR + SAI_IPIDR + SAI identification register + 0x3F8 + 0x20 + read-only + 0x00130031 + + + ID + ID + 0 + 32 + + + + + SAI_SIDR + SAI_SIDR + SAI size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + SAI2 + 0x4400B000 + + + SAI3 + 0x4400C000 + + + SAI4 + 0x50027000 + + + VREFBUF + VREFBUF + VREFBUF + 0x50025000 + + 0x0 + 0x400 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x0 + 0x20 + 0x00000002 + + + ENVR + ENVR + 0 + 1 + read-write + + + HIZ + HIZ + 1 + 1 + read-write + + + VRR + VRR + 3 + 1 + read-only + + + VRS + VRS + 4 + 3 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + TRIM + 0 + 6 + + + + + + + LPTIM1 + LPTIM1 + LPTIM1 + 0x40009000 + + 0x0 + 0x400 + registers + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + read-only + 0x00000000 + + + CMPM + CMPM + 0 + 1 + + + ARRM + ARRM + 1 + 1 + + + EXTTRIG + EXTTRIG + 2 + 1 + + + CMPOK + CMPOK + 3 + 1 + + + ARROK + ARROK + 4 + 1 + + + UP + UP + 5 + 1 + + + DOWN + DOWN + 6 + 1 + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CMPMCF + CMPMCF + 0 + 1 + + + ARRMCF + ARRMCF + 1 + 1 + + + EXTTRIGCF + EXTTRIGCF + 2 + 1 + + + CMPOKCF + CMPOKCF + 3 + 1 + + + ARROKCF + ARROKCF + 4 + 1 + + + UPCF + UPCF + 5 + 1 + + + DOWNCF + DOWNCF + 6 + 1 + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMPMIE + CMPMIE + 0 + 1 + + + ARRMIE + ARRMIE + 1 + 1 + + + EXTTRIGIE + EXTTRIGIE + 2 + 1 + + + CMPOKIE + CMPOKIE + 3 + 1 + + + ARROKIE + ARROKIE + 4 + 1 + + + UPIE + UPIE + 5 + 1 + + + DOWNIE + DOWNIE + 6 + 1 + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + CKSEL + CKSEL + 0 + 1 + + + CKPOL + CKPOL + 1 + 2 + + + CKFLT + CKFLT + 3 + 2 + + + TRGFLT + TRGFLT + 6 + 2 + + + PRESC + PRESC + 9 + 3 + + + TRIGSEL + TRIGSEL + 13 + 3 + + + TRIGEN + TRIGEN + 17 + 2 + + + TIMOUT + TIMOUT + 19 + 1 + + + WAVE + WAVE + 20 + 1 + + + WAVPOL + WAVPOL + 21 + 1 + + + PRELOAD + PRELOAD + 22 + 1 + + + COUNTMODE + COUNTMODE + 23 + 1 + + + ENC + ENC + 24 + 1 + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + ENABLE + 0 + 1 + + + SNGSTRT + SNGSTRT + 1 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + RSTARE + RSTARE + 4 + 1 + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 16 + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + ARR + 0 + 16 + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 16 + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + IN1SEL + 0 + 2 + + + IN2SEL + IN2SEL + 4 + 2 + + + + + LPTIM1_HWCFGR + LPTIM1_HWCFGR + LPTIM 1 peripheral hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00010804 + + + CFG1 + CFG1 + 0 + 8 + + + CFG2 + CFG2 + 8 + 8 + + + CFG3 + CFG3 + 16 + 4 + + + CFG4 + CFG4 + 24 + 8 + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3F8 + 0x20 + read-only + 0x00120011 + + + P_ID + P_ID + 0 + 32 + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + S_ID + S_ID + 0 + 32 + + + + + + + LPTIM2 + LPTIM2 + LPTIM2 + 0x50021000 + + 0x0 + 0x400 + registers + + + + LPTIM2_HWCFGR + LPTIM2_HWCFGR + LPTIM 2 peripheral hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00010804 + + + CFG1 + CFG1 + 0 + 8 + + + CFG2 + CFG2 + 8 + 8 + + + CFG3 + CFG3 + 16 + 4 + + + CFG4 + CFG4 + 24 + 8 + + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + read-only + 0x00000000 + + + CMPM + CMPM + 0 + 1 + + + ARRM + ARRM + 1 + 1 + + + EXTTRIG + EXTTRIG + 2 + 1 + + + CMPOK + CMPOK + 3 + 1 + + + ARROK + ARROK + 4 + 1 + + + UP + UP + 5 + 1 + + + DOWN + DOWN + 6 + 1 + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CMPMCF + CMPMCF + 0 + 1 + + + ARRMCF + ARRMCF + 1 + 1 + + + EXTTRIGCF + EXTTRIGCF + 2 + 1 + + + CMPOKCF + CMPOKCF + 3 + 1 + + + ARROKCF + ARROKCF + 4 + 1 + + + UPCF + UPCF + 5 + 1 + + + DOWNCF + DOWNCF + 6 + 1 + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMPMIE + CMPMIE + 0 + 1 + + + ARRMIE + ARRMIE + 1 + 1 + + + EXTTRIGIE + EXTTRIGIE + 2 + 1 + + + CMPOKIE + CMPOKIE + 3 + 1 + + + ARROKIE + ARROKIE + 4 + 1 + + + UPIE + UPIE + 5 + 1 + + + DOWNIE + DOWNIE + 6 + 1 + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + CKSEL + CKSEL + 0 + 1 + + + CKPOL + CKPOL + 1 + 2 + + + CKFLT + CKFLT + 3 + 2 + + + TRGFLT + TRGFLT + 6 + 2 + + + PRESC + PRESC + 9 + 3 + + + TRIGSEL + TRIGSEL + 13 + 3 + + + TRIGEN + TRIGEN + 17 + 2 + + + TIMOUT + TIMOUT + 19 + 1 + + + WAVE + WAVE + 20 + 1 + + + WAVPOL + WAVPOL + 21 + 1 + + + PRELOAD + PRELOAD + 22 + 1 + + + COUNTMODE + COUNTMODE + 23 + 1 + + + ENC + ENC + 24 + 1 + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + ENABLE + 0 + 1 + + + SNGSTRT + SNGSTRT + 1 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + RSTARE + RSTARE + 4 + 1 + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 16 + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + ARR + 0 + 16 + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 16 + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + IN1SEL + 0 + 2 + + + IN2SEL + IN2SEL + 4 + 2 + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3F8 + 0x20 + read-only + 0x00120011 + + + P_ID + P_ID + 0 + 32 + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + S_ID + S_ID + 0 + 32 + + + + + + + + LPTIM4 + LPTIM4 + LPTIM4 + 0x50023000 + + 0x0 + 0x400 + registers + + + + LPTIM4_HWCFGR + LPTIM4_HWCFGR + LPTIM 4 peripheral hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000804 + + + CFG1 + CFG1 + 0 + 8 + + + CFG2 + CFG2 + 8 + 8 + + + CFG3 + CFG3 + 16 + 4 + + + CFG4 + CFG4 + 24 + 8 + + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + read-only + 0x00000000 + + + CMPM + CMPM + 0 + 1 + + + ARRM + ARRM + 1 + 1 + + + EXTTRIG + EXTTRIG + 2 + 1 + + + CMPOK + CMPOK + 3 + 1 + + + ARROK + ARROK + 4 + 1 + + + UP + UP + 5 + 1 + + + DOWN + DOWN + 6 + 1 + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CMPMCF + CMPMCF + 0 + 1 + + + ARRMCF + ARRMCF + 1 + 1 + + + EXTTRIGCF + EXTTRIGCF + 2 + 1 + + + CMPOKCF + CMPOKCF + 3 + 1 + + + ARROKCF + ARROKCF + 4 + 1 + + + UPCF + UPCF + 5 + 1 + + + DOWNCF + DOWNCF + 6 + 1 + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMPMIE + CMPMIE + 0 + 1 + + + ARRMIE + ARRMIE + 1 + 1 + + + EXTTRIGIE + EXTTRIGIE + 2 + 1 + + + CMPOKIE + CMPOKIE + 3 + 1 + + + ARROKIE + ARROKIE + 4 + 1 + + + UPIE + UPIE + 5 + 1 + + + DOWNIE + DOWNIE + 6 + 1 + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + CKSEL + CKSEL + 0 + 1 + + + CKPOL + CKPOL + 1 + 2 + + + CKFLT + CKFLT + 3 + 2 + + + TRGFLT + TRGFLT + 6 + 2 + + + PRESC + PRESC + 9 + 3 + + + TRIGSEL + TRIGSEL + 13 + 3 + + + TRIGEN + TRIGEN + 17 + 2 + + + TIMOUT + TIMOUT + 19 + 1 + + + WAVE + WAVE + 20 + 1 + + + WAVPOL + WAVPOL + 21 + 1 + + + PRELOAD + PRELOAD + 22 + 1 + + + COUNTMODE + COUNTMODE + 23 + 1 + + + ENC + ENC + 24 + 1 + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + ENABLE + 0 + 1 + + + SNGSTRT + SNGSTRT + 1 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + RSTARE + RSTARE + 4 + 1 + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 16 + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + ARR + 0 + 16 + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 16 + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + IN1SEL + 0 + 2 + + + IN2SEL + IN2SEL + 4 + 2 + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3F8 + 0x20 + read-only + 0x00120011 + + + P_ID + P_ID + 0 + 32 + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + S_ID + S_ID + 0 + 32 + + + + + + + + LPTIM5 + LPTIM5 + LPTIM5 + 0x50024000 + + 0x0 + 0x400 + registers + + + + LPTIM5_HWCFGR + LPTIM5_HWCFGR + LPTIM 5 peripheral hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000804 + + + CFG1 + CFG1 + 0 + 8 + + + CFG2 + CFG2 + 8 + 8 + + + CFG3 + CFG3 + 16 + 4 + + + CFG4 + CFG4 + 24 + 8 + + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + read-only + 0x00000000 + + + CMPM + CMPM + 0 + 1 + + + ARRM + ARRM + 1 + 1 + + + EXTTRIG + EXTTRIG + 2 + 1 + + + CMPOK + CMPOK + 3 + 1 + + + ARROK + ARROK + 4 + 1 + + + UP + UP + 5 + 1 + + + DOWN + DOWN + 6 + 1 + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CMPMCF + CMPMCF + 0 + 1 + + + ARRMCF + ARRMCF + 1 + 1 + + + EXTTRIGCF + EXTTRIGCF + 2 + 1 + + + CMPOKCF + CMPOKCF + 3 + 1 + + + ARROKCF + ARROKCF + 4 + 1 + + + UPCF + UPCF + 5 + 1 + + + DOWNCF + DOWNCF + 6 + 1 + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMPMIE + CMPMIE + 0 + 1 + + + ARRMIE + ARRMIE + 1 + 1 + + + EXTTRIGIE + EXTTRIGIE + 2 + 1 + + + CMPOKIE + CMPOKIE + 3 + 1 + + + ARROKIE + ARROKIE + 4 + 1 + + + UPIE + UPIE + 5 + 1 + + + DOWNIE + DOWNIE + 6 + 1 + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + CKSEL + CKSEL + 0 + 1 + + + CKPOL + CKPOL + 1 + 2 + + + CKFLT + CKFLT + 3 + 2 + + + TRGFLT + TRGFLT + 6 + 2 + + + PRESC + PRESC + 9 + 3 + + + TRIGSEL + TRIGSEL + 13 + 3 + + + TRIGEN + TRIGEN + 17 + 2 + + + TIMOUT + TIMOUT + 19 + 1 + + + WAVE + WAVE + 20 + 1 + + + WAVPOL + WAVPOL + 21 + 1 + + + PRELOAD + PRELOAD + 22 + 1 + + + COUNTMODE + COUNTMODE + 23 + 1 + + + ENC + ENC + 24 + 1 + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + ENABLE + 0 + 1 + + + SNGSTRT + SNGSTRT + 1 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + RSTARE + RSTARE + 4 + 1 + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 16 + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + ARR + 0 + 16 + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 16 + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + IN1SEL + 0 + 2 + + + IN2SEL + IN2SEL + 4 + 2 + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3F8 + 0x20 + read-only + 0x00120011 + + + P_ID + P_ID + 0 + 32 + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + S_ID + S_ID + 0 + 32 + + + + + + + + SYSCFG + SYSCFG + SYSCFG + 0x50020000 + + 0x0 + 0x400 + registers + + + + SYSCFG_BOOTR + SYSCFG_BOOTR + This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. ) + 0x0 + 0x20 + 0x00000000 + + + BOOT0 + BOOT0 + 0 + 1 + read-only + + + BOOT1 + BOOT1 + 1 + 1 + read-only + + + BOOT2 + BOOT2 + 2 + 1 + read-only + + + BOOT0_PD + BOOT0_PD + 4 + 1 + read-write + + + BOOT1_PD + BOOT1_PD + 5 + 1 + read-write + + + BOOT2_PD + BOOT2_PD + 6 + 1 + read-write + + + + + SYSCFG_PMCSETR + SYSCFG_PMCSETR + SYSCFG peripheral mode configuration set register + 0x4 + 0x20 + read-write + 0x00000000 + + + I2C1_FMP + I2C1_FMP + 0 + 1 + + + I2C2_FMP + I2C2_FMP + 1 + 1 + + + I2C3_FMP + I2C3_FMP + 2 + 1 + + + I2C4_FMP + I2C4_FMP + 3 + 1 + + + I2C5_FMP + I2C5_FMP + 4 + 1 + + + I2C6_FMP + I2C6_FMP + 5 + 1 + + + EN_BOOSTER + EN_BOOSTER + 8 + 1 + + + ANASWVDD + ANASWVDD + 9 + 1 + + + ETH_CLK_SEL + ETH_CLK_SEL + 16 + 1 + + + ETH_REF_CLK_SEL + ETH_REF_CLK_SEL + 17 + 1 + + + ETH_SELMII + ETH_SELMII + 20 + 1 + + + ETH_SEL + ETH_SEL + 21 + 3 + + + ANA0_SEL + ANA0_SEL + 24 + 1 + + + ANA1_SEL + ANA1_SEL + 25 + 1 + + + + + SYSCFG_IOCTRLSETR + SYSCFG_IOCTRLSETR + SYSCFG IO control register + 0x18 + 0x20 + read-write + 0x00000000 + + + HSLVEN_TRACE + HSLVEN_TRACE + 0 + 1 + + + HSLVEN_QUADSPI + HSLVEN_QUADSPI + 1 + 1 + + + HSLVEN_ETH + HSLVEN_ETH + 2 + 1 + + + HSLVEN_SDMMC + HSLVEN_SDMMC + 3 + 1 + + + HSLVEN_SPI + HSLVEN_SPI + 4 + 1 + + + + + SYSCFG_ICNR + SYSCFG_ICNR + SYSCFG interconnect control register + 0x1C + 0x20 + read-write + 0x00000000 + + + AXI_M0 + AXI_M0 + 0 + 1 + + + AXI_M1 + AXI_M1 + 1 + 1 + + + AXI_M2 + AXI_M2 + 2 + 1 + + + AXI_M3 + AXI_M3 + 3 + 1 + + + AXI_M5 + AXI_M5 + 5 + 1 + + + AXI_M6 + AXI_M6 + 6 + 1 + + + AXI_M7 + AXI_M7 + 7 + 1 + + + AXI_M8 + AXI_M8 + 8 + 1 + + + AXI_M9 + AXI_M9 + 9 + 1 + + + AXI_M10 + AXI_M10 + 10 + 1 + + + + + SYSCFG_CMPCR + SYSCFG_CMPCR + SYSCFG compensation cell control register + 0x20 + 0x20 + 0x00870000 + + + SW_CTRL + SW_CTRL + 1 + 1 + read-write + + + READY + READY + 8 + 1 + read-only + + + RANSRC + RANSRC + 16 + 4 + read-write + + + RAPSRC + RAPSRC + 20 + 4 + read-write + + + ANSRC + ANSRC + 24 + 4 + read-only + + + APSRC + APSRC + 28 + 4 + read-only + + + + + SYSCFG_CMPENSETR + SYSCFG_CMPENSETR + SYSCFG compensation cell enable set register + 0x24 + 0x20 + read-write + 0x00000000 + + + MPU_EN + MPU_EN + 0 + 1 + + + MCU_EN + MCU_EN + 1 + 1 + + + + + SYSCFG_CMPENCLRR + SYSCFG_CMPENCLRR + SYSCFG compensation cell enable set register + 0x28 + 0x20 + read-write + 0x00000000 + + + MPU_EN + MPU_EN + 0 + 1 + + + MCU_EN + MCU_EN + 1 + 1 + + + + + SYSCFG_CBR + SYSCFG_CBR + SYSCFG control timer break register + 0x2C + 0x20 + read-write + 0x00000000 + + + CLL + CLL + 0 + 1 + + + PVDL + PVDL + 2 + 1 + + + + + SYSCFG_PMCCLRR + SYSCFG_PMCCLRR + SYSCFG peripheral mode configuration clear register + 0x44 + 0x20 + read-write + 0x00000000 + + + I2C1_FMP + I2C1_FMP + 0 + 1 + + + I2C2_FMP + I2C2_FMP + 1 + 1 + + + I2C3_FMP + I2C3_FMP + 2 + 1 + + + I2C4_FMP + I2C4_FMP + 3 + 1 + + + I2C5_FMP + I2C5_FMP + 4 + 1 + + + I2C6_FMP + I2C6_FMP + 5 + 1 + + + EN_BOOSTER + EN_BOOSTER + 8 + 1 + + + ANASWVDD + ANASWVDD + 9 + 1 + + + ETH_CLK_SEL + ETH_CLK_SEL + 16 + 1 + + + ETH_REF_CLK_SEL + ETH_REF_CLK_SEL + 17 + 1 + + + ETH_SELMII + ETH_SELMII + 20 + 1 + + + ETH_SEL + ETH_SEL + 21 + 3 + + + ANA0_SEL + ANA0_SEL + 24 + 1 + + + ANA1_SEL + ANA1_SEL + 25 + 1 + + + + + SYSCFG_IOCTRLCLRR + SYSCFG_IOCTRLCLRR + SYSCFG IO control register + 0x58 + 0x20 + read-write + 0x00000000 + + + HSLVEN_TRACE + HSLVEN_TRACE + 0 + 1 + + + HSLVEN_QUADSPI + HSLVEN_QUADSPI + 1 + 1 + + + HSLVEN_ETH + HSLVEN_ETH + 2 + 1 + + + HSLVEN_SDMMC + HSLVEN_SDMMC + 3 + 1 + + + HSLVEN_SPI + HSLVEN_SPI + 4 + 1 + + + + + SYSCFG_VERR + SYSCFG_VERR + SYSCFG version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + SYSCFG_IPIDR + SYSCFG_IPIDR + SYSCFG identification register + 0x3F8 + 0x20 + read-only + 0x00030001 + + + ID + ID + 0 + 32 + + + + + SYSCFG_SIDR + SYSCFG_SIDR + SYSCFG size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + LPTIM3 + LPTIM3 + LPTIM3 + 0x50022000 + + 0x0 + 0x400 + registers + + + + LPTIM3_CFGR2 + LPTIM3_CFGR2 + LPTIM3 configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + IN1SEL + IN1SEL + 0 + 2 + + + + + LPTIM_ISR + LPTIM_ISR + LPTIM interrupt and status register + 0x0 + 0x20 + read-only + 0x00000000 + + + CMPM + CMPM + 0 + 1 + + + ARRM + ARRM + 1 + 1 + + + EXTTRIG + EXTTRIG + 2 + 1 + + + CMPOK + CMPOK + 3 + 1 + + + ARROK + ARROK + 4 + 1 + + + UP + UP + 5 + 1 + + + DOWN + DOWN + 6 + 1 + + + + + LPTIM_ICR + LPTIM_ICR + LPTIM interrupt clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CMPMCF + CMPMCF + 0 + 1 + + + ARRMCF + ARRMCF + 1 + 1 + + + EXTTRIGCF + EXTTRIGCF + 2 + 1 + + + CMPOKCF + CMPOKCF + 3 + 1 + + + ARROKCF + ARROKCF + 4 + 1 + + + UPCF + UPCF + 5 + 1 + + + DOWNCF + DOWNCF + 6 + 1 + + + + + LPTIM_IER + LPTIM_IER + LPTIM interrupt enable register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMPMIE + CMPMIE + 0 + 1 + + + ARRMIE + ARRMIE + 1 + 1 + + + EXTTRIGIE + EXTTRIGIE + 2 + 1 + + + CMPOKIE + CMPOKIE + 3 + 1 + + + ARROKIE + ARROKIE + 4 + 1 + + + UPIE + UPIE + 5 + 1 + + + DOWNIE + DOWNIE + 6 + 1 + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + CKSEL + CKSEL + 0 + 1 + + + CKPOL + CKPOL + 1 + 2 + + + CKFLT + CKFLT + 3 + 2 + + + TRGFLT + TRGFLT + 6 + 2 + + + PRESC + PRESC + 9 + 3 + + + TRIGSEL + TRIGSEL + 13 + 3 + + + TRIGEN + TRIGEN + 17 + 2 + + + TIMOUT + TIMOUT + 19 + 1 + + + WAVE + WAVE + 20 + 1 + + + WAVPOL + WAVPOL + 21 + 1 + + + PRELOAD + PRELOAD + 22 + 1 + + + COUNTMODE + COUNTMODE + 23 + 1 + + + ENC + ENC + 24 + 1 + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + ENABLE + 0 + 1 + + + SNGSTRT + SNGSTRT + 1 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + RSTARE + RSTARE + 4 + 1 + + + + + LPTIM_CMP + LPTIM_CMP + LPTIM compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + CMP + 0 + 16 + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + ARR + 0 + 16 + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + CNT + 0 + 16 + + + + + LPTIM_VERR + LPTIM_VERR + LPTIM peripheral version identification register + 0x3F4 + 0x20 + read-only + 0x00000014 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + LPTIM_PIDR + LPTIM_PIDR + LPTIM peripheral type identification register + 0x3F8 + 0x20 + read-only + 0x00120011 + + + P_ID + P_ID + 0 + 32 + + + + + LPTIM_SIDR + LPTIM_SIDR + LPTIM registers map size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + S_ID + S_ID + 0 + 32 + + + + + + LPTIM3_HWCFGR + LPTIM3_HWCFGR + LPTIM 3 peripheral hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000804 + + + CFG1 + CFG1 + 0 + 8 + + + CFG2 + CFG2 + 8 + 8 + + + CFG3 + CFG3 + 16 + 4 + + + CFG4 + CFG4 + 24 + 8 + + + + + + + PWR + PWR + PWR + 0x50001000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. + 0x0 + 0x20 + read-write + 0x00000000 + + + LPDS + LPDS + 0 + 1 + + + LPCFG + LPCFG + 1 + 1 + + + LVDS + LVDS + 2 + 1 + + + PVDEN + PVDEN + 4 + 1 + + + PLS + PLS + 5 + 3 + + + DBP + DBP + 8 + 1 + + + AVDEN + AVDEN + 16 + 1 + + + ALS + ALS + 17 + 2 + + + + + PWR_CSR1 + PWR_CSR1 + Reset on any system reset. + 0x4 + 0x20 + read-only + 0x00000000 + + + PVDO + PVDO + 4 + 1 + + + AVDO + AVDO + 16 + 1 + + + + + PWR_CR2 + PWR_CR2 + Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x8 + 0x20 + 0x00000000 + + + BREN + BREN + 0 + 1 + read-write + + + RREN + RREN + 1 + 1 + read-write + + + MONEN + MONEN + 4 + 1 + read-write + + + BRRDY + BRRDY + 16 + 1 + read-only + + + RRRDY + RRRDY + 17 + 1 + read-only + + + VBATL + VBATL + 20 + 1 + read-only + + + VBATH + VBATH + 21 + 1 + read-only + + + TEMPL + TEMPL + 22 + 1 + read-only + + + TEMPH + TEMPH + 23 + 1 + read-only + + + + + PWR_CR3 + PWR_CR3 + Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0xC + 0x20 + 0x50000000 + + + VBE + VBE + 8 + 1 + read-write + + + VBRS + VBRS + 9 + 1 + read-write + + + DDRSREN + DDRSREN + 10 + 1 + read-write + + + DDRSRDIS + DDRSRDIS + 11 + 1 + read-write + + + DDRRETEN + DDRRETEN + 12 + 1 + read-write + + + POPL + POPL + 17 + 5 + read-write + + + USB33DEN + USB33DEN + 24 + 1 + read-write + + + USB33RDY + USB33RDY + 26 + 1 + read-only + + + REG18EN + REG18EN + 28 + 1 + read-write + + + REG18RDY + REG18RDY + 29 + 1 + read-only + + + REG11EN + REG11EN + 30 + 1 + read-write + + + REG11RDY + REG11RDY + 31 + 1 + read-only + + + + + PWR_MPUCR + PWR_MPUCR + See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x10 + 0x20 + 0x00000000 + + + PDDS + PDDS + 0 + 1 + read-write + + + CSTBYDIS + CSTBYDIS + 3 + 1 + read-write + + + STOPF + STOPF + 5 + 1 + read-only + + + SBF + SBF + 6 + 1 + read-only + + + SBFMPU + SBFMPU + 7 + 1 + read-only + + + CSSF + CSSF + 9 + 1 + read-write + + + STANDBYWFIL2 + STANDBYWFIL2 + 15 + 1 + read-only + + + + + PWR_MCUCR + PWR_MCUCR + See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x14 + 0x20 + 0x00000000 + + + PDDS + PDDS + 0 + 1 + read-write + + + STOPF + STOPF + 5 + 1 + read-only + + + SBF + SBF + 6 + 1 + read-only + + + CSSF + CSSF + 9 + 1 + read-write + + + DEEPSLEEP + DEEPSLEEP + 15 + 1 + read-only + + + + + PWR_WKUPCR + PWR_WKUPCR + Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x20 + 0x20 + read-write + 0x00000000 + + + WKUPC1 + WKUPC1 + 0 + 1 + + + WKUPC2 + WKUPC2 + 1 + 1 + + + WKUPC3 + WKUPC3 + 2 + 1 + + + WKUPC4 + WKUPC4 + 3 + 1 + + + WKUPC5 + WKUPC5 + 4 + 1 + + + WKUPC6 + WKUPC6 + 5 + 1 + + + WKUPP1 + WKUPP1 + 8 + 1 + + + WKUPP2 + WKUPP2 + 9 + 1 + + + WKUPP3 + WKUPP3 + 10 + 1 + + + WKUPP4 + WKUPP4 + 11 + 1 + + + WKUPP5 + WKUPP5 + 12 + 1 + + + WKUPP6 + WKUPP6 + 13 + 1 + + + WKUPPUPD1 + WKUPPUPD1 + 16 + 2 + + + WKUPPUPD2 + WKUPPUPD2 + 18 + 2 + + + WKUPPUPD3 + WKUPPUPD3 + 20 + 2 + + + WKUPPUPD4 + WKUPPUPD4 + 22 + 2 + + + WKUPPUPD5 + WKUPPUPD5 + 24 + 2 + + + WKUPPUPD6 + WKUPPUPD6 + 26 + 2 + + + + + PWR_WKUPFR + PWR_WKUPFR + Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) + 0x24 + 0x20 + read-only + 0x00000000 + + + WKUPF1 + WKUPF1 + 0 + 1 + + + WKUPF2 + WKUPF2 + 1 + 1 + + + WKUPF3 + WKUPF3 + 2 + 1 + + + WKUPF4 + WKUPF4 + 3 + 1 + + + WKUPF5 + WKUPF5 + 4 + 1 + + + WKUPF6 + WKUPF6 + 5 + 1 + + + + + PWR_MPUWKUPENR + PWR_MPUWKUPENR + Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x28 + 0x20 + read-write + 0x00000000 + + + WKUPEN1 + WKUPEN1 + 0 + 1 + + + WKUPEN2 + WKUPEN2 + 1 + 1 + + + WKUPEN3 + WKUPEN3 + 2 + 1 + + + WKUPEN4 + WKUPEN4 + 3 + 1 + + + WKUPEN5 + WKUPEN5 + 4 + 1 + + + WKUPEN6 + WKUPEN6 + 5 + 1 + + + + + PWR_MCUWKUPENR + PWR_MCUWKUPENR + Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed. + 0x2C + 0x20 + read-write + 0x00000000 + + + WKUPEN1 + WKUPEN1 + 0 + 1 + + + WKUPEN2 + WKUPEN2 + 1 + 1 + + + WKUPEN3 + WKUPEN3 + 2 + 1 + + + WKUPEN4 + WKUPEN4 + 3 + 1 + + + WKUPEN5 + WKUPEN5 + 4 + 1 + + + WKUPEN6 + WKUPEN6 + 5 + 1 + + + + + PWR_VER + PWR_VER + PWR IP version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + PWR_ID + PWR_ID + PWR IP identification register + 0x3F8 + 0x20 + read-only + 0x00010001 + + + IPID + IPID + 0 + 32 + + + + + PWR_SID + PWR_SID + PWR size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + RCC + RCC + RCC + 0x50000000 + + 0x0 + 0x1000 + registers + + + RCC + RCC global interrupt + 5 + + + RCC_WAKEUP + RCC MPU wakeup interrupt + 145 + + + + RCC_TZCR + RCC_TZCR + This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode. + 0x0 + 0x20 + read-write + 0x00000003 + + + TZEN + TZEN + 0 + 1 + + + MCKPROT + MCKPROT + 1 + 1 + + + + + RCC_OCENSETR + RCC_OCENSETR + This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0xC + 0x20 + read-write + 0x00000001 + + + HSION + HSION + 0 + 1 + + + HSIKERON + HSIKERON + 1 + 1 + + + CSION + CSION + 4 + 1 + + + CSIKERON + CSIKERON + 5 + 1 + + + DIGBYP + DIGBYP + 7 + 1 + + + HSEON + HSEON + 8 + 1 + + + HSEKERON + HSEKERON + 9 + 1 + + + HSEBYP + HSEBYP + 10 + 1 + + + HSECSSON + HSECSSON + 11 + 1 + + + + + RCC_OCENCLRR + RCC_OCENCLRR + This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x10 + 0x20 + read-write + 0x00000001 + + + HSION + HSION + 0 + 1 + + + HSIKERON + HSIKERON + 1 + 1 + + + CSION + CSION + 4 + 1 + + + CSIKERON + CSIKERON + 5 + 1 + + + DIGBYP + DIGBYP + 7 + 1 + + + HSEON + HSEON + 8 + 1 + + + HSEKERON + HSEKERON + 9 + 1 + + + HSEBYP + HSEBYP + 10 + 1 + + + + + RCC_HSICFGR + RCC_HSICFGR + This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x18 + 0x20 + 0x00000000 + + + HSIDIV + HSIDIV + 0 + 2 + read-write + + + HSITRIM + HSITRIM + 8 + 7 + read-write + + + HSICAL + HSICAL + 16 + 12 + read-only + + + + + RCC_CSICFGR + RCC_CSICFGR + This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details. + 0x1C + 0x20 + 0x00001000 + + + CSITRIM + CSITRIM + 8 + 5 + read-write + + + CSICAL + CSICAL + 16 + 8 + read-only + + + + + RCC_MPCKSELR + RCC_MPCKSELR + This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x20 + 0x20 + 0x80000000 + + + MPUSRC + MPUSRC + 0 + 2 + read-write + + + MPUSRCRDY + MPUSRCRDY + 31 + 1 + read-only + + + + + RCC_ASSCKSELR + RCC_ASSCKSELR + This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x24 + 0x20 + 0x80000000 + + + AXISSRC + AXISSRC + 0 + 3 + read-write + + + AXISSRCRDY + AXISSRCRDY + 31 + 1 + read-only + + + + + RCC_RCK12SELR + RCC_RCK12SELR + This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x28 + 0x20 + 0x80000000 + + + PLL12SRC + PLL12SRC + 0 + 2 + read-write + + + PLL12SRCRDY + PLL12SRCRDY + 31 + 1 + read-only + + + + + RCC_MPCKDIVR + RCC_MPCKDIVR + This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. + 0x2C + 0x20 + 0x80000001 + + + MPUDIV + MPUDIV + 0 + 3 + read-write + + + MPUDIVRDY + MPUDIVRDY + 31 + 1 + read-only + + + + + RCC_AXIDIVR + RCC_AXIDIVR + This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. + 0x30 + 0x20 + 0x80000000 + + + AXIDIV + AXIDIV + 0 + 3 + read-write + + + AXIDIVRDY + AXIDIVRDY + 31 + 1 + read-only + + + + + RCC_APB4DIVR + RCC_APB4DIVR + This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. + 0x3C + 0x20 + 0x80000000 + + + APB4DIV + APB4DIV + 0 + 3 + read-write + + + APB4DIVRDY + APB4DIVRDY + 31 + 1 + read-only + + + + + RCC_APB5DIVR + RCC_APB5DIVR + This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. + 0x40 + 0x20 + 0x80000000 + + + APB5DIV + APB5DIV + 0 + 3 + read-write + + + APB5DIVRDY + APB5DIVRDY + 31 + 1 + read-only + + + + + RCC_RTCDIVR + RCC_RTCDIVR + This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode. + 0x44 + 0x20 + read-write + 0x00000000 + + + RTCDIV + RTCDIV + 0 + 6 + + + + + RCC_MSSCKSELR + RCC_MSSCKSELR + This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x48 + 0x20 + 0x80000000 + + + MCUSSRC + MCUSSRC + 0 + 2 + read-write + + + MCUSSRCRDY + MCUSSRCRDY + 31 + 1 + read-only + + + + + RCC_PLL1CR + RCC_PLL1CR + This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x80 + 0x20 + 0x00000000 + + + PLLON + PLLON + 0 + 1 + read-write + + + PLL1RDY + PLL1RDY + 1 + 1 + read-only + + + SSCG_CTRL + SSCG_CTRL + 2 + 1 + read-write + + + DIVPEN + DIVPEN + 4 + 1 + read-write + + + DIVQEN + DIVQEN + 5 + 1 + read-write + + + DIVREN + DIVREN + 6 + 1 + read-write + + + + + RCC_PLL1CFGR1 + RCC_PLL1CFGR1 + This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x84 + 0x20 + read-write + 0x00010031 + + + DIVN + DIVN + 0 + 9 + + + DIVM1 + DIVM1 + 16 + 6 + + + + + RCC_PLL1CFGR2 + RCC_PLL1CFGR2 + This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x88 + 0x20 + read-write + 0x00010100 + + + DIVP + DIVP + 0 + 7 + + + DIVQ + DIVQ + 8 + 7 + + + DIVR + DIVR + 16 + 7 + + + + + RCC_PLL1FRACR + RCC_PLL1FRACR + This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x8C + 0x20 + read-write + 0x00000000 + + + FRACV + FRACV + 3 + 13 + + + FRACLE + FRACLE + 16 + 1 + + + + + RCC_PLL1CSGR + RCC_PLL1CSGR + This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x90 + 0x20 + read-write + 0x00000000 + + + MOD_PER + MOD_PER + 0 + 13 + + + TPDFN_DIS + TPDFN_DIS + 13 + 1 + + + RPDFN_DIS + RPDFN_DIS + 14 + 1 + + + SSCG_MODE + SSCG_MODE + 15 + 1 + + + INC_STEP + INC_STEP + 16 + 15 + + + + + RCC_PLL2CR + RCC_PLL2CR + This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x94 + 0x20 + 0x00000000 + + + PLLON + PLLON + 0 + 1 + read-write + + + PLL2RDY + PLL2RDY + 1 + 1 + read-only + + + SSCG_CTRL + SSCG_CTRL + 2 + 1 + read-write + + + DIVPEN + DIVPEN + 4 + 1 + read-write + + + DIVQEN + DIVQEN + 5 + 1 + read-write + + + DIVREN + DIVREN + 6 + 1 + read-write + + + + + RCC_PLL2CFGR1 + RCC_PLL2CFGR1 + This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x98 + 0x20 + read-write + 0x00010063 + + + DIVN + DIVN + 0 + 9 + + + DIVM2 + DIVM2 + 16 + 6 + + + + + RCC_PLL2CFGR2 + RCC_PLL2CFGR2 + This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0x9C + 0x20 + read-write + 0x00010101 + + + DIVP + DIVP + 0 + 7 + + + DIVQ + DIVQ + 8 + 7 + + + DIVR + DIVR + 16 + 7 + + + + + RCC_PLL2FRACR + RCC_PLL2FRACR + This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0xA0 + 0x20 + read-write + 0x00000000 + + + FRACV + FRACV + 3 + 13 + + + FRACLE + FRACLE + 16 + 1 + + + + + RCC_PLL2CSGR + RCC_PLL2CSGR + This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. + 0xA4 + 0x20 + read-write + 0x00000000 + + + MOD_PER + MOD_PER + 0 + 13 + + + TPDFN_DIS + TPDFN_DIS + 13 + 1 + + + RPDFN_DIS + RPDFN_DIS + 14 + 1 + + + SSCG_MODE + SSCG_MODE + 15 + 1 + + + INC_STEP + INC_STEP + 16 + 15 + + + + + RCC_I2C46CKSELR + RCC_I2C46CKSELR + This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. + 0xC0 + 0x20 + read-write + 0x00000000 + + + I2C46SRC + I2C46SRC + 0 + 3 + + + + + RCC_SPI6CKSELR + RCC_SPI6CKSELR + This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. + 0xC4 + 0x20 + read-write + 0x00000000 + + + SPI6SRC + SPI6SRC + 0 + 3 + + + + + RCC_UART1CKSELR + RCC_UART1CKSELR + This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. + 0xC8 + 0x20 + read-write + 0x00000000 + + + UART1SRC + UART1SRC + 0 + 3 + + + + + RCC_RNG1CKSELR + RCC_RNG1CKSELR + This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. + 0xCC + 0x20 + read-write + 0x00000000 + + + RNG1SRC + RNG1SRC + 0 + 2 + + + + + RCC_CPERCKSELR + RCC_CPERCKSELR + This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays. + 0xD0 + 0x20 + read-write + 0x00000000 + + + CKPERSRC + CKPERSRC + 0 + 2 + + + + + RCC_STGENCKSELR + RCC_STGENCKSELR + This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. + 0xD4 + 0x20 + read-write + 0x00000000 + + + STGENSRC + STGENSRC + 0 + 2 + + + + + RCC_DDRITFCR + RCC_DDRITFCR + This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode. + 0xD8 + 0x20 + read-write + 0x000FD02A + + + DDRC1EN + DDRC1EN + 0 + 1 + + + DDRC1LPEN + DDRC1LPEN + 1 + 1 + + + DDRC2EN + DDRC2EN + 2 + 1 + + + DDRC2LPEN + DDRC2LPEN + 3 + 1 + + + DDRPHYCEN + DDRPHYCEN + 4 + 1 + + + DDRPHYCLPEN + DDRPHYCLPEN + 5 + 1 + + + DDRCAPBEN + DDRCAPBEN + 6 + 1 + + + DDRCAPBLPEN + DDRCAPBLPEN + 7 + 1 + + + AXIDCGEN + AXIDCGEN + 8 + 1 + + + DDRPHYCAPBEN + DDRPHYCAPBEN + 9 + 1 + + + DDRPHYCAPBLPEN + DDRPHYCAPBLPEN + 10 + 1 + + + KERDCG_DLY + KERDCG_DLY + 11 + 3 + + + DDRCAPBRST + DDRCAPBRST + 14 + 1 + + + DDRCAXIRST + DDRCAXIRST + 15 + 1 + + + DDRCORERST + DDRCORERST + 16 + 1 + + + DPHYAPBRST + DPHYAPBRST + 17 + 1 + + + DPHYRST + DPHYRST + 18 + 1 + + + DPHYCTLRST + DPHYCTLRST + 19 + 1 + + + DDRCKMOD + DDRCKMOD + 20 + 3 + + + GSKPMOD + GSKPMOD + 23 + 1 + + + GSKPCTRL + GSKPCTRL + 24 + 1 + + + DFILP_WIDTH + DFILP_WIDTH + 25 + 3 + + + GSKP_DUR + GSKP_DUR + 28 + 4 + + + + + RCC_MP_BOOTCR + RCC_MP_BOOTCR + This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU. + 0x100 + 0x20 + read-write + 0x00000000 + + + MCU_BEN + MCU_BEN + 0 + 1 + + + MPU_BEN + MPU_BEN + 1 + 1 + + + + + RCC_MP_SREQSETR + RCC_MP_SREQSETR + Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. + 0x104 + 0x20 + read-write + 0x00000000 + + + STPREQ_P0 + STPREQ_P0 + 0 + 1 + + + STPREQ_P1 + STPREQ_P1 + 1 + 1 + + + + + RCC_MP_SREQCLRR + RCC_MP_SREQCLRR + Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. + 0x108 + 0x20 + read-write + 0x00000000 + + + STPREQ_P0 + STPREQ_P0 + 0 + 1 + + + STPREQ_P1 + STPREQ_P1 + 1 + 1 + + + + + RCC_MP_GCR + RCC_MP_GCR + The register contains global control bits. If TZEN = , this register can only be modified in secure mode. + 0x10C + 0x20 + read-write + 0x00000000 + + + BOOT_MCU + BOOT_MCU + 0 + 1 + + + + + RCC_MP_APRSTCR + RCC_MP_APRSTCR + This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode. + 0x110 + 0x20 + read-write + 0x00007F00 + + + RDCTLEN + RDCTLEN + 0 + 1 + + + RSTTO + RSTTO + 8 + 7 + + + + + RCC_MP_APRSTSR + RCC_MP_APRSTSR + This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode. + 0x114 + 0x20 + read-only + 0x00000000 + + + RSTTOV + RSTTOV + 8 + 7 + + + + + RCC_BDCR + RCC_BDCR + This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode. + 0x140 + 0x20 + 0x00000020 + + + LSEON + LSEON + 0 + 1 + read-write + + + LSEBYP + LSEBYP + 1 + 1 + read-write + + + LSERDY + LSERDY + 2 + 1 + read-only + + + DIGBYP + DIGBYP + 3 + 1 + read-only + + + LSEDRV + LSEDRV + 4 + 2 + read-write + + + LSECSSON + LSECSSON + 8 + 1 + read-write + + + LSECSSD + LSECSSD + 9 + 1 + read-only + + + RTCSRC + RTCSRC + 16 + 2 + read-only + + + RTCCKEN + RTCCKEN + 20 + 1 + read-write + + + VSWRST + VSWRST + 31 + 1 + read-write + + + + + RCC_RDLSICR + RCC_RDLSICR + This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode. + 0x144 + 0x20 + 0x00000000 + + + LSION + LSION + 0 + 1 + read-write + + + LSIRDY + LSIRDY + 1 + 1 + read-only + + + MRD + MRD + 16 + 5 + read-write + + + EADLY + EADLY + 24 + 3 + read-write + + + SPARE + SPARE + 27 + 5 + read-write + + + + + RCC_APB4RSTSETR + RCC_APB4RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. + 0x180 + 0x20 + read-write + 0x00000000 + + + LTDCRST + LTDCRST + 0 + 1 + + + DSIRST + DSIRST + 4 + 1 + + + DDRPERFMRST + DDRPERFMRST + 8 + 1 + + + USBPHYRST + USBPHYRST + 16 + 1 + + + + + RCC_APB4RSTCLRR + RCC_APB4RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. + 0x184 + 0x20 + read-write + 0x00000000 + + + LTDCRST + LTDCRST + 0 + 1 + + + DSIRST + DSIRST + 4 + 1 + + + DDRPERFMRST + DDRPERFMRST + 8 + 1 + + + USBPHYRST + USBPHYRST + 16 + 1 + + + + + RCC_APB5RSTSETR + RCC_APB5RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x188 + 0x20 + read-write + 0x00000000 + + + SPI6RST + SPI6RST + 0 + 1 + + + I2C4RST + I2C4RST + 2 + 1 + + + I2C6RST + I2C6RST + 3 + 1 + + + USART1RST + USART1RST + 4 + 1 + + + STGENRST + STGENRST + 20 + 1 + + + + + RCC_APB5RSTCLRR + RCC_APB5RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x18C + 0x20 + read-write + 0x00000000 + + + SPI6RST + SPI6RST + 0 + 1 + + + I2C4RST + I2C4RST + 2 + 1 + + + I2C6RST + I2C6RST + 3 + 1 + + + USART1RST + USART1RST + 4 + 1 + + + STGENRST + STGENRST + 20 + 1 + + + + + RCC_AHB5RSTSETR + RCC_AHB5RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x190 + 0x20 + read-write + 0x00000000 + + + GPIOZRST + GPIOZRST + 0 + 1 + + + CRYP1RST + CRYP1RST + 4 + 1 + + + HASH1RST + HASH1RST + 5 + 1 + + + RNG1RST + RNG1RST + 6 + 1 + + + AXIMCRST + AXIMCRST + 16 + 1 + + + + + RCC_AHB5RSTCLRR + RCC_AHB5RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x194 + 0x20 + read-write + 0x00000000 + + + GPIOZRST + GPIOZRST + 0 + 1 + + + CRYP1RST + CRYP1RST + 4 + 1 + + + HASH1RST + HASH1RST + 5 + 1 + + + RNG1RST + RNG1RST + 6 + 1 + + + AXIMCRST + AXIMCRST + 16 + 1 + + + + + RCC_AHB6RSTSETR + RCC_AHB6RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. + 0x198 + 0x20 + read-write + 0x00000000 + + + GPURST + GPURST + 5 + 1 + + + ETHMACRST + ETHMACRST + 10 + 1 + + + FMCRST + FMCRST + 12 + 1 + + + QSPIRST + QSPIRST + 14 + 1 + + + SDMMC1RST + SDMMC1RST + 16 + 1 + + + SDMMC2RST + SDMMC2RST + 17 + 1 + + + CRC1RST + CRC1RST + 20 + 1 + + + USBHRST + USBHRST + 24 + 1 + + + + + RCC_AHB6RSTCLRR + RCC_AHB6RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. + 0x19C + 0x20 + read-write + 0x00000000 + + + ETHMACRST + ETHMACRST + 10 + 1 + + + FMCRST + FMCRST + 12 + 1 + + + QSPIRST + QSPIRST + 14 + 1 + + + SDMMC1RST + SDMMC1RST + 16 + 1 + + + SDMMC2RST + SDMMC2RST + 17 + 1 + + + CRC1RST + CRC1RST + 20 + 1 + + + USBHRST + USBHRST + 24 + 1 + + + + + RCC_TZAHB6RSTSETR + RCC_TZAHB6RSTSETR + This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MDMARST + MDMARST + 0 + 1 + + + + + RCC_TZAHB6RSTCLRR + RCC_TZAHB6RSTCLRR + This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. + 0x1A4 + 0x20 + read-write + 0x00000000 + + + MDMARST + MDMARST + 0 + 1 + + + + + RCC_MP_APB4ENSETR + RCC_MP_APB4ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x200 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDCEN + 0 + 1 + + + DSIEN + DSIEN + 4 + 1 + + + DDRPERFMEN + DDRPERFMEN + 8 + 1 + + + IWDG2APBEN + IWDG2APBEN + 15 + 1 + + + USBPHYEN + USBPHYEN + 16 + 1 + + + STGENROEN + STGENROEN + 20 + 1 + + + + + RCC_MP_APB4ENCLRR + RCC_MP_APB4ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x204 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDCEN + 0 + 1 + + + DSIEN + DSIEN + 4 + 1 + + + DDRPERFMEN + DDRPERFMEN + 8 + 1 + + + IWDG2APBEN + IWDG2APBEN + 15 + 1 + + + USBPHYEN + USBPHYEN + 16 + 1 + + + STGENROEN + STGENROEN + 20 + 1 + + + + + RCC_MP_APB5ENSETR + RCC_MP_APB5ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x208 + 0x20 + read-write + 0x00000000 + + + SPI6EN + SPI6EN + 0 + 1 + + + I2C4EN + I2C4EN + 2 + 1 + + + I2C6EN + I2C6EN + 3 + 1 + + + USART1EN + USART1EN + 4 + 1 + + + RTCAPBEN + RTCAPBEN + 8 + 1 + + + TZC1EN + TZC1EN + 11 + 1 + + + TZC2EN + TZC2EN + 12 + 1 + + + TZPCEN + TZPCEN + 13 + 1 + + + IWDG1APBEN + IWDG1APBEN + 15 + 1 + + + BSECEN + BSECEN + 16 + 1 + + + STGENEN + STGENEN + 20 + 1 + + + + + RCC_MP_APB5ENCLRR + RCC_MP_APB5ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x20C + 0x20 + read-write + 0x00000000 + + + SPI6EN + SPI6EN + 0 + 1 + + + I2C4EN + I2C4EN + 2 + 1 + + + I2C6EN + I2C6EN + 3 + 1 + + + USART1EN + USART1EN + 4 + 1 + + + RTCAPBEN + RTCAPBEN + 8 + 1 + + + TZC1EN + TZC1EN + 11 + 1 + + + TZC2EN + TZC2EN + 12 + 1 + + + TZPCEN + TZPCEN + 13 + 1 + + + IWDG1APBEN + IWDG1APBEN + 15 + 1 + + + BSECEN + BSECEN + 16 + 1 + + + STGENEN + STGENEN + 20 + 1 + + + + + RCC_MP_AHB5ENSETR + RCC_MP_AHB5ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x210 + 0x20 + read-write + 0x00010000 + + + GPIOZEN + GPIOZEN + 0 + 1 + + + CRYP1EN + CRYP1EN + 4 + 1 + + + HASH1EN + HASH1EN + 5 + 1 + + + RNG1EN + RNG1EN + 6 + 1 + + + BKPSRAMEN + BKPSRAMEN + 8 + 1 + + + AXIMCEN + AXIMCEN + 16 + 1 + + + + + RCC_MP_AHB5ENCLRR + RCC_MP_AHB5ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x214 + 0x20 + read-write + 0x00010000 + + + GPIOZEN + GPIOZEN + 0 + 1 + + + CRYP1EN + CRYP1EN + 4 + 1 + + + HASH1EN + HASH1EN + 5 + 1 + + + RNG1EN + RNG1EN + 6 + 1 + + + BKPSRAMEN + BKPSRAMEN + 8 + 1 + + + AXIMCEN + AXIMCEN + 16 + 1 + + + + + RCC_MP_AHB6ENSETR + RCC_MP_AHB6ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x218 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + GPUEN + GPUEN + 5 + 1 + + + ETHCKEN + ETHCKEN + 7 + 1 + + + ETHTXEN + ETHTXEN + 8 + 1 + + + ETHRXEN + ETHRXEN + 9 + 1 + + + ETHMACEN + ETHMACEN + 10 + 1 + + + FMCEN + FMCEN + 12 + 1 + + + QSPIEN + QSPIEN + 14 + 1 + + + SDMMC1EN + SDMMC1EN + 16 + 1 + + + SDMMC2EN + SDMMC2EN + 17 + 1 + + + CRC1EN + CRC1EN + 20 + 1 + + + USBHEN + USBHEN + 24 + 1 + + + + + RCC_MP_AHB6ENCLRR + RCC_MP_AHB6ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . + 0x21C + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + GPUEN + GPUEN + 5 + 1 + + + ETHCKEN + ETHCKEN + 7 + 1 + + + ETHTXEN + ETHTXEN + 8 + 1 + + + ETHRXEN + ETHRXEN + 9 + 1 + + + ETHMACEN + ETHMACEN + 10 + 1 + + + FMCEN + FMCEN + 12 + 1 + + + QSPIEN + QSPIEN + 14 + 1 + + + SDMMC1EN + SDMMC1EN + 16 + 1 + + + SDMMC2EN + SDMMC2EN + 17 + 1 + + + CRC1EN + CRC1EN + 20 + 1 + + + USBHEN + USBHEN + 24 + 1 + + + + + RCC_MP_TZAHB6ENSETR + RCC_MP_TZAHB6ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x220 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + + + RCC_MP_TZAHB6ENCLRR + RCC_MP_TZAHB6ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x224 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + + + RCC_MC_APB4ENSETR + RCC_MC_APB4ENSETR + This register is used to set the peripheral clock enable bit + 0x280 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDCEN + 0 + 1 + + + DSIEN + DSIEN + 4 + 1 + + + DDRPERFMEN + DDRPERFMEN + 8 + 1 + + + USBPHYEN + USBPHYEN + 16 + 1 + + + STGENROEN + STGENROEN + 20 + 1 + + + + + RCC_MC_APB4ENCLRR + RCC_MC_APB4ENCLRR + This register is used to clear the peripheral clock enable bit + 0x284 + 0x20 + read-write + 0x00000000 + + + LTDCEN + LTDCEN + 0 + 1 + + + DSIEN + DSIEN + 4 + 1 + + + DDRPERFMEN + DDRPERFMEN + 8 + 1 + + + USBPHYEN + USBPHYEN + 16 + 1 + + + STGENROEN + STGENROEN + 20 + 1 + + + + + RCC_MC_APB5ENSETR + RCC_MC_APB5ENSETR + This register is used to set the peripheral clock enable bit + 0x288 + 0x20 + read-write + 0x00000000 + + + SPI6EN + SPI6EN + 0 + 1 + + + I2C4EN + I2C4EN + 2 + 1 + + + I2C6EN + I2C6EN + 3 + 1 + + + USART1EN + USART1EN + 4 + 1 + + + RTCAPBEN + RTCAPBEN + 8 + 1 + + + TZC1EN + TZC1EN + 11 + 1 + + + TZC2EN + TZC2EN + 12 + 1 + + + TZPCEN + TZPCEN + 13 + 1 + + + BSECEN + BSECEN + 16 + 1 + + + STGENEN + STGENEN + 20 + 1 + + + + + RCC_MC_APB5ENCLRR + RCC_MC_APB5ENCLRR + This register is used to clear the peripheral clock enable bit + 0x28C + 0x20 + read-write + 0x00000000 + + + SPI6EN + SPI6EN + 0 + 1 + + + I2C4EN + I2C4EN + 2 + 1 + + + I2C6EN + I2C6EN + 3 + 1 + + + USART1EN + USART1EN + 4 + 1 + + + RTCAPBEN + RTCAPBEN + 8 + 1 + + + TZC1EN + TZC1EN + 11 + 1 + + + TZC2EN + TZC2EN + 12 + 1 + + + TZPCEN + TZPCEN + 13 + 1 + + + BSECEN + BSECEN + 16 + 1 + + + STGENEN + STGENEN + 20 + 1 + + + + + RCC_MC_AHB5ENSETR + RCC_MC_AHB5ENSETR + This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. + 0x290 + 0x20 + read-write + 0x00000000 + + + GPIOZEN + GPIOZEN + 0 + 1 + + + CRYP1EN + CRYP1EN + 4 + 1 + + + HASH1EN + HASH1EN + 5 + 1 + + + RNG1EN + RNG1EN + 6 + 1 + + + BKPSRAMEN + BKPSRAMEN + 8 + 1 + + + + + RCC_MC_AHB5ENCLRR + RCC_MC_AHB5ENCLRR + This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. + 0x294 + 0x20 + read-write + 0x00000000 + + + GPIOZEN + GPIOZEN + 0 + 1 + + + CRYP1EN + CRYP1EN + 4 + 1 + + + HASH1EN + HASH1EN + 5 + 1 + + + RNG1EN + RNG1EN + 6 + 1 + + + BKPSRAMEN + BKPSRAMEN + 8 + 1 + + + + + RCC_MC_AHB6ENSETR + RCC_MC_AHB6ENSETR + This register is used to set the peripheral clock enable bit + 0x298 + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + GPUEN + GPUEN + 5 + 1 + + + ETHCKEN + ETHCKEN + 7 + 1 + + + ETHTXEN + ETHTXEN + 8 + 1 + + + ETHRXEN + ETHRXEN + 9 + 1 + + + ETHMACEN + ETHMACEN + 10 + 1 + + + FMCEN + FMCEN + 12 + 1 + + + QSPIEN + QSPIEN + 14 + 1 + + + SDMMC1EN + SDMMC1EN + 16 + 1 + + + SDMMC2EN + SDMMC2EN + 17 + 1 + + + CRC1EN + CRC1EN + 20 + 1 + + + USBHEN + USBHEN + 24 + 1 + + + + + RCC_MC_AHB6ENCLRR + RCC_MC_AHB6ENCLRR + This register is used to clear the peripheral clock enable bit + 0x29C + 0x20 + read-write + 0x00000000 + + + MDMAEN + MDMAEN + 0 + 1 + + + GPUEN + GPUEN + 5 + 1 + + + ETHCKEN + ETHCKEN + 7 + 1 + + + ETHTXEN + ETHTXEN + 8 + 1 + + + ETHRXEN + ETHRXEN + 9 + 1 + + + ETHMACEN + ETHMACEN + 10 + 1 + + + FMCEN + FMCEN + 12 + 1 + + + QSPIEN + QSPIEN + 14 + 1 + + + SDMMC1EN + SDMMC1EN + 16 + 1 + + + SDMMC2EN + SDMMC2EN + 17 + 1 + + + CRC1EN + CRC1EN + 20 + 1 + + + USBHEN + USBHEN + 24 + 1 + + + + + RCC_MP_APB4LPENSETR + RCC_MP_APB4LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits + 0x300 + 0x20 + read-write + 0x00118111 + + + LTDCLPEN + LTDCLPEN + 0 + 1 + + + DSILPEN + DSILPEN + 4 + 1 + + + DDRPERFMLPEN + DDRPERFMLPEN + 8 + 1 + + + IWDG2APBLPEN + IWDG2APBLPEN + 15 + 1 + + + USBPHYLPEN + USBPHYLPEN + 16 + 1 + + + STGENROLPEN + STGENROLPEN + 20 + 1 + + + STGENROSTPEN + STGENROSTPEN + 21 + 1 + + + + + RCC_MP_APB4LPENCLRR + RCC_MP_APB4LPENCLRR + This register is used by the MCU + 0x304 + 0x20 + read-write + 0x00118111 + + + LTDCLPEN + LTDCLPEN + 0 + 1 + + + DSILPEN + DSILPEN + 4 + 1 + + + DDRPERFMLPEN + DDRPERFMLPEN + 8 + 1 + + + IWDG2APBLPEN + IWDG2APBLPEN + 15 + 1 + + + USBPHYLPEN + USBPHYLPEN + 16 + 1 + + + STGENROLPEN + STGENROLPEN + 20 + 1 + + + STGENROSTPEN + STGENROSTPEN + 21 + 1 + + + + + RCC_MP_APB5LPENSETR + RCC_MP_APB5LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. + 0x308 + 0x20 + read-write + 0x0011391D + + + SPI6LPEN + SPI6LPEN + 0 + 1 + + + I2C4LPEN + I2C4LPEN + 2 + 1 + + + I2C6LPEN + I2C6LPEN + 3 + 1 + + + USART1LPEN + USART1LPEN + 4 + 1 + + + RTCAPBLPEN + RTCAPBLPEN + 8 + 1 + + + TZC1LPEN + TZC1LPEN + 11 + 1 + + + TZC2LPEN + TZC2LPEN + 12 + 1 + + + TZPCLPEN + TZPCLPEN + 13 + 1 + + + IWDG1APBLPEN + IWDG1APBLPEN + 15 + 1 + + + BSECLPEN + BSECLPEN + 16 + 1 + + + STGENLPEN + STGENLPEN + 20 + 1 + + + STGENSTPEN + STGENSTPEN + 21 + 1 + + + + + RCC_MP_APB5LPENCLRR + RCC_MP_APB5LPENCLRR + This register is used by the Mpu. + 0x30C + 0x20 + read-write + 0x0011391D + + + SPI6LPEN + SPI6LPEN + 0 + 1 + + + I2C4LPEN + I2C4LPEN + 2 + 1 + + + I2C6LPEN + I2C6LPEN + 3 + 1 + + + USART1LPEN + USART1LPEN + 4 + 1 + + + RTCAPBLPEN + RTCAPBLPEN + 8 + 1 + + + TZC1LPEN + TZC1LPEN + 11 + 1 + + + TZC2LPEN + TZC2LPEN + 12 + 1 + + + TZPCLPEN + TZPCLPEN + 13 + 1 + + + IWDG1APBLPEN + IWDG1APBLPEN + 15 + 1 + + + BSECLPEN + BSECLPEN + 16 + 1 + + + STGENLPEN + STGENLPEN + 20 + 1 + + + STGENSTPEN + STGENSTPEN + 21 + 1 + + + + + RCC_MP_AHB5LPENSETR + RCC_MP_AHB5LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. + 0x310 + 0x20 + read-write + 0x00000171 + + + GPIOZLPEN + GPIOZLPEN + 0 + 1 + + + CRYP1LPEN + CRYP1LPEN + 4 + 1 + + + HASH1LPEN + HASH1LPEN + 5 + 1 + + + RNG1LPEN + RNG1LPEN + 6 + 1 + + + BKPSRAMLPEN + BKPSRAMLPEN + 8 + 1 + + + + + RCC_MP_AHB5LPENCLRR + RCC_MP_AHB5LPENCLRR + This register is used by the MCU + 0x314 + 0x20 + read-write + 0x00000171 + + + GPIOZLPEN + GPIOZLPEN + 0 + 1 + + + CRYP1LPEN + CRYP1LPEN + 4 + 1 + + + HASH1LPEN + HASH1LPEN + 5 + 1 + + + RNG1LPEN + RNG1LPEN + 6 + 1 + + + BKPSRAMLPEN + BKPSRAMLPEN + 8 + 1 + + + + + RCC_MP_AHB6LPENSETR + RCC_MP_AHB6LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits + 0x318 + 0x20 + read-write + 0x011357A1 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + GPULPEN + GPULPEN + 5 + 1 + + + ETHCKLPEN + ETHCKLPEN + 7 + 1 + + + ETHTXLPEN + ETHTXLPEN + 8 + 1 + + + ETHRXLPEN + ETHRXLPEN + 9 + 1 + + + ETHMACLPEN + ETHMACLPEN + 10 + 1 + + + ETHSTPEN + ETHSTPEN + 11 + 1 + + + FMCLPEN + FMCLPEN + 12 + 1 + + + QSPILPEN + QSPILPEN + 14 + 1 + + + SDMMC1LPEN + SDMMC1LPEN + 16 + 1 + + + SDMMC2LPEN + SDMMC2LPEN + 17 + 1 + + + CRC1LPEN + CRC1LPEN + 20 + 1 + + + USBHLPEN + USBHLPEN + 24 + 1 + + + + + RCC_MP_AHB6LPENCLRR + RCC_MP_AHB6LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits + 0x31C + 0x20 + read-write + 0x011357A1 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + GPULPEN + GPULPEN + 5 + 1 + + + ETHCKLPEN + ETHCKLPEN + 7 + 1 + + + ETHTXLPEN + ETHTXLPEN + 8 + 1 + + + ETHRXLPEN + ETHRXLPEN + 9 + 1 + + + ETHMACLPEN + ETHMACLPEN + 10 + 1 + + + ETHSTPEN + ETHSTPEN + 11 + 1 + + + FMCLPEN + FMCLPEN + 12 + 1 + + + QSPILPEN + QSPILPEN + 14 + 1 + + + SDMMC1LPEN + SDMMC1LPEN + 16 + 1 + + + SDMMC2LPEN + SDMMC2LPEN + 17 + 1 + + + CRC1LPEN + CRC1LPEN + 20 + 1 + + + USBHLPEN + USBHLPEN + 24 + 1 + + + + + RCC_MP_TZAHB6LPENSETR + RCC_MP_TZAHB6LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. + 0x320 + 0x20 + read-write + 0x00000001 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + + + RCC_MP_TZAHB6LPENCLRR + RCC_MP_TZAHB6LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. + 0x324 + 0x20 + read-write + 0x00000001 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + + + RCC_MC_APB4LPENSETR + RCC_MC_APB4LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0x380 + 0x20 + read-write + 0x00110111 + + + LTDCLPEN + LTDCLPEN + 0 + 1 + + + DSILPEN + DSILPEN + 4 + 1 + + + DDRPERFMLPEN + DDRPERFMLPEN + 8 + 1 + + + USBPHYLPEN + USBPHYLPEN + 16 + 1 + + + STGENROLPEN + STGENROLPEN + 20 + 1 + + + STGENROSTPEN + STGENROSTPEN + 21 + 1 + + + + + RCC_MC_APB4LPENCLRR + RCC_MC_APB4LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0x384 + 0x20 + read-write + 0x00110111 + + + LTDCLPEN + LTDCLPEN + 0 + 1 + + + DSILPEN + DSILPEN + 4 + 1 + + + DDRPERFMLPEN + DDRPERFMLPEN + 8 + 1 + + + USBPHYLPEN + USBPHYLPEN + 16 + 1 + + + STGENROLPEN + STGENROLPEN + 20 + 1 + + + STGENROSTPEN + STGENROSTPEN + 21 + 1 + + + + + RCC_MC_APB5LPENSETR + RCC_MC_APB5LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0x388 + 0x20 + read-write + 0x0011391D + + + SPI6LPEN + SPI6LPEN + 0 + 1 + + + I2C4LPEN + I2C4LPEN + 2 + 1 + + + I2C6LPEN + I2C6LPEN + 3 + 1 + + + USART1LPEN + USART1LPEN + 4 + 1 + + + RTCAPBLPEN + RTCAPBLPEN + 8 + 1 + + + TZC1LPEN + TZC1LPEN + 11 + 1 + + + TZC2LPEN + TZC2LPEN + 12 + 1 + + + TZPCLPEN + TZPCLPEN + 13 + 1 + + + BSECLPEN + BSECLPEN + 16 + 1 + + + STGENLPEN + STGENLPEN + 20 + 1 + + + STGENSTPEN + STGENSTPEN + 21 + 1 + + + + + RCC_MC_APB5LPENCLRR + RCC_MC_APB5LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0x38C + 0x20 + read-write + 0x0011391D + + + SPI6LPEN + SPI6LPEN + 0 + 1 + + + I2C4LPEN + I2C4LPEN + 2 + 1 + + + I2C6LPEN + I2C6LPEN + 3 + 1 + + + USART1LPEN + USART1LPEN + 4 + 1 + + + RTCAPBLPEN + RTCAPBLPEN + 8 + 1 + + + TZC1LPEN + TZC1LPEN + 11 + 1 + + + TZC2LPEN + TZC2LPEN + 12 + 1 + + + TZPCLPEN + TZPCLPEN + 13 + 1 + + + BSECLPEN + BSECLPEN + 16 + 1 + + + STGENLPEN + STGENLPEN + 20 + 1 + + + STGENSTPEN + STGENSTPEN + 21 + 1 + + + + + RCC_MC_AHB5LPENSETR + RCC_MC_AHB5LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode. + 0x390 + 0x20 + read-write + 0x00000171 + + + GPIOZLPEN + GPIOZLPEN + 0 + 1 + + + CRYP1LPEN + CRYP1LPEN + 4 + 1 + + + HASH1LPEN + HASH1LPEN + 5 + 1 + + + RNG1LPEN + RNG1LPEN + 6 + 1 + + + BKPSRAMLPEN + BKPSRAMLPEN + 8 + 1 + + + + + RCC_MC_AHB5LPENCLRR + RCC_MC_AHB5LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode. + 0x394 + 0x20 + read-write + 0x00000171 + + + GPIOZLPEN + GPIOZLPEN + 0 + 1 + + + CRYP1LPEN + CRYP1LPEN + 4 + 1 + + + HASH1LPEN + HASH1LPEN + 5 + 1 + + + RNG1LPEN + RNG1LPEN + 6 + 1 + + + BKPSRAMLPEN + BKPSRAMLPEN + 8 + 1 + + + + + RCC_MC_AHB6LPENSETR + RCC_MC_AHB6LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0x398 + 0x20 + read-write + 0x011357A1 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + GPULPEN + GPULPEN + 5 + 1 + + + ETHCKLPEN + ETHCKLPEN + 7 + 1 + + + ETHTXLPEN + ETHTXLPEN + 8 + 1 + + + ETHRXLPEN + ETHRXLPEN + 9 + 1 + + + ETHMACLPEN + ETHMACLPEN + 10 + 1 + + + ETHSTPEN + ETHSTPEN + 11 + 1 + + + FMCLPEN + FMCLPEN + 12 + 1 + + + QSPILPEN + QSPILPEN + 14 + 1 + + + SDMMC1LPEN + SDMMC1LPEN + 16 + 1 + + + SDMMC2LPEN + SDMMC2LPEN + 17 + 1 + + + CRC1LPEN + CRC1LPEN + 20 + 1 + + + USBHLPEN + USBHLPEN + 24 + 1 + + + + + RCC_MC_AHB6LPENCLRR + RCC_MC_AHB6LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0x39C + 0x20 + read-write + 0x011357A1 + + + MDMALPEN + MDMALPEN + 0 + 1 + + + GPULPEN + GPULPEN + 5 + 1 + + + ETHCKLPEN + ETHCKLPEN + 7 + 1 + + + ETHTXLPEN + ETHTXLPEN + 8 + 1 + + + ETHRXLPEN + ETHRXLPEN + 9 + 1 + + + ETHMACLPEN + ETHMACLPEN + 10 + 1 + + + ETHSTPEN + ETHSTPEN + 11 + 1 + + + FMCLPEN + FMCLPEN + 12 + 1 + + + QSPILPEN + QSPILPEN + 14 + 1 + + + SDMMC1LPEN + SDMMC1LPEN + 16 + 1 + + + SDMMC2LPEN + SDMMC2LPEN + 17 + 1 + + + CRC1LPEN + CRC1LPEN + 20 + 1 + + + USBHLPEN + USBHLPEN + 24 + 1 + + + + + RCC_BR_RSTSCLRR + RCC_BR_RSTSCLRR + This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode. + 0x400 + 0x20 + read-write + 0x00000015 + + + PORRSTF + PORRSTF + 0 + 1 + + + BORRSTF + BORRSTF + 1 + 1 + + + PADRSTF + PADRSTF + 2 + 1 + + + HCSSRSTF + HCSSRSTF + 3 + 1 + + + VCORERSTF + VCORERSTF + 4 + 1 + + + MPSYSRSTF + MPSYSRSTF + 6 + 1 + + + MCSYSRSTF + MCSYSRSTF + 7 + 1 + + + IWDG1RSTF + IWDG1RSTF + 8 + 1 + + + IWDG2RSTF + IWDG2RSTF + 9 + 1 + + + MPUP0RSTF + MPUP0RSTF + 13 + 1 + + + MPUP1RSTF + MPUP1RSTF + 14 + 1 + + + + + RCC_MP_GRSTCSETR + RCC_MP_GRSTCSETR + This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset. + 0x404 + 0x20 + read-write + 0x00000000 + + + MPSYSRST + MPSYSRST + 0 + 1 + + + MCURST + MCURST + 1 + 1 + + + MPUP0RST + MPUP0RST + 4 + 1 + + + MPUP1RST + MPUP1RST + 5 + 1 + + + + + RCC_MP_RSTSCLRR + RCC_MP_RSTSCLRR + This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. + 0x408 + 0x20 + read-write + 0x00000000 + + + PORRSTF + PORRSTF + 0 + 1 + + + BORRSTF + BORRSTF + 1 + 1 + + + PADRSTF + PADRSTF + 2 + 1 + + + HCSSRSTF + HCSSRSTF + 3 + 1 + + + VCORERSTF + VCORERSTF + 4 + 1 + + + MPSYSRSTF + MPSYSRSTF + 6 + 1 + + + MCSYSRSTF + MCSYSRSTF + 7 + 1 + + + IWDG1RSTF + IWDG1RSTF + 8 + 1 + + + IWDG2RSTF + IWDG2RSTF + 9 + 1 + + + STDBYRSTF + STDBYRSTF + 11 + 1 + + + CSTDBYRSTF + CSTDBYRSTF + 12 + 1 + + + MPUP0RSTF + MPUP0RSTF + 13 + 1 + + + MPUP1RSTF + MPUP1RSTF + 14 + 1 + + + SPARE + SPARE + 15 + 1 + + + + + RCC_MP_IWDGFZSETR + RCC_MP_IWDGFZSETR + This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x40C + 0x20 + read-write + 0x00000000 + + + FZ_IWDG1 + FZ_IWDG1 + 0 + 1 + + + FZ_IWDG2 + FZ_IWDG2 + 1 + 1 + + + + + RCC_MP_IWDGFZCLRR + RCC_MP_IWDGFZCLRR + This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode. + 0x410 + 0x20 + read-write + 0x00000000 + + + FZ_IWDG1 + FZ_IWDG1 + 0 + 1 + + + FZ_IWDG2 + FZ_IWDG2 + 1 + 1 + + + + + RCC_MP_CIER + RCC_MP_CIER + This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. + 0x414 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSIRDYIE + 0 + 1 + + + LSERDYIE + LSERDYIE + 1 + 1 + + + HSIRDYIE + HSIRDYIE + 2 + 1 + + + HSERDYIE + HSERDYIE + 3 + 1 + + + CSIRDYIE + CSIRDYIE + 4 + 1 + + + PLL1DYIE + PLL1DYIE + 8 + 1 + + + PLL2DYIE + PLL2DYIE + 9 + 1 + + + PLL3DYIE + PLL3DYIE + 10 + 1 + + + PLL4DYIE + PLL4DYIE + 11 + 1 + + + LSECSSIE + LSECSSIE + 16 + 1 + + + WKUPIE + WKUPIE + 20 + 1 + + + + + RCC_MP_CIFR + RCC_MP_CIFR + This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. + 0x418 + 0x20 + read-write + 0x00000000 + + + LSIRDYF + LSIRDYF + 0 + 1 + + + LSERDYF + LSERDYF + 1 + 1 + + + HSIRDYF + HSIRDYF + 2 + 1 + + + HSERDYF + HSERDYF + 3 + 1 + + + CSIRDYF + CSIRDYF + 4 + 1 + + + PLL1DYF + PLL1DYF + 8 + 1 + + + PLL2DYF + PLL2DYF + 9 + 1 + + + PLL3DYF + PLL3DYF + 10 + 1 + + + PLL4DYF + PLL4DYF + 11 + 1 + + + LSECSSF + LSECSSF + 16 + 1 + + + WKUPF + WKUPF + 20 + 1 + + + + + RCC_PWRLPDLYCR + RCC_PWRLPDLYCR + This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode. + 0x41C + 0x20 + read-write + 0x00000000 + + + PWRLP_DLY + PWRLP_DLY + 0 + 22 + + + MCTMPSKP + MCTMPSKP + 24 + 1 + + + + + RCC_MP_RSTSSETR + RCC_MP_RSTSSETR + This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. + 0x420 + 0x20 + read-write + 0x00000000 + + + PORRSTF + PORRSTF + 0 + 1 + + + BORRSTF + BORRSTF + 1 + 1 + + + PADRSTF + PADRSTF + 2 + 1 + + + HCSSRSTF + HCSSRSTF + 3 + 1 + + + VCORERSTF + VCORERSTF + 4 + 1 + + + MPSYSRSTF + MPSYSRSTF + 6 + 1 + + + MCSYSRSTF + MCSYSRSTF + 7 + 1 + + + IWDG1RSTF + IWDG1RSTF + 8 + 1 + + + IWDG2RSTF + IWDG2RSTF + 9 + 1 + + + STDBYRSTF + STDBYRSTF + 11 + 1 + + + CSTDBYRSTF + CSTDBYRSTF + 12 + 1 + + + MPUP0RSTF + MPUP0RSTF + 13 + 1 + + + MPUP1RSTF + MPUP1RSTF + 14 + 1 + + + SPARE + SPARE + 15 + 1 + + + + + RCC_MCO1CFGR + RCC_MCO1CFGR + This register is used to select the clock generated on MCO1 output. + 0x800 + 0x20 + read-write + 0x00000000 + + + MCO1SEL + MCO1SEL + 0 + 3 + + + MCO1DIV + MCO1DIV + 4 + 4 + + + MCO1ON + MCO1ON + 12 + 1 + + + + + RCC_MCO2CFGR + RCC_MCO2CFGR + This register is used to select the clock generated on MCO2 output. + 0x804 + 0x20 + read-write + 0x00000000 + + + MCO2SEL + MCO2SEL + 0 + 3 + + + MCO2DIV + MCO2DIV + 4 + 4 + + + MCO2ON + MCO2ON + 12 + 1 + + + + + RCC_OCRDYR + RCC_OCRDYR + This is a read-only access register, It contains the status flags of oscillators. Writing has no effect. + 0x808 + 0x20 + read-only + 0x00000000 + + + HSIRDY + HSIRDY + 0 + 1 + + + HSIDIVRDY + HSIDIVRDY + 2 + 1 + + + CSIRDY + CSIRDY + 4 + 1 + + + HSERDY + HSERDY + 8 + 1 + + + MPUCKRDY + MPUCKRDY + 23 + 1 + + + AXICKRDY + AXICKRDY + 24 + 1 + + + CKREST + CKREST + 25 + 1 + + + + + RCC_DBGCFGR + RCC_DBGCFGR + This is register contains the enable control of the debug and trace function, and the clock divider for the trace function. + 0x80C + 0x20 + read-write + 0x00000001 + + + TRACEDIV + TRACEDIV + 0 + 3 + + + DBGCKEN + DBGCKEN + 8 + 1 + + + TRACECKEN + TRACECKEN + 9 + 1 + + + DBGRST + DBGRST + 12 + 1 + + + + + RCC_RCK3SELR + RCC_RCK3SELR + This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x820 + 0x20 + 0x80000000 + + + PLL3SRC + PLL3SRC + 0 + 2 + read-write + + + PLL3SRCRDY + PLL3SRCRDY + 31 + 1 + read-only + + + + + RCC_RCK4SELR + RCC_RCK4SELR + This register is used to select the reference clock for PLL4. + 0x824 + 0x20 + 0x80000000 + + + PLL4SRC + PLL4SRC + 0 + 2 + read-write + + + PLL4SRCRDY + PLL4SRCRDY + 31 + 1 + read-only + + + + + RCC_TIMG1PRER + RCC_TIMG1PRER + This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information. + 0x828 + 0x20 + 0x80000000 + + + TIMG1PRE + TIMG1PRE + 0 + 1 + read-write + + + TIMG1PRERDY + TIMG1PRERDY + 31 + 1 + read-only + + + + + RCC_TIMG2PRER + RCC_TIMG2PRER + This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information. + 0x82C + 0x20 + 0x80000000 + + + TIMG2PRE + TIMG2PRE + 0 + 1 + read-write + + + TIMG2PRERDY + TIMG2PRERDY + 31 + 1 + read-only + + + + + RCC_MCUDIVR + RCC_MCUDIVR + This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. + 0x830 + 0x20 + 0x80000000 + + + MCUDIV + MCUDIV + 0 + 4 + read-write + + + MCUDIVRDY + MCUDIVRDY + 31 + 1 + read-only + + + + + RCC_APB1DIVR + RCC_APB1DIVR + This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information. + 0x834 + 0x20 + 0x80000000 + + + APB1DIV + APB1DIV + 0 + 3 + read-write + + + APB1DIVRDY + APB1DIVRDY + 31 + 1 + read-only + + + + + RCC_APB2DIVR + RCC_APB2DIVR + This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information. + 0x838 + 0x20 + 0x80000000 + + + APB2DIV + APB2DIV + 0 + 3 + read-write + + + APB2DIVRDY + APB2DIVRDY + 31 + 1 + read-only + + + + + RCC_APB3DIVR + RCC_APB3DIVR + This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information. + 0x83C + 0x20 + 0x80000000 + + + APB3DIV + APB3DIV + 0 + 3 + read-write + + + APB3DIVRDY + APB3DIVRDY + 31 + 1 + read-only + + + + + RCC_PLL3CR + RCC_PLL3CR + This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x880 + 0x20 + 0x00000000 + + + PLLON + PLLON + 0 + 1 + read-write + + + PLL3RDY + PLL3RDY + 1 + 1 + read-only + + + SSCG_CTRL + SSCG_CTRL + 2 + 1 + read-write + + + DIVPEN + DIVPEN + 4 + 1 + read-write + + + DIVQEN + DIVQEN + 5 + 1 + read-write + + + DIVREN + DIVREN + 6 + 1 + read-write + + + + + RCC_PLL3CFGR1 + RCC_PLL3CFGR1 + This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x884 + 0x20 + read-write + 0x00010031 + + + DIVN + DIVN + 0 + 9 + + + DIVM3 + DIVM3 + 16 + 6 + + + IFRGE + IFRGE + 24 + 2 + + + + + RCC_PLL3CFGR2 + RCC_PLL3CFGR2 + This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x888 + 0x20 + read-write + 0x00010101 + + + DIVP + DIVP + 0 + 7 + + + DIVQ + DIVQ + 8 + 7 + + + DIVR + DIVR + 16 + 7 + + + + + RCC_PLL3FRACR + RCC_PLL3FRACR + This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x88C + 0x20 + read-write + 0x00000000 + + + FRACV + FRACV + 3 + 13 + + + FRACLE + FRACLE + 16 + 1 + + + + + RCC_PLL3CSGR + RCC_PLL3CSGR + This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x890 + 0x20 + read-write + 0x00000000 + + + MOD_PER + MOD_PER + 0 + 13 + + + TPDFN_DIS + TPDFN_DIS + 13 + 1 + + + RPDFN_DIS + RPDFN_DIS + 14 + 1 + + + SSCG_MODE + SSCG_MODE + 15 + 1 + + + INC_STEP + INC_STEP + 16 + 15 + + + + + RCC_PLL4CR + RCC_PLL4CR + This register is used to control the PLL4. + 0x894 + 0x20 + 0x00000000 + + + PLLON + PLLON + 0 + 1 + read-write + + + PLL4RDY + PLL4RDY + 1 + 1 + read-only + + + SSCG_CTRL + SSCG_CTRL + 2 + 1 + read-write + + + DIVPEN + DIVPEN + 4 + 1 + read-write + + + DIVQEN + DIVQEN + 5 + 1 + read-write + + + DIVREN + DIVREN + 6 + 1 + read-write + + + + + RCC_PLL4CFGR1 + RCC_PLL4CFGR1 + This register is used to configure the PLL4. + 0x898 + 0x20 + read-write + 0x00010031 + + + DIVN + DIVN + 0 + 9 + + + DIVM4 + DIVM4 + 16 + 6 + + + IFRGE + IFRGE + 24 + 2 + + + + + RCC_PLL4CFGR2 + RCC_PLL4CFGR2 + This register is used to configure the PLL4. + 0x89C + 0x20 + read-write + 0x00000000 + + + DIVP + DIVP + 0 + 7 + + + DIVQ + DIVQ + 8 + 7 + + + DIVR + DIVR + 16 + 7 + + + + + RCC_PLL4FRACR + RCC_PLL4FRACR + This register is used to fine-tune the frequency of the PLL4 VCO. + 0x8A0 + 0x20 + read-write + 0x00000000 + + + FRACV + FRACV + 3 + 13 + + + FRACLE + FRACLE + 16 + 1 + + + + + RCC_PLL4CSGR + RCC_PLL4CSGR + This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. + 0x8A4 + 0x20 + read-write + 0x00000000 + + + MOD_PER + MOD_PER + 0 + 13 + + + TPDFN_DIS + TPDFN_DIS + 13 + 1 + + + RPDFN_DIS + RPDFN_DIS + 14 + 1 + + + SSCG_MODE + SSCG_MODE + 15 + 1 + + + INC_STEP + INC_STEP + 16 + 15 + + + + + RCC_I2C12CKSELR + RCC_I2C12CKSELR + This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8C0 + 0x20 + read-write + 0x00000000 + + + I2C12SRC + I2C12SRC + 0 + 3 + + + + + RCC_I2C35CKSELR + RCC_I2C35CKSELR + This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8C4 + 0x20 + read-write + 0x00000000 + + + I2C35SRC + I2C35SRC + 0 + 3 + + + + + RCC_SAI1CKSELR + RCC_SAI1CKSELR + This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8C8 + 0x20 + read-write + 0x00000000 + + + SAI1SRC + SAI1SRC + 0 + 3 + + + + + RCC_SAI2CKSELR + RCC_SAI2CKSELR + This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8CC + 0x20 + read-write + 0x00000000 + + + SAI2SRC + SAI2SRC + 0 + 3 + + + + + RCC_SAI3CKSELR + RCC_SAI3CKSELR + This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8D0 + 0x20 + read-write + 0x00000000 + + + SAI3SRC + SAI3SRC + 0 + 3 + + + + + RCC_SAI4CKSELR + RCC_SAI4CKSELR + This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8D4 + 0x20 + read-write + 0x00000000 + + + SAI4SRC + SAI4SRC + 0 + 3 + + + + + RCC_SPI2S1CKSELR + RCC_SPI2S1CKSELR + This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8D8 + 0x20 + read-write + 0x00000000 + + + SPI1SRC + SPI1SRC + 0 + 3 + + + + + RCC_SPI2S23CKSELR + RCC_SPI2S23CKSELR + This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8DC + 0x20 + read-write + 0x00000000 + + + SPI23SRC + SPI23SRC + 0 + 3 + + + + + RCC_SPI45CKSELR + RCC_SPI45CKSELR + This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8E0 + 0x20 + read-write + 0x00000000 + + + SPI45SRC + SPI45SRC + 0 + 3 + + + + + RCC_UART6CKSELR + RCC_UART6CKSELR + This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8E4 + 0x20 + read-write + 0x00000000 + + + UART6SRC + UART6SRC + 0 + 3 + + + + + RCC_UART24CKSELR + RCC_UART24CKSELR + This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8E8 + 0x20 + read-write + 0x00000000 + + + UART24SRC + UART24SRC + 0 + 3 + + + + + RCC_UART35CKSELR + RCC_UART35CKSELR + This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8EC + 0x20 + read-write + 0x00000000 + + + UART35SRC + UART35SRC + 0 + 3 + + + + + RCC_UART78CKSELR + RCC_UART78CKSELR + This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8F0 + 0x20 + read-write + 0x00000000 + + + UART78SRC + UART78SRC + 0 + 3 + + + + + RCC_SDMMC12CKSELR + RCC_SDMMC12CKSELR + This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8F4 + 0x20 + read-write + 0x00000003 + + + SDMMC12SRC + SDMMC12SRC + 0 + 3 + + + + + RCC_SDMMC3CKSELR + RCC_SDMMC3CKSELR + This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8F8 + 0x20 + read-write + 0x00000000 + + + SDMMC3SRC + SDMMC3SRC + 0 + 3 + + + + + RCC_ETHCKSELR + RCC_ETHCKSELR + This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x8FC + 0x20 + read-write + 0x00000000 + + + ETHSRC + ETHSRC + 0 + 2 + + + ETHPTPDIV + ETHPTPDIV + 4 + 4 + + + + + RCC_QSPICKSELR + RCC_QSPICKSELR + This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x900 + 0x20 + read-write + 0x00000000 + + + QSPISRC + QSPISRC + 0 + 2 + + + + + RCC_FMCCKSELR + RCC_FMCCKSELR + This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x904 + 0x20 + read-write + 0x00000000 + + + FMCSRC + FMCSRC + 0 + 2 + + + + + RCC_FDCANCKSELR + RCC_FDCANCKSELR + This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x90C + 0x20 + read-write + 0x00000000 + + + FDCANSRC + FDCANSRC + 0 + 2 + + + + + RCC_SPDIFCKSELR + RCC_SPDIFCKSELR + This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. + 0x914 + 0x20 + read-write + 0x00000000 + + + SPDIFSRC + SPDIFSRC + 0 + 2 + + + + + RCC_CECCKSELR + RCC_CECCKSELR + This register is used to control the selection of the kernel clock for the CEC-HDMI. + 0x918 + 0x20 + read-write + 0x00000000 + + + CECSRC + CECSRC + 0 + 2 + + + + + RCC_USBCKSELR + RCC_USBCKSELR + This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG + 0x91C + 0x20 + read-write + 0x00000000 + + + USBPHYSRC + USBPHYSRC + 0 + 2 + + + USBOSRC + USBOSRC + 4 + 1 + + + + + RCC_RNG2CKSELR + RCC_RNG2CKSELR + This register is used to control the selection of the kernel clock for the RNG2. + 0x920 + 0x20 + read-write + 0x00000000 + + + RNG2SRC + RNG2SRC + 0 + 2 + + + + + RCC_DSICKSELR + RCC_DSICKSELR + This register is used to control the selection of the kernel clock for the DSI block. + 0x924 + 0x20 + read-write + 0x00000000 + + + DSISRC + DSISRC + 0 + 1 + + + + + RCC_ADCCKSELR + RCC_ADCCKSELR + This register is used to control the selection of the kernel clock for the ADC block. + 0x928 + 0x20 + read-write + 0x00000000 + + + ADCSRC + ADCSRC + 0 + 2 + + + + + RCC_LPTIM45CKSELR + RCC_LPTIM45CKSELR + This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. + 0x92C + 0x20 + read-write + 0x00000000 + + + LPTIM45SRC + LPTIM45SRC + 0 + 3 + + + + + RCC_LPTIM23CKSELR + RCC_LPTIM23CKSELR + This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. + 0x930 + 0x20 + read-write + 0x00000000 + + + LPTIM23SRC + LPTIM23SRC + 0 + 3 + + + + + RCC_LPTIM1CKSELR + RCC_LPTIM1CKSELR + This register is used to control the selection of the kernel clock for the LPTIM1 block. + 0x934 + 0x20 + read-write + 0x00000000 + + + LPTIM1SRC + LPTIM1SRC + 0 + 3 + + + + + RCC_APB1RSTSETR + RCC_APB1RSTSETR + This register is used to activate the reset of the corresponding peripheral. + 0x980 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2RST + 0 + 1 + + + TIM3RST + TIM3RST + 1 + 1 + + + TIM4RST + TIM4RST + 2 + 1 + + + TIM5RST + TIM5RST + 3 + 1 + + + TIM6RST + TIM6RST + 4 + 1 + + + TIM7RST + TIM7RST + 5 + 1 + + + TIM12RST + TIM12RST + 6 + 1 + + + TIM13RST + TIM13RST + 7 + 1 + + + TIM14RST + TIM14RST + 8 + 1 + + + LPTIM1RST + LPTIM1RST + 9 + 1 + + + SPI2RST + SPI2RST + 11 + 1 + + + SPI3RST + SPI3RST + 12 + 1 + + + USART2RST + USART2RST + 14 + 1 + + + USART3RST + USART3RST + 15 + 1 + + + UART4RST + UART4RST + 16 + 1 + + + UART5RST + UART5RST + 17 + 1 + + + UART7RST + UART7RST + 18 + 1 + + + UART8RST + UART8RST + 19 + 1 + + + I2C1RST + I2C1RST + 21 + 1 + + + I2C2RST + I2C2RST + 22 + 1 + + + I2C3RST + I2C3RST + 23 + 1 + + + I2C5RST + I2C5RST + 24 + 1 + + + SPDIFRST + SPDIFRST + 26 + 1 + + + CECRST + CECRST + 27 + 1 + + + DAC12RST + DAC12RST + 29 + 1 + + + MDIOSRST + MDIOSRST + 31 + 1 + + + + + RCC_APB1RSTCLRR + RCC_APB1RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x984 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2RST + 0 + 1 + + + TIM3RST + TIM3RST + 1 + 1 + + + TIM4RST + TIM4RST + 2 + 1 + + + TIM5RST + TIM5RST + 3 + 1 + + + TIM6RST + TIM6RST + 4 + 1 + + + TIM7RST + TIM7RST + 5 + 1 + + + TIM12RST + TIM12RST + 6 + 1 + + + TIM13RST + TIM13RST + 7 + 1 + + + TIM14RST + TIM14RST + 8 + 1 + + + LPTIM1RST + LPTIM1RST + 9 + 1 + + + SPI2RST + SPI2RST + 11 + 1 + + + SPI3RST + SPI3RST + 12 + 1 + + + USART2RST + USART2RST + 14 + 1 + + + USART3RST + USART3RST + 15 + 1 + + + UART4RST + UART4RST + 16 + 1 + + + UART5RST + UART5RST + 17 + 1 + + + UART7RST + UART7RST + 18 + 1 + + + UART8RST + UART8RST + 19 + 1 + + + I2C1RST + I2C1RST + 21 + 1 + + + I2C2RST + I2C2RST + 22 + 1 + + + I2C3RST + I2C3RST + 23 + 1 + + + I2C5RST + I2C5RST + 24 + 1 + + + SPDIFRST + SPDIFRST + 26 + 1 + + + CECRST + CECRST + 27 + 1 + + + DAC12RST + DAC12RST + 29 + 1 + + + MDIOSRST + MDIOSRST + 31 + 1 + + + + + RCC_APB2RSTSETR + RCC_APB2RSTSETR + This register is used to activate the reset of the corresponding peripheral. + 0x988 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1RST + 0 + 1 + + + TIM8RST + TIM8RST + 1 + 1 + + + TIM15RST + TIM15RST + 2 + 1 + + + TIM16RST + TIM16RST + 3 + 1 + + + TIM17RST + TIM17RST + 4 + 1 + + + SPI1RST + SPI1RST + 8 + 1 + + + SPI4RST + SPI4RST + 9 + 1 + + + SPI5RST + SPI5RST + 10 + 1 + + + USART6RST + USART6RST + 13 + 1 + + + SAI1RST + SAI1RST + 16 + 1 + + + SAI2RST + SAI2RST + 17 + 1 + + + SAI3RST + SAI3RST + 18 + 1 + + + DFSDMRST + DFSDMRST + 20 + 1 + + + FDCANRST + FDCANRST + 24 + 1 + + + + + RCC_APB2RSTCLRR + RCC_APB2RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x98C + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1RST + 0 + 1 + + + TIM8RST + TIM8RST + 1 + 1 + + + TIM15RST + TIM15RST + 2 + 1 + + + TIM16RST + TIM16RST + 3 + 1 + + + TIM17RST + TIM17RST + 4 + 1 + + + SPI1RST + SPI1RST + 8 + 1 + + + SPI4RST + SPI4RST + 9 + 1 + + + SPI5RST + SPI5RST + 10 + 1 + + + USART6RST + USART6RST + 13 + 1 + + + SAI1RST + SAI1RST + 16 + 1 + + + SAI2RST + SAI2RST + 17 + 1 + + + SAI3RST + SAI3RST + 18 + 1 + + + DFSDMRST + DFSDMRST + 20 + 1 + + + FDCANRST + FDCANRST + 24 + 1 + + + + + RCC_APB3RSTSETR + RCC_APB3RSTSETR + This register is used to activate the reset of the corresponding peripheral. + 0x990 + 0x20 + read-write + 0x00000000 + + + LPTIM2RST + LPTIM2RST + 0 + 1 + + + LPTIM3RST + LPTIM3RST + 1 + 1 + + + LPTIM4RST + LPTIM4RST + 2 + 1 + + + LPTIM5RST + LPTIM5RST + 3 + 1 + + + SAI4RST + SAI4RST + 8 + 1 + + + SYSCFGRST + SYSCFGRST + 11 + 1 + + + VREFRST + VREFRST + 13 + 1 + + + DTSRST + DTSRST + 16 + 1 + + + + + RCC_APB3RSTCLRR + RCC_APB3RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x994 + 0x20 + read-write + 0x00000000 + + + LPTIM2RST + LPTIM2RST + 0 + 1 + + + LPTIM3RST + LPTIM3RST + 1 + 1 + + + LPTIM4RST + LPTIM4RST + 2 + 1 + + + LPTIM5RST + LPTIM5RST + 3 + 1 + + + SAI4RST + SAI4RST + 8 + 1 + + + SYSCFGRST + SYSCFGRST + 11 + 1 + + + VREFRST + VREFRST + 13 + 1 + + + DTSRST + DTSRST + 16 + 1 + + + + + RCC_AHB2RSTSETR + RCC_AHB2RSTSETR + This register is used to activate the reset of the corresponding peripheral. + 0x998 + 0x20 + read-write + 0x00000000 + + + DMA1RST + DMA1RST + 0 + 1 + + + DMA2RST + DMA2RST + 1 + 1 + + + DMAMUXRST + DMAMUXRST + 2 + 1 + + + ADC12RST + ADC12RST + 5 + 1 + + + USBORST + USBORST + 8 + 1 + + + SDMMC3RST + SDMMC3RST + 16 + 1 + + + + + RCC_AHB2RSTCLRR + RCC_AHB2RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x99C + 0x20 + read-write + 0x00000000 + + + DMA1RST + DMA1RST + 0 + 1 + + + DMA2RST + DMA2RST + 1 + 1 + + + DMAMUXRST + DMAMUXRST + 2 + 1 + + + ADC12RST + ADC12RST + 5 + 1 + + + USBORST + USBORST + 8 + 1 + + + SDMMC3RST + SDMMC3RST + 16 + 1 + + + + + RCC_AHB3RSTSETR + RCC_AHB3RSTSETR + This register is used to activate the reset of the corresponding peripheral. + 0x9A0 + 0x20 + read-write + 0x00000000 + + + DCMIRST + DCMIRST + 0 + 1 + + + CRYP2RST + CRYP2RST + 4 + 1 + + + HASH2RST + HASH2RST + 5 + 1 + + + RNG2RST + RNG2RST + 6 + 1 + + + CRC2RST + CRC2RST + 7 + 1 + + + HSEMRST + HSEMRST + 11 + 1 + + + IPCCRST + IPCCRST + 12 + 1 + + + + + RCC_AHB3RSTCLRR + RCC_AHB3RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x9A4 + 0x20 + read-write + 0x00000000 + + + DCMIRST + DCMIRST + 0 + 1 + + + CRYP2RST + CRYP2RST + 4 + 1 + + + HASH2RST + HASH2RST + 5 + 1 + + + RNG2RST + RNG2RST + 6 + 1 + + + CRC2RST + CRC2RST + 7 + 1 + + + HSEMRST + HSEMRST + 11 + 1 + + + IPCCRST + IPCCRST + 12 + 1 + + + + + RCC_AHB4RSTSETR + RCC_AHB4RSTSETR + This register is used to activate the reset of the corresponding peripheral + 0x9A8 + 0x20 + read-write + 0x00000000 + + + GPIOARST + GPIOARST + 0 + 1 + + + GPIOBRST + GPIOBRST + 1 + 1 + + + GPIOCRST + GPIOCRST + 2 + 1 + + + GPIODRST + GPIODRST + 3 + 1 + + + GPIOERST + GPIOERST + 4 + 1 + + + GPIOFRST + GPIOFRST + 5 + 1 + + + GPIOGRST + GPIOGRST + 6 + 1 + + + GPIOHRST + GPIOHRST + 7 + 1 + + + GPIOIRST + GPIOIRST + 8 + 1 + + + GPIOJRST + GPIOJRST + 9 + 1 + + + GPIOKRST + GPIOKRST + 10 + 1 + + + + + RCC_AHB4RSTCLRR + RCC_AHB4RSTCLRR + This register is used to release the reset of the corresponding peripheral. + 0x9AC + 0x20 + read-write + 0x00000000 + + + GPIOARST + GPIOARST + 0 + 1 + + + GPIOBRST + GPIOBRST + 1 + 1 + + + GPIOCRST + GPIOCRST + 2 + 1 + + + GPIODRST + GPIODRST + 3 + 1 + + + GPIOERST + GPIOERST + 4 + 1 + + + GPIOFRST + GPIOFRST + 5 + 1 + + + GPIOGRST + GPIOGRST + 6 + 1 + + + GPIOHRST + GPIOHRST + 7 + 1 + + + GPIOIRST + GPIOIRST + 8 + 1 + + + GPIOJRST + GPIOJRST + 9 + 1 + + + GPIOKRST + GPIOKRST + 10 + 1 + + + + + RCC_MP_APB1ENSETR + RCC_MP_APB1ENSETR + This register is used to set the peripheral clock enable bit + 0xA00 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2EN + 0 + 1 + + + TIM3EN + TIM3EN + 1 + 1 + + + TIM4EN + TIM4EN + 2 + 1 + + + TIM5EN + TIM5EN + 3 + 1 + + + TIM6EN + TIM6EN + 4 + 1 + + + TIM7EN + TIM7EN + 5 + 1 + + + TIM12EN + TIM12EN + 6 + 1 + + + TIM13EN + TIM13EN + 7 + 1 + + + TIM14EN + TIM14EN + 8 + 1 + + + LPTIM1EN + LPTIM1EN + 9 + 1 + + + SPI2EN + SPI2EN + 11 + 1 + + + SPI3EN + SPI3EN + 12 + 1 + + + USART2EN + USART2EN + 14 + 1 + + + USART3EN + USART3EN + 15 + 1 + + + UART4EN + UART4EN + 16 + 1 + + + UART5EN + UART5EN + 17 + 1 + + + UART7EN + UART7EN + 18 + 1 + + + UART8EN + UART8EN + 19 + 1 + + + I2C1EN + I2C1EN + 21 + 1 + + + I2C2EN + I2C2EN + 22 + 1 + + + I2C3EN + I2C3EN + 23 + 1 + + + I2C5EN + I2C5EN + 24 + 1 + + + SPDIFEN + SPDIFEN + 26 + 1 + + + CECEN + CECEN + 27 + 1 + + + DAC12EN + DAC12EN + 29 + 1 + + + MDIOSEN + MDIOSEN + 31 + 1 + + + + + RCC_MP_APB1ENCLRR + RCC_MP_APB1ENCLRR + This register is used to clear the peripheral clock enable bit + 0xA04 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2EN + 0 + 1 + + + TIM3EN + TIM3EN + 1 + 1 + + + TIM4EN + TIM4EN + 2 + 1 + + + TIM5EN + TIM5EN + 3 + 1 + + + TIM6EN + TIM6EN + 4 + 1 + + + TIM7EN + TIM7EN + 5 + 1 + + + TIM12EN + TIM12EN + 6 + 1 + + + TIM13EN + TIM13EN + 7 + 1 + + + TIM14EN + TIM14EN + 8 + 1 + + + LPTIM1EN + LPTIM1EN + 9 + 1 + + + SPI2EN + SPI2EN + 11 + 1 + + + SPI3EN + SPI3EN + 12 + 1 + + + USART2EN + USART2EN + 14 + 1 + + + USART3EN + USART3EN + 15 + 1 + + + UART4EN + UART4EN + 16 + 1 + + + UART5EN + UART5EN + 17 + 1 + + + UART7EN + UART7EN + 18 + 1 + + + UART8EN + UART8EN + 19 + 1 + + + I2C1EN + I2C1EN + 21 + 1 + + + I2C2EN + I2C2EN + 22 + 1 + + + I2C3EN + I2C3EN + 23 + 1 + + + I2C5EN + I2C5EN + 24 + 1 + + + SPDIFEN + SPDIFEN + 26 + 1 + + + CECEN + CECEN + 27 + 1 + + + DAC12EN + DAC12EN + 29 + 1 + + + MDIOSEN + MDIOSEN + 31 + 1 + + + + + RCC_MP_APB2ENSETR + RCC_MP_APB2ENSETR + This register is used to set the peripheral clock enable bit + 0xA08 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1EN + 0 + 1 + + + TIM8EN + TIM8EN + 1 + 1 + + + TIM15EN + TIM15EN + 2 + 1 + + + TIM16EN + TIM16EN + 3 + 1 + + + TIM17EN + TIM17EN + 4 + 1 + + + SPI1EN + SPI1EN + 8 + 1 + + + SPI4EN + SPI4EN + 9 + 1 + + + SPI5EN + SPI5EN + 10 + 1 + + + USART6EN + USART6EN + 13 + 1 + + + SAI1EN + SAI1EN + 16 + 1 + + + SAI2EN + SAI2EN + 17 + 1 + + + SAI3EN + SAI3EN + 18 + 1 + + + DFSDMEN + DFSDMEN + 20 + 1 + + + ADFSDMEN + ADFSDMEN + 21 + 1 + + + FDCANEN + FDCANEN + 24 + 1 + + + + + RCC_MP_APB2ENCLRR + RCC_MP_APB2ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. + 0xA0C + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1EN + 0 + 1 + + + TIM8EN + TIM8EN + 1 + 1 + + + TIM15EN + TIM15EN + 2 + 1 + + + TIM16EN + TIM16EN + 3 + 1 + + + TIM17EN + TIM17EN + 4 + 1 + + + SPI1EN + SPI1EN + 8 + 1 + + + SPI4EN + SPI4EN + 9 + 1 + + + SPI5EN + SPI5EN + 10 + 1 + + + USART6EN + USART6EN + 13 + 1 + + + SAI1EN + SAI1EN + 16 + 1 + + + SAI2EN + SAI2EN + 17 + 1 + + + SAI3EN + SAI3EN + 18 + 1 + + + DFSDMEN + DFSDMEN + 20 + 1 + + + ADFSDMEN + ADFSDMEN + 21 + 1 + + + FDCANEN + FDCANEN + 24 + 1 + + + + + RCC_MP_APB3ENSETR + RCC_MP_APB3ENSETR + This register is used to set the peripheral clock enable bit + 0xA10 + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 0 + 1 + + + LPTIM3EN + LPTIM3EN + 1 + 1 + + + LPTIM4EN + LPTIM4EN + 2 + 1 + + + LPTIM5EN + LPTIM5EN + 3 + 1 + + + SAI4EN + SAI4EN + 8 + 1 + + + SYSCFGEN + SYSCFGEN + 11 + 1 + + + VREFEN + VREFEN + 13 + 1 + + + DTSEN + DTSEN + 16 + 1 + + + HDPEN + HDPEN + 20 + 1 + + + + + RCC_MP_APB3ENCLRR + RCC_MP_APB3ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. + 0xA14 + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 0 + 1 + + + LPTIM3EN + LPTIM3EN + 1 + 1 + + + LPTIM4EN + LPTIM4EN + 2 + 1 + + + LPTIM5EN + LPTIM5EN + 3 + 1 + + + SAI4EN + SAI4EN + 8 + 1 + + + SYSCFGEN + SYSCFGEN + 11 + 1 + + + VREFEN + VREFEN + 13 + 1 + + + DTSEN + DTSEN + 16 + 1 + + + HDPEN + HDPEN + 20 + 1 + + + + + RCC_MP_AHB2ENSETR + RCC_MP_AHB2ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral + 0xA18 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1EN + 0 + 1 + + + DMA2EN + DMA2EN + 1 + 1 + + + DMAMUXEN + DMAMUXEN + 2 + 1 + + + ADC12EN + ADC12EN + 5 + 1 + + + USBOEN + USBOEN + 8 + 1 + + + SDMMC3EN + SDMMC3EN + 16 + 1 + + + + + RCC_MP_AHB2ENCLRR + RCC_MP_AHB2ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. + 0xA1C + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1EN + 0 + 1 + + + DMA2EN + DMA2EN + 1 + 1 + + + DMAMUXEN + DMAMUXEN + 2 + 1 + + + ADC12EN + ADC12EN + 5 + 1 + + + USBOEN + USBOEN + 8 + 1 + + + SDMMC3EN + SDMMC3EN + 16 + 1 + + + + + RCC_MP_AHB3ENSETR + RCC_MP_AHB3ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral + 0xA20 + 0x20 + read-write + 0x00000000 + + + DCMIEN + DCMIEN + 0 + 1 + + + CRYP2EN + CRYP2EN + 4 + 1 + + + HASH2EN + HASH2EN + 5 + 1 + + + RNG2EN + RNG2EN + 6 + 1 + + + CRC2EN + CRC2EN + 7 + 1 + + + HSEMEN + HSEMEN + 11 + 1 + + + IPCCEN + IPCCEN + 12 + 1 + + + + + RCC_MP_AHB3ENCLRR + RCC_MP_AHB3ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. + 0xA24 + 0x20 + read-write + 0x00000000 + + + DCMIEN + DCMIEN + 0 + 1 + + + CRYP2EN + CRYP2EN + 4 + 1 + + + HASH2EN + HASH2EN + 5 + 1 + + + RNG2EN + RNG2EN + 6 + 1 + + + CRC2EN + CRC2EN + 7 + 1 + + + HSEMEN + HSEMEN + 11 + 1 + + + IPCCEN + IPCCEN + 12 + 1 + + + + + RCC_MP_AHB4ENSETR + RCC_MP_AHB4ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. + 0xA28 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + GPIOAEN + 0 + 1 + + + GPIOBEN + GPIOBEN + 1 + 1 + + + GPIOCEN + GPIOCEN + 2 + 1 + + + GPIODEN + GPIODEN + 3 + 1 + + + GPIOEEN + GPIOEEN + 4 + 1 + + + GPIOFEN + GPIOFEN + 5 + 1 + + + GPIOGEN + GPIOGEN + 6 + 1 + + + GPIOHEN + GPIOHEN + 7 + 1 + + + GPIOIEN + GPIOIEN + 8 + 1 + + + GPIOJEN + GPIOJEN + 9 + 1 + + + GPIOKEN + GPIOKEN + 10 + 1 + + + + + RCC_MP_AHB4ENCLRR + RCC_MP_AHB4ENCLRR + This register is used to clear the peripheral clock enable bit + 0xA2C + 0x20 + read-write + 0x00000000 + + + GPIOAEN + GPIOAEN + 0 + 1 + + + GPIOBEN + GPIOBEN + 1 + 1 + + + GPIOCEN + GPIOCEN + 2 + 1 + + + GPIODEN + GPIODEN + 3 + 1 + + + GPIOEEN + GPIOEEN + 4 + 1 + + + GPIOFEN + GPIOFEN + 5 + 1 + + + GPIOGEN + GPIOGEN + 6 + 1 + + + GPIOHEN + GPIOHEN + 7 + 1 + + + GPIOIEN + GPIOIEN + 8 + 1 + + + GPIOJEN + GPIOJEN + 9 + 1 + + + GPIOKEN + GPIOKEN + 10 + 1 + + + + + RCC_MP_MLAHBENSETR + RCC_MP_MLAHBENSETR + This register is used to set the peripheral clock enable bit + 0xA38 + 0x20 + read-write + 0x00000010 + + + RETRAMEN + RETRAMEN + 4 + 1 + + + + + RCC_MP_MLAHBENCLRR + RCC_MP_MLAHBENCLRR + This register is used to clear the peripheral clock enable bit. + 0xA3C + 0x20 + read-write + 0x00000010 + + + RETRAMEN + RETRAMEN + 4 + 1 + + + + + RCC_MC_APB1ENSETR + RCC_MC_APB1ENSETR + This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . + 0xA80 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2EN + 0 + 1 + + + TIM3EN + TIM3EN + 1 + 1 + + + TIM4EN + TIM4EN + 2 + 1 + + + TIM5EN + TIM5EN + 3 + 1 + + + TIM6EN + TIM6EN + 4 + 1 + + + TIM7EN + TIM7EN + 5 + 1 + + + TIM12EN + TIM12EN + 6 + 1 + + + TIM13EN + TIM13EN + 7 + 1 + + + TIM14EN + TIM14EN + 8 + 1 + + + LPTIM1EN + LPTIM1EN + 9 + 1 + + + SPI2EN + SPI2EN + 11 + 1 + + + SPI3EN + SPI3EN + 12 + 1 + + + USART2EN + USART2EN + 14 + 1 + + + USART3EN + USART3EN + 15 + 1 + + + UART4EN + UART4EN + 16 + 1 + + + UART5EN + UART5EN + 17 + 1 + + + UART7EN + UART7EN + 18 + 1 + + + UART8EN + UART8EN + 19 + 1 + + + I2C1EN + I2C1EN + 21 + 1 + + + I2C2EN + I2C2EN + 22 + 1 + + + I2C3EN + I2C3EN + 23 + 1 + + + I2C5EN + I2C5EN + 24 + 1 + + + SPDIFEN + SPDIFEN + 26 + 1 + + + CECEN + CECEN + 27 + 1 + + + WWDG1EN + WWDG1EN + 28 + 1 + + + DAC12EN + DAC12EN + 29 + 1 + + + MDIOSEN + MDIOSEN + 31 + 1 + + + + + RCC_MC_APB1ENCLRR + RCC_MC_APB1ENCLRR + This register is used to clear the peripheral clock enable bit of the corresponding peripheral. + 0xA84 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2EN + 0 + 1 + + + TIM3EN + TIM3EN + 1 + 1 + + + TIM4EN + TIM4EN + 2 + 1 + + + TIM5EN + TIM5EN + 3 + 1 + + + TIM6EN + TIM6EN + 4 + 1 + + + TIM7EN + TIM7EN + 5 + 1 + + + TIM12EN + TIM12EN + 6 + 1 + + + TIM13EN + TIM13EN + 7 + 1 + + + TIM14EN + TIM14EN + 8 + 1 + + + LPTIM1EN + LPTIM1EN + 9 + 1 + + + SPI2EN + SPI2EN + 11 + 1 + + + SPI3EN + SPI3EN + 12 + 1 + + + USART2EN + USART2EN + 14 + 1 + + + USART3EN + USART3EN + 15 + 1 + + + UART4EN + UART4EN + 16 + 1 + + + UART5EN + UART5EN + 17 + 1 + + + UART7EN + UART7EN + 18 + 1 + + + UART8EN + UART8EN + 19 + 1 + + + I2C1EN + I2C1EN + 21 + 1 + + + I2C2EN + I2C2EN + 22 + 1 + + + I2C3EN + I2C3EN + 23 + 1 + + + I2C5EN + I2C5EN + 24 + 1 + + + SPDIFEN + SPDIFEN + 26 + 1 + + + CECEN + CECEN + 27 + 1 + + + DAC12EN + DAC12EN + 29 + 1 + + + MDIOSEN + MDIOSEN + 31 + 1 + + + + + RCC_MC_APB2ENSETR + RCC_MC_APB2ENSETR + This register is used to set the peripheral clock enable bit + 0xA88 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1EN + 0 + 1 + + + TIM8EN + TIM8EN + 1 + 1 + + + TIM15EN + TIM15EN + 2 + 1 + + + TIM16EN + TIM16EN + 3 + 1 + + + TIM17EN + TIM17EN + 4 + 1 + + + SPI1EN + SPI1EN + 8 + 1 + + + SPI4EN + SPI4EN + 9 + 1 + + + SPI5EN + SPI5EN + 10 + 1 + + + USART6EN + USART6EN + 13 + 1 + + + SAI1EN + SAI1EN + 16 + 1 + + + SAI2EN + SAI2EN + 17 + 1 + + + SAI3EN + SAI3EN + 18 + 1 + + + DFSDMEN + DFSDMEN + 20 + 1 + + + ADFSDMEN + ADFSDMEN + 21 + 1 + + + FDCANEN + FDCANEN + 24 + 1 + + + + + RCC_MC_APB2ENCLRR + RCC_MC_APB2ENCLRR + This register is used to clear the peripheral clock enable bit + 0xA8C + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1EN + 0 + 1 + + + TIM8EN + TIM8EN + 1 + 1 + + + TIM15EN + TIM15EN + 2 + 1 + + + TIM16EN + TIM16EN + 3 + 1 + + + TIM17EN + TIM17EN + 4 + 1 + + + SPI1EN + SPI1EN + 8 + 1 + + + SPI4EN + SPI4EN + 9 + 1 + + + SPI5EN + SPI5EN + 10 + 1 + + + USART6EN + USART6EN + 13 + 1 + + + SAI1EN + SAI1EN + 16 + 1 + + + SAI2EN + SAI2EN + 17 + 1 + + + SAI3EN + SAI3EN + 18 + 1 + + + DFSDMEN + DFSDMEN + 20 + 1 + + + ADFSDMEN + ADFSDMEN + 21 + 1 + + + FDCANEN + FDCANEN + 24 + 1 + + + + + RCC_MC_APB3ENSETR + RCC_MC_APB3ENSETR + This register is used to set the peripheral clock enable bit + 0xA90 + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 0 + 1 + + + LPTIM3EN + LPTIM3EN + 1 + 1 + + + LPTIM4EN + LPTIM4EN + 2 + 1 + + + LPTIM5EN + LPTIM5EN + 3 + 1 + + + SAI4EN + SAI4EN + 8 + 1 + + + SYSCFGEN + SYSCFGEN + 11 + 1 + + + VREFEN + VREFEN + 13 + 1 + + + DTSEN + DTSEN + 16 + 1 + + + HDPEN + HDPEN + 20 + 1 + + + + + RCC_MC_APB3ENCLRR + RCC_MC_APB3ENCLRR + This register is used to clear the peripheral clock enable bit + 0xA94 + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 0 + 1 + + + LPTIM3EN + LPTIM3EN + 1 + 1 + + + LPTIM4EN + LPTIM4EN + 2 + 1 + + + LPTIM5EN + LPTIM5EN + 3 + 1 + + + SAI4EN + SAI4EN + 8 + 1 + + + SYSCFGEN + SYSCFGEN + 11 + 1 + + + VREFEN + VREFEN + 13 + 1 + + + DTSEN + DTSEN + 16 + 1 + + + HDPEN + HDPEN + 20 + 1 + + + + + RCC_MC_AHB2ENSETR + RCC_MC_AHB2ENSETR + This register is used to set the peripheral clock enable bit + 0xA98 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1EN + 0 + 1 + + + DMA2EN + DMA2EN + 1 + 1 + + + DMAMUXEN + DMAMUXEN + 2 + 1 + + + ADC12EN + ADC12EN + 5 + 1 + + + USBOEN + USBOEN + 8 + 1 + + + SDMMC3EN + SDMMC3EN + 16 + 1 + + + + + RCC_MC_AHB2ENCLRR + RCC_MC_AHB2ENCLRR + This register is used to clear the peripheral clock enable bit + 0xA9C + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA1EN + 0 + 1 + + + DMA2EN + DMA2EN + 1 + 1 + + + DMAMUXEN + DMAMUXEN + 2 + 1 + + + ADC12EN + ADC12EN + 5 + 1 + + + USBOEN + USBOEN + 8 + 1 + + + SDMMC3EN + SDMMC3EN + 16 + 1 + + + + + RCC_MC_AHB3ENSETR + RCC_MC_AHB3ENSETR + This register is used to set the peripheral clock enable bit + 0xAA0 + 0x20 + read-write + 0x00000000 + + + DCMIEN + DCMIEN + 0 + 1 + + + CRYP2EN + CRYP2EN + 4 + 1 + + + HASH2EN + HASH2EN + 5 + 1 + + + RNG2EN + RNG2EN + 6 + 1 + + + CRC2EN + CRC2EN + 7 + 1 + + + HSEMEN + HSEMEN + 11 + 1 + + + IPCCEN + IPCCEN + 12 + 1 + + + + + RCC_MC_AHB3ENCLRR + RCC_MC_AHB3ENCLRR + This register is used to clear the peripheral clock enable bit + 0xAA4 + 0x20 + read-write + 0x00000000 + + + DCMIEN + DCMIEN + 0 + 1 + + + CRYP2EN + CRYP2EN + 4 + 1 + + + HASH2EN + HASH2EN + 5 + 1 + + + RNG2EN + RNG2EN + 6 + 1 + + + CRC2EN + CRC2EN + 7 + 1 + + + HSEMEN + HSEMEN + 11 + 1 + + + IPCCEN + IPCCEN + 12 + 1 + + + + + RCC_MC_AHB4ENSETR + RCC_MC_AHB4ENSETR + This register is used to set the peripheral clock enable bit + 0xAA8 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + GPIOAEN + 0 + 1 + + + GPIOBEN + GPIOBEN + 1 + 1 + + + GPIOCEN + GPIOCEN + 2 + 1 + + + GPIODEN + GPIODEN + 3 + 1 + + + GPIOEEN + GPIOEEN + 4 + 1 + + + GPIOFEN + GPIOFEN + 5 + 1 + + + GPIOGEN + GPIOGEN + 6 + 1 + + + GPIOHEN + GPIOHEN + 7 + 1 + + + GPIOIEN + GPIOIEN + 8 + 1 + + + GPIOJEN + GPIOJEN + 9 + 1 + + + GPIOKEN + GPIOKEN + 10 + 1 + + + + + RCC_MC_AHB4ENCLRR + RCC_MC_AHB4ENCLRR + This register is used to clear the peripheral clock enable bit + 0xAAC + 0x20 + read-write + 0x00000000 + + + GPIOAEN + GPIOAEN + 0 + 1 + + + GPIOBEN + GPIOBEN + 1 + 1 + + + GPIOCEN + GPIOCEN + 2 + 1 + + + GPIODEN + GPIODEN + 3 + 1 + + + GPIOEEN + GPIOEEN + 4 + 1 + + + GPIOFEN + GPIOFEN + 5 + 1 + + + GPIOGEN + GPIOGEN + 6 + 1 + + + GPIOHEN + GPIOHEN + 7 + 1 + + + GPIOIEN + GPIOIEN + 8 + 1 + + + GPIOJEN + GPIOJEN + 9 + 1 + + + GPIOKEN + GPIOKEN + 10 + 1 + + + + + RCC_MC_AXIMENSETR + RCC_MC_AXIMENSETR + This register is used to set the peripheral clock enable bit + 0xAB0 + 0x20 + read-write + 0x00000000 + + + SYSRAMEN + SYSRAMEN + 0 + 1 + + + + + RCC_MC_AXIMENCLRR + RCC_MC_AXIMENCLRR + This register is used to clear the peripheral clock enable bit + 0xAB4 + 0x20 + read-write + 0x00000000 + + + SYSRAMEN + SYSRAMEN + 0 + 1 + + + + + RCC_MC_MLAHBENSETR + RCC_MC_MLAHBENSETR + This register is used to set the peripheral clock enable bit + 0xAB8 + 0x20 + read-write + 0x00000010 + + + RETRAMEN + RETRAMEN + 4 + 1 + + + + + RCC_MC_MLAHBENCLRR + RCC_MC_MLAHBENCLRR + This register is used to clear the peripheral clock enable bit + 0xABC + 0x20 + read-write + 0x00000010 + + + RETRAMEN + RETRAMEN + 4 + 1 + + + + + RCC_MP_APB1LPENSETR + RCC_MP_APB1LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB00 + 0x20 + read-write + 0xADEFDBFF + + + TIM2LPEN + TIM2LPEN + 0 + 1 + + + TIM3LPEN + TIM3LPEN + 1 + 1 + + + TIM4LPEN + TIM4LPEN + 2 + 1 + + + TIM5LPEN + TIM5LPEN + 3 + 1 + + + TIM6LPEN + TIM6LPEN + 4 + 1 + + + TIM7LPEN + TIM7LPEN + 5 + 1 + + + TIM12LPEN + TIM12LPEN + 6 + 1 + + + TIM13LPEN + TIM13LPEN + 7 + 1 + + + TIM14LPEN + TIM14LPEN + 8 + 1 + + + LPTIM1LPEN + LPTIM1LPEN + 9 + 1 + + + SPI2LPEN + SPI2LPEN + 11 + 1 + + + SPI3LPEN + SPI3LPEN + 12 + 1 + + + USART2LPEN + USART2LPEN + 14 + 1 + + + USART3LPEN + USART3LPEN + 15 + 1 + + + UART4LPEN + UART4LPEN + 16 + 1 + + + UART5LPEN + UART5LPEN + 17 + 1 + + + UART7LPEN + UART7LPEN + 18 + 1 + + + UART8LPEN + UART8LPEN + 19 + 1 + + + I2C1LPEN + I2C1LPEN + 21 + 1 + + + I2C2LPEN + I2C2LPEN + 22 + 1 + + + I2C3LPEN + I2C3LPEN + 23 + 1 + + + I2C5LPEN + I2C5LPEN + 24 + 1 + + + SPDIFLPEN + SPDIFLPEN + 26 + 1 + + + CECLPEN + CECLPEN + 27 + 1 + + + DAC12LPEN + DAC12LPEN + 29 + 1 + + + MDIOSLPEN + MDIOSLPEN + 31 + 1 + + + + + RCC_MP_APB1LPENCLRR + RCC_MP_APB1LPENCLRR + This register is used by the MPU in order to clear the PERxLPEN bits . + 0xB04 + 0x20 + read-write + 0xADEFDBFF + + + TIM2LPEN + TIM2LPEN + 0 + 1 + + + TIM3LPEN + TIM3LPEN + 1 + 1 + + + TIM4LPEN + TIM4LPEN + 2 + 1 + + + TIM5LPEN + TIM5LPEN + 3 + 1 + + + TIM6LPEN + TIM6LPEN + 4 + 1 + + + TIM7LPEN + TIM7LPEN + 5 + 1 + + + TIM12LPEN + TIM12LPEN + 6 + 1 + + + TIM13LPEN + TIM13LPEN + 7 + 1 + + + TIM14LPEN + TIM14LPEN + 8 + 1 + + + LPTIM1LPEN + LPTIM1LPEN + 9 + 1 + + + SPI2LPEN + SPI2LPEN + 11 + 1 + + + SPI3LPEN + SPI3LPEN + 12 + 1 + + + USART2LPEN + USART2LPEN + 14 + 1 + + + USART3LPEN + USART3LPEN + 15 + 1 + + + UART4LPEN + UART4LPEN + 16 + 1 + + + UART5LPEN + UART5LPEN + 17 + 1 + + + UART7LPEN + UART7LPEN + 18 + 1 + + + UART8LPEN + UART8LPEN + 19 + 1 + + + I2C1LPEN + I2C1LPEN + 21 + 1 + + + I2C2LPEN + I2C2LPEN + 22 + 1 + + + I2C3LPEN + I2C3LPEN + 23 + 1 + + + I2C5LPEN + I2C5LPEN + 24 + 1 + + + SPDIFLPEN + SPDIFLPEN + 26 + 1 + + + CECLPEN + CECLPEN + 27 + 1 + + + DAC12LPEN + DAC12LPEN + 29 + 1 + + + MDIOSLPEN + MDIOSLPEN + 31 + 1 + + + + + RCC_MP_APB2LPENSETR + RCC_MP_APB2LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB08 + 0x20 + read-write + 0x0137271F + + + TIM1LPEN + TIM1LPEN + 0 + 1 + + + TIM8LPEN + TIM8LPEN + 1 + 1 + + + TIM15LPEN + TIM15LPEN + 2 + 1 + + + TIM16LPEN + TIM16LPEN + 3 + 1 + + + TIM17LPEN + TIM17LPEN + 4 + 1 + + + SPI1LPEN + SPI1LPEN + 8 + 1 + + + SPI4LPEN + SPI4LPEN + 9 + 1 + + + SPI5LPEN + SPI5LPEN + 10 + 1 + + + USART6LPEN + USART6LPEN + 13 + 1 + + + SAI1LPEN + SAI1LPEN + 16 + 1 + + + SAI2LPEN + SAI2LPEN + 17 + 1 + + + SAI3LPEN + SAI3LPEN + 18 + 1 + + + DFSDMLPEN + DFSDMLPEN + 20 + 1 + + + ADFSDMLPEN + ADFSDMLPEN + 21 + 1 + + + FDCANLPEN + FDCANLPEN + 24 + 1 + + + + + RCC_MP_APB2LPENCLRR + RCC_MP_APB2LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB0C + 0x20 + read-write + 0x0137271F + + + TIM1LPEN + TIM1LPEN + 0 + 1 + + + TIM8LPEN + TIM8LPEN + 1 + 1 + + + TIM15LPEN + TIM15LPEN + 2 + 1 + + + TIM16LPEN + TIM16LPEN + 3 + 1 + + + TIM17LPEN + TIM17LPEN + 4 + 1 + + + SPI1LPEN + SPI1LPEN + 8 + 1 + + + SPI4LPEN + SPI4LPEN + 9 + 1 + + + SPI5LPEN + SPI5LPEN + 10 + 1 + + + USART6LPEN + USART6LPEN + 13 + 1 + + + SAI1LPEN + SAI1LPEN + 16 + 1 + + + SAI2LPEN + SAI2LPEN + 17 + 1 + + + SAI3LPEN + SAI3LPEN + 18 + 1 + + + DFSDMLPEN + DFSDMLPEN + 20 + 1 + + + ADFSDMLPEN + ADFSDMLPEN + 21 + 1 + + + FDCANLPEN + FDCANLPEN + 24 + 1 + + + + + RCC_MP_APB3LPENSETR + RCC_MP_APB3LPENSETR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB10 + 0x20 + read-write + 0x0003290F + + + LPTIM2LPEN + LPTIM2LPEN + 0 + 1 + + + LPTIM3LPEN + LPTIM3LPEN + 1 + 1 + + + LPTIM4LPEN + LPTIM4LPEN + 2 + 1 + + + LPTIM5LPEN + LPTIM5LPEN + 3 + 1 + + + SAI4LPEN + SAI4LPEN + 8 + 1 + + + SYSCFGLPEN + SYSCFGLPEN + 11 + 1 + + + VREFLPEN + VREFLPEN + 13 + 1 + + + DTSLPEN + DTSLPEN + 16 + 1 + + + + + RCC_MP_APB3LPENCLRR + RCC_MP_APB3LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB14 + 0x20 + read-write + 0x0003290F + + + LPTIM2LPEN + LPTIM2LPEN + 0 + 1 + + + LPTIM3LPEN + LPTIM3LPEN + 1 + 1 + + + LPTIM4LPEN + LPTIM4LPEN + 2 + 1 + + + LPTIM5LPEN + LPTIM5LPEN + 3 + 1 + + + SAI4LPEN + SAI4LPEN + 8 + 1 + + + SYSCFGLPEN + SYSCFGLPEN + 11 + 1 + + + VREFLPEN + VREFLPEN + 13 + 1 + + + DTSLPEN + DTSLPEN + 16 + 1 + + + + + RCC_MP_AHB2LPENSETR + RCC_MP_AHB2LPENSETR + This register is used by the MPU in order to set the PERxLPEN bit. + 0xB18 + 0x20 + read-write + 0x00010127 + + + DMA1LPEN + DMA1LPEN + 0 + 1 + + + DMA2LPEN + DMA2LPEN + 1 + 1 + + + DMAMUXLPEN + DMAMUXLPEN + 2 + 1 + + + ADC12LPEN + ADC12LPEN + 5 + 1 + + + USBOLPEN + USBOLPEN + 8 + 1 + + + SDMMC3LPEN + SDMMC3LPEN + 16 + 1 + + + + + RCC_MP_AHB2LPENCLRR + RCC_MP_AHB2LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB1C + 0x20 + read-write + 0x00010127 + + + DMA1LPEN + DMA1LPEN + 0 + 1 + + + DMA2LPEN + DMA2LPEN + 1 + 1 + + + DMAMUXLPEN + DMAMUXLPEN + 2 + 1 + + + ADC12LPEN + ADC12LPEN + 5 + 1 + + + USBOLPEN + USBOLPEN + 8 + 1 + + + SDMMC3LPEN + SDMMC3LPEN + 16 + 1 + + + + + RCC_MP_AHB3LPENSETR + RCC_MP_AHB3LPENSETR + This register is used by the MPU + 0xB20 + 0x20 + read-write + 0x000018F1 + + + DCMILPEN + DCMILPEN + 0 + 1 + + + CRYP2LPEN + CRYP2LPEN + 4 + 1 + + + HASH2LPEN + HASH2LPEN + 5 + 1 + + + RNG2LPEN + RNG2LPEN + 6 + 1 + + + CRC2LPEN + CRC2LPEN + 7 + 1 + + + HSEMLPEN + HSEMLPEN + 11 + 1 + + + IPCCLPEN + IPCCLPEN + 12 + 1 + + + + + RCC_MP_AHB3LPENCLRR + RCC_MP_AHB3LPENCLRR + This register is used by the MPU in order to clear the PERxLPEN bit + 0xB24 + 0x20 + read-write + 0x000018F1 + + + DCMILPEN + DCMILPEN + 0 + 1 + + + CRYP2LPEN + CRYP2LPEN + 4 + 1 + + + HASH2LPEN + HASH2LPEN + 5 + 1 + + + RNG2LPEN + RNG2LPEN + 6 + 1 + + + CRC2LPEN + CRC2LPEN + 7 + 1 + + + HSEMLPEN + HSEMLPEN + 11 + 1 + + + IPCCLPEN + IPCCLPEN + 12 + 1 + + + + + RCC_MP_AHB4LPENSETR + RCC_MP_AHB4LPENSETR + This register is used by the MPU + 0xB28 + 0x20 + read-write + 0x000007FF + + + GPIOALPEN + GPIOALPEN + 0 + 1 + + + GPIOBLPEN + GPIOBLPEN + 1 + 1 + + + GPIOCLPEN + GPIOCLPEN + 2 + 1 + + + GPIODLPEN + GPIODLPEN + 3 + 1 + + + GPIOELPEN + GPIOELPEN + 4 + 1 + + + GPIOFLPEN + GPIOFLPEN + 5 + 1 + + + GPIOGLPEN + GPIOGLPEN + 6 + 1 + + + GPIOHLPEN + GPIOHLPEN + 7 + 1 + + + GPIOILPEN + GPIOILPEN + 8 + 1 + + + GPIOJLPEN + GPIOJLPEN + 9 + 1 + + + GPIOKLPEN + GPIOKLPEN + 10 + 1 + + + + + RCC_MP_AHB4LPENCLRR + RCC_MP_AHB4LPENCLRR + This register is used by the MPU + 0xB2C + 0x20 + read-write + 0x000007FF + + + GPIOALPEN + GPIOALPEN + 0 + 1 + + + GPIOBLPEN + GPIOBLPEN + 1 + 1 + + + GPIOCLPEN + GPIOCLPEN + 2 + 1 + + + GPIODLPEN + GPIODLPEN + 3 + 1 + + + GPIOELPEN + GPIOELPEN + 4 + 1 + + + GPIOFLPEN + GPIOFLPEN + 5 + 1 + + + GPIOGLPEN + GPIOGLPEN + 6 + 1 + + + GPIOHLPEN + GPIOHLPEN + 7 + 1 + + + GPIOILPEN + GPIOILPEN + 8 + 1 + + + GPIOJLPEN + GPIOJLPEN + 9 + 1 + + + GPIOKLPEN + GPIOKLPEN + 10 + 1 + + + + + RCC_MP_AXIMLPENSETR + RCC_MP_AXIMLPENSETR + This register is used by the MPU + 0xB30 + 0x20 + read-write + 0x00000001 + + + SYSRAMLPEN + SYSRAMLPEN + 0 + 1 + + + + + RCC_MP_AXIMLPENCLRR + RCC_MP_AXIMLPENCLRR + This register is used by the MPU + 0xB34 + 0x20 + read-write + 0x00000001 + + + SYSRAMLPEN + SYSRAMLPEN + 0 + 1 + + + + + RCC_MP_MLAHBLPENSETR + RCC_MP_MLAHBLPENSETR + This register is used by the MPU in order to set the PERxLPEN bit + 0xB38 + 0x20 + read-write + 0x00000017 + + + SRAM1LPEN + SRAM1LPEN + 0 + 1 + + + SRAM2LPEN + SRAM2LPEN + 1 + 1 + + + SRAM34LPEN + SRAM34LPEN + 2 + 1 + + + RETRAMLPEN + RETRAMLPEN + 4 + 1 + + + + + RCC_MP_MLAHBLPENCLRR + RCC_MP_MLAHBLPENCLRR + This register is used by the MPU in order to clear the PERxLPEN bit + 0xB3C + 0x20 + read-write + 0x00000017 + + + SRAM1LPEN + SRAM1LPEN + 0 + 1 + + + SRAM2LPEN + SRAM2LPEN + 1 + 1 + + + SRAM34LPEN + SRAM34LPEN + 2 + 1 + + + RETRAMLPEN + RETRAMLPEN + 4 + 1 + + + + + RCC_MC_APB1LPENSETR + RCC_MC_APB1LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xB80 + 0x20 + read-write + 0xBDEFDBFF + + + TIM2LPEN + TIM2LPEN + 0 + 1 + + + TIM3LPEN + TIM3LPEN + 1 + 1 + + + TIM4LPEN + TIM4LPEN + 2 + 1 + + + TIM5LPEN + TIM5LPEN + 3 + 1 + + + TIM6LPEN + TIM6LPEN + 4 + 1 + + + TIM7LPEN + TIM7LPEN + 5 + 1 + + + TIM12LPEN + TIM12LPEN + 6 + 1 + + + TIM13LPEN + TIM13LPEN + 7 + 1 + + + TIM14LPEN + TIM14LPEN + 8 + 1 + + + LPTIM1LPEN + LPTIM1LPEN + 9 + 1 + + + SPI2LPEN + SPI2LPEN + 11 + 1 + + + SPI3LPEN + SPI3LPEN + 12 + 1 + + + USART2LPEN + USART2LPEN + 14 + 1 + + + USART3LPEN + USART3LPEN + 15 + 1 + + + UART4LPEN + UART4LPEN + 16 + 1 + + + UART5LPEN + UART5LPEN + 17 + 1 + + + UART7LPEN + UART7LPEN + 18 + 1 + + + UART8LPEN + UART8LPEN + 19 + 1 + + + I2C1LPEN + I2C1LPEN + 21 + 1 + + + I2C2LPEN + I2C2LPEN + 22 + 1 + + + I2C3LPEN + I2C3LPEN + 23 + 1 + + + I2C5LPEN + I2C5LPEN + 24 + 1 + + + SPDIFLPEN + SPDIFLPEN + 26 + 1 + + + CECLPEN + CECLPEN + 27 + 1 + + + WWDG1LPEN + WWDG1LPEN + 28 + 1 + + + DAC12LPEN + DAC12LPEN + 29 + 1 + + + MDIOSLPEN + MDIOSLPEN + 31 + 1 + + + + + RCC_MC_APB1LPENCLRR + RCC_MC_APB1LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bits + 0xB84 + 0x20 + read-write + 0xBDEFDBFF + + + TIM2LPEN + TIM2LPEN + 0 + 1 + + + TIM3LPEN + TIM3LPEN + 1 + 1 + + + TIM4LPEN + TIM4LPEN + 2 + 1 + + + TIM5LPEN + TIM5LPEN + 3 + 1 + + + TIM6LPEN + TIM6LPEN + 4 + 1 + + + TIM7LPEN + TIM7LPEN + 5 + 1 + + + TIM12LPEN + TIM12LPEN + 6 + 1 + + + TIM13LPEN + TIM13LPEN + 7 + 1 + + + TIM14LPEN + TIM14LPEN + 8 + 1 + + + LPTIM1LPEN + LPTIM1LPEN + 9 + 1 + + + SPI2LPEN + SPI2LPEN + 11 + 1 + + + SPI3LPEN + SPI3LPEN + 12 + 1 + + + USART2LPEN + USART2LPEN + 14 + 1 + + + USART3LPEN + USART3LPEN + 15 + 1 + + + UART4LPEN + UART4LPEN + 16 + 1 + + + UART5LPEN + UART5LPEN + 17 + 1 + + + UART7LPEN + UART7LPEN + 18 + 1 + + + UART8LPEN + UART8LPEN + 19 + 1 + + + I2C1LPEN + I2C1LPEN + 21 + 1 + + + I2C2LPEN + I2C2LPEN + 22 + 1 + + + I2C3LPEN + I2C3LPEN + 23 + 1 + + + I2C5LPEN + I2C5LPEN + 24 + 1 + + + SPDIFLPEN + SPDIFLPEN + 26 + 1 + + + CECLPEN + CECLPEN + 27 + 1 + + + WWDG1LPEN + WWDG1LPEN + 28 + 1 + + + DAC12LPEN + DAC12LPEN + 29 + 1 + + + MDIOSLPEN + MDIOSLPEN + 31 + 1 + + + + + RCC_MC_APB2LPENSETR + RCC_MC_APB2LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xB88 + 0x20 + read-write + 0x0137271F + + + TIM1LPEN + TIM1LPEN + 0 + 1 + + + TIM8LPEN + TIM8LPEN + 1 + 1 + + + TIM15LPEN + TIM15LPEN + 2 + 1 + + + TIM16LPEN + TIM16LPEN + 3 + 1 + + + TIM17LPEN + TIM17LPEN + 4 + 1 + + + SPI1LPEN + SPI1LPEN + 8 + 1 + + + SPI4LPEN + SPI4LPEN + 9 + 1 + + + SPI5LPEN + SPI5LPEN + 10 + 1 + + + USART6LPEN + USART6LPEN + 13 + 1 + + + SAI1LPEN + SAI1LPEN + 16 + 1 + + + SAI2LPEN + SAI2LPEN + 17 + 1 + + + SAI3LPEN + SAI3LPEN + 18 + 1 + + + DFSDMLPEN + DFSDMLPEN + 20 + 1 + + + ADFSDMLPEN + ADFSDMLPEN + 21 + 1 + + + FDCANLPEN + FDCANLPEN + 24 + 1 + + + + + RCC_MC_APB2LPENCLRR + RCC_MC_APB2LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0xB8C + 0x20 + read-write + 0x0137271F + + + TIM1LPEN + TIM1LPEN + 0 + 1 + + + TIM8LPEN + TIM8LPEN + 1 + 1 + + + TIM15LPEN + TIM15LPEN + 2 + 1 + + + TIM16LPEN + TIM16LPEN + 3 + 1 + + + TIM17LPEN + TIM17LPEN + 4 + 1 + + + SPI1LPEN + SPI1LPEN + 8 + 1 + + + SPI4LPEN + SPI4LPEN + 9 + 1 + + + SPI5LPEN + SPI5LPEN + 10 + 1 + + + USART6LPEN + USART6LPEN + 13 + 1 + + + SAI1LPEN + SAI1LPEN + 16 + 1 + + + SAI2LPEN + SAI2LPEN + 17 + 1 + + + SAI3LPEN + SAI3LPEN + 18 + 1 + + + DFSDMLPEN + DFSDMLPEN + 20 + 1 + + + ADFSDMLPEN + ADFSDMLPEN + 21 + 1 + + + FDCANLPEN + FDCANLPEN + 24 + 1 + + + + + RCC_MC_APB3LPENSETR + RCC_MC_APB3LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xB90 + 0x20 + read-write + 0x0003290F + + + LPTIM2LPEN + LPTIM2LPEN + 0 + 1 + + + LPTIM3LPEN + LPTIM3LPEN + 1 + 1 + + + LPTIM4LPEN + LPTIM4LPEN + 2 + 1 + + + LPTIM5LPEN + LPTIM5LPEN + 3 + 1 + + + SAI4LPEN + SAI4LPEN + 8 + 1 + + + SYSCFGLPEN + SYSCFGLPEN + 11 + 1 + + + VREFLPEN + VREFLPEN + 13 + 1 + + + DTSLPEN + DTSLPEN + 16 + 1 + + + + + RCC_MC_APB3LPENCLRR + RCC_MC_APB3LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0xB94 + 0x20 + read-write + 0x0003290F + + + LPTIM2LPEN + LPTIM2LPEN + 0 + 1 + + + LPTIM3LPEN + LPTIM3LPEN + 1 + 1 + + + LPTIM4LPEN + LPTIM4LPEN + 2 + 1 + + + LPTIM5LPEN + LPTIM5LPEN + 3 + 1 + + + SAI4LPEN + SAI4LPEN + 8 + 1 + + + SYSCFGLPEN + SYSCFGLPEN + 11 + 1 + + + VREFLPEN + VREFLPEN + 13 + 1 + + + DTSLPEN + DTSLPEN + 16 + 1 + + + + + RCC_MC_AHB2LPENSETR + RCC_MC_AHB2LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xB98 + 0x20 + read-write + 0x00010127 + + + DMA1LPEN + DMA1LPEN + 0 + 1 + + + DMA2LPEN + DMA2LPEN + 1 + 1 + + + DMAMUXLPEN + DMAMUXLPEN + 2 + 1 + + + ADC12LPEN + ADC12LPEN + 5 + 1 + + + USBOLPEN + USBOLPEN + 8 + 1 + + + SDMMC3LPEN + SDMMC3LPEN + 16 + 1 + + + + + RCC_MC_AHB2LPENCLRR + RCC_MC_AHB2LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0xB9C + 0x20 + read-write + 0x00010127 + + + DMA1LPEN + DMA1LPEN + 0 + 1 + + + DMA2LPEN + DMA2LPEN + 1 + 1 + + + DMAMUXLPEN + DMAMUXLPEN + 2 + 1 + + + ADC12LPEN + ADC12LPEN + 5 + 1 + + + USBOLPEN + USBOLPEN + 8 + 1 + + + SDMMC3LPEN + SDMMC3LPEN + 16 + 1 + + + + + RCC_MC_AHB3LPENSETR + RCC_MC_AHB3LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xBA0 + 0x20 + read-write + 0x000018F1 + + + DCMILPEN + DCMILPEN + 0 + 1 + + + CRYP2LPEN + CRYP2LPEN + 4 + 1 + + + HASH2LPEN + HASH2LPEN + 5 + 1 + + + RNG2LPEN + RNG2LPEN + 6 + 1 + + + CRC2LPEN + CRC2LPEN + 7 + 1 + + + HSEMLPEN + HSEMLPEN + 11 + 1 + + + IPCCLPEN + IPCCLPEN + 12 + 1 + + + + + RCC_MC_AHB3LPENCLRR + RCC_MC_AHB3LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit + 0xBA4 + 0x20 + read-write + 0x000018F1 + + + DCMILPEN + DCMILPEN + 0 + 1 + + + CRYP2LPEN + CRYP2LPEN + 4 + 1 + + + HASH2LPEN + HASH2LPEN + 5 + 1 + + + RNG2LPEN + RNG2LPEN + 6 + 1 + + + CRC2LPEN + CRC2LPEN + 7 + 1 + + + HSEMLPEN + HSEMLPEN + 11 + 1 + + + IPCCLPEN + IPCCLPEN + 12 + 1 + + + + + RCC_MC_AHB4LPENSETR + RCC_MC_AHB4LPENSETR + This register is used by the MCU in order to set the PERxLPEN bit. + 0xBA8 + 0x20 + read-write + 0x000007FF + + + GPIOALPEN + GPIOALPEN + 0 + 1 + + + GPIOBLPEN + GPIOBLPEN + 1 + 1 + + + GPIOCLPEN + GPIOCLPEN + 2 + 1 + + + GPIODLPEN + GPIODLPEN + 3 + 1 + + + GPIOELPEN + GPIOELPEN + 4 + 1 + + + GPIOFLPEN + GPIOFLPEN + 5 + 1 + + + GPIOGLPEN + GPIOGLPEN + 6 + 1 + + + GPIOHLPEN + GPIOHLPEN + 7 + 1 + + + GPIOILPEN + GPIOILPEN + 8 + 1 + + + GPIOJLPEN + GPIOJLPEN + 9 + 1 + + + GPIOKLPEN + GPIOKLPEN + 10 + 1 + + + + + RCC_MC_AHB4LPENCLRR + RCC_MC_AHB4LPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. + 0xBAC + 0x20 + read-write + 0x000007FF + + + GPIOALPEN + GPIOALPEN + 0 + 1 + + + GPIOBLPEN + GPIOBLPEN + 1 + 1 + + + GPIOCLPEN + GPIOCLPEN + 2 + 1 + + + GPIODLPEN + GPIODLPEN + 3 + 1 + + + GPIOELPEN + GPIOELPEN + 4 + 1 + + + GPIOFLPEN + GPIOFLPEN + 5 + 1 + + + GPIOGLPEN + GPIOGLPEN + 6 + 1 + + + GPIOHLPEN + GPIOHLPEN + 7 + 1 + + + GPIOILPEN + GPIOILPEN + 8 + 1 + + + GPIOJLPEN + GPIOJLPEN + 9 + 1 + + + GPIOKLPEN + GPIOKLPEN + 10 + 1 + + + + + RCC_MC_AXIMLPENSETR + RCC_MC_AXIMLPENSETR + This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. + 0xBB0 + 0x20 + read-write + 0x00000001 + + + SYSRAMLPEN + SYSRAMLPEN + 0 + 1 + + + + + RCC_MC_AXIMLPENCLRR + RCC_MC_AXIMLPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. + 0xBB4 + 0x20 + read-write + 0x00000001 + + + SYSRAMLPEN + SYSRAMLPEN + 0 + 1 + + + + + RCC_MC_MLAHBLPENSETR + RCC_MC_MLAHBLPENSETR + This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. + 0xBB8 + 0x20 + read-write + 0x00000017 + + + SRAM1LPEN + SRAM1LPEN + 0 + 1 + + + SRAM2LPEN + SRAM2LPEN + 1 + 1 + + + SRAM34LPEN + SRAM34LPEN + 2 + 1 + + + RETRAMLPEN + RETRAMLPEN + 4 + 1 + + + + + RCC_MC_MLAHBLPENCLRR + RCC_MC_MLAHBLPENCLRR + This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. + 0xBBC + 0x20 + read-write + 0x00000017 + + + SRAM1LPEN + SRAM1LPEN + 0 + 1 + + + SRAM2LPEN + SRAM2LPEN + 1 + 1 + + + SRAM34LPEN + SRAM34LPEN + 2 + 1 + + + RETRAMLPEN + RETRAMLPEN + 4 + 1 + + + + + RCC_MC_RSTSCLRR + RCC_MC_RSTSCLRR + This register is used by the MCU to check the reset source. + 0xC00 + 0x20 + read-write + 0x00000015 + + + PORRSTF + PORRSTF + 0 + 1 + + + BORRSTF + BORRSTF + 1 + 1 + + + PADRSTF + PADRSTF + 2 + 1 + + + HCSSRSTF + HCSSRSTF + 3 + 1 + + + VCORERSTF + VCORERSTF + 4 + 1 + + + MCURSTF + MCURSTF + 5 + 1 + + + MPSYSRSTF + MPSYSRSTF + 6 + 1 + + + MCSYSRSTF + MCSYSRSTF + 7 + 1 + + + IWDG1RSTF + IWDG1RSTF + 8 + 1 + + + IWDG2RSTF + IWDG2RSTF + 9 + 1 + + + WWDG1RSTF + WWDG1RSTF + 10 + 1 + + + + + RCC_MC_CIER + RCC_MC_CIER + This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. + 0xC14 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSIRDYIE + 0 + 1 + + + LSERDYIE + LSERDYIE + 1 + 1 + + + HSIRDYIE + HSIRDYIE + 2 + 1 + + + HSERDYIE + HSERDYIE + 3 + 1 + + + CSIRDYIE + CSIRDYIE + 4 + 1 + + + PLL1DYIE + PLL1DYIE + 8 + 1 + + + PLL2DYIE + PLL2DYIE + 9 + 1 + + + PLL3DYIE + PLL3DYIE + 10 + 1 + + + PLL4DYIE + PLL4DYIE + 11 + 1 + + + LSECSSIE + LSECSSIE + 16 + 1 + + + WKUPIE + WKUPIE + 20 + 1 + + + + + RCC_MC_CIFR + RCC_MC_CIFR + This register shall be used by the MCU in order to read and clear the interrupt flags. + 0xC18 + 0x20 + read-write + 0x00000000 + + + LSIRDYF + LSIRDYF + 0 + 1 + + + LSERDYF + LSERDYF + 1 + 1 + + + HSIRDYF + HSIRDYF + 2 + 1 + + + HSERDYF + HSERDYF + 3 + 1 + + + CSIRDYF + CSIRDYF + 4 + 1 + + + PLL1DYF + PLL1DYF + 8 + 1 + + + PLL2DYF + PLL2DYF + 9 + 1 + + + PLL3DYF + PLL3DYF + 10 + 1 + + + PLL4DYF + PLL4DYF + 11 + 1 + + + LSECSSF + LSECSSF + 16 + 1 + + + WKUPF + WKUPF + 20 + 1 + + + + + RCC_VERR + RCC_VERR + This register gives the IP version + 0xFF4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + RCC_IDR + RCC_IDR + This register gives the unique identifier of the RCC + 0xFF8 + 0x20 + read-only + 0x00000001 + + + ID + ID + 0 + 32 + + + + + RCC_SIDR + RCC_SIDR + This register gives the decoding space, which is for the RCC of 4 kB. + 0xFFC + 0x20 + read-only + 0xA3C5DD04 + + + SID + SID + 0 + 32 + + + + + + + IPCC + IPCC + IPCC + 0x4C001000 + + 0x0 + 0x400 + registers + + + + IPCC_C1CR + IPCC_C1CR + IPCC Processor 1 control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXOIE + RXOIE + 0 + 1 + + + TXFIE + TXFIE + 16 + 1 + + + + + IPCC_C1MR + IPCC_C1MR + IPCC Processor 1 mask register + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + CHxOM + CHxOM + 0 + 6 + + + CHxFM + CHxFM + 16 + 6 + + + + + IPCC_C1SCR + IPCC_C1SCR + Reading this register will always return 0x0000 0000. + 0x8 + 0x20 + read-write + 0x00000000 + + + CHxC + CHxC + 0 + 6 + + + CHxS + CHxS + 16 + 6 + + + + + IPCC_C1TOC2SR + IPCC_C1TOC2SR + IPCC processor 1 to processor 2 status register + 0xC + 0x20 + read-only + 0x00000000 + + + CHxF + CHxF + 0 + 6 + + + + + IPCC_C2CR + IPCC_C2CR + IPCC Processor 2 control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXOIE + RXOIE + 0 + 1 + + + TXFIE + TXFIE + 16 + 1 + + + + + IPCC_C2MR + IPCC_C2MR + IPCC Processor 2 mask register + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + CHxOM + CHxOM + 0 + 6 + + + CHxFM + CHxFM + 16 + 6 + + + + + IPCC_C2SCR + IPCC_C2SCR + Reading this register will always return 0x0000 0000. + 0x18 + 0x20 + read-write + 0x00000000 + + + CHxC + CHxC + 0 + 6 + + + CHxS + CHxS + 16 + 6 + + + + + IPCC_C2TOC1SR + IPCC_C2TOC1SR + IPCC processor 2 to processor 1 status register + 0x1C + 0x20 + read-only + 0x00000000 + + + CHxF + CHxF + 0 + 6 + + + + + IPCC_HWCFGR + IPCC_HWCFGR + IPCC Hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000002 + + + CHANNELS + CHANNELS + 0 + 8 + + + + + IPCC_VER + IPCC_VER + IPCC IP Version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MINREV + MINREV + 0 + 4 + + + MAJREV + MAJREV + 4 + 4 + + + + + IPCC_ID + IPCC_ID + IPCC IP Identification register + 0x3F8 + 0x20 + read-only + 0x00100071 + + + IPID + IPID + 0 + 32 + + + + + IPCC_SID + IPCC_SID + IPCC Size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + + + + + + + OTGHSFS1 + OTGHSFS1 + OTGHSFS1 + 0x49000000 + + 0x0 + 0x1000 + registers + + + + OTG_GOTGCTL + OTG_GOTGCTL + The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. + 0x0 + 0x20 + 0x00010000 + + + SRQSCS + SRQSCS + 0 + 1 + read-only + + + SRQ + SRQ + 1 + 1 + read-write + + + VBVALOEN + VBVALOEN + 2 + 1 + read-write + + + VBVALOVAL + VBVALOVAL + 3 + 1 + read-write + + + AVALOEN + AVALOEN + 4 + 1 + read-write + + + AVALOVAL + AVALOVAL + 5 + 1 + read-write + + + BVALOEN + BVALOEN + 6 + 1 + read-write + + + BVALOVAL + BVALOVAL + 7 + 1 + read-write + + + HNGSCS + HNGSCS + 8 + 1 + read-only + + + HNPRQ + HNPRQ + 9 + 1 + read-write + + + HSHNPEN + HSHNPEN + 10 + 1 + read-write + + + DHNPEN + DHNPEN + 11 + 1 + read-write + + + EHEN + EHEN + 12 + 1 + read-write + + + CIDSTS + CIDSTS + 16 + 1 + read-only + + + DBCT + DBCT + 17 + 1 + read-only + + + ASVLD + ASVLD + 18 + 1 + read-only + + + BSVLD + BSVLD + 19 + 1 + read-only + + + OTGVER + OTGVER + 20 + 1 + read-write + + + CURMOD + CURMOD + 21 + 1 + read-only + + + + + OTG_GOTGINT + OTG_GOTGINT + The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + SEDET + 2 + 1 + + + SRSSCHG + SRSSCHG + 8 + 1 + + + HNSSCHG + HNSSCHG + 9 + 1 + + + HNGDET + HNGDET + 17 + 1 + + + ADTOCHG + ADTOCHG + 18 + 1 + + + DBCDNE + DBCDNE + 19 + 1 + + + IDCHNG + IDCHNG + 20 + 1 + + + + + OTG_GAHBCFG + OTG_GAHBCFG + This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. + 0x8 + 0x20 + read-write + 0x00000000 + + + GINTMSK + GINTMSK + 0 + 1 + + + HBSTLEN + HBSTLEN + 1 + 4 + + + DMAEN + DMAEN + 5 + 1 + + + TXFELVL + TXFELVL + 7 + 1 + + + PTXFELVL + PTXFELVL + 8 + 1 + + + + + OTG_GUSBCFG + OTG_GUSBCFG + This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. + 0xC + 0x20 + read-write + 0x00001400 + + + TOCAL + TOCAL + 0 + 3 + + + PHYSEL + PHYSEL + 6 + 1 + + + SRPCAP + SRPCAP + 8 + 1 + + + HNPCAP + HNPCAP + 9 + 1 + + + TRDT + TRDT + 10 + 4 + + + PHYLPC + PHYLPC + 15 + 1 + + + TSDPS + TSDPS + 22 + 1 + + + FHMOD + FHMOD + 29 + 1 + + + FDMOD + FDMOD + 30 + 1 + + + + + OTG_GRSTCTL + OTG_GRSTCTL + The application uses this register to reset various hardware features inside the core. + 0x10 + 0x20 + 0x80000000 + + + CSRST + CSRST + 0 + 1 + read-write + + + PSRST + PSRST + 1 + 1 + read-write + + + RXFFLSH + RXFFLSH + 4 + 1 + read-write + + + TXFFLSH + TXFFLSH + 5 + 1 + read-write + + + TXFNUM + TXFNUM + 6 + 5 + read-write + + + DMAREQ + DMAREQ + 30 + 1 + read-only + + + AHBIDL + AHBIDL + 31 + 1 + read-only + + + + + OTG_GINTSTS + OTG_GINTSTS + This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. + 0x14 + 0x20 + 0x14000020 + + + CMOD + CMOD + 0 + 1 + read-only + + + MMIS + MMIS + 1 + 1 + read-write + + + OTGINT + OTGINT + 2 + 1 + read-only + + + SOF + SOF + 3 + 1 + read-write + + + RXFLVL + RXFLVL + 4 + 1 + read-only + + + NPTXFE + NPTXFE + 5 + 1 + read-only + + + GINAKEFF + GINAKEFF + 6 + 1 + read-only + + + GONAKEFF + GONAKEFF + 7 + 1 + read-only + + + ESUSP + ESUSP + 10 + 1 + read-write + + + USBSUSP + USBSUSP + 11 + 1 + read-write + + + USBRST + USBRST + 12 + 1 + read-write + + + ENUMDNE + ENUMDNE + 13 + 1 + read-write + + + ISOODRP + ISOODRP + 14 + 1 + read-write + + + EOPF + EOPF + 15 + 1 + read-write + + + IEPINT + IEPINT + 18 + 1 + read-only + + + OEPINT + OEPINT + 19 + 1 + read-only + + + IISOIXFR + IISOIXFR + 20 + 1 + read-write + + + IPXFR + IPXFR + 21 + 1 + read-write + + + DATAFSUSP + DATAFSUSP + 22 + 1 + read-write + + + HPRTINT + HPRTINT + 24 + 1 + read-only + + + HCINT + HCINT + 25 + 1 + read-only + + + PTXFE + PTXFE + 26 + 1 + read-only + + + CIDSCHG + CIDSCHG + 28 + 1 + read-write + + + DISCINT + DISCINT + 29 + 1 + read-write + + + SRQINT + SRQINT + 30 + 1 + read-write + + + WKUPINT + WKUPINT + 31 + 1 + read-write + + + + + OTG_GINTMSK + OTG_GINTMSK + This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. + 0x18 + 0x20 + 0x00000000 + + + MMISM + MMISM + 1 + 1 + read-write + + + OTGINT + OTGINT + 2 + 1 + read-write + + + SOFM + SOFM + 3 + 1 + read-write + + + RXFLVLM + RXFLVLM + 4 + 1 + read-write + + + NPTXFEM + NPTXFEM + 5 + 1 + read-write + + + GINAKEFFM + GINAKEFFM + 6 + 1 + read-write + + + GONAKEFFM + GONAKEFFM + 7 + 1 + read-write + + + ESUSPM + ESUSPM + 10 + 1 + read-write + + + USBSUSPM + USBSUSPM + 11 + 1 + read-write + + + USBRST + USBRST + 12 + 1 + read-write + + + ENUMDNEM + ENUMDNEM + 13 + 1 + read-write + + + ISOODRPM + ISOODRPM + 14 + 1 + read-write + + + EOPFM + EOPFM + 15 + 1 + read-write + + + IEPINT + IEPINT + 18 + 1 + read-write + + + OEPINT + OEPINT + 19 + 1 + read-write + + + IISOIXFRM + IISOIXFRM + 20 + 1 + read-write + + + IPXFRM + IPXFRM + 21 + 1 + read-write + + + FSUSPM + FSUSPM + 22 + 1 + read-write + + + RSTDETM + RSTDETM + 23 + 1 + read-write + + + PRTIM + PRTIM + 24 + 1 + read-only + + + HCIM + HCIM + 25 + 1 + read-write + + + PTXFEM + PTXFEM + 26 + 1 + read-write + + + LPMINTM + LPMINTM + 27 + 1 + read-write + + + CIDSCHGM + CIDSCHGM + 28 + 1 + read-write + + + DISCINT + DISCINT + 29 + 1 + read-write + + + SRQIM + SRQIM + 30 + 1 + read-write + + + WUIM + WUIM + 31 + 1 + read-write + + + + + OTG_GRXSTSR + OTG_GRXSTSR + This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + EPNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + FRMNUM + FRMNUM + 21 + 4 + + + STSPHST + STSPHST + 27 + 1 + + + + + OTG_GRXSTSP + OTG_GRXSTSP + This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + EPNUM + 0 + 4 + + + BCNT + BCNT + 4 + 11 + + + DPID + DPID + 15 + 2 + + + PKTSTS + PKTSTS + 17 + 4 + + + FRMNUM + FRMNUM + 21 + 4 + + + STSPHST + STSPHST + 27 + 1 + + + + + OTG_GRXFSIZ + OTG_GRXFSIZ + The application can program the RAM size that must be allocated to the Rx FIFO. + 0x24 + 0x20 + read-write + 0x00000400 + + + RXFD + RXFD + 0 + 16 + + + + + OTG_HNPTXFSIZ + OTG_HNPTXFSIZ + Host mode + 0x28 + 0x20 + read-write + 0x02000200 + + + NPTXFSA + NPTXFSA + 0 + 16 + + + NPTXFD + NPTXFD + 16 + 16 + + + + + OTG_HNPTXSTS + OTG_HNPTXSTS + In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. + 0x2C + 0x20 + read-only + 0x00080400 + + + NPTXFSAV + NPTXFSAV + 0 + 16 + + + NPTQXSAV + NPTQXSAV + 16 + 8 + + + NPTXQTOP + NPTXQTOP + 24 + 7 + + + + + OTG_GCCFG + OTG_GCCFG + OTG general core configuration register + 0x38 + 0x20 + 0x00000000 + + + PDET + PDET + 1 + 1 + read-only + + + SDET + SDET + 2 + 1 + read-only + + + PS2DET + PS2DET + 3 + 1 + read-only + + + PWRDWN + PWRDWN + 16 + 1 + read-write + + + BCDEN + BCDEN + 17 + 1 + read-write + + + PDEN + PDEN + 19 + 1 + read-write + + + SDEN + SDEN + 20 + 1 + read-write + + + VBDEN + VBDEN + 21 + 1 + read-write + + + IDEN + IDEN + 22 + 1 + read-write + + + + + OTG_CID + OTG_CID + This is a register containing the Product ID as reset value. + 0x3C + 0x20 + read-write + 0x00004000 + + + PRODUCT_ID + PRODUCT_ID + 0 + 32 + + + + + OTG_GLPMCFG + OTG_GLPMCFG + OTG core LPM configuration register + 0x54 + 0x20 + 0x00000000 + + + LPMEN + LPMEN + 0 + 1 + read-write + + + LPMACK + LPMACK + 1 + 1 + read-write + + + BESL + BESL + 2 + 4 + read-write + + + REMWAKE + REMWAKE + 6 + 1 + read-write + + + L1SSEN + L1SSEN + 7 + 1 + read-write + + + BESLTHRS + BESLTHRS + 8 + 4 + read-write + + + L1DSEN + L1DSEN + 12 + 1 + read-write + + + LPMRSP + LPMRSP + 13 + 2 + read-only + + + SLPSTS + SLPSTS + 15 + 1 + read-only + + + L1RSMOK + L1RSMOK + 16 + 1 + read-only + + + LPMCHIDX + LPMCHIDX + 17 + 4 + read-write + + + LPMRCNT + LPMRCNT + 21 + 3 + read-write + + + SNDLPM + SNDLPM + 24 + 1 + read-write + + + LPMRCNTSTS + LPMRCNTSTS + 25 + 3 + read-only + + + ENBESL + ENBESL + 28 + 1 + read-write + + + + + OTG_HPTXFSIZ + OTG_HPTXFSIZ + OTG host periodic transmit FIFO size register + 0x100 + 0x20 + read-write + 0x02000400 + + + PTXSA + PTXSA + 0 + 16 + + + PTXFSIZ + PTXFSIZ + 16 + 16 + + + + + OTG_DIEPTXF1 + OTG_DIEPTXF1 + OTG device IN endpoint transmit FIFO 1 size register + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF2 + OTG_DIEPTXF2 + OTG device IN endpoint transmit FIFO 2 size register + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF3 + OTG_DIEPTXF3 + OTG device IN endpoint transmit FIFO 3 size register + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF4 + OTG_DIEPTXF4 + OTG device IN endpoint transmit FIFO 4 size register + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF5 + OTG_DIEPTXF5 + OTG device IN endpoint transmit FIFO 5 size register + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF6 + OTG_DIEPTXF6 + OTG device IN endpoint transmit FIFO 6 size register + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF7 + OTG_DIEPTXF7 + OTG device IN endpoint transmit FIFO 7 size register + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_DIEPTXF8 + OTG_DIEPTXF8 + OTG device IN endpoint transmit FIFO 8 size register + 0x120 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + INEPTXSA + 0 + 16 + + + INEPTXFD + INEPTXFD + 16 + 16 + + + + + OTG_HCFG + OTG_HCFG + This register configures the core after power-on. Do not make changes to this register after initializing the host. + 0x400 + 0x20 + 0x00000000 + + + FSLSPCS + FSLSPCS + 0 + 2 + read-write + + + FSLSS + FSLSS + 2 + 1 + read-only + + + DESCDMA + DESCDMA + 23 + 1 + read-write + + + FRLSTEN + FRLSTEN + 24 + 2 + read-write + + + PERSSCHEDENA + PERSSCHEDENA + 26 + 1 + read-write + + + + + OTG_HFIR + OTG_HFIR + This register stores the frame interval information for the current speed to which the OTG controller has enumerated. + 0x404 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + FRIVL + 0 + 16 + + + RLDCTRL + RLDCTRL + 16 + 1 + + + + + OTG_HFNUM + OTG_HFNUM + This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. + 0x408 + 0x20 + read-only + 0x00003FFF + + + FRNUM + FRNUM + 0 + 16 + + + FTREM + FTREM + 16 + 16 + + + + + OTG_HPTXSTS + OTG_HPTXSTS + This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. + 0x410 + 0x20 + read-only + 0x00080100 + + + PTXFSAVL + PTXFSAVL + 0 + 16 + + + PTXQSAV + PTXQSAV + 16 + 8 + + + PTXQTOP + PTXQTOP + 24 + 8 + + + + + OTG_HAINT + OTG_HAINT + When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. + 0x414 + 0x20 + read-only + 0x00000000 + + + HAINT + HAINT + 0 + 16 + + + + + OTG_HAINTMSK + OTG_HAINTMSK + The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. + 0x418 + 0x20 + read-write + 0x00000000 + + + HAINTM + HAINTM + 0 + 16 + + + + + OTG_HFLBADDR + OTG_HFLBADDR + This register holds the starting address of the frame list information (scatter/gather mode). + 0x41C + 0x20 + read-write + 0x00000000 + + + HFLBADDR + HFLBADDR + 0 + 32 + + + + + OTG_HPRT + OTG_HPRT + This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. + 0x440 + 0x20 + 0x00000000 + + + PCSTS + PCSTS + 0 + 1 + read-only + + + PCDET + PCDET + 1 + 1 + read-write + + + PENA + PENA + 2 + 1 + read-write + + + PENCHNG + PENCHNG + 3 + 1 + read-write + + + POCA + POCA + 4 + 1 + read-only + + + POCCHNG + POCCHNG + 5 + 1 + read-write + + + PRES + PRES + 6 + 1 + read-write + + + PSUSP + PSUSP + 7 + 1 + read-write + + + PRST + PRST + 8 + 1 + read-write + + + PLSTS + PLSTS + 10 + 2 + read-only + + + PPWR + PPWR + 12 + 1 + read-write + + + PTCTL + PTCTL + 13 + 4 + read-write + + + PSPD + PSPD + 17 + 2 + read-only + + + + + OTG_HCCHAR0 + OTG_HCCHAR0 + OTG host channel 0 characteristics register + 0x500 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT0 + OTG_HCSPLT0 + OTG host channel 0 split control register + 0x504 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT0 + OTG_HCINT0 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x508 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK0 + OTG_HCINTMSK0 + This register reflects the mask for each channel status described in the previous section. + 0x50C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ0 + OTG_HCTSIZ0 + OTG host channel 0 transfer size register + 0x510 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA0 + OTG_HCDMA0 + OTG host channel 0 DMA address register in buffer DMA [alternate] + 0x514 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB0 + OTG_HCDMAB0 + OTG host channel-n DMA address buffer register + 0x51C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR1 + OTG_HCCHAR1 + OTG host channel 1 characteristics register + 0x520 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT1 + OTG_HCSPLT1 + OTG host channel 1 split control register + 0x524 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT1 + OTG_HCINT1 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x528 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK1 + OTG_HCINTMSK1 + This register reflects the mask for each channel status described in the previous section. + 0x52C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ1 + OTG_HCTSIZ1 + OTG host channel 1 transfer size register + 0x530 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA1 + OTG_HCDMA1 + OTG host channel 1 DMA address register in buffer DMA [alternate] + 0x534 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB1 + OTG_HCDMAB1 + OTG host channel-n DMA address buffer register + 0x53C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR2 + OTG_HCCHAR2 + OTG host channel 2 characteristics register + 0x540 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT2 + OTG_HCSPLT2 + OTG host channel 2 split control register + 0x544 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT2 + OTG_HCINT2 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x548 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK2 + OTG_HCINTMSK2 + This register reflects the mask for each channel status described in the previous section. + 0x54C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ2 + OTG_HCTSIZ2 + OTG host channel 2 transfer size register + 0x550 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA2 + OTG_HCDMA2 + OTG host channel 2 DMA address register in buffer DMA [alternate] + 0x554 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB2 + OTG_HCDMAB2 + OTG host channel-n DMA address buffer register + 0x55C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR3 + OTG_HCCHAR3 + OTG host channel 3 characteristics register + 0x560 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT3 + OTG_HCSPLT3 + OTG host channel 3 split control register + 0x564 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT3 + OTG_HCINT3 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x568 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK3 + OTG_HCINTMSK3 + This register reflects the mask for each channel status described in the previous section. + 0x56C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ3 + OTG_HCTSIZ3 + OTG host channel 3 transfer size register + 0x570 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA3 + OTG_HCDMA3 + OTG host channel 3 DMA address register in buffer DMA [alternate] + 0x574 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB3 + OTG_HCDMAB3 + OTG host channel-n DMA address buffer register + 0x57C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR4 + OTG_HCCHAR4 + OTG host channel 4 characteristics register + 0x580 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT4 + OTG_HCSPLT4 + OTG host channel 4 split control register + 0x584 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT4 + OTG_HCINT4 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x588 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK4 + OTG_HCINTMSK4 + This register reflects the mask for each channel status described in the previous section. + 0x58C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ4 + OTG_HCTSIZ4 + OTG host channel 4 transfer size register + 0x590 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA4 + OTG_HCDMA4 + OTG host channel 4 DMA address register in buffer DMA [alternate] + 0x594 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB4 + OTG_HCDMAB4 + OTG host channel-n DMA address buffer register + 0x59C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR5 + OTG_HCCHAR5 + OTG host channel 5 characteristics register + 0x5A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT5 + OTG_HCSPLT5 + OTG host channel 5 split control register + 0x5A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT5 + OTG_HCINT5 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x5A8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK5 + OTG_HCINTMSK5 + This register reflects the mask for each channel status described in the previous section. + 0x5AC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ5 + OTG_HCTSIZ5 + OTG host channel 5 transfer size register + 0x5B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA5 + OTG_HCDMA5 + OTG host channel 5 DMA address register in buffer DMA [alternate] + 0x5B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB5 + OTG_HCDMAB5 + OTG host channel-n DMA address buffer register + 0x5BC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR6 + OTG_HCCHAR6 + OTG host channel 6 characteristics register + 0x5C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT6 + OTG_HCSPLT6 + OTG host channel 6 split control register + 0x5C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT6 + OTG_HCINT6 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x5C8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK6 + OTG_HCINTMSK6 + This register reflects the mask for each channel status described in the previous section. + 0x5CC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ6 + OTG_HCTSIZ6 + OTG host channel 6 transfer size register + 0x5D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA6 + OTG_HCDMA6 + OTG host channel 6 DMA address register in buffer DMA [alternate] + 0x5D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB6 + OTG_HCDMAB6 + OTG host channel-n DMA address buffer register + 0x5DC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR7 + OTG_HCCHAR7 + OTG host channel 7 characteristics register + 0x5E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT7 + OTG_HCSPLT7 + OTG host channel 7 split control register + 0x5E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT7 + OTG_HCINT7 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x5E8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK7 + OTG_HCINTMSK7 + This register reflects the mask for each channel status described in the previous section. + 0x5EC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ7 + OTG_HCTSIZ7 + OTG host channel 7 transfer size register + 0x5F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA7 + OTG_HCDMA7 + OTG host channel 7 DMA address register in buffer DMA [alternate] + 0x5F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB7 + OTG_HCDMAB7 + OTG host channel-n DMA address buffer register + 0x5FC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR8 + OTG_HCCHAR8 + OTG host channel 8 characteristics register + 0x600 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT8 + OTG_HCSPLT8 + OTG host channel 8 split control register + 0x604 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT8 + OTG_HCINT8 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x608 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK8 + OTG_HCINTMSK8 + This register reflects the mask for each channel status described in the previous section. + 0x60C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ8 + OTG_HCTSIZ8 + OTG host channel 8 transfer size register + 0x610 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA8 + OTG_HCDMA8 + OTG host channel 8 DMA address register in buffer DMA [alternate] + 0x614 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB8 + OTG_HCDMAB8 + OTG host channel-n DMA address buffer register + 0x61C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR9 + OTG_HCCHAR9 + OTG host channel 9 characteristics register + 0x620 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT9 + OTG_HCSPLT9 + OTG host channel 9 split control register + 0x624 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT9 + OTG_HCINT9 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x628 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK9 + OTG_HCINTMSK9 + This register reflects the mask for each channel status described in the previous section. + 0x62C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ9 + OTG_HCTSIZ9 + OTG host channel 9 transfer size register + 0x630 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA9 + OTG_HCDMA9 + OTG host channel 9 DMA address register in buffer DMA [alternate] + 0x634 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB9 + OTG_HCDMAB9 + OTG host channel-n DMA address buffer register + 0x63C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR10 + OTG_HCCHAR10 + OTG host channel 10 characteristics register + 0x640 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT10 + OTG_HCSPLT10 + OTG host channel 10 split control register + 0x644 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT10 + OTG_HCINT10 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x648 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK10 + OTG_HCINTMSK10 + This register reflects the mask for each channel status described in the previous section. + 0x64C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ10 + OTG_HCTSIZ10 + OTG host channel 10 transfer size register + 0x650 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA10 + OTG_HCDMA10 + OTG host channel 10 DMA address register in buffer DMA [alternate] + 0x654 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB10 + OTG_HCDMAB10 + OTG host channel-n DMA address buffer register + 0x65C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR11 + OTG_HCCHAR11 + OTG host channel 11 characteristics register + 0x660 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT11 + OTG_HCSPLT11 + OTG host channel 11 split control register + 0x664 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT11 + OTG_HCINT11 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x668 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK11 + OTG_HCINTMSK11 + This register reflects the mask for each channel status described in the previous section. + 0x66C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ11 + OTG_HCTSIZ11 + OTG host channel 11 transfer size register + 0x670 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA11 + OTG_HCDMA11 + OTG host channel 11 DMA address register in buffer DMA [alternate] + 0x674 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB11 + OTG_HCDMAB11 + OTG host channel-n DMA address buffer register + 0x67C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR12 + OTG_HCCHAR12 + OTG host channel 12 characteristics register + 0x680 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT12 + OTG_HCSPLT12 + OTG host channel 12 split control register + 0x684 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT12 + OTG_HCINT12 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x688 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK12 + OTG_HCINTMSK12 + This register reflects the mask for each channel status described in the previous section. + 0x68C + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ12 + OTG_HCTSIZ12 + OTG host channel 12 transfer size register + 0x690 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA12 + OTG_HCDMA12 + OTG host channel 12 DMA address register in buffer DMA [alternate] + 0x694 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB12 + OTG_HCDMAB12 + OTG host channel-n DMA address buffer register + 0x69C + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR13 + OTG_HCCHAR13 + OTG host channel 13 characteristics register + 0x6A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT13 + OTG_HCSPLT13 + OTG host channel 13 split control register + 0x6A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT13 + OTG_HCINT13 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x6A8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK13 + OTG_HCINTMSK13 + This register reflects the mask for each channel status described in the previous section. + 0x6AC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ13 + OTG_HCTSIZ13 + OTG host channel 13 transfer size register + 0x6B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA13 + OTG_HCDMA13 + OTG host channel 13 DMA address register in buffer DMA [alternate] + 0x6B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB13 + OTG_HCDMAB13 + OTG host channel-n DMA address buffer register + 0x6BC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR14 + OTG_HCCHAR14 + OTG host channel 14 characteristics register + 0x6C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT14 + OTG_HCSPLT14 + OTG host channel 14 split control register + 0x6C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT14 + OTG_HCINT14 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x6C8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK14 + OTG_HCINTMSK14 + This register reflects the mask for each channel status described in the previous section. + 0x6CC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ14 + OTG_HCTSIZ14 + OTG host channel 14 transfer size register + 0x6D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA14 + OTG_HCDMA14 + OTG host channel 14 DMA address register in buffer DMA [alternate] + 0x6D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB14 + OTG_HCDMAB14 + OTG host channel-n DMA address buffer register + 0x6DC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_HCCHAR15 + OTG_HCCHAR15 + OTG host channel 15 characteristics register + 0x6E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + + + EPNUM + EPNUM + 11 + 4 + + + EPDIR + EPDIR + 15 + 1 + + + LSDEV + LSDEV + 17 + 1 + + + EPTYP + EPTYP + 18 + 2 + + + MCNT + MCNT + 20 + 2 + + + DAD + DAD + 22 + 7 + + + CHDIS + CHDIS + 30 + 1 + + + CHENA + CHENA + 31 + 1 + + + + + OTG_HCSPLT15 + OTG_HCSPLT15 + OTG host channel 15 split control register + 0x6E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + PRTADDR + 0 + 7 + + + HUBADDR + HUBADDR + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + COMPLSPLT + 16 + 1 + + + SPLITEN + SPLITEN + 31 + 1 + + + + + OTG_HCINT15 + OTG_HCINT15 + This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. + 0x6E8 + 0x20 + read-write + 0x00000000 + + + XFRC + XFRC + 0 + 1 + + + CHH + CHH + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STALL + STALL + 3 + 1 + + + NAK + NAK + 4 + 1 + + + ACK + ACK + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERR + TXERR + 7 + 1 + + + BBERR + BBERR + 8 + 1 + + + FRMOR + FRMOR + 9 + 1 + + + DTERR + DTERR + 10 + 1 + + + BNA + BNA + 11 + 1 + + + XCSXACTERR + XCSXACTERR + 12 + 1 + + + DESCLSTROLL + DESCLSTROLL + 13 + 1 + + + + + OTG_HCINTMSK15 + OTG_HCINTMSK15 + This register reflects the mask for each channel status described in the previous section. + 0x6EC + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + CHHM + CHHM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STALLM + STALLM + 3 + 1 + + + NAKM + NAKM + 4 + 1 + + + ACKM + ACKM + 5 + 1 + + + NYET + NYET + 6 + 1 + + + TXERRM + TXERRM + 7 + 1 + + + BBERRM + BBERRM + 8 + 1 + + + FRMORM + FRMORM + 9 + 1 + + + DTERRM + DTERRM + 10 + 1 + + + BNAMSK + BNAMSK + 11 + 1 + + + DESCLSTROLLMSK + DESCLSTROLLMSK + 13 + 1 + + + + + OTG_HCTSIZ15 + OTG_HCTSIZ15 + OTG host channel 15 transfer size register + 0x6F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + DPID + DPID + 29 + 2 + + + + + OTG_HCDMA15 + OTG_HCDMA15 + OTG host channel 15 DMA address register in buffer DMA [alternate] + 0x6F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_HCDMAB15 + OTG_HCDMAB15 + OTG host channel-n DMA address buffer register + 0x6FC + 0x20 + read-only + 0x00000000 + + + HCDMAB + HCDMAB + 0 + 32 + + + + + OTG_DCFG + OTG_DCFG + This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. + 0x800 + 0x20 + read-write + 0x02200000 + + + DSPD + DSPD + 0 + 2 + + + NZLSOHSK + NZLSOHSK + 2 + 1 + + + DAD + DAD + 4 + 7 + + + PFIVL + PFIVL + 11 + 2 + + + XCVRDLY + XCVRDLY + 14 + 1 + + + ERRATIM + ERRATIM + 15 + 1 + + + PERSCHIVL + PERSCHIVL + 24 + 2 + + + + + OTG_DCTL + OTG_DCTL + OTG device control register + 0x804 + 0x20 + 0x00000002 + + + RWUSIG + RWUSIG + 0 + 1 + read-write + + + SDIS + SDIS + 1 + 1 + read-write + + + GINSTS + GINSTS + 2 + 1 + read-only + + + GONSTS + GONSTS + 3 + 1 + read-only + + + TCTL + TCTL + 4 + 3 + read-write + + + SGINAK + SGINAK + 7 + 1 + write-only + + + CGINAK + CGINAK + 8 + 1 + write-only + + + SGONAK + SGONAK + 9 + 1 + write-only + + + CGONAK + CGONAK + 10 + 1 + write-only + + + POPRGDNE + POPRGDNE + 11 + 1 + read-write + + + DSBESLRJCT + DSBESLRJCT + 18 + 1 + read-write + + + + + OTG_DSTS + OTG_DSTS + This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. + 0x808 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + SUSPSTS + 0 + 1 + + + ENUMSPD + ENUMSPD + 1 + 2 + + + EERR + EERR + 3 + 1 + + + FNSOF + FNSOF + 8 + 14 + + + DEVLNSTS + DEVLNSTS + 22 + 2 + + + + + OTG_DIEPMSK + OTG_DIEPMSK + This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. + 0x810 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + TOM + TOM + 3 + 1 + + + ITTXFEMSK + ITTXFEMSK + 4 + 1 + + + INEPNMM + INEPNMM + 5 + 1 + + + INEPNEM + INEPNEM + 6 + 1 + + + TXFURM + TXFURM + 8 + 1 + + + BNAM + BNAM + 9 + 1 + + + NAKM + NAKM + 13 + 1 + + + + + OTG_DOEPMSK + OTG_DOEPMSK + This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. + 0x814 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STUPM + STUPM + 3 + 1 + + + OTEPDM + OTEPDM + 4 + 1 + + + STSPHSRXM + STSPHSRXM + 5 + 1 + + + B2BSTUPM + B2BSTUPM + 6 + 1 + + + OUTPKTERRM + OUTPKTERRM + 8 + 1 + + + BNAM + BNAM + 9 + 1 + + + BERRM + BERRM + 12 + 1 + + + NAKMSK + NAKMSK + 13 + 1 + + + NYETMSK + NYETMSK + 14 + 1 + + + + + OTG_DAINT + OTG_DAINT + When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). + 0x818 + 0x20 + read-only + 0x00000000 + + + IEPINT + IEPINT + 0 + 16 + + + OEPINT + OEPINT + 16 + 16 + + + + + OTG_DAINTMSK + OTG_DAINTMSK + The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. + 0x81C + 0x20 + read-write + 0x00000000 + + + IEPM + IEPM + 0 + 16 + + + OEPM + OEPM + 16 + 16 + + + + + OTG_DVBUSDIS + OTG_DVBUSDIS + This register specifies the VBUS discharge time after VBUS pulsing during SRP. + 0x828 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + VBUSDT + 0 + 16 + + + + + OTG_DVBUSPULSE + OTG_DVBUSPULSE + This register specifies the VBUS pulsing time during SRP. + 0x82C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + DVBUSP + 0 + 16 + + + + + OTG_DTHRCTL + OTG_DTHRCTL + OTG device threshold control register + 0x830 + 0x20 + read-write + 0x00000000 + + + NONISOTHREN + NONISOTHREN + 0 + 1 + + + ISOTHREN + ISOTHREN + 1 + 1 + + + TXTHRLEN + TXTHRLEN + 2 + 9 + + + RXTHREN + RXTHREN + 16 + 1 + + + RXTHRLEN + RXTHRLEN + 17 + 9 + + + ARPEN + ARPEN + 27 + 1 + + + + + OTG_DIEPEMPMSK + OTG_DIEPEMPMSK + This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). + 0x834 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + INEPTXFEM + 0 + 16 + + + + + OTG_DEACHINT + OTG_DEACHINT + OTG device each endpoint interrupt register + 0x838 + 0x20 + read-only + 0x00000000 + + + IEP1INT + IEP1INT + 1 + 1 + + + OEP1INT + OEP1INT + 17 + 1 + + + + + OTG_DEACHINTMSK + OTG_DEACHINTMSK + There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT. + 0x83C + 0x20 + read-write + 0x00000000 + + + IEP1INTM + IEP1INTM + 1 + 1 + + + OEP1INTM + OEP1INTM + 17 + 1 + + + + + OTG_HS_DIEPEACHMSK1 + OTG_HS_DIEPEACHMSK1 + This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. + 0x844 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + TOM + TOM + 3 + 1 + + + ITTXFEMSK + ITTXFEMSK + 4 + 1 + + + INEPNEM + INEPNEM + 6 + 1 + + + TXFURM + TXFURM + 8 + 1 + + + BNAM + BNAM + 9 + 1 + + + NAKM + NAKM + 13 + 1 + + + + + OTG_HS_DOEPEACHMSK1 + OTG_HS_DOEPEACHMSK1 + This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. + 0x884 + 0x20 + read-write + 0x00000000 + + + XFRCM + XFRCM + 0 + 1 + + + EPDM + EPDM + 1 + 1 + + + AHBERRM + AHBERRM + 2 + 1 + + + STUPM + STUPM + 3 + 1 + + + OTEPDM + OTEPDM + 4 + 1 + + + B2BSTUPM + B2BSTUPM + 6 + 1 + + + OUTPKTERRM + OUTPKTERRM + 8 + 1 + + + BNAM + BNAM + 9 + 1 + + + BERRM + BERRM + 12 + 1 + + + NAKMSK + NAKMSK + 13 + 1 + + + NYETMSK + NYETMSK + 14 + 1 + + + + + OTG_DIEPCTL0 + OTG_DIEPCTL0 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x900 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT0 + OTG_DIEPINT0 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x908 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ0 + OTG_DIEPTSIZ0 + The application must modify this register before enabling endpoint 0. + 0x910 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 7 + + + PKTCNT + PKTCNT + 19 + 2 + + + + + OTG_DIEPDMA0 + OTG_DIEPDMA0 + OTG device IN endpoint 0 DMA address register + 0x914 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS0 + OTG_DTXFSTS0 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x918 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL1 + OTG_DIEPCTL1 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x920 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT1 + OTG_DIEPINT1 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x928 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ1 + OTG_DIEPTSIZ1 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x930 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA1 + OTG_DIEPDMA1 + OTG device IN endpoint 1 DMA address register + 0x934 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS1 + OTG_DTXFSTS1 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x938 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL2 + OTG_DIEPCTL2 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x940 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT2 + OTG_DIEPINT2 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x948 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ2 + OTG_DIEPTSIZ2 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x950 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA2 + OTG_DIEPDMA2 + OTG device IN endpoint 2 DMA address register + 0x954 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS2 + OTG_DTXFSTS2 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x958 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL3 + OTG_DIEPCTL3 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x960 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT3 + OTG_DIEPINT3 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x968 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ3 + OTG_DIEPTSIZ3 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x970 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA3 + OTG_DIEPDMA3 + OTG device IN endpoint 3 DMA address register + 0x974 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS3 + OTG_DTXFSTS3 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x978 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL4 + OTG_DIEPCTL4 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x980 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT4 + OTG_DIEPINT4 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x988 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ4 + OTG_DIEPTSIZ4 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x990 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA4 + OTG_DIEPDMA4 + OTG device IN endpoint 4 DMA address register + 0x994 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS4 + OTG_DTXFSTS4 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x998 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL5 + OTG_DIEPCTL5 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x9A0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT5 + OTG_DIEPINT5 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x9A8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ5 + OTG_DIEPTSIZ5 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA5 + OTG_DIEPDMA5 + OTG device IN endpoint 5 DMA address register + 0x9B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS5 + OTG_DTXFSTS5 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x9B8 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL6 + OTG_DIEPCTL6 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x9C0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT6 + OTG_DIEPINT6 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x9C8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ6 + OTG_DIEPTSIZ6 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA6 + OTG_DIEPDMA6 + OTG device IN endpoint 6 DMA address register + 0x9D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS6 + OTG_DTXFSTS6 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x9D8 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL7 + OTG_DIEPCTL7 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0x9E0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT7 + OTG_DIEPINT7 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0x9E8 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ7 + OTG_DIEPTSIZ7 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0x9F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA7 + OTG_DIEPDMA7 + OTG device IN endpoint 7 DMA address register + 0x9F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS7 + OTG_DTXFSTS7 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0x9F8 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DIEPCTL8 + OTG_DIEPCTL8 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xA00 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DIEPINT8 + OTG_DIEPINT8 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xA08 + 0x20 + 0x00000080 + + + XFRC + XFRC + 0 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + AHBERR + AHBERR + 2 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + INEPNM + INEPNM + 5 + 1 + read-write + + + INEPNE + INEPNE + 6 + 1 + read-only + + + TXFE + TXFE + 7 + 1 + read-only + + + TXFIFOUDRN + TXFIFOUDRN + 8 + 1 + read-write + + + BNA + BNA + 9 + 1 + read-write + + + PKTDRPSTS + PKTDRPSTS + 11 + 1 + read-write + + + NAK + NAK + 13 + 1 + read-write + + + + + OTG_DIEPTSIZ8 + OTG_DIEPTSIZ8 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xA10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + MCNT + MCNT + 29 + 2 + + + + + OTG_DIEPDMA8 + OTG_DIEPDMA8 + OTG device IN endpoint 8 DMA address register + 0xA14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DTXFSTS8 + OTG_DTXFSTS8 + This read-only register contains the free space information for the device IN endpoint Tx FIFO. + 0xA18 + 0x20 + read-only + 0x00000200 + + + INEPTFSAV + INEPTFSAV + 0 + 16 + + + + + OTG_DOEPCTL0 + OTG_DOEPCTL0 + This section describes the OTG_DOEPCTL0 register. + 0xB00 + 0x20 + 0x00008000 + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-only + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + EPENA + EPENA + 31 + 1 + write-only + + + + + OTG_DOEPINT0 + OTG_DOEPINT0 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xB08 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ0 + OTG_DOEPTSIZ0 + The application must modify this register before enabling endpoint 0. + 0xB10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 7 + + + PKTCNT + PKTCNT + 19 + 1 + + + STUPCNT + STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA0 + OTG_DOEPDMA0 + OTG device OUT endpoint 0 DMA address register + 0xB14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL1 + OTG_DOEPCTL1 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB20 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT1 + OTG_DOEPINT1 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xB28 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ1 + OTG_DOEPTSIZ1 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB30 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA1 + OTG_DOEPDMA1 + OTG device OUT endpoint 1 DMA address register + 0xB34 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL2 + OTG_DOEPCTL2 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB40 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT2 + OTG_DOEPINT2 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xB48 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ2 + OTG_DOEPTSIZ2 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB50 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA2 + OTG_DOEPDMA2 + OTG device OUT endpoint 2 DMA address register + 0xB54 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL3 + OTG_DOEPCTL3 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB60 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT3 + OTG_DOEPINT3 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xB68 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ3 + OTG_DOEPTSIZ3 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB70 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA3 + OTG_DOEPDMA3 + OTG device OUT endpoint 3 DMA address register + 0xB74 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL4 + OTG_DOEPCTL4 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xB80 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT4 + OTG_DOEPINT4 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xB88 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ4 + OTG_DOEPTSIZ4 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xB90 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA4 + OTG_DOEPDMA4 + OTG device OUT endpoint 4 DMA address register + 0xB94 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL5 + OTG_DOEPCTL5 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBA0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT5 + OTG_DOEPINT5 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xBA8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ5 + OTG_DOEPTSIZ5 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBB0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA5 + OTG_DOEPDMA5 + OTG device OUT endpoint 5 DMA address register + 0xBB4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL6 + OTG_DOEPCTL6 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBC0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT6 + OTG_DOEPINT6 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xBC8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ6 + OTG_DOEPTSIZ6 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBD0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA6 + OTG_DOEPDMA6 + OTG device OUT endpoint 6 DMA address register + 0xBD4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL7 + OTG_DOEPCTL7 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xBE0 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT7 + OTG_DOEPINT7 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xBE8 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ7 + OTG_DOEPTSIZ7 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xBF0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA7 + OTG_DOEPDMA7 + OTG device OUT endpoint 7 DMA address register + 0xBF4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_DOEPCTL8 + OTG_DOEPCTL8 + The application uses this register to control the behavior of each logical endpoint other than endpoint 0. + 0xC00 + 0x20 + 0x00000000 + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + USBAEP + USBAEP + 15 + 1 + read-write + + + EONUM_DPIP + EONUM_DPIP + 16 + 1 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EPTYP + EPTYP + 18 + 2 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + STALL + STALL + 21 + 1 + read-write + + + CNAK + CNAK + 26 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID_SEVNFRM + 28 + 1 + write-only + + + SD1PID_SODDFRM + SD1PID_SODDFRM + 29 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-write + + + EPENA + EPENA + 31 + 1 + read-write + + + + + OTG_DOEPINT8 + OTG_DOEPINT8 + This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. + 0xC08 + 0x20 + read-write + 0x00000080 + + + XFRC + XFRC + 0 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + AHBERR + AHBERR + 2 + 1 + + + STUP + STUP + 3 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STSPHSRX + STSPHSRX + 5 + 1 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OUTPKTERR + OUTPKTERR + 8 + 1 + + + BNA + BNA + 9 + 1 + + + BERR + BERR + 12 + 1 + + + NAK + NAK + 13 + 1 + + + NYET + NYET + 14 + 1 + + + STPKTRX + STPKTRX + 15 + 1 + + + + + OTG_DOEPTSIZ8 + OTG_DOEPTSIZ8 + The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. + 0xC10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + XFRSIZ + 0 + 19 + + + PKTCNT + PKTCNT + 19 + 10 + + + RXDPID_STUPCNT + RXDPID_STUPCNT + 29 + 2 + + + + + OTG_DOEPDMA8 + OTG_DOEPDMA8 + OTG device OUT endpoint 8 DMA address register + 0xC14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMAADDR + 0 + 32 + + + + + OTG_PCGCCTL + OTG_PCGCCTL + This register is available in host and device modes. + 0xE00 + 0x20 + 0x200B8000 + + + STPPCLK + STPPCLK + 0 + 1 + read-write + + + GATEHCLK + GATEHCLK + 1 + 1 + read-write + + + PHYSUSP + PHYSUSP + 4 + 1 + read-only + + + ENL1GTG + ENL1GTG + 5 + 1 + read-write + + + PHYSLEEP + PHYSLEEP + 6 + 1 + read-only + + + SUSP + SUSP + 7 + 1 + read-only + + + + + + + MDIOS + MDIOS + MDIOS + 0x4001C000 + + 0x0 + 0x400 + registers + + + + MDIOS_CR + MDIOS_CR + MDIOS configuration register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + WRIE + WRIE + 1 + 1 + read-write + + + RDIE + RDIE + 2 + 1 + read-write + + + EIE + EIE + 3 + 1 + read-write + + + DPC + DPC + 7 + 1 + read-write + + + PORT_ADDRESS + PORT_ADDRESS + 8 + 5 + read-write + + + + + MDIOS_WRFR + MDIOS_WRFR + MDIOS write flag register + 0x04 + 0x20 + read-only + 0x00000000 + + + WRF + WRF + 0 + 32 + read-only + + + + + MDIOS_CWRFR + MDIOS_CWRFR + MDIOS clear write flag + register + 0x08 + 0x20 + read-write + 0x00000000 + + + CWRF + CWRF + 0 + 32 + read-write + + + + + MDIOS_RDFR + MDIOS_RDFR + MDIOS read flag register + 0x0C + 0x20 + read-only + 0x00000000 + + + RDF + RDF + 0 + 32 + read-only + + + + + MDIOS_CRDFR + MDIOS_CRDFR + MDIOS clear read flag register + 0x10 + 0x20 + read-write + 0x00000000 + + + CRDF + CRDF + 0 + 32 + read-write + + + + + MDIOS_SR + MDIOS_SR + MDIOS status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PERF + PERF + 0 + 1 + read-only + + + SERF + SERF + 1 + 1 + read-only + + + TERF + TERF + 2 + 1 + read-only + + + + + MDIOS_CLRFR + MDIOS_CLRFR + MDIOS clear flag register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPERF + CPERF + 0 + 1 + read-write + + + CSERF + CSERF + 1 + 1 + read-write + + + CTERF + CTERF + 2 + 1 + read-write + + + + + MDIOS_DINR0 + MDIOS_DINR0 + MDIOS input data register + 0x100 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR1 + MDIOS_DINR1 + MDIOS input data register + 0x104 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR2 + MDIOS_DINR2 + MDIOS input data register + 0x108 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR3 + MDIOS_DINR3 + MDIOS input data register + 0x10C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR4 + MDIOS_DINR4 + MDIOS input data register + 0x110 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR5 + MDIOS_DINR5 + MDIOS input data register + 0x114 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR6 + MDIOS_DINR6 + MDIOS input data register + 0x118 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR7 + MDIOS_DINR7 + MDIOS input data register + 0x11C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR8 + MDIOS_DINR8 + MDIOS input data register + 0x120 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR9 + MDIOS_DINR9 + MDIOS input data register + 0x124 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR10 + MDIOS_DINR10 + MDIOS input data register + 0x128 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR11 + MDIOS_DINR11 + MDIOS input data register + 0x12C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR12 + MDIOS_DINR12 + MDIOS input data register + 0x130 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR13 + MDIOS_DINR13 + MDIOS input data register + 0x134 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR14 + MDIOS_DINR14 + MDIOS input data register + 0x138 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR15 + MDIOS_DINR15 + MDIOS input data register + 0x13C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR16 + MDIOS_DINR16 + MDIOS input data register + 0x140 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR17 + MDIOS_DINR17 + MDIOS input data register + 0x144 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR18 + MDIOS_DINR18 + MDIOS input data register + 0x148 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR19 + MDIOS_DINR19 + MDIOS input data register + 0x14C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR20 + MDIOS_DINR20 + MDIOS input data register + 0x150 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR21 + MDIOS_DINR21 + MDIOS input data register + 0x154 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR22 + MDIOS_DINR22 + MDIOS input data register + 0x158 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR23 + MDIOS_DINR23 + MDIOS input data register + 0x15C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR24 + MDIOS_DINR24 + MDIOS input data register + 0x160 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR25 + MDIOS_DINR25 + MDIOS input data register + 0x164 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR26 + MDIOS_DINR26 + MDIOS input data register + 0x168 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR27 + MDIOS_DINR27 + MDIOS input data register + 0x16C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR28 + MDIOS_DINR28 + MDIOS input data register + 0x170 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR29 + MDIOS_DINR29 + MDIOS input data register + 0x174 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR30 + MDIOS_DINR30 + MDIOS input data register + 0x178 + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DINR31 + MDIOS_DINR31 + MDIOS input data register + 0x17C + 0x20 + read-only + 0x00000000 + + + DIN + DIN + 0 + 16 + read-only + + + + + MDIOS_DOUTR0 + MDIOS_DOUTR0 + MDIOS input data register + 0x180 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR1 + MDIOS_DOUTR1 + MDIOS input data register + 0x184 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR2 + MDIOS_DOUTR2 + MDIOS output data register + 0x188 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR3 + MDIOS_DOUTR3 + MDIOS output data register + 0x18C + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR4 + MDIOS_DOUTR4 + MDIOS output data register + 0x190 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR5 + MDIOS_DOUTR5 + MDIOS output data register + 0x194 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR6 + MDIOS_DOUTR6 + MDIOS output data register + 0x198 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR7 + MDIOS_DOUTR7 + MDIOS output data register + 0x19C + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR8 + MDIOS_DOUTR8 + MDIOS output data register + 0x1A0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR9 + MDIOS_DOUTR9 + MDIOS output data register + 0x1A4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR10 + MDIOS_DOUTR10 + MDIOS output data register + 0x1A8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR11 + MDIOS_DOUTR11 + MDIOS output data register + 0x1AC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR12 + MDIOS_DOUTR12 + MDIOS output data register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR13 + MDIOS_DOUTR13 + MDIOS output data register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR14 + MDIOS_DOUTR14 + MDIOS output data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR15 + MDIOS_DOUTR15 + MDIOS output data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR16 + MDIOS_DOUTR16 + MDIOS output data register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR17 + MDIOS_DOUTR17 + MDIOS output data register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR18 + MDIOS_DOUTR18 + MDIOS output data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR19 + MDIOS_DOUTR19 + MDIOS output data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR20 + MDIOS_DOUTR20 + MDIOS output data register + 0x1D0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR21 + MDIOS_DOUTR21 + MDIOS output data register + 0x1D4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR22 + MDIOS_DOUTR22 + MDIOS output data register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR23 + MDIOS_DOUTR23 + MDIOS output data register + 0x1DC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR24 + MDIOS_DOUTR24 + MDIOS output data register + 0x1E0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR25 + MDIOS_DOUTR25 + MDIOS output data register + 0x1E4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR26 + MDIOS_DOUTR26 + MDIOS output data register + 0x1E8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR27 + MDIOS_DOUTR27 + MDIOS output data register + 0x1EC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR28 + MDIOS_DOUTR28 + MDIOS output data register + 0x1F0 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR29 + MDIOS_DOUTR29 + MDIOS output data register + 0x1F4 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR30 + MDIOS_DOUTR30 + MDIOS output data register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_DOUTR31 + MDIOS_DOUTR31 + MDIOS output data register + 0x1FC + 0x20 + read-only + 0x00000000 + + + DOUT + DOUT + 0 + 16 + read-only + + + + + MDIOS_HWCFGR + MDIOS_HWCFGR + MDIOS HW configuration + register + 0x3F0 + 0x20 + read-only + 0x00000020 + + + NBREG + NBREG + 0 + 8 + read-only + + + + + MDIOS_VERR + MDIOS_VERR + MDIOS version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + read-only + + + MAJREV + MAJREV + 4 + 4 + read-only + + + + + MDIOS_IPIDR + MDIOS_IPIDR + MDIOS identification register + 0x3F8 + 0x20 + read-only + 0x00180001 + + + ID + ID + 0 + 32 + read-only + + + + + MDIOS_SIDR + MDIOS_SIDR + MDIOS size identification + register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + read-only + + + + + + + HDMI_CEC + HDMI_CEC + HDMI_CEC + 0x40016000 + + 0x0 + 0x400 + registers + + + + CEC_CR + CEC_CR + CEC control register + 0x00 + 0x20 + read-write + 0x00000000 + + + CECEN + CECEN + 0 + 1 + read-write + + + TXSOM + TXSOM + 1 + 1 + read-write + + + TXEOM + TXEOM + 2 + 1 + read-write + + + + + CEC_CFGR + CEC_CFGR + This register is used to configure the HDMI-CEC controller. +It is mandatory to write CEC_CFGR only when CECEN=0. + 0x04 + 0x20 + read-write + 0x00000000 + + + SFT + SFT + 0 + 3 + read-write + + + RXTOL + RXTOL + 3 + 1 + read-write + + + BRESTP + BRESTP + 4 + 1 + read-write + + + BREGEN + BREGEN + 5 + 1 + read-write + + + LBPEGEN + LBPEGEN + 6 + 1 + read-write + + + BRDNOGEN + BRDNOGEN + 7 + 1 + read-write + + + SFTOP + SFTOP + 8 + 1 + read-write + + + OAR + OAR + 16 + 15 + read-write + + + LSTN + LSTN + 31 + 1 + read-write + + + + + CEC_TXDR + CEC_TXDR + CEC Tx data register + 0x08 + 0x20 + read-write + 0x00000000 + + + TXD + TXD + 0 + 8 + write-only + + + + + CEC_RXDR + CEC_RXDR + CEC Rx data register + 0x0C + 0x20 + read-only + 0x00000000 + + + RXD + RXD + 0 + 8 + read-only + + + + + CEC_ISR + CEC_ISR + CEC Interrupt and Status Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXBR + RXBR + 0 + 1 + read-write + + + RXEND + RXEND + 1 + 1 + read-write + + + RXOVR + RXOVR + 2 + 1 + read-write + + + BRE + BRE + 3 + 1 + read-write + + + SBPE + SBPE + 4 + 1 + read-write + + + LBPE + LBPE + 5 + 1 + read-write + + + RXACKE + RXACKE + 6 + 1 + read-write + + + ARBLST + ARBLST + 7 + 1 + read-write + + + TXBR + TXBR + 8 + 1 + read-write + + + TXEND + TXEND + 9 + 1 + read-write + + + TXUDR + TXUDR + 10 + 1 + read-write + + + TXERR + TXERR + 11 + 1 + read-write + + + TXACKE + TXACKE + 12 + 1 + read-write + + + + + CEC_IER + CEC_IER + CEC interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBRIE + RXBRIE + 0 + 1 + read-write + + + RXENDIE + RXENDIE + 1 + 1 + read-write + + + RXOVRIE + RXOVRIE + 2 + 1 + read-write + + + BREIE + BREIE + 3 + 1 + read-write + + + SBPEIE + SBPEIE + 4 + 1 + read-write + + + LBPEIE + LBPEIE + 5 + 1 + read-write + + + RXACKIE + RXACKIE + 6 + 1 + read-write + + + ARBLSTIE + ARBLSTIE + 7 + 1 + read-write + + + TXBRIE + TXBRIE + 8 + 1 + read-write + + + TXENDIE + TXENDIE + 9 + 1 + read-write + + + TXUDRIE + TXUDRIE + 10 + 1 + read-write + + + TXERRIE + TXERRIE + 11 + 1 + read-write + + + TXACKIE + TXACKIE + 12 + 1 + read-write + + + + + + + SPDIFRX + SPDIFRX + SPDIFRX + 0x4000D000 + + 0x0 + 0x400 + registers + + + + SPDIFRX_CR + SPDIFRX_CR + Control register + 0x00 + 0x20 + read-write + 0x00000000 + + + SPDIFRXEN + SPDIFRXEN + 0 + 2 + read-write + + + RXDMAEN + RXDMAEN + 2 + 1 + read-write + + + RXSTEO + RXSTEO + 3 + 1 + read-write + + + DRFMT + DRFMT + 4 + 2 + read-write + + + PMSK + PMSK + 6 + 1 + read-write + + + VMSK + VMSK + 7 + 1 + read-write + + + CUMSK + CUMSK + 8 + 1 + read-write + + + PTMSK + PTMSK + 9 + 1 + read-write + + + CBDMAEN + CBDMAEN + 10 + 1 + read-write + + + CHSEL + CHSEL + 11 + 1 + read-write + + + NBTR + NBTR + 12 + 2 + read-write + + + WFA + WFA + 14 + 1 + read-write + + + INSEL + INSEL + 16 + 3 + read-write + + + CKSEN + CKSEN + 20 + 1 + read-write + + + CKSBKPEN + CKSBKPEN + 21 + 1 + read-write + + + + + SPDIFRX_IMR + SPDIFRX_IMR + Interrupt mask register + 0x04 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNEIE + 0 + 1 + read-write + + + CSRNEIE + CSRNEIE + 1 + 1 + read-write + + + PERRIE + PERRIE + 2 + 1 + read-write + + + OVRIE + OVRIE + 3 + 1 + read-write + + + SBLKIE + SBLKIE + 4 + 1 + read-write + + + SYNCDIE + SYNCDIE + 5 + 1 + read-write + + + IFEIE + IFEIE + 6 + 1 + read-write + + + + + SPDIFRX_SR + SPDIFRX_SR + Status register + 0x08 + 0x20 + read-only + 0x00000000 + + + RXNE + RXNE + 0 + 1 + read-only + + + CSRNE + CSRNE + 1 + 1 + read-only + + + PERR + PERR + 2 + 1 + read-only + + + OVR + OVR + 3 + 1 + read-only + + + SBD + SBD + 4 + 1 + read-only + + + SYNCD + SYNCD + 5 + 1 + read-only + + + FERR + FERR + 6 + 1 + read-only + + + SERR + SERR + 7 + 1 + read-only + + + TERR + TERR + 8 + 1 + read-only + + + WIDTH5 + WIDTH5 + 16 + 15 + read-only + + + + + SPDIFRX_IFCR + SPDIFRX_IFCR + Interrupt flag clear register + 0x0C + 0x20 + read-write + 0x00000000 + + + PERRCF + PERRCF + 2 + 1 + write-only + + + OVRCF + OVRCF + 3 + 1 + write-only + + + SBDCF + SBDCF + 4 + 1 + write-only + + + SYNCDCF + SYNCDCF + 5 + 1 + write-only + + + + + SPDIFRX_FMT0_DR + SPDIFRX_FMT0_DR + This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00: + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + DR + 0 + 24 + read-only + + + PE + PE + 24 + 1 + read-only + + + V + V + 25 + 1 + read-only + + + U + U + 26 + 1 + read-only + + + C + C + 27 + 1 + read-only + + + PT + PT + 28 + 2 + read-only + + + + + SPDIFRX_CSR + SPDIFRX_CSR + Channel status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + USR + 0 + 16 + read-only + + + CS + CS + 16 + 8 + read-only + + + SOB + SOB + 24 + 1 + read-only + + + + + SPDIFRX_DIR + SPDIFRX_DIR + Debug information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + THI + 0 + 13 + read-only + + + TLO + TLO + 16 + 13 + read-only + + + + + SPDIFRX_VERR + SPDIFRX_VERR + SPDIFRX version register + 0x3F4 + 0x20 + read-only + 0x00000012 + + + MINREV + MINREV + 0 + 4 + read-only + + + MAJREV + MAJREV + 4 + 4 + read-only + + + + + SPDIFRX_IPIDR + SPDIFRX_IPIDR + SPDIFRX identification register + 0x3F8 + 0x20 + read-only + 0x00130041 + + + ID + ID + 0 + 32 + read-only + + + + + SPDIFRX_SIDR + SPDIFRX_SIDR + SPDIFRX size identification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + read-only + + + + + + + WWDG1 + WWDG1 + WWDG1 + 0x4000A000 + + 0x0 + 0x400 + registers + + + WWDG1_IT + Window Watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + Control register + 0x00 + 0x20 + read-write + 0x0000007F + + + T + T + 0 + 7 + read-write + + + WDGA + WDGA + 7 + 1 + read-write + + + + + WWDG_CFR + WWDG_CFR + Configuration register + 0x04 + 0x20 + read-write + 0x0000007F + + + W + W + 0 + 7 + read-write + + + EWI + EWI + 9 + 1 + read-write + + + WDGTB + WDGTB + 11 + 3 + read-write + + + + + WWDG_SR + WWDG_SR + Status register + 0x08 + 0x20 + read-write + 0x00000000 + + + EWIF + EWIF + 0 + 1 + read-write + + + + + WWDG_HWCFGR + WWDG_HWCFGR + WWDG hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000FFF + + + PREDIV + PREDIV + 0 + 16 + read-only + + + + + WWDG_VERR + WWDG_VERR + WWDG version register + 0x3F4 + 0x20 + read-only + 0x00000021 + + + MINREV + MINREV + 0 + 4 + read-only + + + MAJREV + MAJREV + 4 + 4 + read-only + + + + + WWDG_IPIDR + WWDG_IPIDR + WWDG ID register + 0x3F8 + 0x20 + read-only + 0x00120051 + + + ID + ID + 0 + 32 + read-only + + + + + WWDG_SIDR + WWDG_SIDR + WWDG size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + read-only + + + + + + + AXIMC_Mx + AXIMC_Mx + AXIMC_Mx + 0x57042024 + + 0x0 + 0x100000 + registers + + + + AXIMC_M0_FN_MOD2 + AXIMC_M0_FN_MOD2 + AXIMC master 0 packing functionality register + 0x0 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M0_READ_QOS + AXIMC_M0_READ_QOS + AXIMC master 0 read priority register + 0xDC + 0x20 + read-write + 0x00000006 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M0_WRITE_QOS + AXIMC_M0_WRITE_QOS + AXIMC master 0 write priority register + 0xE4 + 0x20 + read-write + 0x00000006 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M0_FN_MOD + AXIMC_M0_FN_MOD + AXIMC master 0 issuing capability override functionality register + 0xE0 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M1_FN_MOD2 + AXIMC_M1_FN_MOD2 + AXIMC master 1 packing functionality register + 0x1000 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M1_READ_QOS + AXIMC_M1_READ_QOS + AXIMC master 1 read priority register + 0x10DC + 0x20 + read-write + 0x00000006 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M1_WRITE_QOS + AXIMC_M1_WRITE_QOS + AXIMC master 1 write priority register + 0x10E0 + 0x20 + read-write + 0x00000006 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M1_FN_MOD + AXIMC_M1_FN_MOD + AXIMC master 1 issuing capability override functionality register + 0x10E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M2_FN_MOD2 + AXIMC_M2_FN_MOD2 + AXIMC master 2 packing functionality register + 0x2000 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M2_READ_QOS + AXIMC_M2_READ_QOS + AXIMC master 2 read priority register + 0x20DC + 0x20 + read-write + 0x00000006 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M2_WRITE_QOS + AXIMC_M2_WRITE_QOS + AXIMC master 2 write priority register + 0x20E0 + 0x20 + read-write + 0x00000006 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M2_FN_MOD + AXIMC_M2_FN_MOD + AXIMC master 2 issuing capability override functionality register + 0x20E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M5_FN_MOD2 + AXIMC_M5_FN_MOD2 + AXIMC master 5 packing functionality register + 0x3000 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M5_READ_QOS + AXIMC_M5_READ_QOS + AXIMC master 5 read priority register + 0x30DC + 0x20 + read-write + 0x00000004 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M5_WRITE_QOS + AXIMC_M5_WRITE_QOS + AXIMC master 5 write priority register + 0x30E0 + 0x20 + read-write + 0x00000004 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M5_FN_MOD + AXIMC_M5_FN_MOD + AXIMC master 5 issuing capability override functionality register + 0x30E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M3_READ_QOS + AXIMC_M3_READ_QOS + AXIMC master 3 read priority register + 0x40DC + 0x20 + read-write + 0x00000007 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M3_WRITE_QOS + AXIMC_M3_WRITE_QOS + AXIMC master 3 write priority register + 0x40E0 + 0x20 + read-write + 0x00000007 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M3_FN_MOD + AXIMC_M3_FN_MOD + AXIMC master 3 packing functionality register + 0x40E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M7_READ_QOS + AXIMC_M7_READ_QOS + AXIMC master 7 read priority register + 0x50DC + 0x20 + read-write + 0x00000008 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M7_WRITE_QOS + AXIMC_M7_WRITE_QOS + AXIMC master 7 write priority register + 0x50E0 + 0x20 + read-write + 0x00000008 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M7_FN_MOD + AXIMC_M7_FN_MOD + AXIMC master 7 issuing capability override functionality register + 0x50E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M8_READ_QOS + AXIMC_M8_READ_QOS + AXIMC master 8 read priority register + 0x60DC + 0x20 + read-write + 0x00000008 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M8_WRITE_QOS + AXIMC_M8_WRITE_QOS + AXIMC master 8 write priority register + 0x60E0 + 0x20 + read-write + 0x00000008 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M8_FN_MOD + AXIMC_M8_FN_MOD + AXIMC master 8 issuing capability override functionality register + 0x60E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M4_FN_MOD2 + AXIMC_M4_FN_MOD2 + AXIMC master 4 packing functionality register + 0x8000 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M4_READ_QOS + AXIMC_M4_READ_QOS + AXIMC master 4 read priority register + 0x80DC + 0x20 + read-write + 0x00000007 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M4_WRITE_QOS + AXIMC_M4_WRITE_QOS + AXIMC master 4 write priority register + 0x80E0 + 0x20 + read-write + 0x00000007 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M4_FN_MOD + AXIMC_M4_FN_MOD + AXIMC master 4 packing functionality register + 0x80E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M9_READ_QOS + AXIMC_M9_READ_QOS + AXIMC master 9 read priority register + 0x90DC + 0x20 + read-write + 0x0000000B + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M9_WRITE_QOS + AXIMC_M9_WRITE_QOS + AXIMC master 9 write priority register + 0x90E0 + 0x20 + read-write + 0x0000000B + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M9_FN_MOD + AXIMC_M9_FN_MOD + AXIMC master 9 issuing capability override functionality register + 0x90E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M10_READ_QOS + AXIMC_M10_READ_QOS + AXIMC master 10 read priority register + 0xA0DC + 0x20 + read-write + 0x0000000B + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M10_WRITE_QOS + AXIMC_M10_WRITE_QOS + AXIMC master 10 write priority register + 0xA0E0 + 0x20 + read-write + 0x0000000B + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M10_FN_MOD + AXIMC_M10_FN_MOD + AXIMC master 10 issuing capability override functionality register + 0xA0E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M6_FN_MOD2 + AXIMC_M6_FN_MOD2 + AXIMC master 6 packing functionality register + 0xB000 + 0x20 + read-write + 0x00000000 + + + BYPASS_MERGE + BYPASS_MERGE + 0 + 1 + read-write + + + + + AXIMC_M6_READ_QOS + AXIMC_M6_READ_QOS + AXIMC master 6 read priority register + 0xB0DC + 0x20 + read-write + 0x00000004 + + + AR_QOS + AR_QOS + 0 + 4 + read-write + + + + + AXIMC_M6_WRITE_QOS + AXIMC_M6_WRITE_QOS + AXIMC master 6 write priority register + 0xB0E0 + 0x20 + read-write + 0x00000004 + + + AW_QOS + AW_QOS + 0 + 4 + read-write + + + + + AXIMC_M6_FN_MOD + AXIMC_M6_FN_MOD + AXIMC master 6 issuing capability override functionality register + 0xB0E4 + 0x20 + read-write + 0x00000000 + + + READ_ISS_OVERRIDE + READ_ISS_OVERRIDE + 0 + 1 + read-write + + + WRITE_ISS_OVERRIDE + WRITE_ISS_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_PERIPH_ID_4 + AXIMC_PERIPH_ID_4 + AXIMC peripheral ID4 register + 0x1FD0 + 0x20 + read-only + 0x00000004 + + + JEP106CON + JEP106CON + 0 + 4 + read-only + + + K4COUNT + K4COUNT + 4 + 4 + read-only + + + + + AXIMC_PERIPH_ID_5 + AXIMC_PERIPH_ID_5 + AXIMC peripheral ID5 register + 0x1FD4 + 0x20 + read-only + 0x00000000 + + + PERIPH_ID_5 + PERIPH_ID_5 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_6 + AXIMC_PERIPH_ID_6 + AXIMC peripheral ID6 register + 0x1FD8 + 0x20 + read-only + 0x00000000 + + + PERIPH_ID_6 + PERIPH_ID_6 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_7 + AXIMC_PERIPH_ID_7 + AXIMC peripheral ID7 register + 0x1FDC + 0x20 + read-only + 0x00000000 + + + PERIPH_ID_7 + PERIPH_ID_7 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_0 + AXIMC_PERIPH_ID_0 + AXIMC peripheral ID0 register + 0x1FE0 + 0x20 + read-only + 0x00000000 + + + PERIPH_ID_0 + PERIPH_ID_0 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_1 + AXIMC_PERIPH_ID_1 + AXIMC peripheral ID1 register + 0x1FE4 + 0x20 + read-only + 0x000000B4 + + + PERIPH_ID_1 + PERIPH_ID_1 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_2 + AXIMC_PERIPH_ID_2 + AXIMC peripheral ID2 register + 0x1FE8 + 0x20 + read-only + 0x0000003B + + + PERIPH_ID_2 + PERIPH_ID_2 + 0 + 8 + read-only + + + + + AXIMC_PERIPH_ID_3 + AXIMC_PERIPH_ID_3 + AXIMC peripheral ID3 register + 0x1FEC + 0x20 + read-only + 0x00000000 + + + CUST_MOD_NUM + CUST_MOD_NUM + 0 + 4 + read-only + + + REV_AND + REV_AND + 4 + 4 + read-only + + + + + AXIMC_COMP_ID_0 + AXIMC_COMP_ID_0 + AXIMC component ID0 register + 0x1FF0 + 0x20 + read-only + 0x0000000D + + + PREAMBLE + PREAMBLE + 0 + 8 + read-only + + + + + AXIMC_COMP_ID_1 + AXIMC_COMP_ID_1 + AXIMC component ID1 register + 0x1FF4 + 0x20 + read-only + 0x000000F0 + + + PREAMBLE + PREAMBLE + 0 + 4 + read-only + + + CLASS + CLASS + 4 + 4 + read-only + + + + + AXIMC_COMP_ID_2 + AXIMC_COMP_ID_2 + AXIMC component ID2 register + 0x1FF8 + 0x20 + read-only + 0x00000005 + + + PREAMBLE + PREAMBLE + 0 + 8 + read-only + + + + + AXIMC_COMP_ID_3 + AXIMC_COMP_ID_3 + AXIMC component ID3 register + 0x1FFC + 0x20 + read-only + 0x000000B1 + + + PREAMBLE + PREAMBLE + 0 + 8 + read-only + + + + + AXIMC_M0_FN_MOD_AHB + AXIMC_M0_FN_MOD_AHB + AXIMC master 0 AHB conversion override functionality register + 0x42028 + 0x20 + read-write + 0x00000000 + + + RD_INC_OVERRIDE + RD_INC_OVERRIDE + 0 + 1 + read-write + + + WR_INC_OVERRIDE + WR_INC_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M1_FN_MOD_AHB + AXIMC_M1_FN_MOD_AHB + AXIMC master 1 AHB conversion override functionality register + 0x43028 + 0x20 + read-write + 0x00000000 + + + RD_INC_OVERRIDE + RD_INC_OVERRIDE + 0 + 1 + read-write + + + WR_INC_OVERRIDE + WR_INC_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M2_FN_MOD_AHB + AXIMC_M2_FN_MOD_AHB + AXIMC master 2 AHB conversion override functionality register + 0x44028 + 0x20 + read-write + 0x00000000 + + + RD_INC_OVERRIDE + RD_INC_OVERRIDE + 0 + 1 + read-write + + + WR_INC_OVERRIDE + WR_INC_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M5_FN_MOD_AHB + AXIMC_M5_FN_MOD_AHB + AXIMC master 5 AHB conversion override functionality register + 0x45028 + 0x20 + read-write + 0x00000000 + + + RD_INC_OVERRIDE + RD_INC_OVERRIDE + 0 + 1 + read-write + + + WR_INC_OVERRIDE + WR_INC_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_M6_FN_MOD_AHB + AXIMC_M6_FN_MOD_AHB + AXIMC master 6 AHB conversion override functionality register + 0x4D028 + 0x20 + read-write + 0x00000000 + + + RD_INC_OVERRIDE + RD_INC_OVERRIDE + 0 + 1 + read-write + + + WR_INC_OVERRIDE + WR_INC_OVERRIDE + 1 + 1 + read-write + + + + + AXIMC_FN_MOD_LB + AXIMC_FN_MOD_LB + AXIMC long burst capability inhibition register + 0x4A02C + 0x20 + read-write + 0x00000000 + + + FN_MOD_LB + FN_MOD_LB + 0 + 1 + read-write + + + + + + + TZC + TZC + TZC + 0x5C006000 + + 0x0 + 0x1000 + registers + + + TZC_IT + TrustZone DDR address space controller + 4 + + + + TZC_BUILD_CONFIG + TZC_BUILD_CONFIG + Provides information about TZC configuration. + 0x00 + 0x20 + read-only + 0x01001F08 + + + NO_OF_REGIONS + NO_OF_REGIONS + 0 + 5 + read-only + + + ADDRESS_WIDTH + ADDRESS_WIDTH + 8 + 6 + read-only + + + NO_OF_FILTERS + NO_OF_FILTERS + 24 + 2 + read-only + + + + + TZC_ACTION + TZC_ACTION + Controls interrupt and bus error response behavior when regions permission failures occur. + 0x04 + 0x20 + read-write + 0x00000000 + + + REACTION_VALUE + REACTION_VALUE + 0 + 2 + read-write + + + + + TZC_GATE_KEEPER + TZC_GATE_KEEPER + Provides control and status for the gate keeper in each filter unit implemented. + 0x08 + 0x20 + read-write + 0x00000000 + + + OPENREQ + OPENREQ + 0 + 2 + read-write + + + OPENSTAT + OPENSTAT + 16 + 2 + read-only + + + + + TZC_SPECULATION_CTRL + TZC_SPECULATION_CTRL + Controls read and write access speculation. + 0x0C + 0x20 + read-write + 0x00000000 + + + READSPEC_DISABLE + READSPEC_DISABLE + 0 + 1 + read-write + + + WRITESPEC_DISABLE + WRITESPEC_DISABLE + 1 + 1 + read-write + + + + + TZC_INT_STATUS + TZC_INT_STATUS + Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. + 0x10 + 0x20 + read-only + 0x00000000 + + + STATUS + STATUS + 0 + 2 + read-only + + + OVERRUN + OVERRUN + 8 + 2 + read-only + + + OVERLAP + OVERLAP + 16 + 2 + read-only + + + + + TZC_INT_CLEAR + TZC_INT_CLEAR + Interrupt clear for each filter. + 0x14 + 0x20 + read-write + 0x00000000 + + + CLEAR + CLEAR + 0 + 2 + write-only + + + + + TZC_FAIL_CONTROL0 + TZC_FAIL_CONTROL0 + Status information about the first access that failed a region permission check in the associated filter (0 to 1). + 0x28 + 0x20 + read-only + 0x00000000 + + + PRIVILEGE + PRIVILEGE + 20 + 1 + read-only + + + NON_SECURE + NON_SECURE + 21 + 1 + read-only + + + DIRECTION + DIRECTION + 24 + 1 + read-only + + + + + TZC_FAIL_ID0 + TZC_FAIL_ID0 + Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. +AXI ID mapping is described in Table4: NSAID definition table (TBD). + 0x2C + 0x20 + read-only + 0x00000000 + + + ID + ID + 0 + 11 + read-only + + + + + TZC_FAIL_CONTROL1 + TZC_FAIL_CONTROL1 + Status information about the first access that failed a region permission check in the associated filter (0 to 1). + 0x38 + 0x20 + read-only + 0x00000000 + + + PRIVILEGE + PRIVILEGE + 20 + 1 + read-only + + + NON_SECURE + NON_SECURE + 21 + 1 + read-only + + + DIRECTION + DIRECTION + 24 + 1 + read-only + + + + + TZC_FAIL_ID1 + TZC_FAIL_ID1 + Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. +AXI ID mapping is described in Table4: NSAID definition table (TBD). + 0x3C + 0x20 + read-only + 0x00000000 + + + ID + ID + 0 + 11 + read-only + + + + + TZC_REGION_ATTRIBUTE0 + TZC_REGION_ATTRIBUTE0 + Region 0 attributes. + 0x110 + 0x20 + read-write + 0x00000003 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-only + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE1 + TZC_REGION_ATTRIBUTE1 + Region x attributes. + 0x130 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE2 + TZC_REGION_ATTRIBUTE2 + Region x attributes. + 0x150 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE3 + TZC_REGION_ATTRIBUTE3 + Region x attributes. + 0x170 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE4 + TZC_REGION_ATTRIBUTE4 + Region x attributes. + 0x190 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE5 + TZC_REGION_ATTRIBUTE5 + Region x attributes. + 0x1B0 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE6 + TZC_REGION_ATTRIBUTE6 + Region x attributes. + 0x1D0 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE7 + TZC_REGION_ATTRIBUTE7 + Region x attributes. + 0x1F0 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_REGION_ATTRIBUTE8 + TZC_REGION_ATTRIBUTE8 + Region x attributes. + 0x210 + 0x20 + read-write + 0x00000000 + + + FILTER_EN + FILTER_EN + 0 + 2 + read-write + + + S_RD_EN + S_RD_EN + 30 + 1 + read-write + + + S_WR_EN + S_WR_EN + 31 + 1 + read-write + + + + + TZC_PID4 + TZC_PID4 + Peripheral ID 4. + 0xFD0 + 0x20 + read-only + 0x00000004 + + + PER_ID_4 + PER_ID_4 + 0 + 8 + read-only + + + + + TZC_PID5 + TZC_PID5 + Peripheral ID 5. + 0xFD4 + 0x20 + read-only + 0x00000000 + + + PER_ID_5 + PER_ID_5 + 0 + 8 + read-only + + + + + TZC_PID6 + TZC_PID6 + Peripheral ID 6. + 0xFD8 + 0x20 + read-only + 0x00000000 + + + PER_ID_6 + PER_ID_6 + 0 + 8 + read-only + + + + + TZC_PID7 + TZC_PID7 + Peripheral ID 7. + 0xFDC + 0x20 + read-only + 0x00000000 + + + PER_ID_7 + PER_ID_7 + 0 + 8 + read-only + + + + + TZC_PID0 + TZC_PID0 + Peripheral ID 0. + 0xFE0 + 0x20 + read-only + 0x00000060 + + + PER_ID_0 + PER_ID_0 + 0 + 8 + read-only + + + + + TZC_PID1 + TZC_PID1 + Peripheral ID 1. + 0xFE4 + 0x20 + read-only + 0x000000B4 + + + PER_ID_1 + PER_ID_1 + 0 + 8 + read-only + + + + + TZC_PID2 + TZC_PID2 + Peripheral ID 2. + 0xFE8 + 0x20 + read-only + 0x0000002B + + + PER_ID_2 + PER_ID_2 + 0 + 8 + read-only + + + + + TZC_PID3 + TZC_PID3 + Peripheral ID 3. + 0xFEC + 0x20 + read-only + 0x00000000 + + + PER_ID_3 + PER_ID_3 + 0 + 8 + read-only + + + + + TZC_CID0 + TZC_CID0 + Component ID 0. + 0xFF0 + 0x20 + read-only + 0x0000000D + + + COMP_ID_0 + COMP_ID_0 + 0 + 8 + read-only + + + + + TZC_CID1 + TZC_CID1 + Component ID 1. + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + COMP_ID_1 + COMP_ID_1 + 0 + 8 + read-only + + + + + TZC_CID2 + TZC_CID2 + Component ID 2. + 0xFF8 + 0x20 + read-only + 0x00000005 + + + COMP_ID_2 + COMP_ID_2 + 0 + 8 + read-only + + + + + TZC_CID3 + TZC_CID3 + Component ID 3. + 0xFFC + 0x20 + read-only + 0x000000B1 + + + COMP_ID_3 + COMP_ID_3 + 0 + 8 + read-only + + + + + TZC_FAIL_ADDRESS_LOW0 + TZC_FAIL_ADDRESS_LOW0 + Address low bits of the first failed access in the associated filter (0 to 1). + 0x20 + 0x20 + read-only + 0x00000000 + + + ADDR_STATUS_LOW + ADDR_STATUS_LOW + 0 + 32 + read-only + + + + + TZC_FAIL_ADDRESS_HIGH0 + TZC_FAIL_ADDRESS_HIGH0 + Address high bit of the first failed access in the associated filter (0 to 1). +Not used with 32bit address. + 0x24 + 0x20 + read-only + 0x00000000 + + + + TZC_FAIL_ADDRESS_LOW1 + TZC_FAIL_ADDRESS_LOW1 + Address low bits of the first failed access in the associated filter (0 to 1). + 0x30 + 0x20 + read-only + 0x00000000 + + + ADDR_STATUS_LOW + ADDR_STATUS_LOW + 0 + 32 + read-only + + + + + TZC_FAIL_ADDRESS_HIGH1 + TZC_FAIL_ADDRESS_HIGH1 + Address high bit of the first failed access in the associated filter (0 to 1). +Not used with 32bit address. + 0x34 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_BASE_HIGH0 + TZC_REGION_BASE_HIGH0 + Base address high are not used with 32-bit address. + 0x104 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW0 + TZC_REGION_TOP_LOW0 + Top address bits [31:12] for region 0. + 0x108 + 0x20 + read-only + 0xFFFFFFFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-only + + + + + TZC_REGION_TOP_HIGH0 + TZC_REGION_TOP_HIGH0 + Top address high of region are not used with 32-bit address. + 0x10C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS0 + TZC_REGION_ID_ACCESS0 + Region non-secure access based on NSAID. + 0x114 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW1 + TZC_REGION_BASE_LOW1 + Base address low for regions 1 to 8. + 0x120 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH1 + TZC_REGION_BASE_HIGH1 + Base address high are not used with 32-bit address. + 0x124 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW1 + TZC_REGION_TOP_LOW1 + Top address bits [31:12] for region x. + 0x128 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH1 + TZC_REGION_TOP_HIGH1 + Top address high of region are not used with 32-bit address. + 0x12C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS1 + TZC_REGION_ID_ACCESS1 + Region non-secure access based on NSAID. + 0x134 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW2 + TZC_REGION_BASE_LOW2 + Base address low for regions 1 to 8. + 0x140 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH2 + TZC_REGION_BASE_HIGH2 + Base address high are not used with 32-bit address. + 0x144 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW2 + TZC_REGION_TOP_LOW2 + Top address bits [31:12] for region x. + 0x148 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH2 + TZC_REGION_TOP_HIGH2 + Top address high of region are not used with 32-bit address. + 0x14C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS2 + TZC_REGION_ID_ACCESS2 + Region non-secure access based on NSAID. + 0x154 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW3 + TZC_REGION_BASE_LOW3 + Base address low for regions 1 to 8. + 0x160 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH3 + TZC_REGION_BASE_HIGH3 + Base address high are not used with 32-bit address. + 0x164 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW3 + TZC_REGION_TOP_LOW3 + Top address bits [31:12] for region x. + 0x168 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH3 + TZC_REGION_TOP_HIGH3 + Top address high of region are not used with 32-bit address. + 0x16C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS3 + TZC_REGION_ID_ACCESS3 + Region non-secure access based on NSAID. + 0x174 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW4 + TZC_REGION_BASE_LOW4 + Base address low for regions 1 to 8. + 0x180 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH4 + TZC_REGION_BASE_HIGH4 + Base address high are not used with 32-bit address. + 0x184 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW4 + TZC_REGION_TOP_LOW4 + Top address bits [31:12] for region x. + 0x188 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH4 + TZC_REGION_TOP_HIGH4 + Top address high of region are not used with 32-bit address. + 0x18C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS4 + TZC_REGION_ID_ACCESS4 + Region non-secure access based on NSAID. + 0x194 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW5 + TZC_REGION_BASE_LOW5 + Base address low for regions 1 to 8. + 0x1A0 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH5 + TZC_REGION_BASE_HIGH5 + Base address high are not used with 32-bit address. + 0x1A4 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW5 + TZC_REGION_TOP_LOW5 + Top address bits [31:12] for region x. + 0x1A8 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH5 + TZC_REGION_TOP_HIGH5 + Top address high of region are not used with 32-bit address. + 0x1AC + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS5 + TZC_REGION_ID_ACCESS5 + Region non-secure access based on NSAID. + 0x1B4 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW6 + TZC_REGION_BASE_LOW6 + Base address low for regions 1 to 8. + 0x1C0 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH6 + TZC_REGION_BASE_HIGH6 + Base address high are not used with 32-bit address. + 0x1C4 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW6 + TZC_REGION_TOP_LOW6 + Top address bits [31:12] for region x. + 0x1C8 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH6 + TZC_REGION_TOP_HIGH6 + Top address high of region are not used with 32-bit address. + 0x1CC + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS6 + TZC_REGION_ID_ACCESS6 + Region non-secure access based on NSAID. + 0x1D4 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW7 + TZC_REGION_BASE_LOW7 + Base address low for regions 1 to 8. + 0x2E0 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH7 + TZC_REGION_BASE_HIGH7 + Base address high are not used with 32-bit address. + 0x2E4 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW7 + TZC_REGION_TOP_LOW7 + Top address bits [31:12] for region x. + 0x1E8 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH7 + TZC_REGION_TOP_HIGH7 + Top address high of region are not used with 32-bit address. + 0x2EC + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS7 + TZC_REGION_ID_ACCESS7 + Region non-secure access based on NSAID. + 0x2F4 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + TZC_REGION_BASE_LOW8 + TZC_REGION_BASE_LOW8 + Base address low for regions 1 to 8. + 0x200 + 0x20 + read-write + 0x00000000 + + + BASE_ADDRESS_LOW + BASE_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_BASE_HIGH8 + TZC_REGION_BASE_HIGH8 + Base address high are not used with 32-bit address. + 0x204 + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_TOP_LOW8 + TZC_REGION_TOP_LOW8 + Top address bits [31:12] for region x. + 0x308 + 0x20 + read-write + 0x00000FFF + + + TOP_ADDRESS_LOW + TOP_ADDRESS_LOW + 12 + 20 + read-write + + + + + TZC_REGION_TOP_HIGH8 + TZC_REGION_TOP_HIGH8 + Top address high of region are not used with 32-bit address. + 0x30C + 0x20 + read-only + 0x00000000 + + + + TZC_REGION_ID_ACCESS8 + TZC_REGION_ID_ACCESS8 + Region non-secure access based on NSAID. + 0x314 + 0x20 + read-write + 0x00000000 + + + NSAID_RD_EN + NSAID_RD_EN + 0 + 16 + read-write + + + NSAID_WR_EN + NSAID_WR_EN + 16 + 16 + read-write + + + + + + + + TIM15 + TIM15 + TIMER + 0x44006000 + + 0x0 + 0x400 + registers + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 0x10 + read-write + 0x0000 + + + CEN + CEN + 0 + 1 + read-write + + + UDIS + UDIS + 1 + 1 + read-write + + + URS + URS + 2 + 1 + read-write + + + OPM + OPM + 3 + 1 + read-write + + + ARPE + ARPE + 7 + 1 + read-write + + + CKD + CKD + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP + 11 + 1 + read-write + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 0x10 + read-write + 0x0000 + + + CCPC + CCPC + 0 + 1 + read-write + + + CCUS + CCUS + 2 + 1 + read-write + + + CCDS + CCDS + 3 + 1 + read-write + + + MMS + MMS + 4 + 3 + read-write + + + TI1S + TI1S + 7 + 1 + read-write + + + OIS1 + OIS1 + 8 + 1 + read-write + + + OIS1N + OIS1N + 9 + 1 + read-write + + + OIS2 + OIS2 + 10 + 1 + read-write + + + + + TIMx_SMCR + TIMx_SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + TS_4_3 + Trigger selection + 20 + 2 + + + SMS_3 + Slave mode selection - bit + 3 + 16 + 1 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable + register + 0x0C + 0x10 + read-write + 0x0000 + + + UIE + UIE + 0 + 1 + read-write + + + CC1IE + CC1IE + 1 + 1 + read-write + + + CC2IE + CC2IE + 2 + 1 + read-write + + + COMIE + COMIE + 5 + 1 + read-write + + + TIE + TIE + 6 + 1 + read-write + + + BIE + BIE + 7 + 1 + read-write + + + UDE + UDE + 8 + 1 + read-write + + + CC1DE + CC1DE + 9 + 1 + read-write + + + CC2DE + CC2DE + 10 + 1 + read-write + + + COMDE + COMDE + 13 + 1 + read-write + + + TDE + TDE + 14 + 1 + read-write + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 0x10 + read-write + 0x0000 + + + UIF + UIF + 0 + 1 + read-write + + + CC1IF + CC1IF + 1 + 1 + read-write + + + CC2IF + CC2IF + 2 + 1 + read-write + + + COMIF + COMIF + 5 + 1 + read-write + + + TIF + TIF + 6 + 1 + read-write + + + BIF + BIF + 7 + 1 + read-write + + + CC1OF + CC1OF + 9 + 1 + read-write + + + CC2OF + CC2OF + 10 + 1 + read-write + + + + + TIMx_EGR + TIMx_EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + BG + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + COMG + 5 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + TIMx_CCMR1_Output + TIMx_CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit + 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit + 3 + 16 + 1 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + TIMx_CCMR1_Input + TIMx_CCMR1_Input + capture/compare mode register 1 (input + mode) + TIMx_CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable + register + 0x20 + 0x10 + read-write + 0x0000 + + + CC1E + CC1E + 0 + 1 + read-write + + + CC1P + CC1P + 1 + 1 + read-write + + + CC1NE + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP + 3 + 1 + read-write + + + CC2E + CC2E + 4 + 1 + read-write + + + CC2P + CC2P + 5 + 1 + read-write + + + CC2NP + CC2NP + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + PSC + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 0x10 + read-write + 0xFFFF + + + ARR + ARR + 0 + 16 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter + register + 0x30 + 0x10 + read-write + 0x0000 + + + REP + REP + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register + 1 + 0x34 + 0x10 + read-write + 0x0000 + + + CCR1 + CCR1 + 0 + 16 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register + 2 + 0x38 + 0x10 + read-write + 0x0000 + + + CCR2 + CCR2 + 0 + 16 + read-write + + + + + TIMx_BDTR + TIMx_BDTR + As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, + BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, + OSSR and DTG[7:0] can be write-locked depending on the + LOCK configuration, it can be necessary to configure all + of them during the first write access to the TIMx_BDTR + register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + read-write + + + LOCK + LOCK + 8 + 2 + read-write + + + OSSI + OSSI + 10 + 1 + read-write + + + OSSR + OSSR + 11 + 1 + read-write + + + BKE + BKE + 12 + 1 + read-write + + + BKP + BKP + 13 + 1 + read-write + + + AOE + AOE + 14 + 1 + read-write + + + MOE + MOE + 15 + 1 + read-write + + + BKF + BKF + 16 + 4 + read-write + + + BKDSRM + BKDSRM + 26 + 1 + read-write + + + BKBID + BKBID + 28 + 1 + read-write + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x48 + 0x10 + read-write + 0x0000 + + + DBA + DBA + 0 + 5 + read-write + + + DBL + DBL + 8 + 5 + read-write + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full + transfer + 0x4C + 0x10 + read-write + 0x0000 + + + DMAB + DMAB + 0 + 16 + read-write + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + read-write + + + BKDF1BK0E + BKDF1BK0E + 8 + 1 + read-write + + + BKINP + BKINP + 9 + 1 + read-write + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + read-write + + + TI2SEL + TI2SEL + 8 + 4 + read-write + + + + + + + TIM16 + TIM16 + TIMER + 0x44007000 + + 0x0 + 0x400 + registers + + + + TIMx_CR1 + TIMx_CR1 + TIM16/TIM17 control register 1 + 0x00 + 0x10 + read-write + 0x0000 + + + CEN + CEN + 0 + 1 + read-write + + + UDIS + UDIS + 1 + 1 + read-write + + + URS + URS + 2 + 1 + read-write + + + OPM + OPM + 3 + 1 + read-write + + + ARPE + ARPE + 7 + 1 + read-write + + + CKD + CKD + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP + 11 + 1 + read-write + + + + + TIMx_CR2 + TIMx_CR2 + TIM16/TIM17 control register 2 + 0x04 + 0x10 + read-write + 0x0000 + + + CCPC + CCPC + 0 + 1 + read-write + + + CCUS + CCUS + 2 + 1 + read-write + + + CCDS + CCDS + 3 + 1 + read-write + + + OIS1 + OIS1 + 8 + 1 + read-write + + + OIS1N + OIS1N + 9 + 1 + read-write + + + + + TIMx_DIER + TIMx_DIER + TIM16/TIM17 DMA/interrupt enable + register + 0x0C + 0x10 + read-write + 0x0000 + + + UIE + UIE + 0 + 1 + read-write + + + CC1IE + CC1IE + 1 + 1 + read-write + + + COMIE + COMIE + 5 + 1 + read-write + + + BIE + BIE + 7 + 1 + read-write + + + UDE + UDE + 8 + 1 + read-write + + + CC1DE + CC1DE + 9 + 1 + read-write + + + COMDE + COMDE + 13 + 1 + read-write + + + + + TIMx_SR + TIMx_SR + TIM16/TIM17 status register + 0x10 + 0x10 + read-write + 0x0000 + + + UIF + UIF + 0 + 1 + read-write + + + CC1IF + CC1IF + 1 + 1 + read-write + + + COMIF + COMIF + 5 + 1 + read-write + + + BIF + BIF + 7 + 1 + read-write + + + CC1OF + CC1OF + 9 + 1 + read-write + + + + + TIMx_EGR + TIMx_EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + TIMx_CCER + TIMx_CCER + TIM16/TIM17 capture/compare enable + register + 0x20 + 0x10 + read-write + 0x0000 + + + CC1E + CC1E + 0 + 1 + read-write + + + CC1P + CC1P + 1 + 1 + read-write + + + CC1NE + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP + 3 + 1 + read-write + + + + + TIMx_CNT + TIMx_CNT + TIM16/TIM17 counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT + 0 + 16 + read-write + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + + + TIMx_PSC + TIMx_PSC + TIM16/TIM17 prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + PSC + 0 + 16 + read-write + + + + + TIMx_ARR + TIMx_ARR + TIM16/TIM17 auto-reload + register + 0x2C + 0x10 + read-write + 0xFFFF + + + ARR + ARR + 0 + 16 + read-write + + + + + TIMx_RCR + TIMx_RCR + TIM16/TIM17 repetition counter + register + 0x30 + 0x10 + read-write + 0x0000 + + + REP + REP + 0 + 8 + read-write + + + + + TIMx_CCR1 + TIMx_CCR1 + TIM16/TIM17 capture/compare register + 1 + 0x34 + 0x10 + read-write + 0x0000 + + + CCR1 + CCR1 + 0 + 16 + read-write + + + + + TIMx_BDTR + TIMx_BDTR + As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, + BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked + depending on the LOCK configuration, it may be necessary + to configure all of them during the first write access to + the TIMx_BDTR register. + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG + 0 + 8 + read-write + + + LOCK + LOCK + 8 + 2 + read-write + + + OSSI + OSSI + 10 + 1 + read-write + + + OSSR + OSSR + 11 + 1 + read-write + + + BKE + BKE + 12 + 1 + read-write + + + BKP + BKP + 13 + 1 + read-write + + + AOE + AOE + 14 + 1 + read-write + + + MOE + MOE + 15 + 1 + read-write + + + BKF + BKF + 16 + 4 + read-write + + + BKDSRM + BKDSRM + 26 + 1 + read-write + + + BKBID + BKBID + 28 + 1 + read-write + + + + + TIMx_DCR + TIMx_DCR + TIM16/TIM17 DMA control + register + 0x48 + 0x10 + read-write + 0x0000 + + + DBA + DBA + 0 + 5 + read-write + + + DBL + DBL + 8 + 5 + read-write + + + + + TIMx_DMAR + TIMx_DMAR + TIM16/TIM17 DMA address for full + transfer + 0x4C + 0x10 + read-write + 0x0000 + + + DMAB + DMAB + 0 + 16 + read-write + + + + + TIMx_AF1 + TIM17_AF1 + TIM17 alternate function register + 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BKINE + 0 + 1 + read-write + + + BKDF1BK2E + BKDF1BK2E + 8 + 1 + read-write + + + BKINP + BKINP + 9 + 1 + read-write + + + + + TIMx_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1SEL + 0 + 4 + read-write + + + + + + + TIM17 + 0x44008000 + + + DLYBQS + DLYBQS + DLYB + 0x58004000 + + 0x0 + 0x1000 + registers + + + + DLYB_CR + DLYB_CR + DLYB control register + 0x00 + 0x20 + read-write + 0x00000000 + + + DEN + DEN + 0 + 1 + read-write + + + SEN + SEN + 1 + 1 + read-write + + + + + DLYB_CFGR + DLYB_CFGR + DLYB configuration register + 0x04 + 0x20 + read-write + 0x00000000 + + + SEL + SEL + 0 + 4 + read-write + + + UNIT + UNIT + 8 + 7 + read-write + + + LNG + LNG + 16 + 12 + read-only + + + LNGF + LNGF + 31 + 1 + read-only + + + + + DLYB_VERR + DLYB_VERR + DLYB IP version register + 0x3F4 + 0x20 + read-only + 0x00000011 + + + MINREV + MINREV + 0 + 4 + read-only + + + MAJREV + MAJREV + 4 + 4 + read-only + + + + + DLYB_IPIDR + DLYB_IPIDR + DLYB IP identification + register + 0x3F8 + 0x20 + read-only + 0x00140051 + + + ID + ID + 0 + 32 + read-only + + + + + DLYB_SIDR + DLYB_SIDR + DLYB size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + SID + 0 + 32 + read-only + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x401 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER3 + ICER3 + Interrupt Clear-Enable + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR3 + ICPR3 + Interrupt Clear-Pending + Register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR26 + IPR26 + Interrupt Priority Register + 0x368 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR27 + IPR27 + Interrupt Priority Register + 0x36C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR28 + IPR28 + Interrupt Priority Register + 0x370 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR29 + IPR29 + Interrupt Priority Register + 0x374 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR30 + IPR30 + Interrupt Priority Register + 0x378 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR31 + IPR31 + Interrupt Priority Register + 0x37C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR32 + IPR32 + Interrupt Priority Register + 0x380 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR33 + IPR33 + Interrupt Priority Register + 0x384 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR34 + IPR34 + Interrupt Priority Register + 0x388 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR35 + IPR35 + Interrupt Priority Register + 0x38C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR36 + IPR36 + Interrupt Priority Register + 0x390 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR37 + IPR37 + Interrupt Priority Register + 0x394 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR38 + IPR38 + Interrupt Priority Register + 0x398 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + ISER4 + ISER4 + Interrupt Set-Enable Register + 0x10 + 0x20 + read-write + 0x00000000 + + + ICER4 + ICER4 + Interrupt Clear-Enable + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + ISPR4 + ISPR4 + Interrupt Set-Pending Register + 0x110 + 0x20 + read-write + 0x00000000 + + + ICPR4 + ICPR4 + Interrupt Clear-Pending + Register + 0x1C4 + 0x20 + read-write + 0x00000000 + + + IABR4 + IABR4 + Interrupt Active Bit Register + 0x210 + 0x20 + read-write + 0x00000000 + + + + + diff --git a/recipes-devtools/cmsis-svd/cmsis-svd_git.bb b/recipes-devtools/cmsis-svd/cmsis-svd_git.bb index 92a1293..8c90551 100644 --- a/recipes-devtools/cmsis-svd/cmsis-svd_git.bb +++ b/recipes-devtools/cmsis-svd/cmsis-svd_git.bb @@ -7,10 +7,10 @@ LIC_FILES_CHKSUM = "\ file://data/STMicro/License.html;md5=9a2821012ac32bea060eccbc76512bdb \ file://data/Freescale/Freescale%20CMSIS-SVD%20License%20Agreement.pdf;md5=33928757d8c2861dc9256ce344d11db3 \ file://data/Fujitsu/License.html;md5=e630487a365e7e0c5e03afcc644ce0ad \ - file://data/Atmel/License.html;md5=466a7215aa18f98886ba2c15dba6b35a \ + file://data/Atmel/LICENSE;md5=c4400c3a321c71218e903363e6f28890 \ " -NO_GENERIC_LICENSE[svd-Atmel] = "data/Atmel/License.html" +NO_GENERIC_LICENSE[svd-Atmel] = "data/Atmel/LICENSE" NO_GENERIC_LICENSE[svd-Freescale] = "data/Freescale/Freescale CMSIS-SVD License Agreement.pdf" NO_GENERIC_LICENSE[svd-Fujitsu] = "data/Fujitsu/License.html" NO_GENERIC_LICENSE[svd-STMicro] = "data/STMicro/License.html" @@ -18,7 +18,7 @@ NO_GENERIC_LICENSE[svd-STMicro] = "data/STMicro/License.html" inherit pkgconfig autotools-brokensep gettext SRC_URI = "git://github.com/posborne/cmsis-svd.git;protocol=https;branch=master" -SRCREV = "2ab163c2aea83eb9b39c163856450089255ce4f2" +SRCREV = "f487b5ca7c132b8f09d11514c509372f83a6cb75" PV = "0.4+git${SRCPV}" @@ -101,7 +101,7 @@ RDEPENDS:${PN}-parser += "python3-xml" LICENSE:${PN}-data-atmel = "svd-Atmel" LICENSE:${PN}-atmel-license = "svd-Atmel" -FILES:${PN}-atmel-license = "${INSTALL_PATH}/data/Atmel/License.html" +FILES:${PN}-atmel-license = "${INSTALL_PATH}/data/Atmel/LICENSE" FILES:${PN}-data-atmel = "${INSTALL_PATH}/data/Atmel/*.svd" RDEPENDS:${PN}-data-atmel += "${PN}-atmel-license" diff --git a/recipes-devtools/cmsis-svd/cmsis-svd_git.bbappend b/recipes-devtools/cmsis-svd/cmsis-svd_git.bbappend index fdb6478..12ba6dd 100644 --- a/recipes-devtools/cmsis-svd/cmsis-svd_git.bbappend +++ b/recipes-devtools/cmsis-svd/cmsis-svd_git.bbappend @@ -1,4 +1,7 @@ # Add stm32mp1 support -SRC_URI:append:stm32mpcommon = " file://0001-data-STMicro-add-support-of-stm32mp15xxx.patch" +SRC_URI:append:stm32mpcommon = " file://STM32MP13xx.svd;subdir=git/data/STMicro" +SRC_URI:append:stm32mpcommon = " file://STM32MP15xxx.svd;subdir=git/data/STMicro" + # Add the same for nativesdk -SRC_URI:append:class-nativesdk = " file://0001-data-STMicro-add-support-of-stm32mp15xxx.patch" +SRC_URI:append:class-nativesdk = " file://STM32MP13xx.svd;subdir=git/data/STMicro" +SRC_URI:append:class-nativesdk = " file://STM32MP15xxx.svd;subdir=git/data/STMicro"