OPENOCD: Support single core and fixes
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
This commit is contained in:
Christophe Priouzeau
parent
8efdfc6932
commit
48d2c10203
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@ -0,0 +1,251 @@
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From b411d805477bd67856403c73bad41534bcf2aa31 Mon Sep 17 00:00:00 2001
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From: Antonio Borneo <antonio.borneo@st.com>
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Date: Mon, 20 May 2019 17:25:18 +0200
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Subject: [PATCH] Support single-core, align access with mmu off, plus fixes
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---
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src/target/adi_v5_stlink.c | 12 --------
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src/target/cortex_a.c | 43 ++++++++++++++++++++++++++---
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src/target/cortex_m.c | 8 +++---
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tcl/target/stm32mp15x.cfg | 56 ++++++++++++++++++++++++++++----------
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4 files changed, 84 insertions(+), 35 deletions(-)
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diff --git a/src/target/adi_v5_stlink.c b/src/target/adi_v5_stlink.c
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index 9e7ab0f64..fd4a4e28a 100644
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--- a/src/target/adi_v5_stlink.c
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+++ b/src/target/adi_v5_stlink.c
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@@ -120,18 +120,6 @@ static int stlink_connect(struct adiv5_dap *dap)
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LOG_INFO("stlink_connect(%sconnect)", dap->do_reconnect ? "re" : "");
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- /* Check if we should reset srst already when connecting, but not if reconnecting. */
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- if (!dap->do_reconnect) {
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- enum reset_types jtag_reset_config = jtag_get_reset_config();
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-
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- if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
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- if (jtag_reset_config & RESET_SRST_NO_GATING)
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- adapter_assert_reset();
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- else
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- LOG_WARNING("\'srst_nogate\' reset_config option is required");
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- }
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- }
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-
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dap->do_reconnect = false;
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dap_invalidate_cache(dap);
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diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
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index 499dacc9b..9f6f3d5d2 100644
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--- a/src/target/cortex_a.c
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+++ b/src/target/cortex_a.c
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@@ -1220,6 +1220,8 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
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retval = cortex_a_poll(target);
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if (retval != ERROR_OK)
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return retval;
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+ if (target->state == TARGET_HALTED)
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+ break;
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if (timeval_ms() > then + 1000) {
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LOG_ERROR("timeout waiting for target halt");
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return ERROR_FAIL;
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@@ -2017,7 +2019,8 @@ static int cortex_a_write_cpu_memory_slow(struct target *target,
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{
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/* Writes count objects of size size from *buffer. Old value of DSCR must
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* be in *dscr; updated to new value. This is slow because it works for
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- * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
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+ * non-word-sized objects. Avoid unaligned accesses as they do not work
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+ * on memory address space without "Normal" attribute. If size == 4 and
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* the address is aligned, cortex_a_write_cpu_memory_fast should be
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* preferred.
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* Preconditions:
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@@ -2174,7 +2177,22 @@ static int cortex_a_write_cpu_memory(struct target *target,
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/* We are doing a word-aligned transfer, so use fast mode. */
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retval = cortex_a_write_cpu_memory_fast(target, count, buffer, &dscr);
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} else {
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- /* Use slow path. */
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+ /* Use slow path. Adjust size for aligned accesses */
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+ switch (address % 4) {
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+ case 1:
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+ case 3:
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+ count *= size;
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+ size = 1;
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+ break;
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+ case 2:
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+ if (size == 4) {
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+ count *= 2;
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+ size = 2;
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+ }
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+ case 0:
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+ default:
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+ break;
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+ }
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retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
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}
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@@ -2260,7 +2278,8 @@ static int cortex_a_read_cpu_memory_slow(struct target *target,
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{
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/* Reads count objects of size size into *buffer. Old value of DSCR must be
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* in *dscr; updated to new value. This is slow because it works for
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- * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
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+ * non-word-sized objects. Avoid unaligned accesses as they do not work
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+ * on memory address space without "Normal" attribute. If size == 4 and
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* the address is aligned, cortex_a_read_cpu_memory_fast should be
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* preferred.
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* Preconditions:
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@@ -2476,7 +2495,23 @@ static int cortex_a_read_cpu_memory(struct target *target,
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/* We are doing a word-aligned transfer, so use fast mode. */
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retval = cortex_a_read_cpu_memory_fast(target, count, buffer, &dscr);
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} else {
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- /* Use slow path. */
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+ /* Use slow path. Adjust size for aligned accesses */
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+ switch (address % 4) {
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+ case 1:
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+ case 3:
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+ count *= size;
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+ size = 1;
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+ break;
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+ case 2:
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+ if (size == 4) {
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+ count *= 2;
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+ size = 2;
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+ }
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+ break;
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+ case 0:
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+ default:
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+ break;
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+ }
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retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
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}
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diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
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index 79975aa89..9b962192f 100644
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--- a/src/target/cortex_m.c
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+++ b/src/target/cortex_m.c
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@@ -532,21 +532,21 @@ static int cortex_m_poll(struct target *target)
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if (cortex_m->dcb_dhcsr & S_HALT) {
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target->state = TARGET_HALTED;
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- if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
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+ if (prev_target_state != TARGET_HALTED) {
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retval = cortex_m_debug_entry(target);
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if (retval != ERROR_OK)
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return retval;
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+ }
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+ if (prev_target_state == TARGET_RUNNING || prev_target_state == TARGET_RESET) {
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if (arm_semihosting(target, &retval) != 0)
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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+
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if (prev_target_state == TARGET_DEBUG_RUNNING) {
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LOG_DEBUG(" ");
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- retval = cortex_m_debug_entry(target);
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- if (retval != ERROR_OK)
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- return retval;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
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}
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diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
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index 992975f87..f95070c3c 100644
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--- a/tcl/target/stm32mp15x.cfg
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+++ b/tcl/target/stm32mp15x.cfg
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@@ -54,8 +54,10 @@ proc cti_prepare_restart_all {} {
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global _CHIPNAME
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cti_prepare_restart cti0
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- cti_prepare_restart cti1
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- if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
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+ if { [$_CHIPNAME.cpu1 was_examined] } {
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+ cti_prepare_restart cti1
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+ }
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+ if { [$_CHIPNAME.cpu2 was_examined] } {
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cti_prepare_restart cti2
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}
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}
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@@ -71,22 +73,22 @@ proc cti_prepare_restart {cti} {
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proc cti_start {} {
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global _CHIPNAME
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- # Configure both Cortex-A CTIs to halt each other
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+ # Configure CTIs to halt the other cores
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# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
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$_CHIPNAME.cti0 write INEN0 0x1
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- $_CHIPNAME.cti1 write INEN0 0x1
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$_CHIPNAME.cti0 write OUTEN0 0x1
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- $_CHIPNAME.cti1 write OUTEN0 0x1
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-
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- $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
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- $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
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-
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- # enable CTIs
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+ $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
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$_CHIPNAME.cti0 enable on
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- $_CHIPNAME.cti1 enable on
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+
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+ if { [$_CHIPNAME.cpu1 was_examined] } {
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+ $_CHIPNAME.cti1 write INEN0 0x1
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+ $_CHIPNAME.cti1 write OUTEN0 0x1
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+ $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
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+ $_CHIPNAME.cti1 enable on
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+ }
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# Cortex-M4 CTI configuration (enable CM4.CTI and join same CTM channels)
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- if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
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+ if { [$_CHIPNAME.cpu2 was_examined] } {
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$_CHIPNAME.cti2 write INEN0 0x1
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$_CHIPNAME.cti2 write OUTEN0 0x1
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$_CHIPNAME.cpu2 configure -event halted { cti_prepare_restart_all }
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@@ -98,8 +100,9 @@ proc cti_stop {} {
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global _CHIPNAME
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$_CHIPNAME.cti0 enable off
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- $_CHIPNAME.cti1 enable off
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-
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+ if { [$_CHIPNAME.cpu1 was_examined] } {
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+ $_CHIPNAME.cti1 enable off
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+ }
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if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
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$_CHIPNAME.cti2 enable off
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}
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@@ -111,7 +114,7 @@ cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
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cti create $_CHIPNAME.cti2 -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
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target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0xE00D0000
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-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000
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+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000 -defer-examine
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target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
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target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
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@@ -228,6 +231,29 @@ adapter_khz $_CLOCK_FREQ
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adapter_nsrst_assert_width 200
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adapter_nsrst_delay 200
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+$_CHIPNAME.ap1 configure -event examine-end {
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+ global _CHIPNAME
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+
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+ # only on dual-cores chips, examine the second core
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+ $_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
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+ if {$cpu1_prsr(0) & 1} {
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+ $_CHIPNAME.cpu1 invoke-event examine-start
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+ set err [catch "$_CHIPNAME.cpu1 arp_examine"]
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+ if { $err } {
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+ $_CHIPNAME.cpu1 invoke-event examine-fail
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+ } else {
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+ $_CHIPNAME.cpu1 invoke-event examine-end
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+ }
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+ }
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+}
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+
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+$_CHIPNAME.cpu1 configure -event examine-end {
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+ global _CHIPNAME
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+
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+ if {[$_CHIPNAME.cpu1 was_examined] && [$_CHIPNAME.cpu0 curstate] eq "halted"} {
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+ halt
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+ }
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+}
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set clients_num 0
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proc clients_inc {} {
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--
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2.21.0
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@ -18,3 +18,4 @@ SRC_URI += "file://0002-Add-support-for-silicon-revB.patch"
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SRC_URI += "file://0003-Align-to-community-code-for-cache-coherency-and-rese.patch"
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SRC_URI += "file://0003-Align-to-community-code-for-cache-coherency-and-rese.patch"
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SRC_URI += "file://0004-Fix-init-command.patch"
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SRC_URI += "file://0004-Fix-init-command.patch"
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SRC_URI += "file://0005-Add-CTI-plus-fixes.patch"
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SRC_URI += "file://0005-Add-CTI-plus-fixes.patch"
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SRC_URI += "file://0006-Support-single-core-align-access-with-mmu-off-plus-f.patch"
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