diff --git a/recipes-bsp/trusted-firmware-a/tf-a-stm32mp-common.inc b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp-common.inc
index 56d76fd..e95cf2c 100644
--- a/recipes-bsp/trusted-firmware-a/tf-a-stm32mp-common.inc
+++ b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp-common.inc
@@ -11,11 +11,12 @@ SRCREV = "a1f02f4f3daae7e21ee58b4c93ec3e46b8f28d15"
 SRC_URI += " \
     file://0001-v2.6-stm32mp-r1.patch \
     file://0002-v2.6-stm32mp-r2.patch \
+    file://0003-v2.6-stm32mp-r2.1.patch\
     "
 
 TF_A_VERSION = "v2.6"
 TF_A_SUBVERSION = "stm32mp"
-TF_A_RELEASE = "r2"
+TF_A_RELEASE = "r2.1"
 PV = "${TF_A_VERSION}-${TF_A_SUBVERSION}-${TF_A_RELEASE}"
 
 ARCHIVER_ST_BRANCH = "${TF_A_VERSION}-${TF_A_SUBVERSION}"
@@ -31,7 +32,7 @@ S = "${WORKDIR}/git"
 BBCLASSEXTEND = "devupstream:target"
 
 SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/arm-trusted-firmware.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
-SRCREV:class-devupstream = "4b6e8e9bf8fa676ff8d1358ea2cf2e44904c2473"
+SRCREV:class-devupstream = "aa1e9e2db80e49ed0259757a0f09ff119725409d"
 
 # ---------------------------------
 # Configure default preference to manage dynamic selection between tarball and github
diff --git a/recipes-bsp/trusted-firmware-a/tf-a-stm32mp.inc b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp.inc
index c968d62..cfa5d82 100644
--- a/recipes-bsp/trusted-firmware-a/tf-a-stm32mp.inc
+++ b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp.inc
@@ -92,7 +92,7 @@ TF_A_SIGN_ENABLE ??= "0"
 TF_A_ENCRYPTED_ENABLE ??= "0"
 
 # Set metadata generation
-TF_A_ENABLE_METADATA ??= "${@bb.utils.contains('MACHINE_FEATURES', 'fw-update', '1', '0', 'd')}"
+TF_A_ENABLE_METADATA ??= "${@bb.utils.contains('MACHINE_FEATURES', 'fw-update', '1', '0', d)}"
 TF_A_METADATA_NAME ?= "metadata"
 TF_A_METADATA_SUFFIX ?= "bin"
 TF_A_METADATA_BINARY ??= "${TF_A_METADATA_NAME}.${TF_A_METADATA_SUFFIX}"
diff --git a/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-v2.6-stm32mp-r2.1.patch b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-v2.6-stm32mp-r2.1.patch
new file mode 100644
index 0000000..e759fd1
--- /dev/null
+++ b/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-v2.6-stm32mp-r2.1.patch
@@ -0,0 +1,582 @@
+From 26924c80204083a5184a425f534e39fbc5d97484 Mon Sep 17 00:00:00 2001
+From: Lionel VITTE <lionel.vitte@st.com>
+Date: Mon, 3 Jul 2023 10:24:57 +0200
+Subject: [PATCH] v2.6-stm32mp-r2.1-rc1
+
+---
+ drivers/mtd/nand/spi_nand.c                   |  3 +-
+ drivers/st/bsec/bsec2.c                       | 17 ----------
+ drivers/st/uart/aarch32/stm32_console.S       |  9 ++++--
+ fdts/stm32mp15-bl2.dtsi                       |  1 -
+ fdts/stm32mp15-bl32.dtsi                      |  1 -
+ include/drivers/spi_nand.h                    |  4 +++
+ include/drivers/st/bsec.h                     |  1 -
+ include/drivers/st/bsec2_reg.h                |  1 -
+ plat/st/common/stm32cubeprogrammer_uart.c     |  9 +++++-
+ plat/st/stm32mp1/include/stm32mp1_private.h   |  4 ++-
+ plat/st/stm32mp1/plat_def_uuid_config.c       | 11 +++++--
+ plat/st/stm32mp1/platform.mk                  |  2 +-
+ plat/st/stm32mp1/stm32mp1_context.c           | 28 +++++++++++++++-
+ .../stm32mp1/stm32mp1_critic_power_wrapper.S  |  9 +-----
+ plat/st/stm32mp1/stm32mp1_def.h               | 11 +++++--
+ plat/st/stm32mp1/stm32mp1_low_power.c         | 22 ++++++-------
+ plat/st/stm32mp1/stm32mp1_pm.c                |  6 ++--
+ plat/st/stm32mp1/stm32mp1_private.c           | 32 ++++++++++++++++++-
+ plat/st/stm32mp1/stm32mp1_ssp.c               |  5 ++-
+ 19 files changed, 119 insertions(+), 57 deletions(-)
+
+diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c
+index abb524d7f..a18b06f58 100644
+--- a/drivers/mtd/nand/spi_nand.c
++++ b/drivers/mtd/nand/spi_nand.c
+@@ -17,7 +17,6 @@
+ 
+ #define SPI_NAND_MAX_ID_LEN		4U
+ #define DELAY_US_400MS			400000U
+-#define MACRONIX_ID			0xC2U
+ 
+ static struct spinand_device spinand_dev;
+ 
+@@ -91,7 +90,7 @@ static int spi_nand_quad_enable(uint8_t manufacturer_id)
+ {
+ 	bool enable = false;
+ 
+-	if (manufacturer_id != MACRONIX_ID) {
++	if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) {
+ 		return 0;
+ 	}
+ 
+diff --git a/drivers/st/bsec/bsec2.c b/drivers/st/bsec/bsec2.c
+index 6a8af5c13..8a07b118e 100644
+--- a/drivers/st/bsec/bsec2.c
++++ b/drivers/st/bsec/bsec2.c
+@@ -582,23 +582,6 @@ uint32_t bsec_permanent_lock_otp(uint32_t otp)
+ 	return result;
+ }
+ 
+-/*
+- * bsec_write_debug_conf: write value in debug feature.
+- *	to enable/disable debug service.
+- * val: value to write.
+- * return value: none.
+- */
+-void bsec_write_debug_conf(uint32_t val)
+-{
+-	if (is_otp_invalid_mode()) {
+-		return;
+-	}
+-
+-	bsec_lock();
+-	mmio_write_32(bsec_base + BSEC_DEN_OFF, val & BSEC_DEN_ALL_MSK);
+-	bsec_unlock();
+-}
+-
+ /*
+  * bsec_read_debug_conf: return debug configuration register value.
+  */
+diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
+index abe47b53f..43039fdc7 100644
+--- a/drivers/st/uart/aarch32/stm32_console.S
++++ b/drivers/st/uart/aarch32/stm32_console.S
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -238,14 +238,19 @@ func console_stm32_core_flush
+ 	cmp	r0, #0
+ 	ASM_ASSERT(ne)
+ #endif /* ENABLE_ASSERTIONS */
++	/* Skip flush if UART is not enabled */
++	ldr	r1, [r0, #USART_CR1]
++	tst	r1, #USART_CR1_UE
++	beq	1f
+ 	/* Check Transmit Data Register Empty */
+ 	mov	r2, #USART_TIMEOUT
+ txe_loop_3:
+ 	subs	r2, r2, #1
+-	beq	plat_panic_handler
++	beq	1f
+ 	ldr	r1, [r0, #USART_ISR]
+ 	tst	r1, #USART_ISR_TXE
+ 	beq	txe_loop_3
++1:
+ 	bx	lr
+ endfunc console_stm32_core_flush
+ 
+diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
+index 6938d9e3f..52c8e1670 100644
+--- a/fdts/stm32mp15-bl2.dtsi
++++ b/fdts/stm32mp15-bl2.dtsi
+@@ -42,7 +42,6 @@
+ 		/delete-node/ rtc@5c004000;
+ 		/delete-node/ etzpc@5c007000;
+ 		/delete-node/ stgen@5c008000;
+-		/delete-node/ i2c@5c009000;
+ 		/delete-node/ tamp@5c00a000;
+ 
+ 		pinctrl@50002000 {
+diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
+index 264aaf098..6de0207dd 100644
+--- a/fdts/stm32mp15-bl32.dtsi
++++ b/fdts/stm32mp15-bl32.dtsi
+@@ -24,7 +24,6 @@
+ 		/delete-node/ mmc@58007000;
+ 		/delete-node/ spi@5c001000;
+ 		/delete-node/ stgen@5c008000;
+-		/delete-node/ i2c@5c009000;
+ 
+ 		pinctrl@50002000 {
+ 			/delete-node/ fmc-0;
+diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h
+index 40e206375..1eddbb6c0 100644
+--- a/include/drivers/spi_nand.h
++++ b/include/drivers/spi_nand.h
+@@ -29,9 +29,13 @@
+ #define SPI_NAND_STATUS_BUSY		BIT(0)
+ #define SPI_NAND_STATUS_ECC_UNCOR	BIT(5)
+ 
++/* Flags for specific configuration */
++#define SPI_NAND_HAS_QE_BIT		BIT(0)
++
+ struct spinand_device {
+ 	struct nand_device *nand_dev;
+ 	struct spi_mem_op spi_read_cache_op;
++	uint32_t flags;
+ 	uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
+ };
+ 
+diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h
+index 145f9d783..909884289 100644
+--- a/include/drivers/st/bsec.h
++++ b/include/drivers/st/bsec.h
+@@ -102,7 +102,6 @@ uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
+ uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
+ uint32_t bsec_permanent_lock_otp(uint32_t otp);
+ 
+-void bsec_write_debug_conf(uint32_t val);
+ uint32_t bsec_read_debug_conf(void);
+ 
+ void bsec_write_scratch(uint32_t val);
+diff --git a/include/drivers/st/bsec2_reg.h b/include/drivers/st/bsec2_reg.h
+index 0d8fedc48..fbe2e3767 100644
+--- a/include/drivers/st/bsec2_reg.h
++++ b/include/drivers/st/bsec2_reg.h
+@@ -94,7 +94,6 @@
+ #define BSEC_SPIDEN			BIT(5)
+ #define BSEC_SPINDEN			BIT(6)
+ #define BSEC_DBGSWGEN			BIT(10)
+-#define BSEC_DEN_ALL_MSK		GENMASK(10, 0)
+ 
+ /* BSEC_FENABLE Register */
+ #define BSEC_FEN_ALL_MSK		GENMASK(14, 0)
+diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c
+index a993afdbf..48da167bf 100644
+--- a/plat/st/common/stm32cubeprogrammer_uart.c
++++ b/plat/st/common/stm32cubeprogrammer_uart.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
++ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -138,11 +138,13 @@ static int uart_send_result(uint8_t byte)
+ 	return uart_write_8(byte);
+ }
+ 
++#if !STM32MP_SSP
+ static int is_valid_header(fip_toc_header_t *header)
+ {
+ 	return (header->name == TOC_HEADER_NAME) &&
+ 	       (header->serial_number != 0U);
+ }
++#endif
+ 
+ static int uart_receive_command(uint8_t *command)
+ {
+@@ -395,12 +397,15 @@ static int uart_start_cmd(uintptr_t buffer)
+ 		return 0;
+ 	}
+ 
++#if !STM32MP_SSP
+ 	if (!is_valid_header((fip_toc_header_t *)buffer)) {
+ 		STM32PROG_ERROR("FIP Header check failed %lx, for phase %u\n",
+ 				buffer, handle.phase);
+ 		return -EIO;
+ 	}
++
+ 	VERBOSE("FIP header looks OK.\n");
++#endif
+ 
+ 	return 0;
+ }
+@@ -589,6 +594,8 @@ static int uart_read(uint8_t id, uintptr_t buffer, size_t length)
+ 		}
+ 	}
+ 
++	stm32_uart_flush(&handle.uart);
++
+ 	return 0;
+ }
+ 
+diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
+index 73222815c..ccddc5bad 100644
+--- a/plat/st/stm32mp1/include/stm32mp1_private.h
++++ b/plat/st/stm32mp1/include/stm32mp1_private.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -47,6 +47,8 @@ void stm32mp1_init_scmi_server(void);
+ void stm32mp1_pm_save_scmi_state(uint8_t *state, size_t size);
+ void stm32mp1_pm_restore_scmi_state(uint8_t *state, size_t size);
+ 
++bool stm32mp_bkpram_get_access(void);
++
+ #if defined(IMAGE_BL32) && DEBUG
+ void stm32mp_dump_core_registers(bool fcore);
+ #endif
+diff --git a/plat/st/stm32mp1/plat_def_uuid_config.c b/plat/st/stm32mp1/plat_def_uuid_config.c
+index efaf56701..4df414468 100644
+--- a/plat/st/stm32mp1/plat_def_uuid_config.c
++++ b/plat/st/stm32mp1/plat_def_uuid_config.c
+@@ -1,9 +1,11 @@
+ /*
+- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
++ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+ 
++#include <stddef.h>
++
+ #include <firmware_image_package.h>
+ 
+ #include "tbbr_config.h"
+@@ -13,6 +15,11 @@ toc_entry_t plat_def_toc_entries[] = {
+ 		.name = "STM32MP CONFIG CERT",
+ 		.uuid = UUID_STM32MP_CONFIG_CERT,
+ 		.cmdline_name = "stm32mp-cfg-cert"
++	},
++
++	{
++		.name = NULL,
++		.uuid = { {0} },
++		.cmdline_name = NULL,
+ 	}
+ };
+-
+diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
+index 9a4122184..97cedb514 100644
+--- a/plat/st/stm32mp1/platform.mk
++++ b/plat/st/stm32mp1/platform.mk
+@@ -14,7 +14,7 @@ STM32MP_RECONFIGURE_CONSOLE ?=	0
+ STM32MP_UART_BAUDRATE	?=	115200
+ 
+ # Add specific ST version
+-ST_VERSION 		:=	r2.0
++ST_VERSION 		:=	r2.1
+ ST_GIT_SHA1		:=	$(shell git rev-parse --short=8 HEAD 2>/dev/null)
+ VERSION_STRING		:=	v${VERSION_MAJOR}.${VERSION_MINOR}-${PLAT}-${ST_VERSION}(${BUILD_TYPE}):${BUILD_STRING}(${ST_GIT_SHA1})
+ 
+diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
+index 4ed88e6c4..4c881e1cf 100644
+--- a/plat/st/stm32mp1/stm32mp1_context.c
++++ b/plat/st/stm32mp1/stm32mp1_context.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -158,6 +158,10 @@ uint32_t stm32_pm_get_optee_ep(void)
+ 
+ void stm32_clean_context(void)
+ {
++	if (!stm32mp_bkpram_get_access()) {
++		return;
++	}
++
+ 	clk_enable(BKPSRAM);
+ 
+ #if defined(IMAGE_BL2)
+@@ -410,6 +414,10 @@ void stm32_context_save_bl2_param(void)
+ {
+ 	struct backup_data_s *backup_data;
+ 
++	if (!stm32mp_bkpram_get_access()) {
++		return;
++	}
++
+ 	clk_enable(BKPSRAM);
+ 
+ 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+@@ -578,6 +586,10 @@ void stm32mp1_pm_save_mce_mkey_in_context(uint8_t *data)
+ 
+ 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ 
++	if (!stm32mp_bkpram_get_access()) {
++		return;
++	}
++
+ 	clk_enable(BKPSRAM);
+ 
+ 	memcpy(backup_data->mce_mkey, data, MCE_KEY_SIZE_IN_BYTES);
+@@ -591,6 +603,11 @@ void stm32mp1_pm_get_mce_mkey_from_context(uint8_t *data)
+ 
+ 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ 
++	if (!stm32mp_bkpram_get_access()) {
++		ERROR("DDR encryption key not available\n");
++		panic();
++	}
++
+ 	clk_enable(BKPSRAM);
+ 
+ 	memcpy(data, backup_data->mce_mkey, MCE_KEY_SIZE_IN_BYTES);
+@@ -606,6 +623,10 @@ void stm32mp1_pm_save_mce_region(uint32_t index, struct stm32_mce_region_s *conf
+ 		panic();
+ 	}
+ 
++	if (!stm32mp_bkpram_get_access()) {
++		return;
++	}
++
+ 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ 
+ 	clk_enable(BKPSRAM);
+@@ -625,6 +646,11 @@ void stm32mp1_pm_get_mce_region(uint32_t index, struct stm32_mce_region_s *confi
+ 
+ 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ 
++	if (!stm32mp_bkpram_get_access()) {
++		ERROR("MCE region not available\n");
++		panic();
++	}
++
+ 	clk_enable(BKPSRAM);
+ 
+ 	memcpy(config, &backup_data->mce_regions[index], sizeof(struct stm32_mce_region_s));
+diff --git a/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S b/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
+index d7981d61c..c3fb5cdbf 100644
+--- a/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
++++ b/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2019-2021, STMicroelectronics - All Rights Reserved
++ * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -61,13 +61,6 @@ func stm32_pwr_down_wfi_wrapper
+ 	# Set sp to BL2 STACK (as BL2 is not using it anymore)
+ 	ldr	sp, =__STACKS_END__
+ 
+-	# Disable MMU as TLB are still stored in DDR,
+-	# and in few instructions DDR won't be readable
+-	bl	disable_mmu_secure
+-
+-	# dsb is done in disable mmu
+-	# isb is done in disable mmu
+-
+ 	mov	r0, r2
+ 	mov	r1, r3
+ 
+diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
+index ba92bd321..d80d64695 100644
+--- a/plat/st/stm32mp1/stm32mp1_def.h
++++ b/plat/st/stm32mp1/stm32mp1_def.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -380,9 +380,11 @@ enum ddr_type {
+ #if STM32MP13
+ #define NAND_OTP			"cfg9_otp"
+ #define NAND2_OTP			"cfg10_otp"
++#define SSP_OTP				"cfg9_otp"
+ #endif
+ #if STM32MP15
+ #define NAND_OTP			"nand_otp"
++#define SSP_OTP				"ssp_otp"
+ #endif
+ #define MONOTONIC_OTP			"monotonic_otp"
+ #define UID_OTP				"uid_otp"
+@@ -390,7 +392,6 @@ enum ddr_type {
+ #define ENCKEY_OTP			"enckey_otp"
+ #define BOARD_ID_OTP			"board_id"
+ #define CFG2_OTP			"cfg2_otp"
+-#define SSP_OTP				"ssp_otp"
+ #define CHIP_CERTIFICATE_OTP		"chip_otp"
+ #define RMA_OTP				"rma_otp"
+ 
+@@ -521,7 +522,13 @@ enum ddr_type {
+ #define TAMP_BKP_REGISTER_BASE		(TAMP_BASE + U(0x100))
+ #define TAMP_BKP_SEC_NUMBER		U(10)
+ #define TAMP_BKP_S_W_NS_R_NUMBER	U(5)
++#define TAMP_CR2			U(0x4)
++#define TAMP_CR2_MASK_NOER		GENMASK_32(7, 0)
++#define TAMP_CR3			U(0x8)
++#define TAMP_CR3_MASK_NOER		GENMASK_32(12, 0)
++#define TAMP_SR				U(0x30)
+ #define TAMP_COUNTR			U(0x40)
++#define TAMP_ERCFGR			U(0x54)
+ 
+ #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
+ static inline uintptr_t tamp_bkpr(uint32_t idx)
+diff --git a/plat/st/stm32mp1/stm32mp1_low_power.c b/plat/st/stm32mp1/stm32mp1_low_power.c
+index a4b473515..0be84c935 100644
+--- a/plat/st/stm32mp1/stm32mp1_low_power.c
++++ b/plat/st/stm32mp1/stm32mp1_low_power.c
+@@ -232,13 +232,6 @@ static void enter_cstop(uint32_t mode, uint32_t nsec_addr)
+ 				;
+ 			}
+ 		}
+-
+-		/* Keep backup RAM content in standby */
+-		mmio_setbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN);
+-		while ((mmio_read_32(pwr_base + PWR_CR2) &
+-			PWR_CR2_BRRDY) == 0U) {
+-			;
+-		}
+ 	}
+ 
+ 	clk_disable(RTCAPB);
+@@ -281,8 +274,8 @@ void stm32_exit_cstop(void)
+ 	dsb();
+ 	isb();
+ 
+-	/* Disable retention and backup RAM content after stop */
+-	mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN);
++	/* Disable retention RAM content after stop */
++	mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_RREN);
+ 
+ 	/* Update STGEN counter with low power mode duration */
+ 	stm32_rtc_get_calendar(&current_calendar);
+@@ -431,11 +424,18 @@ void stm32_init_low_power(void)
+ 	mmio_setbits_32(rcc_base + RCC_MP_SREQCLRR,
+ 			RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1);
+ 
+-	/* Disable retention and backup RAM content after standby */
+-	mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN);
++	/* Disable retention RAM content after standby */
++	mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_RREN);
+ 
+ 	/* Wait 5 HSI periods before re-enabling PLLs after STOP modes */
+ 	mmio_clrsetbits_32(rcc_base + RCC_PWRLPDLYCR,
+ 			   RCC_PWRLPDLYCR_PWRLP_DLY_MASK,
+ 			   PWRLP_TEMPO_5_HSI);
++
++	/* Keep backup RAM content in standby and VBAT mode */
++	mmio_setbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN);
++	while ((mmio_read_32(pwr_base + PWR_CR2) &
++		PWR_CR2_BRRDY) == 0U) {
++		;
++	}
+ }
+diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
+index 1346c11b5..c482af502 100644
+--- a/plat/st/stm32mp1/stm32mp1_pm.c
++++ b/plat/st/stm32mp1/stm32mp1_pm.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -169,13 +169,13 @@ static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
+ 		void (*warm_entrypoint)(void) =
+ 			(void (*)(void))stm32_sec_entrypoint;
+ 
++		disable_mmu_icache_secure();
++
+ 		stm32_pwr_down_wfi(stm32_is_cstop_done(),
+ 				   stm32mp1_get_lp_soc_mode(PSCI_MODE_SYSTEM_SUSPEND));
+ 
+ 		stm32_exit_cstop();
+ 
+-		disable_mmu_icache_secure();
+-
+ 		warm_entrypoint();
+ 	}
+ 
+diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
+index 7e2c0ed4e..97f64e772 100644
+--- a/plat/st/stm32mp1/stm32mp1_private.c
++++ b/plat/st/stm32mp1/stm32mp1_private.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -988,3 +988,33 @@ void stm32_set_max_fwu_trial_boot_cnt(void)
+ 	clk_disable(RTCAPB);
+ }
+ #endif /* PSA_FWU_SUPPORT */
++
++#if STM32MP13
++bool stm32mp_bkpram_get_access(void)
++{
++	static bool state = true;
++
++	if (!state) {
++		return state;
++	}
++
++	clk_enable(RTCAPB);
++
++	if ((mmio_read_32(TAMP_BASE + TAMP_ERCFGR) != 0U) &&
++	    (mmio_read_32(TAMP_BASE + TAMP_SR) != 0U) &&
++	    (((mmio_read_32(TAMP_BASE + TAMP_CR2) & TAMP_CR2_MASK_NOER) == 0U) ||
++	     ((mmio_read_32(TAMP_BASE + TAMP_CR3) & TAMP_CR3_MASK_NOER) == 0U))) {
++		NOTICE("TAMPER detected : Degraded mode\n");
++		state = false;
++	}
++
++	clk_disable(RTCAPB);
++
++	return state;
++}
++#else /* STM32MP15 */
++bool stm32mp_bkpram_get_access(void)
++{
++	return true;
++}
++#endif
+diff --git a/plat/st/stm32mp1/stm32mp1_ssp.c b/plat/st/stm32mp1/stm32mp1_ssp.c
+index ed1fd8ec0..f9ff52f58 100644
+--- a/plat/st/stm32mp1/stm32mp1_ssp.c
++++ b/plat/st/stm32mp1/stm32mp1_ssp.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
++ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -1000,6 +1000,9 @@ void bl2_el3_plat_arch_setup(void)
+ 		initialize_pmic();
+ 	}
+ 
++	stm32_save_boot_interface(boot_context->boot_interface_selected,
++				  boot_context->boot_interface_instance);
++
+ #if DEBUG
+ 	if (stm32mp_uart_console_setup() != 0) {
+ 		goto skip_console_init;
+-- 
+2.25.1
+