From 5c3c6aa07a4fb700b252de6b68d6365c38b6fccf Mon Sep 17 00:00:00 2001 From: Christophe Priouzeau Date: Thu, 16 Jun 2022 16:46:16 +0200 Subject: [PATCH] U-BOOT-STM32MP: v2021.10-stm32mp-r2 Signed-off-by: Romuald JEANNE Change-Id: I4ddc6905fb1e21bfcb6f84a2b5d2dd4d7d95f26c --- classes/fip-utils-stm32mp.bbclass | 9 +- .../u-boot/u-boot-stm32mp-archiver.inc | 34 +- .../u-boot/u-boot-stm32mp-common_2021.10.inc | 8 +- recipes-bsp/u-boot/u-boot-stm32mp.inc | 14 +- ...0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch | 147 + .../0007-ARM-v2021.10-stm32mp-r2-BOARD.patch | 91 + ...ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch | 1179 +++++ ...9-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch | 4567 +++++++++++++++++ .../u-boot-stm32mp/0098-silent_mode.patch | 52 +- 9 files changed, 6053 insertions(+), 48 deletions(-) create mode 100644 recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch create mode 100644 recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2021.10-stm32mp-r2-BOARD.patch create mode 100644 recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch create mode 100644 recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch diff --git a/classes/fip-utils-stm32mp.bbclass b/classes/fip-utils-stm32mp.bbclass index abfeab1..b9da0e4 100644 --- a/classes/fip-utils-stm32mp.bbclass +++ b/classes/fip-utils-stm32mp.bbclass @@ -47,7 +47,6 @@ FIP_UBOOT ?= "u-boot-nodtb" FIP_UBOOT_SUFFIX ?= "bin" FIP_UBOOT_DTB ?= "u-boot" FIP_UBOOT_DTB_SUFFIX ?= "dtb" -FIP_UBOOT_CONFIG ?= "trusted" # Configure default folder path for binaries to package FIP_DEPLOYDIR_FIP ?= "${DEPLOYDIR}/fip" @@ -190,8 +189,8 @@ do_deploy:append:class-target() { [ -f "${FIP_DEPLOYDIR_FWCONF}/${dt}-${FIP_FW_CONFIG}-${config}.${FIP_FW_CONFIG_SUFFIX}" ] || bbfatal "Missing ${dt}-${FIP_FW_CONFIG}-${config}.${FIP_FW_CONFIG_SUFFIX} file in folder: ${FIP_DEPLOYDIR_FWCONF}" FIP_FWCONFIG="--fw-config ${FIP_DEPLOYDIR_FWCONF}/${dt}-${FIP_FW_CONFIG}-${config}.${FIP_FW_CONFIG_SUFFIX}" # Init FIP hw-config settings - [ -f "${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT_DTB}-${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT_DTB}-${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX} file in folder: ${FIP_DEPLOYDIR_UBOOT}" - FIP_HWCONFIG="--hw-config ${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT_DTB}-${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX}" + [ -f "${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT_DTB}-${dt}.${FIP_UBOOT_DTB_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT_DTB}-${dt}.${FIP_UBOOT_DTB_SUFFIX} file in folder: ${FIP_DEPLOYDIR_UBOOT}" + FIP_HWCONFIG="--hw-config ${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT_DTB}-${dt}.${FIP_UBOOT_DTB_SUFFIX}" # Init FIP nt-fw config [ -f "${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT}${soc_suffix}.${FIP_UBOOT_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT}${soc_suffix}.${FIP_UBOOT_SUFFIX} file in folder: ${FIP_DEPLOYDIR_UBOOT}" FIP_NTFW="--nt-fw ${FIP_DEPLOYDIR_UBOOT}/${FIP_UBOOT}${soc_suffix}.${FIP_UBOOT_SUFFIX}" @@ -392,8 +391,8 @@ for config in \$FIP_CONFIG; do [ -f "\$FIP_DEPLOYDIR_FWCONF/\${dt}-${FIP_FW_CONFIG}-\${config}.${FIP_FW_CONFIG_SUFFIX}" ] || bbfatal "Missing \${dt}-${FIP_FW_CONFIG}-\${config}.${FIP_FW_CONFIG_SUFFIX} file in folder: \\\$FIP_DEPLOYDIR_FWCONF or '\\\$FIP_DEPLOYDIR_ROOT/arm-trusted-firmware/fwconfig'" FIP_FWCONFIG="--fw-config \$FIP_DEPLOYDIR_FWCONF/\${dt}-${FIP_FW_CONFIG}-\${config}.${FIP_FW_CONFIG_SUFFIX}" # Init FIP hw-config settings - [ -f "\$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT_DTB}-\${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT_DTB}-\${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX} file in folder: '\\\$FIP_DEPLOYDIR_UBOOT' or '\\\$FIP_DEPLOYDIR_ROOT/u-boot'" - FIP_HWCONFIG="--hw-config \$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT_DTB}-\${dt}-${FIP_UBOOT_CONFIG}.${FIP_UBOOT_DTB_SUFFIX}" + [ -f "\$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT_DTB}-\${dt}.${FIP_UBOOT_DTB_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT_DTB}-\${dt}.${FIP_UBOOT_DTB_SUFFIX} file in folder: '\\\$FIP_DEPLOYDIR_UBOOT' or '\\\$FIP_DEPLOYDIR_ROOT/u-boot'" + FIP_HWCONFIG="--hw-config \$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT_DTB}-\${dt}.${FIP_UBOOT_DTB_SUFFIX}" # Init FIP nt-fw config [ -f "\$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT}\${soc_suffix}.${FIP_UBOOT_SUFFIX}" ] || bbfatal "Missing ${FIP_UBOOT}\${soc_suffix}.${FIP_UBOOT_SUFFIX} file in folder: '\\\$FIP_DEPLOYDIR_UBOOT' or '\\\$FIP_DEPLOYDIR_ROOT/u-boot'" FIP_NTFW="--nt-fw \$FIP_DEPLOYDIR_UBOOT/${FIP_UBOOT}\${soc_suffix}.${FIP_UBOOT_SUFFIX}" diff --git a/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc b/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc index 0e4a3c7..be13bb3 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc @@ -73,42 +73,42 @@ UBOOT_LOCALVERSION = ${UBOOT_LOCALVERSION} define uboot-configs echo " \$(1)" ; \\ \$(foreach defconfig, \$(if \$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG_\$(1))), \\ - echo " defconfig : \$(defconfig)" ; \ - echo " for binary : \$(if \$(UBOOT_BINARY),\$(UBOOT_BINARY),\$(UBOOT_BINARY_\$(defconfig)))" ; \ - echo " with devicetree: \$(if \$(DEVICETREE),\$(DEVICETREE),\$(UBOOT_DEVICETREE_\$(defconfig)))" ; \ + echo " defconfig : \$(defconfig)" ; \\ + echo " for binary : \$(if \$(UBOOT_BINARY),\$(UBOOT_BINARY),\$(UBOOT_BINARY_\$(defconfig)))" ; \\ + echo " with devicetree: \$(if \$(DEVICETREE),\$(DEVICETREE),\$(UBOOT_DEVICETREE_\$(defconfig)))" ; \\ ) endef -# Configure U-Boot configure rules (configure-DEFCONFIG-CONFIG) +# Configure U-Boot configure rules (configure-DEFCONFIG) define configure-rules -configure-\$(1)-\$(2): version +configure-\$(1):: version @mkdir -p \$(BLD_PATH)/\$(1) @echo \$(UBOOT_LOCALVERSION) > \$(BLD_PATH)/\$(1)/.scmversion - \$(MAKE) -C \$(SRC_PATH) O=\$(BLD_PATH)/\$(1) \$(1) + \$(MAKE) -C \$(SRC_PATH) O=\$(BLD_PATH)/\$(1) \$(1) || exit 1 endef -# Configure U-Boot make rules (uboot-DEFCONFIG-CONFIG) +# Configure U-Boot make rules (uboot-DEFCONFIG) define uboot-rules -uboot-\$(1)-\$(2): configure-\$(1)-\$(2) +uboot-\$(1):: configure-\$(1) @mkdir -p \$(DEPLOYDIR) @\$(foreach dt, \$(if \$(DEVICETREE),\$(DEVICETREE),\$(UBOOT_DEVICETREE_\$(1))), \\ \$(MAKE) -C \$(SRC_PATH) ${UBOOT_MAKE_TARGET} \\ O=\$(BLD_PATH)/\$(1) \\ DEVICE_TREE=\$(dt) \\ - DEVICE_TREE_EXT=\$(dt).dtb ; \\ - cp -f \$(BLD_PATH)/\$(1)/\$(3) \$(DEPLOYDIR)/u-boot-\$(dt)-\$(2).\$(shell echo \$(3) | cut -d'.' -f2) ; \\ + DEVICE_TREE_EXT=\$(dt).dtb || exit 1 ; \\ + cp -f \$(BLD_PATH)/\$(1)/\$(3) \$(DEPLOYDIR)/u-boot-\$(dt).\$(shell echo \$(3) | cut -d'.' -f2) || exit 1 ; \\ if [ -f \$(BLD_PATH)/\$(1)/\$(shell echo \$(3) | cut -d'.' -f1).stm32 ]; then \\ - cp -f \$(BLD_PATH)/\$(1)/\$(shell echo \$(3) | cut -d'.' -f1).stm32 \$(DEPLOYDIR)/u-boot-\$(dt)-\$(2).stm32 ; \\ + cp -f \$(BLD_PATH)/\$(1)/\$(shell echo \$(3) | cut -d'.' -f1).stm32 \$(DEPLOYDIR)/u-boot-\$(dt).stm32 ; \\ fi ; \\ if [ -f \$(BLD_PATH)/\$(1)/${SPL_BINARY_STM32} ]; then \\ - cp -f \$(BLD_PATH)/\$(1)/${SPL_BINARY_STM32} \$(DEPLOYDIR)/${SPL_BINARYNAME}-\$(dt)-\$(2) ; \\ + cp -f \$(BLD_PATH)/\$(1)/${SPL_BINARY_STM32} \$(DEPLOYDIR)/${SPL_BINARYNAME}-\$(dt); \\ fi ; \\ ) endef -# Configure U-Boot deploy rules (deploy-DEFCONFIG-CONFIG) +# Configure U-Boot deploy rules (deploy-DEFCONFIG) define deploy-rules -deploy-\$(1)-\$(2): uboot-\$(1)-\$(2) +deploy-\$(1):: uboot-\$(1) @mkdir -p \$(DEPLOYDIR) @mkdir -p \$(DEPLOYDIR)/debug @\$(foreach dt, \$(if \$(DEVICETREE),\$(DEVICETREE),\$(UBOOT_DEVICETREE_\$(1))), \\ @@ -116,17 +116,17 @@ deploy-\$(1)-\$(2): uboot-\$(1)-\$(2) cp -f \$(BLD_PATH)/\$(1)/u-boot-nodtb.bin \$(DEPLOYDIR)/u-boot-nodtb\$(strip \$(foreach soc,${STM32MP_SOC_NAME},\$(if \$(findstring \$(soc),\$(dt)),-\$(soc),))).bin ; \\ fi ; \\ if [ -f \$(BLD_PATH)/\$(1)/${UBOOT_ELF} ]; then \\ - cp -f \$(BLD_PATH)/\$(1)/${UBOOT_ELF} \$(DEPLOYDIR)/debug/u-boot\$(strip \$(foreach soc,${STM32MP_SOC_NAME},\$(if \$(findstring \$(soc),\$(dt)),-\$(soc),)))-\$(2).${UBOOT_ELF_SUFFIX} ; \\ + cp -f \$(BLD_PATH)/\$(1)/${UBOOT_ELF} \$(DEPLOYDIR)/debug/u-boot\$(strip \$(foreach soc,${STM32MP_SOC_NAME},\$(if \$(findstring \$(soc),\$(dt)),-\$(soc),))).${UBOOT_ELF_SUFFIX} ; \\ fi ; \\ if [ -f \$(BLD_PATH)/\$(1)/${SPL_ELF} ]; then \\ - cp -f \$(BLD_PATH)/\$(1)/${SPL_ELF} \$(DEPLOYDIR)/debug/${SPL_ELF_NAME}\$(strip \$(foreach soc,${STM32MP_SOC_NAME},\$(if \$(findstring \$(soc),\$(dt)),-\$(soc),)))-\$(2) ; \\ + cp -f \$(BLD_PATH)/\$(1)/${SPL_ELF} \$(DEPLOYDIR)/debug/${SPL_ELF_NAME}\$(strip \$(foreach soc,${STM32MP_SOC_NAME},\$(if \$(findstring \$(soc),\$(dt)),-\$(soc),))); \\ fi ; \\ ) endef # Configure overall deploy rules list deploy-targets := \$(foreach config, \$(if \$(UBOOT_CONFIG),\$(UBOOT_CONFIG),\$(UBOOT_CONFIGS)), \\ - \$(foreach defconfig, \$(if \$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG_\$(config))), deploy-\$(defconfig)-\$(config)) \\ + \$(foreach defconfig, \$(if \$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG),\$(UBOOT_DEFCONFIG_\$(config))), deploy-\$(defconfig)) \\ ) # Set dependencies list for building all diff --git a/recipes-bsp/u-boot/u-boot-stm32mp-common_2021.10.inc b/recipes-bsp/u-boot/u-boot-stm32mp-common_2021.10.inc index bc72597..b1eada2 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp-common_2021.10.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp-common_2021.10.inc @@ -21,6 +21,10 @@ SRC_URI += "\ file://0003-ARM-v2021.10-stm32mp-r1-MISC-DRIVERS.patch \ file://0004-ARM-v2021.10-stm32mp-r1-DEVICETREE.patch \ file://0005-ARM-v2021.10-stm32mp-r1-CONFIG.patch \ + file://0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch \ + file://0007-ARM-v2021.10-stm32mp-r2-BOARD.patch \ + file://0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch \ + file://0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch \ \ file://0099-Add-external-var-to-allow-build-of-new-devicetree-fi.patch \ " @@ -30,7 +34,7 @@ SRC_URI += "${@bb.utils.contains('ST_UBOOT_DEBUG_TRACE', '1', '', 'file://0098-s U_BOOT_VERSION = "v2021.10" U_BOOT_SUBVERSION = "stm32mp" -U_BOOT_RELEASE = "r1" +U_BOOT_RELEASE = "r2" PV = "${U_BOOT_VERSION}-${U_BOOT_SUBVERSION}-${U_BOOT_RELEASE}" @@ -47,7 +51,7 @@ S = "${WORKDIR}/git" BBCLASSEXTEND = "devupstream:target" SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/u-boot.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}" -SRCREV:class-devupstream = "ef9715e76295f5f6aae49efdb51617b440b54deb" +SRCREV:class-devupstream = "3984366f6997c680b8c6ccc82d50e77a6e1cccf2" # --------------------------------- # Configure default preference to manage dynamic selection between tarball and github diff --git a/recipes-bsp/u-boot/u-boot-stm32mp.inc b/recipes-bsp/u-boot/u-boot-stm32mp.inc index 7f1ae96..b9be664 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp.inc @@ -175,14 +175,14 @@ do_compile:append() { k=$(expr $k + 1); if [ $k -eq $i ]; then binarysuffix=$(echo ${binary} | cut -d'.' -f2) - install -m 644 ${B}/${config}/${binary} ${B}/${config}/u-boot-${devicetree}-${type_suffix}.${binarysuffix} + install -m 644 ${B}/${config}/${binary} ${B}/${config}/u-boot-${devicetree}.${binarysuffix} fi done unset k # As soon as SPL binary exists, copy it with specific binary_type name # This allow to mix u-boot configuration, with and without SPL if [ -f "${B}/${config}/${SPL_BINARY_STM32}" ]; then - install -m 644 ${B}/${config}/${SPL_BINARY_STM32} ${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type_suffix} + install -m 644 ${B}/${config}/${SPL_BINARY_STM32} ${B}/${config}/${SPL_BINARYNAME}-${devicetree} fi done fi @@ -240,11 +240,11 @@ do_deploy:append() { fi fi # Install u-boot binary - install -m 644 ${B}/${config}/u-boot-${devicetree}-${type_suffix}.${binarysuffix} ${DEPLOYDIR}${SUBFOLDER}/ + install -m 644 ${B}/${config}/u-boot-${devicetree}.${binarysuffix} ${DEPLOYDIR}${SUBFOLDER}/ # As soon as SPL binary exists, install it # This allow to mix u-boot configuration, with and without SPL - if [ -f "${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type_suffix}" ]; then - install -m 644 ${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type_suffix} ${DEPLOYDIR}${SUBFOLDER}/ + if [ -f "${B}/${config}/${SPL_BINARYNAME}-${devicetree}" ]; then + install -m 644 ${B}/${config}/${SPL_BINARYNAME}-${devicetree} ${DEPLOYDIR}${SUBFOLDER}/ fi # Init soc suffix soc_suffix="" @@ -258,10 +258,10 @@ do_deploy:append() { install -m 644 ${B}/${config}/u-boot-nodtb.bin ${DEPLOYDIR}${SUBFOLDER}/u-boot-nodtb${soc_suffix}.bin fi if [ -n "${UBOOT_ELF}" ]; then - install -m 644 ${B}/${config}/${UBOOT_ELF} ${DEPLOYDIR}${SUBFOLDER}/debug/u-boot${soc_suffix}-${type_suffix}.${UBOOT_ELF_SUFFIX} + install -m 644 ${B}/${config}/${UBOOT_ELF} ${DEPLOYDIR}${SUBFOLDER}/debug/u-boot${soc_suffix}.${UBOOT_ELF_SUFFIX} fi if [ -n "${SPL_ELF}" ] && [ -f "${B}/${config}/${SPL_ELF}" ]; then - install -m 644 ${B}/${config}/${SPL_ELF} ${DEPLOYDIR}${SUBFOLDER}/debug/${SPL_ELF_NAME}${soc_suffix}-${type_suffix} + install -m 644 ${B}/${config}/${SPL_ELF} ${DEPLOYDIR}${SUBFOLDER}/debug/${SPL_ELF_NAME}${soc_suffix} fi if [ "${UBOOT_SIGN_ENABLE}" = "1" -a -n "${UBOOT_DTB_BINARY}" ] ; then diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch new file mode 100644 index 0000000..9ff86ad --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2021.10-stm32mp-r2-MACHINE.patch @@ -0,0 +1,147 @@ +From 0afeb764866b755d64728e58f279db3e10d8a328 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Wed, 19 Oct 2022 16:58:04 +0200 +Subject: [PATCH 6/9] ARM v2021.10-stm32mp-r2 MACHINE + +Signed-off-by: Romuald JEANNE +--- + .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 33 +++++++++++++------ + .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 5 +++ + arch/arm/mach-stm32mp/include/mach/stm32.h | 1 - + .../arm/mach-stm32mp/include/mach/sys_proto.h | 2 +- + 4 files changed, 29 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +index ce568b44dc2..f9b502c9375 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +@@ -1091,7 +1091,6 @@ static int create_gpt_partitions(struct stm32prog_data *data) + if (!buf) + return -ENOMEM; + +- puts("partitions : "); + /* initialize the selected device */ + for (i = 0; i < data->dev_nb; i++) { + /* create gpt partition support only for full update on MMC */ +@@ -1099,6 +1098,7 @@ static int create_gpt_partitions(struct stm32prog_data *data) + !data->dev[i].full_update) + continue; + ++ printf("partitions on mmc%d: ", data->dev[i].dev_id); + offset = 0; + rootfs_found = false; + memset(buf, 0, buflen); +@@ -1198,8 +1198,8 @@ static int create_gpt_partitions(struct stm32prog_data *data) + sprintf(buf, "part list mmc %d", data->dev[i].dev_id); + run_command(buf, 0); + #endif ++ puts("done\n"); + } +- puts("done\n"); + + #ifdef DEBUG + run_command("mtd list", 0); +@@ -1343,10 +1343,22 @@ static int dfu_init_entities(struct stm32prog_data *data) + struct stm32prog_part_t *part; + struct dfu_entity *dfu; + int alt_nb; ++ u32 otp_size = 0; + + alt_nb = 1; /* number of virtual = CMD*/ +- if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) +- alt_nb++; /* OTP*/ ++ ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { ++ /* OTP_SIZE_SMC = 0 if SMC is not supported */ ++ otp_size = OTP_SIZE_SMC; ++ /* check if PTA BSEC is supported */ ++ ret = optee_ta_open(data); ++ log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret); ++ if (!ret && data->tee) ++ otp_size = OTP_SIZE_TA; ++ if (otp_size) ++ alt_nb++; /* OTP*/ ++ } ++ + if (CONFIG_IS_ENABLED(DM_PMIC)) + alt_nb++; /* PMIC NVMEM*/ + +@@ -1364,6 +1376,7 @@ static int dfu_init_entities(struct stm32prog_data *data) + puts("DFU alt info setting: "); + if (data->part_nb) { + alt_id = 0; ++ ret = 0; + for (phase = 1; + (phase <= PHASE_LAST_USER) && + (alt_id < alt_nb) && !ret; +@@ -1397,12 +1410,8 @@ static int dfu_init_entities(struct stm32prog_data *data) + if (!ret) + ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); + +- if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { +- ret = optee_ta_open(data); +- log_debug("optee_ta result %d\n", ret); +- ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, +- data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC); +- } ++ if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size) ++ ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size); + + if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) + ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE); +@@ -1885,6 +1894,10 @@ static void stm32prog_devices_init(struct stm32prog_data *data) + if (ret) + goto error; + ++ /* empty flashlayout */ ++ if (!data->dev_nb) ++ return; ++ + /* initialize the selected device */ + for (i = 0; i < data->dev_nb; i++) { + ret = init_device(data, &data->dev[i]); +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +index ac300768ca0..0cda487ddd5 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +@@ -20,7 +20,12 @@ + #define DEFAULT_ADDRESS 0xFFFFFFFF + + #define CMD_SIZE 512 ++/* SMC is only supported in SPMIN for STM32MP15x */ ++#ifdef CONFIG_STM32MP15x + #define OTP_SIZE_SMC 1024 ++#else ++#define OTP_SIZE_SMC 0 ++#endif + #define OTP_SIZE_TA 776 + #define PMIC_SIZE 8 + +diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h +index 62acd76c013..fc456ff8e80 100644 +--- a/arch/arm/mach-stm32mp/include/mach/stm32.h ++++ b/arch/arm/mach-stm32mp/include/mach/stm32.h +@@ -134,7 +134,6 @@ enum boot_device { + #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) + #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) + #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +-#define TAMP_BOOT_DEBUG_ON BIT(16) + + enum forced_boot_mode { + BOOT_NORMAL = 0x00, +diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h +index 02debea5469..f19a70e53e0 100644 +--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h ++++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h +@@ -41,7 +41,7 @@ u32 get_cpu_dev(void); + + #define CPU_REV1 0x1000 + #define CPU_REV1_1 0x1001 +-#define CPU_REV1_2 0x1002 ++#define CPU_REV1_2 0x1003 + #define CPU_REV2 0x2000 + #define CPU_REV2_1 0x2001 + +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2021.10-stm32mp-r2-BOARD.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2021.10-stm32mp-r2-BOARD.patch new file mode 100644 index 0000000..e168539 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2021.10-stm32mp-r2-BOARD.patch @@ -0,0 +1,91 @@ +From ea95370bf05dcc38e0b1df21a172840c232d4b21 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Thu, 3 Nov 2022 11:14:30 +0100 +Subject: [PATCH 7/9] ARM v2021.10-stm32mp-r2 BOARD + +Signed-off-by: Romuald JEANNE +--- + board/st/common/stpmic1.c | 14 -------------- + board/st/stm32mp1/stm32mp1.c | 15 +++++---------- + 2 files changed, 5 insertions(+), 24 deletions(-) + +diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c +index 5fb1be2fd3d..d52dce4f657 100644 +--- a/board/st/common/stpmic1.c ++++ b/board/st/common/stpmic1.c +@@ -202,18 +202,4 @@ void stpmic1_init(u32 voltage_mv) + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); +- +- /* Check if debug is enabled to program PMIC according to the bit */ +- if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) { +- log_info("Keep debug unit ON\n"); +- +- pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR, +- STPMIC1_MRST_BUCK_DEBUG, +- STPMIC1_MRST_BUCK_DEBUG); +- +- if (STPMIC1_MRST_LDO_DEBUG) +- pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR, +- STPMIC1_MRST_LDO_DEBUG, +- STPMIC1_MRST_LDO_DEBUG); +- } + } +diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c +index c9b21a76eb7..05f41737e6d 100644 +--- a/board/st/stm32mp1/stm32mp1.c ++++ b/board/st/stm32mp1/stm32mp1.c +@@ -506,7 +506,7 @@ static void sysconf_init(void) + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_DRIVER_GET(stm32mp_pwr_pmic), + &pwr_dev); +- if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) { ++ if (!ret) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); +@@ -567,9 +567,6 @@ static int board_stm32mp15x_dk2_init(void) + struct gpio_desc hdmi, audio; + int ret = 0; + +- if (!IS_ENABLED(CONFIG_DM_REGULATOR)) +- return -ENODEV; +- + /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ + node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); + if (!ofnode_valid(node)) { +@@ -621,8 +618,7 @@ error: + static bool board_is_stm32mp13x_dk(void) + { + if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP13x) && +- (of_machine_is_compatible("st,stm32mp135d-dk") || +- of_machine_is_compatible("st,stm32mp135f-dk"))) ++ of_machine_is_compatible("st,stm32mp135f-dk")) + return true; + + return false; +@@ -860,8 +856,7 @@ int board_init(void) + + board_key_check(); + +- if (IS_ENABLED(CONFIG_DM_REGULATOR)) +- regulators_enable_boot_on(_DEBUG); ++ regulators_enable_boot_on(_DEBUG); + + /* + * sysconf initialisation done only when U-Boot is running in secure +@@ -1438,8 +1433,8 @@ void fdt_update_panel_dsi(void *new_blob) + int ft_board_setup(void *blob, struct bd_info *bd) + { + static const struct node_info nodes[] = { +- { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, +- { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND}, ++ { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, ++ { "spi-nand", MTD_DEV_TYPE_SPINAND}, + { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, + { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, + }; +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch new file mode 100644 index 0000000..2921b73 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch @@ -0,0 +1,1179 @@ +From 86d72a3e8f002145e67aca3906ca663cd43ca059 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Thu, 3 Nov 2022 11:15:44 +0100 +Subject: [PATCH 8/9] ARM v2021.10-stm32mp-r2 MISC-DRIVERS + +Signed-off-by: Romuald JEANNE +--- + Makefile | 2 +- + arch/sandbox/include/asm/gpio.h | 3 +- + cmd/pxe_utils.c | 74 ++++++++++------ + cmd/pxe_utils.h | 2 + + doc/README.pxe | 3 + + doc/board/st/stm32mp1.rst | 4 +- + drivers/clk/clk-stm32-core.c | 147 ++++++++++++++++---------------- + drivers/clk/clk-stm32-core.h | 17 ++-- + drivers/clk/clk_scmi.c | 16 ++-- + drivers/gpio/gpio-uclass.c | 19 +++-- + drivers/gpio/sandbox.c | 16 +++- + drivers/gpio/stm32_gpio.c | 6 ++ + drivers/i2c/stm32f7_i2c.c | 33 ++++--- + drivers/mmc/stm32_sdmmc2.c | 20 +++-- + drivers/pinctrl/pinctrl_stm32.c | 7 +- + drivers/usb/host/ehci-generic.c | 97 +++++++-------------- + drivers/video/stm32/stm32_dsi.c | 25 +++--- + drivers/video/video_bmp.c | 6 +- + include/asm-generic/gpio.h | 1 + + include/power/stpmic1.h | 3 - + test/dm/gpio.c | 5 ++ + 21 files changed, 266 insertions(+), 240 deletions(-) + +diff --git a/Makefile b/Makefile +index 6203f40cb17..9e47e7b0972 100644 +--- a/Makefile ++++ b/Makefile +@@ -3,7 +3,7 @@ + VERSION = 2021 + PATCHLEVEL = 10 + SUBLEVEL = +-EXTRAVERSION = -stm32mp-r1 ++EXTRAVERSION = -stm32mp-r2 + NAME = + + # *DOCUMENTATION* +diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h +index 9e10052667d..1d0f83c01e8 100644 +--- a/arch/sandbox/include/asm/gpio.h ++++ b/arch/sandbox/include/asm/gpio.h +@@ -28,9 +28,10 @@ + #define GPIOD_EXT_DRIVEN BIT(30) /* external source is driven */ + #define GPIOD_EXT_PULL_UP BIT(29) /* GPIO has external pull-up */ + #define GPIOD_EXT_PULL_DOWN BIT(28) /* GPIO has external pull-down */ ++#define GPIOD_EXT_PROTECTED BIT(27) /* GPIO is access protected */ + + #define GPIOD_EXT_PULL (BIT(28) | BIT(29)) +-#define GPIOD_SANDBOX_MASK GENMASK(31, 28) ++#define GPIOD_SANDBOX_MASK GENMASK(31, 27) + + /** + * Return the simulated value of a GPIO (used only in sandbox test code) +diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c +index 067c24e5ff4..45334fc3c70 100644 +--- a/cmd/pxe_utils.c ++++ b/cmd/pxe_utils.c +@@ -268,6 +268,9 @@ static void label_destroy(struct pxe_label *label) + if (label->name) + free(label->name); + ++ if (label->kernel_label) ++ free(label->kernel_label); ++ + if (label->kernel) + free(label->kernel); + +@@ -449,6 +452,7 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + int len = 0; + ulong kernel_addr; + void *buf; ++ bool fdt_use_kernel = false, initrd_use_kernel = false; + + label_print(label); + +@@ -466,11 +470,39 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + return 1; + } + +- if (label->initrd) { ++ /* For FIT, the label can be identical to kernel one */ ++ if (label->fdt && !strcmp(label->kernel_label, label->fdt)) ++ fdt_use_kernel = true; ++ ++ if (label->initrd && !strcmp(label->kernel_label, label->initrd)) ++ initrd_use_kernel = true; ++ ++ if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) { ++ printf("Skipping %s for failure retrieving kernel\n", ++ label->name); ++ return 1; ++ } ++ bootm_argv[1] = env_get("kernel_addr_r"); ++ /* for FIT, append the configuration identifier */ ++ if (label->config) { ++ int len = strlen(bootm_argv[1]) + strlen(label->config) + 1; ++ ++ fit_addr = malloc(len); ++ if (!fit_addr) { ++ printf("malloc fail (FIT address)\n"); ++ return 1; ++ } ++ snprintf(fit_addr, len, "%s%s", bootm_argv[1], label->config); ++ bootm_argv[1] = fit_addr; ++ } ++ ++ if (initrd_use_kernel) { ++ bootm_argv[2] = bootm_argv[1]; ++ } else if (label->initrd) { + if (get_relfile_envaddr(cmdtp, label->initrd, "ramdisk_addr_r") < 0) { + printf("Skipping %s for failure retrieving initrd\n", + label->name); +- return 1; ++ goto cleanup; + } + + bootm_argv[2] = initrd_str; +@@ -480,12 +512,6 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + bootm_argc = 3; + } + +- if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) { +- printf("Skipping %s for failure retrieving kernel\n", +- label->name); +- return 1; +- } +- + if (label->ipappend & 0x1) { + sprintf(ip_str, " ip=%s:%s:%s:%s", + env_get("ipaddr"), env_get("serverip"), +@@ -513,7 +539,7 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + strlen(label->append ?: ""), + strlen(ip_str), strlen(mac_str), + sizeof(bootargs)); +- return 1; ++ goto cleanup; + } + + if (label->append) +@@ -528,20 +554,6 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + printf("append: %s\n", finalbootargs); + } + +- bootm_argv[1] = env_get("kernel_addr_r"); +- /* for FIT, append the configuration identifier */ +- if (label->config) { +- int len = strlen(bootm_argv[1]) + strlen(label->config) + 1; +- +- fit_addr = malloc(len); +- if (!fit_addr) { +- printf("malloc fail (FIT address)\n"); +- return 1; +- } +- snprintf(fit_addr, len, "%s%s", bootm_argv[1], label->config); +- bootm_argv[1] = fit_addr; +- } +- + /* + * fdt usage is optional: + * It handles the following scenarios. +@@ -556,12 +568,17 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + * Scenario 2: If there is an fdt_addr specified, pass it along to + * bootm, and adjust argc appropriately. + * +- * Scenario 3: fdt blob is not available. ++ * Scenario 3: If there is an fdtcontroladdr specified, pass it along to ++ * bootm, and adjust argc appropriately. ++ * ++ * Scenario 4: fdt blob is not available. + */ + bootm_argv[3] = env_get("fdt_addr_r"); + + /* if fdt label is defined then get fdt from server */ +- if (bootm_argv[3]) { ++ if (fdt_use_kernel) { ++ bootm_argv[3] = bootm_argv[1]; ++ } else if (bootm_argv[3]) { + char *fdtfile = NULL; + char *fdtfilefree = NULL; + +@@ -646,6 +663,9 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) + if (!bootm_argv[3]) + bootm_argv[3] = env_get("fdt_addr"); + ++ if (!bootm_argv[3]) ++ bootm_argv[3] = env_get("fdtcontroladdr"); ++ + if (bootm_argv[3]) { + if (!bootm_argv[2]) + bootm_argv[2] = "-"; +@@ -1076,6 +1096,10 @@ static int parse_label_kernel(char **c, struct pxe_label *label) + if (err < 0) + return err; + ++ /* copy the kernel label to compare with FDT / INITRD when FIT is used */ ++ label->kernel_label = strdup(label->kernel); ++ if (!label->kernel_label) ++ return -ENOMEM; + s = strstr(label->kernel, "#"); + if (!s) + return 1; +diff --git a/cmd/pxe_utils.h b/cmd/pxe_utils.h +index bf58e15347c..4cb55edf3cd 100644 +--- a/cmd/pxe_utils.h ++++ b/cmd/pxe_utils.h +@@ -28,6 +28,7 @@ + * Create these with the 'label_create' function given below. + * + * name - the name of the menu as given on the 'menu label' line. ++ * kernel_label - the kernel label, including FIT config if present. + * kernel - the path to the kernel file to use for this label. + * append - kernel command line to use when booting this label + * initrd - path to the initrd to use for this label. +@@ -39,6 +40,7 @@ struct pxe_label { + char num[4]; + char *name; + char *menu; ++ char *kernel_label; + char *kernel; + char *config; + char *append; +diff --git a/doc/README.pxe b/doc/README.pxe +index b67151ca510..ba1ac83d2ae 100644 +--- a/doc/README.pxe ++++ b/doc/README.pxe +@@ -169,6 +169,9 @@ fdt - if this label is chosen, use tftp to retrieve the fdt blob + at . it will be stored at the address indicated in + the fdt_addr_r environment variable, and that address will + be passed to bootm. ++ For FIT image, the device tree can be provided with the same value ++ than kernel, including configuration: ++ #[# - if this label is chosen, use tftp to retrieve a fdt blob + relative to . If the fdtfile environment variable +diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst +index 09187a2a88d..0414378a507 100644 +--- a/doc/board/st/stm32mp1.rst ++++ b/doc/board/st/stm32mp1.rst +@@ -92,7 +92,6 @@ The STM32MP13x is a single Cortex-A7 MPU aimed at various applications. + + Currently the following boards are supported: + +- + stm32mp135d-dk.dts + + stm32mp135f-dk.dts + + +@@ -212,7 +211,6 @@ The supported device trees for STM32MP13x (stm32mp13_defconfig) are: + + + dk: Discovery board + +- + stm32mp135d-dk + + stm32mp135f-dk + + +@@ -274,7 +272,7 @@ Build Procedure + + # export KBUILD_OUTPUT=stm32mp13 + # make stm32mp13_defconfig +- # make DEVICE_TREE=stm32mp135d-dk all ++ # make DEVICE_TREE=stm32mp135f-dk all + + DEVICE_TEE selection is optional as stm32mp135f-dk is the default board of the defconfig:: + +diff --git a/drivers/clk/clk-stm32-core.c b/drivers/clk/clk-stm32-core.c +index 9df10250020..22671a0abc3 100644 +--- a/drivers/clk/clk-stm32-core.c ++++ b/drivers/clk/clk-stm32-core.c +@@ -152,92 +152,112 @@ const struct clk_ops stm32_clk_ops = { + .set_rate = stm32_clk_set_rate, + }; + +-#define UBOOT_DM_CLK_STM32_SETCLR_GATE "clk_stm32_setclr_gate" +- + #define RCC_MP_ENCLRR_OFFSET 4 + +-static void clk_setclr_gate_endisable(struct clk *clk, int enable) ++static void clk_stm32_endisable_gate(const struct stm32_gate_cfg *gate_cfg, ++ void __iomem *base, u8 *cpt, int enable) + { +- struct clk_gate *gate = to_clk_gate(clk); ++ void __iomem *addr = base + gate_cfg->reg_off; ++ u8 set_clr = gate_cfg->set_clr ? RCC_MP_ENCLRR_OFFSET : 0; ++ ++ if (enable) { ++ if (*cpt++ > 0) ++ return; ++ ++ if (set_clr) ++ writel(BIT(gate_cfg->bit_idx), addr); ++ else ++ writel(readl(addr) | BIT(gate_cfg->bit_idx), addr); ++ } else { ++ if (--*cpt > 0) ++ return; + +- if (enable) +- writel(BIT(gate->bit_idx), gate->reg); +- else +- writel(BIT(gate->bit_idx), gate->reg + RCC_MP_ENCLRR_OFFSET); ++ if (set_clr) ++ writel(BIT(gate_cfg->bit_idx), addr + set_clr); ++ else ++ writel(readl(addr) & ~BIT(gate_cfg->bit_idx), addr); ++ } + } + +-static int clk_setclr_gate_enable(struct clk *clk) ++static void clk_stm32_gate_endisable(struct clk *clk, int enable) + { +- clk_setclr_gate_endisable(clk, 1); ++ struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk); ++ ++ clk_stm32_endisable_gate(stm32_gate->gate, stm32_gate->base, ++ &stm32_gate->cpt, enable); ++} ++ ++static int clk_stm32_gate_enable(struct clk *clk) ++{ ++ clk_stm32_gate_endisable(clk, 1); + + return 0; + } + +-static int clk_setclr_gate_disable(struct clk *clk) ++static int clk_stm32_gate_disable(struct clk *clk) + { +- clk_setclr_gate_endisable(clk, 0); ++ clk_stm32_gate_endisable(clk, 0); + + return 0; + } + +-const struct clk_ops clk_stm32_setclr_gate_ops = { +- .enable = clk_setclr_gate_enable, +- .disable = clk_setclr_gate_disable, ++static const struct clk_ops clk_stm32_gate_ops = { ++ .enable = clk_stm32_gate_enable, ++ .disable = clk_stm32_gate_disable, + .get_rate = clk_generic_get_rate, + }; + +-struct clk *clk_stm32_register_setclr_gate(struct device *dev, +- const char *name, +- const char *parent_name, +- unsigned long flags, +- void __iomem *reg, u8 bit_idx, +- u8 clk_gate_flags, spinlock_t *lock) ++#define UBOOT_DM_CLK_STM32_GATE "clk_stm32_gate" ++ ++U_BOOT_DRIVER(clk_stm32_gate) = { ++ .name = UBOOT_DM_CLK_STM32_GATE, ++ .id = UCLASS_CLK, ++ .ops = &clk_stm32_gate_ops, ++}; ++ ++struct clk *clk_stm32_gate_register(struct device *dev, ++ const char *name, ++ const char *parent_name, ++ unsigned long flags, ++ void __iomem *base, ++ const struct stm32_gate_cfg *gate_cfg, ++ spinlock_t *lock) + { +- struct clk_gate *gate; ++ struct clk_stm32_gate *stm32_gate; + struct clk *clk; + int ret; + +- /* allocate the gate */ +- gate = kzalloc(sizeof(*gate), GFP_KERNEL); +- if (!gate) ++ stm32_gate = kzalloc(sizeof(*stm32_gate), GFP_KERNEL); ++ if (!stm32_gate) + return ERR_PTR(-ENOMEM); + +- /* struct clk_gate assignments */ +- gate->reg = reg; +- gate->bit_idx = bit_idx; +- gate->flags = clk_gate_flags; ++ stm32_gate->base = base; ++ stm32_gate->gate = gate_cfg; + +- clk = &gate->clk; ++ clk = &stm32_gate->clk; + clk->flags = flags; + +- ret = clk_register(clk, UBOOT_DM_CLK_STM32_SETCLR_GATE, name, +- parent_name); ++ ret = clk_register(clk, UBOOT_DM_CLK_STM32_GATE, name, parent_name); + if (ret) { +- kfree(gate); ++ kfree(stm32_gate); + return ERR_PTR(ret); + } + + return clk; + } + +-U_BOOT_DRIVER(clk_stm32_setclr_gate) = { +- .name = UBOOT_DM_CLK_STM32_SETCLR_GATE, +- .id = UCLASS_CLK, +- .ops = &clk_stm32_setclr_gate_ops, +-}; +- + struct clk *clk_stm32_register_composite(const char *name, + const char * const *parent_names, + int num_parents, + unsigned long flags, + void __iomem *base, +- const struct stm32_mux_cfg *pcfg, ++ const struct stm32_mux_cfg *mcfg, + const struct stm32_div_cfg *dcfg, + const struct stm32_gate_cfg *gcfg) + { + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_mux *mux = NULL; +- struct clk_gate *gate = NULL; ++ struct clk_stm32_gate *gate = NULL; + struct clk_divider *div = NULL; + struct clk *mux_clk = NULL; + const struct clk_ops *mux_ops = NULL; +@@ -246,17 +266,17 @@ struct clk *clk_stm32_register_composite(const char *name, + struct clk *div_clk = NULL; + const struct clk_ops *div_ops = NULL; + +- if (pcfg) { ++ if (mcfg) { + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + +- mux->reg = base + pcfg->reg_off; +- mux->shift = pcfg->shift; +- mux->mask = BIT(pcfg->width) - 1; +- mux->num_parents = pcfg->num_parents; ++ mux->reg = base + mcfg->reg_off; ++ mux->shift = mcfg->shift; ++ mux->mask = BIT(mcfg->width) - 1; ++ mux->num_parents = mcfg->num_parents; + mux->flags = 0; +- mux->parent_names = pcfg->parent_names; ++ mux->parent_names = mcfg->parent_names; + + mux_clk = &mux->clk; + mux_ops = &clk_mux_ops; +@@ -273,6 +293,9 @@ struct clk *clk_stm32_register_composite(const char *name, + div->width = dcfg->width; + div->flags = dcfg->div_flags; + div->table = dcfg->table; ++ ++ div_clk = &div->clk; ++ div_ops = &clk_divider_ops; + } + + if (gcfg) { +@@ -280,15 +303,11 @@ struct clk *clk_stm32_register_composite(const char *name, + if (!gate) + goto fail; + +- gate->reg = base + gcfg->reg_off; +- gate->bit_idx = gcfg->bit_idx; +- gate->flags = gcfg->gate_flags; ++ gate->base = base; ++ gate->gate = gcfg; + + gate_clk = &gate->clk; +- gate_ops = &clk_gate_ops; +- +- if (gcfg->set_clr) +- gate_ops = &clk_stm32_setclr_gate_ops; ++ gate_ops = &clk_stm32_gate_ops; + } + + clk = clk_register_composite(NULL, name, +@@ -317,25 +336,9 @@ struct clk *_clk_stm32_gate_register(struct device *dev, + { + struct stm32_clk_gate_cfg *clk_cfg = cfg->clock_cfg; + const struct stm32_gate_cfg *gate_cfg = &data->gates[clk_cfg->gate_id]; +- struct clk *clk; + +- if (gate_cfg->set_clr) { +- clk = clk_stm32_register_setclr_gate(dev, cfg->name, +- cfg->parent_name, +- cfg->flags, +- base + gate_cfg->reg_off, +- gate_cfg->bit_idx, +- gate_cfg->gate_flags, +- lock); +- } else { +- clk = clk_register_gate(dev, cfg->name, cfg->parent_name, +- cfg->flags, +- base + gate_cfg->reg_off, +- gate_cfg->bit_idx, +- gate_cfg->gate_flags, +- lock); +- } +- return clk; ++ return clk_stm32_gate_register(dev, cfg->name, cfg->parent_name, ++ cfg->flags, base, gate_cfg, lock); + } + + struct clk * +diff --git a/drivers/clk/clk-stm32-core.h b/drivers/clk/clk-stm32-core.h +index 9233b02c04e..79ca27fbaa4 100644 +--- a/drivers/clk/clk-stm32-core.h ++++ b/drivers/clk/clk-stm32-core.h +@@ -74,6 +74,15 @@ int stm32_rcc_init(struct device *dev, + #define NO_STM32_DIV -1 + #define NO_STM32_GATE -1 + ++struct clk_stm32_gate { ++ struct clk clk; ++ void __iomem *base; ++ const struct stm32_gate_cfg *gate; ++ u8 cpt; ++}; ++ ++#define to_clk_stm32_gate(_clk) container_of(_clk, struct clk_stm32_gate, clk) ++ + struct clk * + _clk_stm32_gate_register(struct device *dev, + const struct stm32_clock_match_data *data, +@@ -141,13 +150,7 @@ struct stm32_clk_composite_cfg { + } + + extern const struct clk_ops stm32_clk_ops; +-extern const struct clk_ops clk_stm32_setclr_gate_ops; ++ + ulong clk_stm32_get_rate_by_name(const char *name); + int clk_stm32_get_by_name(const char *name, struct clk **clkp); +-struct clk *clk_stm32_register_setclr_gate(struct device *dev, +- const char *name, +- const char *parent_name, +- unsigned long flags, +- void __iomem *reg, u8 bit_idx, +- u8 clk_gate_flags, spinlock_t *lock); + +diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c +index 57022685e23..aa339f6af2e 100644 +--- a/drivers/clk/clk_scmi.c ++++ b/drivers/clk/clk_scmi.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Copyright (C) 2019-2020 Linaro Limited ++ * Copyright (C) 2019-2022 Linaro Limited + */ + + #define LOG_CATEGORY UCLASS_CLK +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) + { +@@ -53,7 +54,9 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name) + if (ret) + return ret; + +- *name = out.clock_name; ++ *name = strdup(out.clock_name); ++ if (!*name) ++ return -ENOMEM; + + return 0; + } +@@ -152,21 +155,20 @@ static int scmi_clk_probe(struct udevice *dev) + return ret; + + for (i = 0; i < num_clocks; i++) { ++ /* Clock name is allocated from scmi_clk_get_attibute() */ + char *name; + + if (!scmi_clk_get_attibute(dev, i, &name)) { +- char *clock_name = strdup(name); +- + clk = kzalloc(sizeof(*clk), GFP_KERNEL); +- if (!clk || !clock_name) ++ if (!clk) + ret = -ENOMEM; + else + ret = clk_register(clk, dev->driver->name, +- clock_name, dev->name); ++ name, dev->name); + + if (ret) { + free(clk); +- free(clock_name); ++ free(name); + return ret; + } + +diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c +index 8c77777dbe3..903648f8731 100644 +--- a/drivers/gpio/gpio-uclass.c ++++ b/drivers/gpio/gpio-uclass.c +@@ -824,6 +824,7 @@ static const char * const gpio_function[GPIOF_COUNT] = { + "unused", + "unknown", + "func", ++ "protected", + }; + + static int get_function(struct udevice *dev, int offset, bool skip_unused, +@@ -870,26 +871,31 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) + const struct dm_gpio_ops *ops = gpio_get_ops(dev); + struct gpio_dev_priv *priv; + char *str = buf; ++ const char *label; + int func; + int ret; + int len; ++ bool used; + + BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function)); + + *buf = 0; + priv = dev_get_uclass_priv(dev); +- ret = gpio_get_raw_function(dev, offset, NULL); ++ ret = gpio_get_raw_function(dev, offset, &label); + if (ret < 0) + return ret; + func = ret; + len = snprintf(str, buffsize, "%s%d: %s", + priv->bank_name ? priv->bank_name : "", + offset, gpio_function[func]); +- if (func == GPIOF_INPUT || func == GPIOF_OUTPUT || +- func == GPIOF_UNUSED) { +- const char *label; +- bool used; + ++ switch (func) { ++ case GPIOF_FUNC: ++ snprintf(str + len, buffsize - len, " %s", label ? label : ""); ++ break; ++ case GPIOF_INPUT: ++ case GPIOF_OUTPUT: ++ case GPIOF_UNUSED: + ret = ops->get_value(dev, offset); + if (ret < 0) + return ret; +@@ -897,8 +903,9 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) + snprintf(str + len, buffsize - len, ": %d [%c]%s%s", + ret, + used ? 'x' : ' ', +- used ? " " : "", ++ label ? " " : "", + label ? label : ""); ++ break; + } + + return 0; +diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c +index d008fdd2224..cf5dd0e400e 100644 +--- a/drivers/gpio/sandbox.c ++++ b/drivers/gpio/sandbox.c +@@ -192,12 +192,14 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value) + + static int sb_gpio_get_function(struct udevice *dev, unsigned offset) + { ++ if (get_gpio_flag(dev, offset, GPIOD_EXT_PROTECTED)) ++ return GPIOF_PROTECTED; + if (get_gpio_flag(dev, offset, GPIOD_IS_OUT)) + return GPIOF_OUTPUT; + if (get_gpio_flag(dev, offset, GPIOD_IS_IN)) + return GPIOF_INPUT; + +- return GPIOF_INPUT; /*GPIO is not configurated */ ++ return GPIOF_INPUT; /* GPIO is not configured */ + } + + static int sb_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, +@@ -519,6 +521,14 @@ static int sb_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int gpio_idx; + ulong flags; + int function; ++ static const char * const gpio_function[GPIOF_COUNT] = { ++ "input", ++ "output", ++ "unused", ++ "unknown", ++ "func", ++ "protected", ++ }; + + /* look up for the bank which owns the requested pin */ + gpio_dev = sb_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); +@@ -527,9 +537,7 @@ static int sb_pinctrl_get_pin_muxing(struct udevice *dev, + } else { + function = sb_gpio_get_function(gpio_dev, gpio_idx); + flags = *get_gpio_flags(gpio_dev, gpio_idx); +- +- snprintf(buf, size, "gpio %s %s", +- function == GPIOF_OUTPUT ? "output" : "input", ++ snprintf(buf, size, "gpio %s %s", gpio_function[function], + get_flags_string(flags)); + } + +diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c +index e150fe34296..85271f1dadb 100644 +--- a/drivers/gpio/stm32_gpio.c ++++ b/drivers/gpio/stm32_gpio.c +@@ -171,6 +171,7 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) + { + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; ++ ulong drv_data = dev_get_driver_data(dev); + int bits_index; + int mask; + u32 mode; +@@ -178,6 +179,11 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) + if (!stm32_gpio_is_mapped(dev, offset)) + return GPIOF_UNKNOWN; + ++ /* Return 'protected' if the IO is secured */ ++ if ((drv_data & STM32_GPIO_FLAG_SEC_CTRL) && ++ ((readl(®s->seccfgr) >> SECCFG_BITS(offset)) & SECCFG_MSK)) ++ return GPIOF_PROTECTED; ++ + bits_index = MODE_BITS(offset); + mask = MODE_BITS_MASK << bits_index; + +diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c +index bf2a6c9b4bd..836148e4c1a 100644 +--- a/drivers/i2c/stm32f7_i2c.c ++++ b/drivers/i2c/stm32f7_i2c.c +@@ -57,7 +57,6 @@ struct stm32_i2c_regs { + #define STM32_I2C_CR1_PE BIT(0) + + /* STM32 I2C control 2 */ +-#define STM32_I2C_CR2_AUTOEND BIT(25) + #define STM32_I2C_CR2_RELOAD BIT(24) + #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) + #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) +@@ -283,7 +282,7 @@ static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) + } + + static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, +- struct i2c_msg *msg, bool stop) ++ struct i2c_msg *msg) + { + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); +@@ -304,9 +303,8 @@ static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, + cr2 |= STM32_I2C_CR2_SADD7(msg->addr); + } + +- /* Set nb bytes to transfer and reload or autoend bits */ +- cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD | +- STM32_I2C_CR2_AUTOEND); ++ /* Set nb bytes to transfer and reload (if needed) */ ++ cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD); + if (msg->len > STM32_I2C_MAX_LEN) { + cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); + cr2 |= STM32_I2C_CR2_RELOAD; +@@ -327,7 +325,7 @@ static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, + */ + + static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, +- struct i2c_msg *msg, bool stop) ++ struct i2c_msg *msg) + { + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); +@@ -413,7 +411,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) + setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); + + /* Clear control register 2 */ +- setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); ++ clrbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); + } + + return ret; +@@ -433,7 +431,7 @@ static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, + /* Add errors */ + mask |= STM32_I2C_ISR_ERRORS; + +- stm32_i2c_message_start(i2c_priv, msg, stop); ++ stm32_i2c_message_start(i2c_priv, msg); + + while (msg->len) { + /* +@@ -471,7 +469,7 @@ static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, + mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : + STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; + +- stm32_i2c_handle_reload(i2c_priv, msg, stop); ++ stm32_i2c_handle_reload(i2c_priv, msg); + } else if (!bytes_to_rw) { + /* Wait until TC flag is set */ + mask = STM32_I2C_ISR_TC; +@@ -485,9 +483,9 @@ static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, + } + } + +- /* End of transfer, send stop condition */ +- mask = STM32_I2C_CR2_STOP; +- setbits_le32(®s->cr2, mask); ++ /* End of transfer, send stop condition if appropriate */ ++ if (!ret && !(status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))) ++ setbits_le32(®s->cr2, STM32_I2C_CR2_STOP); + + return stm32_i2c_check_end_of_message(i2c_priv); + } +@@ -916,18 +914,19 @@ static int stm32_of_to_plat(struct udevice *dev) + { + const struct stm32_i2c_data *data; + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); +- u32 rise_time, fall_time; + int ret; + + data = (const struct stm32_i2c_data *)dev_get_driver_data(dev); + if (!data) + return -EINVAL; + +- rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", +- STM32_I2C_RISE_TIME_DEFAULT); ++ i2c_priv->setup.rise_time = dev_read_u32_default(dev, ++ "i2c-scl-rising-time-ns", ++ STM32_I2C_RISE_TIME_DEFAULT); + +- fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", +- STM32_I2C_FALL_TIME_DEFAULT); ++ i2c_priv->setup.fall_time = dev_read_u32_default(dev, ++ "i2c-scl-falling-time-ns", ++ STM32_I2C_FALL_TIME_DEFAULT); + + i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0); + if (!dev_read_bool(dev, "i2c-digital-filter")) +diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c +index 1bfe82a0ba9..7eede1434da 100644 +--- a/drivers/mmc/stm32_sdmmc2.c ++++ b/drivers/mmc/stm32_sdmmc2.c +@@ -511,10 +511,12 @@ retry_cmd: + */ + static void stm32_sdmmc2_reset(struct stm32_sdmmc2_plat *plat) + { +- /* Reset */ +- reset_assert(&plat->reset_ctl); +- udelay(2); +- reset_deassert(&plat->reset_ctl); ++ if (reset_valid(&plat->reset_ctl)) { ++ /* Reset */ ++ reset_assert(&plat->reset_ctl); ++ udelay(2); ++ reset_deassert(&plat->reset_ctl); ++ } + + /* init the needed SDMMC register after reset */ + writel(plat->pwr_reg_msk, plat->base + SDMMC_POWER); +@@ -596,13 +598,16 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) + * clk_div > 0 and NEGEDGE = 1 => command and data generated on + * SDMMCCLK falling edge + */ +- if (desired && ((sys_clock > desired) || ++ if (desired && (sys_clock > desired || mmc->ddr_mode || + IS_RISING_EDGE(plat->clk_reg_msk))) { + clk = DIV_ROUND_UP(sys_clock, 2 * desired); + if (clk > SDMMC_CLKCR_CLKDIV_MAX) + clk = SDMMC_CLKCR_CLKDIV_MAX; + } + ++ if (mmc->ddr_mode) ++ clk |= SDMMC_CLKCR_DDR; ++ + if (mmc->bus_width == 4) + clk |= SDMMC_CLKCR_WIDBUS_4; + if (mmc->bus_width == 8) +@@ -670,14 +675,15 @@ static int stm32_sdmmc2_of_to_plat(struct udevice *dev) + if (ret) + return ret; + ++ cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); ++ + ret = clk_get_by_index(dev, 0, &plat->clk); + if (ret) + return ret; + + ret = reset_get_by_index(dev, 0, &plat->reset_ctl); + if (ret) { +- clk_free(&plat->clk); +- return ret; ++ dev_dbg(dev, "No reset provided\n"); + } + + gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio, +diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c +index 9c881011458..e98e0a368a5 100644 +--- a/drivers/pinctrl/pinctrl_stm32.c ++++ b/drivers/pinctrl/pinctrl_stm32.c +@@ -285,7 +285,8 @@ static int stm32_pinctrl_probe(struct udevice *dev) + return 0; + } + +-static int stm32_gpio_config(struct gpio_desc *desc, ++static int stm32_gpio_config(ofnode node, ++ struct gpio_desc *desc, + const struct stm32_gpio_ctl *ctl) + { + struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); +@@ -328,6 +329,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, + index = desc->offset; + clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + ++ uc_priv->name[desc->offset] = strdup(ofnode_get_name(node)); ++ + hwspinlock_unlock(&ctrl_priv->hws); + + return 0; +@@ -422,7 +425,7 @@ static int stm32_pinctrl_config(ofnode node) + if (rv) + return rv; + desc.offset = gpio_dsc.pin; +- rv = stm32_gpio_config(&desc, &gpio_ctl); ++ rv = stm32_gpio_config(node, &desc, &gpio_ctl); + log_debug("rv = %d\n\n", rv); + if (rv) + return rv; +diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c +index 4c28a69b989..5856e898a8b 100644 +--- a/drivers/usb/host/ehci-generic.c ++++ b/drivers/usb/host/ehci-generic.c +@@ -23,14 +23,12 @@ + */ + struct generic_ehci { + struct ehci_ctrl ctrl; +- struct clk *clocks; +- struct reset_ctl *resets; ++ struct clk_bulk clocks; ++ struct reset_ctl_bulk resets; + struct phy phy; + #ifdef CONFIG_DM_REGULATOR + struct udevice *vbus_supply; + #endif +- int clock_count; +- int reset_count; + }; + + #ifdef CONFIG_DM_REGULATOR +@@ -81,68 +79,31 @@ static int ehci_usb_probe(struct udevice *dev) + struct generic_ehci *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; +- int i, err, ret, clock_nb, reset_nb; ++ int err, ret; + + err = 0; +- priv->clock_count = 0; +- clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks", +- "#clock-cells", 0); +- if (clock_nb > 0) { +- priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), +- GFP_KERNEL); +- if (!priv->clocks) +- return -ENOMEM; +- +- for (i = 0; i < clock_nb; i++) { +- err = clk_get_by_index(dev, i, &priv->clocks[i]); +- +- if (err < 0) +- break; +- err = clk_enable(&priv->clocks[i]); +- if (err && err != -ENOSYS) { +- dev_err(dev, "failed to enable clock %d\n", i); +- clk_free(&priv->clocks[i]); +- goto clk_err; +- } +- priv->clock_count++; +- } +- } else { +- if (clock_nb != -ENOENT) { +- dev_err(dev, "failed to get clock phandle(%d)\n", +- clock_nb); +- return clock_nb; +- } ++ ret = clk_get_bulk(dev, &priv->clocks); ++ if (ret) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return ret; + } + +- priv->reset_count = 0; +- reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets", +- "#reset-cells", 0); +- if (reset_nb > 0) { +- priv->resets = devm_kcalloc(dev, reset_nb, +- sizeof(struct reset_ctl), +- GFP_KERNEL); +- if (!priv->resets) +- return -ENOMEM; +- +- for (i = 0; i < reset_nb; i++) { +- err = reset_get_by_index(dev, i, &priv->resets[i]); +- if (err < 0) +- break; +- +- if (reset_deassert(&priv->resets[i])) { +- dev_err(dev, "failed to deassert reset %d\n", +- i); +- reset_free(&priv->resets[i]); +- goto reset_err; +- } +- priv->reset_count++; +- } +- } else { +- if (reset_nb != -ENOENT) { +- dev_err(dev, "failed to get reset phandle(%d)\n", +- reset_nb); +- goto clk_err; +- } ++ err = clk_enable_bulk(&priv->clocks); ++ if (err) { ++ dev_err(dev, "Failed to enable clocks\n"); ++ goto clk_err; ++ } ++ ++ err = reset_get_bulk(dev, &priv->resets); ++ if (err) { ++ dev_err(dev, "Failed to get resets\n"); ++ goto clk_err; ++ } ++ ++ err = reset_deassert_bulk(&priv->resets); ++ if (err) { ++ dev_err(dev, "Failed to get deassert resets\n"); ++ goto reset_err; + } + + err = ehci_enable_vbus_supply(dev); +@@ -174,13 +135,13 @@ regulator_err: + dev_err(dev, "failed to disable VBUS supply\n"); + + reset_err: +- ret = reset_release_all(priv->resets, priv->reset_count); ++ ret = reset_release_bulk(&priv->resets); + if (ret) +- dev_err(dev, "failed to assert all resets\n"); ++ dev_err(dev, "failed to release resets\n"); + clk_err: +- ret = clk_release_all(priv->clocks, priv->clock_count); ++ ret = clk_release_bulk(&priv->clocks); + if (ret) +- dev_err(dev, "failed to disable all clocks\n"); ++ dev_err(dev, "failed to release clocks\n"); + + return err; + } +@@ -202,11 +163,11 @@ static int ehci_usb_remove(struct udevice *dev) + if (ret) + return ret; + +- ret = reset_release_all(priv->resets, priv->reset_count); ++ ret = reset_release_bulk(&priv->resets); + if (ret) + return ret; + +- return clk_release_all(priv->clocks, priv->clock_count); ++ return clk_release_bulk(&priv->clocks); + } + + static const struct udevice_id ehci_usb_ids[] = { +diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c +index 134abd93e19..5871ac7c4ff 100644 +--- a/drivers/video/stm32/stm32_dsi.c ++++ b/drivers/video/stm32/stm32_dsi.c +@@ -433,19 +433,17 @@ static int stm32_dsi_probe(struct udevice *dev) + return -EINVAL; + } + +- if (IS_ENABLED(CONFIG_DM_REGULATOR)) { +- ret = device_get_supply_regulator(dev, "phy-dsi-supply", +- &priv->vdd_reg); +- if (ret && ret != -ENOENT) { +- dev_err(dev, "Warning: cannot get phy dsi supply\n"); +- return -ENODEV; +- } ++ ret = device_get_supply_regulator(dev, "phy-dsi-supply", ++ &priv->vdd_reg); ++ if (ret && ret != -ENOENT) { ++ dev_err(dev, "Warning: cannot get phy dsi supply\n"); ++ return -ENODEV; ++ } + +- if (ret != -ENOENT) { +- ret = regulator_set_enable(priv->vdd_reg, true); +- if (ret) +- return ret; +- } ++ if (ret != -ENOENT) { ++ ret = regulator_set_enable(priv->vdd_reg, true); ++ if (ret) ++ return ret; + } + + ret = clk_get_by_name(device->dev, "pclk", &clk); +@@ -493,8 +491,7 @@ static int stm32_dsi_probe(struct udevice *dev) + err_clk: + clk_disable(&clk); + err_reg: +- if (IS_ENABLED(CONFIG_DM_REGULATOR)) +- regulator_set_enable(priv->vdd_reg, false); ++ regulator_set_enable(priv->vdd_reg, false); + + return ret; + } +diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c +index 1e6f07ff4b0..438627dc36c 100644 +--- a/drivers/video/video_bmp.c ++++ b/drivers/video/video_bmp.c +@@ -338,9 +338,9 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, + for (i = 0; i < height; ++i) { + for (j = 0; j < width; j++) { + if (bpix == 16) { +- /* 16bit 555RGB format */ +- *(u16 *)fb = ((bmap[2] >> 3) << 10) | +- ((bmap[1] >> 3) << 5) | ++ /* 16bit 565RGB format */ ++ *(u16 *)fb = ((bmap[2] >> 3) << 11) | ++ ((bmap[1] >> 2) << 5) | + (bmap[0] >> 3); + bmap += 3; + fb += 2; +diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h +index e33cde7abdd..f29d231fb65 100644 +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -110,6 +110,7 @@ enum gpio_func_t { + GPIOF_UNUSED, /* Not claimed */ + GPIOF_UNKNOWN, /* Not known */ + GPIOF_FUNC, /* Not used as a GPIO */ ++ GPIOF_PROTECTED, /* Protected access */ + + GPIOF_COUNT, + }; +diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h +index d3567df326c..201b1df762e 100644 +--- a/include/power/stpmic1.h ++++ b/include/power/stpmic1.h +@@ -23,12 +23,9 @@ + + /* BUCKS_MRST_CR */ + #define STPMIC1_MRST_BUCK(buck) BIT(buck) +-#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ +- STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) + + /* LDOS_MRST_CR */ + #define STPMIC1_MRST_LDO(ldo) BIT(ldo) +-#define STPMIC1_MRST_LDO_DEBUG 0 + + /* BUCKx_MAIN_CR (x=1...4) */ + #define STPMIC1_BUCK_ENA BIT(0) +diff --git a/test/dm/gpio.c b/test/dm/gpio.c +index 33ae98701f4..f63c4b99797 100644 +--- a/test/dm/gpio.c ++++ b/test/dm/gpio.c +@@ -113,6 +113,11 @@ static int dm_test_gpio(struct unit_test_state *uts) + ut_asserteq_str("a", name); + ut_asserteq(20, offset_count); + ++ /* Flag a pin as protected, and check its status */ ++ ut_assertok(gpio_lookup_name("a1", &dev, &offset, &gpio)); ++ sandbox_gpio_set_flags(dev, 1, GPIOD_EXT_PROTECTED); ++ ut_asserteq(GPIOF_PROTECTED, gpio_get_raw_function(dev, 1, NULL)); ++ + /* add gpio hog tests */ + ut_assertok(gpio_hog_lookup_name("hog_input_active_low", &desc)); + ut_asserteq(GPIOD_IS_IN | GPIOD_ACTIVE_LOW, desc->flags); +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch new file mode 100644 index 0000000..e16b033 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch @@ -0,0 +1,4567 @@ +From 76a6a7e3dca63b7649695ebb3eeee0af17454cf7 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Thu, 3 Nov 2022 11:16:18 +0100 +Subject: [PATCH 9/9] ARM v2021.10-stm32mp-r2 DEVICETREE + +Signed-off-by: Romuald JEANNE +--- + arch/arm/dts/Makefile | 2 - + arch/arm/dts/stm32mp131.dtsi | 104 ++- + arch/arm/dts/stm32mp133.dtsi | 15 +- + arch/arm/dts/stm32mp135d-dk-u-boot.dtsi | 70 -- + arch/arm/dts/stm32mp135d-dk.dts | 687 ------------------ + arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 66 +- + arch/arm/dts/stm32mp135f-dk.dts | 38 +- + arch/arm/dts/stm32mp13xc.dtsi | 3 + + arch/arm/dts/stm32mp13xf.dtsi | 3 + + arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi | 12 +- + arch/arm/dts/stm32mp15-pinctrl.dtsi | 140 ++-- + arch/arm/dts/stm32mp151.dtsi | 132 +++- + arch/arm/dts/stm32mp157a-avenger96.dts | 8 - + arch/arm/dts/stm32mp157a-dhcor-avenger96.dts | 38 + + arch/arm/dts/stm32mp157c-dk2.dts | 1 - + arch/arm/dts/stm32mp157f-dk2.dts | 1 - + arch/arm/dts/stm32mp15xc.dtsi | 3 + + arch/arm/dts/stm32mp15xf.dtsi | 3 + + arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 162 +---- + arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi | 165 +++++ + .../dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi | 4 + + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 14 +- + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi | 325 +++++++++ + .../dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi | 6 +- + arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts | 88 +-- + arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi | 147 ++++ + ...-dhcom.dtsi => stm32mp15xx-dhcom-som.dtsi} | 391 ++++++---- + arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 43 +- + .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 2 + + arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 202 +---- + arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi | 451 ++++++++++++ + arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 7 +- + ...-io3v3.dtsi => stm32mp15xx-dhcor-som.dtsi} | 30 +- + arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 8 + + arch/arm/dts/stm32mp15xx-dkx.dtsi | 27 +- + arch/arm/dts/stm32mp15xx-edx.dtsi | 18 +- + arch/arm/dts/stm32mp15xx-evx.dtsi | 12 +- + 37 files changed, 1874 insertions(+), 1554 deletions(-) + delete mode 100644 arch/arm/dts/stm32mp135d-dk-u-boot.dtsi + delete mode 100644 arch/arm/dts/stm32mp135d-dk.dts + delete mode 100644 arch/arm/dts/stm32mp157a-avenger96.dts + create mode 100644 arch/arm/dts/stm32mp157a-dhcor-avenger96.dts + create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi + create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi + create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi + rename arch/arm/dts/{stm32mp15xx-dhcom.dtsi => stm32mp15xx-dhcom-som.dtsi} (56%) + create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi + rename arch/arm/dts/{stm32mp15xx-dhcor-io3v3.dtsi => stm32mp15xx-dhcor-som.dtsi} (91%) + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index cb6e07726e3..c202571f34a 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1075,11 +1075,9 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb + dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb + + dtb-$(CONFIG_STM32MP13x) += \ +- stm32mp135d-dk.dtb \ + stm32mp135f-dk.dtb + + dtb-$(CONFIG_STM32MP15x) += \ +- stm32mp157a-avenger96.dtb \ + stm32mp157a-dk1.dtb \ + stm32mp157a-ed1.dtb \ + stm32mp157a-ev1.dtb \ +diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi +index d19cf69401d..8121ddc97f1 100644 +--- a/arch/arm/dts/stm32mp131.dtsi ++++ b/arch/arm/dts/stm32mp131.dtsi +@@ -24,6 +24,7 @@ + clock-names = "cpu"; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; ++ #cooling-cells = <2>; + }; + }; + +@@ -48,11 +49,13 @@ + }; + + firmware { +- optee { ++ optee: optee { + method = "smc"; + compatible = "linaro,optee-tz"; + interrupt-parent = <&intc>; + interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; + }; + + scmi: scmi { +@@ -148,7 +151,12 @@ + thermal-sensors = <&dts>; + + trips { +- cpu-crit { ++ cpu_alert: cpu-alert0 { ++ temperature = <95000>; ++ hysteresis = <10000>; ++ type = "passive"; ++ }; ++ cpu_crit: cpu-crit0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; +@@ -156,6 +164,10 @@ + }; + + cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = <&cpu0 1 1>; ++ }; + }; + }; + }; +@@ -836,6 +848,8 @@ + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; +@@ -844,6 +858,23 @@ + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; ++ ++ channel@13 { ++ reg = <13>; ++ label = "vrefint"; ++ }; ++ channel@14 { ++ reg = <14>; ++ label = "vddcore"; ++ }; ++ channel@16 { ++ reg = <16>; ++ label = "vddcpu"; ++ }; ++ channel@17 { ++ reg = <17>; ++ label = "vddq_ddr"; ++ }; + }; + }; + +@@ -1152,10 +1183,59 @@ + }; + + exti: interrupt-controller@5000d000 { +- compatible = "st,stm32mp13-exti", "syscon"; ++ compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; ++ #address-cells = <0>; + reg = <0x5000d000 0x400>; ++ ++ exti-interrupt-map { ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ interrupt-map-mask = <0xffffffff 0>; ++ interrupt-map = ++ <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, ++ <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, ++ <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, ++ <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, ++ <5 0 &intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, ++ <6 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, ++ <7 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, ++ <8 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <9 0 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, ++ <10 0 &intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, ++ <11 0 &intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, ++ <12 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, ++ <13 0 &intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, ++ <14 0 &intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, ++ <15 0 &intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, ++ <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, ++ <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, ++ <21 0 &intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, ++ <22 0 &intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, ++ <23 0 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, ++ <24 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, ++ <25 0 &intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, ++ <26 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, ++ <27 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, ++ <28 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, ++ <29 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, ++ <30 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, ++ <31 0 &intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, ++ <32 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, ++ <33 0 &intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, ++ <42 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, ++ <43 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, ++ <44 0 &intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, ++ <47 0 &intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, ++ <48 0 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, ++ <50 0 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, ++ <52 0 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, ++ <53 0 &intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, ++ <68 0 &intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, ++ <70 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; ++ }; + }; + + syscfg: syscon@50020000 { +@@ -1406,12 +1486,6 @@ + status = "disabled"; + }; + +- stmmac_axi_config_0: stmmac-axi-config { +- snps,wr_osr_lmt = <0x7>; +- snps,rd_osr_lmt = <0x7>; +- snps,blen = <0 0 0 0 16 8 4>; +- }; +- + eth1: eth1@5800a000 { + compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac"; + reg = <0x5800a000 0x2000>; +@@ -1432,11 +1506,15 @@ + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; +- snps,axi-config = <&stmmac_axi_config_0>; ++ snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; +- power-domains = <&pd_core>; +- wakeup-source; + status = "disabled"; ++ ++ stmmac_axi_config_1: stmmac-axi-config { ++ snps,wr_osr_lmt = <0x7>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,blen = <0 0 0 0 16 8 4>; ++ }; + }; + + usbh_ohci: usbh-ohci@5800c000 { +@@ -1543,7 +1621,7 @@ + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ +- pinctrl: pin-controller@50002000 { ++ pinctrl: pinctrl@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; +diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi +index e00c30cb6e4..b46e3891364 100644 +--- a/arch/arm/dts/stm32mp133.dtsi ++++ b/arch/arm/dts/stm32mp133.dtsi +@@ -23,6 +23,8 @@ + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; +@@ -31,6 +33,11 @@ + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; ++ ++ channel@18 { ++ reg = <18>; ++ label = "vrefint"; ++ }; + }; + }; + +@@ -79,9 +86,15 @@ + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; +- snps,axi-config = <&stmmac_axi_config_0>; ++ snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + status = "disabled"; ++ ++ stmmac_axi_config_2: stmmac-axi-config { ++ snps,wr_osr_lmt = <0x7>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,blen = <0 0 0 0 16 8 4>; ++ }; + }; + }; + }; +diff --git a/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi +deleted file mode 100644 +index b969add65c3..00000000000 +--- a/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi ++++ /dev/null +@@ -1,70 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +-/* +- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved +- */ +- +-#include "stm32mp13-u-boot.dtsi" +- +-/ { +- aliases { +- mmc0 = &sdmmc1; +- usb0 = &usbotg_hs; +- }; +- +- config { +- u-boot,boot-led = "led-blue"; +- u-boot,error-led = "led-red"; +- u-boot,mmc-env-partition = "u-boot-env"; +- st,adc_usb_pd = <&adc1 6>, <&adc1 12>; +- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- }; +- +- leds { +- led-red { +- color = ; +- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- }; +- }; +-}; +- +-&adc_1 { +- status = "okay"; +-}; +- +-&panel_rgb { +- compatible = "rocktech,rk043fn48h","simple-panel"; +- +- display-timings { +- timing@0 { +- clock-frequency = <10000000>; +- hactive = <480>; +- vactive = <272>; +- hfront-porch = <10>; +- hback-porch = <10>; +- hsync-len = <52>; +- vfront-porch = <10>; +- vback-porch = <10>; +- vsync-len = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +-}; +- +-&uart4 { +- u-boot,dm-pre-reloc; +-}; +- +-&uart4_pins_a { +- u-boot,dm-pre-reloc; +- pins1 { +- u-boot,dm-pre-reloc; +- }; +- pins2 { +- u-boot,dm-pre-reloc; +- }; +-}; +diff --git a/arch/arm/dts/stm32mp135d-dk.dts b/arch/arm/dts/stm32mp135d-dk.dts +deleted file mode 100644 +index d56874fb3dd..00000000000 +--- a/arch/arm/dts/stm32mp135d-dk.dts ++++ /dev/null +@@ -1,687 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved +- * Author: Alexandre Torgue for STMicroelectronics. +- */ +- +-/dts-v1/; +- +-#include +-#include +-#include +-#include +-#include "stm32mp135.dtsi" +-#include "stm32mp13xd.dtsi" +-#include "stm32mp13-pinctrl.dtsi" +- +-/ { +- model = "STMicroelectronics STM32MP135D-DK Discovery Board"; +- compatible = "st,stm32mp135d-dk", "st,stm32mp135"; +- +- aliases { +- ethernet0 = ð1; +- ethernet1 = ð2; +- serial0 = &uart4; +- serial1 = &usart1; +- serial2 = &uart8; +- serial3 = &usart2; +- }; +- +- chosen { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- stdout-path = "serial0:115200n8"; +- +- framebuffer { +- compatible = "simple-framebuffer"; +- clocks = <&rcc LTDC_PX>; +- status = "disabled"; +- }; +- }; +- +- clocks { +- clk_ext_camera: clk-ext-camera { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- clk_mco1: clk-mco1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- }; +- +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xc0000000 0x20000000>; +- }; +- +- gpio-keys { +- compatible = "gpio-keys"; +- +- user-pa13 { +- label = "User-PA13"; +- linux,code = ; +- gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- led-blue { +- function = LED_FUNCTION_HEARTBEAT; +- color = ; +- gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- }; +- +- reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- optee_framebuffer@dd000000 { +- reg = <0xdd000000 0x1000000>; +- no-map; +- }; +- +- optee@de000000 { +- reg = <0xde000000 0x2000000>; +- no-map; +- }; +- }; +- +- v3v3_ao: v3v3_ao { +- compatible = "regulator-fixed"; +- regulator-name = "v3v3_ao"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- }; +- +- panel_backlight: panel-backlight { +- compatible = "gpio-backlight"; +- gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; +- default-on; +- default-brightness-level = <0>; +- status = "okay"; +- }; +- +- panel_rgb: panel-rgb { +- compatible = "rocktech,rk043fn48h", "panel-dpi"; +- enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; +- backlight = <&panel_backlight>; +- power-supply = <&scmi_v3v3_sw>; +- data-mapping = "bgr666"; +- status = "okay"; +- +- width-mm = <105>; +- height-mm = <67>; +- +- port { +- panel_in_rgb: endpoint { +- remote-endpoint = <<dc_out_rgb>; +- }; +- }; +- +- panel-timing { +- clock-frequency = <10000000>; +- hactive = <480>; +- vactive = <272>; +- hsync-len = <52>; +- hfront-porch = <10>; +- hback-porch = <10>; +- vsync-len = <10>; +- vfront-porch = <10>; +- vback-porch = <10>; +- hsync-active = <0>; +- vsync-active = <0>; +- de-active = <1>; +- pixelclk-active = <1>; +- }; +- }; +- +- wifi_pwrseq: wifi-pwrseq { +- compatible = "mmc-pwrseq-simple"; +- reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>; +- }; +-}; +- +-&adc_1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&adc1_usb_cc_pins_a>; +- vdda-supply = <&scmi_vdd_adc>; +- vref-supply = <&scmi_vdd_adc>; +- status = "okay"; +- adc1: adc@0 { +- /* +- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. +- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: +- * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. +- * Use arbitrary margin here (e.g. 5us). +- */ +- st,min-sample-time-nsecs = <5000>; +- /* USB Type-C CC1 & CC2 */ +- st,adc-channels = <6 12>; +- status = "okay"; +- }; +-}; +- +-&crc1 { +- status = "okay"; +-}; +- +-&dcmipp { +- status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcmipp_pins_a>; +- pinctrl-1 = <&dcmipp_sleep_pins_a>; +- port { +- dcmipp_0: endpoint { +- remote-endpoint = <&mipid02_2>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <0>; +- pclk-max-frequency = <120000000>; +- }; +- }; +-}; +- +-&dma1 { +- sram = <&dma_pool>; +-}; +- +-&dma2 { +- sram = <&dma_pool>; +-}; +- +-&dts { +- status = "okay"; +-}; +- +-ð1 { +- status = "okay"; +- pinctrl-0 = <ð1_rmii_pins_a>; +- pinctrl-1 = <ð1_rmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rmii"; +- max-speed = <100>; +- phy-handle = <&phy0_eth1>; +- nvmem-cells = <ðernet_mac1_address>; +- nvmem-cell-names = "mac-address"; +- +- mdio1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- +- phy0_eth1: ethernet-phy@0 { +- compatible = "ethernet-phy-id0007.c131"; +- reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; +- reg = <0>; +- interrupt-parent = <&gpioi>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +-}; +- +-ð2 { +- status = "okay"; +- pinctrl-0 = <ð2_rmii_pins_a>; +- pinctrl-1 = <ð2_rmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rmii"; +- max-speed = <100>; +- phy-handle = <&phy0_eth2>; +- st,ext-phyclk; +- phy-supply = <&scmi_v3v3_sw>; +- nvmem-cells = <ðernet_mac2_address>; +- nvmem-cell-names = "mac-address"; +- +- mdio1 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0_eth2: ethernet-phy@0 { +- compatible = "ethernet-phy-id0007.c131"; +- reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>; +- reg = <0>; +- }; +- }; +-}; +- +-&i2c1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c1_pins_a>; +- pinctrl-1 = <&i2c1_sleep_pins_a>; +- i2c-scl-rising-time-ns = <96>; +- i2c-scl-falling-time-ns = <3>; +- clock-frequency = <1000000>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- mcp23017: pinctrl@21 { +- compatible = "microchip,mcp23017"; +- reg = <0x21>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <12 IRQ_TYPE_LEVEL_LOW>; +- interrupt-parent = <&gpiog>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcp23017_pins_a>; +- interrupt-controller; +- #interrupt-cells = <2>; +- microchip,irq-mirror; +- }; +- +- stm32g0@53 { +- compatible = "st,stm32g0-typec"; +- reg = <0x53>; +- /* Alert pin on PI2 */ +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpioi>; +- /* Internal pull-up on PI2 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&stm32g0_intn_pins_a>; +- firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; +- power-domains = <&pd_core>; +- wakeup-source; +- connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- +- port { +- con_usb_c_g0_ep: endpoint { +- remote-endpoint = <&usbotg_hs_ep>; +- }; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_pins_a>; +- pinctrl-1 = <&i2c5_sleep_pins_a>; +- i2c-scl-rising-time-ns = <170>; +- i2c-scl-falling-time-ns = <5>; +- clock-frequency = <400000>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- gc2145: gc2145@3c { +- compatible = "galaxycore,gc2145"; +- reg = <0x3c>; +- clocks = <&clk_ext_camera>; +- IOVDD-supply = <&scmi_v3v3_sw>; +- AVDD-supply = <&scmi_v3v3_sw>; +- DVDD-supply = <&scmi_v3v3_sw>; +- powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- status = "okay"; +- +- port { +- gc2145_ep: endpoint { +- remote-endpoint = <&mipid02_0>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- goodix: goodix_ts@5d { +- compatible = "goodix,gt911"; +- reg = <0x5d>; +- pinctrl-names = "default"; +- pinctrl-0 = <&goodix_pins_a>; +- interrupt-parent = <&gpiof>; +- interrupts = <5 IRQ_TYPE_EDGE_FALLING>; +- reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; +- AVDD28-supply = <&scmi_v3v3_sw>; +- VDDIO-supply = <&scmi_v3v3_sw>; +- touchscreen-size-x = <480>; +- touchscreen-size-y = <272>; +- status = "okay" ; +- }; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- clocks = <&clk_ext_camera>; +- clock-names = "xclk"; +- DOVDD-supply = <&scmi_v3v3_sw>; +- status = "disabled"; +- powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- +- port { +- ov5640_0: endpoint { +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- +- stmipi: stmipi@14 { +- compatible = "st,st-mipid02"; +- reg = <0x14>; +- status = "okay"; +- clocks = <&clk_mco1>; +- clock-names = "xclk"; +- VDDE-supply = <&scmi_v1v8_periph>; +- VDDIN-supply = <&scmi_v1v8_periph>; +- reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- port@0 { +- reg = <0>; +- +- mipid02_0: endpoint { +- data-lanes = <1 2>; +- lane-polarities = <0 0 0>; +- remote-endpoint = <&gc2145_ep>; +- }; +- }; +- port@2 { +- reg = <2>; +- +- mipid02_2: endpoint { +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <0>; +- remote-endpoint = <&dcmipp_0>; +- }; +- }; +- }; +- }; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-<dc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <<dc_pins_a>; +- pinctrl-1 = <<dc_sleep_pins_a>; +- status = "okay"; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- ltdc_out_rgb: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&panel_in_rgb>; +- }; +- }; +-}; +- +-&rtc { +- st,lsco = ; +- pinctrl-0 = <&rtc_out2_rmp_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&scmi_regu { +- scmi_vddcpu: voltd-vddcpu { +- voltd-name = "vddcpu"; +- regulator-name = "vddcpu"; +- }; +- scmi_vdd: voltd-vdd { +- voltd-name = "vdd"; +- regulator-name = "vdd"; +- }; +- scmi_vddcore: voltd-vddcore { +- voltd-name = "vddcore"; +- regulator-name = "vddcore"; +- }; +- scmi_vdd_adc: voltd-vdd_adc { +- voltd-name = "vdd_adc"; +- regulator-name = "vdd_adc"; +- }; +- scmi_vdd_usb: voltd-vdd_usb { +- voltd-name = "vdd_usb"; +- regulator-name = "vdd_usb"; +- }; +- scmi_vdd_sd: voltd-vdd_sd { +- voltd-name = "vdd_sd"; +- regulator-name = "vdd_sd"; +- }; +- scmi_v1v8_periph: voltd-v1v8_periph { +- voltd-name = "v1v8_periph"; +- regulator-name = "v1v8_periph"; +- }; +- scmi_v3v3_sw: voltd-v3v3_sw { +- voltd-name = "v3v3_sw"; +- regulator-name = "v3v3_sw"; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; +- cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&scmi_vdd_sd>; +- status = "okay"; +-}; +- +-/* Wifi */ +-&sdmmc2 { +- arm,primecell-periphid = <0x10153180>; +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; +- non-removable; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3_ao>; +- mmc-pwrseq = <&wifi_pwrseq>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- brcmf: bcrmf@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; +-}; +- +-&spi5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&spi5_pins_a>; +- pinctrl-1 = <&spi5_sleep_pins_a>; +- status = "disabled"; +-}; +- +-&sram { +- dma_pool: dma-sram@0 { +- reg = <0x0 0x4000>; +- pool; +- }; +-}; +- +-&timers3 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm3_pins_a>; +- pinctrl-1 = <&pwm3_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@2 { +- status = "okay"; +- }; +-}; +- +-&timers4 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm4_pins_a>; +- pinctrl-1 = <&pwm4_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@3 { +- status = "okay"; +- }; +-}; +- +-&timers8 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm8_pins_a>; +- pinctrl-1 = <&pwm8_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@7 { +- status = "okay"; +- }; +-}; +- +-&timers14 { +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm14_pins_a>; +- pinctrl-1 = <&pwm14_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@13 { +- status = "okay"; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart4_pins_a>; +- pinctrl-1 = <&uart4_sleep_pins_a>; +- pinctrl-2 = <&uart4_idle_pins_a>; +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "okay"; +-}; +- +-&uart8 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&uart8_pins_a>; +- pinctrl-1 = <&uart8_sleep_pins_a>; +- pinctrl-2 = <&uart8_idle_pins_a>; +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +-}; +- +-&usart1 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&usart1_pins_a>; +- pinctrl-1 = <&usart1_sleep_pins_a>; +- pinctrl-2 = <&usart1_idle_pins_a>; +- uart-has-rtscts; +- status = "disabled"; +-}; +- +-/* Bluetooth */ +-&usart2 { +- pinctrl-names = "default", "sleep", "idle"; +- pinctrl-0 = <&usart2_pins_a>; +- pinctrl-1 = <&usart2_sleep_pins_a>; +- pinctrl-2 = <&usart2_idle_pins_a>; +- uart-has-rtscts; +- status = "okay"; +- +- bluetooth { +- shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>; +- compatible = "brcm,bcm43438-bt"; +- max-speed = <3000000>; +- vbat-supply = <&v3v3_ao>; +- vddio-supply = <&v3v3_ao>; +- }; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- usb-role-switch; +- status = "okay"; +- port { +- usbotg_hs_ep: endpoint { +- remote-endpoint = <&con_usb_c_g0_ep>; +- }; +- }; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&scmi_vdd_usb>; +- st,current-boost-microamp = <1000>; +- st,decrease-hs-slew-rate; +- st,tune-hs-dc-level = <2>; +- st,enable-hs-rftime-reduction; +- st,trim-hs-current = <11>; +- st,trim-hs-impedance = <2>; +- st,tune-squelch-level = <1>; +- st,enable-hs-rx-gain-eq; +- st,no-hs-ftime-ctrl; +- st,no-lsfs-sc; +- +- /* +- * Hack to keep hub active if wakeup source is enabled +- * otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled +- */ +- connector { +- compatible = "usb-a-connector"; +- vbus-supply = <&scmi_v3v3_sw>; +- }; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&scmi_vdd_usb>; +- st,current-boost-microamp = <1000>; +- st,decrease-hs-slew-rate; +- st,tune-hs-dc-level = <2>; +- st,enable-hs-rftime-reduction; +- st,trim-hs-current = <11>; +- st,trim-hs-impedance = <2>; +- st,tune-squelch-level = <1>; +- st,enable-hs-rx-gain-eq; +- st,no-hs-ftime-ctrl; +- st,no-lsfs-sc; +-}; +diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +index 2b21966ece4..b969add65c3 100644 +--- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +@@ -3,4 +3,68 @@ + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + */ + +-#include "stm32mp135d-dk-u-boot.dtsi" ++#include "stm32mp13-u-boot.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc1; ++ usb0 = &usbotg_hs; ++ }; ++ ++ config { ++ u-boot,boot-led = "led-blue"; ++ u-boot,error-led = "led-red"; ++ u-boot,mmc-env-partition = "u-boot-env"; ++ st,adc_usb_pd = <&adc1 6>, <&adc1 12>; ++ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ }; ++ ++ leds { ++ led-red { ++ color = ; ++ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++&adc_1 { ++ status = "okay"; ++}; ++ ++&panel_rgb { ++ compatible = "rocktech,rk043fn48h","simple-panel"; ++ ++ display-timings { ++ timing@0 { ++ clock-frequency = <10000000>; ++ hactive = <480>; ++ vactive = <272>; ++ hfront-porch = <10>; ++ hback-porch = <10>; ++ hsync-len = <52>; ++ vfront-porch = <10>; ++ vback-porch = <10>; ++ vsync-len = <10>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ de-active = <1>; ++ pixelclk-active = <1>; ++ }; ++ }; ++}; ++ ++&uart4 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&uart4_pins_a { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts +index ef2d9f13748..a2735571286 100644 +--- a/arch/arm/dts/stm32mp135f-dk.dts ++++ b/arch/arm/dts/stm32mp135f-dk.dts +@@ -151,6 +151,18 @@ + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>; + }; ++ ++ wake_up { ++ compatible = "gpio-keys"; ++ status = "okay"; ++ ++ button { ++ label = "wake-up"; ++ linux,code = ; ++ interrupts-extended = <&optee 0>; ++ status = "okay"; ++ }; ++ }; + }; + + &adc_1 { +@@ -160,16 +172,21 @@ + vref-supply = <&scmi_vdd_adc>; + status = "okay"; + adc1: adc@0 { ++ status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ +- st,min-sample-time-nsecs = <5000>; +- /* USB Type-C CC1 & CC2 */ +- st,adc-channels = <6 12>; +- status = "okay"; ++ channel@6 { ++ reg = <6>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@12 { ++ reg = <12>; ++ st,min-sample-time-ns = <5000>; ++ }; + }; + }; + +@@ -230,6 +247,7 @@ + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg = <0>; ++ wakeup-source; + }; + }; + }; +@@ -288,14 +306,9 @@ + stm32g0@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; +- /* Alert pin on PI2 */ +- interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +- interrupt-parent = <&gpioi>; +- /* Internal pull-up on PI2 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&stm32g0_intn_pins_a>; ++ /* Alert pin on PI2 (PWR wakeup pin), managed by optee */ ++ interrupts-extended = <&optee 1>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; +- power-domains = <&pd_core>; + wakeup-source; + connector { + compatible = "usb-c-connector"; +@@ -354,7 +367,7 @@ + VDDIO-supply = <&scmi_v3v3_sw>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; +- status = "okay" ; ++ status = "okay"; + }; + + ov5640: camera@3c { +@@ -491,7 +504,6 @@ + + /* Wifi */ + &sdmmc2 { +- arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>; +diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi +index 4d00e759288..fc4ba53feca 100644 +--- a/arch/arm/dts/stm32mp13xc.dtsi ++++ b/arch/arm/dts/stm32mp13xc.dtsi +@@ -12,6 +12,9 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>, ++ <&mdma 29 0x3 0x400808 0x0 0x0 0x0>; ++ dma-names = "in", "out"; + status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi +index 4d00e759288..fc4ba53feca 100644 +--- a/arch/arm/dts/stm32mp13xf.dtsi ++++ b/arch/arm/dts/stm32mp13xf.dtsi +@@ -12,6 +12,9 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>, ++ <&mdma 29 0x3 0x400808 0x0 0x0 0x0>; ++ dma-names = "in", "out"; + status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi +index b4030e5c942..bfa78e50b3b 100644 +--- a/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi ++++ b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi +@@ -89,7 +89,7 @@ + }; + }; + +- m4_ethernet0_rgmii_pins_a: m4-rgmii-0 { ++ m4_ethernet0_rgmii_pins_a: m4-ethernet0-rgmii-0 { + pins { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -492,16 +492,16 @@ + }; + }; + +- m4_usbotg_hs_pins_a: m4-usbotg_hs-0 { ++ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 { + pins { +- pinmux = ; /* OTG_ID */ ++ pinmux = , /* OTG_FS_DM */ ++ ; /* OTG_FS_DP */ + }; + }; + +- m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 { ++ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 { + pins { +- pinmux = , /* OTG_FS_DM */ +- ; /* OTG_FS_DP */ ++ pinmux = ; /* OTG_ID */ + }; + }; + }; +diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi +index d2f2cc8f367..43eb55cb1f5 100644 +--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi +@@ -190,7 +190,7 @@ + }; + }; + +- ethernet0_rgmii_pins_a: rgmii-0 { ++ ethernet0_rgmii_pins_a: ethernet0-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -221,7 +221,7 @@ + }; + }; + +- ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { ++ ethernet0_rgmii_sleep_pins_a: ethernet0-rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -241,7 +241,7 @@ + }; + }; + +- ethernet0_rgmii_pins_b: rgmii-1 { ++ ethernet0_rgmii_pins_b: ethernet0-rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -272,7 +272,7 @@ + }; + }; + +- ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { ++ ethernet0_rgmii_sleep_pins_b: ethernet0-rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -292,7 +292,7 @@ + }; + }; + +- ethernet0_rgmii_pins_c: rgmii-2 { ++ ethernet0_rgmii_pins_c: ethernet0-rgmii-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -323,7 +323,7 @@ + }; + }; + +- ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { ++ ethernet0_rgmii_sleep_pins_c: ethernet0-rgmii-sleep-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ +@@ -343,7 +343,7 @@ + }; + }; + +- ethernet0_rmii_pins_a: rmii-0 { ++ ethernet0_rmii_pins_a: ethernet0-rmii-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ +@@ -363,7 +363,7 @@ + }; + }; + +- ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { ++ ethernet0_rmii_sleep_pins_a: ethernet0-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ +@@ -945,7 +945,7 @@ + }; + }; + +- m_can1_sleep_pins_a: m_can1-sleep-0 { ++ m_can1_sleep_pins_a: m-can1-sleep-0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ +@@ -965,7 +965,7 @@ + }; + }; + +- m_can1_sleep_pins_b: m_can1-sleep-1 { ++ m_can1_sleep_pins_b: m-can1-sleep-1 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ +@@ -985,7 +985,7 @@ + }; + }; + +- m_can2_sleep_pins_a: m_can2-sleep-0 { ++ m_can2_sleep_pins_a: m-can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ +@@ -1152,23 +1152,8 @@ + }; + }; + +- qspi_clk_pins_a: qspi-clk-0 { +- pins { +- pinmux = ; /* QSPI_CLK */ +- bias-disable; +- drive-push-pull; +- slew-rate = <3>; +- }; +- }; +- +- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { +- pins { +- pinmux = ; /* QSPI_CLK */ +- }; +- }; +- + qspi_bk1_pins_a: qspi-bk1-0 { +- pins1 { ++ pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ +@@ -1177,12 +1162,6 @@ + drive-push-pull; + slew-rate = <1>; + }; +- pins2 { +- pinmux = ; /* QSPI_BK1_NCS */ +- bias-pull-up; +- drive-push-pull; +- slew-rate = <1>; +- }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { +@@ -1190,13 +1169,12 @@ + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ +- , /* QSPI_BK1_IO3 */ +- ; /* QSPI_BK1_NCS */ ++ ; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_bk2_pins_a: qspi-bk2-0 { +- pins1 { ++ pins { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ +@@ -1205,7 +1183,49 @@ + drive-push-pull; + slew-rate = <1>; + }; +- pins2 { ++ }; ++ ++ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { ++ pins { ++ pinmux = , /* QSPI_BK2_IO0 */ ++ , /* QSPI_BK2_IO1 */ ++ , /* QSPI_BK2_IO2 */ ++ ; /* QSPI_BK2_IO3 */ ++ }; ++ }; ++ ++ qspi_clk_pins_a: qspi-clk-0 { ++ pins { ++ pinmux = ; /* QSPI_CLK */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <3>; ++ }; ++ }; ++ ++ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { ++ pins { ++ pinmux = ; /* QSPI_CLK */ ++ }; ++ }; ++ ++ qspi_cs1_pins_a: qspi-cs1-0 { ++ pins { ++ pinmux = ; /* QSPI_BK1_NCS */ ++ bias-pull-up; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { ++ pins { ++ pinmux = ; /* QSPI_BK1_NCS */ ++ }; ++ }; ++ ++ qspi_cs2_pins_a: qspi-cs2-0 { ++ pins { + pinmux = ; /* QSPI_BK2_NCS */ + bias-pull-up; + drive-push-pull; +@@ -1213,13 +1233,9 @@ + }; + }; + +- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { ++ qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { + pins { +- pinmux = , /* QSPI_BK2_IO0 */ +- , /* QSPI_BK2_IO1 */ +- , /* QSPI_BK2_IO2 */ +- , /* QSPI_BK2_IO3 */ +- ; /* QSPI_BK2_NCS */ ++ pinmux = ; /* QSPI_BK2_NCS */ + }; + }; + +@@ -1280,7 +1296,7 @@ + }; + }; + +- sai2a_sleep_pins_c: sai2a-2 { ++ sai2a_sleep_pins_c: sai2a-sleep-2 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ +@@ -1372,6 +1388,18 @@ + }; + }; + ++ sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { ++ pins1 { ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ ; /* SDMMC1_D3 */ ++ slew-rate = <1>; ++ drive-push-pull; ++ bias-disable; ++ }; ++ }; ++ + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ +@@ -1396,18 +1424,6 @@ + }; + }; + +- sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { +- pins1 { +- pinmux = , /* SDMMC1_D0 */ +- , /* SDMMC1_D1 */ +- , /* SDMMC1_D2 */ +- ; /* SDMMC1_D3 */ +- slew-rate = <1>; +- drive-push-pull; +- bias-disable; +- }; +- }; +- + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ +@@ -1986,7 +2002,7 @@ + }; + }; + +- uart8_rtscts_pins_a: uart8rtscts-0 { ++ uart8_rtscts_pins_a: uart8-rtscts-0 { + pins { + pinmux = , /* UART8_RTS */ + ; /* UART8_CTS */ +@@ -2178,16 +2194,16 @@ + }; + }; + +- usbotg_hs_pins_a: usbotg-hs-0 { ++ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { + pins { +- pinmux = ; /* OTG_ID */ ++ pinmux = , /* OTG_FS_DM */ ++ ; /* OTG_FS_DP */ + }; + }; + +- usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { ++ usbotg_hs_pins_a: usbotg-hs-0 { + pins { +- pinmux = , /* OTG_FS_DM */ +- ; /* OTG_FS_DP */ ++ pinmux = ; /* OTG_ID */ + }; + }; + }; +diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi +index 2d403bb0907..4a7d413d167 100644 +--- a/arch/arm/dts/stm32mp151.dtsi ++++ b/arch/arm/dts/stm32mp151.dtsi +@@ -431,6 +431,17 @@ + }; + }; + ++ i2s2: audio-controller@4000b000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x4000b000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 39 0x400 0x01>, ++ <&dmamux1 40 0x400 0x01>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; +@@ -445,13 +456,13 @@ + status = "disabled"; + }; + +- i2s2: audio-controller@4000b000 { ++ i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 39 0x400 0x01>, +- <&dmamux1 40 0x400 0x01>; ++ reg = <0x4000c000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 61 0x400 0x01>, ++ <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; +@@ -470,17 +481,6 @@ + status = "disabled"; + }; + +- i2s3: audio-controller@4000c000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 61 0x400 0x01>, +- <&dmamux1 62 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; +@@ -770,25 +770,25 @@ + status = "disabled"; + }; + +- spi1: spi@44004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; ++ i2s1: audio-controller@44004000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = ; +- clocks = <&rcc SPI1_K>; +- resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + +- i2s1: audio-controller@44004000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; ++ spi1: spi@44004000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; ++ clocks = <&rcc SPI1_K>; ++ resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; +@@ -1145,6 +1145,8 @@ + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; +@@ -1156,6 +1158,8 @@ + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; +@@ -1164,6 +1168,14 @@ + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; ++ channel@13 { ++ reg = <13>; ++ label = "vrefint"; ++ }; ++ channel@14 { ++ reg = <14>; ++ label = "vddcore"; ++ }; + }; + }; + +@@ -1298,18 +1310,67 @@ + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; ++ #address-cells = <0>; + reg = <0x5000d000 0x400>; + hwlocks = <&hsem 1 1>; ++ wakeup-parent = <&pwr_irq>; + +- /* exti_pwr is an extra interrupt controller used for +- * EXTI 55 to 60. It's mapped on pwr interrupt +- * controller. +- */ +- exti_pwr: exti-pwr { +- interrupt-controller; ++ exti-interrupt-map { ++ #address-cells = <0>; + #interrupt-cells = <2>; +- interrupt-parent = <&pwr_irq>; +- st,irq-number = <6>; ++ interrupt-map-mask = <0xffffffff 0>; ++ interrupt-map = ++ <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, ++ <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, ++ <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, ++ <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, ++ <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, ++ <5 0 &intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, ++ <6 0 &intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, ++ <7 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, ++ <8 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, ++ <9 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, ++ <10 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, ++ <11 0 &intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, ++ <12 0 &intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, ++ <13 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, ++ <14 0 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, ++ <15 0 &intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, ++ <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, ++ <21 0 &intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, ++ <22 0 &intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, ++ <23 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, ++ <24 0 &intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, ++ <25 0 &intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, ++ <26 0 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, ++ <27 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, ++ <28 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, ++ <29 0 &intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, ++ <30 0 &intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, ++ <31 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, ++ <32 0 &intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, ++ <33 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, ++ <43 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, ++ <44 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, ++ <47 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, ++ <48 0 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <50 0 &intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, ++ <52 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, ++ <53 0 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, ++ <54 0 &intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, ++ <55 0 &pwr_irq 0 IRQ_TYPE_EDGE_FALLING 0>, ++ <56 0 &pwr_irq 1 IRQ_TYPE_EDGE_FALLING 0>, ++ <57 0 &pwr_irq 2 IRQ_TYPE_EDGE_FALLING 0>, ++ <58 0 &pwr_irq 3 IRQ_TYPE_EDGE_FALLING 0>, ++ <59 0 &pwr_irq 4 IRQ_TYPE_EDGE_FALLING 0>, ++ <60 0 &pwr_irq 5 IRQ_TYPE_EDGE_FALLING 0>, ++ <61 0 &intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, ++ <65 0 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, ++ <68 0 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, ++ <69 0 &intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, ++ <70 0 &intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, ++ <73 0 &intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + +@@ -1720,7 +1781,6 @@ + reg = <0x5c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_USART1>; +- resets = <&scmi_reset RST_SCMI_USART1>; + wakeup-source; + power-domains = <&pd_core>; + status = "disabled"; +@@ -1835,7 +1895,7 @@ + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ +- pinctrl: pin-controller@50002000 { ++ pinctrl: pinctrl@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; +@@ -1967,7 +2027,7 @@ + }; + }; + +- pinctrl_z: pin-controller-z@54004000 { ++ pinctrl_z: pinctrl@54004000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; +diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts +deleted file mode 100644 +index 9c165104fbe..00000000000 +--- a/arch/arm/dts/stm32mp157a-avenger96.dts ++++ /dev/null +@@ -1,8 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +-/* +- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved +- * Author: Manivannan Sadhasivam +- */ +- +-/* This is kept for backward compatibility and will be removed */ +-#include "stm32mp15xx-dhcor-avenger96.dts" +diff --git a/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts +new file mode 100644 +index 00000000000..2e3c9fbb4eb +--- /dev/null ++++ b/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts +@@ -0,0 +1,38 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) ++/* ++ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved ++ * Author: Manivannan Sadhasivam ++ * Copyright (C) 2020 Marek Vasut ++ * ++ * DHCOR STM32MP1 variant: ++ * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG ++ * DHCOR PCB number: 586-100 or newer ++ * Avenger96 PCB number: 588-200 or newer ++ */ ++ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xx-dhcor-som.dtsi" ++#include "stm32mp15xx-dhcor-avenger96.dtsi" ++ ++/ { ++ model = "Arrow Electronics STM32MP157A Avenger96 board"; ++ compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", ++ "st,stm32mp157"; ++}; ++ ++&m_can1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&m_can1_pins_b>; ++ pinctrl-1 = <&m_can1_sleep_pins_b>; ++ status = "disabled"; ++}; ++ ++&m_can2 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&m_can2_pins_a>; ++ pinctrl-1 = <&m_can2_sleep_pins_a>; ++ status = "disabled"; ++}; +diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts +index a46941d6f7b..0190bd17dd1 100644 +--- a/arch/arm/dts/stm32mp157c-dk2.dts ++++ b/arch/arm/dts/stm32mp157c-dk2.dts +@@ -113,7 +113,6 @@ + + /* Wifi */ + &sdmmc2 { +- arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; +diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts +index 3cd2e730342..d854ed0ac1d 100644 +--- a/arch/arm/dts/stm32mp157f-dk2.dts ++++ b/arch/arm/dts/stm32mp157f-dk2.dts +@@ -113,7 +113,6 @@ + + /* Wifi */ + &sdmmc2 { +- arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; +diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi +index 67d38d13337..71787e804f3 100644 +--- a/arch/arm/dts/stm32mp15xc.dtsi ++++ b/arch/arm/dts/stm32mp15xc.dtsi +@@ -14,6 +14,9 @@ + interrupts = ; + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; ++ dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>, ++ <&mdma1 30 0x3 0x400808 0x0 0x0 0x0>; ++ dma-names = "in", "out"; + status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi +index f4a77bf9a49..26989fae473 100644 +--- a/arch/arm/dts/stm32mp15xf.dtsi ++++ b/arch/arm/dts/stm32mp15xf.dtsi +@@ -14,6 +14,9 @@ + interrupts = ; + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; ++ dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>, ++ <&mdma1 30 0x3 0x400808 0x0 0x0 0x0>; ++ dma-names = "in", "out"; + status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +index 4948ccd4014..1ef9ac29cea 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts ++++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +@@ -2,166 +2,14 @@ + /* + * Copyright (C) 2020 Marek Vasut + */ ++/dts-v1/; + +-#include "stm32mp15xx-dhcom.dtsi" ++#include "stm32mp151.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xx-dhcom-som.dtsi" ++#include "stm32mp15xx-dhcom-drc02.dtsi" + + / { + model = "DH Electronics STM32MP15xx DHCOM DRC02"; + compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx"; +- +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&adc { +- status = "disabled"; +-}; +- +-&dac { +- status = "disabled"; +-}; +- +-&gpiob { +- /* +- * NOTE: On DRC02, the RS485_RX_En is controlled by a separate +- * GPIO line, however the STM32 UART driver assumes RX happens +- * during TX anyway and that it only controls drive enable DE +- * line. Hence, the RX is always enabled here. +- */ +- usb-hub { +- gpio-hog; +- gpios = <8 0>; +- output-high; +- line-name = "rs485-rx-en"; +- }; +-}; +- +-&gpiod { +- gpio-line-names = "", "", "", "", +- "", "", "", "", +- "", "", "", "Out1", +- "Out2", "", "", ""; +-}; +- +-&gpioi { +- gpio-line-names = "In1", "", "", "", +- "", "", "", "", +- "In2", "", "", "", +- "", "", "", ""; +- +- /* +- * NOTE: The USB Hub on the DRC02 needs a reset signal to be +- * pulled high in order to be detected by the USB Controller. +- * This signal should be handled by USB power sequencing in +- * order to reset the Hub when USB bus is powered down, but +- * so far there is no such functionality. +- */ +- usb-hub { +- gpio-hog; +- gpios = <2 0>; +- output-high; +- line-name = "usb-hub-reset"; +- }; +-}; +- +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "okay"; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c5 { /* TP7/TP8 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&sdmmc3 { +- /* +- * On DRC02, the SoM does not have SDIO WiFi. The pins +- * are used for on-board microSD slot instead. +- */ +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_a>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; +- cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; +- disable-wp; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&v3v3>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- cs-gpios = <&gpioz 3 0>; +- /* Use PIO for the display */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; /* Enable once there is display driver */ +- /* +- * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are +- * also connected to the display board connector. +- */ +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins_a>; +- status = "okay"; +-}; +- +-/* +- * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), +- * however the STM32MP1 pinmux cannot map them to UART4 . +- */ +- +-&uart8 { /* RS485 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a>; +- rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +- vdda1v1-supply = <®11>; +- vdda1v8-supply = <®18>; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi +new file mode 100644 +index 00000000000..4b10b013ffd +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi +@@ -0,0 +1,165 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright (C) 2020 Marek Vasut ++ */ ++ ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart8; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&adc { ++ status = "disabled"; ++}; ++ ++&dac { ++ status = "disabled"; ++}; ++ ++&gpiob { ++ /* ++ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate ++ * GPIO line, however the STM32 UART driver assumes RX happens ++ * during TX anyway and that it only controls drive enable DE ++ * line. Hence, the RX is always enabled here. ++ */ ++ rs485-rx-en-hog { ++ gpio-hog; ++ gpios = <8 0>; ++ output-low; ++ line-name = "rs485-rx-en"; ++ }; ++}; ++ ++&gpiod { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-B", "", ++ "", "", "", "DRC02-Out1", ++ "DRC02-Out2", "", "", ""; ++}; ++ ++&gpioi { ++ gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", ++ "DHCOM-R", "DHCOM-M", "", "", ++ "DRC02-In2", "", "", "", ++ "", "", "", ""; ++ ++ /* ++ * NOTE: The USB Hub on the DRC02 needs a reset signal to be ++ * pulled high in order to be detected by the USB Controller. ++ * This signal should be handled by USB power sequencing in ++ * order to reset the Hub when USB bus is powered down, but ++ * so far there is no such functionality. ++ */ ++ usb-hub-hog { ++ gpio-hog; ++ gpios = <2 0>; ++ output-high; ++ line-name = "usb-hub-reset"; ++ }; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c04"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2c4 { ++ touchscreen@49 { ++ status = "disabled"; ++ }; ++}; ++ ++&i2c5 { /* TP7/TP8 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&sdmmc3 { ++ /* ++ * On DRC02, the SoM does not have SDIO WiFi. The pins ++ * are used for on-board microSD slot instead. ++ */ ++ /delete-property/broken-cd; ++ cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; ++ disable-wp; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>; ++ cs-gpios = <&gpioz 3 0>; ++ /* Use PIO for the display */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; /* Enable once there is display driver */ ++ /* ++ * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are ++ * also connected to the display board connector. ++ */ ++}; ++ ++&usart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usart3_pins_a>; ++ status = "okay"; ++}; ++ ++/* ++ * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), ++ * however the STM32MP1 pinmux cannot map them to UART4 . ++ */ ++ ++&uart8 { /* RS485 */ ++ linux,rs485-enabled-at-boot-time; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8_pins_a>; ++ rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ status = "okay"; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi +index 12f89b33987..2324926f9df 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi +@@ -4,3 +4,7 @@ + */ + + #include "stm32mp15xx-dhcom-u-boot.dtsi" ++ ++&usbotg_hs { ++ dr_mode = "peripheral"; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +index 52a77c41231..e2e01e2146c 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts ++++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +@@ -2,18 +2,14 @@ + /* + * Copyright (C) 2019 Marek Vasut + */ ++/dts-v1/; + +-#include "stm32mp15xx-dhcom.dtsi" ++#include "stm32mp151.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xx-dhcom-som.dtsi" ++#include "stm32mp15xx-dhcom-pdk2.dtsi" + + / { + model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; +- +- aliases { +- serial0 = &uart4; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi +new file mode 100644 +index 00000000000..fbf3826933e +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi +@@ -0,0 +1,325 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright (C) 2019-2020 Marek Vasut ++ */ ++ ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart8; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ clk_ext_audio_codec: clock-codec { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++ ++ display_bl: display-bl { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; ++ default-brightness-level = <8>; ++ enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; ++ power-supply = <®_panel_bl>; ++ status = "okay"; ++ }; ++ ++ gpio-keys-polled { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <20>; ++ ++ /* ++ * The EXTi IRQ line 3 is shared with ethernet, ++ * so mark this as polled GPIO key. ++ */ ++ button-0 { ++ label = "TA1-GPIO-A"; ++ linux,code = ; ++ gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* ++ * The EXTi IRQ line 6 is shared with touchscreen, ++ * so mark this as polled GPIO key. ++ */ ++ button-1 { ++ label = "TA2-GPIO-B"; ++ linux,code = ; ++ gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* ++ * The EXTi IRQ line 0 is shared with PMIC, ++ * so mark this as polled GPIO key. ++ */ ++ button-2 { ++ label = "TA3-GPIO-C"; ++ linux,code = ; ++ gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ button-3 { ++ label = "TA4-GPIO-D"; ++ linux,code = ; ++ gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ }; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "green:led5"; ++ gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ status = "disabled"; ++ }; ++ ++ led-1 { ++ label = "green:led6"; ++ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led-2 { ++ label = "green:led7"; ++ gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led-3 { ++ label = "green:led8"; ++ gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ panel { ++ compatible = "edt,etm0700g0edh6"; ++ backlight = <&display_bl>; ++ power-supply = <®_panel_bl>; ++ ++ port { ++ lcd_panel_in: endpoint { ++ remote-endpoint = <&lcd_display_out>; ++ }; ++ }; ++ }; ++ ++ reg_panel_bl: regulator-panel-bl { ++ compatible = "regulator-fixed"; ++ regulator-name = "panel_backlight"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_panel_supply>; ++ }; ++ ++ reg_panel_supply: regulator-panel-supply { ++ compatible = "regulator-fixed"; ++ regulator-name = "panel_supply"; ++ regulator-min-microvolt = <24000000>; ++ regulator-max-microvolt = <24000000>; ++ }; ++ ++ sound { ++ compatible = "audio-graph-card"; ++ routing = ++ "MIC_IN", "Capture", ++ "Capture", "Mic Bias", ++ "Playback", "HP_OUT"; ++ dais = <&sai2a_port &sai2b_port>; ++ status = "okay"; ++ }; ++}; ++ ++&cec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cec_pins_a>; ++ status = "okay"; ++}; ++ ++&i2c2 { /* Header X22 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++}; ++ ++&i2c5 { /* Header X21 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ sgtl5000: codec@a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ #sound-dai-cells = <0>; ++ clocks = <&clk_ext_audio_codec>; ++ VDDA-supply = <&v3v3>; ++ VDDIO-supply = <&vdd>; ++ ++ sgtl5000_port: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgtl5000_tx_endpoint: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&sai2a_endpoint>; ++ frame-master = <&sgtl5000_tx_endpoint>; ++ bitclock-master = <&sgtl5000_tx_endpoint>; ++ }; ++ ++ sgtl5000_rx_endpoint: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&sai2b_endpoint>; ++ frame-master = <&sgtl5000_rx_endpoint>; ++ bitclock-master = <&sgtl5000_rx_endpoint>; ++ }; ++ }; ++ ++ }; ++ ++ touchscreen@38 { ++ compatible = "edt,edt-ft5406"; ++ reg = <0x38>; ++ interrupt-parent = <&gpioc>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ ++ }; ++}; ++ ++<dc { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <<dc_pins_b>; ++ pinctrl-1 = <<dc_sleep_pins_b>; ++ status = "okay"; ++ ++ port { ++ lcd_display_out: endpoint { ++ remote-endpoint = <&lcd_panel_in>; ++ }; ++ }; ++}; ++ ++&sai2 { ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++ clock-names = "pclk", "x8k", "x11k"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; ++ pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; ++ status = "okay"; ++ ++ sai2a: audio-controller@4400b004 { ++ #clock-cells = <0>; ++ dma-names = "tx"; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ status = "okay"; ++ ++ sai2a_port: port { ++ sai2a_endpoint: endpoint { ++ remote-endpoint = <&sgtl5000_tx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <512>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <16>; ++ }; ++ }; ++ }; ++ ++ sai2b: audio-controller@4400b024 { ++ dma-names = "rx"; ++ st,sync = <&sai2a 2>; ++ clocks = <&rcc SAI2_K>, <&sai2a>; ++ clock-names = "sai_ck", "MCLK"; ++ status = "okay"; ++ ++ sai2b_port: port { ++ sai2b_endpoint: endpoint { ++ remote-endpoint = <&sgtl5000_rx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <512>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <16>; ++ }; ++ }; ++ }; ++}; ++ ++&timers2 { ++ /* spare dmas for other usage (un-delete to enable pwm capture) */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++ pwm2: pwm { ++ pinctrl-0 = <&pwm2_pins_a>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ }; ++ timer@1 { ++ status = "okay"; ++ }; ++}; ++ ++&usart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usart3_pins_a>; ++ status = "okay"; ++}; ++ ++&uart8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; ++ uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ dr_mode = "otg"; ++ pinctrl-0 = <&usbotg_hs_pins_a>; ++ pinctrl-names = "default"; ++ phy-names = "usb2-phy"; ++ phys = <&usbphyc_port1 0>; ++ vbus-supply = <&vbus_otg>; ++ status = "okay"; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +index 3cac663d987..5bc6698f87f 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +@@ -11,4 +11,8 @@ + }; + }; + +-/delete-node/ &ksz8851; ++/delete-node/ &ks8851; ++ ++&usbotg_hs { ++ dr_mode = "peripheral"; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +index 59d13713d88..06770b47873 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts ++++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +@@ -2,92 +2,14 @@ + /* + * Copyright (C) 2020 Marek Vasut + */ ++/dts-v1/; + +-#include "stm32mp15xx-dhcom.dtsi" ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xx-dhcom-som.dtsi" ++#include "stm32mp15xx-dhcom-picoitx.dtsi" + + / { + model = "DH Electronics STM32MP15xx DHCOM PicoITX"; + compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx"; +- +- aliases { +- serial0 = &uart4; +- serial1 = &usart3; +- serial2 = &uart8; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&adc { +- status = "disabled"; +-}; +- +-&dac { +- status = "disabled"; +-}; +- +-&gpioa { +- /* +- * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable +- * port power. This signal should be handled by USB power sequencing +- * in order to turn on port power when USB bus is powered up, but so +- * far there is no such functionality. +- */ +- usb-port-power { +- gpio-hog; +- gpios = <13 0>; +- output-low; +- line-name = "usb-port-power"; +- }; +-}; +- +-&i2c2 { /* On board-to-board connector (optional) */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c5 { /* On board-to-board connector */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&usart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&usart3_pins_a>; +- status = "okay"; +-}; +- +-&uart8 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart8_pins_a>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +- vdda1v1-supply = <®11>; +- vdda1v8-supply = <®18>; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi +new file mode 100644 +index 00000000000..ba816ef8b9b +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi +@@ -0,0 +1,147 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright (C) 2020 Marek Vasut ++ */ ++ ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart8; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "yellow:led"; ++ gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++&adc { ++ status = "disabled"; ++}; ++ ++&dac { ++ status = "disabled"; ++}; ++ ++&fmc { ++ status = "disabled"; ++}; ++ ++&gpioa { ++ /* ++ * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable ++ * port power. This signal should be handled by USB power sequencing ++ * in order to turn on port power when USB bus is powered up, but so ++ * far there is no such functionality. ++ */ ++ usb-port-power-hog { ++ gpio-hog; ++ gpios = <13 0>; ++ output-low; ++ line-name = "usb-port-power"; ++ }; ++}; ++ ++&gpioc { ++ gpio-line-names = "", "", "", "", ++ "", "", "PicoITX-In1", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpiod { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-B", "", ++ "", "", "", "PicoITX-Out1", ++ "PicoITX-Out2", "", "", ""; ++}; ++ ++&gpiog { ++ gpio-line-names = "PicoITX-In2", "", "", "", ++ "", "", "", "", ++ "DHCOM-L", "", "", "", ++ "", "", "", ""; ++}; ++ ++&i2c2 { /* On board-to-board connector (optional) */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&i2c5 { /* On board-to-board connector */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&ksz8851 { ++ status = "disabled"; ++}; ++ ++&usart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usart3_pins_a>; ++ status = "okay"; ++}; ++ ++&uart8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; ++ status = "okay"; ++}; ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ status = "okay"; ++}; ++ ++&usbh_ohci { ++ phys = <&usbphyc_port0>; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ dr_mode = "otg"; ++ pinctrl-0 = <&usbotg_hs_pins_a>; ++ pinctrl-names = "default"; ++ phy-names = "usb2-phy"; ++ phys = <&usbphyc_port1 0>; ++ vbus-supply = <&vbus_otg>; ++ status = "okay"; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +similarity index 56% +rename from arch/arm/dts/stm32mp15xx-dhcom.dtsi +rename to arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +index a1d1b8dec76..dfaf71b9a5e 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +@@ -1,11 +1,8 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + /* +- * Copyright (C) 2019 Marek Vasut ++ * Copyright (C) 2019-2020 Marek Vasut + */ +-/dts-v1/; + +-#include "stm32mp157.dtsi" +-#include "stm32mp15xc.dtsi" + #include "stm32mp15-pinctrl.dtsi" + #include "stm32mp15xxaa-pinctrl.dtsi" + #include +@@ -13,8 +10,10 @@ + + / { + aliases { +- eeprom0 = &eeprom0; + ethernet0 = ðernet0; ++ ethernet1 = &ksz8851; ++ rtc0 = &hwrtc; ++ rtc1 = &rtc; + }; + + memory@c0000000 { +@@ -22,6 +21,48 @@ + reg = <0xC0000000 0x40000000>; + }; + ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mcuram2: mcuram2@10000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10000000 0x40000>; ++ no-map; ++ }; ++ ++ vdev0vring0: vdev0vring0@10040000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10040000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0vring1: vdev0vring1@10041000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10041000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0buffer: vdev0buffer@10042000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10042000 0x4000>; ++ no-map; ++ }; ++ ++ mcuram: mcuram@30000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x30000000 0x40000>; ++ no-map; ++ }; ++ ++ retram: retram@38000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x38000000 0x10000>; ++ no-map; ++ }; ++ }; ++ + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; +@@ -30,20 +71,49 @@ + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; ++ vin-supply = <&vdd>; + }; + }; + +-&cec { +- pinctrl-names = "default"; +- pinctrl-0 = <&cec_pins_a>; ++&adc { ++ vdd-supply = <&vdd>; ++ vdda-supply = <&vdda>; ++ vref-supply = <&vdda>; + status = "okay"; ++ ++ adc1: adc@0 { ++ status = "okay"; ++ channel@0 { ++ reg = <0>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ }; ++ ++ adc2: adc@100 { ++ status = "okay"; ++ channel@1 { ++ reg = <1>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ }; + }; + +-&dcmi { ++&crc1 { + status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcmi_pins_a>; +- pinctrl-1 = <&dcmi_sleep_pins_a>; ++}; ++ ++&dac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; ++ vref-supply = <&vdda>; ++ status = "okay"; ++ ++ dac1: dac@1 { ++ status = "okay"; ++ }; ++ dac2: dac@2 { ++ status = "okay"; ++ }; + }; + + &dts { +@@ -53,12 +123,12 @@ + ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; +- pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; ++ pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; +- phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; ++ st,eth-ref-clk-sel; + + mdio0 { + #address-cells = <1>; +@@ -67,18 +137,114 @@ + + phy0: ethernet-phy@1 { + reg = <1>; ++ /* LAN8710Ai */ ++ compatible = "ethernet-phy-id0007.c0f0", ++ "ethernet-phy-ieee802.3-c22"; ++ clocks = <&rcc ETHCK_K>; ++ reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <500>; ++ reset-deassert-us = <500>; ++ smsc,disable-energy-detect; ++ interrupt-parent = <&gpioi>; ++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + +-&i2c2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; ++&fmc { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&fmc_pins_b>; ++ pinctrl-1 = <&fmc_sleep_pins_b>; ++ status = "okay"; ++ ++ ksz8851: ethernet@1,0 { ++ compatible = "micrel,ks8851-mll"; ++ reg = <1 0x0 0x2>, <1 0x2 0x20000>; ++ interrupt-parent = <&gpioc>; ++ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ++ bank-width = <2>; ++ ++ /* Timing values are in nS */ ++ st,fmc2-ebi-cs-mux-enable; ++ st,fmc2-ebi-cs-transaction-type = <4>; ++ st,fmc2-ebi-cs-buswidth = <16>; ++ st,fmc2-ebi-cs-address-setup-ns = <5>; ++ st,fmc2-ebi-cs-address-hold-ns = <5>; ++ st,fmc2-ebi-cs-bus-turnaround-ns = <5>; ++ st,fmc2-ebi-cs-data-setup-ns = <45>; ++ st,fmc2-ebi-cs-data-hold-ns = <1>; ++ st,fmc2-ebi-cs-write-address-setup-ns = <5>; ++ st,fmc2-ebi-cs-write-address-hold-ns = <5>; ++ st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; ++ st,fmc2-ebi-cs-write-data-setup-ns = <45>; ++ st,fmc2-ebi-cs-write-data-hold-ns = <1>; ++ }; ++}; ++ ++&gpioa { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-K", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpiob { ++ gpio-line-names = "", "", "", "", ++ "", "", "", "", ++ "DHCOM-Q", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpioc { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-E", "", ++ "", "", "", "", ++ "", "", "", ""; + status = "okay"; + }; + ++&gpiod { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-B", "", ++ "", "", "", "DHCOM-F", ++ "DHCOM-D", "", "", ""; ++}; ++ ++&gpioe { ++ gpio-line-names = "", "", "", "", ++ "", "", "DHCOM-P", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpiof { ++ gpio-line-names = "", "", "", "DHCOM-A", ++ "", "", "", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpiog { ++ gpio-line-names = "DHCOM-C", "", "", "", ++ "", "", "", "", ++ "DHCOM-L", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpioh { ++ gpio-line-names = "", "", "", "", ++ "", "", "", "DHCOM-N", ++ "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", ++ "DHCOM-T", "", "DHCOM-S", ""; ++}; ++ ++&gpioi { ++ gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", ++ "DHCOM-R", "DHCOM-M", "", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ + &i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; +@@ -89,6 +255,11 @@ + /delete-property/dmas; + /delete-property/dma-names; + ++ hwrtc: rtc@32 { ++ compatible = "microcrystal,rv8803"; ++ reg = <0x32>; ++ }; ++ + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; +@@ -146,6 +317,7 @@ + + vdda: ldo1 { + regulator-name = "vdda"; ++ regulator-always-on; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; +@@ -168,8 +340,6 @@ + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; + interrupts = ; + }; + +@@ -191,24 +361,23 @@ + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; +- regulator-over-current-protection; + }; + +- bst_out: boost { ++ bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; +- }; ++ }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; +- }; ++ }; + +- vbus_sw: pwr_sw2 { ++ vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; +- regulator-active-discharge; +- }; ++ regulator-active-discharge = <1>; ++ }; + }; + + onkey { +@@ -225,21 +394,20 @@ + }; + }; + +- eeprom0: eeprom@50 { ++ touchscreen@49 { ++ compatible = "ti,tsc2004"; ++ reg = <0x49>; ++ vio-supply = <&v3v3>; ++ interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; ++ }; ++ ++ eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + +-&i2c5 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- + &ipcc { + status = "okay"; + }; +@@ -250,8 +418,12 @@ + }; + + &m4_rproc { ++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, ++ <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; ++ interrupt-parent = <&exti>; ++ interrupts = <68 1>; + status = "okay"; + }; + +@@ -260,42 +432,6 @@ + vdd_3v3_usbfs-supply = <&vdd_usb>; + }; + +-&pinctrl { +- ethernet0_rmii_pins_a: rmii-0 { +- pins1 { +- pinmux = , /* ETH1_RMII_TXD0 */ +- , /* ETH1_RMII_TXD1 */ +- , /* ETH1_RMII_TX_EN */ +- , /* ETH1_RMII_REF_CLK */ +- , /* ETH1_MDIO */ +- ; /* ETH1_MDC */ +- bias-disable; +- drive-push-pull; +- slew-rate = <2>; +- }; +- pins2 { +- pinmux = , /* ETH1_RMII_RXD0 */ +- , /* ETH1_RMII_RXD1 */ +- ; /* ETH1_RMII_CRS_DV */ +- bias-disable; +- }; +- }; +- +- ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { +- pins1 { +- pinmux = , /* ETH1_RMII_TXD0 */ +- , /* ETH1_RMII_TXD1 */ +- , /* ETH1_RMII_TX_EN */ +- , /* ETH1_MDIO */ +- , /* ETH1_MDC */ +- , /* ETH1_RMII_RXD0 */ +- , /* ETH1_RMII_RXD1 */ +- , /* ETH1_RMII_REF_CLK */ +- ; /* ETH1_RMII_CRS_DV */ +- }; +- }; +-}; +- + &qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; +@@ -305,7 +441,7 @@ + #size-cells = <0>; + status = "okay"; + +- flash0: mx66l51235l@0 { ++ flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; +@@ -324,14 +460,19 @@ + }; + + &sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-names = "default", "opendrain", "sleep", "init"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; ++ pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; ++ st,use-ckin; ++ st,cmd-gpios = <&gpiod 2 0>; ++ st,ck-gpios = <&gpioc 12 0>; ++ st,ckin-gpios = <&gpioe 4 0>; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +@@ -352,75 +493,33 @@ + }; + + &sdmmc2 { +- pinctrl-names = "default"; ++ pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; +- st,sig-dir; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&v3v3>; ++ mmc-ddr-3_3v; + status = "okay"; + }; + +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "disabled"; +-}; +- +-&timers2 { +- /* spare dmas for other usage (un-delete to enable pwm capture) */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm2_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- timer@1 { +- status = "okay"; +- }; +-}; +- +-&timers6 { ++&sdmmc3 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc3_b4_pins_a>; ++ pinctrl-1 = <&sdmmc3_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; ++ broken-cd; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&v3v3>; ++ mmc-ddr-3_3v; + status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- timer@5 { +- status = "okay"; +- }; +-}; +- +-&timers8 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm8_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- timer@7 { +- status = "okay"; +- }; +-}; +- +-&timers12 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm12_pins_a>; +- pinctrl-names = "default"; +- status = "okay"; +- }; +- timer@11 { +- status = "okay"; +- }; + }; + + &uart4 { +@@ -428,29 +527,3 @@ + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- phy-names = "usb"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- dr_mode = "peripheral"; +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- vbus-supply = <&vbus_otg>; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +index 1ec4702585e..d156cf8fc92 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +@@ -9,6 +9,8 @@ + #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" + #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" + ++/delete-node/ &ksz8851; ++ + / { + aliases { + i2c1 = &i2c2; +@@ -18,7 +20,8 @@ + mmc1 = &sdmmc2; + spi0 = &qspi; + usb0 = &usbotg_hs; +- ethernet1 = &ksz8851; ++ eeprom0 = &eeprom0; ++ ethernet1 = &ks8851; + }; + + config { +@@ -30,28 +33,34 @@ + dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; + }; + +- led { +- red { +- label = "error"; +- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- status = "okay"; +- }; +- +- blue { +- default-state = "on"; +- }; +- }; +- + /* This is actually on FMC2, but we do not have bus driver for that */ +- ksz8851: ks8851mll@64000000 { ++ ks8851: ks8851mll@64000000 { + compatible = "micrel,ks8851-mll"; + reg = <0x64000000 0x20000>; + }; + }; + ++ðernet0 { ++ phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; ++ /delete-property/ st,eth-ref-clk-sel; ++}; ++ ++ðernet0_rmii_pins_a { ++ pins1 { ++ pinmux = , /* ETH1_RMII_TXD0 */ ++ , /* ETH1_RMII_TXD1 */ ++ , /* ETH1_RMII_TX_EN */ ++ , /* ETH1_RMII_REF_CLK */ ++ , /* ETH1_MDIO */ ++ ; /* ETH1_MDC */ ++ }; ++}; ++ + &i2c4 { + u-boot,dm-pre-reloc; ++ ++ eeprom0: eeprom@50 { ++ }; + }; + + &i2c4_pins_a { +@@ -61,6 +70,10 @@ + }; + }; + ++&phy0 { ++ /delete-property/ reset-gpios; ++}; ++ + &pinctrl { + /* These should bound to FMC2 bus driver, but we do not have one */ + pinctrl-0 = <&fmc_pins_b &mco2_pins_a>; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +index c96eba99c5e..6e6543b5e4a 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +@@ -21,6 +21,8 @@ + + + ðernet0 { ++ phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; ++ + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +index 0e860e5cf88..76ac5a873c1 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts ++++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +@@ -7,206 +7,12 @@ + + /dts-v1/; + +-#include "stm32mp15xx-dhcor-io1v8.dtsi" +-#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi" ++#include "stm32mp151.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15xx-dhcor-som.dtsi" ++#include "stm32mp15xx-dhcor-avenger96.dtsi" + + / { + model = "Arrow Electronics STM32MP15xx Avenger96 board"; + compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; +- +- aliases { +- eeprom0 = &eeprom0; +- ethernet0 = ðernet0; +- mmc0 = &sdmmc1; +- serial0 = &uart4; +- serial1 = &uart7; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- led { +- compatible = "gpio-leds"; +- led1 { +- label = "green:user0"; +- gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- default-state = "off"; +- }; +- +- led2 { +- label = "green:user1"; +- gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc0"; +- default-state = "off"; +- }; +- +- led3 { +- label = "green:user2"; +- gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "mmc1"; +- default-state = "off"; +- }; +- +- led4 { +- label = "green:user3"; +- gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "none"; +- default-state = "off"; +- panic-indicator; +- }; +- +- led5 { +- label = "yellow:wifi"; +- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "phy0tx"; +- default-state = "off"; +- }; +- +- led6 { +- label = "blue:bt"; +- gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "bluetooth-power"; +- default-state = "off"; +- }; +- }; +- +- sd_switch: regulator-sd_switch { +- compatible = "regulator-gpio"; +- regulator-name = "sd_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- regulator-always-on; +- +- gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1>, +- <2900000 0x0>; +- }; +-}; +- +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_c>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@7 { +- reg = <7>; +- }; +- }; +-}; +- +-&i2c1 { /* X6 I2C1 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins_b>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c2 { /* X6 I2C2 */ +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins_c>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- /delete-property/dmas; +- /delete-property/dma-names; +-}; +- +-&i2c4 { +- eeprom0: eeprom@53 { +- compatible = "atmel,24c02"; +- reg = <0x53>; +- pagesize = <16>; +- }; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&sd_switch>; +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; +- non-removable; +- no-sd; +- no-sdio; +- st,neg-edge; +- bus-width = <8>; +- vmmc-supply = <&v3v3>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&spi2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2_pins_a>; +- status = "okay"; +-}; +- +-&uart4 { +- /* On Low speed expansion header */ +- label = "LS-UART1"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_b>; +- status = "okay"; +-}; +- +-&uart7 { +- /* On Low speed expansion header */ +- label = "LS-UART0"; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart7_pins_a>; +- status = "okay"; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- phy-names = "usb"; +- status = "okay"; +-}; +- +-&usbotg_hs { +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi +new file mode 100644 +index 00000000000..d21c0a2bfbe +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi +@@ -0,0 +1,451 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) ++/* ++ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved ++ * Author: Manivannan Sadhasivam ++ * Copyright (C) 2020 Marek Vasut ++ */ ++ ++/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ ++#include "stm32mp15xx-dhcor-io1v8.dtsi" ++ ++/ { ++ aliases { ++ ethernet0 = ðernet0; ++ mmc0 = &sdmmc1; ++ serial0 = &uart4; ++ serial1 = &uart7; ++ serial2 = &usart2; ++ spi0 = &qspi; ++ }; ++ ++ /* XTal Q1 */ ++ cec_clock: clk-cec-fixed { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ hdmi-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con: endpoint { ++ remote-endpoint = <&adv7513_out>; ++ }; ++ }; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ led1 { ++ label = "green:user0"; ++ gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ ++ led2 { ++ label = "green:user1"; ++ gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "mmc0"; ++ default-state = "off"; ++ }; ++ ++ led3 { ++ label = "green:user2"; ++ gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "mmc1"; ++ default-state = "off"; ++ }; ++ ++ led4 { ++ label = "green:user3"; ++ gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ default-state = "off"; ++ panic-indicator; ++ }; ++ }; ++ ++ sd_switch: regulator-sd_switch { ++ compatible = "regulator-gpio"; ++ regulator-name = "sd_switch"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2900000>; ++ regulator-type = "voltage"; ++ regulator-always-on; ++ ++ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0>; ++ states = <1800000 0x1>, ++ <2900000 0x0>; ++ }; ++ ++ sound { ++ compatible = "audio-graph-card"; ++ label = "STM32MP1-AV96-HDMI"; ++ dais = <&sai2a_port>; ++ status = "okay"; ++ }; ++ ++ wlan_pwr: regulator-wlan { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "wl-reg"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&adc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&adc12_ain_pins_b>; ++ vdd-supply = <&vdd>; ++ vdda-supply = <&vdda>; ++ vref-supply = <&vdda>; ++ status = "okay"; ++ ++ adc1: adc@0 { ++ status = "okay"; ++ channel@0 { ++ reg = <0>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@1 { ++ reg = <1>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@6 { ++ reg = <6>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ }; ++ ++ adc2: adc@100 { ++ status = "okay"; ++ channel@0 { ++ reg = <0>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@1 { ++ reg = <1>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@2 { ++ reg = <2>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ }; ++}; ++ ++ðernet0 { ++ status = "okay"; ++ pinctrl-0 = <ðernet0_rgmii_pins_c>; ++ pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ phy-handle = <&phy0>; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; ++ reset-delay-us = <1000>; ++ ++ phy0: ethernet-phy@7 { ++ reg = <7>; ++ ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <540>; ++ rxd0-skew-ps = <420>; ++ rxd1-skew-ps = <420>; ++ rxd2-skew-ps = <420>; ++ rxd3-skew-ps = <420>; ++ ++ txc-skew-ps = <1440>; ++ txen-skew-ps = <540>; ++ txd0-skew-ps = <420>; ++ txd1-skew-ps = <420>; ++ txd2-skew-ps = <420>; ++ txd3-skew-ps = <420>; ++ }; ++ }; ++}; ++ ++&gpioa { ++ gpio-line-names = "", "", "", "", ++ "", "", "", "", ++ "", "", "", "AV96-K", ++ "AV96-I", "", "AV96-A", ""; ++}; ++ ++&gpiob { ++ gpio-line-names = "", "", "", "", ++ "", "AV96-J", "", "", ++ "", "", "", "AV96-B", ++ "", "AV96-L", "", ""; ++}; ++ ++&gpioc { ++ gpio-line-names = "", "", "", "AV96-C", ++ "", "", "", "", ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpiod { ++ gpio-line-names = "", "", "", "", ++ "", "", "", "", ++ "AV96-D", "", "", "", ++ "", "", "AV96-E", "AV96-F"; ++}; ++ ++&gpiof { ++ gpio-line-names = "", "", "", "", ++ "", "", "", "", ++ "", "", "", "", ++ "AV96-G", "AV96-H", "", ""; ++}; ++ ++&i2c1 { /* X6 I2C1 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_b>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&i2c2 { /* X6 I2C2 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_c>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&i2c4 { ++ hdmi-transmitter@3d { ++ compatible = "adi,adv7513"; ++ reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; ++ reg-names = "main", "edid", "cec", "packet"; ++ clocks = <&cec_clock>; ++ clock-names = "cec"; ++ ++ avdd-supply = <&v3v3>; ++ dvdd-supply = <&v3v3>; ++ pvdd-supply = <&v3v3>; ++ dvdd-3v-supply = <&v3v3>; ++ bgvdd-supply = <&v3v3>; ++ ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-parent = <&gpiog>; ++ ++ status = "okay"; ++ ++ adi,input-depth = <8>; ++ adi,input-colorspace = "rgb"; ++ adi,input-clock = "1x"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ adv7513_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ adv7513_out: endpoint { ++ remote-endpoint = <&hdmi_con>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ adv7513_i2s0: endpoint { ++ remote-endpoint = <&sai2a_endpoint>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++<dc { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <<dc_pins_d>; ++ pinctrl-1 = <<dc_sleep_pins_d>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&adv7513_in>; ++ }; ++ }; ++}; ++ ++&sai2 { ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&sai2a_pins_c>; ++ pinctrl-1 = <&sai2a_sleep_pins_c>; ++ clock-names = "pclk", "x8k", "x11k"; ++ status = "okay"; ++ ++ sai2a: audio-controller@4400b004 { ++ #clock-cells = <0>; ++ dma-names = "tx"; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ status = "okay"; ++ ++ sai2a_port: port { ++ sai2a_endpoint: endpoint { ++ remote-endpoint = <&adv7513_i2s0>; ++ format = "i2s"; ++ mclk-fs = <256>; ++ }; ++ }; ++ }; ++}; ++ ++&sdmmc1 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; ++ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; ++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; ++ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ disable-wp; ++ st,sig-dir; ++ st,neg-edge; ++ st,use-ckin; ++ bus-width = <4>; ++ vmmc-supply = <&vdd_sd>; ++ vqmmc-supply = <&sd_switch>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; ++ bus-width = <8>; ++ mmc-ddr-1_8v; ++ no-sd; ++ no-sdio; ++ non-removable; ++ st,neg-edge; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&vdd_io>; ++ status = "okay"; ++}; ++ ++&sdmmc3 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc3_b4_pins_b>; ++ pinctrl-1 = <&sdmmc3_b4_od_pins_b>; ++ pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; ++ broken-cd; ++ non-removable; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&wlan_pwr>; ++ status = "okay"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++&spi2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ cs-gpios = <&gpioi 0 0>; ++ status = "disabled"; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&uart4 { ++ /* On Low speed expansion header */ ++ label = "LS-UART1"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_b>; ++ status = "okay"; ++}; ++ ++&uart7 { ++ /* On Low speed expansion header */ ++ label = "LS-UART0"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ uart-has-rtscts; ++ status = "okay"; ++}; ++ ++/* Bluetooth */ ++&usart2 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&usart2_pins_a>; ++ pinctrl-1 = <&usart2_sleep_pins_a>; ++ st,hw-flow-ctrl; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ pinctrl-0 = <&usbotg_hs_pins_a>; ++ pinctrl-names = "default"; ++ phy-names = "usb2-phy"; ++ phys = <&usbphyc_port1 0>; ++ status = "okay"; ++ vbus-supply = <&vbus_otg>; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +index 75435424d67..75172314d7a 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +@@ -1,12 +1,12 @@ + // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) + /* ++ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved ++ * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +-#include "stm32mp15xx-dhcor-io3v3.dtsi" +- + / { +- /* Enpirion EP3A8LQI U2 on the 1V8 IO DHCOR */ ++ /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; +@@ -20,5 +20,4 @@ + + &pwr_regulators { + vdd-supply = <&vdd_io>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; + }; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +similarity index 91% +rename from arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi +rename to arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +index 94cf80dbede..44ecc470858 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +@@ -4,9 +4,7 @@ + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ +-/dts-v1/; + +-#include "stm32mp157.dtsi" + #include "stm32mp15-pinctrl.dtsi" + #include "stm32mp15xxac-pinctrl.dtsi" + #include +@@ -23,6 +21,14 @@ + }; + }; + ++&crc1 { ++ status = "okay"; ++}; ++ ++&dts { ++ status = "okay"; ++}; ++ + &i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; +@@ -35,7 +41,7 @@ + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; +- interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; +@@ -53,7 +59,7 @@ + + vddcore: buck1 { + regulator-name = "vddcore"; +- regulator-min-microvolt = <800000>; ++ regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; +@@ -92,7 +98,6 @@ + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; +- interrupt-parent = <&pmic>; + }; + + v2v8: ldo2 { +@@ -100,7 +105,6 @@ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; +- interrupt-parent = <&pmic>; + }; + + vtt_ddr: ldo3 { +@@ -114,7 +118,6 @@ + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; +- interrupt-parent = <&pmic>; + }; + + vdd_sd: ldo5 { +@@ -122,7 +125,6 @@ + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; +- interrupt-parent = <&pmic>; + regulator-boot-on; + }; + +@@ -131,7 +133,6 @@ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; +- interrupt-parent = <&pmic>; + regulator-enable-ramp-delay = <300000>; + }; + +@@ -143,20 +144,17 @@ + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; +- interrupt-parent = <&pmic>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; +- interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; +- interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + }; +@@ -173,6 +171,12 @@ + status = "disabled"; + }; + }; ++ ++ eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; + }; + + &iwdg2 { +@@ -194,7 +198,7 @@ + #size-cells = <0>; + status = "okay"; + +- flash0: spi-flash@0 { ++ flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +index 48a046ecc64..bca07b5e375 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +@@ -15,6 +15,11 @@ + + / { + u-boot,dm-pre-reloc; ++ ++ aliases { ++ eeprom0 = &eeprom0; ++ }; ++ + config { + dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>; + dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>; +@@ -27,6 +32,9 @@ + + &i2c4 { + u-boot,dm-pre-reloc; ++ ++ eeprom0: eeprom@53 { ++ }; + }; + + &i2c4_pins_a { +diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi +index d5abbfd510f..58bb9eca86a 100644 +--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi +@@ -118,22 +118,33 @@ + vref-supply = <&vrefbuf>; + status = "okay"; + adc1: adc@0 { ++ status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (56 + 47kOhms) * 5pF => 2.5us. + * Use arbitrary margin here (e.g. 5us). + */ +- st,min-sample-time-nsecs = <5000>; +- /* USB Type-C CC1 & CC2 */ +- st,adc-channels = <18 19>; +- status = "okay"; ++ channel@18 { ++ reg = <18>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@19 { ++ reg = <19>; ++ st,min-sample-time-ns = <5000>; ++ }; + }; + adc2: adc@100 { +- /* USB Type-C CC1 & CC2 */ +- st,adc-channels = <18 19>; +- st,min-sample-time-nsecs = <5000>; + status = "okay"; ++ /* USB Type-C CC1 & CC2 */ ++ channel@18 { ++ reg = <18>; ++ st,min-sample-time-ns = <5000>; ++ }; ++ channel@19 { ++ reg = <19>; ++ st,min-sample-time-ns = <5000>; ++ }; + }; + }; + +@@ -311,7 +322,7 @@ + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; +- interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; +diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi +index db0f911353a..014ce3863d3 100644 +--- a/arch/arm/dts/stm32mp15xx-edx.dtsi ++++ b/arch/arm/dts/stm32mp15xx-edx.dtsi +@@ -114,10 +114,20 @@ + vref-supply = <&vdda>; + status = "disabled"; + adc1: adc@0 { +- st,adc-channels = <0 1 6>; +- /* 16.5 ck_cycles sampling time */ +- st,min-sample-time-nsecs = <400>; + status = "okay"; ++ channel@0 { ++ reg = <0>; ++ /* 16.5 ck_cycles sampling time */ ++ st,min-sample-time-ns = <400>; ++ }; ++ channel@1 { ++ reg = <1>; ++ st,min-sample-time-ns = <400>; ++ }; ++ channel@6 { ++ reg = <6>; ++ st,min-sample-time-ns = <400>; ++ }; + }; + }; + +@@ -177,7 +187,7 @@ + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; +- interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; +diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi +index fa453817aa8..fe8a8dfc46b 100644 +--- a/arch/arm/dts/stm32mp15xx-evx.dtsi ++++ b/arch/arm/dts/stm32mp15xx-evx.dtsi +@@ -463,8 +463,16 @@ + + &qspi { + pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; +- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; ++ pinctrl-0 = <&qspi_clk_pins_a ++ &qspi_bk1_pins_a ++ &qspi_cs1_pins_a ++ &qspi_bk2_pins_a ++ &qspi_cs2_pins_a>; ++ pinctrl-1 = <&qspi_clk_sleep_pins_a ++ &qspi_bk1_sleep_pins_a ++ &qspi_cs1_sleep_pins_a ++ &qspi_bk2_sleep_pins_a ++ &qspi_cs2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0098-silent_mode.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0098-silent_mode.patch index 2ab8842..db8ce76 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0098-silent_mode.patch +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0098-silent_mode.patch @@ -1,24 +1,42 @@ -From 2132a1ff883c92953e906ba8f32b13641bdb98c7 Mon Sep 17 00:00:00 2001 +From 9538ad0348aef5f00cd0a6858873d5ffac2e287f Mon Sep 17 00:00:00 2001 From: Christophe Priouzeau -Date: Fri, 16 Jul 2021 16:25:20 +0200 -Subject: [PATCH 12/12] cpr_silent +Date: Wed, 28 Sep 2022 10:52:51 +0200 +Subject: [PATCH] silent_mode +Signed-off-by: Christophe Priouzeau --- - include/configs/stm32mp1.h | 1 + - 1 file changed, 1 insertion(+) + include/configs/stm32mp13_st_common.h | 3 ++- + include/configs/stm32mp15_st_common.h | 3 ++- + 2 files changed, 4 insertions(+), 2 deletions(-) -diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h -index 72424abb8b..0088ced206 100644 ---- a/include/configs/stm32mp1.h -+++ b/include/configs/stm32mp1.h -@@ -159,6 +159,7 @@ - "env_check=if env info -p -d -q; then env save; fi\0" \ - STM32MP_BOOTCMD \ - BOOTENV \ -+ "silent=1\0" \ - "boot_net_usb_start=true\0" +diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h +index 41681537a2..49d3398663 100644 +--- a/include/configs/stm32mp13_st_common.h ++++ b/include/configs/stm32mp13_st_common.h +@@ -10,7 +10,8 @@ + + #define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" \ +- "console=ttySTM0\0" ++ "console=ttySTM0\0" \ ++ "silent=1\0" + + #include + +diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h +index c395f7f986..81865b24ea 100644 +--- a/include/configs/stm32mp15_st_common.h ++++ b/include/configs/stm32mp15_st_common.h +@@ -10,7 +10,8 @@ + + #define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" \ +- "console=ttySTM0\0" ++ "console=ttySTM0\0" \ ++ "silent=1\0" + + #include - #endif /* ifndef CONFIG_SPL_BUILD */ -- -2.17.1 +2.25.1