diff --git a/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.01.bb b/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.01.bb deleted file mode 100644 index 8752651..0000000 --- a/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.01.bb +++ /dev/null @@ -1,27 +0,0 @@ -SUMMARY = "U-Boot bootloader fw_printenv/setenv utilities" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" - -SRC_URI = " \ - file://fw_env.config.mmc \ - file://fw_env.config.nand \ - file://fw_env.config.nor \ -" -DEPENDS += "u-boot-fw-utils" - -# Specific function to manage any trial for source code extraction through -# devtool which can not be supported as we're sharing original source from -# virtual/bootloader provider via STAGING_UBOOT_DIR shared folder -python () { - if bb.data.inherits_class('devtool-source', d): - bb.fatal('The %s recipe does not actually check out own source and thus cannot be supported by devtool.' % d.getVar("BPN")) -} - -do_install () { - install -d ${D}${sysconfdir} - install -m 0644 ${WORKDIR}/fw_env.config.* ${D}${sysconfdir}/ -} - - -FILES_${PN} += "${sysconfdir}/" -RDEPENDS_${PN} += "u-boot-fw-utils" diff --git a/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.10.bb b/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.10.bb new file mode 100644 index 0000000..2696698 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-fw-config-stm32mp_2020.10.bb @@ -0,0 +1,24 @@ +SUMMARY = "U-Boot bootloader fw_printenv/setenv utilities" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +SRC_URI = " \ + file://fw_env.config.mmc \ + file://fw_env.config.nand \ + file://fw_env.config.nor \ +" + +DEPENDS += "u-boot-fw-utils" + +do_install () { + install -d ${D}${sysconfdir} + install -m 0644 ${WORKDIR}/fw_env.config.* ${D}${sysconfdir}/ + if ${@bb.utils.contains('MACHINE_FEATURES','fip','true','false',d)}; then + sed -i 's/ssbl/fip/g' ${D}${sysconfdir}/fw_env.config.mmc + sed -i 's/0x280000/0x480000/g' ${D}${sysconfdir}/fw_env.config.nor + sed -i 's/0x2C0000/0x4C0000/g' ${D}${sysconfdir}/fw_env.config.nor + fi +} + +FILES_${PN} += "${sysconfdir}/" +RDEPENDS_${PN} += "u-boot-fw-utils" diff --git a/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc b/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc index 5faf149..e0f24d5 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp-archiver.inc @@ -35,94 +35,153 @@ archiver_create_makefile_for_sdk() { mkdir -p ${ARCHIVER_OUTDIR} - # Remove default variable - echo "LDFLAGS=" > ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "CFLAGS=" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "CPPFLAGS=" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk + cat << EOF > ${ARCHIVER_OUTDIR}/Makefile.sdk +# Set default path +SRC_PATH ?= \$(PWD) +BLD_PATH ?= \$(SRC_PATH)/../build +DEPLOYDIR ?= \$(SRC_PATH)/../deploy - echo "LOCAL_PATH=\$(PWD)" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "UBOOT_LOCALVERSION=${UBOOT_LOCALVERSION}" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +# Remove default variables +LDFLAGS = +CFLAGS = +CPPFLAGS = - # Configure default U-Boot configs - echo "UBOOT_CONFIGS ?= ${uboot_configs}" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "DEVICE_TREE ?= ${UBOOT_DEVICETREE}" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +UBOOT_LOCALVERSION = ${UBOOT_LOCALVERSION} - echo "help:" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo \"Configured U-Boot config(s):\"" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @for config in \$(UBOOT_CONFIGS); do \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " defconfig=\$\$(echo \$\$config | cut -d',' -f1) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " type=\$\$(echo \$\$config | cut -d',' -f2) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " binary=\$\$(echo \$\$config | cut -d',' -f3) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo \" \$\$defconfig config (\$\$type type) for \$\$binary binary\" ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " for devicetree in \$(DEVICE_TREE); do \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo \" with device tree: \$\$devicetree\" ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " done ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " done" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo \"Available targets:\"" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo \" all : build U-Boot binaries for defined config(s)\"" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @echo \" clean : clean build directories from generated files\"" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +# Configure default U-Boot configs +UBOOT_CONFIGS ?= ${uboot_configs} +DEVICE_TREE ?= ${UBOOT_DEVICETREE} - echo "version:" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @if test ! -e .scmversion ; then echo \$(UBOOT_LOCALVERSION) > \$(LOCAL_PATH)/.scmversion; fi" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +# Configure default fip feature +ENABLE_FIP ?= "${@bb.utils.contains('MACHINE_FEATURES','fip','1','',d)}" - echo "all: version" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " for config in \$(UBOOT_CONFIGS); do \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " uboot_config=\$\$(echo \$\$config | cut -d',' -f1) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " uboot_type=-\$\$(echo \$\$config | cut -d',' -f2) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " uboot_binary=\$\$(echo \$\$config | cut -d',' -f3) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " uboot_suffix=\$\$(echo \$\$uboot_binary | cut -d'.' -f2) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - # Make sure about configuration set - echo " if test -z \"\$\$uboot_config\" -o -z \"\$\$uboot_type\" -o -z \"\$\$uboot_binary\"; then \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo \"[ERROR] UBOOT_CONFIGS wrongly configured. It should be space separated list of element ,,\" ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " exit 1 ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " fi ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - # Init folder and defconfig selected - echo " if [ ! -d \$(LOCAL_PATH)/../build\$\$uboot_type ]; then \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " mkdir -p \$(LOCAL_PATH)/../build\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo \$(UBOOT_LOCALVERSION) > \$(LOCAL_PATH)/../build\$\$uboot_type/.scmversion ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " \$(MAKE) -C \$(LOCAL_PATH) O=\$(LOCAL_PATH)/../build\$\$uboot_type \$\$uboot_config ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " fi ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - # Build binaries - echo " if [ -z \"\$(DEVICE_TREE)\" ]; then \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " \$(MAKE) -C \$(LOCAL_PATH) O=\$(LOCAL_PATH)/../build\$\$uboot_type ${UBOOT_MAKE_TARGET} ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - # Copy binary files with explicit name - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/\$\$uboot_binary \$(LOCAL_PATH)/../build\$\$uboot_type/u-boot\$\$uboot_type.\$\$uboot_suffix ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${UBOOT_ELF} \$(LOCAL_PATH)/../build\$\$uboot_type/u-boot\$\$uboot_type.${UBOOT_ELF_SUFFIX} ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " if [ -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARY_STM32} ]; then \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARY_STM32} \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARYNAME}\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_ELF} \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_ELF_NAME}\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " fi ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " else \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " for devicetree in \$(DEVICE_TREE); do \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " \$(MAKE) -C \$(LOCAL_PATH) O=\$(LOCAL_PATH)/../build\$\$uboot_type ${UBOOT_MAKE_TARGET} DEVICE_TREE=\$\$devicetree DEVICE_TREE_EXT=\$\$devicetree.dtb; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - # Copy binary files with explicit name - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/\$\$uboot_binary \$(LOCAL_PATH)/../build\$\$uboot_type/u-boot-\$\$devicetree\$\$uboot_type.\$\$uboot_suffix ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${UBOOT_ELF} \$(LOCAL_PATH)/../build\$\$uboot_type/u-boot-\$\$devicetree\$\$uboot_type.${UBOOT_ELF_SUFFIX} ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " if [ -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARY_STM32} ]; then \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARY_STM32} \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_BINARYNAME}-\$\$devicetree\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " cp -f \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_ELF} \$(LOCAL_PATH)/../build\$\$uboot_type/${SPL_ELF_NAME}-\$\$devicetree\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " fi ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " done ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " fi ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " done" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo "" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +help: + @echo + @echo "Configured U-Boot config(s):" + @for config in \$(UBOOT_CONFIGS); do \\ + defconfig=\$\$(echo \$\$config | cut -d',' -f1) ; \\ + type=\$\$(echo \$\$config | cut -d',' -f2) ; \\ + binary=\$\$(echo \$\$config | cut -d',' -f3) ; \\ + echo " \$\$defconfig config (\$\$type type) for \$\$binary binary" ; \\ + for devicetree in \$(DEVICE_TREE); do \\ + echo " with device tree: \$\$devicetree" ; \\ + done ; \\ + done + @echo + @echo "U-Boot folder configuration:" + @echo " SRC_PATH = \$(SRC_PATH)" + @echo " BLD_PATH = \$(BLD_PATH)" + @echo " DEPLOYDIR = \$(DEPLOYDIR)" + @echo + @echo "FIP configuration:" + @echo " ENABLE_FIP = \$(ENABLE_FIP) ('1' to generate fip binary)" +ifeq (\$(ENABLE_FIP),1) + @echo " Do not forget to set FIP deploydir folders (such as FIP_DEPLOYDIR_ROOT) to provide path to needed binaries" +endif + @echo + @echo "Available targets:" + @echo " all : build U-Boot binaries for defined config(s)" + @echo " clean : clean build directories from generated files" - echo "clean:" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " @for config in \$(UBOOT_CONFIGS); do \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " uboot_type=-\$\$(echo \$\$config | cut -d',' -f2) ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " echo \"Removing \$(LOCAL_PATH)/../build\$\$uboot_type ...\" ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " rm -rf \$(LOCAL_PATH)/../build\$\$uboot_type ; \\" >> ${ARCHIVER_OUTDIR}/Makefile.sdk - echo " done" >> ${ARCHIVER_OUTDIR}/Makefile.sdk +version: + @if test ! -e .scmversion ; then echo \$(UBOOT_LOCALVERSION) > \$(SRC_PATH)/.scmversion; fi + +all: uboot \$(if \$(ENABLE_FIP),fip) + +uboot: version + @for config in \$(UBOOT_CONFIGS); do \\ + uboot_config=\$\$(echo \$\$config | cut -d',' -f1) ; \\ + uboot_type=\$\$(echo \$\$config | cut -d',' -f2) ; \\ + uboot_binary=\$\$(echo \$\$config | cut -d',' -f3) ; \\ + uboot_suffix=\$\$(echo \$\$uboot_binary | cut -d'.' -f2) ; \\ + # Configure destination folder \\ + if [ "\$\$uboot_suffix" = "img" ]; then \\ + subfolder=/\$\$uboot_type ; \\ + else \\ + subfolder= ; \\ + fi ; \\ + mkdir -p \$(DEPLOYDIR)\$\$subfolder ; \\ + mkdir -p \$(DEPLOYDIR)\$\$subfolder/debug ; \\ + # Make sure about configuration set \\ + if test -z "\$\$uboot_config" -o -z "\$\$uboot_type" -o -z "\$\$uboot_binary"; then \\ + echo ; \\ + echo "[ERROR] UBOOT_CONFIGS wrongly configured. It should be space separated list of element ,," ; \\ + echo ; \\ + exit 1 ; \\ + fi ; \\ + # Dynamic update for defconfig file \\ + if [ "\$\$uboot_suffix" = "stm32" ]; then \\ + if ! grep -q 'CONFIG_STM32MP15x_STM32IMAGE=y' "\$(SRC_PATH)/configs/\$\$uboot_config"; then \\ + echo "CONFIG_STM32MP15x_STM32IMAGE=y" >> "\$(SRC_PATH)/configs/\$\$uboot_config" ; \\ + fi ; \\ + fi ; \\ + # Init folder and defconfig selected \\ + if [ ! -d \$(BLD_PATH)/\$\$uboot_type ]; then \\ + mkdir -p \$(BLD_PATH)/\$\$uboot_type ; \\ + echo \$(UBOOT_LOCALVERSION) > \$(BLD_PATH)/\$\$uboot_type/.scmversion ; \\ + \$(MAKE) -C \$(SRC_PATH) O=\$(BLD_PATH)/\$\$uboot_type \$\$uboot_config ; \\ + fi ; \\ + # Build binaries \\ + if [ -z "\$(DEVICE_TREE)" ]; then \\ + \$(MAKE) -C \$(SRC_PATH) O=\$(BLD_PATH)/\$\$uboot_type ${UBOOT_MAKE_TARGET} ; \\ + # Copy binary files with explicit name \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/\$\$uboot_binary \$(DEPLOYDIR)\$\$subfolder/u-boot-\$\$uboot_type.\$\$uboot_suffix ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${SPL_BINARY_STM32} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${SPL_BINARY_STM32} \$(DEPLOYDIR)\$\$subfolder/${SPL_BINARYNAME}-\$\$uboot_type ; \\ + fi ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${UBOOT_ELF} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${UBOOT_ELF} \$(DEPLOYDIR)\$\$subfolder/debug/u-boot-\$\$uboot_type.${UBOOT_ELF_SUFFIX} ; \\ + fi ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${SPL_ELF} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${SPL_ELF} \$(DEPLOYDIR)\$\$subfolder/debug/${SPL_ELF_NAME}-\$\$uboot_type ; \\ + fi ; \\ + # Install 'u-boot-nodtb.bin' binary in case '*.dtb' binary installation configured \\ + if [ "\$\$uboot_suffix" = "dtb" ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/u-boot-nodtb.bin \$(DEPLOYDIR)\$\$subfolder/u-boot-nodtb.bin ; \\ + fi ; \\ + else \\ + for devicetree in \$(DEVICE_TREE); do \\ + \$(MAKE) -C \$(SRC_PATH) O=\$(BLD_PATH)/\$\$uboot_type ${UBOOT_MAKE_TARGET} DEVICE_TREE=\$\$devicetree DEVICE_TREE_EXT=\$\$devicetree.dtb; \\ + # Copy binary files with explicit name \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/\$\$uboot_binary \$(DEPLOYDIR)\$\$subfolder/u-boot-\$\$devicetree-\$\$uboot_type.\$\$uboot_suffix ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${SPL_BINARY_STM32} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${SPL_BINARY_STM32} \$(DEPLOYDIR)\$\$subfolder/${SPL_BINARYNAME}-\$\$devicetree-\$\$uboot_type ; \\ + fi ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${UBOOT_ELF} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${UBOOT_ELF} \$(DEPLOYDIR)\$\$subfolder/debug/u-boot-\$\$devicetree-\$\$uboot_type.${UBOOT_ELF_SUFFIX} ; \\ + fi ; \\ + if [ -f \$(BLD_PATH)/\$\$uboot_type/${SPL_ELF} ]; then \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/${SPL_ELF} \$(DEPLOYDIR)\$\$subfolder/debug/${SPL_ELF_NAME}-\$\$devicetree-\$\$uboot_type ; \\ + fi ; \\ + # Install ''u-boot-nodtb.bin' binary in case '*.dtb' binary installation configured \\ + if [ "\$\$uboot_suffix" = "dtb" ]; then \\ + # Init soc suffix \\ + soc_suffix="" ; \\ + if [ -n "${STM32MP_SOC_NAME}" ]; then \\ + for soc in ${STM32MP_SOC_NAME}; do \\ + if [ "\$\$(echo \$\$devicetree | grep -c \$\$soc)" -eq 1 ]; then \\ + soc_suffix="-\$\$soc" ; \\ + fi ; \\ + done ; \\ + fi ; \\ + cp -f \$(BLD_PATH)/\$\$uboot_type/u-boot-nodtb.bin \$(DEPLOYDIR)\$\$subfolder/u-boot-nodtb\$\$soc_suffix.bin ; \\ + fi ; \\ + done ; \\ + fi ; \\ + done + +fip: uboot + FIP_DEPLOYDIR_UBOOT=\$(DEPLOYDIR) FIP_DEVICETREE="\$(DEVICE_TREE)" fiptool-stm32mp + +clean: + @for config in \$(UBOOT_CONFIGS); do \\ + uboot_type=\$\$(echo \$\$config | cut -d',' -f2) ; \\ + echo "Removing \$(BLD_PATH)/\$\$uboot_type ..." ; \\ + rm -rf \$(BLD_PATH)/\$\$uboot_type ; \\ + done + @echo "Removing \$(DEPLOYDIR) ..." + @rm -rf \$(DEPLOYDIR) + @echo +EOF } do_ar_original[prefuncs] += "archiver_create_makefile_for_sdk" diff --git a/recipes-bsp/u-boot/u-boot-stm32mp-common_2020.01.inc b/recipes-bsp/u-boot/u-boot-stm32mp-common_2020.10.inc similarity index 53% rename from recipes-bsp/u-boot/u-boot-stm32mp-common_2020.01.inc rename to recipes-bsp/u-boot/u-boot-stm32mp-common_2020.10.inc index 8ca458f..a6e0f45 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp-common_2020.01.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp-common_2020.10.inc @@ -4,7 +4,7 @@ HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome" SECTION = "bootloaders" LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=5a7450c57ffe5ae63fd732446b988025" DEPENDS += "dtc-native bc-native" DEPENDS += "flex-native bison-native" @@ -12,27 +12,20 @@ DEPENDS += "flex-native bison-native" COMPATIBLE_MACHINE = "(stm32mpcommon)" SRC_URI = "git://github.com/u-boot/u-boot.git;protocol=https" -SRCREV = "0b0c6af38738f2c132cfd41a240889acaa031c8f" +SRCREV = "050acee119b3757fee3bd128f55d720fdd9bb890" SRC_URI += "\ - file://0001-ARM-v2020.01-stm32mp-r1-MACHINE.patch \ - file://0002-ARM-v2020.01-stm32mp-r1-BOARD.patch \ - file://0003-ARM-v2020.01-stm32mp-r1-MISC-DRIVERS.patch \ - file://0004-ARM-v2020.01-stm32mp-r1-DEVICETREE.patch \ - file://0005-ARM-v2020.01-stm32mp-r1-CONFIG.patch \ - \ - file://0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch \ - file://0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch \ - file://0008-ARM-v2020.01-stm32mp-r2-BOARD.patch \ - file://0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch \ - file://0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch \ + file://0001-ARM-v2020.10-stm32mp-r1-MACHINE.patch \ + file://0002-ARM-v2020.10-stm32mp-r1-BOARD.patch \ + file://0003-ARM-v2020.10-stm32mp-r1-MISC-DRIVERS.patch \ + file://0004-ARM-v2020.10-stm32mp-r1-DEVICETREE.patch \ + file://0005-ARM-v2020.10-stm32mp-r1-CONFIG.patch \ \ file://0099-Add-external-var-to-allow-build-of-new-devicetree-fi.patch \ - file://remove-redundant-yyloc-global.patch \ " -U_BOOT_VERSION = "2020.01" -PV = "${U_BOOT_VERSION}.r2" +U_BOOT_VERSION = "2020.10" +PV = "${U_BOOT_VERSION}.r1" S = "${WORKDIR}/git" @@ -42,7 +35,7 @@ S = "${WORKDIR}/git" BBCLASSEXTEND = "devupstream:target" SRC_URI_class-devupstream = "git://github.com/STMicroelectronics/u-boot.git;protocol=https;branch=v${U_BOOT_VERSION}-stm32mp" -SRCREV_class-devupstream = "7d786860495d4d121a13f949cdca589ebfb281bf" +SRCREV_class-devupstream = "d2c99cb7e5b7dc74236f67fcced156956155cd71" # --------------------------------- # Configure default preference to manage dynamic selection between tarball and github diff --git a/recipes-bsp/u-boot/u-boot-stm32mp.inc b/recipes-bsp/u-boot/u-boot-stm32mp.inc index e05948e..dec41fc 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp.inc +++ b/recipes-bsp/u-boot/u-boot-stm32mp.inc @@ -14,7 +14,7 @@ SPL_BINARYNAME = "${@os.path.basename(d.getVar("SPL_BINARY_STM32"))}" SPL_BINARYROOT = "${@d.getVar('SPL_BINARY_STM32').split('.')[0]}" # Configure for debug elf -ELF_DEBUG_ENABLE ?= "" +ELF_DEBUG_ENABLE ?= "1" UBOOT_ELF = "${@'u-boot' if d.getVar('ELF_DEBUG_ENABLE') == '1' else ''}" SPL_ELF = "${@'${SPL_BINARYROOT}' if d.getVar('ELF_DEBUG_ENABLE') == '1' else ''}" SPL_ELF_NAME = "${@os.path.basename(d.getVar("SPL_ELF"))}.elf" @@ -22,6 +22,10 @@ SPL_ELF_NAME = "${@os.path.basename(d.getVar("SPL_ELF"))}.elf" # Init UBOOT_DEVICETREE list if not configured UBOOT_DEVICETREE ?= "" +# Init default MTDPART configurations +UBOOT_MTDPART_CHECK_ENABLE ??= "" +UBOOT_MTDPART_CHECK ??= "" + # ----------------------------------------------- # Enable use of work-shared folder STAGING_UBOOT_DIR = "${TMPDIR}/work-shared/${MACHINE}/uboot-source" @@ -55,6 +59,84 @@ base_do_unpack_append () { os.symlink(ubootsrc, s) } +# ----------------------------------------------------------------------------- +# Prepend configure to handle specific configuration (here fip) +# +do_configure_prepend() { + if [ -n "${UBOOT_CONFIG}" ]; then + unset i j + for config in ${UBOOT_MACHINE}; do + if [ -f "${S}/configs/${config}" ]; then + # Create copy of original defconfig + cp -f "${S}/configs/${config}" "${WORKDIR}/" + i=$(expr $i + 1); + for binary in ${UBOOT_BINARIES}; do + j=$(expr $j + 1); + if [ $j -eq $i ]; then + binarysuffix=$(echo ${binary} | cut -d'.' -f2) + # Make sure to select STM32IMAGE if requested + if [ "${binarysuffix}" = "stm32" ]; then + if ! grep -q 'CONFIG_STM32MP15x_STM32IMAGE=y' "${S}/configs/${config}"; then + echo "CONFIG_STM32MP15x_STM32IMAGE=y" >> "${S}/configs/${config}" + fi + fi + fi + done + unset j + fi + done + unset i + fi +} + +# ----------------------------------------------------------------------------- +# Append configure to handle specific MTDPART check if required +# +do_configure_append() { + if [ -n "${UBOOT_MTDPART_CHECK_ENABLE}" ]; then + if [ -n "${UBOOT_CONFIG}" ]; then + for config in ${UBOOT_MACHINE}; do + for mtdpart_check_config in ${UBOOT_MTDPART_CHECK_ENABLE}; do + if [ "${mtdpart_check_config}" = "${config}" ]; then + if [ -f "${B}/${config}/.config" ]; then + for mtdpart_chk in $(echo "${UBOOT_MTDPART_CHECK}"); do + mtdpart_conf=$(echo ${mtdpart_chk} | cut -d'=' -f1) + mtdpart_set=$(echo ${mtdpart_chk} | cut -d'=' -f2) + if grep -q "${mtdpart_conf}=" "${B}/${config}/.config"; then + bbnote "Found ${mtdpart_conf} definition in '.config' file from '${config}/' build folder" + # Get the current MTDPART configuration settings (and remove the double quotes) + mtdpart_cur=$(grep "${mtdpart_conf}=" "${B}/${config}/.config" | cut -d'=' -f2 | sed 's/"//g') + # Init for loop on configured partition list + i=0 + mtdpart_count=$(echo "${mtdpart_cur}" | awk -F',' '{print NF-1}') + while [ ${i} -lt "${mtdpart_count}" ]; do + i=$(expr $i + 1) + mtdpart_cur_size=$(echo ${mtdpart_cur} | cut -d',' -f${i} | sed 's/\([0-9]*[mk]\).*/\1/') + mtdpart_set_size=$(echo ${mtdpart_set} | cut -d',' -f${i} | sed 's/\([0-9]*\).*/\1/') + # Make sure to use KiB format for partition size + if [ -z "$(echo ${mtdpart_cur_size} | grep m)" ]; then + cur_size_kb=$(echo ${mtdpart_cur_size} | sed 's/k//') + else + cur_size_kb=$(expr $(echo ${mtdpart_cur_size} | sed 's/m//') \* 1024) + fi + # Compare partition size + if [ "${mtdpart_set_size}" != "${cur_size_kb}" ]; then + bbfatal "The default settings for ${mtdpart_conf} (${mtdpart_cur}) is different from the one configured (${mtdpart_set}) : ${mtdpart_set_size}k versus ${mtdpart_cur_size}" + fi + done + bbnote "Found ${mtdpart_set} settings for ${mtdpart_conf} in '.config' file from '${config}/' build folder : configuration is ok" + else + bbfatal "${mtdpart_conf} definition not found in '.config' file from '${config}/' build folder : may need update for CONFIG name..." + fi + done + fi + fi + done + done + fi + fi +} + # ----------------------------------------------------------------------------- # Append compile to handle specific device tree compilation # @@ -75,6 +157,7 @@ do_compile_append() { oe_runmake -C ${S} O=${B}/${config} DEVICE_TREE=${devicetree} DEVICE_TREE_EXT=${devicetree}.dtb for binary in ${UBOOT_BINARIES}; do binarysuffix=$(echo ${binary} | cut -d'.' -f2) + binaryprefix=$(echo ${binary} | cut -d'.' -f1) k=$(expr $k + 1); if [ $k -eq $i ]; then install -m 644 ${B}/${config}/${binary} ${B}/${config}/u-boot-${devicetree}-${type}.${binarysuffix} @@ -107,16 +190,13 @@ do_compile_append() { # ----------------------------------------------------------------------------- # Append deploy to handle specific device tree binary deployement # -do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}/bootloader" +do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}/u-boot" do_deploy_append() { if [ -n "${UBOOT_DEVICETREE}" ]; then # Clean deploydir from any available binary first # This allows to only install the devicetree binary ones rm -rf ${DEPLOYDIR} - # Install destination folder - install -d ${DEPLOYDIR} - for devicetree in ${UBOOT_DEVICETREE}; do if [ -n "${UBOOT_CONFIG}" ]; then unset i j k @@ -129,17 +209,43 @@ do_deploy_append() { binarysuffix=$(echo ${binary} | cut -d'.' -f2) k=$(expr $k + 1); if [ $k -eq $i ]; then - install -m 644 ${B}/${config}/u-boot-${devicetree}-${type}.${binarysuffix} ${DEPLOYDIR} + # Manage subfolder in case of u-boot.img + if [ "${binarysuffix}" = "img" ]; then + SUBFOLDER=/${type} + else + SUBFOLDER="" + fi + # Install destination folder + install -d ${DEPLOYDIR}${SUBFOLDER} + if [ -n "${ELF_DEBUG_ENABLE}" ]; then + install -d ${DEPLOYDIR}${SUBFOLDER}/debug + fi + # Install u-boot binary + install -m 644 ${B}/${config}/u-boot-${devicetree}-${type}.${binarysuffix} ${DEPLOYDIR}${SUBFOLDER} if [ -n "${UBOOT_ELF}" ]; then - install -m 644 ${B}/${config}/u-boot-${devicetree}-${type}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR} + install -d ${DEPLOYDIR}${SUBFOLDER}/debug + install -m 644 ${B}/${config}/u-boot-${devicetree}-${type}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR}${SUBFOLDER}/debug/ + fi + # Install 'u-boot-nodtb.bin' binary in case '*.dtb' binary installation configured + if [ "${binarysuffix}" = "dtb" ]; then + # Init soc suffix + soc_suffix="" + if [ -n "${STM32MP_SOC_NAME}" ]; then + for soc in ${STM32MP_SOC_NAME}; do + if [ "$(echo ${devicetree} | grep -c ${soc})" -eq 1 ]; then + soc_suffix="-${soc}" + fi + done + fi + install -m 644 ${B}/${config}/u-boot-nodtb.bin ${DEPLOYDIR}${SUBFOLDER}/u-boot-nodtb${soc_suffix}.bin fi # As soon as SPL binary exists, install it # This allow to mix u-boot configuration, with and without SPL if [ -f ${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type} ]; then - install -m 644 ${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type} ${DEPLOYDIR} + install -m 644 ${B}/${config}/${SPL_BINARYNAME}-${devicetree}-${type} ${DEPLOYDIR}${SUBFOLDER}/ fi if [ -n "${SPL_ELF}" ] && [ -f ${B}/${config}/${SPL_ELF_NAME}-${devicetree}-${type} ]; then - install -m 644 ${B}/${config}/${SPL_ELF_NAME}-${devicetree}-${type} ${DEPLOYDIR} + install -m 644 ${B}/${config}/${SPL_ELF_NAME}-${devicetree}-${type} ${DEPLOYDIR}${SUBFOLDER}/debug fi fi done diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.01-stm32mp-r1-MACHINE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.01-stm32mp-r1-MACHINE.patch deleted file mode 100644 index 8888864..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.01-stm32mp-r1-MACHINE.patch +++ /dev/null @@ -1,5105 +0,0 @@ -From c4b103412f1a8cd3472b9d82f7d73737803cf7e7 Mon Sep 17 00:00:00 2001 -From: Romuald JEANNE -Date: Fri, 5 Jun 2020 13:41:19 +0200 -Subject: [PATCH 1/5] ARM v2020.01-stm32mp-r1 MACHINE - ---- - .gitignore | 3 + - CONTRIBUTING.md | 30 + - MAINTAINERS | 1 + - Makefile | 2 +- - arch/arm/lib/bootm.c | 3 + - arch/arm/lib/crt0.S | 3 +- - arch/arm/mach-stm32mp/Kconfig | 79 +- - arch/arm/mach-stm32mp/Makefile | 4 +- - arch/arm/mach-stm32mp/boot_params.c | 45 + - arch/arm/mach-stm32mp/bsec.c | 121 +- - arch/arm/mach-stm32mp/cmd_stm32prog/Makefile | 9 + - .../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 191 +++ - arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 1743 ++++++++++++++++++++ - arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 185 +++ - .../mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 993 +++++++++++ - .../arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 232 +++ - arch/arm/mach-stm32mp/cpu.c | 107 +- - arch/arm/mach-stm32mp/dram_init.c | 18 + - arch/arm/mach-stm32mp/fdt.c | 132 +- - arch/arm/mach-stm32mp/include/mach/bsec.h | 7 + - arch/arm/mach-stm32mp/include/mach/ddr.h | 6 +- - arch/arm/mach-stm32mp/include/mach/stm32.h | 24 +- - arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h | 13 +- - arch/arm/mach-stm32mp/include/mach/stm32prog.h | 16 + - arch/arm/mach-stm32mp/include/mach/sys_proto.h | 24 +- - arch/arm/mach-stm32mp/psci.c | 22 + - arch/arm/mach-stm32mp/pwr_regulator.c | 31 +- - arch/arm/mach-stm32mp/spl.c | 43 +- - arch/arm/mach-stm32mp/syscon.c | 1 - - arch/sandbox/dts/test.dts | 85 +- - arch/sandbox/include/asm/gpio.h | 38 +- - 31 files changed, 4044 insertions(+), 167 deletions(-) - create mode 100644 CONTRIBUTING.md - create mode 100644 arch/arm/mach-stm32mp/boot_params.c - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/Makefile - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c - create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c - create mode 100644 arch/arm/mach-stm32mp/include/mach/bsec.h - create mode 100644 arch/arm/mach-stm32mp/include/mach/stm32prog.h - -diff --git a/.gitignore b/.gitignore -index 2e1c8bf..bb2dfee 100644 ---- a/.gitignore -+++ b/.gitignore -@@ -92,3 +92,6 @@ GTAGS - *.orig - *~ - \#*# -+ -+/oe-* -+bitbake-cookerdaemon.log -diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md -new file mode 100644 -index 0000000..3d1bacd ---- /dev/null -+++ b/CONTRIBUTING.md -@@ -0,0 +1,30 @@ -+# Contributing guide -+ -+This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you. -+ -+This guide mainly focuses on the proper use of Git. -+ -+## 1. Issues -+ -+STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus). -+ -+## 2. Pull Requests -+ -+STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. -+ -+* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). -+* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. -+* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com). -+ -+Please note that: -+* The Corporate CLA will always take precedence over the Individual CLA. -+* One CLA submission is sufficient, for any project proposed by STMicroelectronics. -+ -+__How to proceed__ -+ -+* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version. -+* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted. -+ -+__Note__ -+ -+Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered. -diff --git a/MAINTAINERS b/MAINTAINERS -index 438fb22..afc2f19 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -337,6 +337,7 @@ L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) - T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git - S: Maintained - F: arch/arm/mach-stm32mp/ -+F: doc/board/st/ - F: drivers/adc/stm32-adc* - F: drivers/clk/clk_stm32mp1.c - F: drivers/gpio/stm32_gpio.c -diff --git a/Makefile b/Makefile -index 1766f5a..8b390bc 100644 ---- a/Makefile -+++ b/Makefile -@@ -3,7 +3,7 @@ - VERSION = 2020 - PATCHLEVEL = 01 - SUBLEVEL = --EXTRAVERSION = -+EXTRAVERSION = -stm32mp-r1 - NAME = - - # *DOCUMENTATION* -diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c -index 769a642..9453c09 100644 ---- a/arch/arm/lib/bootm.c -+++ b/arch/arm/lib/bootm.c -@@ -74,6 +74,9 @@ void arch_lmb_reserve(struct lmb *lmb) - gd->bd->bi_dram[bank].size - 1; - if (sp > bank_end) - continue; -+ if (bank_end > gd->ram_top) -+ bank_end = gd->ram_top - 1; -+ - lmb_reserve(lmb, sp, bank_end - sp + 1); - break; - } -diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S -index fb6c37c..df9dd83 100644 ---- a/arch/arm/lib/crt0.S -+++ b/arch/arm/lib/crt0.S -@@ -127,8 +127,7 @@ ENTRY(_main) - ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ - bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ - mov sp, r0 -- ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ -- sub r9, r9, #GD_SIZE /* new GD is below bd */ -+ ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ - - adr lr, here - ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ -diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig -index ae28f6e..f9f7943 100644 ---- a/arch/arm/mach-stm32mp/Kconfig -+++ b/arch/arm/mach-stm32mp/Kconfig -@@ -33,8 +33,8 @@ config SYS_MALLOC_LEN - config ENV_SIZE - default 0x2000 - --config TARGET_STM32MP1 -- bool "Support stm32mp1xx" -+config STM32MP15x -+ bool "Support STMicroelectronics STM32MP15x Soc" - select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED - select CPU_V7A - select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED -@@ -45,19 +45,47 @@ config TARGET_STM32MP1 - select STM32_RESET - select STM32_SERIAL - select SYS_ARCH_TIMER -+ imply CMD_NVEDIT_INFO -+ imply SYSRESET_PSCI if STM32MP1_TRUSTED -+ imply SYSRESET_SYSCON if !STM32MP1_TRUSTED -+ help -+ support of STMicroelectronics SOC STM32MP15x family -+ STM32MP157, STM32MP153 or STM32MP151 -+ STMicroelectronics MPU with core ARMv7 -+ dual core A7 for STM32MP157/3, monocore for STM32MP151 -+ target all the STMicroelectronics board with SOC STM32MP1 family -+ -+choice -+ prompt "STM32MP15x board select" -+ optional -+ -+config TARGET_ST_STM32MP15x -+ bool "STMicroelectronics STM32MP15x boards" -+ select STM32MP15x - imply BOOTCOUNT_LIMIT -+ imply BOOTSTAGE - imply CMD_BOOTCOUNT -+ imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE -- imply SYSRESET_PSCI if STM32MP1_TRUSTED -- imply SYSRESET_SYSCON if !STM32MP1_TRUSTED -+ imply VERSION_VARIABLE - help -- target STMicroelectronics SOC STM32MP1 family -- STM32MP157, STM32MP153 or STM32MP151 -- STMicroelectronics MPU with core ARMv7 -- dual core A7 for STM32MP157/3, monocore for STM32MP151 -+ target the STMicroelectronics board with SOC STM32MP15x -+ managed by board/st/stm32mp1: -+ Evalulation board (EV1) or Discovery board (DK1 and DK2). -+ The difference between board are managed with devicetree -+ -+config TARGET_DH_STM32MP1_PDK2 -+ bool "DH STM32MP1 PDK2" -+ select STM32MP15x -+ imply BOOTCOUNT_LIMIT -+ imply CMD_BOOTCOUNT -+ help -+ Target the DH PDK2 development kit with STM32MP15x SoM. -+ -+endchoice - - config STM32MP1_TRUSTED - bool "Support trusted boot with TF-A" -@@ -69,23 +97,8 @@ config STM32MP1_TRUSTED - BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32 - TF-A monitor provides proprietary SMC to manage secure devices - --config STM32MP1_OPTEE -- bool "Support trusted boot with TF-A and OP-TEE" -- depends on STM32MP1_TRUSTED -- default n -- help -- Say Y here to enable boot with TF-A and OP-TEE -- Trusted boot chain is : -- BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32 -- OP-TEE monitor provides ST SMC to access to secure resources -- - config SYS_TEXT_BASE -- prompt "U-Boot base address" - default 0xC0100000 -- help -- configure the U-Boot base address -- when DDR driver is used: -- DDR + 1MB (0xC0100000) - - config NR_DRAM_BANKS - default 1 -@@ -100,11 +113,28 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 - - config STM32_ETZPC - bool "STM32 Extended TrustZone Protection" -- depends on TARGET_STM32MP1 -+ depends on STM32MP15x - default y - help - Say y to enable STM32 Extended TrustZone Protection - -+config CMD_STM32PROG -+ bool "command stm32prog for STM32CudeProgrammer" -+ select DFU -+ select DFU_RAM -+ select DFU_VIRT -+ select PARTITION_TYPE_GUID -+ imply CMD_GPT if MMC -+ imply CMD_MTD if MTD -+ imply DFU_MMC if MMC -+ imply DFU_MTD if MTD -+ help -+ activate a specific command stm32prog for STM32MP soc family -+ witch update the device with the tools STM32CubeProgrammer, -+ using UART with STM32 protocol or USB with DFU protocol -+ NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based -+ on U-Boot DFU framework -+ - config CMD_STM32KEY - bool "command stm32key to fuse public key hash" - default y -@@ -147,5 +177,6 @@ config DEBUG_UART_CLOCK - endif - - source "board/st/stm32mp1/Kconfig" -+source "board/dhelectronics/dh_stm32mp1/Kconfig" - - endif -diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile -index eee39c2..1fdacf4 100644 ---- a/arch/arm/mach-stm32mp/Makefile -+++ b/arch/arm/mach-stm32mp/Makefile -@@ -6,13 +6,15 @@ - obj-y += cpu.o - obj-y += dram_init.o - obj-y += syscon.o -+obj-y += bsec.o - - ifdef CONFIG_SPL_BUILD - obj-y += spl.o - else --obj-y += bsec.o -+obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/ - obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o - obj-$(CONFIG_ARMV7_PSCI) += psci.o -+obj-$(CONFIG_STM32MP1_TRUSTED) += boot_params.o - endif - - obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o -diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c -new file mode 100644 -index 0000000..e4351de ---- /dev/null -+++ b/arch/arm/mach-stm32mp/boot_params.c -@@ -0,0 +1,45 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+ -+/* -+ * Force data-section, as .bss will not be valid -+ * when save_boot_params is invoked. -+ */ -+static unsigned long nt_fw_dtb __section(".data"); -+ -+/* -+ * Save the FDT address provided by TF-A in r2 at boot time -+ * This function is called from start.S -+ */ -+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, -+ unsigned long r3) -+{ -+ nt_fw_dtb = r2; -+ -+ save_boot_params_ret(); -+} -+ -+/* -+ * Use the saved FDT address provided by TF-A at boot time (NT_FW_CONFIG = -+ * Non Trusted Firmware configuration file) when the pointer is valid -+ */ -+void *board_fdt_blob_setup(void) -+{ -+ debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb); -+ -+ /* use external device tree only if address is valid */ -+ if (nt_fw_dtb >= STM32_DDR_BASE) { -+ if (fdt_magic(nt_fw_dtb) == FDT_MAGIC) -+ return (void *)nt_fw_dtb; -+ debug("%s: DTB not found.\n", __func__); -+ } -+ debug("%s: fall back to builtin DTB, %p\n", __func__, &_end); -+ -+ return (void *)&_end; -+} -diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c -index a77c706..7e04ddd 100644 ---- a/arch/arm/mach-stm32mp/bsec.c -+++ b/arch/arm/mach-stm32mp/bsec.c -@@ -7,13 +7,12 @@ - #include - #include - #include -+#include - #include - #include - #include - - #define BSEC_OTP_MAX_VALUE 95 -- --#ifndef CONFIG_STM32MP1_TRUSTED - #define BSEC_TIMEOUT_US 10000 - - /* BSEC REGISTER OFFSET (base relative) */ -@@ -22,11 +21,13 @@ - #define BSEC_OTP_WRDATA_OFF 0x008 - #define BSEC_OTP_STATUS_OFF 0x00C - #define BSEC_OTP_LOCK_OFF 0x010 -+#define BSEC_DENABLE_OFF 0x014 - #define BSEC_DISTURBED_OFF 0x01C - #define BSEC_ERROR_OFF 0x034 --#define BSEC_SPLOCK_OFF 0x064 /* Program safmem sticky lock */ --#define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */ --#define BSEC_SRLOCK_OFF 0x094 /* shadowing sticky lock */ -+#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */ -+#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */ -+#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */ -+#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */ - #define BSEC_OTP_DATA_OFF 0x200 - - /* BSEC_CONFIGURATION Register MASK */ -@@ -46,6 +47,9 @@ - #define BSEC_MODE_PROGFAIL_MASK 0x10 - #define BSEC_MODE_PWR_MASK 0x20 - -+/* DENABLE Register */ -+#define BSEC_DENABLE_DBGSWENABLE BIT(10) -+ - /* - * OTP Lock services definition - * Value must corresponding to the bit number in the register -@@ -53,12 +57,12 @@ - #define BSEC_LOCK_PROGRAM 0x04 - - /** -- * bsec_check_error() - Check status of one otp -- * @base: base address of bsec IP -+ * bsec_lock() - manage lock for each type SR/SP/SW -+ * @address: address of bsec IP register - * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) -- * Return: 0 if no error, -EAGAIN or -ENOTSUPP -+ * Return: true if locked else false - */ --static u32 bsec_check_error(u32 base, u32 otp) -+static bool bsec_read_lock(u32 address, u32 otp) - { - u32 bit; - u32 bank; -@@ -66,21 +70,17 @@ static u32 bsec_check_error(u32 base, u32 otp) - bit = 1 << (otp & OTP_LOCK_MASK); - bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); - -- if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) -- return -EAGAIN; -- else if (readl(base + BSEC_ERROR_OFF + bank) & bit) -- return -ENOTSUPP; -- -- return 0; -+ return !!(readl(address + bank) & bit); - } - -+#ifndef CONFIG_STM32MP1_TRUSTED - /** -- * bsec_lock() - manage lock for each type SR/SP/SW -- * @address: address of bsec IP register -+ * bsec_check_error() - Check status of one otp -+ * @base: base address of bsec IP - * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) -- * Return: true if locked else false -+ * Return: 0 if no error, -EAGAIN or -ENOTSUPP - */ --static bool bsec_read_lock(u32 address, u32 otp) -+static u32 bsec_check_error(u32 base, u32 otp) - { - u32 bit; - u32 bank; -@@ -88,7 +88,12 @@ static bool bsec_read_lock(u32 address, u32 otp) - bit = 1 << (otp & OTP_LOCK_MASK); - bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); - -- return !!(readl(address + bank) & bit); -+ if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) -+ return -EAGAIN; -+ else if (readl(base + BSEC_ERROR_OFF + bank) & bit) -+ return -ENOTSUPP; -+ -+ return 0; - } - - /** -@@ -324,6 +329,16 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) - #endif - } - -+static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) -+{ -+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); -+ -+ /* return OTP permanent write lock status */ -+ *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); -+ -+ return 0; -+} -+ - static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) - { - #ifdef CONFIG_STM32MP1_TRUSTED -@@ -350,22 +365,41 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) - #endif - } - -+static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) -+{ -+#ifdef CONFIG_STM32MP1_TRUSTED -+ if (val == 1) -+ return stm32_smc_exec(STM32_SMC_BSEC, -+ STM32_SMC_WRLOCK_OTP, -+ otp, 0); -+ if (val == 0) -+ return 0; /* nothing to do */ -+ -+ return -EINVAL; -+#else -+ return -ENOTSUPP; -+#endif -+} -+ - static int stm32mp_bsec_read(struct udevice *dev, int offset, - void *buf, int size) - { - int ret; - int i; -- bool shadow = true; -+ bool shadow = true, lock = false; - int nb_otp = size / sizeof(u32); - int otp; - unsigned int offs = offset; - -- if (offs >= STM32_BSEC_OTP_OFFSET) { -+ if (offs >= STM32_BSEC_LOCK_OFFSET) { -+ offs -= STM32_BSEC_LOCK_OFFSET; -+ lock = true; -+ } else if (offs >= STM32_BSEC_OTP_OFFSET) { - offs -= STM32_BSEC_OTP_OFFSET; - shadow = false; - } - -- if (offs < 0 || (offs % 4) || (size % 4)) -+ if ((offs % 4) || (size % 4)) - return -EINVAL; - - otp = offs / sizeof(u32); -@@ -373,7 +407,9 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, - for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) { - u32 *addr = &((u32 *)buf)[i - otp]; - -- if (shadow) -+ if (lock) -+ ret = stm32mp_bsec_read_lock(dev, addr, i); -+ else if (shadow) - ret = stm32mp_bsec_read_shadow(dev, addr, i); - else - ret = stm32mp_bsec_read_otp(dev, addr, i); -@@ -392,17 +428,20 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, - { - int ret = 0; - int i; -- bool shadow = true; -+ bool shadow = true, lock = false; - int nb_otp = size / sizeof(u32); - int otp; - unsigned int offs = offset; - -- if (offs >= STM32_BSEC_OTP_OFFSET) { -+ if (offs >= STM32_BSEC_LOCK_OFFSET) { -+ offs -= STM32_BSEC_LOCK_OFFSET; -+ lock = true; -+ } else if (offs >= STM32_BSEC_OTP_OFFSET) { - offs -= STM32_BSEC_OTP_OFFSET; - shadow = false; - } - -- if (offs < 0 || (offs % 4) || (size % 4)) -+ if ((offs % 4) || (size % 4)) - return -EINVAL; - - otp = offs / sizeof(u32); -@@ -410,7 +449,9 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, - for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) { - u32 *val = &((u32 *)buf)[i - otp]; - -- if (shadow) -+ if (lock) -+ ret = stm32mp_bsec_write_lock(dev, *val, i); -+ else if (shadow) - ret = stm32mp_bsec_write_shadow(dev, *val, i); - else - ret = stm32mp_bsec_write_otp(dev, *val, i); -@@ -437,7 +478,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) - return 0; - } - --#ifndef CONFIG_STM32MP1_TRUSTED -+#if !defined(CONFIG_STM32MP1_TRUSTED) && !defined(CONFIG_SPL_BUILD) - static int stm32mp_bsec_probe(struct udevice *dev) - { - int otp; -@@ -464,7 +505,27 @@ U_BOOT_DRIVER(stm32mp_bsec) = { - .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), - .ops = &stm32mp_bsec_ops, --#ifndef CONFIG_STM32MP1_TRUSTED -+#if !defined(CONFIG_STM32MP1_TRUSTED) && !defined(CONFIG_SPL_BUILD) - .probe = stm32mp_bsec_probe, - #endif - }; -+ -+bool bsec_dbgswenable(void) -+{ -+ struct udevice *dev; -+ struct stm32mp_bsec_platdata *plat; -+ int ret; -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stm32mp_bsec), &dev); -+ if (ret || !dev) { -+ pr_debug("bsec driver not available\n"); -+ return false; -+ } -+ -+ plat = dev_get_platdata(dev); -+ if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE) -+ return true; -+ -+ return false; -+} -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile -new file mode 100644 -index 0000000..548a378 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile -@@ -0,0 +1,9 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+# -+ -+obj-y += cmd_stm32prog.o -+obj-y += stm32prog.o -+obj-y += stm32prog_serial.o -+obj-y += stm32prog_usb.o -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c -new file mode 100644 -index 0000000..db1f3a7 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "stm32prog.h" -+ -+struct stm32prog_data *stm32prog_data; -+ -+static void enable_vidconsole(void) -+{ -+#ifdef CONFIG_DM_VIDEO -+ char *stdname; -+ char buf[64]; -+ -+ stdname = env_get("stdout"); -+ if (!stdname || !strstr(stdname, "vidconsole")) { -+ if (!stdname) -+ snprintf(buf, sizeof(buf), "serial,vidconsole"); -+ else -+ snprintf(buf, sizeof(buf), "%s,vidconsole", stdname); -+ env_set("stdout", buf); -+ } -+ -+ stdname = env_get("stderr"); -+ if (!stdname || !strstr(stdname, "vidconsole")) { -+ if (!stdname) -+ snprintf(buf, sizeof(buf), "serial,vidconsole"); -+ else -+ snprintf(buf, sizeof(buf), "%s,vidconsole", stdname); -+ env_set("stderr", buf); -+ } -+#endif -+} -+ -+static int do_stm32prog(cmd_tbl_t *cmdtp, int flag, int argc, -+ char * const argv[]) -+{ -+ ulong addr, size; -+ int dev, ret; -+ enum stm32prog_link_t link = LINK_UNDEFINED; -+ bool reset = false; -+ struct image_header_s header; -+ struct stm32prog_data *data; -+ u32 uimage, dtb; -+ -+ if (argc < 3 || argc > 5) -+ return CMD_RET_USAGE; -+ -+ if (!strcmp(argv[1], "usb")) -+ link = LINK_USB; -+ else if (!strcmp(argv[1], "serial")) -+ link = LINK_SERIAL; -+ -+ if (link == LINK_UNDEFINED) { -+ pr_err("not supported link=%s\n", argv[1]); -+ return CMD_RET_USAGE; -+ } -+ -+ dev = (int)simple_strtoul(argv[2], NULL, 10); -+ -+ addr = STM32_DDR_BASE; -+ size = 0; -+ if (argc > 3) { -+ addr = simple_strtoul(argv[3], NULL, 16); -+ if (!addr) -+ return CMD_RET_FAILURE; -+ } -+ if (argc > 4) -+ size = simple_strtoul(argv[4], NULL, 16); -+ -+ /* check STM32IMAGE presence */ -+ if (size == 0 && -+ !stm32prog_header_check((struct raw_header_s *)addr, &header)) { -+ size = header.image_length + BL_HEADER_SIZE; -+ -+ /* uImage detected in STM32IMAGE, execute the script */ -+ if (IMAGE_FORMAT_LEGACY == -+ genimg_get_format((void *)(addr + BL_HEADER_SIZE))) -+ return source(addr + BL_HEADER_SIZE, "script@1"); -+ } -+ -+ enable_vidconsole(); -+ -+ data = (struct stm32prog_data *)malloc(sizeof(*data)); -+ -+ if (!data) { -+ pr_err("Alloc failed."); -+ return CMD_RET_FAILURE; -+ } -+ stm32prog_data = data; -+ -+ ret = stm32prog_init(data, addr, size); -+ if (ret) -+ printf("Invalid or missing layout file."); -+ -+ /* prepare DFU for device read/write */ -+ ret = stm32prog_dfu_init(data); -+ if (ret) -+ goto cleanup; -+ -+ switch (link) { -+ case LINK_SERIAL: -+ ret = stm32prog_serial_init(data, dev); -+ if (ret) -+ goto cleanup; -+ reset = stm32prog_serial_loop(data); -+ break; -+ case LINK_USB: -+ reset = stm32prog_usb_loop(data, dev); -+ break; -+ default: -+ goto cleanup; -+ } -+ -+ uimage = data->uimage; -+ dtb = data->dtb; -+ -+ stm32prog_clean(data); -+ free(stm32prog_data); -+ stm32prog_data = NULL; -+ -+ puts("Download done\n"); -+ -+ if (uimage) { -+ char boot_addr_start[20]; -+ char dtb_addr[20]; -+ char *bootm_argv[5] = { -+ "bootm", boot_addr_start, "-", dtb_addr, NULL -+ }; -+ if (!dtb) -+ bootm_argv[3] = env_get("fdtcontroladdr"); -+ else -+ snprintf(dtb_addr, sizeof(dtb_addr) - 1, -+ "0x%x", dtb); -+ -+ snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, -+ "0x%x", uimage); -+ printf("Booting kernel at %s - %s...\n\n\n", -+ boot_addr_start, bootm_argv[3]); -+ /* Try bootm for legacy and FIT format image */ -+ if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) -+ do_bootm(cmdtp, 0, 4, bootm_argv); -+ else if CONFIG_IS_ENABLED(CMD_BOOTZ) -+ do_bootz(cmdtp, 0, 4, bootm_argv); -+ } -+ -+ if (reset) { -+ puts("Reset...\n"); -+ run_command("reset", 0); -+ } -+ -+ return CMD_RET_SUCCESS; -+ -+cleanup: -+ stm32prog_clean(data); -+ free(stm32prog_data); -+ stm32prog_data = NULL; -+ -+ return CMD_RET_FAILURE; -+} -+ -+U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, -+ " [] []\n" -+ "start communication with tools STM32Cubeprogrammer on with Flashlayout at ", -+ " = serial|usb\n" -+ " = device instance\n" -+ " = address of flashlayout\n" -+ " = size of flashlayout\n" -+); -+ -+bool stm32prog_get_tee_partitions(void) -+{ -+ if (stm32prog_data) -+ return stm32prog_data->tee_detected; -+ -+ return false; -+} -+ -+bool stm32prog_get_fsbl_nor(void) -+{ -+ if (stm32prog_data) -+ return stm32prog_data->fsbl_nor_detected; -+ -+ return false; -+} -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c -new file mode 100644 -index 0000000..f2f9ed9 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c -@@ -0,0 +1,1743 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "stm32prog.h" -+ -+/* Primary GPT header size for 128 entries : 17kB = 34 LBA of 512B */ -+#define GPT_HEADER_SZ 34 -+ -+#define OPT_SELECT BIT(0) -+#define OPT_EMPTY BIT(1) -+#define OPT_DELETE BIT(2) -+ -+#define IS_SELECT(part) ((part)->option & OPT_SELECT) -+#define IS_EMPTY(part) ((part)->option & OPT_EMPTY) -+#define IS_DELETE(part) ((part)->option & OPT_DELETE) -+ -+#define ALT_BUF_LEN SZ_1K -+ -+#define ROOTFS_MMC0_UUID \ -+ EFI_GUID(0xE91C4E10, 0x16E6, 0x4C0E, \ -+ 0xBD, 0x0E, 0x77, 0xBE, 0xCF, 0x4A, 0x35, 0x82) -+ -+#define ROOTFS_MMC1_UUID \ -+ EFI_GUID(0x491F6117, 0x415D, 0x4F53, \ -+ 0x88, 0xC9, 0x6E, 0x0D, 0xE5, 0x4D, 0xEA, 0xC6) -+ -+#define ROOTFS_MMC2_UUID \ -+ EFI_GUID(0xFD58F1C7, 0xBE0D, 0x4338, \ -+ 0x88, 0xE9, 0xAD, 0x8F, 0x05, 0x0A, 0xEB, 0x18) -+ -+/* RAW parttion (binary / bootloader) used Linux - reserved UUID */ -+#define LINUX_RESERVED_UUID "8DA63339-0007-60C0-C436-083AC8230908" -+ -+/* -+ * unique partition guid (uuid) for partition named "rootfs" -+ * on each MMC instance = SD Card or eMMC -+ * allow fixed kernel bootcmd: "rootf=PARTUID=e91c4e10-..." -+ */ -+static const efi_guid_t uuid_mmc[3] = { -+ ROOTFS_MMC0_UUID, -+ ROOTFS_MMC1_UUID, -+ ROOTFS_MMC2_UUID -+}; -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+/* order of column in flash layout file */ -+enum stm32prog_col_t { -+ COL_OPTION, -+ COL_ID, -+ COL_NAME, -+ COL_TYPE, -+ COL_IP, -+ COL_OFFSET, -+ COL_NB_STM32 -+}; -+ -+/* partition handling routines : CONFIG_CMD_MTDPARTS */ -+int mtdparts_init(void); -+int find_dev_and_part(const char *id, struct mtd_device **dev, -+ u8 *part_num, struct part_info **part); -+ -+char *stm32prog_get_error(struct stm32prog_data *data) -+{ -+ static const char error_msg[] = "Unspecified"; -+ -+ if (strlen(data->error) == 0) -+ strcpy(data->error, error_msg); -+ -+ return data->error; -+} -+ -+u8 stm32prog_header_check(struct raw_header_s *raw_header, -+ struct image_header_s *header) -+{ -+ unsigned int i; -+ -+ header->present = 0; -+ header->image_checksum = 0x0; -+ header->image_length = 0x0; -+ -+ if (!raw_header || !header) { -+ pr_debug("%s:no header data\n", __func__); -+ return -1; -+ } -+ if (raw_header->magic_number != -+ (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { -+ pr_debug("%s:invalid magic number : 0x%x\n", -+ __func__, raw_header->magic_number); -+ return -2; -+ } -+ /* only header v1.0 supported */ -+ if (raw_header->header_version != 0x00010000) { -+ pr_debug("%s:invalid header version : 0x%x\n", -+ __func__, raw_header->header_version); -+ return -3; -+ } -+ if (raw_header->reserved1 != 0x0 || raw_header->reserved2) { -+ pr_debug("%s:invalid reserved field\n", __func__); -+ return -4; -+ } -+ for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) { -+ if (raw_header->padding[i] != 0) { -+ pr_debug("%s:invalid padding field\n", __func__); -+ return -5; -+ } -+ } -+ header->present = 1; -+ header->image_checksum = le32_to_cpu(raw_header->image_checksum); -+ header->image_length = le32_to_cpu(raw_header->image_length); -+ -+ return 0; -+} -+ -+static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) -+{ -+ u32 i, checksum; -+ u8 *payload; -+ -+ /* compute checksum on payload */ -+ payload = (u8 *)addr; -+ checksum = 0; -+ for (i = header->image_length; i > 0; i--) -+ checksum += *(payload++); -+ -+ return checksum; -+} -+ -+/* FLASHLAYOUT PARSING *****************************************/ -+static int parse_option(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ char *c = p; -+ -+ part->option = 0; -+ if (!strcmp(p, "-")) -+ return 0; -+ -+ while (*c) { -+ switch (*c) { -+ case 'P': -+ part->option |= OPT_SELECT; -+ break; -+ case 'E': -+ part->option |= OPT_EMPTY; -+ break; -+ case 'D': -+ part->option |= OPT_DELETE; -+ break; -+ default: -+ result = -EINVAL; -+ stm32prog_err("Layout line %d: invalid option '%c' in %s)", -+ i, *c, p); -+ return -EINVAL; -+ } -+ c++; -+ } -+ if (!(part->option & OPT_SELECT)) { -+ stm32prog_err("Layout line %d: missing 'P' in option %s", i, p); -+ return -EINVAL; -+ } -+ -+ return result; -+} -+ -+static int parse_id(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ unsigned long value; -+ -+ result = strict_strtoul(p, 0, &value); -+ part->id = value; -+ if (result || value > PHASE_LAST_USER) { -+ stm32prog_err("Layout line %d: invalid phase value = %s", i, p); -+ result = -EINVAL; -+ } -+ -+ return result; -+} -+ -+static int parse_name(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ -+ if (strlen(p) < sizeof(part->name)) { -+ strcpy(part->name, p); -+ } else { -+ stm32prog_err("Layout line %d: partition name too long [%d]: %s", -+ i, strlen(p), p); -+ result = -EINVAL; -+ } -+ -+ return result; -+} -+ -+static int parse_type(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ int len = 0; -+ -+ part->bin_nb = 0; -+ if (!strncmp(p, "Binary", 6)) { -+ part->part_type = PART_BINARY; -+ -+ /* search for Binary(X) case */ -+ len = strlen(p); -+ part->bin_nb = 1; -+ if (len > 6) { -+ if (len < 8 || -+ (p[6] != '(') || -+ (p[len - 1] != ')')) -+ result = -EINVAL; -+ else -+ part->bin_nb = -+ simple_strtoul(&p[7], NULL, 10); -+ } -+ } else if (!strcmp(p, "System")) { -+ part->part_type = PART_SYSTEM; -+ } else if (!strcmp(p, "FileSystem")) { -+ part->part_type = PART_FILESYSTEM; -+ } else if (!strcmp(p, "RawImage")) { -+ part->part_type = RAW_IMAGE; -+ } else { -+ result = -EINVAL; -+ } -+ if (result) -+ stm32prog_err("Layout line %d: type parsing error : '%s'", -+ i, p); -+ -+ return result; -+} -+ -+static int parse_ip(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ unsigned int len = 0; -+ -+ part->dev_id = 0; -+ if (!strcmp(p, "none")) { -+ part->target = STM32PROG_NONE; -+ } else if (!strncmp(p, "mmc", 3)) { -+ part->target = STM32PROG_MMC; -+ len = 3; -+ } else if (!strncmp(p, "nor", 3)) { -+ part->target = STM32PROG_NOR; -+ len = 3; -+ } else if (!strncmp(p, "nand", 4)) { -+ part->target = STM32PROG_NAND; -+ len = 4; -+ } else if (!strncmp(p, "spi-nand", 8)) { -+ part->target = STM32PROG_SPI_NAND; -+ len = 8; -+ } else if (!strncmp(p, "ram", 3)) { -+ part->target = STM32PROG_RAM; -+ len = 0; -+ } else { -+ result = -EINVAL; -+ } -+ if (len) { -+ /* only one digit allowed for device id */ -+ if (strlen(p) != len + 1) { -+ result = -EINVAL; -+ } else { -+ part->dev_id = p[len] - '0'; -+ if (part->dev_id > 9) -+ result = -EINVAL; -+ } -+ } -+ if (result) -+ stm32prog_err("Layout line %d: ip parsing error: '%s'", i, p); -+ -+ return result; -+} -+ -+static int parse_offset(struct stm32prog_data *data, -+ int i, char *p, struct stm32prog_part_t *part) -+{ -+ int result = 0; -+ char *tail; -+ -+ part->part_id = 0; -+ part->addr = 0; -+ part->size = 0; -+ /* eMMC boot parttion */ -+ if (!strncmp(p, "boot", 4)) { -+ if (strlen(p) != 5) { -+ result = -EINVAL; -+ } else { -+ if (p[4] == '1') -+ part->part_id = -1; -+ else if (p[4] == '2') -+ part->part_id = -2; -+ else -+ result = -EINVAL; -+ } -+ if (result) -+ stm32prog_err("Layout line %d: invalid part '%s'", -+ i, p); -+ } else { -+ part->addr = simple_strtoull(p, &tail, 0); -+ if (tail == p || *tail != '\0') { -+ stm32prog_err("Layout line %d: invalid offset '%s'", -+ i, p); -+ result = -EINVAL; -+ } -+ } -+ -+ return result; -+} -+ -+static -+int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p, -+ struct stm32prog_part_t *part) = { -+ [COL_OPTION] = parse_option, -+ [COL_ID] = parse_id, -+ [COL_NAME] = parse_name, -+ [COL_TYPE] = parse_type, -+ [COL_IP] = parse_ip, -+ [COL_OFFSET] = parse_offset, -+}; -+ -+static int parse_flash_layout(struct stm32prog_data *data, -+ ulong addr, -+ ulong size) -+{ -+ int column = 0, part_nb = 0, ret; -+ bool end_of_line, eof; -+ char *p, *start, *last, *col; -+ struct stm32prog_part_t *part; -+ int part_list_size; -+ int i; -+ -+ data->part_nb = 0; -+ -+ /* check if STM32image is detected */ -+ if (!stm32prog_header_check((struct raw_header_s *)addr, -+ &data->header)) { -+ u32 checksum; -+ -+ addr = addr + BL_HEADER_SIZE; -+ size = data->header.image_length; -+ -+ checksum = stm32prog_header_checksum(addr, &data->header); -+ if (checksum != data->header.image_checksum) { -+ stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x", -+ checksum, data->header.image_checksum); -+ return -EIO; -+ } -+ } -+ if (!size) -+ return -EINVAL; -+ -+ start = (char *)addr; -+ last = start + size; -+ -+ *last = 0x0; /* force null terminated string */ -+ pr_debug("flash layout =\n%s\n", start); -+ -+ /* calculate expected number of partitions */ -+ part_list_size = 1; -+ p = start; -+ while (*p && (p < last)) { -+ if (*p++ == '\n') { -+ part_list_size++; -+ if (p < last && *p == '#') -+ part_list_size--; -+ } -+ } -+ if (part_list_size > PHASE_LAST_USER) { -+ stm32prog_err("Layout: too many partition (%d)", -+ part_list_size); -+ return -1; -+ } -+ part = calloc(sizeof(struct stm32prog_part_t), part_list_size); -+ if (!part) { -+ stm32prog_err("Layout: alloc failed"); -+ return -ENOMEM; -+ } -+ data->part_array = part; -+ -+ /* main parsing loop */ -+ i = 1; -+ eof = false; -+ p = start; -+ col = start; /* 1st column */ -+ end_of_line = false; -+ while (!eof) { -+ switch (*p) { -+ /* CR is ignored and replaced by NULL character */ -+ case '\r': -+ *p = '\0'; -+ p++; -+ continue; -+ case '\0': -+ end_of_line = true; -+ eof = true; -+ break; -+ case '\n': -+ end_of_line = true; -+ break; -+ case '\t': -+ break; -+ case '#': -+ /* comment line is skipped */ -+ if (column == 0 && p == col) { -+ while ((p < last) && *p) -+ if (*p++ == '\n') -+ break; -+ col = p; -+ i++; -+ if (p >= last || !*p) { -+ eof = true; -+ end_of_line = true; -+ } -+ continue; -+ } -+ /* fall through */ -+ /* by default continue with the next character */ -+ default: -+ p++; -+ continue; -+ } -+ -+ /* replace by \0: allow string parsing for each column */ -+ *p = '\0'; -+ p++; -+ if (p >= last) { -+ eof = true; -+ end_of_line = true; -+ } -+ -+ /* skip empty line and multiple TAB in tsv file */ -+ if (strlen(col) == 0) { -+ col = p; -+ /* skip empty line */ -+ if (column == 0 && end_of_line) { -+ end_of_line = false; -+ i++; -+ } -+ continue; -+ } -+ -+ if (column < COL_NB_STM32) { -+ ret = parse[column](data, i, col, part); -+ if (ret) -+ return ret; -+ } -+ -+ /* save the beginning of the next column */ -+ column++; -+ col = p; -+ -+ if (!end_of_line) -+ continue; -+ -+ /* end of the line detected */ -+ end_of_line = false; -+ -+ if (column < COL_NB_STM32) { -+ stm32prog_err("Layout line %d: no enought column", i); -+ return -EINVAL; -+ } -+ column = 0; -+ part_nb++; -+ part++; -+ i++; -+ if (part_nb >= part_list_size) { -+ part = NULL; -+ if (!eof) { -+ stm32prog_err("Layout: no enought memory for %d part", -+ part_nb); -+ return -EINVAL; -+ } -+ } -+ } -+ data->part_nb = part_nb; -+ if (data->part_nb == 0) { -+ stm32prog_err("Layout: no partition found"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static int __init part_cmp(void *priv, struct list_head *a, struct list_head *b) -+{ -+ struct stm32prog_part_t *parta, *partb; -+ -+ parta = container_of(a, struct stm32prog_part_t, list); -+ partb = container_of(b, struct stm32prog_part_t, list); -+ -+ if (parta->part_id != partb->part_id) -+ return parta->part_id - partb->part_id; -+ else -+ return parta->addr > partb->addr ? 1 : -1; -+} -+ -+static void get_mtd_by_target(char *string, enum stm32prog_target target, -+ int dev_id) -+{ -+ const char *dev_str; -+ -+ switch (target) { -+ case STM32PROG_NOR: -+ dev_str = "nor"; -+ break; -+ case STM32PROG_NAND: -+ dev_str = "nand"; -+ break; -+ case STM32PROG_SPI_NAND: -+ dev_str = "spi-nand"; -+ break; -+ default: -+ dev_str = "invalid"; -+ break; -+ } -+ sprintf(string, "%s%d", dev_str, dev_id); -+} -+ -+static int init_device(struct stm32prog_data *data, -+ struct stm32prog_dev_t *dev) -+{ -+ struct mmc *mmc = NULL; -+ struct blk_desc *block_dev = NULL; -+#ifdef CONFIG_MTD -+ struct mtd_info *mtd = NULL; -+ char mtd_id[16]; -+#endif -+ int part_id; -+ int ret; -+ u64 first_addr = 0, last_addr = 0; -+ struct stm32prog_part_t *part, *next_part; -+ u64 part_addr, part_size; -+ bool part_found; -+ const char *part_name; -+ -+ switch (dev->target) { -+#ifdef CONFIG_MMC -+ case STM32PROG_MMC: -+ mmc = find_mmc_device(dev->dev_id); -+ if (mmc_init(mmc)) { -+ stm32prog_err("mmc device %d not found", dev->dev_id); -+ return -ENODEV; -+ } -+ block_dev = mmc_get_blk_desc(mmc); -+ if (!block_dev) { -+ stm32prog_err("mmc device %d not probed", dev->dev_id); -+ return -ENODEV; -+ } -+ dev->erase_size = mmc->erase_grp_size * block_dev->blksz; -+ dev->mmc = mmc; -+ -+ /* reserve a full erase group for each GTP headers */ -+ if (mmc->erase_grp_size > GPT_HEADER_SZ) { -+ first_addr = dev->erase_size; -+ last_addr = (u64)(block_dev->lba - -+ mmc->erase_grp_size) * -+ block_dev->blksz; -+ } else { -+ first_addr = (u64)GPT_HEADER_SZ * block_dev->blksz; -+ last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) * -+ block_dev->blksz; -+ } -+ pr_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id, -+ block_dev->lba, block_dev->blksz); -+ pr_debug(" available address = 0x%llx..0x%llx\n", -+ first_addr, last_addr); -+ pr_debug(" full_update = %d\n", dev->full_update); -+ break; -+#endif -+#ifdef CONFIG_MTD -+ case STM32PROG_NOR: -+ case STM32PROG_NAND: -+ case STM32PROG_SPI_NAND: -+ get_mtd_by_target(mtd_id, dev->target, dev->dev_id); -+ pr_debug("%s\n", mtd_id); -+ -+ mtdparts_init(); -+ mtd = get_mtd_device_nm(mtd_id); -+ if (IS_ERR(mtd)) { -+ stm32prog_err("MTD device %s not found", mtd_id); -+ return -ENODEV; -+ } -+ first_addr = 0; -+ last_addr = mtd->size; -+ dev->erase_size = mtd->erasesize; -+ pr_debug("MTD device %s: size=%lld erasesize=%d\n", -+ mtd_id, mtd->size, mtd->erasesize); -+ pr_debug(" available address = 0x%llx..0x%llx\n", -+ first_addr, last_addr); -+ dev->mtd = mtd; -+ break; -+#endif -+ case STM32PROG_RAM: -+ first_addr = gd->bd->bi_dram[0].start; -+ last_addr = first_addr + gd->bd->bi_dram[0].size; -+ dev->erase_size = 1; -+ break; -+ default: -+ stm32prog_err("unknown device type = %d", dev->target); -+ return -ENODEV; -+ } -+ pr_debug(" erase size = 0x%x\n", dev->erase_size); -+ pr_debug(" full_update = %d\n", dev->full_update); -+ -+ /* order partition list in offset order */ -+ list_sort(NULL, &dev->part_list, &part_cmp); -+ part_id = 1; -+ pr_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n"); -+ list_for_each_entry(part, &dev->part_list, list) { -+ if (part->bin_nb > 1) { -+ if ((dev->target != STM32PROG_NAND && -+ dev->target != STM32PROG_SPI_NAND) || -+ part->id >= PHASE_FIRST_USER || -+ strncmp(part->name, "fsbl", 4)) { -+ stm32prog_err("%s (0x%x): multiple binary %d not supported", -+ part->name, part->id, -+ part->bin_nb); -+ return -EINVAL; -+ } -+ } -+ if (part->part_type == RAW_IMAGE) { -+ part->part_id = 0x0; -+ part->addr = 0x0; -+ if (block_dev) -+ part->size = block_dev->lba * block_dev->blksz; -+ else -+ part->size = last_addr; -+ pr_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n", -+ part->option, part->id, part->name, -+ part->part_type, part->bin_nb, part->target, -+ part->dev_id, part->addr, part->size); -+ continue; -+ } -+ if (part->part_id < 0) { /* boot hw partition for eMMC */ -+ if (mmc) { -+ part->size = mmc->capacity_boot; -+ } else { -+ stm32prog_err("%s (0x%x): hw partition not expected : %d", -+ part->name, part->id, -+ part->part_id); -+ return -ENODEV; -+ } -+ } else { -+ part->part_id = part_id++; -+ -+ /* last partition : size to the end of the device */ -+ if (part->list.next != &dev->part_list) { -+ next_part = -+ container_of(part->list.next, -+ struct stm32prog_part_t, -+ list); -+ if (part->addr < next_part->addr) { -+ part->size = next_part->addr - -+ part->addr; -+ } else { -+ stm32prog_err("%s (0x%x): same address : 0x%llx == %s (0x%x): 0x%llx", -+ part->name, part->id, -+ part->addr, -+ next_part->name, -+ next_part->id, -+ next_part->addr); -+ return -EINVAL; -+ } -+ } else { -+ if (part->addr <= last_addr) { -+ part->size = last_addr - part->addr; -+ } else { -+ stm32prog_err("%s (0x%x): invalid address 0x%llx (max=0x%llx)", -+ part->name, part->id, -+ part->addr, last_addr); -+ return -EINVAL; -+ } -+ } -+ if (part->addr < first_addr) { -+ stm32prog_err("%s (0x%x): invalid address 0x%llx (min=0x%llx)", -+ part->name, part->id, -+ part->addr, first_addr); -+ return -EINVAL; -+ } -+ } -+ if ((part->addr & ((u64)part->dev->erase_size - 1)) != 0) { -+ stm32prog_err("%s (0x%x): not aligned address : 0x%llx on erase size 0x%x", -+ part->name, part->id, part->addr, -+ part->dev->erase_size); -+ return -EINVAL; -+ } -+ pr_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx", -+ part->part_id, part->option, part->id, part->name, -+ part->part_type, part->bin_nb, part->target, -+ part->dev_id, part->addr, part->size); -+ -+ part_addr = 0; -+ part_size = 0; -+ part_found = false; -+ -+ /* check coherency with existing partition */ -+ if (block_dev) { -+ /* -+ * block devices with GPT: check user partition size -+ * only for partial update, the GPT partions are be -+ * created for full update -+ */ -+ if (dev->full_update || part->part_id < 0) { -+ pr_debug("\n"); -+ continue; -+ } -+ disk_partition_t partinfo; -+ -+ ret = part_get_info(block_dev, part->part_id, -+ &partinfo); -+ -+ if (ret) { -+ stm32prog_err("%s (0x%x):Couldn't find part %d on device mmc %d", -+ part->name, part->id, -+ part_id, part->dev_id); -+ return -ENODEV; -+ } -+ part_addr = (u64)partinfo.start * partinfo.blksz; -+ part_size = (u64)partinfo.size * partinfo.blksz; -+ part_name = (char *)partinfo.name; -+ part_found = true; -+ } -+ -+#ifdef CONFIG_MTD -+ if (mtd) { -+ char mtd_part_id[32]; -+ struct part_info *mtd_part; -+ struct mtd_device *mtd_dev; -+ u8 part_num; -+ -+ sprintf(mtd_part_id, "%s,%d", mtd_id, -+ part->part_id - 1); -+ ret = find_dev_and_part(mtd_part_id, &mtd_dev, -+ &part_num, &mtd_part); -+ if (ret != 0) { -+ stm32prog_err("%s (0x%x): Invalid MTD partition %s", -+ part->name, part->id, -+ mtd_part_id); -+ return -ENODEV; -+ } -+ part_addr = mtd_part->offset; -+ part_size = mtd_part->size; -+ part_name = mtd_part->name; -+ part_found = true; -+ } -+#endif -+ -+ /* no partition for this device */ -+ if (!part_found) { -+ pr_debug("\n"); -+ continue; -+ } -+ -+ pr_debug(" %08llx %08llx\n", part_addr, part_size); -+ -+ if (part->addr != part_addr) { -+ stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected", -+ part->name, part->id, part->part_id, -+ part_name, part->addr, part_addr); -+ return -ENODEV; -+ } -+ if (part->size != part_size) { -+ stm32prog_err("%s (0x%x): Bad size for partition %d (%s) at 0x%llx = 0x%llx <> 0x%llx expected", -+ part->name, part->id, part->part_id, -+ part_name, part->addr, part->size, -+ part_size); -+ return -ENODEV; -+ } -+ } -+ return 0; -+} -+ -+static int treat_partition_list(struct stm32prog_data *data) -+{ -+ int i, j; -+ struct stm32prog_part_t *part; -+ -+ for (j = 0; j < STM32PROG_MAX_DEV; j++) { -+ data->dev[j].target = STM32PROG_NONE; -+ INIT_LIST_HEAD(&data->dev[j].part_list); -+ } -+ -+ data->tee_detected = false; -+ data->fsbl_nor_detected = false; -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ part->alt_id = -1; -+ -+ /* skip partition with IP="none" */ -+ if (part->target == STM32PROG_NONE) { -+ if (IS_SELECT(part)) { -+ stm32prog_err("Layout: selected none phase = 0x%x", -+ part->id); -+ return -EINVAL; -+ } -+ continue; -+ } -+ -+ if (part->id == PHASE_FLASHLAYOUT || -+ part->id > PHASE_LAST_USER) { -+ stm32prog_err("Layout: invalid phase = 0x%x", -+ part->id); -+ return -EINVAL; -+ } -+ for (j = i + 1; j < data->part_nb; j++) { -+ if (part->id == data->part_array[j].id) { -+ stm32prog_err("Layout: duplicated phase 0x%x at line %d and %d", -+ part->id, i, j); -+ return -EINVAL; -+ } -+ } -+ for (j = 0; j < STM32PROG_MAX_DEV; j++) { -+ if (data->dev[j].target == STM32PROG_NONE) { -+ /* new device found */ -+ data->dev[j].target = part->target; -+ data->dev[j].dev_id = part->dev_id; -+ data->dev[j].full_update = true; -+ data->dev_nb++; -+ break; -+ } else if ((part->target == data->dev[j].target) && -+ (part->dev_id == data->dev[j].dev_id)) { -+ break; -+ } -+ } -+ if (j == STM32PROG_MAX_DEV) { -+ stm32prog_err("Layout: too many device"); -+ return -EINVAL; -+ } -+ switch (part->target) { -+ case STM32PROG_NOR: -+ if (!data->fsbl_nor_detected && -+ !strncmp(part->name, "fsbl", 4)) -+ data->fsbl_nor_detected = true; -+ /* fallthrough */ -+ case STM32PROG_NAND: -+ case STM32PROG_SPI_NAND: -+ if (!data->tee_detected && -+ !strncmp(part->name, "tee", 3)) -+ data->tee_detected = true; -+ break; -+ default: -+ break; -+ } -+ part->dev = &data->dev[j]; -+ if (!IS_SELECT(part)) -+ part->dev->full_update = false; -+ list_add_tail(&part->list, &data->dev[j].part_list); -+ } -+ -+ return 0; -+} -+ -+static int create_partitions(struct stm32prog_data *data) -+{ -+#ifdef CONFIG_MMC -+ int offset = 0; -+ const int buflen = SZ_8K; -+ char *buf; -+ char uuid[UUID_STR_LEN + 1]; -+ unsigned char *uuid_bin; -+ unsigned int mmc_id; -+ int i; -+ bool rootfs_found; -+ struct stm32prog_part_t *part; -+ -+ buf = malloc(buflen); -+ if (!buf) -+ return -ENOMEM; -+ -+ puts("partitions : "); -+ /* initialize the selected device */ -+ for (i = 0; i < data->dev_nb; i++) { -+ /* create gpt partition support only for full update on MMC */ -+ if (data->dev[i].target != STM32PROG_MMC || -+ !data->dev[i].full_update) -+ continue; -+ -+ offset = 0; -+ rootfs_found = false; -+ memset(buf, 0, buflen); -+ -+ list_for_each_entry(part, &data->dev[i].part_list, list) { -+ /* skip eMMC boot partitions */ -+ if (part->part_id < 0) -+ continue; -+ /* skip Raw Image */ -+ if (part->part_type == RAW_IMAGE) -+ continue; -+ -+ if (offset + 100 > buflen) { -+ pr_debug("\n%s: buffer too small, %s skippped", -+ __func__, part->name); -+ continue; -+ } -+ -+ if (!offset) -+ offset += sprintf(buf, "gpt write mmc %d \"", -+ data->dev[i].dev_id); -+ -+ offset += snprintf(buf + offset, buflen - offset, -+ "name=%s,start=0x%llx,size=0x%llx", -+ part->name, -+ part->addr, -+ part->size); -+ -+ if (part->part_type == PART_BINARY) -+ offset += snprintf(buf + offset, -+ buflen - offset, -+ ",type=" -+ LINUX_RESERVED_UUID); -+ else -+ offset += snprintf(buf + offset, -+ buflen - offset, -+ ",type=linux"); -+ -+ if (part->part_type == PART_SYSTEM) -+ offset += snprintf(buf + offset, -+ buflen - offset, -+ ",bootable"); -+ -+ if (!rootfs_found && !strcmp(part->name, "rootfs")) { -+ mmc_id = part->dev_id; -+ rootfs_found = true; -+ if (mmc_id < ARRAY_SIZE(uuid_mmc)) { -+ uuid_bin = -+ (unsigned char *)uuid_mmc[mmc_id].b; -+ uuid_bin_to_str(uuid_bin, uuid, -+ UUID_STR_FORMAT_GUID); -+ offset += snprintf(buf + offset, -+ buflen - offset, -+ ",uuid=%s", uuid); -+ } -+ } -+ -+ offset += snprintf(buf + offset, buflen - offset, ";"); -+ } -+ -+ if (offset) { -+ offset += snprintf(buf + offset, buflen - offset, "\""); -+ pr_debug("\ncmd: %s\n", buf); -+ if (run_command(buf, 0)) { -+ stm32prog_err("GPT partitionning fail: %s", -+ buf); -+ free(buf); -+ -+ return -1; -+ } -+ } -+ -+ if (data->dev[i].mmc) -+ part_init(mmc_get_blk_desc(data->dev[i].mmc)); -+ -+#ifdef DEBUG -+ sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id); -+ pr_debug("\ncmd: %s", buf); -+ if (run_command(buf, 0)) -+ printf("fail !\n"); -+ else -+ printf("OK\n"); -+ -+ sprintf(buf, "part list mmc %d", data->dev[i].dev_id); -+ run_command(buf, 0); -+#endif -+ } -+ puts("done\n"); -+ -+#ifdef DEBUG -+ run_command("mtd list", 0); -+#endif -+ free(buf); -+#endif -+ -+ return 0; -+} -+ -+static int stm32prog_alt_add(struct stm32prog_data *data, -+ struct dfu_entity *dfu, -+ struct stm32prog_part_t *part) -+{ -+ int ret = 0; -+ int offset = 0; -+ char devstr[10]; -+ char dfustr[10]; -+ char buf[ALT_BUF_LEN]; -+ u32 size; -+ char multiplier, type; -+ -+ /* max 3 digit for sector size */ -+ if (part->size > SZ_1M) { -+ size = (u32)(part->size / SZ_1M); -+ multiplier = 'M'; -+ } else if (part->size > SZ_1K) { -+ size = (u32)(part->size / SZ_1K); -+ multiplier = 'K'; -+ } else { -+ size = (u32)part->size; -+ multiplier = 'B'; -+ } -+ if (IS_SELECT(part) && !IS_EMPTY(part)) -+ type = 'e'; /*Readable and Writeable*/ -+ else -+ type = 'a';/*Readable*/ -+ -+ memset(buf, 0, sizeof(buf)); -+ offset = snprintf(buf, ALT_BUF_LEN - offset, -+ "@%s/0x%02x/1*%d%c%c ", -+ part->name, part->id, -+ size, multiplier, type); -+ -+ if (part->target == STM32PROG_RAM) { -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ "ram 0x%llx 0x%llx", -+ part->addr, part->size); -+ } else if (part->part_type == RAW_IMAGE) { -+ u64 dfu_size; -+ -+ if (part->dev->target == STM32PROG_MMC) -+ dfu_size = part->size / part->dev->mmc->read_bl_len; -+ else -+ dfu_size = part->size; -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ "raw 0x0 0x%llx", dfu_size); -+ } else if (part->part_id < 0) { -+ u64 nb_blk = part->size / part->dev->mmc->read_bl_len; -+ -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ "raw 0x%llx 0x%llx", -+ part->addr, nb_blk); -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ " mmcpart %d;", -(part->part_id)); -+ } else { -+ if (part->part_type == PART_SYSTEM && -+ (part->target == STM32PROG_NAND || -+ part->target == STM32PROG_NOR || -+ part->target == STM32PROG_SPI_NAND)) -+ offset += snprintf(buf + offset, -+ ALT_BUF_LEN - offset, -+ "partubi"); -+ else -+ offset += snprintf(buf + offset, -+ ALT_BUF_LEN - offset, -+ "part"); -+ /* dev_id requested by DFU MMC */ -+ if (part->target == STM32PROG_MMC) -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ " %d", part->dev_id); -+ offset += snprintf(buf + offset, ALT_BUF_LEN - offset, -+ " %d;", part->part_id); -+ } -+ switch (part->target) { -+#ifdef CONFIG_MMC -+ case STM32PROG_MMC: -+ sprintf(dfustr, "mmc"); -+ sprintf(devstr, "%d", part->dev_id); -+ break; -+#endif -+#ifdef CONFIG_MTD -+ case STM32PROG_NAND: -+ case STM32PROG_NOR: -+ case STM32PROG_SPI_NAND: -+ sprintf(dfustr, "mtd"); -+ get_mtd_by_target(devstr, part->target, part->dev_id); -+ break; -+#endif -+ case STM32PROG_RAM: -+ sprintf(dfustr, "ram"); -+ sprintf(devstr, "0"); -+ break; -+ default: -+ stm32prog_err("invalid target: %d", part->target); -+ return -ENODEV; -+ } -+ pr_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf); -+ ret = dfu_alt_add(dfu, dfustr, devstr, buf); -+ pr_debug("dfu_alt_add(%s,%s,%s) result %d\n", -+ dfustr, devstr, buf, ret); -+ -+ return ret; -+} -+ -+static int stm32prog_alt_add_virt(struct dfu_entity *dfu, -+ char *name, int phase, int size) -+{ -+ int ret = 0; -+ char devstr[4]; -+ char buf[ALT_BUF_LEN]; -+ -+ sprintf(devstr, "%d", phase); -+ sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size); -+ ret = dfu_alt_add(dfu, "virt", devstr, buf); -+ pr_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret); -+ -+ return ret; -+} -+ -+static int dfu_init_entities(struct stm32prog_data *data) -+{ -+ int ret = 0; -+ int phase, i, alt_id; -+ struct stm32prog_part_t *part; -+ struct dfu_entity *dfu; -+ int alt_nb; -+ -+ alt_nb = 3; /* number of virtual = CMD, OTP, PMIC*/ -+ if (data->part_nb == 0) -+ alt_nb++; /* +1 for FlashLayout */ -+ else -+ for (i = 0; i < data->part_nb; i++) { -+ if (data->part_array[i].target != STM32PROG_NONE) -+ alt_nb++; -+ } -+ -+ if (dfu_alt_init(alt_nb, &dfu)) -+ return -ENODEV; -+ -+ puts("DFU alt info setting: "); -+ if (data->part_nb) { -+ alt_id = 0; -+ for (phase = 1; -+ (phase <= PHASE_LAST_USER) && -+ (alt_id < alt_nb) && !ret; -+ phase++) { -+ /* ordering alt setting by phase id */ -+ part = NULL; -+ for (i = 0; i < data->part_nb; i++) { -+ if (phase == data->part_array[i].id) { -+ part = &data->part_array[i]; -+ break; -+ } -+ } -+ if (!part) -+ continue; -+ if (part->target == STM32PROG_NONE) -+ continue; -+ part->alt_id = alt_id; -+ alt_id++; -+ -+ ret = stm32prog_alt_add(data, dfu, part); -+ } -+ } else { -+ char buf[ALT_BUF_LEN]; -+ -+ sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000", -+ PHASE_FLASHLAYOUT, STM32_DDR_BASE); -+ ret = dfu_alt_add(dfu, "ram", NULL, buf); -+ pr_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret); -+ } -+ -+ if (!ret) -+ ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, 512); -+ -+ if (!ret) -+ ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, 512); -+ -+ if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) -+ ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, 8); -+ -+ if (ret) -+ stm32prog_err("dfu init failed: %d", ret); -+ puts("done\n"); -+ -+#ifdef DEBUG -+ dfu_show_entities(); -+#endif -+ return ret; -+} -+ -+int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, -+ long *size) -+{ -+ pr_debug("%s: %x %lx\n", __func__, offset, *size); -+ -+ if (!data->otp_part) { -+ data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE); -+ if (!data->otp_part) -+ return -ENOMEM; -+ } -+ -+ if (!offset) -+ memset(data->otp_part, 0, OTP_SIZE); -+ -+ if (offset + *size > OTP_SIZE) -+ *size = OTP_SIZE - offset; -+ -+ memcpy((void *)((u32)data->otp_part + offset), buffer, *size); -+ -+ return 0; -+} -+ -+int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, -+ long *size) -+{ -+#ifndef CONFIG_ARM_SMCCC -+ stm32prog_err("OTP update not supported"); -+ -+ return -1; -+#else -+ int result = 0; -+ -+ pr_debug("%s: %x %lx\n", __func__, offset, *size); -+ /* alway read for first packet */ -+ if (!offset) { -+ if (!data->otp_part) -+ data->otp_part = -+ memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE); -+ -+ if (!data->otp_part) { -+ result = -ENOMEM; -+ goto end_otp_read; -+ } -+ -+ /* init struct with 0 */ -+ memset(data->otp_part, 0, OTP_SIZE); -+ -+ /* call the service */ -+ result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, -+ (u32)data->otp_part, 0); -+ if (result) -+ goto end_otp_read; -+ } -+ -+ if (!data->otp_part) { -+ result = -ENOMEM; -+ goto end_otp_read; -+ } -+ -+ if (offset + *size > OTP_SIZE) -+ *size = OTP_SIZE - offset; -+ memcpy(buffer, (void *)((u32)data->otp_part + offset), *size); -+ -+end_otp_read: -+ pr_debug("%s: result %i\n", __func__, result); -+ -+ return result; -+#endif -+} -+ -+int stm32prog_otp_start(struct stm32prog_data *data) -+{ -+#ifndef CONFIG_ARM_SMCCC -+ stm32prog_err("OTP update not supported"); -+ -+ return -1; -+#else -+ int result = 0; -+ struct arm_smccc_res res; -+ -+ if (!data->otp_part) { -+ stm32prog_err("start OTP without data"); -+ return -1; -+ } -+ -+ arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, -+ (u32)data->otp_part, 0, 0, 0, 0, 0, &res); -+ -+ if (!res.a0) { -+ switch (res.a1) { -+ case 0: -+ result = 0; -+ break; -+ case 1: -+ stm32prog_err("Provisioning"); -+ result = 0; -+ break; -+ default: -+ pr_err("%s: OTP incorrect value (err = %ld)\n", -+ __func__, res.a1); -+ result = -EINVAL; -+ break; -+ } -+ } else { -+ pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", -+ __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0); -+ result = -EINVAL; -+ } -+ -+ free(data->otp_part); -+ data->otp_part = NULL; -+ pr_debug("%s: result %i\n", __func__, result); -+ -+ return result; -+#endif -+} -+ -+int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer, -+ long *size) -+{ -+ pr_debug("%s: %x %lx\n", __func__, offset, *size); -+ -+ if (!offset) -+ memset(data->pmic_part, 0, PMIC_SIZE); -+ -+ if (offset + *size > PMIC_SIZE) -+ *size = PMIC_SIZE - offset; -+ -+ memcpy(&data->pmic_part[offset], buffer, *size); -+ -+ return 0; -+} -+ -+int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer, -+ long *size) -+{ -+ int result = 0, ret; -+ struct udevice *dev; -+ -+ if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) { -+ stm32prog_err("PMIC update not supported"); -+ -+ return -EOPNOTSUPP; -+ } -+ -+ pr_debug("%s: %x %lx\n", __func__, offset, *size); -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stpmic1_nvm), -+ &dev); -+ if (ret) -+ return ret; -+ -+ /* alway request PMIC for first packet */ -+ if (!offset) { -+ /* init struct with 0 */ -+ memset(data->pmic_part, 0, PMIC_SIZE); -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stpmic1_nvm), -+ &dev); -+ if (ret) -+ return ret; -+ -+ ret = misc_read(dev, 0xF8, data->pmic_part, PMIC_SIZE); -+ if (ret < 0) { -+ result = ret; -+ goto end_pmic_read; -+ } -+ if (ret != PMIC_SIZE) { -+ result = -EACCES; -+ goto end_pmic_read; -+ } -+ } -+ -+ if (offset + *size > PMIC_SIZE) -+ *size = PMIC_SIZE - offset; -+ -+ memcpy(buffer, &data->pmic_part[offset], *size); -+ -+end_pmic_read: -+ pr_debug("%s: result %i\n", __func__, result); -+ return result; -+} -+ -+int stm32prog_pmic_start(struct stm32prog_data *data) -+{ -+ int ret; -+ struct udevice *dev; -+ -+ if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) { -+ stm32prog_err("PMIC update not supported"); -+ -+ return -EOPNOTSUPP; -+ } -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stpmic1_nvm), -+ &dev); -+ if (ret) -+ return ret; -+ -+ return misc_write(dev, 0xF8, data->pmic_part, PMIC_SIZE); -+} -+ -+/* copy FSBL on NAND to improve reliability on NAND */ -+static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) -+{ -+ int ret, i; -+ void *fsbl; -+ struct image_header_s header; -+ struct raw_header_s raw_header; -+ struct dfu_entity *dfu; -+ long size, offset; -+ -+ if (part->target != STM32PROG_NAND && -+ part->target != STM32PROG_SPI_NAND) -+ return -1; -+ -+ dfu = dfu_get_entity(part->alt_id); -+ -+ /* read header */ -+ dfu_transaction_cleanup(dfu); -+ size = BL_HEADER_SIZE; -+ ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); -+ if (ret) -+ return ret; -+ if (stm32prog_header_check(&raw_header, &header)) -+ return -1; -+ -+ /* read header + payload */ -+ size = header.image_length + BL_HEADER_SIZE; -+ size = round_up(size, part->dev->mtd->erasesize); -+ fsbl = calloc(1, size); -+ if (!fsbl) -+ return -ENOMEM; -+ ret = dfu->read_medium(dfu, 0, fsbl, &size); -+ pr_debug("%s read size=%lx ret=%d\n", __func__, size, ret); -+ if (ret) -+ goto error; -+ -+ dfu_transaction_cleanup(dfu); -+ offset = 0; -+ for (i = part->bin_nb - 1; i > 0; i--) { -+ offset += size; -+ /* write to the next erase block */ -+ ret = dfu->write_medium(dfu, offset, fsbl, &size); -+ pr_debug("%s copy at ofset=%lx size=%lx ret=%d", -+ __func__, offset, size, ret); -+ if (ret) -+ goto error; -+ } -+ -+error: -+ free(fsbl); -+ return ret; -+} -+ -+static void stm32prog_end_phase(struct stm32prog_data *data) -+{ -+ if (data->phase == PHASE_FLASHLAYOUT) { -+ if (parse_flash_layout(data, STM32_DDR_BASE, 0)) -+ stm32prog_err("Layout: invalid FlashLayout"); -+ return; -+ } -+ -+ if (!data->cur_part) -+ return; -+ -+ if (data->cur_part->target == STM32PROG_RAM) { -+ if (data->cur_part->part_type == PART_SYSTEM) -+ data->uimage = data->cur_part->addr; -+ if (data->cur_part->part_type == PART_FILESYSTEM) -+ data->dtb = data->cur_part->addr; -+ } -+ -+ if (CONFIG_IS_ENABLED(MMC) && -+ data->cur_part->part_id < 0) { -+ char cmdbuf[60]; -+ -+ sprintf(cmdbuf, "mmc bootbus %d 0 0 0; mmc partconf %d 1 %d 0", -+ data->cur_part->dev_id, data->cur_part->dev_id, -+ -(data->cur_part->part_id)); -+ if (run_command(cmdbuf, 0)) { -+ stm32prog_err("commands '%s' failed", cmdbuf); -+ return; -+ } -+ } -+ -+ if (CONFIG_IS_ENABLED(MTD) && -+ data->cur_part->bin_nb > 1) { -+ if (stm32prog_copy_fsbl(data->cur_part)) { -+ stm32prog_err("%s (0x%x): copy of fsbl failed", -+ data->cur_part->name, data->cur_part->id); -+ return; -+ } -+ } -+} -+ -+void stm32prog_do_reset(struct stm32prog_data *data) -+{ -+ if (data->phase == PHASE_RESET) { -+ data->phase = PHASE_DO_RESET; -+ puts("Reset requested\n"); -+ } -+} -+ -+void stm32prog_next_phase(struct stm32prog_data *data) -+{ -+ int phase, i; -+ struct stm32prog_part_t *part; -+ bool found; -+ -+ phase = data->phase; -+ switch (phase) { -+ case PHASE_RESET: -+ case PHASE_END: -+ case PHASE_DO_RESET: -+ return; -+ } -+ -+ /* found next selected partition */ -+ data->dfu_seq = 0; -+ data->cur_part = NULL; -+ data->phase = PHASE_END; -+ found = false; -+ do { -+ phase++; -+ if (phase > PHASE_LAST_USER) -+ break; -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ if (part->id == phase) { -+ if (IS_SELECT(part) && !IS_EMPTY(part)) { -+ data->cur_part = part; -+ data->phase = phase; -+ found = true; -+ } -+ break; -+ } -+ } -+ } while (!found); -+ -+ if (data->phase == PHASE_END) -+ puts("Phase=END\n"); -+} -+ -+static int part_delete(struct stm32prog_data *data, -+ struct stm32prog_part_t *part) -+{ -+ int ret = 0; -+#ifdef CONFIG_MMC -+ unsigned long blks, blks_offset, blks_size; -+ struct blk_desc *block_dev = NULL; -+ #endif -+#ifdef CONFIG_MTD -+ char cmdbuf[40]; -+ char devstr[10]; -+#endif -+ -+ printf("Erasing %s ", part->name); -+ switch (part->target) { -+#ifdef CONFIG_MMC -+ case STM32PROG_MMC: -+ printf("on mmc %d: ", part->dev->dev_id); -+ block_dev = mmc_get_blk_desc(part->dev->mmc); -+ blks_offset = lldiv(part->addr, part->dev->mmc->read_bl_len); -+ blks_size = lldiv(part->size, part->dev->mmc->read_bl_len); -+ /* -1 or -2 : delete boot partition of MMC -+ * need to switch to associated hwpart 1 or 2 -+ */ -+ if (part->part_id < 0) -+ if (blk_select_hwpart_devnum(IF_TYPE_MMC, -+ part->dev->dev_id, -+ -part->part_id)) -+ return -1; -+ blks = blk_derase(block_dev, blks_offset, blks_size); -+ /* return to user partition */ -+ if (part->part_id < 0) -+ blk_select_hwpart_devnum(IF_TYPE_MMC, -+ part->dev->dev_id, 0); -+ if (blks != blks_size) { -+ ret = -1; -+ stm32prog_err("%s (0x%x): MMC erase failed", -+ part->name, part->id); -+ } -+ break; -+#endif -+#ifdef CONFIG_MTD -+ case STM32PROG_NOR: -+ case STM32PROG_NAND: -+ case STM32PROG_SPI_NAND: -+ get_mtd_by_target(devstr, part->target, part->dev->dev_id); -+ printf("on %s: ", devstr); -+ sprintf(cmdbuf, "mtd erase %s 0x%llx 0x%llx", -+ devstr, part->addr, part->size); -+ if (run_command(cmdbuf, 0)) { -+ ret = -1; -+ stm32prog_err("%s (0x%x): MTD erase commands failed (%s)", -+ part->name, part->id, cmdbuf); -+ } -+ break; -+#endif -+ case STM32PROG_RAM: -+ printf("on ram: "); -+ memset((void *)(uintptr_t)part->addr, 0, (size_t)part->size); -+ break; -+ default: -+ ret = -1; -+ stm32prog_err("%s (0x%x): erase invalid", part->name, part->id); -+ break; -+ } -+ if (!ret) -+ printf("done\n"); -+ -+ return ret; -+} -+ -+static void stm32prog_devices_init(struct stm32prog_data *data) -+{ -+ int i; -+ int ret; -+ struct stm32prog_part_t *part; -+ -+ ret = treat_partition_list(data); -+ if (ret) -+ goto error; -+ -+ /* initialize the selected device */ -+ for (i = 0; i < data->dev_nb; i++) { -+ ret = init_device(data, &data->dev[i]); -+ if (ret) -+ goto error; -+ } -+ -+ /* delete RAW partition before create partition */ -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ -+ if (part->part_type != RAW_IMAGE) -+ continue; -+ -+ if (!IS_SELECT(part) || !IS_DELETE(part)) -+ continue; -+ -+ ret = part_delete(data, part); -+ if (ret) -+ goto error; -+ } -+ -+ ret = create_partitions(data); -+ if (ret) -+ goto error; -+ -+ /* delete partition GPT or MTD */ -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ -+ if (part->part_type == RAW_IMAGE) -+ continue; -+ -+ if (!IS_SELECT(part) || !IS_DELETE(part)) -+ continue; -+ -+ ret = part_delete(data, part); -+ if (ret) -+ goto error; -+ } -+ -+ return; -+ -+error: -+ data->part_nb = 0; -+} -+ -+int stm32prog_dfu_init(struct stm32prog_data *data) -+{ -+ /* init device if no error */ -+ if (data->part_nb) -+ stm32prog_devices_init(data); -+ -+ if (data->part_nb) -+ stm32prog_next_phase(data); -+ -+ /* prepare DFU for device read/write */ -+ dfu_free_entities(); -+ return dfu_init_entities(data); -+} -+ -+int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size) -+{ -+ memset(data, 0x0, sizeof(*data)); -+ data->read_phase = PHASE_RESET; -+ data->phase = PHASE_FLASHLAYOUT; -+ -+ return parse_flash_layout(data, addr, size); -+} -+ -+void stm32prog_clean(struct stm32prog_data *data) -+{ -+ /* clean */ -+ dfu_free_entities(); -+ free(data->part_array); -+ free(data->otp_part); -+ free(data->buffer); -+ free(data->header_data); -+} -+ -+/* DFU callback: used after serial and direct DFU USB access */ -+void dfu_flush_callback(struct dfu_entity *dfu) -+{ -+ if (!stm32prog_data) -+ return; -+ -+ if (dfu->dev_type == DFU_DEV_VIRT) { -+ if (dfu->data.virt.dev_num == PHASE_OTP) -+ stm32prog_otp_start(stm32prog_data); -+ else if (dfu->data.virt.dev_num == PHASE_PMIC) -+ stm32prog_pmic_start(stm32prog_data); -+ return; -+ } -+ -+ if (dfu->dev_type == DFU_DEV_RAM) { -+ if (dfu->alt == 0 && -+ stm32prog_data->phase == PHASE_FLASHLAYOUT) { -+ stm32prog_end_phase(stm32prog_data); -+ /* waiting DFU DETACH for reenumeration */ -+ } -+ } -+ -+ if (!stm32prog_data->cur_part) -+ return; -+ -+ if (dfu->alt == stm32prog_data->cur_part->alt_id) { -+ stm32prog_end_phase(stm32prog_data); -+ stm32prog_next_phase(stm32prog_data); -+ } -+} -+ -+void dfu_initiated_callback(struct dfu_entity *dfu) -+{ -+ if (!stm32prog_data) -+ return; -+ -+ if (!stm32prog_data->cur_part) -+ return; -+ -+ /* force the saved offset for the current partition */ -+ if (dfu->alt == stm32prog_data->cur_part->alt_id) { -+ dfu->offset = stm32prog_data->offset; -+ stm32prog_data->dfu_seq = 0; -+ pr_debug("dfu offset = 0x%llx\n", dfu->offset); -+ } -+} -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h -new file mode 100644 -index 0000000..bae4e91 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h -@@ -0,0 +1,185 @@ -+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#ifndef _STM32PROG_H_ -+#define _STM32PROG_H_ -+ -+/* - phase defines ------------------------------------------------*/ -+#define PHASE_FLASHLAYOUT 0x00 -+#define PHASE_FIRST_USER 0x10 -+#define PHASE_LAST_USER 0xF0 -+#define PHASE_CMD 0xF1 -+#define PHASE_OTP 0xF2 -+#define PHASE_PMIC 0xF4 -+#define PHASE_END 0xFE -+#define PHASE_RESET 0xFF -+#define PHASE_DO_RESET 0x1FF -+ -+#define DEFAULT_ADDRESS 0xFFFFFFFF -+ -+#define OTP_SIZE 1024 -+#define PMIC_SIZE 8 -+ -+enum stm32prog_target { -+ STM32PROG_NONE, -+ STM32PROG_MMC, -+ STM32PROG_NAND, -+ STM32PROG_NOR, -+ STM32PROG_SPI_NAND, -+ STM32PROG_RAM -+}; -+ -+enum stm32prog_link_t { -+ LINK_SERIAL, -+ LINK_USB, -+ LINK_UNDEFINED, -+}; -+ -+struct image_header_s { -+ bool present; -+ u32 image_checksum; -+ u32 image_length; -+}; -+ -+struct raw_header_s { -+ u32 magic_number; -+ u32 image_signature[64 / 4]; -+ u32 image_checksum; -+ u32 header_version; -+ u32 image_length; -+ u32 image_entry_point; -+ u32 reserved1; -+ u32 load_address; -+ u32 reserved2; -+ u32 version_number; -+ u32 option_flags; -+ u32 ecdsa_algorithm; -+ u32 ecdsa_public_key[64 / 4]; -+ u32 padding[83 / 4]; -+ u32 binary_type; -+}; -+ -+#define BL_HEADER_SIZE sizeof(struct raw_header_s) -+ -+/* partition type in flashlayout file */ -+enum stm32prog_part_type { -+ PART_BINARY, -+ PART_SYSTEM, -+ PART_FILESYSTEM, -+ RAW_IMAGE -+}; -+ -+/* device information */ -+struct stm32prog_dev_t { -+ enum stm32prog_target target; -+ char dev_id; -+ u32 erase_size; -+ struct mmc *mmc; -+ struct mtd_info *mtd; -+ /* list of partition for this device / ordered in offset */ -+ struct list_head part_list; -+ bool full_update; -+}; -+ -+/* partition information build from FlashLayout and device */ -+struct stm32prog_part_t { -+ /* FlashLayout information */ -+ int option; -+ int id; -+ enum stm32prog_part_type part_type; -+ enum stm32prog_target target; -+ char dev_id; -+ -+ /* partition name -+ * (16 char in gpt, + 1 for null terminated string -+ */ -+ char name[16 + 1]; -+ u64 addr; -+ u64 size; -+ enum stm32prog_part_type bin_nb; /* SSBL repeatition */ -+ -+ /* information on associated device */ -+ struct stm32prog_dev_t *dev; /* pointer to device */ -+ s16 part_id; /* partition id in device */ -+ int alt_id; /* alt id in usb/dfu */ -+ -+ struct list_head list; -+}; -+ -+#define STM32PROG_MAX_DEV 5 -+struct stm32prog_data { -+ /* Layout information */ -+ int dev_nb; /* device number*/ -+ struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */ -+ int part_nb; /* nb of partition */ -+ struct stm32prog_part_t *part_array; /* array of partition */ -+ bool tee_detected; -+ bool fsbl_nor_detected; -+ -+ /* command internal information */ -+ unsigned int phase; -+ u32 offset; -+ char error[255]; -+ struct stm32prog_part_t *cur_part; -+ u32 *otp_part; -+ u8 pmic_part[PMIC_SIZE]; -+ -+ /* STM32 header information */ -+ struct raw_header_s *header_data; -+ struct image_header_s header; -+ -+ /* SERIAL information */ -+ u32 cursor; -+ u32 packet_number; -+ u32 checksum; -+ u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/ -+ int dfu_seq; -+ u8 read_phase; -+ -+ /* bootm information */ -+ u32 uimage; -+ u32 dtb; -+}; -+ -+extern struct stm32prog_data *stm32prog_data; -+ -+/* OTP access */ -+int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, -+ u8 *buffer, long *size); -+int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, -+ u8 *buffer, long *size); -+int stm32prog_otp_start(struct stm32prog_data *data); -+ -+/* PMIC access */ -+int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, -+ u8 *buffer, long *size); -+int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, -+ u8 *buffer, long *size); -+int stm32prog_pmic_start(struct stm32prog_data *data); -+ -+/* generic part*/ -+u8 stm32prog_header_check(struct raw_header_s *raw_header, -+ struct image_header_s *header); -+int stm32prog_dfu_init(struct stm32prog_data *data); -+void stm32prog_next_phase(struct stm32prog_data *data); -+void stm32prog_do_reset(struct stm32prog_data *data); -+ -+char *stm32prog_get_error(struct stm32prog_data *data); -+ -+#define stm32prog_err(args...) {\ -+ if (data->phase != PHASE_RESET) { \ -+ sprintf(data->error, args); \ -+ data->phase = PHASE_RESET; \ -+ pr_err("Error: %s\n", data->error); } \ -+ } -+ -+/* Main function */ -+int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size); -+int stm32prog_serial_init(struct stm32prog_data *data, int link_dev); -+bool stm32prog_serial_loop(struct stm32prog_data *data); -+bool stm32prog_usb_loop(struct stm32prog_data *data, int dev); -+void stm32prog_clean(struct stm32prog_data *data); -+ -+#endif -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c -new file mode 100644 -index 0000000..5a16979 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c -@@ -0,0 +1,993 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "stm32prog.h" -+ -+/* - configuration part -----------------------------*/ -+#define USART_BL_VERSION 0x40 /* USART bootloader version V4.0*/ -+#define UBOOT_BL_VERSION 0x03 /* bootloader version V0.3*/ -+#define DEVICE_ID_BYTE1 0x05 /* MSB byte of device ID*/ -+#define DEVICE_ID_BYTE2 0x00 /* LSB byte of device ID*/ -+#define USART_RAM_BUFFER_SIZE 256 /* Size of USART_RAM_Buf buffer*/ -+ -+/* - Commands -----------------------------*/ -+#define GET_CMD_COMMAND 0x00 /* Get CMD command*/ -+#define GET_VER_COMMAND 0x01 /* Get Version command*/ -+#define GET_ID_COMMAND 0x02 /* Get ID command*/ -+#define GET_PHASE_COMMAND 0x03 /* Get Phase command*/ -+#define RM_COMMAND 0x11 /* Read Memory command*/ -+#define READ_PART_COMMAND 0x12 /* Read Partition command*/ -+#define START_COMMAND 0x21 /* START command (Go)*/ -+#define DOWNLOAD_COMMAND 0x31 /* Download command*/ -+/* existing command for other STM32 but not used */ -+/* ERASE 0x43 */ -+/* EXTENDED_ERASE 0x44 */ -+/* WRITE_UNPROTECTED 0x73 */ -+/* READOUT_PROTECT 0x82 */ -+/* READOUT_UNPROTECT 0x92 */ -+ -+/* - miscellaneous defines ----------------------------------------*/ -+#define INIT_BYTE 0x7F /*Init Byte ID*/ -+#define ACK_BYTE 0x79 /*Acknowlede Byte ID*/ -+#define NACK_BYTE 0x1F /*No Acknowlede Byte ID*/ -+#define ABORT_BYTE 0x5F /*ABORT*/ -+ -+struct udevice *down_serial_dev; -+ -+const u8 cmd_id[] = { -+ GET_CMD_COMMAND, -+ GET_VER_COMMAND, -+ GET_ID_COMMAND, -+ GET_PHASE_COMMAND, -+ RM_COMMAND, -+ READ_PART_COMMAND, -+ START_COMMAND, -+ DOWNLOAD_COMMAND -+}; -+ -+#define NB_CMD sizeof(cmd_id) -+ -+/* DFU support for serial *********************************************/ -+static struct dfu_entity *stm32prog_get_entity(struct stm32prog_data *data) -+{ -+ int alt_id; -+ -+ if (!data->cur_part) -+ if (data->phase == PHASE_FLASHLAYOUT) -+ alt_id = 0; -+ else -+ return NULL; -+ else -+ alt_id = data->cur_part->alt_id; -+ -+ return dfu_get_entity(alt_id); -+} -+ -+static int stm32prog_write(struct stm32prog_data *data, u8 *buffer, -+ u32 buffer_size) -+{ -+ struct dfu_entity *dfu_entity; -+ u8 ret = 0; -+ -+ dfu_entity = stm32prog_get_entity(data); -+ if (!dfu_entity) -+ return -ENODEV; -+ -+ ret = dfu_write(dfu_entity, -+ buffer, -+ buffer_size, -+ data->dfu_seq); -+ -+ if (ret) { -+ stm32prog_err("DFU write failed [%d] cnt: %d", -+ ret, data->dfu_seq); -+ } -+ data->dfu_seq++; -+ /* handle rollover as in driver/dfu/dfu.c */ -+ data->dfu_seq &= 0xffff; -+ if (buffer_size == 0) -+ data->dfu_seq = 0; /* flush done */ -+ -+ return ret; -+} -+ -+static int stm32prog_read(struct stm32prog_data *data, u8 phase, u32 offset, -+ u8 *buffer, u32 buffer_size) -+{ -+ struct dfu_entity *dfu_entity; -+ struct stm32prog_part_t *part; -+ u32 size; -+ int ret, i; -+ -+ if (data->dfu_seq) { -+ stm32prog_err("DFU write pending for phase %d, seq %d", -+ data->phase, data->dfu_seq); -+ return -EINVAL; -+ } -+ if (phase == PHASE_FLASHLAYOUT || phase > PHASE_LAST_USER) { -+ stm32prog_err("read failed : phase %d is invalid", phase); -+ return -EINVAL; -+ } -+ if (data->read_phase <= PHASE_LAST_USER && -+ phase != data->read_phase) { -+ /* clear previous read session */ -+ dfu_entity = dfu_get_entity(data->read_phase - 1); -+ if (dfu_entity) -+ dfu_transaction_cleanup(dfu_entity); -+ } -+ -+ dfu_entity = NULL; -+ /* found partition for the expected phase */ -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ if (part->id == phase) -+ dfu_entity = dfu_get_entity(part->alt_id); -+ } -+ if (!dfu_entity) { -+ stm32prog_err("read failed : phase %d is unknown", phase); -+ return -ENODEV; -+ } -+ -+ /* clear pending read before to force offset */ -+ if (dfu_entity->inited && -+ (data->read_phase != phase || data->offset != offset)) -+ dfu_transaction_cleanup(dfu_entity); -+ -+ /* initiate before to force offset */ -+ if (!dfu_entity->inited) { -+ ret = dfu_transaction_initiate(dfu_entity, true); -+ if (ret < 0) { -+ stm32prog_err("DFU read init failed [%d] phase = %d offset = 0x%08x", -+ ret, phase, offset); -+ return ret; -+ } -+ } -+ /* force new offset */ -+ if (dfu_entity->offset != offset) -+ dfu_entity->offset = offset; -+ data->offset = offset; -+ data->read_phase = phase; -+ pr_debug("\nSTM32 download read %s offset=0x%x\n", -+ dfu_entity->name, offset); -+ ret = dfu_read(dfu_entity, buffer, buffer_size, -+ dfu_entity->i_blk_seq_num); -+ if (ret < 0) { -+ stm32prog_err("DFU read failed [%d] phase = %d offset = 0x%08x", -+ ret, phase, offset); -+ return ret; -+ } -+ -+ size = ret; -+ -+ if (size < buffer_size) { -+ data->offset = 0; -+ data->read_phase = PHASE_END; -+ memset(buffer + size, 0, buffer_size - size); -+ } else { -+ data->offset += size; -+ } -+ -+ return ret; -+} -+ -+/* UART access ***************************************************/ -+int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) -+{ -+ struct udevice *dev = NULL; -+ int node; -+ char alias[10]; -+ const char *path; -+ struct dm_serial_ops *ops; -+ /* no parity, 8 bits, 1 stop */ -+ u32 serial_config = SERIAL_DEFAULT_CONFIG; -+ -+ down_serial_dev = NULL; -+ -+ sprintf(alias, "serial%d", link_dev); -+ path = fdt_get_alias(gd->fdt_blob, alias); -+ if (!path) { -+ pr_err("%s alias not found", alias); -+ return -ENODEV; -+ } -+ node = fdt_path_offset(gd->fdt_blob, path); -+ if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, -+ &dev)) { -+ down_serial_dev = dev; -+ } else if (node > 0 && -+ !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node), -+ &dev, false)) { -+ if (!device_probe(dev)) -+ down_serial_dev = dev; -+ } -+ if (!down_serial_dev) { -+ pr_err("%s = %s device not found", alias, path); -+ return -ENODEV; -+ } -+ -+ /* force silent console on uart only when used */ -+ if (gd->cur_serial_dev == down_serial_dev) -+ gd->flags |= GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT; -+ else -+ gd->flags &= ~(GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT); -+ -+ ops = serial_get_ops(down_serial_dev); -+ -+ if (!ops) { -+ pr_err("%s = %s missing ops", alias, path); -+ return -ENODEV; -+ } -+ if (!ops->setconfig) { -+ pr_err("%s = %s missing setconfig", alias, path); -+ return -ENODEV; -+ } -+ -+ clrsetbits_le32(&serial_config, SERIAL_PAR_MASK, SERIAL_PAR_EVEN); -+ -+ data->buffer = memalign(CONFIG_SYS_CACHELINE_SIZE, -+ USART_RAM_BUFFER_SIZE); -+ -+ return ops->setconfig(down_serial_dev, serial_config); -+} -+ -+static void stm32prog_serial_flush(void) -+{ -+ struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); -+ int err; -+ -+ do { -+ err = ops->getc(down_serial_dev); -+ } while (err != -EAGAIN); -+} -+ -+static int stm32prog_serial_getc_err(void) -+{ -+ struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); -+ int err; -+ -+ do { -+ err = ops->getc(down_serial_dev); -+ if (err == -EAGAIN) { -+ ctrlc(); -+ WATCHDOG_RESET(); -+ } -+ } while ((err == -EAGAIN) && (!had_ctrlc())); -+ -+ return err; -+} -+ -+static u8 stm32prog_serial_getc(void) -+{ -+ int err; -+ -+ err = stm32prog_serial_getc_err(); -+ -+ return err >= 0 ? err : 0; -+} -+ -+static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count) -+{ -+ struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); -+ int err; -+ -+ do { -+ err = ops->getc(down_serial_dev); -+ if (err >= 0) { -+ *buffer++ = err; -+ *count -= 1; -+ } else if (err == -EAGAIN) { -+ ctrlc(); -+ WATCHDOG_RESET(); -+ } else { -+ break; -+ } -+ } while (*count && !had_ctrlc()); -+ -+ return !!(err < 0); -+} -+ -+static void stm32prog_serial_putc(u8 w_byte) -+{ -+ struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); -+ int err; -+ -+ do { -+ err = ops->putc(down_serial_dev, w_byte); -+ } while (err == -EAGAIN); -+} -+ -+/* Helper function ************************************************/ -+ -+static u8 stm32prog_header(struct stm32prog_data *data) -+{ -+ u8 ret; -+ u8 boot = 0; -+ struct dfu_entity *dfu_entity; -+ u64 size = 0; -+ -+ dfu_entity = stm32prog_get_entity(data); -+ if (!dfu_entity) -+ return -ENODEV; -+ -+ printf("\nSTM32 download write %s\n", dfu_entity->name); -+ -+ /* force cleanup to avoid issue with previous read */ -+ dfu_transaction_cleanup(dfu_entity); -+ -+ ret = stm32prog_header_check(data->header_data, -+ &data->header); -+ -+ /* no header : max size is partition size */ -+ if (ret) { -+ dfu_entity->get_medium_size(dfu_entity, &size); -+ data->header.image_length = size; -+ } -+ -+ /**** Flash the header if necessary for boot partition */ -+ if (data->phase < PHASE_FIRST_USER) -+ boot = 1; -+ -+ /* write header if boot partition */ -+ if (boot) { -+ if (ret) { -+ stm32prog_err("invalid header (error %d)", ret); -+ } else { -+ ret = stm32prog_write(data, -+ (u8 *)data->header_data, -+ BL_HEADER_SIZE); -+ } -+ } else { -+ if (ret) -+ printf(" partition without checksum\n"); -+ ret = 0; -+ } -+ -+ free(data->header_data); -+ data->header_data = NULL; -+ -+ return ret; -+} -+ -+static u8 stm32prog_start(struct stm32prog_data *data, u32 address) -+{ -+ u8 ret = 0; -+ struct dfu_entity *dfu_entity; -+ -+ if (address < 0x100) { -+ if (address == PHASE_OTP) -+ return stm32prog_otp_start(data); -+ -+ if (address == PHASE_PMIC) -+ return stm32prog_pmic_start(data); -+ -+ if (address == PHASE_RESET || address == PHASE_END) { -+ data->cur_part = NULL; -+ data->dfu_seq = 0; -+ data->phase = address; -+ return 0; -+ } -+ if (address != data->phase) { -+ stm32prog_err("invalid received phase id %d, current phase is %d", -+ (u8)address, (u8)data->phase); -+ return -EINVAL; -+ } -+ } -+ /* check the last loaded partition */ -+ if (address == DEFAULT_ADDRESS || address == data->phase) { -+ switch (data->phase) { -+ case PHASE_END: -+ case PHASE_RESET: -+ case PHASE_DO_RESET: -+ data->cur_part = NULL; -+ data->phase = PHASE_DO_RESET; -+ return 0; -+ } -+ dfu_entity = stm32prog_get_entity(data); -+ if (!dfu_entity) -+ return -ENODEV; -+ -+ if (data->dfu_seq) { -+ ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq); -+ data->dfu_seq = 0; -+ if (ret) { -+ stm32prog_err("DFU flush failed [%d]", ret); -+ return ret; -+ } -+ } -+ printf("\n received length = 0x%x\n", data->cursor); -+ if (data->header.present) { -+ if (data->cursor != -+ (data->header.image_length + BL_HEADER_SIZE)) { -+ stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)", -+ data->cursor, -+ data->header.image_length + -+ BL_HEADER_SIZE); -+ return -EIO; -+ } -+ if (data->header.image_checksum != data->checksum) { -+ stm32prog_err("invalid checksum received (0x%x expected 0x%x)", -+ data->checksum, -+ data->header.image_checksum); -+ return -EIO; -+ } -+ printf("\n checksum OK (0x%x)\n", data->checksum); -+ } -+ -+ /* update DFU with received flashlayout */ -+ if (data->phase == PHASE_FLASHLAYOUT) -+ stm32prog_dfu_init(data); -+ } else { -+ void (*entry)(void) = (void *)address; -+ -+ printf("## Starting application at 0x%x ...\n", address); -+ (*entry)(); -+ printf("## Application terminated\n"); -+ ret = -ENOEXEC; -+ } -+ -+ return ret; -+} -+ -+/** -+ * get_address() - Get address if it is valid -+ * -+ * @tmp_xor: Current xor value to update -+ * @return The address area -+ */ -+static u32 get_address(u8 *tmp_xor) -+{ -+ u32 address = 0x0; -+ u8 data; -+ -+ data = stm32prog_serial_getc(); -+ *tmp_xor ^= data; -+ address |= ((u32)data) << 24; -+ -+ data = stm32prog_serial_getc(); -+ address |= ((u32)data) << 16; -+ *tmp_xor ^= data; -+ -+ data = stm32prog_serial_getc(); -+ address |= ((u32)data) << 8; -+ *tmp_xor ^= data; -+ -+ data = stm32prog_serial_getc(); -+ address |= ((u32)data); -+ *tmp_xor ^= data; -+ -+ return address; -+} -+ -+static void stm32prog_serial_result(u8 result) -+{ -+ /* always flush fifo before to send result */ -+ stm32prog_serial_flush(); -+ stm32prog_serial_putc(result); -+} -+ -+/* Command -----------------------------------------------*/ -+/** -+ * get_cmd_command() - Respond to Get command -+ * -+ * @data: Current command context -+ */ -+static void get_cmd_command(struct stm32prog_data *data) -+{ -+ u32 counter = 0x0; -+ -+ stm32prog_serial_putc(NB_CMD); -+ stm32prog_serial_putc(USART_BL_VERSION); -+ -+ for (counter = 0; counter < NB_CMD; counter++) -+ stm32prog_serial_putc(cmd_id[counter]); -+ -+ stm32prog_serial_result(ACK_BYTE); -+} -+ -+/** -+ * get_version_command() - Respond to Get Version command -+ * -+ * @data: Current command context -+ */ -+static void get_version_command(struct stm32prog_data *data) -+{ -+ stm32prog_serial_putc(UBOOT_BL_VERSION); -+ stm32prog_serial_result(ACK_BYTE); -+} -+ -+/** -+ * get_id_command() - Respond to Get ID command -+ * -+ * @data: Current command context -+ */ -+static void get_id_command(struct stm32prog_data *data) -+{ -+ /* Send Device IDCode */ -+ stm32prog_serial_putc(0x1); -+ stm32prog_serial_putc(DEVICE_ID_BYTE1); -+ stm32prog_serial_putc(DEVICE_ID_BYTE2); -+ stm32prog_serial_result(ACK_BYTE); -+} -+ -+/** -+ * get_phase_command() - Respond to Get phase -+ * -+ * @data: Current command context -+ */ -+static void get_phase_command(struct stm32prog_data *data) -+{ -+ char *err_msg = NULL; -+ u8 i, length = 0; -+ u32 destination = DEFAULT_ADDRESS; /* destination address */ -+ int phase = data->phase; -+ -+ if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { -+ err_msg = stm32prog_get_error(data); -+ length = strlen(err_msg); -+ } -+ if (phase == PHASE_FLASHLAYOUT) -+ destination = STM32_DDR_BASE; -+ -+ stm32prog_serial_putc(length + 5); /* Total length */ -+ stm32prog_serial_putc(phase & 0xFF); /* partition ID */ -+ stm32prog_serial_putc(destination); /* byte 1 of address */ -+ stm32prog_serial_putc(destination >> 8); /* byte 2 of address */ -+ stm32prog_serial_putc(destination >> 16); /* byte 3 of address */ -+ stm32prog_serial_putc(destination >> 24); /* byte 4 of address */ -+ -+ stm32prog_serial_putc(length); /* Information length */ -+ for (i = 0; i < length; i++) -+ stm32prog_serial_putc(err_msg[i]); -+ stm32prog_serial_result(ACK_BYTE); -+ -+ if (phase == PHASE_RESET) -+ stm32prog_do_reset(data); -+} -+ -+/** -+ * read_memory_command() - Read data from memory -+ * -+ * @data: Current command context -+ */ -+static void read_memory_command(struct stm32prog_data *data) -+{ -+ u32 address = 0x0; -+ u8 rcv_data = 0x0, tmp_xor = 0x0; -+ u32 counter = 0x0; -+ -+ /* Read memory address */ -+ address = get_address(&tmp_xor); -+ -+ /* If address memory is not received correctly */ -+ rcv_data = stm32prog_serial_getc(); -+ if (rcv_data != tmp_xor) { -+ stm32prog_serial_result(NACK_BYTE); -+ return; -+ } -+ -+ stm32prog_serial_result(ACK_BYTE); -+ -+ /* Read the number of bytes to be received: -+ * Max NbrOfData = Data + 1 = 256 -+ */ -+ rcv_data = stm32prog_serial_getc(); -+ tmp_xor = ~rcv_data; -+ if (stm32prog_serial_getc() != tmp_xor) { -+ stm32prog_serial_result(NACK_BYTE); -+ return; -+ } -+ -+ /* If checksum is correct send ACK */ -+ stm32prog_serial_result(ACK_BYTE); -+ -+ /* Send data to the host: -+ * Number of data to read = data + 1 -+ */ -+ for (counter = (rcv_data + 1); counter != 0; counter--) -+ stm32prog_serial_putc(*(u8 *)(address++)); -+} -+ -+/** -+ * start_command() - Respond to start command -+ * -+ * Jump to user application in RAM or partition check -+ * -+ * @data: Current command context -+ */ -+static void start_command(struct stm32prog_data *data) -+{ -+ u32 address = 0; -+ u8 tmp_xor = 0x0; -+ u8 ret, rcv_data; -+ -+ /* Read memory address */ -+ address = get_address(&tmp_xor); -+ -+ /* If address memory is not received correctly */ -+ rcv_data = stm32prog_serial_getc(); -+ if (rcv_data != tmp_xor) { -+ stm32prog_serial_result(NACK_BYTE); -+ return; -+ } -+ /* validate partition */ -+ ret = stm32prog_start(data, -+ address); -+ -+ if (ret) -+ stm32prog_serial_result(ABORT_BYTE); -+ else -+ stm32prog_serial_result(ACK_BYTE); -+} -+ -+/** -+ * download_command() - Respond to download command -+ * -+ * Write data to not volatile memory, Flash -+ * -+ * @data: Current command context -+ */ -+static void download_command(struct stm32prog_data *data) -+{ -+ u32 address = 0x0; -+ u8 my_xor = 0x0; -+ u8 rcv_xor; -+ u32 counter = 0x0, codesize = 0x0; -+ u8 *ramaddress = 0; -+ u8 rcv_data = 0x0; -+ struct image_header_s *image_header = &data->header; -+ u32 cursor = data->cursor; -+ long size = 0; -+ u8 operation; -+ u32 packet_number; -+ u32 result = ACK_BYTE; -+ u8 ret; -+ unsigned int i; -+ bool error; -+ int rcv; -+ -+ address = get_address(&my_xor); -+ -+ /* If address memory is not received correctly */ -+ rcv_xor = stm32prog_serial_getc(); -+ if (rcv_xor != my_xor) { -+ result = NACK_BYTE; -+ goto end; -+ } -+ -+ /* If address valid send ACK */ -+ stm32prog_serial_result(ACK_BYTE); -+ -+ /* get packet number and operation type */ -+ operation = (u8)((u32)address >> 24); -+ packet_number = ((u32)(((u32)address << 8))) >> 8; -+ -+ switch (operation) { -+ /* supported operation */ -+ case PHASE_FLASHLAYOUT: -+ case PHASE_OTP: -+ case PHASE_PMIC: -+ break; -+ default: -+ result = NACK_BYTE; -+ goto end; -+ } -+ /* check the packet number */ -+ if (packet_number == 0) { -+ /* erase: re-initialize the image_header struct */ -+ data->packet_number = 0; -+ if (data->header_data) -+ memset(data->header_data, 0, BL_HEADER_SIZE); -+ else -+ data->header_data = calloc(1, BL_HEADER_SIZE); -+ cursor = 0; -+ data->cursor = 0; -+ data->checksum = 0; -+ /*idx = cursor;*/ -+ } else { -+ data->packet_number++; -+ } -+ -+ /* Check with the number of current packet if the device receive -+ * the true packet -+ */ -+ if (packet_number != data->packet_number) { -+ data->packet_number--; -+ result = NACK_BYTE; -+ goto end; -+ } -+ -+ /*-- Read number of bytes to be written and data -----------*/ -+ -+ /* Read the number of bytes to be written: -+ * Max NbrOfData = data + 1 <= 256 -+ */ -+ rcv_data = stm32prog_serial_getc(); -+ -+ /* NbrOfData to write = data + 1 */ -+ codesize = rcv_data + 0x01; -+ -+ if (codesize > USART_RAM_BUFFER_SIZE) { -+ result = NACK_BYTE; -+ goto end; -+ } -+ -+ /* Checksum Initialization */ -+ my_xor = rcv_data; -+ -+ /* UART receive data and send to Buffer */ -+ counter = codesize; -+ error = stm32prog_serial_get_buffer(data->buffer, &counter); -+ -+ /* read checksum */ -+ if (!error) { -+ rcv = stm32prog_serial_getc_err(); -+ error = !!(rcv < 0); -+ rcv_xor = rcv; -+ } -+ -+ if (error) { -+ printf("transmission error on packet %d, byte %d\n", -+ packet_number, codesize - counter); -+ /* waiting end of packet before flush & NACK */ -+ mdelay(30); -+ data->packet_number--; -+ result = NACK_BYTE; -+ goto end; -+ } -+ -+ /* Compute Checksum */ -+ ramaddress = data->buffer; -+ for (counter = codesize; counter != 0; counter--) -+ my_xor ^= *(ramaddress++); -+ -+ /* If Checksum is incorrect */ -+ if (rcv_xor != my_xor) { -+ printf("checksum error on packet %d\n", -+ packet_number); -+ /* wait to be sure that all data are received -+ * in the FIFO before flush -+ */ -+ mdelay(30); -+ data->packet_number--; -+ result = NACK_BYTE; -+ goto end; -+ } -+ -+ /* Update current position in buffer */ -+ data->cursor += codesize; -+ -+ if (operation == PHASE_OTP) { -+ size = data->cursor - cursor; -+ /* no header for OTP */ -+ if (stm32prog_otp_write(data, cursor, -+ data->buffer, &size)) -+ result = ABORT_BYTE; -+ goto end; -+ } -+ -+ if (operation == PHASE_PMIC) { -+ size = data->cursor - cursor; -+ /* no header for PMIC */ -+ if (stm32prog_pmic_write(data, cursor, -+ data->buffer, &size)) -+ result = ABORT_BYTE; -+ goto end; -+ } -+ -+ if (cursor < BL_HEADER_SIZE) { -+ /* size = portion of header in this chunck */ -+ if (data->cursor >= BL_HEADER_SIZE) -+ size = BL_HEADER_SIZE - cursor; -+ else -+ size = data->cursor - cursor; -+ memcpy((void *)((u32)(data->header_data) + cursor), -+ data->buffer, size); -+ cursor += size; -+ -+ if (cursor == BL_HEADER_SIZE) { -+ /* Check and Write the header */ -+ if (stm32prog_header(data)) { -+ result = ABORT_BYTE; -+ goto end; -+ } -+ } else { -+ goto end; -+ } -+ } -+ -+ if (image_header->present) { -+ if (data->cursor <= BL_HEADER_SIZE) -+ goto end; -+ /* compute checksum on payload */ -+ for (i = (unsigned long)size; i < codesize; i++) -+ data->checksum += data->buffer[i]; -+ -+ if (data->cursor > -+ image_header->image_length + BL_HEADER_SIZE) { -+ pr_err("expected size exceeded\n"); -+ result = ABORT_BYTE; -+ goto end; -+ } -+ -+ /* write data (payload) */ -+ ret = stm32prog_write(data, -+ &data->buffer[size], -+ codesize - size); -+ } else { -+ /* write all */ -+ ret = stm32prog_write(data, -+ data->buffer, -+ codesize); -+ } -+ if (ret) -+ result = ABORT_BYTE; -+ -+end: -+ stm32prog_serial_result(result); -+} -+ -+/** -+ * read_partition() - Respond to read command -+ * -+ * Read data from not volatile memory, Flash -+ * -+ * @data: Current command context -+ */ -+static void read_partition_command(struct stm32prog_data *data) -+{ -+ u32 i, part_id, codesize, offset = 0, rcv_data; -+ long size; -+ u8 tmp_xor; -+ int res; -+ u8 buffer[256]; -+ -+ part_id = stm32prog_serial_getc(); -+ tmp_xor = part_id; -+ -+ offset = get_address(&tmp_xor); -+ -+ rcv_data = stm32prog_serial_getc(); -+ if (rcv_data != tmp_xor) { -+ pr_debug("1st checksum received = %x, computed %x\n", -+ rcv_data, tmp_xor); -+ goto error; -+ } -+ stm32prog_serial_putc(ACK_BYTE); -+ -+ /* NbrOfData to read = data + 1 */ -+ rcv_data = stm32prog_serial_getc(); -+ codesize = rcv_data + 0x01; -+ tmp_xor = rcv_data; -+ -+ rcv_data = stm32prog_serial_getc(); -+ if ((rcv_data ^ tmp_xor) != 0xFF) { -+ pr_debug("2nd checksum received = %x, computed %x\n", -+ rcv_data, tmp_xor); -+ goto error; -+ } -+ -+ pr_debug("%s : %x\n", __func__, part_id); -+ rcv_data = 0; -+ switch (part_id) { -+ case PHASE_OTP: -+ size = codesize; -+ if (!stm32prog_otp_read(data, offset, buffer, &size)) -+ rcv_data = size; -+ break; -+ case PHASE_PMIC: -+ size = codesize; -+ if (!stm32prog_pmic_read(data, offset, buffer, &size)) -+ rcv_data = size; -+ break; -+ default: -+ res = stm32prog_read(data, part_id, offset, -+ buffer, codesize); -+ if (res > 0) -+ rcv_data = res; -+ break; -+ } -+ if (rcv_data > 0) { -+ stm32prog_serial_putc(ACK_BYTE); -+ /*----------- Send data to the host -----------*/ -+ for (i = 0; i < rcv_data; i++) -+ stm32prog_serial_putc(buffer[i]); -+ /*----------- Send filler to the host -----------*/ -+ for (; i < codesize; i++) -+ stm32prog_serial_putc(0x0); -+ return; -+ } -+ stm32prog_serial_result(ABORT_BYTE); -+ return; -+ -+error: -+ stm32prog_serial_result(NACK_BYTE); -+} -+ -+/* MAIN function = SERIAL LOOP ***********************************************/ -+ -+/** -+ * stm32prog_serial_loop() - USART bootloader Loop routine -+ * -+ * @data: Current command context -+ * @return true if reset is needed after loop -+ */ -+bool stm32prog_serial_loop(struct stm32prog_data *data) -+{ -+ u32 counter = 0x0; -+ u8 command = 0x0; -+ u8 found; -+ int phase = data->phase; -+ -+ /* element of cmd_func need to aligned with cmd_id[]*/ -+ void (*cmd_func[NB_CMD])(struct stm32prog_data *) = { -+ /* GET_CMD_COMMAND */ get_cmd_command, -+ /* GET_VER_COMMAND */ get_version_command, -+ /* GET_ID_COMMAND */ get_id_command, -+ /* GET_PHASE_COMMAND */ get_phase_command, -+ /* RM_COMMAND */ read_memory_command, -+ /* READ_PART_COMMAND */ read_partition_command, -+ /* START_COMMAND */ start_command, -+ /* DOWNLOAD_COMMAND */ download_command -+ }; -+ -+ /* flush and NACK pending command received during u-boot init -+ * request command reemit -+ */ -+ stm32prog_serial_result(NACK_BYTE); -+ -+ clear_ctrlc(); /* forget any previous Control C */ -+ while (!had_ctrlc()) { -+ phase = data->phase; -+ -+ if (phase == PHASE_DO_RESET) -+ return true; -+ -+ /* Get the user command: read first byte */ -+ command = stm32prog_serial_getc(); -+ -+ if (command == INIT_BYTE) { -+ puts("\nConnected\n"); -+ stm32prog_serial_result(ACK_BYTE); -+ continue; -+ } -+ -+ found = 0; -+ for (counter = 0; counter < NB_CMD; counter++) -+ if (cmd_id[counter] == command) { -+ found = 1; -+ break; -+ } -+ if (found) -+ if ((command ^ stm32prog_serial_getc()) != 0xFF) -+ found = 0; -+ if (!found) { -+ /* wait to be sure that all data are received -+ * in the FIFO before flush (CMD and XOR) -+ */ -+ mdelay(3); -+ stm32prog_serial_result(NACK_BYTE); -+ } else { -+ stm32prog_serial_result(ACK_BYTE); -+ cmd_func[counter](data); -+ } -+ WATCHDOG_RESET(); -+ } -+ -+ /* clean device */ -+ if (gd->cur_serial_dev == down_serial_dev) { -+ /* restore console on uart */ -+ gd->flags &= ~(GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT); -+ } -+ down_serial_dev = NULL; -+ -+ return false; /* no reset after ctrlc */ -+} -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c -new file mode 100644 -index 0000000..30547f9 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c -@@ -0,0 +1,232 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "stm32prog.h" -+ -+static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase, -+ u32 offset) -+{ -+ struct stm32prog_part_t *part; -+ int i; -+ -+ if (phase == data->phase) { -+ data->offset = offset; -+ data->dfu_seq = 0; -+ return 0; -+ } -+ -+ /* found partition for phase */ -+ for (i = 0; i < data->part_nb; i++) { -+ part = &data->part_array[i]; -+ if (part->id == phase) { -+ data->cur_part = part; -+ data->phase = phase; -+ data->offset = offset; -+ data->dfu_seq = 0; -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+static int stm32prog_cmd_write(u64 offset, void *buf, long *len) -+{ -+ u8 phase; -+ u32 address; -+ u8 *pt = buf; -+ void (*entry)(void); -+ int ret; -+ -+ if (*len < 5) { -+ pr_err("size not allowed\n"); -+ return -EINVAL; -+ } -+ if (offset) { -+ pr_err("invalid offset\n"); -+ return -EINVAL; -+ } -+ phase = pt[0]; -+ address = (pt[1] << 24) | (pt[2] << 16) | (pt[3] << 8) | pt[4]; -+ if (phase == PHASE_RESET) { -+ entry = (void *)address; -+ printf("## Starting application at 0x%x ...\n", address); -+ (*entry)(); -+ printf("## Application terminated\n"); -+ return 0; -+ } -+ /* set phase and offset */ -+ ret = stm32prog_set_phase(stm32prog_data, phase, address); -+ if (ret) -+ pr_err("failed: %d\n", ret); -+ return ret; -+} -+ -+#define PHASE_MIN_SIZE 9 -+static int stm32prog_cmd_read(u64 offset, void *buf, long *len) -+{ -+ u32 destination = DEFAULT_ADDRESS; /* destination address */ -+ u32 dfu_offset; -+ u8 *pt_buf = buf; -+ int phase; -+ char *err_msg; -+ int length; -+ -+ if (*len < PHASE_MIN_SIZE) { -+ pr_err("request exceeds allowed area\n"); -+ return -EINVAL; -+ } -+ if (offset) { -+ *len = 0; /* EOF for second request */ -+ return 0; -+ } -+ phase = stm32prog_data->phase; -+ if (phase == PHASE_FLASHLAYOUT) -+ destination = STM32_DDR_BASE; -+ dfu_offset = stm32prog_data->offset; -+ -+ /* mandatory header, size = PHASE_MIN_SIZE */ -+ *pt_buf++ = (u8)(phase & 0xFF); -+ *pt_buf++ = (u8)(destination); -+ *pt_buf++ = (u8)(destination >> 8); -+ *pt_buf++ = (u8)(destination >> 16); -+ *pt_buf++ = (u8)(destination >> 24); -+ *pt_buf++ = (u8)(dfu_offset); -+ *pt_buf++ = (u8)(dfu_offset >> 8); -+ *pt_buf++ = (u8)(dfu_offset >> 16); -+ *pt_buf++ = (u8)(dfu_offset >> 24); -+ -+ if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { -+ err_msg = stm32prog_get_error(stm32prog_data); -+ length = strlen(err_msg); -+ if (length + PHASE_MIN_SIZE > *len) -+ length = *len - PHASE_MIN_SIZE; -+ -+ memcpy(pt_buf, err_msg, length); -+ *len = PHASE_MIN_SIZE + length; -+ stm32prog_do_reset(stm32prog_data); -+ } else if (phase == PHASE_FLASHLAYOUT) { -+ *pt_buf++ = stm32prog_data->part_nb ? 1 : 0; -+ *len = PHASE_MIN_SIZE + 1; -+ } else { -+ *len = PHASE_MIN_SIZE; -+ } -+ -+ return 0; -+} -+ -+int stm32prog_write_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len) -+{ -+ if (dfu->dev_type != DFU_DEV_VIRT) -+ return -EINVAL; -+ -+ switch (dfu->data.virt.dev_num) { -+ case PHASE_CMD: -+ return stm32prog_cmd_write(offset, buf, len); -+ -+ case PHASE_OTP: -+ return stm32prog_otp_write(stm32prog_data, (u32)offset, -+ buf, len); -+ -+ case PHASE_PMIC: -+ return stm32prog_pmic_write(stm32prog_data, (u32)offset, -+ buf, len); -+ } -+ *len = 0; -+ return 0; -+} -+ -+int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len) -+{ -+ if (dfu->dev_type != DFU_DEV_VIRT) -+ return -EINVAL; -+ -+ switch (dfu->data.virt.dev_num) { -+ case PHASE_CMD: -+ return stm32prog_cmd_read(offset, buf, len); -+ -+ case PHASE_OTP: -+ return stm32prog_otp_read(stm32prog_data, (u32)offset, -+ buf, len); -+ -+ case PHASE_PMIC: -+ return stm32prog_pmic_read(stm32prog_data, (u32)offset, -+ buf, len); -+ } -+ *len = 0; -+ return 0; -+} -+ -+int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) -+{ -+ if (dfu->dev_type != DFU_DEV_VIRT) { -+ *size = 0; -+ pr_debug("%s, invalid dev_type = %d\n", -+ __func__, dfu->dev_type); -+ return -EINVAL; -+ } -+ -+ switch (dfu->data.virt.dev_num) { -+ case PHASE_CMD: -+ *size = 512; -+ break; -+ case PHASE_OTP: -+ *size = OTP_SIZE; -+ break; -+ case PHASE_PMIC: -+ *size = PMIC_SIZE; -+ break; -+ } -+ -+ return 0; -+} -+ -+bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) -+{ -+ int ret; -+ bool result; -+ /* USB download gadget for STM32 Programmer */ -+ char product[128]; -+ char name[SOC_NAME_SIZE]; -+ -+ get_soc_name(name); -+ snprintf(product, sizeof(product), -+ "USB download gadget@Device ID /0x%03X, @Revision ID /0x%04X, @Name /%s,", -+ get_cpu_dev(), get_cpu_rev(), name); -+ g_dnl_set_product(product); -+ -+ if (stm32prog_data->phase == PHASE_FLASHLAYOUT) { -+ ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); -+ if (ret || stm32prog_data->phase == PHASE_DO_RESET) -+ return ret; -+ /* prepare the second enumeration with the FlashLayout */ -+ if (stm32prog_data->phase == PHASE_FLASHLAYOUT) -+ stm32prog_dfu_init(data); -+ /* found next selected partition */ -+ stm32prog_next_phase(data); -+ } -+ -+ ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); -+ -+ result = !!(ret) || (stm32prog_data->phase == PHASE_DO_RESET); -+ -+ g_dnl_set_product(NULL); -+ -+ return result; -+} -+ -+int g_dnl_get_board_bcd_device_number(int gcnum) -+{ -+ pr_debug("%s\n", __func__); -+ return 0x200; -+} -diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c -index ed7d9f6..305534f 100644 ---- a/arch/arm/mach-stm32mp/cpu.c -+++ b/arch/arm/mach-stm32mp/cpu.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -35,7 +36,9 @@ - #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) - - #define PWR_CR1 (STM32_PWR_BASE + 0x00) -+#define PWR_MCUCR (STM32_PWR_BASE + 0x14) - #define PWR_CR1_DBP BIT(8) -+#define PWR_MCUCR_SBF BIT(6) - - /* DBGMCU register */ - #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -@@ -59,12 +62,6 @@ - #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) - #define BOOTROM_INSTANCE_SHIFT 16 - --/* BSEC OTP index */ --#define BSEC_OTP_RPN 1 --#define BSEC_OTP_SERIAL 13 --#define BSEC_OTP_PKG 16 --#define BSEC_OTP_MAC 57 -- - /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ - #define RPN_SHIFT 0 - #define RPN_MASK GENMASK(7, 0) -@@ -149,8 +146,13 @@ static void dbgmcu_init(void) - { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - -- /* Freeze IWDG2 if Cortex-A7 is in debug mode */ -- setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); -+ /* -+ * Freeze IWDG2 if Cortex-A7 is in debug mode -+ * done in TF-A for TRUSTED boot and -+ * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE -+ */ -+ if (!CONFIG_IS_ENABLED(STM32MP1_TRUSTED) && bsec_dbgswenable()) -+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); - } - #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ - -@@ -206,6 +208,11 @@ int arch_cpu_init(void) - security_init(); - update_bootmode(); - #endif -+ /* Reset Coprocessor state unless it wakes up from Standby power mode */ -+ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { -+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); -+ writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); -+ } - #endif - - boot_mode = get_bootmode(); -@@ -230,9 +237,22 @@ void enable_caches(void) - - static u32 read_idc(void) - { -- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); -+ /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ -+ if (bsec_dbgswenable()) { -+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); -+ -+ return readl(DBGMCU_IDC); -+ } - -- return readl(DBGMCU_IDC); -+ if (CONFIG_IS_ENABLED(STM32MP15x)) -+ return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ -+ else -+ return 0x0; -+} -+ -+u32 get_cpu_dev(void) -+{ -+ return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; - } - - u32 get_cpu_rev(void) -@@ -265,11 +285,7 @@ static u32 get_cpu_rpn(void) - - u32 get_cpu_type(void) - { -- u32 id; -- -- id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; -- -- return (id << 16) | get_cpu_rpn(); -+ return (get_cpu_dev() << 16) | get_cpu_rpn(); - } - - /* Get Package options from OTP */ -@@ -278,25 +294,42 @@ u32 get_cpu_package(void) - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); - } - --#if defined(CONFIG_DISPLAY_CPUINFO) --int print_cpuinfo(void) -+void get_soc_name(char name[SOC_NAME_SIZE]) - { - char *cpu_s, *cpu_r, *pkg; - - /* MPUs Part Numbers */ - switch (get_cpu_type()) { -+ case CPU_STM32MP157Fxx: -+ cpu_s = "157F"; -+ break; -+ case CPU_STM32MP157Dxx: -+ cpu_s = "157D"; -+ break; - case CPU_STM32MP157Cxx: - cpu_s = "157C"; - break; - case CPU_STM32MP157Axx: - cpu_s = "157A"; - break; -+ case CPU_STM32MP153Fxx: -+ cpu_s = "153F"; -+ break; -+ case CPU_STM32MP153Dxx: -+ cpu_s = "153D"; -+ break; - case CPU_STM32MP153Cxx: - cpu_s = "153C"; - break; - case CPU_STM32MP153Axx: - cpu_s = "153A"; - break; -+ case CPU_STM32MP151Fxx: -+ cpu_s = "151F"; -+ break; -+ case CPU_STM32MP151Dxx: -+ cpu_s = "151D"; -+ break; - case CPU_STM32MP151Cxx: - cpu_s = "151C"; - break; -@@ -335,12 +368,24 @@ int print_cpuinfo(void) - case CPU_REVB: - cpu_r = "B"; - break; -+ case CPU_REVZ: -+ cpu_r = "Z"; -+ break; - default: - cpu_r = "?"; - break; - } - -- printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); -+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); -+} -+ -+#if defined(CONFIG_DISPLAY_CPUINFO) -+int print_cpuinfo(void) -+{ -+ char name[SOC_NAME_SIZE]; -+ -+ get_soc_name(name); -+ printf("CPU: %s\n", name); - - return 0; - } -@@ -405,6 +450,10 @@ static void setup_boot_mode(void) - env_set("boot_device", "nand"); - env_set("boot_instance", "0"); - break; -+ case BOOT_FLASH_SPINAND: -+ env_set("boot_device", "spi-nand"); -+ env_set("boot_instance", "0"); -+ break; - case BOOT_FLASH_NOR: - env_set("boot_device", "nor"); - env_set("boot_instance", "0"); -@@ -449,7 +498,7 @@ static void setup_boot_mode(void) - * If there is no MAC address in the environment, then it will be initialized - * (silently) from the value in the OTP. - */ --static int setup_mac_address(void) -+__weak int setup_mac_address(void) - { - #if defined(CONFIG_NET) - int ret; -@@ -481,8 +530,9 @@ static int setup_mac_address(void) - return -EINVAL; - } - pr_debug("OTP MAC address = %pM\n", enetaddr); -- ret = !eth_env_set_enetaddr("ethaddr", enetaddr); -- if (!ret) -+ -+ ret = eth_env_set_enetaddr("ethaddr", enetaddr); -+ if (ret) - pr_err("Failed to set mac address %pM from OTP: %d\n", - enetaddr, ret); - #endif -@@ -492,13 +542,13 @@ static int setup_mac_address(void) - - static int setup_serial_number(void) - { -+ char *serial_env; - char serial_string[25]; - u32 otp[3] = {0, 0, 0 }; - struct udevice *dev; - int ret; - -- if (env_get("serial#")) -- return 0; -+ serial_env = env_get("serial#"); - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), -@@ -512,6 +562,15 @@ static int setup_serial_number(void) - return ret; - - sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); -+ -+ if (serial_env) { -+ if (!strcmp(serial_string, serial_env)) -+ return 0; -+ /* For invalid enviromnent (serial# change), reset to default */ -+ env_set_default("serial number mismatch", 0); -+ } -+ -+ /* save serial number */ - env_set("serial#", serial_string); - - return 0; -@@ -519,9 +578,9 @@ static int setup_serial_number(void) - - int arch_misc_init(void) - { -+ setup_serial_number(); - setup_boot_mode(); - setup_mac_address(); -- setup_serial_number(); - - return 0; - } -diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c -index 7688b3e..3233415 100644 ---- a/arch/arm/mach-stm32mp/dram_init.c -+++ b/arch/arm/mach-stm32mp/dram_init.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - - DECLARE_GLOBAL_DATA_PTR; -@@ -31,3 +32,20 @@ int dram_init(void) - - return 0; - } -+ -+ulong board_get_usable_ram_top(ulong total_size) -+{ -+ phys_addr_t reg; -+ struct lmb lmb; -+ -+ /* found enough not-reserved memory to relocated U-Boot */ -+ lmb_init(&lmb); -+ lmb_add(&lmb, gd->ram_base, gd->ram_size); -+ boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); -+ reg = lmb_alloc(&lmb, CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); -+ -+ if (reg) -+ return ALIGN(reg + CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); -+ -+ return gd->ram_top; -+} -diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c -index 82c430b..21b5f09 100644 ---- a/arch/arm/mach-stm32mp/fdt.c -+++ b/arch/arm/mach-stm32mp/fdt.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -23,6 +24,12 @@ - - #define ETZPC_RESERVED 0xffffffff - -+#define STM32_FDCAN_BASE 0x4400e000 -+#define STM32_CRYP2_BASE 0x4c005000 -+#define STM32_CRYP1_BASE 0x54001000 -+#define STM32_GPU_BASE 0x59000000 -+#define STM32_DSI_BASE 0x5a000000 -+ - static const u32 stm32mp1_ip_addr[] = { - 0x5c008000, /* 00 stgenc */ - 0x54000000, /* 01 bkpsram */ -@@ -33,7 +40,7 @@ static const u32 stm32mp1_ip_addr[] = { - ETZPC_RESERVED, /* 06 reserved */ - 0x54003000, /* 07 rng1 */ - 0x54002000, /* 08 hash1 */ -- 0x54001000, /* 09 cryp1 */ -+ STM32_CRYP1_BASE, /* 09 cryp1 */ - 0x5a003000, /* 0A ddrctrl */ - 0x5a004000, /* 0B ddrphyc */ - 0x5c009000, /* 0C i2c6 */ -@@ -86,7 +93,7 @@ static const u32 stm32mp1_ip_addr[] = { - 0x4400b000, /* 3B sai2 */ - 0x4400c000, /* 3C sai3 */ - 0x4400d000, /* 3D dfsdm */ -- 0x4400e000, /* 3E tt_fdcan */ -+ STM32_FDCAN_BASE, /* 3E tt_fdcan */ - ETZPC_RESERVED, /* 3F reserved */ - 0x50021000, /* 40 lptim2 */ - 0x50022000, /* 41 lptim3 */ -@@ -99,7 +106,7 @@ static const u32 stm32mp1_ip_addr[] = { - 0x48003000, /* 48 adc */ - 0x4c002000, /* 49 hash2 */ - 0x4c003000, /* 4A rng2 */ -- 0x4c005000, /* 4B cryp2 */ -+ STM32_CRYP2_BASE, /* 4B cryp2 */ - ETZPC_RESERVED, /* 4C reserved */ - ETZPC_RESERVED, /* 4D reserved */ - ETZPC_RESERVED, /* 4E reserved */ -@@ -126,11 +133,13 @@ static const u32 stm32mp1_ip_addr[] = { - static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) - { - int node; -+ fdt_addr_t regs; - - for (node = fdt_first_subnode(fdt, offset); - node >= 0; - node = fdt_next_subnode(fdt, node)) { -- if (addr == (u32)fdt_getprop(fdt, node, "reg", 0)) { -+ regs = fdtdec_get_addr(fdt, node, "reg"); -+ if (addr == regs) { - if (fdtdec_get_is_enabled(fdt, node)) { - fdt_status_disabled(fdt, node); - -@@ -143,11 +152,11 @@ static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) - return false; - } - --static int stm32_fdt_fixup_etzpc(void *fdt) -+static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) - { - const u32 *array; - int array_size, i; -- int soc_node, offset, shift; -+ int offset, shift; - u32 addr, status, decprot[ETZPC_DECPROT_NB]; - - array = stm32mp1_ip_addr; -@@ -156,10 +165,6 @@ static int stm32_fdt_fixup_etzpc(void *fdt) - for (i = 0; i < ETZPC_DECPROT_NB; i++) - decprot[i] = readl(ETZPC_DECPROT(i)); - -- soc_node = fdt_path_offset(fdt, "/soc"); -- if (soc_node < 0) -- return soc_node; -- - for (i = 0; i < array_size; i++) { - offset = i / NB_PROT_PER_REG; - shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; -@@ -180,6 +185,60 @@ static int stm32_fdt_fixup_etzpc(void *fdt) - return 0; - } - -+/* deactivate all the cpu except core 0 */ -+static void stm32_fdt_fixup_cpu(void *blob, char *name) -+{ -+ int off; -+ u32 reg; -+ -+ off = fdt_path_offset(blob, "/cpus"); -+ if (off < 0) { -+ printf("%s: couldn't find /cpus node\n", __func__); -+ return; -+ } -+ -+ off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); -+ while (off != -FDT_ERR_NOTFOUND) { -+ reg = fdtdec_get_addr(blob, off, "reg"); -+ if (reg != 0) { -+ fdt_del_node(blob, off); -+ printf("FDT: cpu %d node remove for %s\n", reg, name); -+ /* after delete we can't trust the offsets anymore */ -+ off = -1; -+ } -+ off = fdt_node_offset_by_prop_value(blob, off, -+ "device_type", "cpu", 4); -+ } -+} -+ -+static void stm32_fdt_disable(void *fdt, int offset, u32 addr, -+ const char *string, const char *name) -+{ -+ if (fdt_disable_subnode_by_address(fdt, offset, addr)) -+ printf("FDT: %s@%08x node disabled for %s\n", -+ string, addr, name); -+} -+ -+static void stm32_fdt_disable_optee(void *blob) -+{ -+ int off, node; -+ -+ off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); -+ if (off >= 0 && fdtdec_get_is_enabled(blob, off)) -+ fdt_status_disabled(blob, off); -+ -+ /* Disabled "optee@..." reserved-memory node */ -+ off = fdt_path_offset(blob, "/reserved-memory/"); -+ if (off < 0) -+ return; -+ for (node = fdt_first_subnode(blob, off); -+ node >= 0; -+ node = fdt_next_subnode(blob, node)) { -+ if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) -+ fdt_status_disabled(blob, node); -+ } -+} -+ - /* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. -@@ -187,14 +246,59 @@ static int stm32_fdt_fixup_etzpc(void *fdt) - int ft_system_setup(void *blob, bd_t *bd) - { - int ret = 0; -- u32 pkg; -+ int soc; -+ u32 pkg, cpu; -+ char name[SOC_NAME_SIZE]; -+ -+ soc = fdt_path_offset(blob, "/soc"); -+ if (soc < 0) -+ return soc; - - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { -- ret = stm32_fdt_fixup_etzpc(blob); -+ ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; - } - -+ /* MPUs Part Numbers and name*/ -+ cpu = get_cpu_type(); -+ get_soc_name(name); -+ -+ switch (cpu) { -+ case CPU_STM32MP151Fxx: -+ case CPU_STM32MP151Dxx: -+ case CPU_STM32MP151Cxx: -+ case CPU_STM32MP151Axx: -+ stm32_fdt_fixup_cpu(blob, name); -+ /* after cpu delete we can't trust the soc offsets anymore */ -+ soc = fdt_path_offset(blob, "/soc"); -+ stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); -+ /* fall through */ -+ case CPU_STM32MP153Fxx: -+ case CPU_STM32MP153Dxx: -+ case CPU_STM32MP153Cxx: -+ case CPU_STM32MP153Axx: -+ stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); -+ stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name); -+ break; -+ default: -+ break; -+ } -+ -+ switch (cpu) { -+ case CPU_STM32MP157Dxx: -+ case CPU_STM32MP157Axx: -+ case CPU_STM32MP153Dxx: -+ case CPU_STM32MP153Axx: -+ case CPU_STM32MP151Dxx: -+ case CPU_STM32MP151Axx: -+ stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); -+ stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); -+ break; -+ default: -+ break; -+ } -+ - switch (get_cpu_package()) { - case PKG_AA_LBGA448: - pkg = STM32MP_PKG_AA; -@@ -219,5 +323,9 @@ int ft_system_setup(void *blob, bd_t *bd) - "st,package", pkg, false); - } - -+ if (!CONFIG_IS_ENABLED(OPTEE) || -+ !tee_find_device(NULL, NULL, NULL, NULL)) -+ stm32_fdt_disable_optee(blob); -+ - return ret; - } -diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h -new file mode 100644 -index 0000000..252eac3 ---- /dev/null -+++ b/arch/arm/mach-stm32mp/include/mach/bsec.h -@@ -0,0 +1,7 @@ -+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+/* check self hosted debug status = BSEC_DENABLE.DBGSWENABLE */ -+bool bsec_dbgswenable(void); -diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h -index b8a17cf..bfc42a7 100644 ---- a/arch/arm/mach-stm32mp/include/mach/ddr.h -+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h -@@ -9,8 +9,10 @@ - /* DDR power initializations */ - enum ddr_type { - STM32MP_DDR3, -- STM32MP_LPDDR2, -- STM32MP_LPDDR3, -+ STM32MP_LPDDR2_16, -+ STM32MP_LPDDR2_32, -+ STM32MP_LPDDR3_16, -+ STM32MP_LPDDR3_32, - }; - - int board_ddr_power_init(enum ddr_type ddr_type); -diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h -index b3e9ccc..8820bc4 100644 ---- a/arch/arm/mach-stm32mp/include/mach/stm32.h -+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h -@@ -37,7 +37,6 @@ - /* enumerated used to identify the SYSCON driver instance */ - enum { - STM32MP_SYSCON_UNKNOWN, -- STM32MP_SYSCON_PWR, - STM32MP_SYSCON_SYSCFG, - }; - -@@ -80,15 +79,29 @@ enum boot_device { - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, -+ -+ BOOT_FLASH_SPINAND = 0x70, -+ BOOT_FLASH_SPINAND_1 = 0x71, - }; - - /* TAMP registers */ - #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) -+/* secure access */ - #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) - #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) -+/* non secure access */ -+#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) -+#define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) - #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) - #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) - -+#define TAMP_COPRO_STATE_OFF 0 -+#define TAMP_COPRO_STATE_INIT 1 -+#define TAMP_COPRO_STATE_CRUN 2 -+#define TAMP_COPRO_STATE_CSTOP 3 -+#define TAMP_COPRO_STATE_STANDBY 4 -+#define TAMP_COPRO_STATE_CRASH 5 -+ - #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) - #define TAMP_BOOT_MODE_SHIFT 8 - #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -@@ -111,7 +124,14 @@ enum forced_boot_mode { - #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4) - #define STM32_BSEC_OTP_OFFSET 0x80000000 - #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4) -- -+#define STM32_BSEC_LOCK_OFFSET 0xC0000000 -+#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) -+ -+/* BSEC OTP index */ -+#define BSEC_OTP_RPN 1 -+#define BSEC_OTP_SERIAL 13 -+#define BSEC_OTP_PKG 16 -+#define BSEC_OTP_MAC 57 - #define BSEC_OTP_BOARD 59 - - #endif /* __ASSEMBLY__*/ -diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -index 8130546..dea5b4a 100644 ---- a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -+++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -@@ -18,8 +18,16 @@ - #define STM32_SMC_VERSION 0x82000000 - - /* Secure Service access from Non-secure */ -+#define STM32_SMC_RCC 0x82001000 -+#define STM32_SMC_PWR 0x82001001 -+#define STM32_SMC_RTC 0x82001002 - #define STM32_SMC_BSEC 0x82001003 - -+/* Register access service use for RCC/RTC/PWR */ -+#define STM32_SMC_REG_WRITE 0x1 -+#define STM32_SMC_REG_SET 0x2 -+#define STM32_SMC_REG_CLEAR 0x3 -+ - /* Service for BSEC */ - #define STM32_SMC_READ_SHADOW 0x01 - #define STM32_SMC_PROG_OTP 0x02 -@@ -27,6 +35,7 @@ - #define STM32_SMC_READ_OTP 0x04 - #define STM32_SMC_READ_ALL 0x05 - #define STM32_SMC_WRITE_ALL 0x06 -+#define STM32_SMC_WRLOCK_OTP 0x07 - - /* SMC error codes */ - #define STM32_SMC_OK 0x0 -@@ -45,8 +54,8 @@ static inline u32 stm32_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *result) - arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res); - - if (res.a0) { -- pr_err("%s: Failed to exec in secure mode (err = %ld)\n", -- __func__, res.a0); -+ pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", -+ __func__, svc, op, res.a0); - return -EINVAL; - } - if (result) -diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h -new file mode 100644 -index 0000000..c080b9c ---- /dev/null -+++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#define STM32PROG_VIRT_FIRST_DEV_NUM 0xF1 -+ -+int stm32prog_write_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len); -+int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len); -+int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); -+ -+bool stm32prog_get_tee_partitions(void); -+ -+bool stm32prog_get_fsbl_nor(void); -diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h -index 99eefab..b6ad3c6 100644 ---- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h -+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h -@@ -3,19 +3,31 @@ - * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved - */ - --/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/ -+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */ - #define CPU_STM32MP157Cxx 0x05000000 - #define CPU_STM32MP157Axx 0x05000001 - #define CPU_STM32MP153Cxx 0x05000024 - #define CPU_STM32MP153Axx 0x05000025 - #define CPU_STM32MP151Cxx 0x0500002E - #define CPU_STM32MP151Axx 0x0500002F -+#define CPU_STM32MP157Fxx 0x05000080 -+#define CPU_STM32MP157Dxx 0x05000081 -+#define CPU_STM32MP153Fxx 0x050000A4 -+#define CPU_STM32MP153Dxx 0x050000A5 -+#define CPU_STM32MP151Fxx 0x050000AE -+#define CPU_STM32MP151Dxx 0x050000AF - - /* return CPU_STMP32MP...Xxx constants */ - u32 get_cpu_type(void); - -+#define CPU_DEV_STM32MP15 0x500 -+ -+/* return CPU_DEV constants */ -+u32 get_cpu_dev(void); -+ - #define CPU_REVA 0x1000 - #define CPU_REVB 0x2000 -+#define CPU_REVZ 0x2001 - - /* return CPU_REV constants */ - u32 get_cpu_rev(void); -@@ -28,5 +40,15 @@ u32 get_cpu_package(void); - #define PKG_AC_TFBGA361 2 - #define PKG_AD_TFBGA257 1 - -+/* Get SOC name */ -+#define SOC_NAME_SIZE 20 -+void get_soc_name(char name[SOC_NAME_SIZE]); -+ - /* return boot mode */ - u32 get_bootmode(void); -+ -+int setup_mac_address(void); -+ -+/* board power management : configure vddcore according OPP */ -+void board_vddcore_init(u32 voltage_mv); -+int board_vddcore_set(void); -diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c -index 1d91b2d..3fb038d 100644 ---- a/arch/arm/mach-stm32mp/psci.c -+++ b/arch/arm/mach-stm32mp/psci.c -@@ -30,6 +30,22 @@ u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = { - PSCI_AFFINITY_LEVEL_ON, - PSCI_AFFINITY_LEVEL_OFF}; - -+static u32 __secure_data cntfrq; -+ -+static u32 __secure cp15_read_cntfrq(void) -+{ -+ u32 frq; -+ -+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); -+ -+ return frq; -+} -+ -+static void __secure cp15_write_cntfrq(u32 frq) -+{ -+ asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq)); -+} -+ - static inline void psci_set_state(int cpu, u8 state) - { - psci_state[cpu] = state; -@@ -63,6 +79,9 @@ void __secure psci_arch_cpu_entry(void) - - psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); - -+ /* write the saved cntfrq */ -+ cp15_write_cntfrq(cntfrq); -+ - /* reset magic in TAMP register */ - writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); - } -@@ -130,6 +149,9 @@ s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, - if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) - return ARM_PSCI_RET_ALREADY_ON; - -+ /* read and save cntfrq of current cpu to write on target cpu */ -+ cntfrq = cp15_read_cntfrq(); -+ - /* reset magic in TAMP register */ - if (readl(TAMP_BACKUP_MAGIC_NUMBER)) - writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); -diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c -index 9484645..7219af5 100644 ---- a/arch/arm/mach-stm32mp/pwr_regulator.c -+++ b/arch/arm/mach-stm32mp/pwr_regulator.c -@@ -6,8 +6,9 @@ - #include - #include - #include --#include - #include -+#include -+#include - #include - #include - -@@ -26,19 +27,28 @@ struct stm32mp_pwr_reg_info { - }; - - struct stm32mp_pwr_priv { -- struct regmap *regmap; -+ fdt_addr_t base; - }; - - static int stm32mp_pwr_write(struct udevice *dev, uint reg, - const uint8_t *buff, int len) - { -+#ifndef CONFIG_STM32MP1_TRUSTED - struct stm32mp_pwr_priv *priv = dev_get_priv(dev); -+#endif - u32 val = *(u32 *)buff; - - if (len != 4) - return -EINVAL; - -- return regmap_write(priv->regmap, STM32MP_PWR_CR3, val); -+#ifdef CONFIG_STM32MP1_TRUSTED -+ return stm32_smc_exec(STM32_SMC_PWR, STM32_SMC_REG_WRITE, -+ STM32MP_PWR_CR3, val); -+#else /* CONFIG_STM32MP1_TRUSTED */ -+ writel(val, priv->base + STM32MP_PWR_CR3); -+ -+ return 0; -+#endif /* CONFIG_STM32MP1_TRUSTED */ - } - - static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, -@@ -49,21 +59,18 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, - if (len != 4) - return -EINVAL; - -- return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff); -+ *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3); -+ -+ return 0; - } - - static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev) - { - struct stm32mp_pwr_priv *priv = dev_get_priv(dev); -- struct regmap *regmap; - -- regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR); -- if (IS_ERR(regmap)) { -- pr_err("%s: unable to find regmap (%ld)\n", __func__, -- PTR_ERR(regmap)); -- return PTR_ERR(regmap); -- } -- priv->regmap = regmap; -+ priv->base = dev_read_addr(dev); -+ if (priv->base == FDT_ADDR_T_NONE) -+ return -EINVAL; - - return 0; - } -diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c -index a3b0d6f..f4b4c3b 100644 ---- a/arch/arm/mach-stm32mp/spl.c -+++ b/arch/arm/mach-stm32mp/spl.c -@@ -38,6 +38,8 @@ u32 spl_boot_device(void) - return BOOT_DEVICE_NAND; - case BOOT_FLASH_NOR_QSPI: - return BOOT_DEVICE_SPI; -+ case BOOT_FLASH_SPINAND_1: -+ return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */ - } - - return BOOT_DEVICE_MMC1; -@@ -75,40 +77,47 @@ void spl_display_print(void) - } - #endif - -+__weak int board_vddcore_set(void) -+{ -+ return 0; -+} -+ - void board_init_f(ulong dummy) - { - struct udevice *dev; -- int ret; -+ int ret, clk, reset, pinctrl, power; - - arch_cpu_init(); - - ret = spl_early_init(); - if (ret) { -- debug("spl_early_init() failed: %d\n", ret); -+ debug("%s: spl_early_init() failed: %d\n", __func__, ret); - hang(); - } - -- ret = uclass_get_device(UCLASS_CLK, 0, &dev); -- if (ret) { -- debug("Clock init failed: %d\n", ret); -- return; -- } -+ clk = uclass_get_device(UCLASS_CLK, 0, &dev); -+ if (clk) -+ debug("%s: Clock init failed: %d\n", __func__, clk); - -- ret = uclass_get_device(UCLASS_RESET, 0, &dev); -- if (ret) { -- debug("Reset init failed: %d\n", ret); -- return; -- } -+ reset = uclass_get_device(UCLASS_RESET, 0, &dev); -+ if (reset) -+ debug("%s: Reset init failed: %d\n", __func__, reset); - -- ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); -- if (ret) { -- debug("%s: Cannot find pinctrl device\n", __func__); -- return; -- } -+ pinctrl = uclass_get_device(UCLASS_PINCTRL, 0, &dev); -+ if (pinctrl) -+ debug("%s: Cannot find pinctrl device: %d\n", -+ __func__, pinctrl); - - /* enable console uart printing */ - preloader_console_init(); - -+ /* change vddcore if needed after clock tree init */ -+ power = board_vddcore_set(); -+ -+ if (clk || reset || pinctrl || power) -+ printf("%s: probe failed clk=%d reset=%d pinctrl=%d power=%d\n", -+ __func__, clk, reset, pinctrl, power); -+ - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); -diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c -index 6070837..3e61ce4 100644 ---- a/arch/arm/mach-stm32mp/syscon.c -+++ b/arch/arm/mach-stm32mp/syscon.c -@@ -9,7 +9,6 @@ - #include - - static const struct udevice_id stm32mp_syscon_ids[] = { -- { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR }, - { .compatible = "st,stm32mp157-syscfg", - .data = STM32MP_SYSCON_SYSCFG }, - { } -diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts -index fdb08f2..b69f0da 100644 ---- a/arch/sandbox/dts/test.dts -+++ b/arch/sandbox/dts/test.dts -@@ -1,5 +1,8 @@ - /dts-v1/; - -+#include -+#include -+ - / { - model = "sandbox"; - compatible = "sandbox"; -@@ -13,6 +16,7 @@ - eth5 = ð_5; - gpio1 = &gpio_a; - gpio2 = &gpio_b; -+ gpio3 = &gpio_c; - i2c0 = "/i2c@0"; - mmc0 = "/mmc0"; - mmc1 = "/mmc1"; -@@ -86,11 +90,21 @@ - ping-expect = <0>; - ping-add = <0>; - u-boot,dm-pre-reloc; -- test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>, -+ test-gpios = <&gpio_a 1>, <&gpio_a 4>, -+ <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>, - <0>, <&gpio_a 12>; -- test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>, -- <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>, -- <&gpio_b 9 0xc 3 2 1>; -+ test2-gpios = <&gpio_a 1>, <&gpio_a 4>, -+ <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>, -+ <&gpio_b 7 GPIO_IN 3 2 1>, -+ <&gpio_b 8 GPIO_OUT 3 2 1>, -+ <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>; -+ test3-gpios = -+ <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>, -+ <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>, -+ <&gpio_c 2 GPIO_OUT>, -+ <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>, -+ <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>, -+ <&gpio_c 5 GPIO_IN>; - int-value = <1234>; - uint-value = <(-1234)>; - }; -@@ -274,20 +288,32 @@ - }; - }; - -- gpio_a: base-gpios { -- compatible = "sandbox,gpio"; -- gpio-controller; -- #gpio-cells = <1>; -- gpio-bank-name = "a"; -- sandbox,gpio-count = <20>; -- }; -+ pinctrl-gpio { -+ compatible = "sandbox,pinctrl-gpio"; -+ -+ gpio_a: base-gpios { -+ compatible = "sandbox,gpio"; -+ gpio-controller; -+ #gpio-cells = <1>; -+ gpio-bank-name = "a"; -+ sandbox,gpio-count = <20>; -+ }; - -- gpio_b: extra-gpios { -- compatible = "sandbox,gpio"; -- gpio-controller; -- #gpio-cells = <5>; -- gpio-bank-name = "b"; -- sandbox,gpio-count = <10>; -+ gpio_b: extra-gpios { -+ compatible = "sandbox,gpio"; -+ gpio-controller; -+ #gpio-cells = <5>; -+ gpio-bank-name = "b"; -+ sandbox,gpio-count = <10>; -+ }; -+ -+ gpio_c: pinmux-gpios { -+ compatible = "sandbox,gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-bank-name = "c"; -+ sandbox,gpio-count = <10>; -+ }; - }; - - i2c@0 { -@@ -851,6 +877,31 @@ - - pinctrl { - compatible = "sandbox,pinctrl"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios>; -+ -+ gpios: gpios { -+ gpio0 { -+ pins = "GPIO0"; -+ bias-pull-up; -+ input-disable; -+ }; -+ gpio1 { -+ pins = "GPIO1"; -+ output-high; -+ drive-open-drain; -+ }; -+ gpio2 { -+ pins = "GPIO2"; -+ bias-pull-down; -+ input-enable; -+ }; -+ gpio3 { -+ pins = "GPIO3"; -+ bias-disable; -+ }; -+ }; - }; - - hwspinlock@0 { -diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h -index de8ac37..df4ba4f 100644 ---- a/arch/sandbox/include/asm/gpio.h -+++ b/arch/sandbox/include/asm/gpio.h -@@ -43,43 +43,43 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); - int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); - - /** -- * Set or reset the simulated open drain mode of a GPIO (used only in sandbox -- * test code) -+ * Return the simulated direction of a GPIO (used only in sandbox test code) - * -- * @param gp GPIO number -- * @param value value to set (0 for enabled open drain mode, non-zero for -- * disabled) -- * @return -1 on error, 0 if ok -+ * @param dev device to use -+ * @param offset GPIO offset within bank -+ * @return -1 on error, 0 if GPIO is input, >0 if output - */ --int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value); -+int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); - - /** -- * Return the state of the simulated open drain mode of a GPIO (used only in -- * sandbox test code) -+ * Set the simulated direction of a GPIO (used only in sandbox test code) - * -- * @param gp GPIO number -- * @return -1 on error, 0 if GPIO is input, >0 if output -+ * @param dev device to use -+ * @param offset GPIO offset within bank -+ * @param output 0 to set as input, 1 to set as output -+ * @return -1 on error, 0 if ok - */ --int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset); -+int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, -+ int output); - - /** -- * Return the simulated direction of a GPIO (used only in sandbox test code) -+ * Return the simulated flags of a GPIO (used only in sandbox test code) - * - * @param dev device to use - * @param offset GPIO offset within bank -- * @return -1 on error, 0 if GPIO is input, >0 if output -+ * @return dir_flags: bitfield accesses by GPIOD_ defines - */ --int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); -+ulong sandbox_gpio_get_dir_flags(struct udevice *dev, unsigned int offset); - - /** -- * Set the simulated direction of a GPIO (used only in sandbox test code) -+ * Set the simulated flags of a GPIO (used only in sandbox test code) - * - * @param dev device to use - * @param offset GPIO offset within bank -- * @param output 0 to set as input, 1 to set as output -+ * @param flags dir_flags: bitfield accesses by GPIOD_ defines - * @return -1 on error, 0 if ok - */ --int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, -- int output); -+int sandbox_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong flags); - - #endif --- -2.7.4 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.10-stm32mp-r1-MACHINE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.10-stm32mp-r1-MACHINE.patch new file mode 100644 index 0000000..eb43b7e --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0001-ARM-v2020.10-stm32mp-r1-MACHINE.patch @@ -0,0 +1,1362 @@ +From 69911b18f94bb32fd3592745d5fdead473e76103 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Tue, 16 Mar 2021 08:16:59 +0100 +Subject: [PATCH 1/5] ARM v2020.10-stm32mp-r1 MACHINE + +Signed-off-by: Romuald JEANNE +--- + .gitignore | 3 + + CONTRIBUTING.md | 30 ++++++ + Makefile | 2 +- + arch/arc/include/asm/config.h | 2 - + arch/arm/include/asm/config.h | 1 - + arch/arm/include/asm/system.h | 3 + + arch/arm/lib/cache-cp15.c | 35 +++++-- + arch/arm/mach-stm32mp/Kconfig | 38 +++---- + arch/arm/mach-stm32mp/Makefile | 2 +- + arch/arm/mach-stm32mp/bsec.c | 10 ++ + arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 34 +++++++ + arch/arm/mach-stm32mp/cmd_stm32prog/Makefile | 8 +- + .../cmd_stm32prog/cmd_stm32prog.c | 25 ++--- + .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 66 +++++++++---- + .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 36 ++++++- + .../cmd_stm32prog/stm32prog_serial.c | 53 ++++------ + arch/arm/mach-stm32mp/config.mk | 2 +- + arch/arm/mach-stm32mp/cpu.c | 30 +++--- + arch/arm/mach-stm32mp/fdt.c | 11 ++- + arch/arm/mach-stm32mp/include/mach/stm32.h | 2 + + .../mach-stm32mp/include/mach/stm32mp1_smc.h | 50 +++++++--- + .../arm/mach-stm32mp/include/mach/stm32prog.h | 1 + + arch/arm/mach-stm32mp/pwr_regulator.c | 5 + + arch/arm/mach-stm32mp/spl.c | 5 +- + arch/m68k/include/asm/config.h | 1 - + arch/microblaze/include/asm/config.h | 2 - + arch/mips/include/asm/config.h | 1 - + arch/nds32/include/asm/config.h | 1 - + arch/powerpc/include/asm/config.h | 1 - + arch/riscv/include/asm/config.h | 1 - + arch/riscv/lib/fdt_fixup.c | 2 +- + arch/sandbox/dts/test.dts | 37 +++++++ + arch/sandbox/include/asm/scmi_test.h | 99 +++++++++++++++++++ + arch/sh/include/asm/config.h | 2 - + arch/x86/include/asm/config.h | 1 - + arch/xtensa/include/asm/config.h | 2 - + 36 files changed, 460 insertions(+), 144 deletions(-) + create mode 100644 CONTRIBUTING.md + create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig + create mode 100644 arch/sandbox/include/asm/scmi_test.h + +diff --git a/.gitignore b/.gitignore +index e66aa864da..a489ae7874 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -95,3 +95,6 @@ GTAGS + + # Python cache + __pycache__ ++ ++/oe-* ++bitbake-cookerdaemon.log +diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md +new file mode 100644 +index 0000000000..3d1bacd78a +--- /dev/null ++++ b/CONTRIBUTING.md +@@ -0,0 +1,30 @@ ++# Contributing guide ++ ++This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you. ++ ++This guide mainly focuses on the proper use of Git. ++ ++## 1. Issues ++ ++STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus). ++ ++## 2. Pull Requests ++ ++STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. ++ ++* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). ++* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. ++* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com). ++ ++Please note that: ++* The Corporate CLA will always take precedence over the Individual CLA. ++* One CLA submission is sufficient, for any project proposed by STMicroelectronics. ++ ++__How to proceed__ ++ ++* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version. ++* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted. ++ ++__Note__ ++ ++Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered. +diff --git a/Makefile b/Makefile +index d4736bb501..6bd0841c4b 100644 +--- a/Makefile ++++ b/Makefile +@@ -3,7 +3,7 @@ + VERSION = 2020 + PATCHLEVEL = 10 + SUBLEVEL = +-EXTRAVERSION = ++EXTRAVERSION = -stm32mp-r1 + NAME = + + # *DOCUMENTATION* +diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h +index d88c361488..46e94be141 100644 +--- a/arch/arc/include/asm/config.h ++++ b/arch/arc/include/asm/config.h +@@ -8,6 +8,4 @@ + + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + +-#define CONFIG_LMB +- + #endif /*__ASM_ARC_CONFIG_H_ */ +diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h +index bf692ce279..14860d89b6 100644 +--- a/arch/arm/include/asm/config.h ++++ b/arch/arm/include/asm/config.h +@@ -6,7 +6,6 @@ + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #if defined(CONFIG_ARCH_LS1021A) || \ +diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h +index ce552944b7..932f12af1c 100644 +--- a/arch/arm/include/asm/system.h ++++ b/arch/arm/include/asm/system.h +@@ -458,6 +458,7 @@ static inline void set_dacr(unsigned int val) + + /* options available for data cache on each page */ + enum dcache_option { ++ INVALID_ENTRY = 0, + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, + DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), + DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), +@@ -488,6 +489,7 @@ enum dcache_option { + * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate + */ + enum dcache_option { ++ INVALID_ENTRY = 0, + DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, + DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, +@@ -497,6 +499,7 @@ enum dcache_option { + #define TTB_SECT_AP (3 << 10) + /* options available for data cache on each page */ + enum dcache_option { ++ INVALID_ENTRY = 0, + DCACHE_OFF = 0x12, + DCACHE_WRITETHROUGH = 0x1a, + DCACHE_WRITEBACK = 0x1e, +diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c +index abd81d21c7..94e9b9c861 100644 +--- a/arch/arm/lib/cache-cp15.c ++++ b/arch/arm/lib/cache-cp15.c +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -96,27 +97,33 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + mmu_page_table_flush(startpt, stoppt); + } + +-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, +- enum dcache_option option) +-{ +- mmu_set_region_dcache_behaviour_phys(start, start, size, option); +-} +- + __weak void dram_bank_mmu_setup(int bank) + { + struct bd_info *bd = gd->bd; ++ struct lmb lmb; + int i; + + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + ++ /* ++ * don't allow cache on reserved memory tagged 'no-map' in DT ++ * => avoid speculative access to "secure" data ++ */ ++ lmb_init_and_reserve(&lmb, bd, (void *)gd->fdt_blob); ++ + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); +- i++) +- set_section_dcache(i, DCACHE_DEFAULT_OPTION); ++ i++) { ++ if (lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, ++ LMB_NOMAP)) ++ set_section_dcache(i, INVALID_ENTRY); ++ else ++ set_section_dcache(i, DCACHE_DEFAULT_OPTION); ++ } + } + + /* to activate the MMU we need to set up virtual memory: use 1M areas */ +@@ -313,6 +320,12 @@ int dcache_status(void) + { + return 0; /* always off */ + } ++ ++void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, ++ enum dcache_option option) ++{ ++} ++ + #else + void dcache_enable(void) + { +@@ -328,4 +341,10 @@ int dcache_status(void) + { + return (get_cr() & CR_C) != 0; + } ++ ++void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, ++ enum dcache_option option) ++{ ++ mmu_set_region_dcache_behaviour_phys(start, start, size, option); ++} + #endif +diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig +index 478fd2f17d..af0246d031 100644 +--- a/arch/arm/mach-stm32mp/Kconfig ++++ b/arch/arm/mach-stm32mp/Kconfig +@@ -56,6 +56,13 @@ config STM32MP15x + dual core A7 for STM32MP157/3, monocore for STM32MP151 + target all the STMicroelectronics board with SOC STM32MP1 family + ++config STM32MP15x_STM32IMAGE ++ bool "Support STM32 image for generated U-Boot image" ++ depends on STM32MP15x && TFABOOT ++ help ++ Support of STM32 image generation for SOC STM32MP15x ++ for TF-A boot when FIP container is not used ++ + choice + prompt "STM32MP15x board select" + optional +@@ -93,6 +100,19 @@ config SYS_TEXT_BASE + config NR_DRAM_BANKS + default 1 + ++config DDR_CACHEABLE_SIZE ++ hex "Size of the DDR marked cacheable in pre-reloc stage" ++ default 0x10000000 if TFABOOT ++ default 0x40000000 ++ help ++ Define the size of the DDR marked as cacheable in U-Boot ++ pre-reloc stage. ++ This option can be useful to avoid speculatif access ++ to secured area of DDR used by TF-A or OP-TEE before U-Boot ++ initialization. ++ The areas marked "no-map" in device tree should be located ++ before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. ++ + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 + hex "Partition on MMC2 to use to load U-Boot from" + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +@@ -108,23 +128,6 @@ config STM32_ETZPC + help + Say y to enable STM32 Extended TrustZone Protection + +-config CMD_STM32PROG +- bool "command stm32prog for STM32CudeProgrammer" +- select DFU +- select DFU_RAM +- select DFU_VIRT +- select PARTITION_TYPE_GUID +- imply CMD_GPT if MMC +- imply CMD_MTD if MTD +- imply DFU_MMC if MMC +- imply DFU_MTD if MTD +- help +- activate a specific command stm32prog for STM32MP soc family +- witch update the device with the tools STM32CubeProgrammer, +- using UART with STM32 protocol or USB with DFU protocol +- NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based +- on U-Boot DFU framework +- + config CMD_STM32KEY + bool "command stm32key to fuse public key hash" + default y +@@ -164,6 +167,7 @@ config DEBUG_UART_CLOCK + default 64000000 + endif + ++source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" + source "board/st/stm32mp1/Kconfig" + source "board/dhelectronics/dh_stm32mp1/Kconfig" + +diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile +index c8aa24d489..aa39867080 100644 +--- a/arch/arm/mach-stm32mp/Makefile ++++ b/arch/arm/mach-stm32mp/Makefile +@@ -11,7 +11,7 @@ obj-y += bsec.o + ifdef CONFIG_SPL_BUILD + obj-y += spl.o + else +-obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/ ++obj-y += cmd_stm32prog/ + obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o + obj-$(CONFIG_ARMV7_PSCI) += psci.o + obj-$(CONFIG_TFABOOT) += boot_params.o +diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c +index a9b9bd0902..3583368a91 100644 +--- a/arch/arm/mach-stm32mp/bsec.c ++++ b/arch/arm/mach-stm32mp/bsec.c +@@ -4,6 +4,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -486,6 +487,15 @@ static int stm32mp_bsec_probe(struct udevice *dev) + { + int otp; + struct stm32mp_bsec_platdata *plat; ++ struct clk_bulk clk_bulk; ++ int ret; ++ ++ ret = clk_get_bulk(dev, &clk_bulk); ++ if (!ret) { ++ ret = clk_enable_bulk(&clk_bulk); ++ if (ret) ++ return ret; ++ } + + /* + * update unlocked shadow for OTP cleared by the rom code +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +new file mode 100644 +index 0000000000..f4c0d18d4d +--- /dev/null ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +@@ -0,0 +1,34 @@ ++ ++config CMD_STM32PROG ++ bool "command stm32prog for STM32CudeProgrammer" ++ select DFU ++ select DFU_RAM ++ select DFU_VIRT ++ select PARTITION_TYPE_GUID ++ imply CMD_GPT if MMC ++ imply CMD_MTD if MTD ++ imply DFU_MMC if MMC ++ imply DFU_MTD if MTD ++ help ++ activate a specific command stm32prog for STM32MP soc family ++ witch update the device with the tools STM32CubeProgrammer ++ NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based ++ on U-Boot DFU framework ++ ++config CMD_STM32PROG_USB ++ bool "support stm32prog over USB" ++ depends on CMD_STM32PROG ++ default y ++ help ++ activate the command "stm32prog usb" for STM32MP soc family ++ witch update the device with the tools STM32CubeProgrammer, ++ using USB with DFU protocol ++ ++config CMD_STM32PROG_SERIAL ++ bool "support stm32prog over UART" ++ depends on CMD_STM32PROG ++ default y ++ help ++ activate the command "stm32prog serial" for STM32MP soc family ++ with the tools STM32CubeProgrammer using U-Boot serial device ++ and UART protocol. +\ No newline at end of file +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile +index 548a378921..b57e1bf870 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile +@@ -3,7 +3,7 @@ + # Copyright (C) 2020, STMicroelectronics - All Rights Reserved + # + +-obj-y += cmd_stm32prog.o +-obj-y += stm32prog.o +-obj-y += stm32prog_serial.o +-obj-y += stm32prog_usb.o ++obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog.o ++obj-$(CONFIG_CMD_STM32PROG) += stm32prog.o ++obj-$(CONFIG_CMD_STM32PROG_SERIAL) += stm32prog_serial.o ++obj-$(CONFIG_CMD_STM32PROG_USB) += stm32prog_usb.o +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +index 49dd25b28f..a20980a6ae 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +@@ -50,9 +50,9 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, + if (argc < 3 || argc > 5) + return CMD_RET_USAGE; + +- if (!strcmp(argv[1], "usb")) ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && !strcmp(argv[1], "usb")) + link = LINK_USB; +- else if (!strcmp(argv[1], "serial")) ++ else if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && !strcmp(argv[1], "serial")) + link = LINK_SERIAL; + + if (link == LINK_UNDEFINED) { +@@ -73,15 +73,16 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, + size = simple_strtoul(argv[4], NULL, 16); + + /* check STM32IMAGE presence */ +- if (size == 0 && +- !stm32prog_header_check((struct raw_header_s *)addr, &header)) { +- size = header.image_length + BL_HEADER_SIZE; +- +- /* uImage detected in STM32IMAGE, execute the script */ +- if (IMAGE_FORMAT_LEGACY == +- genimg_get_format((void *)(addr + BL_HEADER_SIZE))) +- return image_source_script(addr + BL_HEADER_SIZE, +- "script@1"); ++ if (size == 0) { ++ stm32prog_header_check((struct raw_header_s *)addr, &header); ++ if (header.type == HEADER_STM32IMAGE) { ++ size = header.image_length + BL_HEADER_SIZE; ++ ++ /* uImage detected in STM32IMAGE, execute the script */ ++ if (IMAGE_FORMAT_LEGACY == ++ genimg_get_format((void *)(addr + BL_HEADER_SIZE))) ++ return image_source_script(addr + BL_HEADER_SIZE, "script@1"); ++ } + } + + if (IS_ENABLED(CONFIG_DM_VIDEO)) +@@ -174,6 +175,7 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, + " = size of flashlayout\n" + ); + ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + bool stm32prog_get_tee_partitions(void) + { + if (stm32prog_data) +@@ -181,6 +183,7 @@ bool stm32prog_get_tee_partitions(void) + + return false; + } ++#endif + + bool stm32prog_get_fsbl_nor(void) + { +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +index ec3355d816..627bb52a11 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +@@ -59,8 +59,6 @@ static const efi_guid_t uuid_mmc[3] = { + ROOTFS_MMC2_UUID + }; + +-DECLARE_GLOBAL_DATA_PTR; +- + /* order of column in flash layout file */ + enum stm32prog_col_t { + COL_OPTION, +@@ -72,6 +70,16 @@ enum stm32prog_col_t { + COL_NB_STM32 + }; + ++#define FIP_TOC_HEADER_NAME 0xAA640001 ++ ++struct fip_toc_header { ++ u32 name; ++ u32 serial_number; ++ u64 flags; ++}; ++ ++DECLARE_GLOBAL_DATA_PTR; ++ + /* partition handling routines : CONFIG_CMD_MTDPARTS */ + int mtdparts_init(void); + int find_dev_and_part(const char *id, struct mtd_device **dev, +@@ -87,46 +95,57 @@ char *stm32prog_get_error(struct stm32prog_data *data) + return data->error; + } + +-u8 stm32prog_header_check(struct raw_header_s *raw_header, +- struct image_header_s *header) ++static bool stm32prog_is_fip_header(struct fip_toc_header *header) ++{ ++ return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number; ++} ++ ++void stm32prog_header_check(struct raw_header_s *raw_header, ++ struct image_header_s *header) + { + unsigned int i; + +- header->present = 0; ++ if (!raw_header || !header) { ++ pr_debug("%s:no header data\n", __func__); ++ return; ++ } ++ ++ header->type = HEADER_NONE; + header->image_checksum = 0x0; + header->image_length = 0x0; + +- if (!raw_header || !header) { +- pr_debug("%s:no header data\n", __func__); +- return -1; ++ if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { ++ header->type = HEADER_FIP; ++ return; + } ++ + if (raw_header->magic_number != + (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { + pr_debug("%s:invalid magic number : 0x%x\n", + __func__, raw_header->magic_number); +- return -2; ++ return; + } + /* only header v1.0 supported */ + if (raw_header->header_version != 0x00010000) { + pr_debug("%s:invalid header version : 0x%x\n", + __func__, raw_header->header_version); +- return -3; ++ return; + } + if (raw_header->reserved1 != 0x0 || raw_header->reserved2) { + pr_debug("%s:invalid reserved field\n", __func__); +- return -4; ++ return; + } + for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) { + if (raw_header->padding[i] != 0) { + pr_debug("%s:invalid padding field\n", __func__); +- return -5; ++ return; + } + } +- header->present = 1; ++ header->type = HEADER_STM32IMAGE; + header->image_checksum = le32_to_cpu(raw_header->image_checksum); + header->image_length = le32_to_cpu(raw_header->image_length); + +- return 0; ++ return; + } + + static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) +@@ -355,8 +374,8 @@ static int parse_flash_layout(struct stm32prog_data *data, + data->part_nb = 0; + + /* check if STM32image is detected */ +- if (!stm32prog_header_check((struct raw_header_s *)addr, +- &data->header)) { ++ stm32prog_header_check((struct raw_header_s *)addr, &data->header); ++ if (data->header.type == HEADER_STM32IMAGE) { + u32 checksum; + + addr = addr + BL_HEADER_SIZE; +@@ -768,9 +787,8 @@ static int init_device(struct stm32prog_data *data, + part_found = true; + } + ++ /* no partition for this device */ + if (!part_found) { +- stm32prog_err("%s (0x%x): Invalid partition", +- part->name, part->id); + pr_debug("\n"); + continue; + } +@@ -804,7 +822,9 @@ static int treat_partition_list(struct stm32prog_data *data) + INIT_LIST_HEAD(&data->dev[j].part_list); + } + ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + data->tee_detected = false; ++#endif + data->fsbl_nor_detected = false; + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; +@@ -858,10 +878,12 @@ static int treat_partition_list(struct stm32prog_data *data) + /* fallthrough */ + case STM32PROG_NAND: + case STM32PROG_SPI_NAND: ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + if (!data->tee_detected && + !strncmp(part->name, "tee", 3)) + data->tee_detected = true; + break; ++#endif + default: + break; + } +@@ -1410,7 +1432,7 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) + + if (part->target != STM32PROG_NAND && + part->target != STM32PROG_SPI_NAND) +- return -1; ++ return -EINVAL; + + dfu = dfu_get_entity(part->alt_id); + +@@ -1420,8 +1442,10 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) + ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); + if (ret) + return ret; +- if (stm32prog_header_check(&raw_header, &header)) +- return -1; ++ ++ stm32prog_header_check(&raw_header, &header); ++ if (header.type != HEADER_STM32IMAGE) ++ return -ENOENT; + + /* read header + payload */ + size = header.image_length + BL_HEADER_SIZE; +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +index bae4e91c01..fadcd1fa8f 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +@@ -37,8 +37,14 @@ enum stm32prog_link_t { + LINK_UNDEFINED, + }; + ++enum stm32prog_header_t { ++ HEADER_NONE, ++ HEADER_STM32IMAGE, ++ HEADER_FIP, ++}; ++ + struct image_header_s { +- bool present; ++ enum stm32prog_header_t type; + u32 image_checksum; + u32 image_length; + }; +@@ -115,7 +121,9 @@ struct stm32prog_data { + struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */ + int part_nb; /* nb of partition */ + struct stm32prog_part_t *part_array; /* array of partition */ ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + bool tee_detected; ++#endif + bool fsbl_nor_detected; + + /* command internal information */ +@@ -160,8 +168,8 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, + int stm32prog_pmic_start(struct stm32prog_data *data); + + /* generic part*/ +-u8 stm32prog_header_check(struct raw_header_s *raw_header, +- struct image_header_s *header); ++void stm32prog_header_check(struct raw_header_s *raw_header, ++ struct image_header_s *header); + int stm32prog_dfu_init(struct stm32prog_data *data); + void stm32prog_next_phase(struct stm32prog_data *data); + void stm32prog_do_reset(struct stm32prog_data *data); +@@ -177,9 +185,29 @@ char *stm32prog_get_error(struct stm32prog_data *data); + + /* Main function */ + int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size); ++void stm32prog_clean(struct stm32prog_data *data); ++ ++#ifdef CONFIG_CMD_STM32PROG_SERIAL + int stm32prog_serial_init(struct stm32prog_data *data, int link_dev); + bool stm32prog_serial_loop(struct stm32prog_data *data); ++#else ++static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) ++{ ++ return -ENOSYS; ++} ++static inline bool stm32prog_serial_loop(struct stm32prog_data *data) ++{ ++ return false; ++} ++#endif ++ ++#ifdef CONFIG_CMD_STM32PROG_USB + bool stm32prog_usb_loop(struct stm32prog_data *data, int dev); +-void stm32prog_clean(struct stm32prog_data *data); ++#else ++static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) ++{ ++ return false; ++} ++#endif + + #endif +diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +index 8aad4be467..0c3c215b3d 100644 +--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c ++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +@@ -186,36 +186,19 @@ static int stm32prog_read(struct stm32prog_data *data, u8 phase, u32 offset, + int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) + { + struct udevice *dev = NULL; +- int node; +- char alias[10]; +- const char *path; + struct dm_serial_ops *ops; + /* no parity, 8 bits, 1 stop */ + u32 serial_config = SERIAL_DEFAULT_CONFIG; + + down_serial_dev = NULL; + +- sprintf(alias, "serial%d", link_dev); +- path = fdt_get_alias(gd->fdt_blob, alias); +- if (!path) { +- pr_err("%s alias not found", alias); +- return -ENODEV; +- } +- node = fdt_path_offset(gd->fdt_blob, path); +- if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, +- &dev)) { +- down_serial_dev = dev; +- } else if (node > 0 && +- !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node), +- &dev, false)) { +- if (!device_probe(dev)) +- down_serial_dev = dev; +- } +- if (!down_serial_dev) { +- pr_err("%s = %s device not found", alias, path); ++ if (uclass_get_device_by_seq(UCLASS_SERIAL, link_dev, &dev)) { ++ pr_err("serial %d device not found\n", link_dev); + return -ENODEV; + } + ++ down_serial_dev = dev; ++ + /* force silent console on uart only when used */ + if (gd->cur_serial_dev == down_serial_dev) + gd->flags |= GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT; +@@ -225,11 +208,11 @@ int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) + ops = serial_get_ops(down_serial_dev); + + if (!ops) { +- pr_err("%s = %s missing ops", alias, path); ++ pr_err("serial %d = %s missing ops\n", link_dev, dev->name); + return -ENODEV; + } + if (!ops->setconfig) { +- pr_err("%s = %s missing setconfig", alias, path); ++ pr_err("serial %d = %s missing setconfig\n", link_dev, dev->name); + return -ENODEV; + } + +@@ -325,11 +308,10 @@ static u8 stm32prog_header(struct stm32prog_data *data) + /* force cleanup to avoid issue with previous read */ + dfu_transaction_cleanup(dfu_entity); + +- ret = stm32prog_header_check(data->header_data, +- &data->header); ++ stm32prog_header_check(data->header_data, &data->header); + +- /* no header : max size is partition size */ +- if (ret) { ++ /* no stm32 image header : max size is partition size */ ++ if (data->header.type != HEADER_STM32IMAGE) { + dfu_entity->get_medium_size(dfu_entity, &size); + data->header.image_length = size; + } +@@ -397,16 +379,15 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) + if (!dfu_entity) + return -ENODEV; + +- if (data->dfu_seq) { +- ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq); +- data->dfu_seq = 0; +- if (ret) { +- stm32prog_err("DFU flush failed [%d]", ret); +- return ret; +- } ++ ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq); ++ if (ret) { ++ stm32prog_err("DFU flush failed [%d]", ret); ++ return ret; + } ++ data->dfu_seq = 0; ++ + printf("\n received length = 0x%x\n", data->cursor); +- if (data->header.present) { ++ if (data->header.type == HEADER_STM32IMAGE) { + if (data->cursor != + (data->header.image_length + BL_HEADER_SIZE)) { + stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)", +@@ -806,7 +787,7 @@ static void download_command(struct stm32prog_data *data) + } + } + +- if (image_header->present) { ++ if (data->header.type == HEADER_STM32IMAGE) { + if (data->cursor <= BL_HEADER_SIZE) + goto end; + /* compute checksum on payload */ +diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk +index c30bf482f7..f7f5b77c41 100644 +--- a/arch/arm/mach-stm32mp/config.mk ++++ b/arch/arm/mach-stm32mp/config.mk +@@ -4,7 +4,7 @@ + # + + ifndef CONFIG_SPL +-INPUTS-y += u-boot.stm32 ++INPUTS-$(CONFIG_STM32MP15x_STM32IMAGE) += u-boot.stm32 + else + ifdef CONFIG_SPL_BUILD + INPUTS-y += u-boot-spl.stm32 +diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c +index f19e5c3f33..b81825a0bf 100644 +--- a/arch/arm/mach-stm32mp/cpu.c ++++ b/arch/arm/mach-stm32mp/cpu.c +@@ -219,18 +219,21 @@ static void early_enable_caches(void) + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + ++#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; ++#endif + + dcache_enable(); + + if (IS_ENABLED(CONFIG_SPL_BUILD)) + mmu_set_region_dcache_behaviour( +- ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), +- round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), ++ ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), ++ ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), + DCACHE_DEFAULT_OPTION); + else +- mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, ++ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, ++ CONFIG_DDR_CACHEABLE_SIZE, + DCACHE_DEFAULT_OPTION); + } + +@@ -260,7 +263,8 @@ int arch_cpu_init(void) + + boot_mode = get_bootmode(); + +- if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && ++ (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + #if defined(CONFIG_DEBUG_UART) && \ + !defined(CONFIG_TFABOOT) && \ +@@ -460,7 +464,6 @@ static void setup_boot_mode(void) + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); + struct udevice *dev; +- int alias; + + pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", + __func__, boot_ctx, boot_mode, instance, forced_mode); +@@ -470,17 +473,22 @@ static void setup_boot_mode(void) + break; + /* serial : search associated alias in devicetree */ + sprintf(cmd, "serial@%x", serial_addr[instance]); +- if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) +- break; +- if (fdtdec_get_alias_seq(gd->fdt_blob, "serial", +- dev_of_offset(dev), &alias)) ++ if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { ++ /* restore console on error */ ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) ++ gd->flags &= ~(GD_FLG_SILENT | ++ GD_FLG_DISABLE_CONSOLE); ++ printf("uart%d = %s not found in device tree!\n", ++ instance, cmd); + break; +- sprintf(cmd, "%d", alias); ++ } ++ sprintf(cmd, "%d", dev->seq); + env_set("boot_device", "serial"); + env_set("boot_instance", cmd); + + /* restore console on uart when not used */ +- if (gd->cur_serial_dev != dev) { ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && ++ (gd->cur_serial_dev != dev)) { + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + printf("serial boot with console enabled!\n"); +diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c +index 0de1d82291..cfaac8a416 100644 +--- a/arch/arm/mach-stm32mp/fdt.c ++++ b/arch/arm/mach-stm32mp/fdt.c +@@ -328,7 +328,16 @@ int ft_system_setup(void *blob, struct bd_info *bd) + "st,package", pkg, false); + } + +- if (!CONFIG_IS_ENABLED(OPTEE) || ++ /* ++ * TEMP: remove OP-TEE nodes in kernel device tree ++ * copied from U-Boot device tree by optee_copy_fdt_nodes ++ * when OP-TEE is not detected (probe failed) ++ * these OP-TEE nodes are present in -u-boot.dtsi ++ * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility ++ * when FIP is not used by TF-A ++ */ ++ if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && ++ CONFIG_IS_ENABLED(OPTEE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + +diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h +index 5fdb893b0e..af7ccdcc48 100644 +--- a/arch/arm/mach-stm32mp/include/mach/stm32.h ++++ b/arch/arm/mach-stm32mp/include/mach/stm32.h +@@ -91,8 +91,10 @@ enum boot_device { + + /* TAMP registers */ + #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) ++/* secure access */ + #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) + #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) ++/* non secure access */ + #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) + #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) + #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) +diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h +index 4ad14f963b..d72747ca31 100644 +--- a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h ++++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h +@@ -8,19 +8,53 @@ + + #include + ++/* SMC service generic return codes */ ++#define STM32_SMC_OK 0x00000000U ++#define STM32_SMC_NOT_SUPPORTED 0xFFFFFFFFU ++#define STM32_SMC_FAILED 0xFFFFFFFEU ++#define STM32_SMC_INVALID_PARAMS 0xFFFFFFFDU ++ + /* +- * SMC function IDs for STM32 Service queries ++ * SMC function IDs for STM32 Service queries. + * STM32 SMC services use the space between 0x82000000 and 0x8200FFFF + * like this is defined in SMC calling Convention by ARM +- * for SiP (silicon Partner) +- * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html ++ * for SiP (silicon Partner). ++ * https://developer.arm.com/docs/den0028/latest + */ +-#define STM32_SMC_VERSION 0x82000000 + + /* Secure Service access from Non-secure */ ++ ++/* ++ * SMC function STM32_SMC_PWR. ++ * ++ * Argument a0: (input) SMCC ID. ++ * (output) Status return code. ++ * Argument a1: (input) Service ID (STM32_SMC_REG_xxx). ++ * Argument a2: (input) Register offset or physical address. ++ * (output) Register read value, if applicable. ++ * Argument a3: (input) Register target value if applicable. ++ */ ++#define STM32_SMC_PWR 0x82001001 ++ ++/* ++ * SMC functions STM32_SMC_BSEC. ++ * ++ * Argument a0: (input) SMCC ID. ++ * (output) Status return code. ++ * Argument a1: (input) Service ID (STM32_SMC_READ_xxx/_PROG_xxx/_WRITE_xxx). ++ * (output) OTP read value, if applicable. ++ * Argument a2: (input) OTP index. ++ * Argument a3: (input) OTP value if applicable. ++ */ + #define STM32_SMC_BSEC 0x82001003 + +-/* Service for BSEC */ ++/* Service ID for STM32_SMC_PWR */ ++#define STM32_SMC_REG_READ 0x0 ++#define STM32_SMC_REG_WRITE 0x1 ++#define STM32_SMC_REG_SET 0x2 ++#define STM32_SMC_REG_CLEAR 0x3 ++ ++/* Service ID for STM32_SMC_BSEC */ + #define STM32_SMC_READ_SHADOW 0x01 + #define STM32_SMC_PROG_OTP 0x02 + #define STM32_SMC_WRITE_SHADOW 0x03 +@@ -29,12 +63,6 @@ + #define STM32_SMC_WRITE_ALL 0x06 + #define STM32_SMC_WRLOCK_OTP 0x07 + +-/* SMC error codes */ +-#define STM32_SMC_OK 0x0 +-#define STM32_SMC_NOT_SUPPORTED -1 +-#define STM32_SMC_FAILED -2 +-#define STM32_SMC_INVALID_PARAMS -3 +- + #define stm32_smc_exec(svc, op, data1, data2) \ + stm32_smc(svc, op, data1, data2, NULL) + +diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h +index c080b9cc42..241eec48d5 100644 +--- a/arch/arm/mach-stm32mp/include/mach/stm32prog.h ++++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h +@@ -11,6 +11,7 @@ int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len); + int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); + ++/* only needed for CONFIG_STM32MP15x_STM32IMAGE, prototype defined to avoid compilation issue */ + bool stm32prog_get_tee_partitions(void); + + bool stm32prog_get_fsbl_nor(void); +diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c +index 900dee4c38..1fbd180990 100644 +--- a/arch/arm/mach-stm32mp/pwr_regulator.c ++++ b/arch/arm/mach-stm32mp/pwr_regulator.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -41,6 +42,10 @@ static int stm32mp_pwr_write(struct udevice *dev, uint reg, + if (len != 4) + return -EINVAL; + ++ if (IS_ENABLED(CONFIG_TFABOOT)) ++ return stm32_smc_exec(STM32_SMC_PWR, STM32_SMC_REG_WRITE, ++ STM32MP_PWR_CR3, val); ++ + writel(val, priv->base + STM32MP_PWR_CR3); + + return 0; +diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c +index e84bdad7bf..66a634654e 100644 +--- a/arch/arm/mach-stm32mp/spl.c ++++ b/arch/arm/mach-stm32mp/spl.c +@@ -55,6 +55,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) + return MMCSD_MODE_RAW; + } + ++#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + int spl_mmc_boot_partition(const u32 boot_device) + { + switch (boot_device) { +@@ -66,6 +67,7 @@ int spl_mmc_boot_partition(const u32 boot_device) + return -EINVAL; + } + } ++#endif + + #ifdef CONFIG_SPL_DISPLAY_PRINT + void spl_display_print(void) +@@ -138,7 +140,8 @@ void board_init_f(ulong dummy) + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) +- mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, ++ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, ++ CONFIG_DDR_CACHEABLE_SIZE, + DCACHE_DEFAULT_OPTION); + } + +diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h +index c7363c0b51..b692cc9202 100644 +--- a/arch/m68k/include/asm/config.h ++++ b/arch/m68k/include/asm/config.h +@@ -8,7 +8,6 @@ + + #define CONFIG_NEEDS_MANUAL_RELOC + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #endif +diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h +index 1124272915..e65e3649fe 100644 +--- a/arch/microblaze/include/asm/config.h ++++ b/arch/microblaze/include/asm/config.h +@@ -6,8 +6,6 @@ + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ + +-#define CONFIG_LMB +- + #ifndef CONFIG_SPL_BUILD + #define CONFIG_NEEDS_MANUAL_RELOC + #endif +diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h +index 7ea443673a..221eb93d58 100644 +--- a/arch/mips/include/asm/config.h ++++ b/arch/mips/include/asm/config.h +@@ -6,7 +6,6 @@ + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #endif +diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h +index 8964a58f27..6c1cbce7ef 100644 +--- a/arch/nds32/include/asm/config.h ++++ b/arch/nds32/include/asm/config.h +@@ -7,6 +7,5 @@ + + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ +-#define CONFIG_LMB + + #endif +diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h +index c9c9964630..99b410dc9b 100644 +--- a/arch/powerpc/include/asm/config.h ++++ b/arch/powerpc/include/asm/config.h +@@ -18,7 +18,6 @@ + #define HWCONFIG_BUFFER_SIZE 256 + #endif + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #ifndef CONFIG_MAX_MEM_MAPPED +diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h +index 156cb94dc0..d911007537 100644 +--- a/arch/riscv/include/asm/config.h ++++ b/arch/riscv/include/asm/config.h +@@ -7,7 +7,6 @@ + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #endif +diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c +index 5b2420243f..d02062fd5b 100644 +--- a/arch/riscv/lib/fdt_fixup.c ++++ b/arch/riscv/lib/fdt_fixup.c +@@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) + pmp_mem.start = addr; + pmp_mem.end = addr + size - 1; + err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, +- &phandle); ++ &phandle, false); + if (err < 0 && err != -FDT_ERR_EXISTS) { + log_err("failed to add reserved memory: %d\n", err); + return err; +diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts +index 9f45c48e4e..7023f33a67 100644 +--- a/arch/sandbox/dts/test.dts ++++ b/arch/sandbox/dts/test.dts +@@ -356,6 +356,37 @@ + sandbox_firmware: sandbox-firmware { + compatible = "sandbox,firmware"; + }; ++ ++ sandbox-scmi-agent@0 { ++ compatible = "sandbox,scmi-agent"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk_scmi0: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ ++ reset_scmi0: protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <1>; ++ }; ++ }; ++ ++ sandbox-scmi-agent@1 { ++ compatible = "sandbox,scmi-agent"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk_scmi1: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ ++ protocol@10 { ++ reg = <0x10>; ++ }; ++ }; + }; + + pinctrl-gpio { +@@ -1036,6 +1067,12 @@ + compatible = "sandbox,virtio2"; + }; + ++ sandbox_scmi { ++ compatible = "sandbox,scmi-devices"; ++ clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>; ++ resets = <&reset_scmi0 3>; ++ }; ++ + pinctrl { + compatible = "sandbox,pinctrl"; + +diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h +new file mode 100644 +index 0000000000..3e8b0068fd +--- /dev/null ++++ b/arch/sandbox/include/asm/scmi_test.h +@@ -0,0 +1,99 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020, Linaro Limited ++ */ ++ ++#ifndef __SANDBOX_SCMI_TEST_H ++#define __SANDBOX_SCMI_TEST_H ++ ++struct udevice; ++struct sandbox_scmi_agent; ++struct sandbox_scmi_service; ++ ++/** ++ * struct sandbox_scmi_clk - Simulated clock exposed by SCMI ++ * @id: Identifier of the clock used in the SCMI protocol ++ * @enabled: Clock state: true if enabled, false if disabled ++ * @rate: Clock rate in Hertz ++ */ ++struct sandbox_scmi_clk { ++ uint id; ++ bool enabled; ++ ulong rate; ++}; ++ ++/** ++ * struct sandbox_scmi_reset - Simulated reset controller exposed by SCMI ++ * @asserted: Reset control state: true if asserted, false if desasserted ++ */ ++struct sandbox_scmi_reset { ++ uint id; ++ bool asserted; ++}; ++ ++/** ++ * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent ++ * @idx: Identifier for the SCMI agent, its index ++ * @clk: Simulated clocks ++ * @clk_count: Simulated clocks array size ++ * @clk: Simulated reset domains ++ * @clk_count: Simulated reset domains array size ++ */ ++struct sandbox_scmi_agent { ++ uint idx; ++ struct sandbox_scmi_clk *clk; ++ size_t clk_count; ++ struct sandbox_scmi_reset *reset; ++ size_t reset_count; ++}; ++ ++/** ++ * struct sandbox_scmi_service - Reference to simutaed SCMI agents/services ++ * @agent: Pointer to SCMI sandbox agent pointers array ++ * @agent_count: Number of emulated agents exposed in array @agent. ++ */ ++struct sandbox_scmi_service { ++ struct sandbox_scmi_agent **agent; ++ size_t agent_count; ++}; ++ ++/** ++ * struct sandbox_scmi_devices - Reference to devices probed through SCMI ++ * @clk: Array the clock devices ++ * @clk_count: Number of clock devices probed ++ * @reset: Array the reset controller devices ++ * @reset_count: Number of reset controller devices probed ++ */ ++struct sandbox_scmi_devices { ++ struct clk *clk; ++ size_t clk_count; ++ struct reset_ctl *reset; ++ size_t reset_count; ++}; ++ ++#ifdef CONFIG_SCMI_FIRMWARE ++/** ++ * sandbox_scmi_service_context - Get the simulated SCMI services context ++ * @return: Reference to backend simulated resources state ++ */ ++struct sandbox_scmi_service *sandbox_scmi_service_ctx(void); ++ ++/** ++ * sandbox_scmi_devices_get_ref - Get references to devices accessed through SCMI ++ * @dev: Reference to the test device used get test resources ++ * @return: Reference to the devices probed by the SCMI test ++ */ ++struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev); ++#else ++static inline struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) ++{ ++ return NULL; ++} ++ ++static inline ++struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev) ++{ ++ return NULL; ++} ++#endif /* CONFIG_SCMI_FIRMWARE */ ++#endif /* __SANDBOX_SCMI_TEST_H */ +diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h +index e1cd322152..406156dff5 100644 +--- a/arch/sh/include/asm/config.h ++++ b/arch/sh/include/asm/config.h +@@ -8,8 +8,6 @@ + + #include + +-#define CONFIG_LMB +- + /* Timer */ + #define CONFIG_SYS_TIMER_COUNTS_DOWN + #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h +index 7ea443673a..221eb93d58 100644 +--- a/arch/x86/include/asm/config.h ++++ b/arch/x86/include/asm/config.h +@@ -6,7 +6,6 @@ + #ifndef _ASM_CONFIG_H_ + #define _ASM_CONFIG_H_ + +-#define CONFIG_LMB + #define CONFIG_SYS_BOOT_RAMDISK_HIGH + + #endif +diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h +index 5a95fc93f7..a1096ab196 100644 +--- a/arch/xtensa/include/asm/config.h ++++ b/arch/xtensa/include/asm/config.h +@@ -9,8 +9,6 @@ + + #include + +-#define CONFIG_LMB +- + /* + * Make boot parameters available in the MMUv2 virtual memory layout by + * restricting used physical memory to the first 128MB. +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.01-stm32mp-r1-BOARD.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.01-stm32mp-r1-BOARD.patch deleted file mode 100644 index a3d5c11..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.01-stm32mp-r1-BOARD.patch +++ /dev/null @@ -1,3450 +0,0 @@ -From 44c04ad9a03583c1508393fcfd7a640b6521473a Mon Sep 17 00:00:00 2001 -From: Romuald JEANNE -Date: Fri, 5 Jun 2020 13:43:23 +0200 -Subject: [PATCH 2/5] ARM v2020.01-stm32mp-r1 BOARD - ---- - board/dhelectronics/dh_stm32mp1/Kconfig | 22 + - board/dhelectronics/dh_stm32mp1/MAINTAINERS | 7 + - board/dhelectronics/dh_stm32mp1/Makefile | 13 + - board/dhelectronics/dh_stm32mp1/board.c | 547 ++++++++++++++++++++++++ - board/st/common/Kconfig | 71 ++++ - board/st/common/MAINTAINERS | 6 + - board/st/common/Makefile | 11 + - board/st/common/cmd_stboard.c | 176 ++++++++ - board/st/common/stm32mp_dfu.c | 245 +++++++++++ - board/st/common/stm32mp_mtdparts.c | 167 ++++++++ - board/st/stm32mp1/Kconfig | 20 +- - board/st/stm32mp1/MAINTAINERS | 1 - - board/st/stm32mp1/Makefile | 1 - - board/st/stm32mp1/README | 504 +--------------------- - board/st/stm32mp1/board.c | 57 ++- - board/st/stm32mp1/cmd_stboard.c | 145 ------- - board/st/stm32mp1/stm32mp1.c | 426 +++++++------------ - board/sunxi/board.c | 2 +- - doc/board/index.rst | 1 + - doc/board/st/index.rst | 9 + - doc/board/st/stm32mp1.rst | 624 ++++++++++++++++++++++++++++ - 21 files changed, 2103 insertions(+), 952 deletions(-) - create mode 100644 board/dhelectronics/dh_stm32mp1/Kconfig - create mode 100644 board/dhelectronics/dh_stm32mp1/MAINTAINERS - create mode 100644 board/dhelectronics/dh_stm32mp1/Makefile - create mode 100644 board/dhelectronics/dh_stm32mp1/board.c - create mode 100644 board/st/common/Kconfig - create mode 100644 board/st/common/MAINTAINERS - create mode 100644 board/st/common/Makefile - create mode 100644 board/st/common/cmd_stboard.c - create mode 100644 board/st/common/stm32mp_dfu.c - create mode 100644 board/st/common/stm32mp_mtdparts.c - delete mode 100644 board/st/stm32mp1/cmd_stboard.c - create mode 100644 doc/board/st/index.rst - create mode 100644 doc/board/st/stm32mp1.rst - -diff --git a/board/dhelectronics/dh_stm32mp1/Kconfig b/board/dhelectronics/dh_stm32mp1/Kconfig -new file mode 100644 -index 0000000..69cc48f ---- /dev/null -+++ b/board/dhelectronics/dh_stm32mp1/Kconfig -@@ -0,0 +1,22 @@ -+if TARGET_DH_STM32MP1_PDK2 -+ -+config SYS_BOARD -+ default "dh_stm32mp1" -+ -+config SYS_VENDOR -+ default "dhelectronics" -+ -+config SYS_CONFIG_NAME -+ default "stm32mp1" -+ -+config ENV_SECT_SIZE -+ default 0x10000 if ENV_IS_IN_SPI_FLASH -+ -+config ENV_OFFSET -+ default 0x1E0000 if ENV_IS_IN_SPI_FLASH -+ -+config ENV_OFFSET_REDUND -+ default 0x1F0000 if ENV_IS_IN_SPI_FLASH -+ -+source "board/st/common/Kconfig" -+endif -diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS -new file mode 100644 -index 0000000..1511ecb ---- /dev/null -+++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS -@@ -0,0 +1,7 @@ -+DH_STM32MP1_PDK2 BOARD -+M: Marek Vasut -+S: Maintained -+F: arch/arm/dts/stm32mp15xx-dhcom* -+F: board/dhelectronics/dh_stm32mp1/ -+F: configs/stm32mp15_dhcom_basic_defconfig -+F: include/configs/stm32mp1.h -diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile -new file mode 100644 -index 0000000..e8f218d ---- /dev/null -+++ b/board/dhelectronics/dh_stm32mp1/Makefile -@@ -0,0 +1,13 @@ -+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+# -+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved -+# -+ -+ifdef CONFIG_SPL_BUILD -+obj-y += ../../st/stm32mp1/spl.o -+endif -+ -+obj-y += ../../st/stm32mp1/board.o board.o -+ -+obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o -+obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o -diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c -new file mode 100644 -index 0000000..53325e8 ---- /dev/null -+++ b/board/dhelectronics/dh_stm32mp1/board.c -@@ -0,0 +1,547 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* SYSCFG registers */ -+#define SYSCFG_BOOTR 0x00 -+#define SYSCFG_PMCSETR 0x04 -+#define SYSCFG_IOCTRLSETR 0x18 -+#define SYSCFG_ICNR 0x1C -+#define SYSCFG_CMPCR 0x20 -+#define SYSCFG_CMPENSETR 0x24 -+#define SYSCFG_PMCCLRR 0x44 -+ -+#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) -+#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 -+ -+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) -+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) -+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) -+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) -+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) -+ -+#define SYSCFG_CMPCR_SW_CTRL BIT(1) -+#define SYSCFG_CMPCR_READY BIT(8) -+ -+#define SYSCFG_CMPENSETR_MPU_EN BIT(0) -+ -+#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) -+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) -+ -+#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) -+ -+#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) -+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 -+#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) -+#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) -+ -+/* -+ * Get a global data pointer -+ */ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int setup_mac_address(void) -+{ -+ struct udevice *dev; -+ ofnode eeprom; -+ unsigned char enetaddr[6]; -+ int ret; -+ -+ ret = eth_env_get_enetaddr("ethaddr", enetaddr); -+ if (ret) /* ethaddr is already set */ -+ return 0; -+ -+ eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); -+ if (!ofnode_valid(eeprom)) { -+ printf("Invalid hardware path to EEPROM!\n"); -+ return -ENODEV; -+ } -+ -+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); -+ if (ret) { -+ printf("Cannot find EEPROM!\n"); -+ return ret; -+ } -+ -+ ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6); -+ if (ret) { -+ printf("Error reading configuration EEPROM!\n"); -+ return ret; -+ } -+ -+ if (is_valid_ethaddr(enetaddr)) -+ eth_env_set_enetaddr("ethaddr", enetaddr); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ char *mode; -+ const char *fdt_compat; -+ int fdt_compat_len; -+ -+ if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) -+ mode = "trusted"; -+ else -+ mode = "basic"; -+ -+ printf("Board: stm32mp1 in %s mode", mode); -+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", -+ &fdt_compat_len); -+ if (fdt_compat && fdt_compat_len) -+ printf(" (%s)", fdt_compat); -+ puts("\n"); -+ -+ return 0; -+} -+ -+static void board_key_check(void) -+{ -+#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG) -+ ofnode node; -+ struct gpio_desc gpio; -+ enum forced_boot_mode boot_mode = BOOT_NORMAL; -+ -+ node = ofnode_path("/config"); -+ if (!ofnode_valid(node)) { -+ debug("%s: no /config node?\n", __func__); -+ return; -+ } -+#ifdef CONFIG_FASTBOOT -+ if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, -+ &gpio, GPIOD_IS_IN)) { -+ debug("%s: could not find a /config/st,fastboot-gpios\n", -+ __func__); -+ } else { -+ if (dm_gpio_get_value(&gpio)) { -+ puts("Fastboot key pressed, "); -+ boot_mode = BOOT_FASTBOOT; -+ } -+ -+ dm_gpio_free(NULL, &gpio); -+ } -+#endif -+#ifdef CONFIG_CMD_STM32PROG -+ if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, -+ &gpio, GPIOD_IS_IN)) { -+ debug("%s: could not find a /config/st,stm32prog-gpios\n", -+ __func__); -+ } else { -+ if (dm_gpio_get_value(&gpio)) { -+ puts("STM32Programmer key pressed, "); -+ boot_mode = BOOT_STM32PROG; -+ } -+ dm_gpio_free(NULL, &gpio); -+ } -+#endif -+ -+ if (boot_mode != BOOT_NORMAL) { -+ puts("entering download mode...\n"); -+ clrsetbits_le32(TAMP_BOOT_CONTEXT, -+ TAMP_BOOT_FORCED_MASK, -+ boot_mode); -+ } -+#endif -+} -+ -+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -+ -+#include -+int g_dnl_board_usb_cable_connected(void) -+{ -+ struct udevice *dwc2_udc_otg; -+ int ret; -+ -+ ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC, -+ DM_GET_DRIVER(dwc2_udc_otg), -+ &dwc2_udc_otg); -+ if (!ret) -+ debug("dwc2_udc_otg init failed\n"); -+ -+ return dwc2_udc_B_session_valid(dwc2_udc_otg); -+} -+ -+#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 -+#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb -+ -+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -+{ -+ if (!strcmp(name, "usb_dnl_dfu")) -+ put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); -+ else if (!strcmp(name, "usb_dnl_fastboot")) -+ put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, -+ &dev->idProduct); -+ else -+ put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); -+ -+ return 0; -+} -+ -+#endif /* CONFIG_USB_GADGET */ -+ -+#ifdef CONFIG_LED -+static int get_led(struct udevice **dev, char *led_string) -+{ -+ char *led_name; -+ int ret; -+ -+ led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); -+ if (!led_name) { -+ pr_debug("%s: could not find %s config string\n", -+ __func__, led_string); -+ return -ENOENT; -+ } -+ ret = led_get_by_label(led_name, dev); -+ if (ret) { -+ debug("%s: get=%d\n", __func__, ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int setup_led(enum led_state_t cmd) -+{ -+ struct udevice *dev; -+ int ret; -+ -+ ret = get_led(&dev, "u-boot,boot-led"); -+ if (ret) -+ return ret; -+ -+ ret = led_set_state(dev, cmd); -+ return ret; -+} -+#endif -+ -+static void __maybe_unused led_error_blink(u32 nb_blink) -+{ -+#ifdef CONFIG_LED -+ int ret; -+ struct udevice *led; -+ u32 i; -+#endif -+ -+ if (!nb_blink) -+ return; -+ -+#ifdef CONFIG_LED -+ ret = get_led(&led, "u-boot,error-led"); -+ if (!ret) { -+ /* make u-boot,error-led blinking */ -+ /* if U32_MAX and 125ms interval, for 17.02 years */ -+ for (i = 0; i < 2 * nb_blink; i++) { -+ led_set_state(led, LEDST_TOGGLE); -+ mdelay(125); -+ WATCHDOG_RESET(); -+ } -+ } -+#endif -+ -+ /* infinite: the boot process must be stopped */ -+ if (nb_blink == U32_MAX) -+ hang(); -+} -+ -+static void sysconf_init(void) -+{ -+#ifndef CONFIG_STM32MP1_TRUSTED -+ u8 *syscfg; -+#ifdef CONFIG_DM_REGULATOR -+ struct udevice *pwr_dev; -+ struct udevice *pwr_reg; -+ struct udevice *dev; -+ int ret; -+ u32 otp = 0; -+#endif -+ u32 bootr; -+ -+ syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); -+ -+ /* interconnect update : select master using the port 1 */ -+ /* LTDC = AXI_M9 */ -+ /* GPU = AXI_M8 */ -+ /* today information is hardcoded in U-Boot */ -+ writel(BIT(9), syscfg + SYSCFG_ICNR); -+ -+ /* disable Pull-Down for boot pin connected to VDD */ -+ bootr = readl(syscfg + SYSCFG_BOOTR); -+ bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); -+ bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; -+ writel(bootr, syscfg + SYSCFG_BOOTR); -+ -+#ifdef CONFIG_DM_REGULATOR -+ /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI -+ * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. -+ * The customer will have to disable this for low frequencies -+ * or if AFMUX is selected but the function not used, typically for -+ * TRACE. Otherwise, impact on power consumption. -+ * -+ * WARNING: -+ * enabling High Speed mode while VDD>2.7V -+ * with the OTP product_below_2v5 (OTP 18, BIT 13) -+ * erroneously set to 1 can damage the IC! -+ * => U-Boot set the register only if VDD < 2.7V (in DT) -+ * but this value need to be consistent with board design -+ */ -+ ret = uclass_get_device_by_driver(UCLASS_PMIC, -+ DM_GET_DRIVER(stm32mp_pwr_pmic), -+ &pwr_dev); -+ if (!ret) { -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stm32mp_bsec), -+ &dev); -+ if (ret) { -+ pr_err("Can't find stm32mp_bsec driver\n"); -+ return; -+ } -+ -+ ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); -+ if (ret > 0) -+ otp = otp & BIT(13); -+ -+ /* get VDD = vdd-supply */ -+ ret = device_get_supply_regulator(pwr_dev, "vdd-supply", -+ &pwr_reg); -+ -+ /* check if VDD is Low Voltage */ -+ if (!ret) { -+ if (regulator_get_value(pwr_reg) < 2700000) { -+ writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | -+ SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | -+ SYSCFG_IOCTRLSETR_HSLVEN_ETH | -+ SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | -+ SYSCFG_IOCTRLSETR_HSLVEN_SPI, -+ syscfg + SYSCFG_IOCTRLSETR); -+ -+ if (!otp) -+ pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); -+ } else { -+ if (otp) -+ pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); -+ } -+ } else { -+ debug("VDD unknown"); -+ } -+ } -+#endif -+ -+ /* activate automatic I/O compensation -+ * warning: need to ensure CSI enabled and ready in clock driver -+ */ -+ writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); -+ -+ while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) -+ ; -+ clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); -+#endif -+} -+ -+/* board dependent setup after realloc */ -+int board_init(void) -+{ -+ struct udevice *dev; -+ -+ /* address of boot parameters */ -+ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; -+ -+ /* probe all PINCTRL for hog */ -+ for (uclass_first_device(UCLASS_PINCTRL, &dev); -+ dev; -+ uclass_next_device(&dev)) { -+ pr_debug("probe pincontrol = %s\n", dev->name); -+ } -+ -+ board_key_check(); -+ -+#ifdef CONFIG_DM_REGULATOR -+ regulators_enable_boot_on(_DEBUG); -+#endif -+ -+ sysconf_init(); -+ -+ if (CONFIG_IS_ENABLED(LED)) -+ led_default_state(); -+ -+ return 0; -+} -+ -+int board_late_init(void) -+{ -+ char *boot_device; -+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -+ const void *fdt_compat; -+ int fdt_compat_len; -+ -+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", -+ &fdt_compat_len); -+ if (fdt_compat && fdt_compat_len) { -+ if (strncmp(fdt_compat, "st,", 3) != 0) -+ env_set("board_name", fdt_compat); -+ else -+ env_set("board_name", fdt_compat + 3); -+ } -+#endif -+ -+ /* Check the boot-source to disable bootdelay */ -+ boot_device = env_get("boot_device"); -+ if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) -+ env_set("bootdelay", "0"); -+ -+ return 0; -+} -+ -+void board_quiesce_devices(void) -+{ -+#ifdef CONFIG_LED -+ setup_led(LEDST_OFF); -+#endif -+} -+ -+/* eth init function : weak called in eqos driver */ -+int board_interface_eth_init(struct udevice *dev, -+ phy_interface_t interface_type) -+{ -+ u8 *syscfg; -+ u32 value; -+ bool eth_clk_sel_reg = false; -+ bool eth_ref_clk_sel_reg = false; -+ -+ /* Gigabit Ethernet 125MHz clock selection. */ -+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); -+ -+ /* Ethernet 50Mhz RMII clock selection */ -+ eth_ref_clk_sel_reg = -+ dev_read_bool(dev, "st,eth_ref_clk_sel"); -+ -+ syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); -+ -+ if (!syscfg) -+ return -ENODEV; -+ -+ switch (interface_type) { -+ case PHY_INTERFACE_MODE_MII: -+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | -+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL; -+ debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ if (eth_clk_sel_reg) -+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | -+ SYSCFG_PMCSETR_ETH_CLK_SEL; -+ else -+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; -+ debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ if (eth_ref_clk_sel_reg) -+ value = SYSCFG_PMCSETR_ETH_SEL_RMII | -+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL; -+ else -+ value = SYSCFG_PMCSETR_ETH_SEL_RMII; -+ debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ if (eth_clk_sel_reg) -+ value = SYSCFG_PMCSETR_ETH_SEL_RGMII | -+ SYSCFG_PMCSETR_ETH_CLK_SEL; -+ else -+ value = SYSCFG_PMCSETR_ETH_SEL_RGMII; -+ debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); -+ break; -+ default: -+ debug("%s: Do not manage %d interface\n", -+ __func__, interface_type); -+ /* Do not manage others interfaces */ -+ return -EINVAL; -+ } -+ -+ /* clear and set ETH configuration bits */ -+ writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | -+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, -+ syscfg + SYSCFG_PMCCLRR); -+ writel(value, syscfg + SYSCFG_PMCSETR); -+ -+ return 0; -+} -+ -+enum env_location env_get_location(enum env_operation op, int prio) -+{ -+ if (prio) -+ return ENVL_UNKNOWN; -+ -+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -+ return ENVL_SPI_FLASH; -+#else -+ return ENVL_NOWHERE; -+#endif -+} -+ -+#if defined(CONFIG_OF_BOARD_SETUP) -+int ft_board_setup(void *blob, bd_t *bd) -+{ -+ return 0; -+} -+#endif -+ -+static void board_copro_image_process(ulong fw_image, size_t fw_size) -+{ -+ int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ -+ -+ if (!rproc_is_initialized()) -+ if (rproc_init()) { -+ printf("Remote Processor %d initialization failed\n", -+ id); -+ return; -+ } -+ -+ ret = rproc_load(id, fw_image, fw_size); -+ printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", -+ id, fw_image, fw_size, ret ? " Failed!" : " Success!"); -+ -+ if (!ret) { -+ rproc_start(id); -+ env_set("copro_state", "booted"); -+ } -+} -+ -+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); -diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig -new file mode 100644 -index 0000000..750dbb6 ---- /dev/null -+++ b/board/st/common/Kconfig -@@ -0,0 +1,71 @@ -+config CMD_STBOARD -+ bool "stboard - command for OTP board information" -+ depends on ARCH_STM32MP -+ default y if TARGET_ST_STM32MP15x -+ help -+ This compile the stboard command to -+ read and write the board in the OTP. -+ -+config MTDPARTS_NAND0_BOOT -+ string "mtd boot partitions for nand0" -+ default "2m(fsbl),2m(ssbl1),2m(ssbl2)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the partitions of nand0 used to build mtparts dynamically -+ for boot from nand0. -+ Each partition need to be aligned with the device erase block size, -+ 512KB is the max size for the NAND supported by stm32mp1 platform. -+ -+config MTDPARTS_NAND0_TEE -+ string "mtd tee partitions for nand0" -+ default "512k(teeh),512k(teed),512k(teex)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the tee partitions added in mtparts dynamically -+ when tee is supported with boot from nand0. -+ Each partition need to be aligned with the device erase block size, -+ 512KB is the max size for the NAND supported by stm32mp1 platform. -+ -+config MTDPARTS_NOR0_BOOT -+ string "mtd boot partitions for nor0" -+ default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the partitions of nand0 used to build mtparts dynamically -+ for boot from nor0. -+ Each partition need to be aligned with the device erase block size, -+ with 256KB we support all the NOR. -+ U-Boot env partition (512kB) use 2 erase block for redundancy. -+ -+config MTDPARTS_NOR0_TEE -+ string "mtd tee partitions for nor0" -+ default "256k(teeh),512k(teed),256k(teex)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the tee partitions added in mtparts dynamically -+ when tee is supported with boot from nor0. -+ -+config MTDPARTS_SPINAND0_BOOT -+ string "mtd boot partitions for spi-nand0" -+ default "2m(fsbl),2m(ssbl1),2m(ssbl2)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the partitions of nand0 used to build mtparts dynamically -+ for boot from spi-nand0, -+ 512KB is the max size for the NAND supported by stm32mp1 platform. -+ -+config MTDPARTS_SPINAND0_TEE -+ string "mtd tee partitions for spi-nand0" -+ default "512k(teeh),512k(teed),512k(teex)" -+ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP -+ help -+ This define the tee partitions added in mtparts dynamically -+ when tee is supported with boot from spi-nand0, -+ 512KB is the max size for the NAND supported by stm32mp1 platform. -+ -+config DFU_ALT_RAM0 -+ string "dfu for ram0" -+ default "uImage ram 0xc2000000 0x2000000;devicetree.dtb ram 0xc4000000 0x100000;uramdisk.image.gz ram 0xc4400000 0x10000000" -+ depends on ARCH_STM32MP && SET_DFU_ALT_INFO -+ help -+ This defines the partitions of ram used to build dfu dynamically. -diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS -new file mode 100644 -index 0000000..3b02f4a ---- /dev/null -+++ b/board/st/common/MAINTAINERS -@@ -0,0 +1,6 @@ -+ST BOARDS -+M: Patrick Delaunay -+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) -+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git -+S: Maintained -+F: board/st/common/ -diff --git a/board/st/common/Makefile b/board/st/common/Makefile -new file mode 100644 -index 0000000..aa030bac ---- /dev/null -+++ b/board/st/common/Makefile -@@ -0,0 +1,11 @@ -+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+# -+# Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+# -+ -+obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o -+ -+ifeq ($(CONFIG_ARCH_STM32MP),y) -+obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o -+obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o -+endif -diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c -new file mode 100644 -index 0000000..3ead1ed ---- /dev/null -+++ b/board/st/common/cmd_stboard.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved -+ */ -+ -+#ifndef CONFIG_SPL_BUILD -+#include -+#include -+#include -+#include -+#include -+ -+static bool check_stboard(u16 board) -+{ -+ unsigned int i; -+ const u16 st_board_id[] = { -+ 0x1272, -+ 0x1263, -+ 0x1264, -+ 0x1298, -+ 0x1341, -+ 0x1497, -+ }; -+ -+ for (i = 0; i < ARRAY_SIZE(st_board_id); i++) -+ if (board == st_board_id[i]) -+ return true; -+ -+ return false; -+} -+ -+static void display_stboard(u32 otp) -+{ -+ printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n", -+ otp >> 16, -+ (otp >> 12) & 0xF, -+ (otp >> 4) & 0xF, -+ ((otp >> 8) & 0xF) - 1 + 'A', -+ otp & 0xF); -+} -+ -+static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, -+ char * const argv[]) -+{ -+ int ret; -+ u32 otp, lock; -+ u8 revision; -+ unsigned long board, var_cpn, var_fg, bom; -+ struct udevice *dev; -+ int confirmed = argc == 7 && !strcmp(argv[1], "-y"); -+ -+ argc -= 1 + confirmed; -+ argv += 1 + confirmed; -+ -+ if (argc != 0 && argc != 5) -+ return CMD_RET_USAGE; -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stm32mp_bsec), -+ &dev); -+ -+ ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), -+ &otp, sizeof(otp)); -+ -+ if (ret < 0) { -+ puts("OTP read error"); -+ return CMD_RET_FAILURE; -+ } -+ -+ ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), -+ &lock, sizeof(lock)); -+ if (ret < 0) { -+ puts("LOCK read error"); -+ return CMD_RET_FAILURE; -+ } -+ -+ if (argc == 0) { -+ if (!otp) -+ puts("Board : OTP board FREE\n"); -+ else -+ display_stboard(otp); -+ printf(" OTP %d %s locked !\n", BSEC_OTP_BOARD, -+ lock == 1 ? "" : "NOT"); -+ return CMD_RET_SUCCESS; -+ } -+ -+ if (otp) { -+ display_stboard(otp); -+ printf("ERROR: OTP board not FREE\n"); -+ return CMD_RET_FAILURE; -+ } -+ -+ if (strict_strtoul(argv[0], 16, &board) < 0 || -+ board == 0 || board > 0xFFFF) { -+ printf("argument %d invalid: %s\n", 1, argv[0]); -+ return CMD_RET_USAGE; -+ } -+ -+ if (strict_strtoul(argv[1], 10, &var_cpn) < 0 || -+ var_cpn == 0 || var_cpn > 15) { -+ printf("argument %d invalid: %s\n", 2, argv[1]); -+ return CMD_RET_USAGE; -+ } -+ -+ revision = argv[2][0] - 'A' + 1; -+ if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) { -+ printf("argument %d invalid: %s\n", 3, argv[2]); -+ return CMD_RET_USAGE; -+ } -+ -+ if (strict_strtoul(argv[3], 10, &var_fg) < 0 || -+ var_fg > 15) { -+ printf("argument %d invalid: %s\n", 4, argv[3]); -+ return CMD_RET_USAGE; -+ } -+ -+ if (strict_strtoul(argv[4], 10, &bom) < 0 || -+ bom == 0 || bom > 15) { -+ printf("argument %d invalid: %s\n", 4, argv[3]); -+ return CMD_RET_USAGE; -+ } -+ -+ otp = (board << 16) | (var_cpn << 12) | (revision << 8) | -+ (var_fg << 4) | bom; -+ display_stboard(otp); -+ printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp); -+ -+ if (!check_stboard((u16)board)) { -+ printf("Unknown board MB%04x\n", (u16)board); -+ return CMD_RET_FAILURE; -+ } -+ if (!confirmed) { -+ printf("Warning: Programming BOARD in OTP is irreversible!\n"); -+ printf("Really perform this OTP programming? \n"); -+ -+ if (!confirm_yesno()) { -+ puts("BOARD programming aborted\n"); -+ return CMD_RET_FAILURE; -+ } -+ } -+ -+ ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), -+ &otp, sizeof(otp)); -+ -+ if (ret < 0) { -+ puts("BOARD programming error\n"); -+ return CMD_RET_FAILURE; -+ } -+ -+ /* write persistent lock */ -+ otp = 1; -+ ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), -+ &otp, sizeof(otp)); -+ if (ret < 0) { -+ puts("BOARD lock error\n"); -+ return CMD_RET_FAILURE; -+ } -+ -+ puts("BOARD programming done\n"); -+ -+ return CMD_RET_SUCCESS; -+} -+ -+U_BOOT_CMD(stboard, 7, 0, do_stboard, -+ "read/write board reference in OTP", -+ "\n" -+ " Print current board information\n" -+ "stboard [-y] \n" -+ " Write board information\n" -+ " - Board: xxxx, example 1264 for MB1264\n" -+ " - VarCPN: 1...15\n" -+ " - Revision: A...O\n" -+ " - VarFG: 0...15\n" -+ " - BOM: 1...15\n"); -+ -+#endif -diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c -new file mode 100644 -index 0000000..3bd005b ---- /dev/null -+++ b/board/st/common/stm32mp_dfu.c -@@ -0,0 +1,245 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DFU_ALT_BUF_LEN SZ_1K -+ -+static void board_get_alt_info_mmc(struct udevice *dev, char *buf) -+{ -+ disk_partition_t info; -+ int p, len, devnum; -+ bool first = true; -+ const char *name; -+ struct mmc *mmc; -+ struct blk_desc *desc; -+ -+ mmc = mmc_get_mmc_dev(dev); -+ if (!mmc) -+ return; -+ -+ if (mmc_init(mmc)) -+ return; -+ -+ desc = mmc_get_blk_desc(mmc); -+ if (!desc) -+ return; -+ -+ name = blk_get_if_type_name(desc->if_type); -+ devnum = desc->devnum; -+ len = strlen(buf); -+ -+ if (buf[0] != '\0') -+ len += snprintf(buf + len, -+ DFU_ALT_BUF_LEN - len, "&"); -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s %d=", name, devnum); -+ -+ if (IS_MMC(mmc) && mmc->capacity_boot) { -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s%d_boot1 raw 0x0 0x%llx mmcpart 1;", -+ name, devnum, mmc->capacity_boot); -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s%d_boot2 raw 0x0 0x%llx mmcpart 2", -+ name, devnum, mmc->capacity_boot); -+ first = false; -+ } -+ -+ for (p = 1; p < MAX_SEARCH_PARTITIONS; p++) { -+ if (part_get_info(desc, p, &info)) -+ continue; -+ if (!first) -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";"); -+ first = false; -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s%d_%s part %d %d", -+ name, devnum, info.name, devnum, p); -+ } -+} -+ -+static void board_get_alt_info_mtd(struct mtd_info *mtd, char *buf) -+{ -+ struct mtd_info *part; -+ bool first = true; -+ const char *name; -+ int len, partnum = 0; -+ -+ name = mtd->name; -+ len = strlen(buf); -+ -+ if (buf[0] != '\0') -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, "&"); -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "mtd %s=", name); -+ -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s raw 0x0 0x%llx ", -+ name, mtd->size); -+ -+ list_for_each_entry(part, &mtd->partitions, node) { -+ partnum++; -+ if (!first) -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";"); -+ first = false; -+ -+ len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, -+ "%s_%s part %d", -+ name, part->name, partnum); -+ } -+} -+ -+void set_dfu_alt_info(char *interface, char *devstr) -+{ -+ struct udevice *dev; -+ struct mtd_info *mtd; -+ -+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); -+ -+ if (env_get("dfu_alt_info")) -+ return; -+ -+ memset(buf, 0, sizeof(buf)); -+ -+ snprintf(buf, DFU_ALT_BUF_LEN, -+ "ram 0=%s", CONFIG_DFU_ALT_RAM0); -+ -+ if (!uclass_get_device(UCLASS_MMC, 0, &dev)) -+ board_get_alt_info_mmc(dev, buf); -+ -+ if (!uclass_get_device(UCLASS_MMC, 1, &dev)) -+ board_get_alt_info_mmc(dev, buf); -+ -+ if (CONFIG_IS_ENABLED(MTD)) { -+ /* probe all MTD devices */ -+ mtd_probe_devices(); -+ -+ /* probe SPI flash device on a bus */ -+ if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { -+ mtd = get_mtd_device_nm("nor0"); -+ if (!IS_ERR_OR_NULL(mtd)) -+ board_get_alt_info_mtd(mtd, buf); -+ } -+ -+ mtd = get_mtd_device_nm("nand0"); -+ if (!IS_ERR_OR_NULL(mtd)) -+ board_get_alt_info_mtd(mtd, buf); -+ -+ mtd = get_mtd_device_nm("spi-nand0"); -+ if (!IS_ERR_OR_NULL(mtd)) -+ board_get_alt_info_mtd(mtd, buf); -+ } -+ -+#ifdef CONFIG_DFU_VIRT -+ strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN); -+ -+ if (IS_ENABLED(CONFIG_PMIC_STPMIC1)) -+ strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN); -+#endif -+ -+ env_set("dfu_alt_info", buf); -+ puts("DFU alt info setting: done\n"); -+} -+ -+#if CONFIG_IS_ENABLED(DFU_VIRT) -+#include -+#include -+ -+static int dfu_otp_read(u64 offset, u8 *buffer, long *size) -+{ -+ struct udevice *dev; -+ int ret; -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stm32mp_bsec), -+ &dev); -+ if (ret) -+ return ret; -+ -+ ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size); -+ if (ret >= 0) { -+ *size = ret; -+ ret = 0; -+ } -+ -+ return 0; -+} -+ -+static int dfu_pmic_read(u64 offset, u8 *buffer, long *size) -+{ -+ int ret; -+#ifdef CONFIG_PMIC_STPMIC1 -+ struct udevice *dev; -+ -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stpmic1_nvm), -+ &dev); -+ if (ret) -+ return ret; -+ -+ ret = misc_read(dev, 0xF8 + offset, buffer, *size); -+ if (ret >= 0) { -+ *size = ret; -+ ret = 0; -+ } -+ if (ret == -EACCES) { -+ *size = 0; -+ ret = 0; -+ } -+#else -+ pr_err("PMIC update not supported"); -+ ret = -EOPNOTSUPP; -+#endif -+ -+ return ret; -+} -+ -+int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len) -+{ -+ switch (dfu->data.virt.dev_num) { -+ case 0x0: -+ return dfu_otp_read(offset, buf, len); -+ case 0x1: -+ return dfu_pmic_read(offset, buf, len); -+ } -+ -+ if (CONFIG_IS_ENABLED(CMD_STM32PROG) && -+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) -+ return stm32prog_read_medium_virt(dfu, offset, buf, len); -+ -+ *len = 0; -+ return 0; -+} -+ -+int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, -+ void *buf, long *len) -+{ -+ if (CONFIG_IS_ENABLED(CMD_STM32PROG) && -+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) -+ return stm32prog_write_medium_virt(dfu, offset, buf, len); -+ -+ return -EOPNOTSUPP; -+} -+ -+int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) -+{ -+ if (CONFIG_IS_ENABLED(CMD_STM32PROG) && -+ dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) -+ return stm32prog_get_medium_size_virt(dfu, size); -+ -+ *size = SZ_1K; -+ -+ return 0; -+} -+ -+#endif -diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c -new file mode 100644 -index 0000000..9f5897f ---- /dev/null -+++ b/board/st/common/stm32mp_mtdparts.c -@@ -0,0 +1,167 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTDPARTS_LEN 256 -+#define MTDIDS_LEN 128 -+ -+/* -+ * Get a global data pointer -+ */ -+DECLARE_GLOBAL_DATA_PTR; -+ -+/** -+ * update the variables "mtdids" and "mtdparts" with boot, tee and user strings -+ */ -+static void board_set_mtdparts(const char *dev, -+ char *mtdids, -+ char *mtdparts, -+ const char *boot, -+ const char *tee, -+ const char *user) -+{ -+ /* mtdids: "=, ...." */ -+ if (mtdids[0] != '\0') -+ strcat(mtdids, ","); -+ strcat(mtdids, dev); -+ strcat(mtdids, "="); -+ strcat(mtdids, dev); -+ -+ /* mtdparts: "mtdparts=:>;..." */ -+ if (mtdparts[0] != '\0') -+ strncat(mtdparts, ";", MTDPARTS_LEN); -+ else -+ strcat(mtdparts, "mtdparts="); -+ -+ strncat(mtdparts, dev, MTDPARTS_LEN); -+ strncat(mtdparts, ":", MTDPARTS_LEN); -+ -+ if (boot) { -+ strncat(mtdparts, boot, MTDPARTS_LEN); -+ strncat(mtdparts, ",", MTDPARTS_LEN); -+ } -+ -+ if (tee) { -+ strncat(mtdparts, tee, MTDPARTS_LEN); -+ strncat(mtdparts, ",", MTDPARTS_LEN); -+ } -+ -+ strncat(mtdparts, user, MTDPARTS_LEN); -+} -+ -+void board_mtdparts_default(const char **mtdids, const char **mtdparts) -+{ -+ struct mtd_info *mtd; -+ struct udevice *dev; -+ static char parts[3 * MTDPARTS_LEN + 1]; -+ static char ids[MTDIDS_LEN + 1]; -+ static bool mtd_initialized; -+ bool tee, nor, nand, spinand, serial; -+ -+ if (mtd_initialized) { -+ *mtdids = ids; -+ *mtdparts = parts; -+ return; -+ } -+ -+ tee = false; -+ nor = false; -+ nand = false; -+ spinand = false; -+ serial = false; -+ -+ switch (get_bootmode() & TAMP_BOOT_DEVICE_MASK) { -+ case BOOT_SERIAL_UART: -+ case BOOT_SERIAL_USB: -+ serial = true; -+ if (CONFIG_IS_ENABLED(CMD_STM32PROG)) { -+ tee = stm32prog_get_tee_partitions(); -+ nor = stm32prog_get_fsbl_nor(); -+ } -+ nand = true; -+ spinand = true; -+ break; -+ case BOOT_FLASH_NAND: -+ nand = true; -+ break; -+ case BOOT_FLASH_SPINAND: -+ spinand = true; -+ break; -+ case BOOT_FLASH_NOR: -+ nor = true; -+ break; -+ default: -+ break; -+ } -+ -+ if (!serial && CONFIG_IS_ENABLED(OPTEE) && -+ tee_find_device(NULL, NULL, NULL, NULL)) -+ tee = true; -+ -+ memset(parts, 0, sizeof(parts)); -+ memset(ids, 0, sizeof(ids)); -+ -+ /* probe all MTD devices */ -+ for (uclass_first_device(UCLASS_MTD, &dev); -+ dev; -+ uclass_next_device(&dev)) { -+ pr_debug("mtd device = %s\n", dev->name); -+ } -+ -+ if (nor || nand) { -+ mtd = get_mtd_device_nm("nand0"); -+ if (!IS_ERR_OR_NULL(mtd)) { -+ const char *mtd_boot = CONFIG_MTDPARTS_NAND0_BOOT; -+ const char *mtd_tee = CONFIG_MTDPARTS_NAND0_TEE; -+ -+ board_set_mtdparts("nand0", ids, parts, -+ !nor ? mtd_boot : NULL, -+ !nor && tee ? mtd_tee : NULL, -+ "-(UBI)"); -+ put_mtd_device(mtd); -+ } -+ } -+ -+ if (nor || spinand) { -+ mtd = get_mtd_device_nm("spi-nand0"); -+ if (!IS_ERR_OR_NULL(mtd)) { -+ const char *mtd_boot = CONFIG_MTDPARTS_SPINAND0_BOOT; -+ const char *mtd_tee = CONFIG_MTDPARTS_SPINAND0_TEE; -+ -+ board_set_mtdparts("spi-nand0", ids, parts, -+ !nor ? mtd_boot : NULL, -+ !nor && tee ? mtd_tee : NULL, -+ "-(UBI)"); -+ put_mtd_device(mtd); -+ } -+ } -+ -+ if (nor) { -+ if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { -+ const char *mtd_boot = CONFIG_MTDPARTS_NOR0_BOOT; -+ const char *mtd_tee = CONFIG_MTDPARTS_NOR0_TEE; -+ -+ board_set_mtdparts("nor0", ids, parts, -+ mtd_boot, -+ tee ? mtd_tee : NULL, -+ "-(nor_user)"); -+ } -+ } -+ -+ mtd_initialized = true; -+ *mtdids = ids; -+ *mtdparts = parts; -+ debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts); -+} -diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig -index 4fa2360..c5ab755 100644 ---- a/board/st/stm32mp1/Kconfig -+++ b/board/st/stm32mp1/Kconfig -@@ -1,4 +1,4 @@ --if TARGET_STM32MP1 -+if TARGET_ST_STM32MP15x - - config SYS_BOARD - default "stm32mp1" -@@ -9,21 +9,5 @@ config SYS_VENDOR - config SYS_CONFIG_NAME - default "stm32mp1" - --config ENV_SECT_SIZE -- default 0x40000 if ENV_IS_IN_SPI_FLASH -- --config ENV_OFFSET -- default 0x280000 if ENV_IS_IN_SPI_FLASH -- --config CMD_STBOARD -- bool "stboard - command for OTP board information" -- default y -- help -- This compile the stboard command to -- read and write the board in the OTP. -- --config TARGET_STM32MP157C_DK2 -- bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board" -- default y -- -+source "board/st/common/Kconfig" - endif -diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS -index 2930947..96c4559 100644 ---- a/board/st/stm32mp1/MAINTAINERS -+++ b/board/st/stm32mp1/MAINTAINERS -@@ -6,6 +6,5 @@ S: Maintained - F: arch/arm/dts/stm32mp15* - F: board/st/stm32mp1/ - F: configs/stm32mp15_basic_defconfig --F: configs/stm32mp15_optee_defconfig - F: configs/stm32mp15_trusted_defconfig - F: include/configs/stm32mp1.h -diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile -index 3c6c035..8188075 100644 ---- a/board/st/stm32mp1/Makefile -+++ b/board/st/stm32mp1/Makefile -@@ -7,7 +7,6 @@ ifdef CONFIG_SPL_BUILD - obj-y += spl.o - else - obj-y += stm32mp1.o --obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o - endif - - obj-y += board.o -diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README -index f2069bc..8172d26 100644 ---- a/board/st/stm32mp1/README -+++ b/board/st/stm32mp1/README -@@ -1,503 +1 @@ --SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause --# --# Copyright (C) 2018 STMicroelectronics - All Rights Reserved --# -- --U-Boot on STMicroelectronics STM32MP1 --====================================== -- --1. Summary --========== --This is a quick instruction for setup stm32mp1 boards. -- --2. Supported devices --==================== --U-Boot supports one STMP32MP1 SoCs: STM32MP157 -- --The STM32MP157 is a Cortex-A MPU aimed at various applications. --It features: --- Dual core Cortex-A7 application core --- 2D/3D image composition with GPU --- Standard memories interface support --- Standard connectivity, widely inherited from the STM32 MCU family --- Comprehensive security support -- --Everything is supported in Linux but U-Boot is limited to: --1. UART --2. SDCard/MMC controller (SDMMC) --3. NAND controller (FMC) --4. NOR controller (QSPI) --5. USB controller (OTG DWC2) --6. Ethernet controller -- --And the necessary drivers --1. I2C --2. STPMIC1 (PMIC and regulator) --3. Clock, Reset, Sysreset --4. Fuse -- --Currently the following boards are supported: --+ stm32mp157c-ev1 --+ stm32mp157c-ed1 --+ stm32mp157a-dk1 --+ stm32mp157c-dk2 --+ stm32mp157a-avenger96 -- --3. Boot Sequences --================= -- --BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel) -- --with FSBL = First Stage Bootloader -- SSBL = Second Stage Bootloader -- --3 boot configurations are supported: -- --1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig) -- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot -- TF-A performs a full initialization of Secure peripherals and installs a -- secure monitor. -- U-Boot is running in normal world and uses TF-A monitor -- to access to secure resources. -- --2) The "Trusted" boot chain with OP-TEE -- (defconfig_file : stm32mp15_optee_defconfig) -- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot -- TF-A performs a full initialization of Secure peripherals and installs OP-TEE -- from specific partitions (teeh, teed, teex). -- U-Boot is running in normal world and uses OP-TEE monitor to access -- to secure resources. -- --3) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) -- BootRom => FSBL = U-Boot SPL => SSBL = U-Boot -- SPL has limited security initialisation -- U-Boot is running in secure mode and provide a secure monitor to the kernel -- with only PSCI support (Power State Coordination Interface defined by ARM). -- --All the STM32MP1 boards supported by U-Boot use the same generic board --stm32mp1 which support all the bootable devices. -- --Each board is configurated only with the associated device tree. -- --4. Device Tree Selection --======================== -- --You need to select the appropriate device tree for your board, --the supported device trees for stm32mp157 are: -- --+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) -- dts: stm32mp157c-ev1 -- --+ ed1: daughter board with pmic stpmic1 -- dts: stm32mp157c-ed1 -- --+ dk1: Discovery board -- dts: stm32mp157a-dk1 -- --+ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel -- dts: stm32mp157c-dk2 -- --+ avenger96: Avenger96 board from Arrow Electronics -- dts: stm32mp157a-avenger96 -- --5. Build Procedure --================== -- --1. Install required tools for U-Boot -- -- + install package needed in U-Boot makefile -- (libssl-dev, swig, libpython-dev...) -- + install ARMv7 toolchain for 32bit Cortex-A (from Linaro, -- from SDK for STM32MP1, or any crosstoolchains from your distribution) -- --2. Set the cross compiler: -- -- # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- -- (you can use any gcc cross compiler compatible with U-Boot) -- --3. Select the output directory (optional) -- -- # export KBUILD_OUTPUT=/path/to/output -- -- for example: use one output directory for each configuration -- # export KBUILD_OUTPUT=stm32mp15_trusted -- # export KBUILD_OUTPUT=stm32mp15_optee -- # export KBUILD_OUTPUT=stm32mp15_basic -- -- you can build outside of code directory: -- # export KBUILD_OUTPUT=../build/stm32mp15_trusted -- --4. Configure U-Boot: -- -- # make -- -- - For trusted boot mode : "stm32mp15_trusted_defconfig" -- - For trusted with OP-TEE boot mode : "stm32mp15_optee_defconfig" -- - For basic boot mode: "stm32mp15_basic_defconfig" -- --5. Configure the device-tree and build the U-Boot image: -- -- # make DEVICE_TREE= all -- -- example: -- a) trusted boot on ev1 -- # export KBUILD_OUTPUT=stm32mp15_trusted -- # make stm32mp15_trusted_defconfig -- # make DEVICE_TREE=stm32mp157c-ev1 all -- -- b) trusted with OP-TEE boot on dk2 -- # export KBUILD_OUTPUT=stm32mp15_optee -- # make stm32mp15_optee_defconfig -- # make DEVICE_TREE=stm32mp157c-dk2 all -- -- c) basic boot on ev1 -- # export KBUILD_OUTPUT=stm32mp15_basic -- # make stm32mp15_basic_defconfig -- # make DEVICE_TREE=stm32mp157c-ev1 all -- -- d) basic boot on ed1 -- # export KBUILD_OUTPUT=stm32mp15_basic -- # make stm32mp15_basic_defconfig -- # make DEVICE_TREE=stm32mp157c-ed1 all -- -- e) basic boot on dk1 -- # export KBUILD_OUTPUT=stm32mp15_basic -- # make stm32mp15_basic_defconfig -- # make DEVICE_TREE=stm32mp157a-dk1 all -- -- f) basic boot on avenger96 -- # export KBUILD_OUTPUT=stm32mp15_basic -- # make stm32mp15_basic_defconfig -- # make DEVICE_TREE=stm32mp157a-avenger96 all -- --6. Output files -- -- BootRom and TF-A expect binaries with STM32 image header -- SPL expects file with U-Boot uImage header -- -- So in the output directory (selected by KBUILD_OUTPUT), -- you can found the needed files: -- -- a) For Trusted boot (with or without OP-TEE) -- + FSBL = tf-a.stm32 (provided by TF-A compilation) -- + SSBL = u-boot.stm32 -- -- b) For Basic boot -- + FSBL = spl/u-boot-spl.stm32 -- + SSBL = u-boot.img -- --6. Switch Setting for Boot Mode --=============================== -- --You can select the boot mode, on the board with one switch : -- --- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2 -- -- ----------------------------------- -- Boot Mode BOOT2 BOOT1 BOOT0 -- ----------------------------------- -- Reserved 0 0 0 -- NOR 0 0 1 -- SD-Card 1 0 1 -- eMMC 0 1 0 -- NAND 0 1 1 -- Recovery 1 1 0 -- Recovery 0 0 0 -- --- on board DK1/DK2 with the switch SW1 : BOOT0, BOOT2 -- (BOOT1 forced to 0, NOR not supported) -- -- -------------------------- -- Boot Mode BOOT2 BOOT0 -- -------------------------- -- Reserved 1 0 -- SD-Card 1 1 -- Recovery 0 0 -- --- Boot mode of Avenger96 can be selected using switch S3 -- -- ----------------------------------- -- Boot Mode BOOT2 BOOT1 BOOT0 -- ----------------------------------- -- Recovery 0 0 0 -- NOR 0 0 1 -- SD-Card 1 0 1 -- eMMC 0 1 0 -- NAND 0 1 1 -- Reserved 1 0 0 -- Recovery 1 1 0 -- SD-Card 1 1 1 -- --Recovery is a boot from serial link (UART/USB) and it is used with --STM32CubeProgrammer tool to load executable in RAM and to update the flash --devices available on the board (NOR/NAND/eMMC/SDCARD). --The communication between HOST and board is based on --- for UARTs : the uart protocol used with all MCU STM32 --- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32) -- --7. Prepare an SDCard --=================== -- --The minimal requirements for STMP32MP1 boot up to U-Boot are: --- GPT partitioning (with gdisk or with sgdisk) --- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB --- one ssbl partition for U-Boot -- --Then the minimal GPT partition is: -- ----- ------- --------- -------------- -- | Num | Name | Size | Content | -- ----- ------- -------- --------------- -- | 1 | fsbl1 | 256 KiB | TF-A or SPL | -- | 2 | fsbl2 | 256 KiB | TF-A or SPL | -- | 3 | ssbl | enought | U-Boot | -- | * | - | - | Boot/Rootfs | -- ----- ------- --------- -------------- -- --(*) add bootable partition for extlinux.conf -- following Generic Distribution -- (doc/README.distro for use) -- -- according the used card reader select the block device -- (/dev/sdx or /dev/mmcblk0) -- in the next example I use /dev/mmcblk0 -- --for example: with gpt table with 128 entries -- -- a) remove previous formatting -- # sgdisk -o /dev/ -- -- b) create minimal image -- # sgdisk --resize-table=128 -a 1 \ -- -n 1:34:545 -c 1:fsbl1 \ -- -n 2:546:1057 -c 2:fsbl2 \ -- -n 3:1058:5153 -c 3:ssbl \ -- -p /dev/ -- -- you can add other partitions for kernel -- one partition rootfs for example: -- -n 4:5154: -c 4:rootfs \ -- -- c) copy the FSBL (2 times) and SSBL file on the correct partition. -- in this example in partition 1 to 3 -- -- for basic boot mode : = /dev/mmcblk0 -- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1 -- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2 -- # dd if=u-boot.img of=/dev/mmcblk0p3 -- -- for trusted boot mode : -- # dd if=tf-a.stm32 of=/dev/mmcblk0p1 -- # dd if=tf-a.stm32 of=/dev/mmcblk0p2 -- # dd if=u-boot.stm32 of=/dev/mmcblk0p3 -- --To boot from SDCard, select BootPinMode = 1 0 1 and reset. -- --8. Prepare eMMC --=============== --You can use U-Boot to copy binary in eMMC. -- --In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img) --are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs). -- --To boot from SDCard, select BootPinMode = 1 0 1 and reset. -- --Then you update the eMMC with the next U-Boot command : -- --a) prepare GPT on eMMC, -- example with 2 partitions, bootfs and roots: -- -- # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512" -- # gpt write mmc 1 ${emmc_part} -- --b) copy SPL on eMMC on firts boot partition -- (SPL max size is 256kB, with LBA 512, 0x200) -- -- # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32 -- # mmc dev 1 -- # mmc partconf 1 1 1 1 -- # mmc write ${fileaddr} 0 200 -- # mmc partconf 1 1 1 0 -- --c) copy U-Boot in first GPT partition of eMMC -- -- # ext4load mmc 0:4 0xC0000000 u-boot.img -- # mmc dev 1 -- # part start mmc 1 1 partstart -- # part size mmc 1 1 partsize -- # mmc write ${fileaddr} ${partstart} ${partsize} -- --To boot from eMMC, select BootPinMode = 0 1 0 and reset. -- --9. MAC Address --============== -- --Please read doc/README.enetaddr for the implementation guidelines for mac id --usage. Basically, environment has precedence over board specific storage. -- --Mac id storage and retrieval in stm32mp otp : --- OTP_57[31:0] = MAC_ADDR[31:0] --- OTP_58[15:0] = MAC_ADDR[47:32] -- --To program a MAC address on virgin OTP words above, you can use the fuse command --on bank 0 to access to internal OTP: -- -- example to set mac address "12:34:56:78:9a:bc" -- -- 1- Write OTP -- STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a -- -- 2- Read OTP -- STM32MP> fuse sense 0 57 2 -- Sensing bank 0: -- Word 0x00000039: 78563412 0000bc9a -- -- 3- next REBOOT : -- ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc" -- -- 4 check env update -- STM32MP> print ethaddr -- ethaddr=12:34:56:78:9a:bc -- --10. Coprocessor firmware --======================== -- --U-Boot can boot the coprocessor before the kernel (coprocessor early boot). -- --A/ Manuallly by using rproc commands (update the bootcmd) -- Configurations -- # env set name_copro "rproc-m4-fw.elf" -- # env set dev_copro 0 -- # env set loadaddr_copro 0xC1000000 -- -- Load binary from bootfs partition (number 4) on SDCard (mmc 0) -- # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro} -- => ${filesize} updated with the size of the loaded file -- -- Start M4 firmware with remote proc command -- # rproc init -- # rproc load ${dev_copro} ${loadaddr_copro} ${filesize} -- # rproc start ${dev_copro} -- --B/ Automatically by using FIT feature and generic DISTRO bootcmd -- -- see examples in this directory : -- -- Generate FIT including kernel + device tree + M4 firmware -- with cfg with M4 boot -- $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb -- -- Then using DISTRO configuration file: see extlinux.conf to select -- the correct configuration -- => stm32mp157c-ev1-m4 -- => stm32mp157c-dk2-m4 -- --11. DFU support --=============== -- --The DFU is supported on ST board. --The env variable dfu_alt_info is automatically build, and all --the memory present on the ST boards are exported. -- --The mode is started by -- --STM32MP> dfu 0 -- --On EV1 board: -- --STM32MP> dfu 0 list -- --DFU alt settings list: --dev: RAM alt: 0 name: uImage layout: RAM_ADDR --dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR --dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR --dev: eMMC alt: 3 name: sdcard_fsbl1 layout: RAW_ADDR --dev: eMMC alt: 4 name: sdcard_fsbl2 layout: RAW_ADDR --dev: eMMC alt: 5 name: sdcard_ssbl layout: RAW_ADDR --dev: eMMC alt: 6 name: sdcard_bootfs layout: RAW_ADDR --dev: eMMC alt: 7 name: sdcard_vendorfs layout: RAW_ADDR --dev: eMMC alt: 8 name: sdcard_rootfs layout: RAW_ADDR --dev: eMMC alt: 9 name: sdcard_userfs layout: RAW_ADDR --dev: eMMC alt: 10 name: emmc_fsbl1 layout: RAW_ADDR --dev: eMMC alt: 11 name: emmc_fsbl2 layout: RAW_ADDR --dev: eMMC alt: 12 name: emmc_ssbl layout: RAW_ADDR --dev: eMMC alt: 13 name: emmc_bootfs layout: RAW_ADDR --dev: eMMC alt: 14 name: emmc_vendorfs layout: RAW_ADDR --dev: eMMC alt: 15 name: emmc_rootfs layout: RAW_ADDR --dev: eMMC alt: 16 name: emmc_userfs layout: RAW_ADDR --dev: MTD alt: 17 name: nor_fsbl1 layout: RAW_ADDR --dev: MTD alt: 18 name: nor_fsbl2 layout: RAW_ADDR --dev: MTD alt: 19 name: nor_ssbl layout: RAW_ADDR --dev: MTD alt: 20 name: nor_env layout: RAW_ADDR --dev: MTD alt: 21 name: nand_fsbl layout: RAW_ADDR --dev: MTD alt: 22 name: nand_ssbl1 layout: RAW_ADDR --dev: MTD alt: 23 name: nand_ssbl2 layout: RAW_ADDR --dev: MTD alt: 24 name: nand_UBI layout: RAW_ADDR --dev: VIRT alt: 25 name: OTP layout: RAW_ADDR --dev: VIRT alt: 26 name: PMIC layout: RAW_ADDR -- --All the supported device are exported for dfu-util tool: -- --$> dfu-util -l --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=26, name="PMIC", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=25, name="OTP", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=24, name="nand_UBI", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=23, name="nand_ssbl2", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=22, name="nand_ssbl1", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="nand_fsbl", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="nor_env", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nor_ssbl", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor_fsbl2", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor_fsbl1", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="emmc_userfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="emmc_rootfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="emmc_vendorfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="emmc_bootfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="emmc_ssbl", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="emmc_fsbl2", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="emmc_fsbl1", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="sdcard_userfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="sdcard_rootfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="sdcard_vendorfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="sdcard_bootfs", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="sdcard_ssbl", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="sdcard_fsbl2", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="sdcard_fsbl1", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330" --Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330" -- --You can update the boot device: -- --#SDCARD --$> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img --$> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 -- --#EMMC --$> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img --$> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 --$> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 -- --#NOR --$> dfu-util -d 0483:5720 -a 17 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 18 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 19 -D u-boot-stm32mp157c-ev1-trusted.img -- --#NAND (UBI partition used for NAND only boot or NOR + NAND boot) --$> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32 --$> dfu-util -d 0483:5720 -a 22 -D u-boot-stm32mp157c-ev1-trusted.img --$> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img --$> dfu-util -d 0483:5720 -a 24 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi -- --And you can also dump the OTP and the PMIC NVM with: -- --$> dfu-util -d 0483:5720 -a 25 -U otp.bin --$> dfu-util -d 0483:5720 -a 26 -U pmic.bin -+see doc/board/st/stm32mp1.rst -diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c -index c3d832f..3e38aef 100644 ---- a/board/st/stm32mp1/board.c -+++ b/board/st/stm32mp1/board.c -@@ -38,11 +38,46 @@ void board_debug_uart_init(void) - #endif - - #ifdef CONFIG_PMIC_STPMIC1 -+u32 opp_voltage_mv; -+ -+void board_vddcore_init(u32 voltage_mv) -+{ -+ opp_voltage_mv = voltage_mv; -+} -+ -+int board_vddcore_set(void) -+{ -+ struct udevice *dev; -+ int ret; -+ u32 value; -+ -+ if (!opp_voltage_mv) -+ return 0; -+ -+ ret = uclass_get_device_by_driver(UCLASS_PMIC, -+ DM_GET_DRIVER(pmic_stpmic1), &dev); -+ if (ret) -+ return ret; -+ -+ /* VDDCORE= STMPCI1 BUCK1 ramp=+25mV, 5 => 725mV, 36 => 1500mV */ -+ value = ((opp_voltage_mv - 725) / 25) + 5; -+ if (value < 5) -+ value = 5; -+ if (value > 36) -+ value = 36; -+ -+ return pmic_clrsetbits(dev, -+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK1), -+ STPMIC1_BUCK_VOUT_MASK, -+ STPMIC1_BUCK_VOUT(value)); -+} -+ - int board_ddr_power_init(enum ddr_type ddr_type) - { - struct udevice *dev; - bool buck3_at_1800000v = false; - int ret; -+ u32 buck2; - - ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmic1), &dev); -@@ -102,8 +137,10 @@ int board_ddr_power_init(enum ddr_type ddr_type) - - break; - -- case STM32MP_LPDDR2: -- case STM32MP_LPDDR3: -+ case STM32MP_LPDDR2_16: -+ case STM32MP_LPDDR2_32: -+ case STM32MP_LPDDR3_16: -+ case STM32MP_LPDDR3_32: - /* - * configure VDD_DDR1 = LDO3 - * Set LDO3 to 1.8V -@@ -133,11 +170,23 @@ int board_ddr_power_init(enum ddr_type ddr_type) - if (ret < 0) - return ret; - -- /* VDD_DDR2 : Set BUCK2 to 1.2V */ -+ /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/ -+ switch (ddr_type) { -+ case STM32MP_LPDDR2_32: -+ case STM32MP_LPDDR3_32: -+ buck2 = STPMIC1_BUCK2_1250000V; -+ break; -+ default: -+ case STM32MP_LPDDR2_16: -+ case STM32MP_LPDDR3_16: -+ buck2 = STPMIC1_BUCK2_1200000V; -+ break; -+ } -+ - ret = pmic_clrsetbits(dev, - STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), - STPMIC1_BUCK_VOUT_MASK, -- STPMIC1_BUCK2_1200000V); -+ buck2); - if (ret < 0) - return ret; - -diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c -deleted file mode 100644 -index 04352ae..0000000 ---- a/board/st/stm32mp1/cmd_stboard.c -+++ /dev/null -@@ -1,145 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause --/* -- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved -- */ -- --#include --#include --#include --#include --#include -- --static bool check_stboard(u16 board) --{ -- unsigned int i; -- const u16 st_board_id[] = { -- 0x1272, -- 0x1263, -- 0x1264, -- 0x1298, -- 0x1341, -- 0x1497, -- }; -- -- for (i = 0; i < ARRAY_SIZE(st_board_id); i++) -- if (board == st_board_id[i]) -- return true; -- -- return false; --} -- --static void display_stboard(u32 otp) --{ -- printf("Board: MB%04x Var%d Rev.%c-%02d\n", -- otp >> 16, -- (otp >> 12) & 0xF, -- ((otp >> 8) & 0xF) - 1 + 'A', -- otp & 0xF); --} -- --static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, -- char * const argv[]) --{ -- int ret; -- u32 otp; -- u8 revision; -- unsigned long board, variant, bom; -- struct udevice *dev; -- int confirmed = argc == 6 && !strcmp(argv[1], "-y"); -- -- argc -= 1 + confirmed; -- argv += 1 + confirmed; -- -- if (argc != 0 && argc != 4) -- return CMD_RET_USAGE; -- -- ret = uclass_get_device_by_driver(UCLASS_MISC, -- DM_GET_DRIVER(stm32mp_bsec), -- &dev); -- -- ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), -- &otp, sizeof(otp)); -- -- if (ret < 0) { -- puts("OTP read error"); -- return CMD_RET_FAILURE; -- } -- -- if (argc == 0) { -- if (!otp) -- puts("Board : OTP board FREE\n"); -- else -- display_stboard(otp); -- return CMD_RET_SUCCESS; -- } -- -- if (otp) { -- display_stboard(otp); -- printf("ERROR: OTP board not FREE\n"); -- return CMD_RET_FAILURE; -- } -- -- if (strict_strtoul(argv[0], 16, &board) < 0 || -- board == 0 || board > 0xFFFF) { -- printf("argument %d invalid: %s\n", 1, argv[0]); -- return CMD_RET_USAGE; -- } -- -- if (strict_strtoul(argv[1], 10, &variant) < 0 || -- variant == 0 || variant > 15) { -- printf("argument %d invalid: %s\n", 2, argv[1]); -- return CMD_RET_USAGE; -- } -- -- revision = argv[2][0] - 'A' + 1; -- if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) { -- printf("argument %d invalid: %s\n", 3, argv[2]); -- return CMD_RET_USAGE; -- } -- -- if (strict_strtoul(argv[3], 10, &bom) < 0 || -- bom == 0 || bom > 15) { -- printf("argument %d invalid: %s\n", 4, argv[3]); -- return CMD_RET_USAGE; -- } -- -- otp = (board << 16) | (variant << 12) | (revision << 8) | bom; -- display_stboard(otp); -- printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp); -- -- if (!check_stboard((u16)board)) { -- printf("Unknown board MB%04x\n", (u16)board); -- return CMD_RET_FAILURE; -- } -- if (!confirmed) { -- printf("Warning: Programming BOARD in OTP is irreversible!\n"); -- printf("Really perform this OTP programming? \n"); -- -- if (!confirm_yesno()) { -- puts("BOARD programming aborted\n"); -- return CMD_RET_FAILURE; -- } -- } -- -- ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), -- &otp, sizeof(otp)); -- -- if (ret) { -- puts("BOARD programming error\n"); -- return CMD_RET_FAILURE; -- } -- puts("BOARD programming done\n"); -- -- return CMD_RET_SUCCESS; --} -- --U_BOOT_CMD(stboard, 6, 0, do_stboard, -- "read/write board reference in OTP", -- "\n" -- " Print current board information\n" -- "stboard [-y] \n" -- " Write board information\n" -- " - Board: xxxx, example 1264 for MB1264\n" -- " - Variant: 1 ... 15\n" -- " - Revision: A...O\n" -- " - BOM: 1...15\n"); -diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c -index cee3500..617d05d 100644 ---- a/board/st/stm32mp1/stm32mp1.c -+++ b/board/st/stm32mp1/stm32mp1.c -@@ -15,9 +15,7 @@ - #include - #include - #include --#include - #include --#include - #include - #include - #include -@@ -31,6 +29,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -77,6 +76,39 @@ DECLARE_GLOBAL_DATA_PTR; - #define USB_START_LOW_THRESHOLD_UV 1230000 - #define USB_START_HIGH_THRESHOLD_UV 2150000 - -+static void stboard_lock(struct udevice *dev) -+{ -+ int ret; -+ u32 lock; -+ u32 mac[2]; -+ -+ ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), -+ &lock, sizeof(lock)); -+ if (ret != sizeof(lock) || lock == 1) -+ return; -+ -+ lock = 1; -+ misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), &lock, sizeof(lock)); -+ printf("Lock the BOARD OTP (%d)\n", BSEC_OTP_BOARD); -+ -+ /* check LOCK status on MAC address */ -+ ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), -+ &mac, sizeof(mac)); -+ if (ret != sizeof(mac) || (mac[0] == 0x0 && mac[1] == 0x0)) -+ return; -+ -+ ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_MAC), -+ &mac, sizeof(mac)); -+ /* already locked : nothing to do */ -+ if (ret != sizeof(mac) || (mac[0] == 1 && mac[1] == 1)) -+ return; -+ -+ mac[0] = 1; -+ mac[1] = 1; -+ misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_MAC), &mac, sizeof(mac)); -+ printf("Lock the MAC OTP (%d)\n", BSEC_OTP_MAC); -+} -+ - int checkboard(void) - { - int ret; -@@ -86,9 +118,7 @@ int checkboard(void) - const char *fdt_compat; - int fdt_compat_len; - -- if (IS_ENABLED(CONFIG_STM32MP1_OPTEE)) -- mode = "trusted with OP-TEE"; -- else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) -+ if (CONFIG_IS_ENABLED(STM32MP1_TRUSTED)) - mode = "trusted"; - else - mode = "basic"; -@@ -100,19 +130,27 @@ int checkboard(void) - printf(" (%s)", fdt_compat); - puts("\n"); - -- ret = uclass_get_device_by_driver(UCLASS_MISC, -- DM_GET_DRIVER(stm32mp_bsec), -- &dev); -+ if (CONFIG_IS_ENABLED(CMD_STBOARD)) { -+ ret = uclass_get_device_by_driver(UCLASS_MISC, -+ DM_GET_DRIVER(stm32mp_bsec), -+ &dev); - -- if (!ret) -- ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), -- &otp, sizeof(otp)); -- if (ret > 0 && otp) { -- printf("Board: MB%04x Var%d Rev.%c-%02d\n", -- otp >> 16, -- (otp >> 12) & 0xF, -- ((otp >> 8) & 0xF) - 1 + 'A', -- otp & 0xF); -+ if (!ret) -+ ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), -+ &otp, sizeof(otp)); -+ if (ret > 0 && otp) { -+ printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n", -+ otp >> 16, -+ (otp >> 12) & 0xF, -+ (otp >> 4) & 0xF, -+ ((otp >> 8) & 0xF) - 1 + 'A', -+ otp & 0xF); -+ -+ /* LOCK OTP for board ID and MAC address on ST board */ -+ if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && -+ ((otp >> 16) == 0x1272 || (otp >> 16) == 0x1263)) -+ stboard_lock(dev); -+ } - } - - return 0; -@@ -274,9 +312,11 @@ static int get_led(struct udevice **dev, char *led_string) - - return 0; - } -+#endif - - static int setup_led(enum led_state_t cmd) - { -+#ifdef CONFIG_LED - struct udevice *dev; - int ret; - -@@ -286,8 +326,10 @@ static int setup_led(enum led_state_t cmd) - - ret = led_set_state(dev, cmd); - return ret; --} -+#else -+ return 0; - #endif -+} - - static void __maybe_unused led_error_blink(u32 nb_blink) - { -@@ -310,6 +352,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink) - mdelay(125); - WATCHDOG_RESET(); - } -+ led_set_state(led, LEDST_ON); - } - #endif - -@@ -429,7 +472,7 @@ static int board_check_usb_power(void) - if (max_uV > USB_WARNING_LOW_THRESHOLD_UV && - max_uV <= USB_START_LOW_THRESHOLD_UV && - min_uV <= USB_LOW_THRESHOLD_UV) { -- pr_err("* WARNING 1.5mA power supply detected *\n"); -+ pr_err("* WARNING 1.5A power supply detected *\n"); - nb_blink = 3; - } - -@@ -462,10 +505,10 @@ static void sysconf_init(void) - struct udevice *pwr_dev; - struct udevice *pwr_reg; - struct udevice *dev; -- int ret; - u32 otp = 0; - #endif -- u32 bootr; -+ int ret; -+ u32 bootr, val; - - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - -@@ -542,8 +585,15 @@ static void sysconf_init(void) - */ - writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); - -- while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) -- ; -+ /* poll until ready (1s timeout) */ -+ ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val, -+ val & SYSCFG_CMPCR_READY, -+ 1000000); -+ if (ret) { -+ pr_err("SYSCFG: I/O compensation failed, timeout.\n"); -+ led_error_blink(10); -+ } -+ - clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); - #endif - } -@@ -607,31 +657,67 @@ error: - - static bool board_is_dk2(void) - { -- if (CONFIG_IS_ENABLED(TARGET_STM32MP157C_DK2) && -- of_machine_is_compatible("st,stm32mp157c-dk2")) -+ if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && -+ (of_machine_is_compatible("st,stm32mp157c-dk2") || -+ of_machine_is_compatible("st,stm32mp157f-dk2"))) - return true; - - return false; - } - #endif - --/* board dependent setup after realloc */ --int board_init(void) -+static bool board_is_ev1(void) -+{ -+ if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && -+ (of_machine_is_compatible("st,stm32mp157a-ev1") || -+ of_machine_is_compatible("st,stm32mp157c-ev1") || -+ of_machine_is_compatible("st,stm32mp157d-ev1") || -+ of_machine_is_compatible("st,stm32mp157f-ev1"))) -+ return true; -+ -+ return false; -+} -+ -+/* touchscreen driver: only used for pincontrol configuration */ -+static const struct udevice_id goodix_ids[] = { -+ { .compatible = "goodix,gt9147", }, -+ { } -+}; -+ -+U_BOOT_DRIVER(goodix) = { -+ .name = "goodix", -+ .id = UCLASS_NOP, -+ .of_match = goodix_ids, -+}; -+ -+static int board_ev1_init(void) - { - struct udevice *dev; -+ int ret; -+ -+ /* configure IRQ line on EV1 for touchscreen before LCD reset */ -+ ret = uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(goodix), -+ &dev); -+ if (ret) -+ debug("goodix init failed: %d\n", ret); - -+ return ret; -+} -+ -+/* board dependent setup after realloc */ -+int board_init(void) -+{ - /* address of boot parameters */ - gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; - -- /* probe all PINCTRL for hog */ -- for (uclass_first_device(UCLASS_PINCTRL, &dev); -- dev; -- uclass_next_device(&dev)) { -- pr_debug("probe pincontrol = %s\n", dev->name); -- } -+ if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) -+ gpio_hog_probe_all(); - - board_key_check(); - -+ if (board_is_ev1()) -+ board_ev1_init(); -+ - #ifdef CONFIG_DM_REGULATOR - if (board_is_dk2()) - dk2_i2c1_fix(); -@@ -641,8 +727,10 @@ int board_init(void) - - sysconf_init(); - -- if (CONFIG_IS_ENABLED(CONFIG_LED)) -+ if (CONFIG_IS_ENABLED(LED)) { - led_default_state(); -+ setup_led(LEDST_ON); -+ } - - return 0; - } -@@ -661,10 +749,19 @@ int board_late_init(void) - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); - if (fdt_compat && fdt_compat_len) { -- if (strncmp(fdt_compat, "st,", 3) != 0) -+ if (strncmp(fdt_compat, "st,", 3) != 0) { - env_set("board_name", fdt_compat); -- else -+ } else { -+ char dtb_name[256]; -+ int buf_len = sizeof(dtb_name); -+ - env_set("board_name", fdt_compat + 3); -+ -+ strncpy(dtb_name, fdt_compat + 3, buf_len); -+ buf_len -= strlen(fdt_compat + 3); -+ strncat(dtb_name, ".dtb", buf_len); -+ env_set("fdtfile", dtb_name); -+ } - } - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), -@@ -690,7 +787,8 @@ int board_late_init(void) - - /* Check the boot-source to disable bootdelay */ - boot_device = env_get("boot_device"); -- if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) -+ if (boot_device && -+ (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))) - env_set("bootdelay", "0"); - - return 0; -@@ -781,6 +879,11 @@ enum env_location env_get_location(enum env_operation op, int prio) - return ENVL_UNKNOWN; - - switch (bootmode & TAMP_BOOT_DEVICE_MASK) { -+#ifdef CONFIG_ENV_IS_IN_MMC -+ case BOOT_FLASH_SD: -+ case BOOT_FLASH_EMMC: -+ return ENVL_MMC; -+#endif - #ifdef CONFIG_ENV_IS_IN_EXT4 - case BOOT_FLASH_SD: - case BOOT_FLASH_EMMC: -@@ -788,6 +891,7 @@ enum env_location env_get_location(enum env_operation op, int prio) - #endif - #ifdef CONFIG_ENV_IS_IN_UBI - case BOOT_FLASH_NAND: -+ case BOOT_FLASH_SPINAND: - return ENVL_UBI; - #endif - #ifdef CONFIG_ENV_IS_IN_SPI_FLASH -@@ -822,105 +926,12 @@ const char *env_ext4_get_dev_part(void) - } - #endif - --#ifdef CONFIG_SYS_MTDPARTS_RUNTIME -- --#define MTDPARTS_LEN 256 --#define MTDIDS_LEN 128 -- --/** -- * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long. -- * If we need to access it before the env is relocated, then we need -- * to use our own stack buffer. gd->env_buf will be too small. -- * -- * @param buf temporary buffer pointer MTDPARTS_LEN long -- * @return mtdparts variable string, NULL if not found -- */ --static const char *env_get_mtdparts(const char *str, char *buf) -+#if defined(CONFIG_ENV_IS_IN_MMC) -+int mmc_get_env_dev(void) - { -- if (gd->flags & GD_FLG_ENV_READY) -- return env_get(str); -- if (env_get_f(str, buf, MTDPARTS_LEN) != -1) -- return buf; -- -- return NULL; --} -- --/** -- * update the variables "mtdids" and "mtdparts" with content of mtdparts_ -- */ --static void board_get_mtdparts(const char *dev, -- char *mtdids, -- char *mtdparts) --{ -- char env_name[32] = "mtdparts_"; -- char tmp_mtdparts[MTDPARTS_LEN]; -- const char *tmp; -- -- /* name of env variable to read = mtdparts_ */ -- strcat(env_name, dev); -- tmp = env_get_mtdparts(env_name, tmp_mtdparts); -- if (tmp) { -- /* mtdids: "=, ...." */ -- if (mtdids[0] != '\0') -- strcat(mtdids, ","); -- strcat(mtdids, dev); -- strcat(mtdids, "="); -- strcat(mtdids, dev); -- -- /* mtdparts: "mtdparts=:>;..." */ -- if (mtdparts[0] != '\0') -- strncat(mtdparts, ";", MTDPARTS_LEN); -- else -- strcat(mtdparts, "mtdparts="); -- strncat(mtdparts, dev, MTDPARTS_LEN); -- strncat(mtdparts, ":", MTDPARTS_LEN); -- strncat(mtdparts, tmp, MTDPARTS_LEN); -- } --} -- --void board_mtdparts_default(const char **mtdids, const char **mtdparts) --{ -- struct mtd_info *mtd; -- struct udevice *dev; -- static char parts[3 * MTDPARTS_LEN + 1]; -- static char ids[MTDIDS_LEN + 1]; -- static bool mtd_initialized; -- -- if (mtd_initialized) { -- *mtdids = ids; -- *mtdparts = parts; -- return; -- } -- -- memset(parts, 0, sizeof(parts)); -- memset(ids, 0, sizeof(ids)); -- -- /* probe all MTD devices */ -- for (uclass_first_device(UCLASS_MTD, &dev); -- dev; -- uclass_next_device(&dev)) { -- pr_debug("mtd device = %s\n", dev->name); -- } -- -- mtd = get_mtd_device_nm("nand0"); -- if (!IS_ERR_OR_NULL(mtd)) { -- board_get_mtdparts("nand0", ids, parts); -- put_mtd_device(mtd); -- } -- -- mtd = get_mtd_device_nm("spi-nand0"); -- if (!IS_ERR_OR_NULL(mtd)) { -- board_get_mtdparts("spi-nand0", ids, parts); -- put_mtd_device(mtd); -- } -- -- if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) -- board_get_mtdparts("nor0", ids, parts); -+ u32 bootmode = get_bootmode(); - -- mtd_initialized = true; -- *mtdids = ids; -- *mtdparts = parts; -- debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts); -+ return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1; - } - #endif - -@@ -930,6 +941,7 @@ int ft_board_setup(void *blob, bd_t *bd) - #ifdef CONFIG_FDT_FIXUP_PARTITIONS - struct node_info nodes[] = { - { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, -+ { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND}, - { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, - }; - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -@@ -939,148 +951,6 @@ int ft_board_setup(void *blob, bd_t *bd) - } - #endif - --#ifdef CONFIG_SET_DFU_ALT_INFO --#define DFU_ALT_BUF_LEN SZ_1K -- --static void board_get_alt_info(const char *dev, char *buff) --{ -- char var_name[32] = "dfu_alt_info_"; -- int ret; -- -- ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN); -- -- /* name of env variable to read = dfu_alt_info_ */ -- strcat(var_name, dev); -- ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN); -- if (ret) { -- if (buff[0] != '\0') -- strcat(buff, "&"); -- strncat(buff, tmp_alt, DFU_ALT_BUF_LEN); -- } --} -- --void set_dfu_alt_info(char *interface, char *devstr) --{ -- struct udevice *dev; -- struct mtd_info *mtd; -- -- ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); -- -- if (env_get("dfu_alt_info")) -- return; -- -- memset(buf, 0, sizeof(buf)); -- -- /* probe all MTD devices */ -- mtd_probe_devices(); -- -- board_get_alt_info("ram", buf); -- -- if (!uclass_get_device(UCLASS_MMC, 0, &dev)) -- board_get_alt_info("mmc0", buf); -- -- if (!uclass_get_device(UCLASS_MMC, 1, &dev)) -- board_get_alt_info("mmc1", buf); -- -- if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) -- board_get_alt_info("nor0", buf); -- -- mtd = get_mtd_device_nm("nand0"); -- if (!IS_ERR_OR_NULL(mtd)) -- board_get_alt_info("nand0", buf); -- -- mtd = get_mtd_device_nm("spi-nand0"); -- if (!IS_ERR_OR_NULL(mtd)) -- board_get_alt_info("spi-nand0", buf); -- --#ifdef CONFIG_DFU_VIRT -- strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN); -- -- if (IS_ENABLED(CONFIG_PMIC_STPMIC1)) -- strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN); --#endif -- -- env_set("dfu_alt_info", buf); -- puts("DFU alt info setting: done\n"); --} -- --#if CONFIG_IS_ENABLED(DFU_VIRT) --#include --#include -- --int dfu_otp_read(u64 offset, u8 *buffer, long *size) --{ -- struct udevice *dev; -- int ret; -- -- ret = uclass_get_device_by_driver(UCLASS_MISC, -- DM_GET_DRIVER(stm32mp_bsec), -- &dev); -- if (ret) -- return ret; -- -- ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size); -- if (ret >= 0) { -- *size = ret; -- ret = 0; -- } -- -- return 0; --} -- --int dfu_pmic_read(u64 offset, u8 *buffer, long *size) --{ -- int ret; --#ifdef CONFIG_PMIC_STPMIC1 -- struct udevice *dev; -- -- ret = uclass_get_device_by_driver(UCLASS_MISC, -- DM_GET_DRIVER(stpmic1_nvm), -- &dev); -- if (ret) -- return ret; -- -- ret = misc_read(dev, 0xF8 + offset, buffer, *size); -- if (ret >= 0) { -- *size = ret; -- ret = 0; -- } -- if (ret == -EACCES) { -- *size = 0; -- ret = 0; -- } --#else -- pr_err("PMIC update not supported"); -- ret = -EOPNOTSUPP; --#endif -- -- return ret; --} -- --int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, -- void *buf, long *len) --{ -- switch (dfu->data.virt.dev_num) { -- case 0x0: -- return dfu_otp_read(offset, buf, len); -- case 0x1: -- return dfu_pmic_read(offset, buf, len); -- } -- *len = 0; -- return 0; --} -- --int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) --{ -- *size = SZ_1K; -- -- return 0; --} -- --#endif -- --#endif -- - static void board_copro_image_process(ulong fw_image, size_t fw_size) - { - int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ -@@ -1096,10 +966,8 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size) - printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", - id, fw_image, fw_size, ret ? " Failed!" : " Success!"); - -- if (!ret) { -+ if (!ret) - rproc_start(id); -- env_set("copro_state", "booted"); -- } - } - - U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); -diff --git a/board/sunxi/board.c b/board/sunxi/board.c -index b9450a0..f02141d 100644 ---- a/board/sunxi/board.c -+++ b/board/sunxi/board.c -@@ -706,7 +706,7 @@ int g_dnl_board_usb_cable_connected(void) - - ret = generic_phy_init(&phy); - if (ret) { -- pr_err("failed to init %s USB PHY\n", dev->name); -+ pr_debug("failed to init %s USB PHY\n", dev->name); - return ret; - } - -diff --git a/doc/board/index.rst b/doc/board/index.rst -index 00e72f5..21fddd2 100644 ---- a/doc/board/index.rst -+++ b/doc/board/index.rst -@@ -15,4 +15,5 @@ Board-specific doc - intel/index - renesas/index - sifive/index -+ st/index - xilinx/index -diff --git a/doc/board/st/index.rst b/doc/board/st/index.rst -new file mode 100644 -index 0000000..91f1d51 ---- /dev/null -+++ b/doc/board/st/index.rst -@@ -0,0 +1,9 @@ -+.. SPDX-License-Identifier: GPL-2.0+ -+ -+STMicroelectronics -+================== -+ -+.. toctree:: -+ :maxdepth: 2 -+ -+ stm32mp1 -diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst -new file mode 100644 -index 0000000..62de184 ---- /dev/null -+++ b/doc/board/st/stm32mp1.rst -@@ -0,0 +1,624 @@ -+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+.. sectionauthor:: Patrick Delaunay -+ -+STM32MP15x boards -+================= -+ -+This is a quick instruction for setup STM32MP15x boards. -+ -+Supported devices -+----------------- -+ -+U-Boot supports STMP32MP15x SoCs: -+ -+ - STM32MP157 -+ - STM32MP153 -+ - STM32MP151 -+ -+The STM32MP15x is a Cortex-A MPU aimed at various applications. -+ -+It features: -+ -+ - Dual core Cortex-A7 application core (Single on STM32MP151) -+ - 2D/3D image composition with GPU (only on STM32MP157) -+ - Standard memories interface support -+ - Standard connectivity, widely inherited from the STM32 MCU family -+ - Comprehensive security support -+ -+Each line comes with a security option (cryptography & secure boot) and -+a Cortex-A frequency option: -+ -+ - A : Cortex-A7 @ 650 MHz -+ - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz -+ - D : Cortex-A7 @ 800 MHz -+ - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz -+ -+Everything is supported in Linux but U-Boot is limited to: -+ -+ 1. UART -+ 2. SD card/MMC controller (SDMMC) -+ 3. NAND controller (FMC) -+ 4. NOR controller (QSPI) -+ 5. USB controller (OTG DWC2) -+ 6. Ethernet controller -+ -+And the necessary drivers -+ -+ 1. I2C -+ 2. STPMIC1 (PMIC and regulator) -+ 3. Clock, Reset, Sysreset -+ 4. Fuse -+ -+Currently the following boards are supported: -+ -+ + stm32mp157a-avenger96.dts -+ + stm32mp157a-dk1.dts -+ + stm32mp157a-ed1.dts -+ + stm32mp157a-ev1.dts -+ + stm32mp157c-dk2.dts -+ + stm32mp157c-ed1.dts -+ + stm32mp157c-ev1.dts -+ + stm32mp157d-dk1.dts -+ + stm32mp157d-ed1.dts -+ + stm32mp157d-ev1.dts -+ + stm32mp157f-dk2.dts -+ + stm32mp157f-ed1.dts -+ + stm32mp157f-ev1.dts -+ -+Boot Sequences -+-------------- -+ -+3 boot configurations are supported with: -+ -++----------+------------------------+-------------------------+--------------+ -+| **ROM** | **FSBL** | **SSBL** | **OS** | -++ **code** +------------------------+-------------------------+--------------+ -+| | First Stage Bootloader | Second Stage Bootloader | Linux Kernel | -++ +------------------------+-------------------------+--------------+ -+| | embedded RAM | DDR | -++----------+------------------------+-------------------------+--------------+ -+ -+The **Trusted** boot chain -+`````````````````````````` -+ -+defconfig_file : stm32mp15_trusted_defconfig -+ -+ +-------------+-------------------------+------------+-------+ -+ | ROM code | FSBL | SSBL | OS | -+ + +-------------------------+------------+-------+ -+ | |Trusted Firmware-A (TF-A)| U-Boot | Linux | -+ +-------------+-------------------------+------------+-------+ -+ | TrustZone |secure monitor | -+ +-------------+-------------------------+------------+-------+ -+ -+TF-A performs a full initialization of Secure peripherals and installs a -+secure monitor, BL32: -+ -+ * SPMin provided by TF-A or -+ * OP-TEE from specific partitions (teeh, teed, teex). -+ -+U-Boot is running in normal world and uses the secure monitor to access -+to secure resources. -+ -+The **Basic** boot chain -+```````````````````````` -+ -+defconfig_file : stm32mp15_basic_defconfig -+ -+ +-------------+------------+------------+-------+ -+ | ROM code | FSBL | SSBL | OS | -+ + +------------+------------+-------+ -+ | |U-Boot SPL | U-Boot | Linux | -+ +-------------+------------+------------+-------+ -+ | TrustZone | | PSCI from U-Boot | -+ +-------------+------------+------------+-------+ -+ -+SPL has limited security initialization -+ -+U-Boot is running in secure mode and provide a secure monitor to the kernel -+with only PSCI support (Power State Coordination Interface defined by ARM). -+ -+All the STM32MP15x boards supported by U-Boot use the same generic board -+stm32mp1 which support all the bootable devices. -+ -+Each board is configured only with the associated device tree. -+ -+Device Tree Selection -+--------------------- -+ -+You need to select the appropriate device tree for your board, -+the supported device trees for STM32MP15x are: -+ -++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) -+ -+ + stm32mp157a-ev1 -+ + stm32mp157c-ev1 -+ + stm32mp157d-ev1 -+ + stm32mp157f-ev1 -+ -++ ed1: daughter board with pmic stpmic1 -+ -+ + stm32mp157a-ed1 -+ + stm32mp157c-ed1 -+ + stm32mp157d-ed1 -+ + stm32mp157f-ed1 -+ -++ dk1: Discovery board -+ -+ + stm32mp157a-dk1 -+ + stm32mp157d-dk1 -+ -++ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel -+ -+ + stm32mp157c-dk2 -+ + stm32mp157f-dk2 -+ -++ avenger96: Avenger96 board from Arrow Electronics -+ -+ + stm32mp157a-avenger96 -+ -+Build Procedure -+--------------- -+ -+1. Install the required tools for U-Boot -+ -+ * install package needed in U-Boot makefile -+ (libssl-dev, swig, libpython-dev...) -+ -+ * install ARMv7 toolchain for 32bit Cortex-A (from Linaro, -+ from SDK for STM32MP15x, or any crosstoolchains from your distribution) -+ (you can use any gcc cross compiler compatible with U-Boot) -+ -+2. Set the cross compiler:: -+ -+ # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- -+ -+3. Select the output directory (optional):: -+ -+ # export KBUILD_OUTPUT=/path/to/output -+ -+ for example: use one output directory for each configuration:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_trusted -+ # export KBUILD_OUTPUT=stm32mp15_basic -+ -+ you can build outside of code directory:: -+ -+ # export KBUILD_OUTPUT=../build/stm32mp15_trusted -+ -+4. Configure U-Boot:: -+ -+ # make -+ -+ with : -+ -+ - For **trusted** boot mode : **stm32mp15_trusted_defconfig** -+ - For basic boot mode: stm32mp15_basic_defconfig -+ -+5. Configure the device-tree and build the U-Boot image:: -+ -+ # make DEVICE_TREE= all -+ -+ Examples: -+ -+ a) trusted boot on ev1:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_trusted -+ # make stm32mp15_trusted_defconfig -+ # make DEVICE_TREE=stm32mp157c-ev1 all -+ -+ b) trusted with OP-TEE boot on dk2:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_trusted -+ # make stm32mp15_trusted_defconfig -+ # make DEVICE_TREE=stm32mp157c-dk2 all -+ -+ c) basic boot on ev1:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_basic -+ # make stm32mp15_basic_defconfig -+ # make DEVICE_TREE=stm32mp157c-ev1 all -+ -+ d) basic boot on ed1:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_basic -+ # make stm32mp15_basic_defconfig -+ # make DEVICE_TREE=stm32mp157c-ed1 all -+ -+ e) basic boot on dk1:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_basic -+ # make stm32mp15_basic_defconfig -+ # make DEVICE_TREE=stm32mp157a-dk1 all -+ -+ f) basic boot on avenger96:: -+ -+ # export KBUILD_OUTPUT=stm32mp15_basic -+ # make stm32mp15_basic_defconfig -+ # make DEVICE_TREE=stm32mp157a-avenger96 all -+ -+6. Output files -+ -+ BootRom and TF-A expect binaries with STM32 image header -+ SPL expects file with U-Boot uImage header -+ -+ So in the output directory (selected by KBUILD_OUTPUT), -+ you can found the needed files: -+ -+ - For **Trusted** boot (with or without OP-TEE) -+ -+ - FSBL = **tf-a.stm32** (provided by TF-A compilation) -+ - SSBL = **u-boot.stm32** -+ -+ - For Basic boot -+ -+ - FSBL = spl/u-boot-spl.stm32 -+ - SSBL = u-boot.img -+ -+Switch Setting for Boot Mode -+---------------------------- -+ -+You can select the boot mode, on the board with one switch, to select -+the boot pin values = BOOT0, BOOT1, BOOT2 -+ -+ +-------------+---------+---------+---------+ -+ |*Boot Mode* | *BOOT2* | *BOOT1* | *BOOT0* | -+ +=============+=========+=========+=========+ -+ | Recovery | 0 | 0 | 0 | -+ +-------------+---------+---------+---------+ -+ | NOR | 0 | 0 | 1 | -+ +-------------+---------+---------+---------+ -+ | eMMC | 0 | 1 | 0 | -+ +-------------+---------+---------+---------+ -+ | NAND | 0 | 1 | 1 | -+ +-------------+---------+---------+---------+ -+ | Reserved | 1 | 0 | 0 | -+ +-------------+---------+---------+---------+ -+ | SD-Card | 1 | 0 | 1 | -+ +-------------+---------+---------+---------+ -+ | Recovery | 1 | 1 | 0 | -+ +-------------+---------+---------+---------+ -+ | SPI-NAND | 1 | 1 | 1 | -+ +-------------+---------+---------+---------+ -+ -+- on the **daugther board ed1 = MB1263** with the switch SW1 -+- on **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable) -+- on board **DK1/DK2** with the switch SW1 = BOOT0, BOOT2 -+ with only 2 pins available (BOOT1 is forced to 0 and NOR not supported), -+ the possible value becomes: -+ -+ +-------------+---------+---------+ -+ |*Boot Mode* | *BOOT2* | *BOOT0* | -+ +=============+=========+=========+ -+ | Recovery | 0 | 0 | -+ +-------------+---------+---------+ -+ | NOR (NA)| 0 | 1 | -+ +-------------+---------+---------+ -+ | Reserved | 1 | 0 | -+ +-------------+---------+---------+ -+ | SD-Card | 1 | 1 | -+ +-------------+---------+---------+ -+ -+Recovery is a boot from serial link (UART/USB) and it is used with -+STM32CubeProgrammer tool to load executable in RAM and to update the flash -+devices available on the board (NOR/NAND/eMMC/SD card). -+ -+The communication between HOST and board is based on -+ -+ - for UARTs : the uart protocol used with all MCU STM32 -+ - for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32) -+ -+Prepare an SD card -+------------------ -+ -+The minimal requirements for STMP32MP15x boot up to U-Boot are: -+ -+- GPT partitioning (with gdisk or with sgdisk) -+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB -+- one ssbl partition for U-Boot -+ -+Then the minimal GPT partition is: -+ -+ +-------+--------+---------+-------------+ -+ | *Num* | *Name* | *Size* | *Content* | -+ +=======+========+=========+=============+ -+ | 1 | fsbl1 | 256 KiB | TF-A or SPL | -+ +-------+--------+---------+-------------+ -+ | 2 | fsbl2 | 256 KiB | TF-A or SPL | -+ +-------+--------+---------+-------------+ -+ | 3 | ssbl | enought | U-Boot | -+ +-------+--------+---------+-------------+ -+ | 4 | | | Rootfs | -+ +-------+--------+---------+-------------+ -+ -+Add a 4th partition (Rootfs) marked bootable with a file extlinux.conf -+following the Generic Distribution feature (doc/README.distro for use). -+ -+According the used card reader select the correct block device -+(for example /dev/sdx or /dev/mmcblk0). -+ -+In the next example, it is /dev/mmcblk0 -+ -+For example: with gpt table with 128 entries -+ -+a) remove previous formatting:: -+ -+ # sgdisk -o /dev/ -+ -+b) create minimal image:: -+ -+ # sgdisk --resize-table=128 -a 1 \ -+ -n 1:34:545 -c 1:fsbl1 \ -+ -n 2:546:1057 -c 2:fsbl2 \ -+ -n 3:1058:5153 -c 3:ssbl \ -+ -n 4:5154: -c 4:rootfs \ -+ -p /dev/ -+ -+ With other partition for kernel one partition rootfs for kernel. -+ -+c) copy the FSBL (2 times) and SSBL file on the correct partition. -+ in this example in partition 1 to 3 -+ -+ for basic boot mode : = /dev/mmcblk0:: -+ -+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1 -+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2 -+ # dd if=u-boot.img of=/dev/mmcblk0p3 -+ -+ for trusted boot mode: :: -+ -+ # dd if=tf-a.stm32 of=/dev/mmcblk0p1 -+ # dd if=tf-a.stm32 of=/dev/mmcblk0p2 -+ # dd if=u-boot.stm32 of=/dev/mmcblk0p3 -+ -+To boot from SD card, select BootPinMode = 1 0 1 and reset. -+ -+Prepare eMMC -+------------ -+ -+You can use U-Boot to copy binary in eMMC. -+ -+In the next example, you need to boot from SD card and the images -+(u-boot-spl.stm32, u-boot.img) are presents on SD card (mmc 0) -+in ext4 partition 4 (bootfs). -+ -+To boot from SD card, select BootPinMode = 1 0 1 and reset. -+ -+Then you update the eMMC with the next U-Boot command : -+ -+a) prepare GPT on eMMC, -+ example with 2 partitions, bootfs and roots:: -+ -+ # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512" -+ # gpt write mmc 1 ${emmc_part} -+ -+b) copy SPL on eMMC on firts boot partition -+ (SPL max size is 256kB, with LBA 512, 0x200):: -+ -+ # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32 -+ # mmc dev 1 -+ # mmc partconf 1 1 1 1 -+ # mmc write ${fileaddr} 0 200 -+ # mmc partconf 1 1 1 0 -+ -+c) copy U-Boot in first GPT partition of eMMC:: -+ -+ # ext4load mmc 0:4 0xC0000000 u-boo t.img -+ # mmc dev 1 -+ # part start mmc 1 1 partstart -+ # mmc write ${fileaddr} ${partstart} ${filesize} -+ -+To boot from eMMC, select BootPinMode = 0 1 0 and reset. -+ -+MAC Address -+----------- -+ -+Please read doc/README.enetaddr for the implementation guidelines for mac id -+usage. Basically, environment has precedence over board specific storage. -+ -+For STMicroelectonics board, it is retrieved in STM32MP15x OTP : -+ -+ - OTP_57[31:0] = MAC_ADDR[31:0] -+ - OTP_58[15:0] = MAC_ADDR[47:32] -+ -+To program a MAC address on virgin OTP words above, you can use the fuse command -+on bank 0 to access to internal OTP and lock them: -+ -+Prerequisite: check if a MAC address isn't yet programmed in OTP -+ -+1) check OTP: their value must be equal to 0:: -+ -+ STM32MP> fuse sense 0 57 2 -+ Sensing bank 0: -+ Word 0x00000039: 00000000 00000000 -+ -+2) check environment variable:: -+ -+ STM32MP> env print ethaddr -+ ## Error: "ethaddr" not defined -+ -+3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked):: -+ -+ STM32MP> fuse sense 0 0x10000039 2 -+ Sensing bank 0: -+ Word 0x10000039: 00000000 00000000 -+ -+Example to set mac address "12:34:56:78:9a:bc" -+ -+1) Write OTP:: -+ -+ STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a -+ -+2) Read OTP:: -+ -+ STM32MP> fuse sense 0 57 2 -+ Sensing bank 0: -+ Word 0x00000039: 78563412 0000bc9a -+ -+3) Lock OTP:: -+ -+ STM32MP> fuse prog 0 0x10000039 1 1 -+ -+ STM32MP> fuse sense 0 0x10000039 2 -+ Sensing bank 0: -+ Word 0x10000039: 00000001 00000001 -+ -+4) next REBOOT, in the trace:: -+ -+ ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc" -+ -+5) check env update:: -+ -+ STM32MP> env print ethaddr -+ ethaddr=12:34:56:78:9a:bc -+ -+.. warning:: This command can't be executed twice on the same board as -+ OTP are protected. It is already done for the board -+ provided by STMicroelectronics. -+ -+Coprocessor firmware -+-------------------- -+ -+U-Boot can boot the coprocessor before the kernel (coprocessor early boot). -+ -+a) Manuallly by using rproc commands (update the bootcmd) -+ -+ Configurations:: -+ -+ # env set name_copro "rproc-m4-fw.elf" -+ # env set dev_copro 0 -+ # env set loadaddr_copro 0xC1000000 -+ -+ Load binary from bootfs partition (number 4) on SD card (mmc 0):: -+ -+ # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro} -+ -+ => ${filesize} variable is updated with the size of the loaded file. -+ -+ Start M4 firmware with remote proc command:: -+ -+ # rproc init -+ # rproc load ${dev_copro} ${loadaddr_copro} ${filesize} -+ # rproc start ${dev_copro}"00270033 -+ -+b) Automatically by using FIT feature and generic DISTRO bootcmd -+ -+ see examples in the board stm32mp1 directory: fit_copro_kernel_dtb.its -+ -+ Generate FIT including kernel + device tree + M4 firmware with cfg with M4 boot:: -+ -+ $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb -+ -+ Then using DISTRO configuration file: see extlinux.conf to select the correct -+ configuration: -+ -+ - stm32mp157c-ev1-m4 -+ - stm32mp157c-dk2-m4 -+ -+DFU support -+----------- -+ -+The DFU is supported on ST board. -+ -+The env variable dfu_alt_info is automatically build, and all -+the memory present on the ST boards are exported. -+ -+The dfu mode is started by the command:: -+ -+ STM32MP> dfu 0 -+ -+On EV1 board, booting from SD card, without OP-TEE:: -+ -+ STM32MP> dfu 0 list -+ DFU alt settings list: -+ dev: RAM alt: 0 name: uImage layout: RAM_ADDR -+ dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR -+ dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR -+ dev: eMMC alt: 3 name: mmc0_fsbl1 layout: RAW_ADDR -+ dev: eMMC alt: 4 name: mmc0_fsbl2 layout: RAW_ADDR -+ dev: eMMC alt: 5 name: mmc0_ssbl layout: RAW_ADDR -+ dev: eMMC alt: 6 name: mmc0_bootfs layout: RAW_ADDR -+ dev: eMMC alt: 7 name: mmc0_vendorfs layout: RAW_ADDR -+ dev: eMMC alt: 8 name: mmc0_rootfs layout: RAW_ADDR -+ dev: eMMC alt: 9 name: mmc0_userfs layout: RAW_ADDR -+ dev: eMMC alt: 10 name: mmc1_boot1 layout: RAW_ADDR -+ dev: eMMC alt: 11 name: mmc1_boot2 layout: RAW_ADDR -+ dev: eMMC alt: 12 name: mmc1_ssbl layout: RAW_ADDR -+ dev: eMMC alt: 13 name: mmc1_bootfs layout: RAW_ADDR -+ dev: eMMC alt: 14 name: mmc1_vendorfs layout: RAW_ADDR -+ dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR -+ dev: eMMC alt: 16 name: mmc1_userfs layout: RAW_ADDR -+ dev: MTD alt: 17 name: nor0 layout: RAW_ADDR -+ dev: MTD alt: 18 name: nand0 layout: RAW_ADDR -+ dev: VIRT alt: 19 name: OTP layout: RAW_ADDR -+ dev: VIRT alt: 20 name: PMIC layout: RAW_ADDR -+ -+All the supported device are exported for dfu-util tool:: -+ -+ $> dfu-util -l -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="PMIC", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="OTP", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nand0", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor0", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="mmc1_userfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="mmc1_vendorfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="mmc1_bootfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="mmc1_ssbl", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="mmc1_boot2", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="mmc1_boot1", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="mmc0_userfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="mmc0_rootfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="mmc0_vendorfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="mmc0_bootfs", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="mmc0_ssbl", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="mmc0_fsbl2", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="mmc0_fsbl1", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330" -+ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330" -+ -+You can update the boot device: -+ -+- SD card (mmc0) :: -+ -+ $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img -+ $> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 -+ -+- EMMC (mmc1):: -+ -+ $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img -+ $> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 -+ $> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 -+ -+- you can also dump the OTP and the PMIC NVM with:: -+ -+ $> dfu-util -d 0483:5720 -a 19 -U otp.bin -+ $> dfu-util -d 0483:5720 -a 20 -U pmic.bin -+ -+ -+When the board is booting for nor0 or nand0, -+only the MTD partition on the boot devices are available, for example: -+ -+- NOR (nor0 = alt 20) & NAND (nand0 = alt 26) :: -+ -+ $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img -+ $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi -+ -+- NAND (nand0 = alt 21):: -+ -+ $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32 -+ $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img -+ $> dfu-util -d 0483:5720 -a 24 -D u-boot-stm32mp157c-ev1-trusted.img -+ $> dfu-util -d 0483:5720 -a 25 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi --- -2.7.4 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.10-stm32mp-r1-BOARD.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.10-stm32mp-r1-BOARD.patch new file mode 100644 index 0000000..596e94f --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0002-ARM-v2020.10-stm32mp-r1-BOARD.patch @@ -0,0 +1,811 @@ +From f792f9d20e0a99373263c540b271adc8143de743 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Tue, 16 Mar 2021 08:16:11 +0100 +Subject: [PATCH 2/5] ARM v2020.10-stm32mp-r1 BOARD + +Signed-off-by: Romuald JEANNE +--- + board/st/common/Kconfig | 21 +++- + board/st/common/stm32mp_dfu.c | 9 +- + board/st/common/stm32mp_mtdparts.c | 47 +++++--- + board/st/stm32mp1/fit_copro_kernel_dtb.its | 18 ++- + board/st/stm32mp1/fit_kernel_dtb.its | 6 +- + board/st/stm32mp1/stm32mp1.c | 134 +++++++++++++-------- + doc/board/st/stm32mp1.rst | 124 +++++++++++-------- + 7 files changed, 227 insertions(+), 132 deletions(-) + +diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig +index ddcf33a122..2f57118bb2 100644 +--- a/board/st/common/Kconfig ++++ b/board/st/common/Kconfig +@@ -8,18 +8,22 @@ config CMD_STBOARD + + config MTDPARTS_NAND0_BOOT + string "mtd boot partitions for nand0" +- default "2m(fsbl),2m(ssbl1),2m(ssbl2)" ++ default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \ ++ !TFABOOT ++ default "2m(fsbl),4m(fip1),4m(fip2)" + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + help + This define the partitions of nand0 used to build mtparts dynamically + for boot from nand0. + Each partition need to be aligned with the device erase block size, + 512KB is the max size for the NAND supported by stm32mp1 platform. ++ The fsbl partition support multiple copy of the same binary, one by ++ erase block. + + config MTDPARTS_NAND0_TEE + string "mtd tee partitions for nand0" + default "512k(teeh),512k(teed),512k(teex)" +- depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP ++ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE + help + This define the tee partitions added in mtparts dynamically + when tee is supported with boot from nand0. +@@ -28,7 +32,9 @@ config MTDPARTS_NAND0_TEE + + config MTDPARTS_NOR0_BOOT + string "mtd boot partitions for nor0" +- default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" ++ default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if STM32MP15x_STM32IMAGE || \ ++ !TFABOOT ++ default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)" + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + help + This define the partitions of nand0 used to build mtparts dynamically +@@ -40,24 +46,27 @@ config MTDPARTS_NOR0_BOOT + config MTDPARTS_NOR0_TEE + string "mtd tee partitions for nor0" + default "256k(teeh),512k(teed),256k(teex)" +- depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP ++ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE + help + This define the tee partitions added in mtparts dynamically + when tee is supported with boot from nor0. + + config MTDPARTS_SPINAND0_BOOT + string "mtd boot partitions for spi-nand0" +- default "2m(fsbl),2m(ssbl1),2m(ssbl2)" ++ default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || !TFABOOT ++ default "2m(fsbl),4m(fip1),4m(fip2)" + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + help + This define the partitions of nand0 used to build mtparts dynamically + for boot from spi-nand0, + 512KB is the max size for the NAND supported by stm32mp1 platform. ++ The fsbl partition support multiple copy of the same binary, one by ++ erase block. + + config MTDPARTS_SPINAND0_TEE + string "mtd tee partitions for spi-nand0" + default "512k(teeh),512k(teed),512k(teex)" +- depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP ++ depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE + help + This define the tee partitions added in mtparts dynamically + when tee is supported with boot from spi-nand0, +diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c +index aab7d741ac..09913f6ec7 100644 +--- a/board/st/common/stm32mp_dfu.c ++++ b/board/st/common/stm32mp_dfu.c +@@ -142,7 +142,8 @@ void set_dfu_alt_info(char *interface, char *devstr) + board_get_alt_info_mtd(mtd, buf); + } + +- if (IS_ENABLED(CONFIG_DFU_VIRT)) { ++ if (IS_ENABLED(CONFIG_DFU_VIRT) && ++ IS_ENABLED(CMD_STM32PROG_USB)) { + strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN); + + if (IS_ENABLED(CONFIG_PMIC_STPMIC1)) +@@ -216,7 +217,7 @@ int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, + return dfu_pmic_read(offset, buf, len); + } + +- if (CONFIG_IS_ENABLED(CMD_STM32PROG) && ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && + dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) + return stm32prog_read_medium_virt(dfu, offset, buf, len); + +@@ -227,7 +228,7 @@ int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, + int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) + { +- if (CONFIG_IS_ENABLED(CMD_STM32PROG) && ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && + dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) + return stm32prog_write_medium_virt(dfu, offset, buf, len); + +@@ -236,7 +237,7 @@ int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, + + int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) + { +- if (CONFIG_IS_ENABLED(CMD_STM32PROG) && ++ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && + dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM) + return stm32prog_get_medium_size_virt(dfu, size); + +diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c +index 9f5897f8c8..baddadc3a5 100644 +--- a/board/st/common/stm32mp_mtdparts.c ++++ b/board/st/common/stm32mp_mtdparts.c +@@ -10,7 +10,9 @@ + #include + #include + #include ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + #include ++#endif + #include + #include + +@@ -29,7 +31,9 @@ static void board_set_mtdparts(const char *dev, + char *mtdids, + char *mtdparts, + const char *boot, ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + const char *tee, ++#endif + const char *user) + { + /* mtdids: "=, ...." */ +@@ -53,10 +57,12 @@ static void board_set_mtdparts(const char *dev, + strncat(mtdparts, ",", MTDPARTS_LEN); + } + ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + if (tee) { + strncat(mtdparts, tee, MTDPARTS_LEN); + strncat(mtdparts, ",", MTDPARTS_LEN); + } ++#endif + + strncat(mtdparts, user, MTDPARTS_LEN); + } +@@ -68,7 +74,10 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + static char parts[3 * MTDPARTS_LEN + 1]; + static char ids[MTDIDS_LEN + 1]; + static bool mtd_initialized; +- bool tee, nor, nand, spinand, serial; ++ bool nor, nand, spinand, serial; ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ bool tee = false; ++#endif + + if (mtd_initialized) { + *mtdids = ids; +@@ -76,7 +85,6 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + return; + } + +- tee = false; + nor = false; + nand = false; + spinand = false; +@@ -87,7 +95,9 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + case BOOT_SERIAL_USB: + serial = true; + if (CONFIG_IS_ENABLED(CMD_STM32PROG)) { ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + tee = stm32prog_get_tee_partitions(); ++#endif + nor = stm32prog_get_fsbl_nor(); + } + nand = true; +@@ -106,9 +116,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + break; + } + ++#ifdef CONFIG_STM32MP15x_STM32IMAGE + if (!serial && CONFIG_IS_ENABLED(OPTEE) && + tee_find_device(NULL, NULL, NULL, NULL)) + tee = true; ++#endif + + memset(parts, 0, sizeof(parts)); + memset(ids, 0, sizeof(ids)); +@@ -120,29 +132,27 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + pr_debug("mtd device = %s\n", dev->name); + } + +- if (nor || nand) { ++ if (nand) { + mtd = get_mtd_device_nm("nand0"); + if (!IS_ERR_OR_NULL(mtd)) { +- const char *mtd_boot = CONFIG_MTDPARTS_NAND0_BOOT; +- const char *mtd_tee = CONFIG_MTDPARTS_NAND0_TEE; +- + board_set_mtdparts("nand0", ids, parts, +- !nor ? mtd_boot : NULL, +- !nor && tee ? mtd_tee : NULL, ++ CONFIG_MTDPARTS_NAND0_BOOT, ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ !nor && tee ? CONFIG_MTDPARTS_NAND0_TEE : NULL, ++#endif + "-(UBI)"); + put_mtd_device(mtd); + } + } + +- if (nor || spinand) { ++ if (spinand) { + mtd = get_mtd_device_nm("spi-nand0"); + if (!IS_ERR_OR_NULL(mtd)) { +- const char *mtd_boot = CONFIG_MTDPARTS_SPINAND0_BOOT; +- const char *mtd_tee = CONFIG_MTDPARTS_SPINAND0_TEE; +- + board_set_mtdparts("spi-nand0", ids, parts, +- !nor ? mtd_boot : NULL, +- !nor && tee ? mtd_tee : NULL, ++ CONFIG_MTDPARTS_SPINAND0_BOOT, ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ !nor && tee ? CONFIG_MTDPARTS_SPINAND0_TEE : NULL, ++#endif + "-(UBI)"); + put_mtd_device(mtd); + } +@@ -150,12 +160,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) + + if (nor) { + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { +- const char *mtd_boot = CONFIG_MTDPARTS_NOR0_BOOT; +- const char *mtd_tee = CONFIG_MTDPARTS_NOR0_TEE; +- + board_set_mtdparts("nor0", ids, parts, +- mtd_boot, +- tee ? mtd_tee : NULL, ++ CONFIG_MTDPARTS_NOR0_BOOT, ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ tee ? CONFIG_MTDPARTS_NOR0_TEE : NULL, ++#endif + "-(nor_user)"); + } + } +diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its +index 3e08fd943e..dc43639af4 100644 +--- a/board/st/stm32mp1/fit_copro_kernel_dtb.its ++++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its +@@ -1,6 +1,20 @@ + /* + * Compilation: + * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb ++ * ++ * M4 firmware to load with remoteproc: rproc-m4-fw.elf ++ * ++ * Files in linux build dir: ++ * - arch/arm/boot/zImage ++ * - arch/arm/boot/dts/stm32mp157c-dk2.dtb ++ * - arch/arm/boot/dts/stm32mp157c-ev1.dtb ++ * ++ * load mmc 0:4 $kernel_addr_r fit_copro_kernel_dtb.itb ++ * bootm $kernel_addr_r ++ * bootm $kernel_addr_r#dk2 ++ * bootm $kernel_addr_r#ev1 ++ * bootm $kernel_addr_r#dk2-m4 ++ * bootm $kernel_addr_r#ev1-m4 + */ + + /dts-v1/; +@@ -29,8 +43,8 @@ + arch = "arm"; + os = "linux"; + compression = "none"; +- load = <0xC0008000>; +- entry = <0xC0008000>; ++ load = <0xC4000000>; ++ entry = <0xC4000000>; + hash-1 { + algo = "sha1"; + }; +diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its +index 18d03ebf3c..8456a3c460 100644 +--- a/board/st/stm32mp1/fit_kernel_dtb.its ++++ b/board/st/stm32mp1/fit_kernel_dtb.its +@@ -3,7 +3,7 @@ + * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb + * + * Files in linux build dir: +- * - arch/arm/boot/zImage ++ * - arch/arm/boot/Image (gzipped in Image.gz) + * - arch/arm/boot/dts/stm32mp157c-dk2.dtb + * - arch/arm/boot/dts/stm32mp157c-ev1.dtb + * +@@ -23,11 +23,11 @@ + images { + kernel { + description = "Linux kernel"; +- data = /incbin/("zImage"); ++ data = /incbin/("Image.gz"); + type = "kernel"; + arch = "arm"; + os = "linux"; +- compression = "none"; ++ compression = "gzip"; + load = <0xC0008000>; + entry = <0xC0008000>; + hash-1 { +diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c +index 3b677d339b..9a02e14ba5 100644 +--- a/board/st/stm32mp1/stm32mp1.c ++++ b/board/st/stm32mp1/stm32mp1.c +@@ -101,7 +101,9 @@ int checkboard(void) + const char *fdt_compat; + int fdt_compat_len; + +- if (IS_ENABLED(CONFIG_TFABOOT)) ++ if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE)) ++ mode = "trusted - stm32image"; ++ else if (IS_ENABLED(CONFIG_TFABOOT)) + mode = "trusted"; + else + mode = "basic"; +@@ -288,42 +290,13 @@ static void __maybe_unused led_error_blink(u32 nb_blink) + hang(); + } + +-static int board_check_usb_power(void) ++static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV) + { + struct ofnode_phandle_args adc_args; + struct udevice *adc; +- ofnode node; + unsigned int raw; +- int max_uV = 0; +- int min_uV = USB_START_HIGH_THRESHOLD_UV; +- int ret, uV, adc_count; +- u32 nb_blink; +- u8 i; +- +- if (!IS_ENABLED(CONFIG_ADC)) +- return -ENODEV; +- +- node = ofnode_path("/config"); +- if (!ofnode_valid(node)) { +- debug("%s: no /config node?\n", __func__); +- return -ENOENT; +- } +- +- /* +- * Retrieve the ADC channels devices and get measurement +- * for each of them +- */ +- adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", +- "#io-channel-cells"); +- if (adc_count < 0) { +- if (adc_count == -ENOENT) +- return 0; +- +- pr_err("%s: can't find adc channel (%d)\n", __func__, +- adc_count); +- +- return adc_count; +- } ++ int ret, uV; ++ int i; + + for (i = 0; i < adc_count; i++) { + if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd", +@@ -352,10 +325,10 @@ static int board_check_usb_power(void) + } + /* Convert to uV */ + if (!adc_raw_to_uV(adc, raw, &uV)) { +- if (uV > max_uV) +- max_uV = uV; +- if (uV < min_uV) +- min_uV = uV; ++ if (uV > *max_uV) ++ *max_uV = uV; ++ if (uV < *min_uV) ++ *min_uV = uV; + pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__, + adc->name, adc_args.args[0], raw, uV); + } else { +@@ -364,18 +337,66 @@ static int board_check_usb_power(void) + } + } + ++ return 0; ++} ++ ++static int board_check_usb_power(void) ++{ ++ ofnode node; ++ int max_uV = 0; ++ int min_uV = USB_START_HIGH_THRESHOLD_UV; ++ int adc_count, ret; ++ u32 nb_blink; ++ u8 i; ++ ++ if (!IS_ENABLED(CONFIG_ADC)) ++ return -ENODEV; ++ ++ node = ofnode_path("/config"); ++ if (!ofnode_valid(node)) { ++ debug("%s: no /config node?\n", __func__); ++ return -ENOENT; ++ } ++ + /* +- * If highest value is inside 1.23 Volts and 2.10 Volts, that means +- * board is plugged on an USB-C 3A power supply and boot process can +- * continue. ++ * Retrieve the ADC channels devices and get measurement ++ * for each of them + */ +- if (max_uV > USB_START_LOW_THRESHOLD_UV && +- max_uV <= USB_START_HIGH_THRESHOLD_UV && +- min_uV <= USB_LOW_THRESHOLD_UV) +- return 0; ++ adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", ++ "#io-channel-cells"); ++ if (adc_count < 0) { ++ if (adc_count == -ENOENT) ++ return 0; + +- pr_err("****************************************************\n"); ++ pr_err("%s: can't find adc channel (%d)\n", __func__, ++ adc_count); ++ ++ return adc_count; ++ } ++ ++ /* perform maximum of 2 ADC measurement to detect power supply current */ ++ for (i = 0; i < 2; i++) { ++ ret = adc_measurement(node, adc_count, &min_uV, &max_uV); ++ if (ret) ++ return ret; ++ ++ /* ++ * If highest value is inside 1.23 Volts and 2.10 Volts, that means ++ * board is plugged on an USB-C 3A power supply and boot process can ++ * continue. ++ */ ++ if (max_uV > USB_START_LOW_THRESHOLD_UV && ++ max_uV <= USB_START_HIGH_THRESHOLD_UV && ++ min_uV <= USB_LOW_THRESHOLD_UV) ++ return 0; + ++ if (i == 0) { ++ pr_debug("Previous ADC measurements was not the one expected, retry in 20ms\n"); ++ mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */ ++ } ++ } ++ ++ pr_err("****************************************************\n"); + /* + * If highest and lowest value are either both below + * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that +@@ -583,7 +604,8 @@ error: + static bool board_is_dk2(void) + { + if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && +- of_machine_is_compatible("st,stm32mp157c-dk2")) ++ (of_machine_is_compatible("st,stm32mp157c-dk2") || ++ of_machine_is_compatible("st,stm32mp157f-dk2"))) + return true; + + return false; +@@ -832,10 +854,17 @@ const char *env_ext4_get_dev_part(void) + + return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1]; + } ++ + int mmc_get_env_dev(void) + { +- u32 bootmode = get_bootmode(); ++ u32 bootmode; ++ ++ if (CONFIG_SYS_MMC_ENV_DEV >= 0) ++ return CONFIG_SYS_MMC_ENV_DEV; + ++ bootmode = get_bootmode(); ++ ++ /* use boot instance to select the correct mmc device identifier */ + return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1; + } + +@@ -848,9 +877,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) + { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, + { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, + }; +- +- if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) +- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); ++ char *boot_device; ++ ++ /* Check the boot-source and don't update MTD for serial or usb boot */ ++ boot_device = env_get("boot_device"); ++ if (!boot_device || ++ (strcmp(boot_device, "serial") && strcmp(boot_device, "usb"))) ++ if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) ++ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + return 0; + } +diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst +index e74f7afdae..ad95e12068 100644 +--- a/doc/board/st/stm32mp1.rst ++++ b/doc/board/st/stm32mp1.rst +@@ -52,15 +52,23 @@ And the necessary drivers + Currently the following boards are supported: + + + stm32mp157a-dk1.dts ++ + stm32mp157a-ed1.dts ++ + stm32mp157a-ev1.dts + + stm32mp157c-dk2.dts + + stm32mp157c-ed1.dts + + stm32mp157c-ev1.dts ++ + stm32mp157d-dk1.dts ++ + stm32mp157d-ed1.dts ++ + stm32mp157d-ev1.dts ++ + stm32mp157f-dk2.dts ++ + stm32mp157f-ed1.dts ++ + stm32mp157f-ev1.dts + + stm32mp15xx-dhcor-avenger96.dts + + Boot Sequences + -------------- + +-3 boot configurations are supported with: ++2 boot configurations are supported with: + + +----------+------------------------+-------------------------+--------------+ + | **ROM** | **FSBL** | **SSBL** | **OS** | +@@ -83,14 +91,10 @@ defconfig_file : stm32mp15_trusted_defconfig + | TrustZone |secure monitor | + +-------------+-------------------------+------------+-------+ + +-TF-A performs a full initialization of Secure peripherals and installs a +-secure monitor, BL32: +- +- * SPMin provided by TF-A or +- * OP-TEE from specific partitions (teeh, teed, teex). +- +-U-Boot is running in normal world and uses the secure monitor to access +-to secure resources. ++TF-A (BL2) initialize the DDR and loads the next stage binaries from a FIP file: ++ + BL32: a secure monitor BL32 = SPMin provided by TF-A or OP-TEE : performs a full initialization of Secure peripherals and provides service to normal world ++ + BL33: a non-trusted firmware = U-Boot, running in normal world and uses the secure monitor to access to secure resources. ++ + HW_CONFIG: The hardware configuration file = the U-Boot device tree + + The **Basic** boot chain + ```````````````````````` +@@ -123,19 +127,27 @@ the supported device trees for STM32MP15x are: + + + ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) + ++ + stm32mp157a-ev1 + + stm32mp157c-ev1 ++ + stm32mp157d-ev1 ++ + stm32mp157f-ev1 + + + ed1: daughter board with pmic stpmic1 + ++ + stm32mp157a-ed1 + + stm32mp157c-ed1 ++ + stm32mp157d-ed1 ++ + stm32mp157f-ed1 + + + dk1: Discovery board + + + stm32mp157a-dk1 ++ + stm32mp157d-dk1 + + + dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel + + + stm32mp157c-dk2 ++ + stm32mp157f-dk2 + + + avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM + +@@ -223,16 +235,24 @@ Build Procedure + + 6. Output files + +- BootRom and TF-A expect binaries with STM32 image header +- SPL expects file with U-Boot uImage header ++ The ROM code expects FSBL binaries with STM32 image header. ++ TF-A expect a FIP binary, with OS monitor (SPmin or OP-TEE) and with U-Boot binary + device tree. ++ SPL expects file with U-Boot uImage header. + + So in the output directory (selected by KBUILD_OUTPUT), + you can found the needed files: + + - For **Trusted** boot (with or without OP-TEE) + +- - FSBL = **tf-a.stm32** (provided by TF-A compilation) +- - SSBL = **u-boot.stm32** ++ - FSBL = **tf-a.stm32** and **tf-a-fip.bin** (provided by TF-A compilation) ++ - SSBL = **u-boot-nodtb.bin** and **u-boot.dtb** ++ ++ The file tf-a-fip.bin includes the 2 U-Boot files, u-boot-nodtb.bin and u-boot.dtb; ++ they are needed during the TF-A compilation(BL33=u-boot-nodtb.bin BL33_CFG=u-boot.dtb). ++ ++ You can also update a existing it with the tools provided by TF-A: ++ ++ # fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb tf-a-fip-stm32mp157c-ev1.bin + + - For Basic boot + +@@ -298,22 +318,24 @@ Prepare an SD card + The minimal requirements for STMP32MP15x boot up to U-Boot are: + + - GPT partitioning (with gdisk or with sgdisk) +-- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB +-- one ssbl partition for U-Boot ++- 2 fsbl partitions, named "fsbl1" and "fsbl2", size at least 256KiB ++- one partition named "fip" for FIP or U-Boot (TF-A search the "fip" ++ partition and SPL search the 3th partition, because ++ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3) + + Then the minimal GPT partition is: + +- +-------+--------+---------+-------------+ +- | *Num* | *Name* | *Size* | *Content* | +- +=======+========+=========+=============+ +- | 1 | fsbl1 | 256 KiB | TF-A or SPL | +- +-------+--------+---------+-------------+ +- | 2 | fsbl2 | 256 KiB | TF-A or SPL | +- +-------+--------+---------+-------------+ +- | 3 | ssbl | enought | U-Boot | +- +-------+--------+---------+-------------+ +- | 4 | | | Rootfs | +- +-------+--------+---------+-------------+ ++ +-------+--------+---------+------------------------------+ ++ | *Num* | *Name* | *Size* | *Content* | ++ +=======+========+=========+==============================+ ++ | 1 | fsbl1 | 256 KiB | TF-A BL2 (tf-a.stm32) or SPL | ++ +-------+--------+---------+------------------------------+ ++ | 2 | fsbl2 | 256 KiB | TF-A BL2 (tf-a.stm32) or SPL | ++ +-------+--------+---------+------------------------------+ ++ | 3 | fip | enought | tf-a-fip.bin or u-boot.img | ++ +-------+--------+---------+------------------------------+ ++ | 4 | | | Rootfs | ++ +-------+--------+---------+------------------------------+ + + Add a 4th partition (Rootfs) marked bootable with a file extlinux.conf + following the Generic Distribution feature (doc/README.distro for use). +@@ -334,7 +356,7 @@ b) create minimal image:: + # sgdisk --resize-table=128 -a 1 \ + -n 1:34:545 -c 1:fsbl1 \ + -n 2:546:1057 -c 2:fsbl2 \ +- -n 3:1058:5153 -c 3:ssbl \ ++ -n 3:1058:5153 -c 3:fip \ + -n 4:5154: -c 4:rootfs \ + -p /dev/ + +@@ -353,7 +375,7 @@ c) copy the FSBL (2 times) and SSBL file on the correct partition. + + # dd if=tf-a.stm32 of=/dev/mmcblk0p1 + # dd if=tf-a.stm32 of=/dev/mmcblk0p2 +- # dd if=u-boot.stm32 of=/dev/mmcblk0p3 ++ # dd if=tf-a-fip.bin of=/dev/mmcblk0p3 + + To boot from SD card, select BootPinMode = 1 0 1 and reset. + +@@ -363,8 +385,8 @@ Prepare eMMC + You can use U-Boot to copy binary in eMMC. + + In the next example, you need to boot from SD card and the images +-(u-boot-spl.stm32, u-boot.img) are presents on SD card (mmc 0) +-in ext4 partition 4 (bootfs). ++(tf-a.stm32, tf-a-fip.bin / u-boot-spl.stm32, u-boot.img) are presents ++on SD card (mmc 0) in ext4 partition 4 (bootfs). + + To boot from SD card, select BootPinMode = 1 0 1 and reset. + +@@ -373,13 +395,16 @@ Then you update the eMMC with the next U-Boot command : + a) prepare GPT on eMMC, + example with 2 partitions, bootfs and roots:: + +- # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512" ++ # setenv emmc_part "name=fip,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512" + # gpt write mmc 1 ${emmc_part} + + b) copy SPL on eMMC on firts boot partition + (SPL max size is 256kB, with LBA 512, 0x200):: + ++ # ext4load mmc 0:4 0xC0000000 tf-a.stm32 ++ or + # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32 ++ + # mmc dev 1 + # mmc partconf 1 1 1 1 + # mmc write ${fileaddr} 0 200 +@@ -387,7 +412,10 @@ b) copy SPL on eMMC on firts boot partition + + c) copy U-Boot in first GPT partition of eMMC:: + +- # ext4load mmc 0:4 0xC0000000 u-boo t.img ++ # ext4load mmc 0:4 0xC0000000 tf-a-fip.bin ++ or ++ # ext4load mmc 0:4 0xC0000000 u-boot.img ++ + # mmc dev 1 + # part start mmc 1 1 partstart + # mmc write ${fileaddr} ${partstart} ${filesize} +@@ -520,14 +548,14 @@ On EV1 board, booting from SD card, without OP-TEE:: + dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR + dev: eMMC alt: 3 name: mmc0_fsbl1 layout: RAW_ADDR + dev: eMMC alt: 4 name: mmc0_fsbl2 layout: RAW_ADDR +- dev: eMMC alt: 5 name: mmc0_ssbl layout: RAW_ADDR ++ dev: eMMC alt: 5 name: mmc0_fip layout: RAW_ADDR + dev: eMMC alt: 6 name: mmc0_bootfs layout: RAW_ADDR + dev: eMMC alt: 7 name: mmc0_vendorfs layout: RAW_ADDR + dev: eMMC alt: 8 name: mmc0_rootfs layout: RAW_ADDR + dev: eMMC alt: 9 name: mmc0_userfs layout: RAW_ADDR + dev: eMMC alt: 10 name: mmc1_boot1 layout: RAW_ADDR + dev: eMMC alt: 11 name: mmc1_boot2 layout: RAW_ADDR +- dev: eMMC alt: 12 name: mmc1_ssbl layout: RAW_ADDR ++ dev: eMMC alt: 12 name: mmc1_fip layout: RAW_ADDR + dev: eMMC alt: 13 name: mmc1_bootfs layout: RAW_ADDR + dev: eMMC alt: 14 name: mmc1_vendorfs layout: RAW_ADDR + dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR +@@ -548,14 +576,14 @@ All the supported device are exported for dfu-util tool:: + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="mmc1_vendorfs", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="mmc1_bootfs", serial="002700333338511934383330" +- Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="mmc1_ssbl", serial="002700333338511934383330" ++ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="mmc1_fip", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="mmc1_boot2", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="mmc1_boot1", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="mmc0_userfs", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="mmc0_rootfs", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="mmc0_vendorfs", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="mmc0_bootfs", serial="002700333338511934383330" +- Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="mmc0_ssbl", serial="002700333338511934383330" ++ Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="mmc0_fip", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="mmc0_fsbl2", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="mmc0_fsbl1", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330" +@@ -566,9 +594,9 @@ You can update the boot device: + + - SD card (mmc0) :: + +- $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img ++ $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 5 -D tf-a-fip-stm32mp157c-ev1.bin + $> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 + $> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 + $> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 +@@ -576,9 +604,9 @@ You can update the boot device: + + - EMMC (mmc1):: + +- $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img ++ $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 12 -D tf-a-fip-stm32mp157c-ev1.bin + $> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 + $> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 + $> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 +@@ -595,14 +623,14 @@ only the MTD partition on the boot devices are available, for example: + + - NOR (nor0 = alt 20) & NAND (nand0 = alt 26) :: + +- $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img ++ $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 23 -D tf-a-fip-stm32mp157c-ev1.bin + $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi + + - NAND (nand0 = alt 21):: + +- $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32 +- $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img +- $> dfu-util -d 0483:5720 -a 24 -D u-boot-stm32mp157c-ev1-trusted.img ++ $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1.stm32 ++ $> dfu-util -d 0483:5720 -a 23 -D tf-a-fip-stm32mp157c-ev1.bin ++ $> dfu-util -d 0483:5720 -a 24 -D tf-a-fip-stm32mp157c-ev1.bin + $> dfu-util -d 0483:5720 -a 25 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.01-stm32mp-r1-MISC-DRIVERS.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.01-stm32mp-r1-MISC-DRIVERS.patch deleted file mode 100644 index d13fb6b..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.01-stm32mp-r1-MISC-DRIVERS.patch +++ /dev/null @@ -1,9969 +0,0 @@ -From b3ad756bcf4959e8ec4c2cfdcd8d0eeeca12a845 Mon Sep 17 00:00:00 2001 -From: Romuald JEANNE -Date: Fri, 5 Jun 2020 13:45:13 +0200 -Subject: [PATCH 3/5] ARM v2020.01-stm32mp-r1 MISC-DRIVERS - ---- - cmd/Kconfig | 1 + - cmd/dtimg.c | 50 ++- - cmd/mtd.c | 24 +- - cmd/nvedit.c | 39 ++- - common/board_f.c | 27 +- - common/cli_readline.c | 6 + - common/image-android-dt.c | 42 +++ - configs/igep00x0_defconfig | 1 + - configs/mt8518_ap1_emmc_defconfig | 2 + - configs/odroid-xu3_defconfig | 1 + - configs/odroid_defconfig | 1 + - configs/sandbox64_defconfig | 1 + - configs/sandbox_defconfig | 1 + - configs/sandbox_flattree_defconfig | 1 + - configs/sandbox_spl_defconfig | 1 + - doc/README.gpio | 42 +++ - doc/android/fastboot.txt | 3 + - doc/device-tree-bindings/clock/st,stm32-rcc.txt | 37 ++ - doc/device-tree-bindings/clock/st,stm32mp1.txt | 36 +- - doc/device-tree-bindings/gpio/gpio.txt | 304 ++++++++++------- - doc/device-tree-bindings/i2c/i2c-stm32.txt | 105 +++++- - .../memory-controllers/st,stm32mp1-ddr.txt | 2 + - doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt | 6 +- - doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt | 55 ++- - drivers/ata/dwc_ahci.c | 4 +- - drivers/clk/Kconfig | 8 + - drivers/clk/Makefile | 1 + - drivers/clk/clk_scmi.c | 152 +++++++++ - drivers/clk/clk_stm32mp1.c | 378 +++++++++++++++++---- - drivers/core/of_access.c | 32 ++ - drivers/core/ofnode.c | 48 +++ - drivers/core/read.c | 16 + - drivers/core/root.c | 52 +-- - drivers/dfu/Kconfig | 5 + - drivers/fastboot/Kconfig | 68 ++++ - drivers/fastboot/fb_command.c | 72 ++++ - drivers/fastboot/fb_mmc.c | 118 +++++++ - drivers/gpio/gpio-uclass.c | 203 ++++++++--- - drivers/gpio/mpc8xxx_gpio.c | 22 -- - drivers/gpio/sandbox.c | 321 ++++++++++++++--- - drivers/gpio/stm32_gpio.c | 152 ++++++++- - drivers/i2c/stm32f7_i2c.c | 128 +++---- - drivers/mailbox/Kconfig | 7 + - drivers/mailbox/Makefile | 1 + - drivers/mailbox/arm-smc-mbox.c | 118 +++++++ - drivers/misc/Kconfig | 12 + - drivers/misc/Makefile | 1 + - drivers/misc/scmi_agent.c | 337 ++++++++++++++++++ - drivers/mmc/stm32_sdmmc2.c | 2 +- - drivers/mtd/Kconfig | 7 + - drivers/net/dwc_eth_qos.c | 73 +++- - drivers/phy/phy-stm32-usbphyc.c | 2 +- - drivers/phy/phy-uclass.c | 40 ++- - drivers/pinctrl/pinctrl-generic.c | 30 +- - drivers/pinctrl/pinctrl-sandbox.c | 44 ++- - drivers/pinctrl/pinctrl-single.c | 27 +- - drivers/pinctrl/pinctrl-stmfx.c | 232 +++++++++---- - drivers/pinctrl/pinctrl_stm32.c | 27 +- - drivers/power/regulator/stm32-vrefbuf.c | 16 +- - drivers/ram/stm32mp1/stm32mp1_ddr.c | 54 ++- - drivers/ram/stm32mp1/stm32mp1_ddr.h | 1 + - drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + - drivers/ram/stm32mp1/stm32mp1_interactive.c | 17 +- - drivers/ram/stm32mp1/stm32mp1_ram.c | 34 +- - drivers/ram/stm32mp1/stm32mp1_tests.c | 31 +- - drivers/ram/stm32mp1/stm32mp1_tuning.c | 223 ++++++++++-- - drivers/remoteproc/rproc-elf-loader.c | 269 +++++++++++++++ - drivers/remoteproc/stm32_copro.c | 61 +++- - drivers/reset/Kconfig | 8 + - drivers/reset/Makefile | 1 + - drivers/reset/reset-scmi.c | 86 +++++ - drivers/tee/optee/core.c | 13 +- - drivers/usb/dwc3/core.c | 12 +- - drivers/usb/gadget/dwc2_udc_otg.c | 6 +- - drivers/usb/gadget/g_dnl.c | 8 + - drivers/usb/host/dwc2.c | 118 ++++++- - drivers/usb/host/ehci-hcd.c | 8 +- - drivers/usb/host/ohci-generic.c | 8 +- - drivers/usb/musb-new/sunxi.c | 8 +- - drivers/video/orisetech_otm8009a.c | 20 +- - drivers/video/raydium-rm68200.c | 20 +- - drivers/video/stm32/stm32_dsi.c | 15 +- - env/mmc.c | 26 +- - include/asm-generic/gpio.h | 102 +++--- - include/clk.h | 104 +++++- - include/configs/odroid.h | 1 - - include/configs/odroid_xu3.h | 1 - - include/configs/omap3_igep00x0.h | 2 - - include/configs/stm32f429-evaluation.h | 15 +- - include/configs/stm32f469-discovery.h | 15 +- - include/configs/stm32f746-disco.h | 15 +- - include/configs/stm32h743-disco.h | 14 +- - include/configs/stm32h743-eval.h | 14 +- - include/configs/stm32mp1.h | 208 +++++++----- - include/dfu.h | 3 + - include/dm/of_access.h | 40 +++ - include/dm/ofnode.h | 63 +++- - include/dm/read.h | 67 ++++ - include/dt-bindings/clock/stm32mp1-clks.h | 33 ++ - include/dt-bindings/gpio/gpio.h | 6 + - include/dt-bindings/gpio/sandbox-gpio.h | 24 ++ - include/dt-bindings/mfd/stm32h7-rcc.h | 1 - - include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 + - include/dt-bindings/reset/stm32mp1-resets.h | 13 + - include/dt-bindings/rtc/rtc-stm32.h | 13 + - include/dt-bindings/soc/stm32-hdp.h | 108 ++++++ - include/env_internal.h | 31 ++ - include/fastboot.h | 6 + - include/g_dnl.h | 1 + - include/i2c.h | 26 ++ - include/image-android-dt.h | 2 + - include/mipi_dsi.h | 6 + - include/mtd.h | 2 + - include/power/stpmic1.h | 1 + - include/remoteproc.h | 70 ++++ - include/scmi_agent.h | 82 +++++ - lib/libfdt/fdt_ro.c | 20 +- - lib/optee/optee.c | 2 +- - scripts/config_whitelist.txt | 2 - - scripts/dtc/libfdt/fdt_ro.c | 20 +- - scripts/dtc/libfdt/libfdt.h | 33 +- - test/dm/Makefile | 1 + - test/dm/gpio.c | 69 +++- - test/dm/ofread.c | 50 +++ - test/dm/remoteproc.c | 91 ++++- - test/dm/test-fdt.c | 4 +- - test/py/tests/test_env.py | 44 +++ - test/py/tests/test_pinmux.py | 38 ++- - tools/fdtgrep.c | 6 +- - tools/stm32image.c | 5 +- - 130 files changed, 5029 insertions(+), 1038 deletions(-) - create mode 100644 doc/README.gpio - create mode 100644 drivers/clk/clk_scmi.c - create mode 100644 drivers/mailbox/arm-smc-mbox.c - create mode 100644 drivers/misc/scmi_agent.c - create mode 100644 drivers/reset/reset-scmi.c - create mode 100644 include/dt-bindings/gpio/sandbox-gpio.h - create mode 100644 include/dt-bindings/rtc/rtc-stm32.h - create mode 100644 include/dt-bindings/soc/stm32-hdp.h - create mode 100644 include/scmi_agent.h - create mode 100644 test/dm/ofread.c - -diff --git a/cmd/Kconfig b/cmd/Kconfig -index 1e4cf14..8a44461 100644 ---- a/cmd/Kconfig -+++ b/cmd/Kconfig -@@ -551,6 +551,7 @@ config CMD_NVEDIT_INFO - This command can be optionally used for evaluation in scripts: - [-d] : evaluate whether default environment is used - [-p] : evaluate whether environment can be persisted -+ [-q] : quiet output - The result of multiple evaluations will be combined with AND. - - endmenu -diff --git a/cmd/dtimg.c b/cmd/dtimg.c -index 6c5d53c..cd221b2 100644 ---- a/cmd/dtimg.c -+++ b/cmd/dtimg.c -@@ -99,10 +99,52 @@ static int do_dtimg_size(cmd_tbl_t *cmdtp, int flag, int argc, - return dtimg_get_fdt(argc, argv, CMD_DTIMG_SIZE); - } - -+static int do_dtimg_getindex(cmd_tbl_t *cmdtp, int flag, int argc, -+ char * const argv[]) -+{ -+ char *endp; -+ ulong hdr_addr; -+ int index; -+ char buf[512] = { 0 }; -+ -+ if (argc < 4) -+ return CMD_RET_USAGE; -+ -+ hdr_addr = simple_strtoul(argv[1], &endp, 16); -+ if (*endp != '\0') { -+ printf("Error: Wrong image address\n"); -+ return CMD_RET_FAILURE; -+ } -+ -+ if (!android_dt_check_header(hdr_addr)) { -+ printf("Error: DT image header is incorrect\n"); -+ return CMD_RET_FAILURE; -+ } -+ -+ index = android_dt_get_index(hdr_addr, strtoul(argv[2], NULL, 0), -+ strtoul(argv[3], NULL, 0)); -+ -+ if (index < 0) { -+ printf("Error: board id %04lx not found in DT table\n", -+ strtoul(argv[2], NULL, 0)); -+ return CMD_RET_FAILURE; -+ } -+ -+ snprintf(buf, sizeof(buf), "%i", index); -+ -+ if (argc == 5) -+ env_set(argv[4], buf); -+ else -+ printf("%s\n", buf); -+ -+ return CMD_RET_SUCCESS; -+} -+ - static cmd_tbl_t cmd_dtimg_sub[] = { - U_BOOT_CMD_MKENT(dump, 2, 0, do_dtimg_dump, "", ""), - U_BOOT_CMD_MKENT(start, 4, 0, do_dtimg_start, "", ""), - U_BOOT_CMD_MKENT(size, 4, 0, do_dtimg_size, "", ""), -+ U_BOOT_CMD_MKENT(getindex, 5, 0, do_dtimg_getindex, "", ""), - }; - - static int do_dtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -@@ -138,5 +180,11 @@ U_BOOT_CMD( - " - get size (hex, bytes) of FDT in the image, by index\n" - " : image address in RAM, in hex\n" - " : index of desired FDT in the image\n" -- " : name of variable where to store size of FDT" -+ " : name of variable where to store size of FDT\n" -+ "dtimg getindex [varname]\n" -+ " - get index of FDT in the image, by board identifier and revision\n" -+ " : image address in RAM, in hex\n" -+ " : board identifier\n" -+ " : board revision (0 if not used)\n" -+ " [varname]: name of variable where to store index of FDT" - ); -diff --git a/cmd/mtd.c b/cmd/mtd.c -index 1b6b8dd..a559b5a 100644 ---- a/cmd/mtd.c -+++ b/cmd/mtd.c -@@ -387,7 +387,7 @@ static int do_mtd_erase(cmd_tbl_t *cmdtp, int flag, int argc, - struct mtd_info *mtd; - u64 off, len; - bool scrub; -- int ret; -+ int ret = 0; - - if (argc < 2) - return CMD_RET_USAGE; -@@ -423,22 +423,22 @@ static int do_mtd_erase(cmd_tbl_t *cmdtp, int flag, int argc, - - erase_op.mtd = mtd; - erase_op.addr = off; -- erase_op.len = len; -+ erase_op.len = mtd->erasesize; - erase_op.scrub = scrub; - -- while (erase_op.len) { -+ while (len) { - ret = mtd_erase(mtd, &erase_op); - -- /* Abort if its not a bad block error */ -- if (ret != -EIO) -- break; -- -- printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr); -+ if (ret) { -+ /* Abort if its not a bad block error */ -+ if (ret != -EIO) -+ break; -+ printf("Skipping bad block at 0x%08llx\n", -+ erase_op.addr); -+ } - -- /* Skip bad block and continue behind it */ -- erase_op.len -= erase_op.fail_addr - erase_op.addr; -- erase_op.len -= mtd->erasesize; -- erase_op.addr = erase_op.fail_addr + mtd->erasesize; -+ len -= mtd->erasesize; -+ erase_op.addr += mtd->erasesize; - } - - if (ret && ret != -EIO) -diff --git a/cmd/nvedit.c b/cmd/nvedit.c -index 81d94cd..218fdfb 100644 ---- a/cmd/nvedit.c -+++ b/cmd/nvedit.c -@@ -1219,12 +1219,18 @@ static int print_env_info(void) - * env info - display environment information - * env info [-d] - evaluate whether default environment is used - * env info [-p] - evaluate whether environment can be persisted -+ * Add [-q] - quiet mode, use only for command result, for test by example: -+ * test env info -p -d -q - */ - static int do_env_info(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) - { - int eval_flags = 0; - int eval_results = 0; -+ bool quiet = false; -+#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) -+ enum env_location loc; -+#endif - - /* display environment information */ - if (argc <= 1) -@@ -1242,6 +1248,9 @@ static int do_env_info(cmd_tbl_t *cmdtp, int flag, - case 'p': - eval_flags |= ENV_INFO_IS_PERSISTED; - break; -+ case 'q': -+ quiet = true; -+ break; - default: - return CMD_RET_USAGE; - } -@@ -1251,20 +1260,30 @@ static int do_env_info(cmd_tbl_t *cmdtp, int flag, - /* evaluate whether default environment is used */ - if (eval_flags & ENV_INFO_IS_DEFAULT) { - if (gd->flags & GD_FLG_ENV_DEFAULT) { -- printf("Default environment is used\n"); -+ if (!quiet) -+ printf("Default environment is used\n"); - eval_results |= ENV_INFO_IS_DEFAULT; - } else { -- printf("Environment was loaded from persistent storage\n"); -+ if (!quiet) -+ printf("Environment was loaded from persistent storage\n"); - } - } - - /* evaluate whether environment can be persisted */ - if (eval_flags & ENV_INFO_IS_PERSISTED) { --#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) -- printf("Environment can be persisted\n"); -- eval_results |= ENV_INFO_IS_PERSISTED; -+#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) -+ loc = env_get_location(ENVOP_SAVE, gd->env_load_prio); -+ if (ENVL_NOWHERE != loc && ENVL_UNKNOWN != loc) { -+ if (!quiet) -+ printf("Environment can be persisted\n"); -+ eval_results |= ENV_INFO_IS_PERSISTED; -+ } else { -+ if (!quiet) -+ printf("Environment cannot be persisted\n"); -+ } - #else -- printf("Environment cannot be persisted\n"); -+ if (!quiet) -+ printf("Environment cannot be persisted\n"); - #endif - } - -@@ -1321,7 +1340,7 @@ static cmd_tbl_t cmd_env_sub[] = { - U_BOOT_CMD_MKENT(import, 5, 0, do_env_import, "", ""), - #endif - #if defined(CONFIG_CMD_NVEDIT_INFO) -- U_BOOT_CMD_MKENT(info, 2, 0, do_env_info, "", ""), -+ U_BOOT_CMD_MKENT(info, 3, 0, do_env_info, "", ""), - #endif - U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), - #if defined(CONFIG_CMD_RUN) -@@ -1400,8 +1419,10 @@ static char env_help_text[] = - #endif - #if defined(CONFIG_CMD_NVEDIT_INFO) - "env info - display environment information\n" -- "env info [-d] - whether default environment is used\n" -- "env info [-p] - whether environment can be persisted\n" -+ "env info [-d] [-p] [-q] - evaluate environment information\n" -+ " \"-d\": default environment is used\n" -+ " \"-p\": environment can be persisted\n" -+ " \"-q\": quiet output\n" - #endif - "env print [-a | name ...] - print environment\n" - #if defined(CONFIG_CMD_NVEDIT_EFI) -diff --git a/common/board_f.c b/common/board_f.c -index d66afb3..ef59630 100644 ---- a/common/board_f.c -+++ b/common/board_f.c -@@ -470,6 +470,17 @@ static int reserve_uboot(void) - return 0; - } - -+/* -+ * reserve after start_addr_sp the requested size and make the stack pointer -+ * 16-byte aligned, this alignment is needed for cast on the reserved memory -+ * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes -+ * = ARMv8 Instruction Set Overview: quad word, 16 bytes -+ */ -+static unsigned long reserve_stack_aligned(size_t size) -+{ -+ return ALIGN_DOWN(gd->start_addr_sp - size, 16); -+} -+ - #ifdef CONFIG_SYS_NONCACHED_MEMORY - static int reserve_noncached(void) - { -@@ -495,7 +506,7 @@ static int reserve_noncached(void) - /* reserve memory for malloc() area */ - static int reserve_malloc(void) - { -- gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; -+ gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN); - debug("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); - #ifdef CONFIG_SYS_NONCACHED_MEMORY -@@ -509,7 +520,7 @@ static int reserve_malloc(void) - static int reserve_board(void) - { - if (!gd->bd) { -- gd->start_addr_sp -= sizeof(bd_t); -+ gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t)); - gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); - memset(gd->bd, '\0', sizeof(bd_t)); - debug("Reserving %zu Bytes for Board Info at: %08lx\n", -@@ -528,7 +539,7 @@ static int setup_machine(void) - - static int reserve_global_data(void) - { -- gd->start_addr_sp -= sizeof(gd_t); -+ gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t)); - gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); - debug("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof(gd_t), gd->start_addr_sp); -@@ -546,7 +557,7 @@ static int reserve_fdt(void) - if (gd->fdt_blob) { - gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); - -- gd->start_addr_sp -= gd->fdt_size; -+ gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size); - gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); - debug("Reserving %lu Bytes for FDT at: %08lx\n", - gd->fdt_size, gd->start_addr_sp); -@@ -561,7 +572,7 @@ static int reserve_bootstage(void) - #ifdef CONFIG_BOOTSTAGE - int size = bootstage_get_size(); - -- gd->start_addr_sp -= size; -+ gd->start_addr_sp = reserve_stack_aligned(size); - gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); - debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, - gd->start_addr_sp); -@@ -578,8 +589,7 @@ __weak int arch_reserve_stacks(void) - static int reserve_stacks(void) - { - /* make stack pointer 16-byte aligned */ -- gd->start_addr_sp -= 16; -- gd->start_addr_sp &= ~0xf; -+ gd->start_addr_sp = reserve_stack_aligned(16); - - /* - * let the architecture-specific code tailor gd->start_addr_sp and -@@ -591,8 +601,7 @@ static int reserve_stacks(void) - static int reserve_bloblist(void) - { - #ifdef CONFIG_BLOBLIST -- gd->start_addr_sp &= ~0xf; -- gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE; -+ gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE); - gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); - #endif - -diff --git a/common/cli_readline.c b/common/cli_readline.c -index 6ef7a3e..a0ae778 100644 ---- a/common/cli_readline.c -+++ b/common/cli_readline.c -@@ -14,6 +14,12 @@ - #include - #include - -+#ifdef CONFIG_SPL_BUILD -+#undef CONFIG_CMDLINE_EDITING -+#undef CONFIG_AUTO_COMPLETE -+#undef CONFIG_SHOW_ACTIVITY -+#endif -+ - DECLARE_GLOBAL_DATA_PTR; - - static const char erase_seq[] = "\b \b"; /* erase sequence */ -diff --git a/common/image-android-dt.c b/common/image-android-dt.c -index a2d52df..a325e67 100644 ---- a/common/image-android-dt.c -+++ b/common/image-android-dt.c -@@ -154,4 +154,46 @@ void android_dt_print_contents(ulong hdr_addr) - unmap_sysmem(fdt); - } - } -+ - #endif -+ -+/** -+ * Get dtb index based on board identifier and revision. -+ * -+ * @param hdr_addr Start address of DT image -+ * @param board_id board identifier -+ * @param board_rev board revision (0 if not used) -+ * -+ * @return index in dt table -+ */ -+int android_dt_get_index(ulong hdr_addr, u32 board_id, u32 board_rev) -+{ -+ const struct dt_table_header *hdr; -+ u32 entry_count, entries_offset, entry_size; -+ u32 i; -+ int ret = -1; -+ -+ hdr = map_sysmem(hdr_addr, sizeof(*hdr)); -+ entry_count = fdt32_to_cpu(hdr->dt_entry_count); -+ entries_offset = fdt32_to_cpu(hdr->dt_entries_offset); -+ entry_size = fdt32_to_cpu(hdr->dt_entry_size); -+ unmap_sysmem(hdr); -+ -+ for (i = 0; i < entry_count; ++i) { -+ const ulong e_addr = hdr_addr + entries_offset + i * entry_size; -+ const struct dt_table_entry *e; -+ -+ e = map_sysmem(e_addr, sizeof(*e)); -+ -+ if ((fdt32_to_cpu(e->id) == board_id) && -+ (board_rev == 0 || fdt32_to_cpu(e->rev) == board_rev)) { -+ ret = i; -+ unmap_sysmem(e); -+ break; -+ } -+ -+ unmap_sysmem(e); -+ } -+ -+ return ret; -+} -diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig -index cb72a01..483f37c 100644 ---- a/configs/igep00x0_defconfig -+++ b/configs/igep00x0_defconfig -@@ -52,6 +52,7 @@ CONFIG_NET_RANDOM_ETHADDR=y - CONFIG_DM_MMC=y - CONFIG_MMC_OMAP_HS=y - CONFIG_MTD=y -+CONFIG_SYS_MTDPARTS_RUNTIME=y - CONFIG_MTD_RAW_NAND=y - CONFIG_SYS_NAND_BUSWIDTH_16BIT=y - CONFIG_SPL_NAND_SIMPLE=y -diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig -index 6d824cc..be5ab64 100644 ---- a/configs/mt8518_ap1_emmc_defconfig -+++ b/configs/mt8518_ap1_emmc_defconfig -@@ -16,6 +16,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc" - CONFIG_REGMAP=y - CONFIG_SYSCON=y - CONFIG_CLK=y -+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y -+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y - CONFIG_DM_MMC=y - CONFIG_MMC_HS200_SUPPORT=y - CONFIG_MMC_MTK=y -diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig -index 20038d4..ff0bdc3 100644 ---- a/configs/odroid-xu3_defconfig -+++ b/configs/odroid-xu3_defconfig -@@ -38,6 +38,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y - CONFIG_ADC=y - CONFIG_ADC_EXYNOS=y - CONFIG_DFU_MMC=y -+CONFIG_SET_DFU_ALT_INFO=y - CONFIG_SUPPORT_EMMC_BOOT=y - CONFIG_MMC_DW=y - CONFIG_MTD=y -diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig -index be914e4..c77541c 100644 ---- a/configs/odroid_defconfig -+++ b/configs/odroid_defconfig -@@ -39,6 +39,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y - CONFIG_DFU_MMC=y -+CONFIG_SET_DFU_ALT_INFO=y - CONFIG_SYS_I2C_S3C24X0=y - CONFIG_MMC_DW=y - CONFIG_MMC_SDHCI=y -diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig -index cc536ff..f3565a9 100644 ---- a/configs/sandbox64_defconfig -+++ b/configs/sandbox64_defconfig -@@ -27,6 +27,7 @@ CONFIG_CMD_ASKENV=y - CONFIG_CMD_GREPENV=y - CONFIG_CMD_ENV_CALLBACK=y - CONFIG_CMD_ENV_FLAGS=y -+CONFIG_CMD_NVEDIT_INFO=y - CONFIG_LOOPW=y - CONFIG_CMD_MD5SUM=y - CONFIG_CMD_MEMINFO=y -diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig -index 64245f7..8a2d397 100644 ---- a/configs/sandbox_defconfig -+++ b/configs/sandbox_defconfig -@@ -30,6 +30,7 @@ CONFIG_CMD_ASKENV=y - CONFIG_CMD_GREPENV=y - CONFIG_CMD_ENV_CALLBACK=y - CONFIG_CMD_ENV_FLAGS=y -+CONFIG_CMD_NVEDIT_INFO=y - CONFIG_LOOPW=y - CONFIG_CMD_MD5SUM=y - CONFIG_CMD_MEMINFO=y -diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig -index bb31b00..ffd0dfa 100644 ---- a/configs/sandbox_flattree_defconfig -+++ b/configs/sandbox_flattree_defconfig -@@ -22,6 +22,7 @@ CONFIG_CMD_BOOTZ=y - # CONFIG_CMD_ELF is not set - CONFIG_CMD_ASKENV=y - CONFIG_CMD_GREPENV=y -+CONFIG_CMD_NVEDIT_INFO=y - CONFIG_LOOPW=y - CONFIG_CMD_MD5SUM=y - CONFIG_CMD_MEMINFO=y -diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig -index 61a8ffd..ab2c29a 100644 ---- a/configs/sandbox_spl_defconfig -+++ b/configs/sandbox_spl_defconfig -@@ -33,6 +33,7 @@ CONFIG_CMD_ASKENV=y - CONFIG_CMD_GREPENV=y - CONFIG_CMD_ENV_CALLBACK=y - CONFIG_CMD_ENV_FLAGS=y -+CONFIG_CMD_NVEDIT_INFO=y - CONFIG_LOOPW=y - CONFIG_CMD_MD5SUM=y - CONFIG_CMD_MEMINFO=y -diff --git a/doc/README.gpio b/doc/README.gpio -new file mode 100644 -index 0000000..548ff37 ---- /dev/null -+++ b/doc/README.gpio -@@ -0,0 +1,42 @@ -+ -+GPIO hog (CONFIG_GPIO_HOG) -+-------- -+ -+All the GPIO hog are initialized in gpio_hog_probe_all() function called in -+board_r.c just before board_late_init() but you can also acces directly to -+the gpio with gpio_hog_lookup_name(). -+ -+ -+Example, for the device tree: -+ -+ tca6416@20 { -+ compatible = "ti,tca6416"; -+ reg = <0x20>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ -+ env_reset { -+ gpio-hog; -+ input; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ }; -+ boot_rescue { -+ gpio-hog; -+ input; -+ line-name = "foo-bar-gpio"; -+ gpios = <7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+You can than access the gpio in your board code with: -+ -+ struct gpio_desc *desc; -+ int ret; -+ -+ ret = gpio_hog_lookup_name("boot_rescue", &desc); -+ if (ret) -+ return; -+ if (dm_gpio_get_value(desc) == 1) -+ printf("\nBooting into Rescue System\n"); -+ else if (dm_gpio_get_value(desc) == 0) -+ printf("\nBoot normal\n"); -diff --git a/doc/android/fastboot.txt b/doc/android/fastboot.txt -index 9de1322..e01eec6 100644 ---- a/doc/android/fastboot.txt -+++ b/doc/android/fastboot.txt -@@ -23,6 +23,9 @@ The current implementation supports the following standard commands: - The following OEM commands are supported (if enabled): - - - oem format - this executes ``gpt write mmc %x $partitions`` -+- oem partconf - this executes - ``mmc partconf %x 0`` to configure eMMC -+ with = boot_ack boot_partition -+- oem bootbus - this executes - ``mmc bootbus %x %s`` to configure eMMC - - Support for both eMMC and NAND devices is included. - -diff --git a/doc/device-tree-bindings/clock/st,stm32-rcc.txt b/doc/device-tree-bindings/clock/st,stm32-rcc.txt -index 0532d81..b240121 100644 ---- a/doc/device-tree-bindings/clock/st,stm32-rcc.txt -+++ b/doc/device-tree-bindings/clock/st,stm32-rcc.txt -@@ -10,6 +10,7 @@ Required properties: - - compatible: Should be: - "st,stm32f42xx-rcc" - "st,stm32f469-rcc" -+ "st,stm32f746-rcc" - - reg: should be register base and length as documented in the - datasheet - - #reset-cells: 1, see below -@@ -17,6 +18,9 @@ Required properties: - property, containing a phandle to the clock device node, an index selecting - between gated clocks and other clocks and an index specifying the clock to - use. -+- clocks: External oscillator clock phandle -+ - high speed external clock signal (HSE) -+ - external I2S clock (I2S_CKIN) - - Example: - -@@ -25,6 +29,7 @@ Example: - #clock-cells = <2> - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; -+ clocks = <&clk_hse>, <&clk_i2s_ckin>; - }; - - Specifying gated clocks -@@ -66,6 +71,38 @@ The secondary index is bound with the following magic numbers: - - 0 SYSTICK - 1 FCLK -+ 2 CLK_LSI (low-power clock source) -+ 3 CLK_LSE (generated from a 32.768 kHz low-speed external -+ crystal or ceramic resonator) -+ 4 CLK_HSE_RTC (HSE division factor for RTC clock) -+ 5 CLK_RTC (real-time clock) -+ 6 PLL_VCO_I2S (vco frequency of I2S pll) -+ 7 PLL_VCO_SAI (vco frequency of SAI pll) -+ 8 CLK_LCD (LCD-TFT) -+ 9 CLK_I2S (I2S clocks) -+ 10 CLK_SAI1 (audio clocks) -+ 11 CLK_SAI2 -+ 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) -+ 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) -+ -+ 14 CLK_HSI (Internal ocscillator clock) -+ 15 CLK_SYSCLK (System Clock) -+ 16 CLK_HDMI_CEC (HDMI-CEC clock) -+ 17 CLK_SPDIF (SPDIF-Rx clock) -+ 18 CLK_USART1 (U(s)arts clocks) -+ 19 CLK_USART2 -+ 20 CLK_USART3 -+ 21 CLK_UART4 -+ 22 CLK_UART5 -+ 23 CLK_USART6 -+ 24 CLK_UART7 -+ 25 CLK_UART8 -+ 26 CLK_I2C1 (I2S clocks) -+ 27 CLK_I2C2 -+ 28 CLK_I2C3 -+ 29 CLK_I2C4 -+ 30 CLK_LPTIMER (LPTimer1 clock) -+) - - Example: - -diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt -index ec1d703..4d4136d 100644 ---- a/doc/device-tree-bindings/clock/st,stm32mp1.txt -+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt -@@ -12,6 +12,9 @@ describes the fields added for clock tree initialization which are not present - in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt - file. - -+This parent node may optionally have additional children nodes which define -+specific init values for RCC elements. -+ - The added properties for clock tree initialization are: - - Required properties: -@@ -78,13 +81,20 @@ Required properties: - >; - - Optional Properties: --- st,pll : A specific PLL configuration, including frequency. -+- children for a PLL configuration with "st,stm32mp1-pll" compatible -+ -+ each PLL children nodes for PLL1 to PLL4 (see ref manual for details) -+ are listed with associated reg 0 to 3. -+ PLLx is off when the associated node is absent or deactivated. - -- PLL children nodes for PLL1 to PLL4 (see ref manual for details) -- are listed with associated index 0 to 3 (st,pll@0 to st,pll@3). -- PLLx is off when the associated node is absent. -+ For PLL1, when the node is absent, the frequency of the OPP node is used -+ to compute the PLL setting (see compatible "operating-points-v2" in -+ opp/opp.txt for details). - - Here are the available properties for each PLL node: -+ - compatible: should be "st,stm32mp1-pll" -+ -+ - reg: index of the pll instance - - - cfg: The parameters for PLL configuration in the following order: - DIVM DIVN DIVP DIVQ DIVR Output. -@@ -118,18 +128,26 @@ Optional Properties: - - Example: - st,pll@0 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <0>; - cfg = < 1 53 0 0 0 1 >; - frac = < 0x810 >; - }; - st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; - cfg = < 1 43 1 0 0 PQR(0,1,1) >; - csg = < 10 20 1 >; - }; - st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; - cfg = < 2 85 3 13 3 0 >; - csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; - }; - st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; - cfg = < 2 78 4 7 9 3 >; - }; - -@@ -277,6 +295,8 @@ Example of clock tree initialization - u-boot,dm-pre-reloc; - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; - #clock-cells = <1>; - #reset-cells = <1>; - interrupts = ; -@@ -347,6 +367,8 @@ Example of clock tree initialization - - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; -@@ -355,6 +377,8 @@ Example of clock tree initialization - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), - R = 533 (DDR) */ - pll2: st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; -@@ -362,6 +386,8 @@ Example of clock tree initialization - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; -@@ -369,6 +395,8 @@ Example of clock tree initialization - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt -index e146917..1481ed6 100644 ---- a/doc/device-tree-bindings/gpio/gpio.txt -+++ b/doc/device-tree-bindings/gpio/gpio.txt -@@ -4,19 +4,12 @@ Specifying GPIO information for devices - 1) gpios property - ----------------- - --Nodes that makes use of GPIOs should specify them using one or more --properties, each containing a 'gpio-list': -- -- gpio-list ::= [gpio-list] -- single-gpio ::= -- gpio-phandle : phandle to gpio controller node -- gpio-specifier : Array of #gpio-cells specifying specific gpio -- (controller specific) -- - GPIO properties should be named "[-]gpios", with being the purpose - of this GPIO for the device. While a non-existent is considered valid - for compatibility reasons (resolving to the "gpios" property), it is not allowed --for new bindings. -+for new bindings. Also, GPIO properties named "[-]gpio" are valid and old -+bindings use it, but are only supported for compatibility reasons and should not -+be used for newer bindings since it has been deprecated. - - GPIO properties can contain one or more GPIO phandles, but only in exceptional - cases should they contain more than one. If your device uses several GPIOs with -@@ -31,30 +24,28 @@ The following example could be used to describe GPIO pins used as device enable - and bit-banged data signals: - - gpio1: gpio1 { -- gpio-controller -- #gpio-cells = <2>; -- }; -- gpio2: gpio2 { -- gpio-controller -- #gpio-cells = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; - }; - [...] - -- enable-gpios = <&gpio2 2>; - data-gpios = <&gpio1 12 0>, - <&gpio1 13 0>, - <&gpio1 14 0>, - <&gpio1 15 0>; - --Note that gpio-specifier length is controller dependent. In the --above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 --only uses one. -+In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is -+a local offset to the GPIO line and the second cell represent consumer flags, -+such as if the consumer desire the line to be active low (inverted) or open -+drain. This is the recommended practice. - --gpio-specifier may encode: bank, pin position inside the bank, --whether pin is open-drain and whether pin is logically inverted. --Exact meaning of each specifier cell is controller specific, and must --be documented in the device tree binding for the device. Use the macros --defined in include/dt-bindings/gpio/gpio.h whenever possible: -+The exact meaning of each specifier cell is controller specific, and must be -+documented in the device tree binding for the device, but it is strongly -+recommended to use the two-cell approach. -+ -+Most controllers are specifying a generic flag bitfield in the last cell, so -+for these, use the macros defined in -+include/dt-bindings/gpio/gpio.h whenever possible: - - Example of a node using GPIOs: - -@@ -65,6 +56,30 @@ Example of a node using GPIOs: - GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes - GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. - -+Optional standard bitfield specifiers for the last cell: -+ -+- Bit 0: 0 means active high, 1 means active low -+- Bit 1: 0 mean push-pull wiring, see: -+ https://en.wikipedia.org/wiki/Push-pull_output -+ 1 means single-ended wiring, see: -+ https://en.wikipedia.org/wiki/Single-ended_triode -+- Bit 2: 0 means open-source, 1 means open drain, see: -+ https://en.wikipedia.org/wiki/Open_collector -+- Bit 3: 0 means the output should be maintained during sleep/low-power mode -+ 1 means the output state can be lost during sleep/low-power mode -+- Bit 4: 0 means no pull-up resistor should be enabled -+ 1 means a pull-up resistor should be enabled -+ This setting only applies to hardware with a simple on/off -+ control for pull-up configuration. If the hardware has more -+ elaborate pull-up configuration, it should be represented -+ using a pin control binding. -+- Bit 5: 0 means no pull-down resistor should be enabled -+ 1 means a pull-down resistor should be enabled -+ This setting only applies to hardware with a simple on/off -+ control for pull-down configuration. If the hardware has more -+ elaborate pull-down configuration, it should be represented -+ using a pin control binding. -+ - 1.1) GPIO specifier best practices - ---------------------------------- - -@@ -116,6 +131,80 @@ Every GPIO controller node must contain both an empty "gpio-controller" - property, and a #gpio-cells integer property, which indicates the number of - cells in a gpio-specifier. - -+Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an -+instance of a hardware IP core on a silicon die, usually exposed to the -+programmer as a coherent range of I/O addresses. Usually each such bank is -+exposed in the device tree as an individual gpio-controller node, reflecting -+the fact that the hardware was synthesized by reusing the same IP block a -+few times over. -+ -+Optionally, a GPIO controller may have a "ngpios" property. This property -+indicates the number of in-use slots of available slots for GPIOs. The -+typical example is something like this: the hardware register is 32 bits -+wide, but only 18 of the bits have a physical counterpart. The driver is -+generally written so that all 32 bits can be used, but the IP block is reused -+in a lot of designs, some using all 32 bits, some using 18 and some using -+12. In this case, setting "ngpios = <18>;" informs the driver that only the -+first 18 GPIOs, at local offset 0 .. 17, are in use. -+ -+If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -+additional set of tuples is needed to specify which GPIOs are unusable, with -+the gpio-reserved-ranges binding. This property indicates the start and size -+of the GPIOs that can't be used. -+ -+Optionally, a GPIO controller may have a "gpio-line-names" property. This is -+an array of strings defining the names of the GPIO lines going out of the -+GPIO controller. This name should be the most meaningful producer name -+for the system, such as a rail name indicating the usage. Package names -+such as pin name are discouraged: such lines have opaque names (since they -+are by definition generic purpose) and such names are usually not very -+helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are -+reasonable line names as they describe what the line is used for. "GPIO0" -+is not a good name to give to a GPIO line. Placeholders are discouraged: -+rather use the "" (blank string) if the use of the GPIO line is undefined -+in your design. The names are assigned starting from line offset 0 from -+left to right from the passed array. An incomplete array (where the number -+of passed named are less than ngpios) will still be used up until the last -+provided valid line index. -+ -+Example: -+ -+gpio-controller@00000000 { -+ compatible = "foo"; -+ reg = <0x00000000 0x1000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ ngpios = <18>; -+ gpio-reserved-ranges = <0 4>, <12 2>; -+ gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", -+ "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", -+ "Row A", "Row B", "Row C", "Row D", "NMI button", -+ "poweroff", "reset"; -+} -+ -+The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism -+providing automatic GPIO request and configuration as part of the -+gpio-controller's driver probe function. -+ -+Each GPIO hog definition is represented as a child node of the GPIO controller. -+Required properties: -+- gpio-hog: A property specifying that this child node represents a GPIO hog. -+- gpios: Store the GPIO information (id, flags, ...) for each GPIO to -+ affect. Shall contain an integer multiple of the number of cells -+ specified in its parent node (GPIO controller node). -+Only one of the following properties scanned in the order shown below. -+This means that when multiple properties are present they will be searched -+in the order presented below and the first match is taken as the intended -+configuration. -+- input: A property specifying to set the GPIO direction as input. -+- output-low A property specifying to set the GPIO direction as output with -+ the value low. -+- output-high A property specifying to set the GPIO direction as output with -+ the value high. -+ -+Optional properties: -+- line-name: The GPIO label name. If not present the node name is used. -+ - Example of two SOC GPIO banks defined as gpio-controller nodes: - - qe_pio_a: gpio-controller@1400 { -@@ -137,46 +226,40 @@ Example of two SOC GPIO banks defined as gpio-controller nodes: - - Some or all of the GPIOs provided by a GPIO controller may be routed to pins - on the package via a pin controller. This allows muxing those pins between --GPIO and other functions. -+GPIO and other functions. It is a fairly common practice among silicon -+engineers. -+ -+2.2) Ordinary (numerical) GPIO ranges -+------------------------------------- - - It is useful to represent which GPIOs correspond to which pins on which pin --controllers. The gpio-ranges property described below represents this, and --contains information structures as follows: -- -- gpio-range-list ::= [gpio-range-list] -- single-gpio-range ::= | -- numeric-gpio-range ::= -- -- named-gpio-range ::= '<0 0>' -- pinctrl-phandle : phandle to pin controller node -- gpio-base : Base GPIO ID in the GPIO controller -- pinctrl-base : Base pinctrl pin ID in the pin controller -- count : The number of GPIOs/pins in this range -- --The "pin controller node" mentioned above must conform to the bindings --described in ../pinctrl/pinctrl-bindings.txt. -- --In case named gpio ranges are used (ranges with both and -- set to 0), the property gpio-ranges-group-names contains one string --for every single-gpio-range in gpio-ranges: -- gpiorange-names-list ::= [gpiorange-names-list] -- gpiorange-name : Name of the pingroup associated to the GPIO range in -- the respective pin controller. -- --Elements of gpiorange-names-list corresponding to numeric ranges contain --the empty string. Elements of gpiorange-names-list corresponding to named --ranges contain the name of a pin group defined in the respective pin --controller. The number of pins/GPIOs in the range is the number of pins in --that pin group. -+controllers. The gpio-ranges property described below represents this with -+a discrete set of ranges mapping pins from the pin controller local number space -+to pins in the GPIO controller local number space. - --Previous versions of this binding required all pin controller nodes that --were referenced by any gpio-ranges property to contain a property named --#gpio-range-cells with value <3>. This requirement is now deprecated. --However, that property may still exist in older device trees for --compatibility reasons, and would still be required even in new device --trees that need to be compatible with older software. -+The format is: <[pin controller phandle], [GPIO controller offset], -+ [pin controller offset], [number of pins]>; -+ -+The GPIO controller offset pertains to the GPIO controller node containing the -+range definition. -+ -+The pin controller node referenced by the phandle must conform to the bindings -+described in pinctrl/pinctrl-bindings.txt. -+ -+Each offset runs from 0 to N. It is perfectly fine to pile any number of -+ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but -+in practice these ranges are often lumped in discrete sets. -+ -+Example: -+ -+ gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; -+ -+This means: -+- pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and -+- pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 - --Example 1: -+ -+Verbose example: - - qe_pio_e: gpio-controller@1460 { - #gpio-cells = <2>; -@@ -187,12 +270,33 @@ Example 1: - }; - - Here, a single GPIO controller has GPIOs 0..9 routed to pin controller --pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's --pins 50..59. -+pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's -+pins 50..69. -+ -+ -+2.3) GPIO ranges from named pin groups -+-------------------------------------- -+ -+It is also possible to use pin groups for gpio ranges when pin groups are the -+easiest and most convenient mapping. -+ -+Both both and must set to 0 when using named pin groups -+names. -+ -+The property gpio-ranges-group-names must contain exactly one string for each -+range. -+ -+Elements of gpio-ranges-group-names must contain the name of a pin group -+defined in the respective pin controller. The number of pins/GPIO lines in the -+range is the number of pins in that pin group. The number of pins of that -+group is defined int the implementation and not in the device tree. - --Example 2: -+If numerical and named pin groups are mixed, the string corresponding to a -+numerical pin range in gpio-ranges-group-names must be empty. - -- gpio_pio_i: gpio-controller@14B0 { -+Example: -+ -+ gpio_pio_i: gpio-controller@14b0 { - #gpio-cells = <2>; - compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; - reg = <0x1480 0x18>; -@@ -207,66 +311,14 @@ Example 2: - "bar"; - }; - --Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO --ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2 --are named "foo" and "bar". -- --3) GPIO hog definitions ------------------------- -- --The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism --providing automatic GPIO request and configuration as part of the --gpio-controller's driver probe function. -+Here, three GPIO ranges are defined referring to two pin controllers. - --Each GPIO hog definition is represented as a child node of the GPIO controller. --Required properties: --- gpio-hog: A property specifying that this child node represents a GPIO hog. --- gpios: Store the GPIO information (id, flags) for the GPIO to -- affect. -+pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges -+in pinctrl2 are defined using the pin groups named "foo" and "bar". - -- ! Not yet support more than one gpio ! -- --Only one of the following properties scanned in the order shown below. --- input: A property specifying to set the GPIO direction as input. --- output-low A property specifying to set the GPIO direction as output with -- the value low. --- output-high A property specifying to set the GPIO direction as output with -- the value high. -- --Optional properties: --- line-name: The GPIO label name. If not present the node name is used. -- --Example: -- -- tca6416@20 { -- compatible = "ti,tca6416"; -- reg = <0x20>; -- #gpio-cells = <2>; -- gpio-controller; -- -- env_reset { -- gpio-hog; -- input; -- gpios = <6 GPIO_ACTIVE_LOW>; -- }; -- boot_rescue { -- gpio-hog; -- input; -- line-name = "foo-bar-gpio"; -- gpios = <7 GPIO_ACTIVE_LOW>; -- }; -- }; -- --For the above Example you can than access the gpio in your boardcode --with: -- -- struct gpio_desc *desc; -- int ret; -- -- ret = gpio_hog_lookup_name("boot_rescue", &desc); -- if (ret) -- return; -- if (dm_gpio_get_value(desc) == 1) -- printf("\nBooting into Rescue System\n"); -- else if (dm_gpio_get_value(desc) == 0) -- printf("\nBoot normal\n"); -+Previous versions of this binding required all pin controller nodes that -+were referenced by any gpio-ranges property to contain a property named -+#gpio-range-cells with value <3>. This requirement is now deprecated. -+However, that property may still exist in older device trees for -+compatibility reasons, and would still be required even in new device -+trees that need to be compatible with older software. -diff --git a/doc/device-tree-bindings/i2c/i2c-stm32.txt b/doc/device-tree-bindings/i2c/i2c-stm32.txt -index df03743..7f7686e 100644 ---- a/doc/device-tree-bindings/i2c/i2c-stm32.txt -+++ b/doc/device-tree-bindings/i2c/i2c-stm32.txt -@@ -1,30 +1,109 @@ --* I2C controller embedded in STMicroelectronis STM32 platforms -+* I2C controller embedded in STMicroelectronics STM32 I2C platform - - Required properties : --- compatible : Must be "st,stm32f7-i2c" -+- compatible : Must be one of the following -+ - "st,stm32f4-i2c" -+ - "st,stm32f7-i2c" - - reg : Offset and length of the register set for the device --- resets: Must contain the phandle to the reset controller --- clocks: Must contain the input clock of the I2C instance -+- interrupts : Must contain the interrupt id for I2C event and then the -+ interrupt id for I2C error. -+ Optionnaly a wakeup interrupt may be specified. -+- resets: Must contain the phandle to the reset controller. -+- clocks: Must contain the input clock of the I2C instance. - - A pinctrl state named "default" must be defined to set pins in mode of -- operation for I2C transfer -+ operation for I2C transfer. An optional pinctrl state named "sleep" has to -+ be defined as well as to put I2C in low power mode in suspend mode. - - #address-cells = <1>; - - #size-cells = <0>; - - Optional properties : - - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, -- the default 100 kHz frequency will be used. As only Normal, Fast and Fast+ -- modes are implemented, possible values are 100000, 400000 and 1000000. -+ the default 100 kHz frequency will be used. -+ For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are -+ 100000 and 400000. -+ For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode -+ Plus are supported, possible values are 100000, 400000 and 1000000. -+- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25) -+ For STM32F7, STM32H7 and STM32MP1 only. -+- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10) -+ For STM32F7, STM32H7 and STM32MP1 only. -+ I2C Timings are derived from these 2 values -+- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode -+ Plus speed is selected by slave. -+ 1st cell : phandle to syscfg -+ 2nd cell : register offset within SYSCFG -+ 3rd cell : register bitmask for FMP bit -+ For STM32F7, STM32H7 and STM32MP1 only. -+- st,syscfg-fmp-clr: Use to clear Fast Mode Plus bit within SYSCFG when Fast -+ Mode Plus speed is selected by slave. -+ 1st cell: phandle to syscfg -+ 2nd cell: clear register offset within SYSCFG -+ 3rd cell: register bitmask for FMP clear bit -+ For STM32MP1 family only. - - Example : - -- i2c1: i2c@40005400 { -- compatible = "st,stm32f7-i2c"; -+ i2c@40005400 { -+ compatible = "st,stm32f4-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; - reg = <0x40005400 0x400>; -- resets = <&rcc 181>; -- clocks = <&clk_pclk1>; -+ interrupts = <31>, -+ <32>; -+ resets = <&rcc 277>; -+ clocks = <&rcc 0 149>; -+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_i2c1>; -- clock-frequency = <400000>; -+ }; -+ -+ i2c@40005400 { -+ compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; -+ reg = <0x40005400 0x400>; -+ interrupts = <31>, -+ <32>; -+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>; -+ clocks = <&rcc 1 CLK_I2C1>; -+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; -+ pinctrl-1 = <&i2c1_sda_pin_sleep>, <&i2c1_scl_pin_sleep>; -+ pinctrl-names = "default", "sleep"; -+ st,syscfg-fmp = <&syscfg 0x4 0x1>; -+ st,syscfg-fmp-clr = <&syscfg 0x44 0x1>; -+ }; -+ -+ i2c@40013000 { -+ compatible = "st,stm32f7-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x40013000 0x400>; -+ interrupt-names = "event", "error", "wakeup"; -+ interrupts-extended = <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, -+ <&exti 22 1>; -+ clocks = <&rcc I2C2_K>; -+ resets = <&rcc I2C2_R>; -+ st,syscfg-fmp = <&syscfg 0x4 0x2>; -+ st,syscfg-fmp-clr = <&syscfg 0x44 0x2>; -+ }; -+ -+ -+* I2C Devices -+ -+An I2C device connected onto STM32 I2C controller must use a format described by -+i2c.txt file. -+ -+Required properties : -+- compatible -+ Device driver compatible name -+- reg -+ I2C slave addresses (see i2c.txt for more details) -+ -+Optional properties : -+ -+ i2c@40013000 { -+ camera@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ }; - }; -diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt -index ee708ce..ac6a7df 100644 ---- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt -+++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt -@@ -129,6 +129,8 @@ phyc attributes: - MR3 - - - st,phy-cal : phy cal depending of calibration or tuning of DDR -+ This parameter is optional; when it is absent the built-in PHY -+ calibration is done. - for STM32MP15x: 12 values are requested in this order - DX0DLLCR - DX0DQTR -diff --git a/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt -index 70e76be..ad2bef8 100644 ---- a/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt -+++ b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt -@@ -18,8 +18,10 @@ Optional properties: - - dmas: DMA specifiers (see: dma/stm32-mdma.txt) - - dma-names: Must be "tx", "rx" and "ecc" - --Optional children nodes: --Children nodes represent the available NAND chips. -+* NAND device bindings: -+ -+Required properties: -+- reg: describes the CS lines assigned to the NAND device. - - Optional properties: - - nand-on-flash-bbt: see nand.txt -diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -index da98407..156229b 100644 ---- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -+++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -@@ -27,6 +27,7 @@ Required properties: - - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY - - #address-cells: number of address cells for phys sub-nodes, must be <1> - - #size-cells: number of size cells for phys sub-nodes, must be <0> -+- #clock-cells: number of clock cells for ck_usbo_48m consumer, must be <0> - - Optional properties: - - assigned-clocks: phandle + clock specifier for the PLL phy clock -@@ -36,7 +37,7 @@ Optional properties: - Required nodes: one sub-node per port the controller provides. - - Phy sub-nodes --============== -+============= - - Required properties: - - reg: phy port index -@@ -45,29 +46,73 @@ Required properties: - - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY - port#1 and must be <1> for PHY port#2, to select USB controller - -+Optional properties: -+- st,phy-tuning : phandle to the usb phy tuning node, see Phy tuning node below -+ -+Phy tuning node -+=============== -+ -+It may be necessary to adjust the phy settings to compensate parasitics, which -+can be due to USB connector/receptacle, routing, ESD protection component, ... -+ -+Here is the list of all optional parameters to tune the interface of the phy -+(HS for High-Speed, FS for Full-Speed, LS for Low-Speed) -+ -+Optional properties: -+- st,current-boost: <1> current boosting of 1mA -+ <2> current boosting of 2mA -+- st,no-lsfs-fb-cap: disables the LS/FS feedback capacitor -+- st,hs-slew-ctrl: slows the HS driver slew rate by 10% -+- st,hs-dc-level: <0> decreases the HS driver DC level by 5 to 7mV -+ <1> increases the HS driver DC level by 5 to 7mV -+ <2> increases the HS driver DC level by 10 to 14mV -+- st,fs-rftime-tuning: enables the FS rise/fall tuning option -+- st,hs-rftime-reduction: enables the HS rise/fall reduction feature -+- st,hs-current-trim: controls HS driver current trimming for choke -+- st,hs-impedance-trim: controls HS driver impedance tuning for choke -+- st,squelch-level: adjusts the squelch DC threshold value -+- st,hs-rx-gain-eq: enables the HS Rx gain equalizer -+- st,hs-rx-offset: adjusts the HS Rx offset -+- st,no-hs-ftime-ctrl: disables the HS fall time control of single -+ ended signals during pre-emphasis -+- st,no-lsfs-sc: disables the short circuit protection in LS/FS driver -+- st,hs-tx-staggering: enables the basic staggering in HS Tx mode -+ - - Example: -+ usb_phy_tuning: usb-phy-tuning { -+ st,current-boost = <2>; -+ st,no-lfs-fb-cap; -+ st,hs-dc-level = <2>; -+ st,hs-rftime-reduction; -+ st,hs-current-trim = <5>; -+ st,hs-impedance-trim = <0>; -+ st,squelch-level = <1>; -+ st,no-hs-ftime-ctrl; -+ st,hs-tx-staggering; -+ }; -+ - usbphyc: usb-phy@5a006000 { - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc_clk USBPHY_K>; - resets = <&rcc_rst USBPHY_R>; -+ vdda1v1-supply = <®11>; -+ vdda1v8-supply = <®18>; - #address-cells = <1>; - #size-cells = <0>; -+ #clock-cells = <0>; - - usbphyc_port0: usb-phy@0 { - reg = <0>; - phy-supply = <&vdd_usb>; -- vdda1v1-supply = <®11>; -- vdda1v8-supply = <®18> - #phy-cells = <0>; - }; - - usbphyc_port1: usb-phy@1 { - reg = <1>; - phy-supply = <&vdd_usb>; -- vdda1v1-supply = <®11>; -- vdda1v8-supply = <®18> - #phy-cells = <1>; -+ st,phy-tuning = <&usb_phy_tuning>; - }; - }; -diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c -index 017650a..3c2a3ac 100644 ---- a/drivers/ata/dwc_ahci.c -+++ b/drivers/ata/dwc_ahci.c -@@ -62,13 +62,13 @@ static int dwc_ahci_probe(struct udevice *dev) - - ret = generic_phy_init(&phy); - if (ret) { -- pr_err("unable to initialize the sata phy\n"); -+ pr_debug("unable to initialize the sata phy\n"); - return ret; - } - - ret = generic_phy_power_on(&phy); - if (ret) { -- pr_err("unable to power on the sata phy\n"); -+ pr_debug("unable to power on the sata phy\n"); - return ret; - } - -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index 16d4237..322f02a 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -141,6 +141,14 @@ config CLK_CDCE9XX - Enable the clock synthesizer driver for CDCE913/925/937/949 - series of chips. - -+config CLK_SCMI -+ bool "Enable SCMI clock driver" -+ select SCMI_AGENT -+ help -+ Enable this option if you want to support clock devices exposed -+ by a SCMI agent based on SCMI clock protocol communication -+ with a SCMI server. -+ - source "drivers/clk/analogbits/Kconfig" - source "drivers/clk/at91/Kconfig" - source "drivers/clk/exynos/Kconfig" -diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index 06131ed..b732852 100644 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o - obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o - obj-$(CONFIG_CLK_OWL) += owl/ - obj-$(CONFIG_CLK_RENESAS) += renesas/ -+obj-$(CONFIG_CLK_SCMI) += clk_scmi.o - obj-$(CONFIG_CLK_SIFIVE) += sifive/ - obj-$(CONFIG_ARCH_SUNXI) += sunxi/ - obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o -diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c -new file mode 100644 -index 0000000..f24b8b0 ---- /dev/null -+++ b/drivers/clk/clk_scmi.c -@@ -0,0 +1,152 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Linaro Limited -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+enum scmi_clock_message_id { -+ SCMI_CLOCK_RATE_SET = 0x5, -+ SCMI_CLOCK_RATE_GET = 0x6, -+ SCMI_CLOCK_CONFIG_SET = 0x7, -+}; -+ -+#define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0) -+#define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1)) -+#define SCMI_CLK_RATE_ROUND_DOWN 0 -+#define SCMI_CLK_RATE_ROUND_UP BIT(2) -+#define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3) -+ -+struct scmi_clk_state_in { -+ u32 clock_id; -+ u32 attributes; -+}; -+ -+struct scmi_clk_state_out { -+ s32 status; -+}; -+ -+static int scmi_clk_gate(struct clk *clk, int enable) -+{ -+ struct scmi_clk_state_in in = { -+ .clock_id = clk->id, -+ .attributes = enable, -+ }; -+ struct scmi_clk_state_out out; -+ struct scmi_msg scmi_msg = { -+ .protocol_id = SCMI_PROTOCOL_ID_CLOCK, -+ .message_id = SCMI_CLOCK_CONFIG_SET, -+ .in_msg = (u8 *)&in, -+ .in_msg_sz = sizeof(in), -+ .out_msg = (u8 *)&out, -+ .out_msg_sz = sizeof(out), -+ }; -+ int rc; -+ -+ rc = scmi_agent_process_msg(clk->dev->parent, &scmi_msg); -+ if (rc) -+ return rc; -+ -+ return scmi_to_linux_errno(out.status); -+} -+ -+static int scmi_clk_enable(struct clk *clk) -+{ -+ return scmi_clk_gate(clk, 1); -+} -+ -+static int scmi_clk_disable(struct clk *clk) -+{ -+ return scmi_clk_gate(clk, 0); -+} -+ -+struct scmi_clk_rate_get_in { -+ u32 clock_id; -+}; -+ -+struct scmi_clk_rate_get_out { -+ s32 status; -+ u32 rate_lsb; -+ u32 rate_msb; -+}; -+ -+static ulong scmi_clk_get_rate(struct clk *clk) -+{ -+ struct scmi_clk_rate_get_in in = { -+ .clock_id = clk->id, -+ }; -+ struct scmi_clk_rate_get_out out; -+ struct scmi_msg scmi_msg = { -+ .protocol_id = SCMI_PROTOCOL_ID_CLOCK, -+ .message_id = SCMI_CLOCK_RATE_GET, -+ .in_msg = (u8 *)&in, -+ .in_msg_sz = sizeof(in), -+ .out_msg = (u8 *)&out, -+ .out_msg_sz = sizeof(out), -+ }; -+ int rc; -+ -+ rc = scmi_agent_process_msg(clk->dev->parent, &scmi_msg); -+ if (rc) -+ return 0; -+ -+ rc = scmi_to_linux_errno(out.status); -+ if (rc) -+ return 0; -+ -+ return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb); -+} -+ -+struct scmi_clk_rate_set_in { -+ u32 clock_id; -+ u32 flags; -+ u32 rate_lsb; -+ u32 rate_msb; -+}; -+ -+struct scmi_clk_rate_set_out { -+ s32 status; -+}; -+ -+static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) -+{ -+ struct scmi_clk_rate_set_in in = { -+ .clock_id = clk->id, -+ .flags = SCMI_CLK_RATE_ASYNC_NORESP | -+ SCMI_CLK_RATE_ROUND_CLOSEST, -+ .rate_lsb = (u32)rate, -+ .rate_msb = (u32)((u64)rate >> 32), -+ }; -+ struct scmi_clk_rate_set_out out; -+ struct scmi_msg scmi_msg = { -+ .protocol_id = SCMI_PROTOCOL_ID_CLOCK, -+ .message_id = SCMI_CLOCK_RATE_SET, -+ .in_msg = (u8 *)&in, -+ .in_msg_sz = sizeof(in), -+ .out_msg = (u8 *)&out, -+ .out_msg_sz = sizeof(out), -+ }; -+ int rc; -+ -+ rc = scmi_agent_process_msg(clk->dev->parent, &scmi_msg); -+ if (rc) -+ return 0; -+ -+ return scmi_to_linux_errno(out.status); -+} -+ -+static const struct clk_ops scmi_clk_ops = { -+ .enable = scmi_clk_enable, -+ .disable = scmi_clk_disable, -+ .get_rate = scmi_clk_get_rate, -+ .set_rate = scmi_clk_set_rate, -+}; -+ -+U_BOOT_DRIVER(scmi_clock) = { -+ .name = "scmi_clk", -+ .id = UCLASS_CLK, -+ .ops = &scmi_clk_ops, -+}; -diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c -index 3718970..76fddcc 100644 ---- a/drivers/clk/clk_stm32mp1.c -+++ b/drivers/clk/clk_stm32mp1.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -95,6 +96,7 @@ DECLARE_GLOBAL_DATA_PTR; - #define RCC_I2C12CKSELR 0x8C0 - #define RCC_I2C35CKSELR 0x8C4 - #define RCC_SPI2S1CKSELR 0x8D8 -+#define RCC_SPI45CKSELR 0x8E0 - #define RCC_UART6CKSELR 0x8E4 - #define RCC_UART24CKSELR 0x8E8 - #define RCC_UART35CKSELR 0x8EC -@@ -241,7 +243,7 @@ DECLARE_GLOBAL_DATA_PTR; - enum stm32mp1_parent_id { - /* - * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved -- * they are used as index in osc[] as entry point -+ * they are used as index in osc_clk[] as clock reference - */ - _HSI, - _HSE, -@@ -304,6 +306,7 @@ enum stm32mp1_parent_sel { - _DSI_SEL, - _ADC12_SEL, - _SPI1_SEL, -+ _SPI45_SEL, - _RTC_SEL, - _PARENT_SEL_NB, - _UNKNOWN_SEL = 0xff, -@@ -420,8 +423,7 @@ struct stm32mp1_clk_data { - struct stm32mp1_clk_priv { - fdt_addr_t base; - const struct stm32mp1_clk_data *data; -- ulong osc[NB_OSC]; -- struct udevice *osc_dev[NB_OSC]; -+ struct clk osc_clk[NB_OSC]; - }; - - #define STM32MP1_CLK(off, b, idx, s) \ -@@ -527,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { - STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), - - STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL), -+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL), - STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), - - STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), -@@ -602,6 +605,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; - static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; - static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER, - _PLL3_R}; -+static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, -+ _HSE_KER}; - static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE}; - - static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { -@@ -620,22 +625,33 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { - STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, - sdmmc3_parents), - STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), -- STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), -- STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), -+ STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents), -+ STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents), - STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), - STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), - STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), - STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), -- STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents), -+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents), - STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents), -+ STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents), - STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT, - (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT), - rtc_parents), - }; - - #ifdef STM32MP1_CLOCK_TREE_INIT -+ - /* define characteristic of PLL according type */ -+#define DIVM_MIN 0 -+#define DIVM_MAX 63 - #define DIVN_MIN 24 -+#define DIVP_MIN 0 -+#define DIVP_MAX 127 -+#define FRAC_MAX 8192 -+ -+#define PLL1600_VCO_MIN 800000000 -+#define PLL1600_VCO_MAX 1600000000 -+ - static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { - [PLL_800] = { - .refclk_min = 4, -@@ -746,6 +762,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { - [_DSI_SEL] = "DSI", - [_ADC12_SEL] = "ADC12", - [_SPI1_SEL] = "SPI1", -+ [_SPI45_SEL] = "SPI45", - [_RTC_SEL] = "RTC", - }; - -@@ -763,7 +780,7 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) - return 0; - } - -- return priv->osc[idx]; -+ return clk_get_rate(&priv->osc_clk[idx]); - } - - static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) -@@ -946,10 +963,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) - case RCC_MPCKSELR_PLL: - case RCC_MPCKSELR_PLL_MPUDIV: - clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); -- if (p == RCC_MPCKSELR_PLL_MPUDIV) { -+ if ((reg & RCC_SELR_SRC_MASK) == -+ RCC_MPCKSELR_PLL_MPUDIV) { - reg = readl(priv->base + RCC_MPCKDIVR); -- clock /= stm32mp1_mpu_div[reg & -- RCC_MPUDIV_MASK]; -+ clock >>= stm32mp1_mpu_div[reg & -+ RCC_MPUDIV_MASK]; - } - break; - } -@@ -1178,6 +1196,213 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk) - } - - #ifdef STM32MP1_CLOCK_TREE_INIT -+ -+bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type) -+{ -+ unsigned int id; -+ -+ switch (opp_id) { -+ case 1: -+ case 2: -+ id = opp_id; -+ break; -+ default: -+ id = 1; /* default value */ -+ break; -+ } -+ -+ switch (cpu_type) { -+ case CPU_STM32MP157Fxx: -+ case CPU_STM32MP157Dxx: -+ case CPU_STM32MP153Fxx: -+ case CPU_STM32MP153Dxx: -+ case CPU_STM32MP151Fxx: -+ case CPU_STM32MP151Dxx: -+ return true; -+ default: -+ return id == 1; -+ } -+} -+ -+__weak void board_vddcore_init(u32 voltage_mv) -+{ -+} -+ -+/* -+ * gets OPP parameters (frequency in KHz and voltage in mV) from -+ * an OPP table subnode. Platform HW support capabilities are also checked. -+ * Returns 0 on success and a negative FDT error code on failure. -+ */ -+static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode, -+ u32 *freq_khz, u32 *voltage_mv) -+{ -+ u32 opp_hw; -+ u64 read_freq_64; -+ u32 read_voltage_32; -+ -+ *freq_khz = 0; -+ *voltage_mv = 0; -+ -+ opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0); -+ if (opp_hw) -+ if (!stm32mp1_supports_opp(opp_hw, cpu_type)) -+ return -FDT_ERR_BADVALUE; -+ -+ read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) / -+ 1000ULL; -+ read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) / -+ 1000U; -+ -+ if (!read_voltage_32 || !read_freq_64) -+ return -FDT_ERR_NOTFOUND; -+ -+ /* Frequency value expressed in KHz must fit on 32 bits */ -+ if (read_freq_64 > U32_MAX) -+ return -FDT_ERR_BADVALUE; -+ -+ /* Millivolt value must fit on 16 bits */ -+ if (read_voltage_32 > U16_MAX) -+ return -FDT_ERR_BADVALUE; -+ -+ *freq_khz = (u32)read_freq_64; -+ *voltage_mv = read_voltage_32; -+ -+ return 0; -+} -+ -+/* -+ * parses OPP table in DT and finds the parameters for the -+ * highest frequency supported by the HW platform. -+ * Returns 0 on success and a negative FDT error code on failure. -+ */ -+int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz) -+{ -+ ofnode node, subnode; -+ int ret; -+ u32 freq = 0U, voltage = 0U; -+ u32 cpu_type = get_cpu_type(); -+ -+ node = ofnode_by_compatible(ofnode_null(), "operating-points-v2"); -+ if (!ofnode_valid(node)) -+ return -FDT_ERR_NOTFOUND; -+ -+ ofnode_for_each_subnode(subnode, node) { -+ unsigned int read_freq; -+ unsigned int read_voltage; -+ -+ ret = stm32mp1_get_opp(cpu_type, subnode, -+ &read_freq, &read_voltage); -+ if (ret) -+ continue; -+ -+ if (read_freq > freq) { -+ freq = read_freq; -+ voltage = read_voltage; -+ } -+ } -+ -+ if (!freq || !voltage) -+ return -FDT_ERR_NOTFOUND; -+ -+ *freq_hz = (u64)1000U * freq; -+ board_vddcore_init(voltage); -+ -+ return 0; -+} -+ -+static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc, -+ u32 *pllcfg, u32 *fracv) -+{ -+ u32 post_divm; -+ u32 input_freq; -+ u64 output_freq; -+ u64 freq; -+ u64 vco; -+ u32 divm, divn, divp, frac; -+ int i, ret; -+ u32 diff; -+ u32 best_diff = U32_MAX; -+ -+ /* PLL1 is 1600 */ -+ const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max; -+ const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U; -+ const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U; -+ -+ ret = stm32mp1_get_max_opp_freq(priv, &output_freq); -+ if (ret) { -+ debug("PLL1 OPP configuraton not found (%d).\n", ret); -+ return ret; -+ } -+ -+ switch (clksrc) { -+ case CLK_PLL12_HSI: -+ input_freq = stm32mp1_clk_get_fixed(priv, _HSI); -+ break; -+ case CLK_PLL12_HSE: -+ input_freq = stm32mp1_clk_get_fixed(priv, _HSE); -+ break; -+ default: -+ return -EINTR; -+ } -+ -+ /* Following parameters have always the same value */ -+ pllcfg[PLLCFG_Q] = 0; -+ pllcfg[PLLCFG_R] = 0; -+ pllcfg[PLLCFG_O] = PQR(1, 0, 0); -+ -+ for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) { -+ post_divm = (u32)(input_freq / (divm + 1)); -+ if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX) -+ continue; -+ -+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { -+ freq = output_freq * (divm + 1) * (divp + 1); -+ divn = (u32)((freq / input_freq) - 1); -+ if (divn < DIVN_MIN || divn > DIVN_MAX) -+ continue; -+ -+ frac = (u32)(((freq * FRAC_MAX) / input_freq) - -+ ((divn + 1) * FRAC_MAX)); -+ /* 2 loops to refine the fractional part */ -+ for (i = 2; i != 0; i--) { -+ if (frac > FRAC_MAX) -+ break; -+ -+ vco = (post_divm * (divn + 1)) + -+ ((post_divm * (u64)frac) / -+ FRAC_MAX); -+ if (vco < (PLL1600_VCO_MIN / 2) || -+ vco > (PLL1600_VCO_MAX / 2)) { -+ frac++; -+ continue; -+ } -+ freq = vco / (divp + 1); -+ if (output_freq < freq) -+ diff = (u32)(freq - output_freq); -+ else -+ diff = (u32)(output_freq - freq); -+ if (diff < best_diff) { -+ pllcfg[PLLCFG_M] = divm; -+ pllcfg[PLLCFG_N] = divn; -+ pllcfg[PLLCFG_P] = divp; -+ *fracv = frac; -+ -+ if (diff == 0) -+ return 0; -+ -+ best_diff = diff; -+ } -+ frac++; -+ } -+ } -+ } -+ -+ if (best_diff == U32_MAX) -+ return -1; -+ -+ return 0; -+} -+ - static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, - u32 mask_on) - { -@@ -1217,7 +1442,7 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, - } - - static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, -- int lsedrv) -+ u32 lsedrv) - { - u32 value; - -@@ -1316,7 +1541,7 @@ static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) - break; - - if (hsidiv == 4) { -- pr_err("clk-hsi frequency invalid"); -+ pr_err("hsi frequency invalid"); - return -1; - } - -@@ -1649,7 +1874,10 @@ static int stm32mp1_clktree(struct udevice *dev) - unsigned int clksrc[CLKSRC_NB]; - unsigned int clkdiv[CLKDIV_NB]; - unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; -- ofnode plloff[_PLL_NB]; -+ unsigned int pllfracv[_PLL_NB]; -+ unsigned int pllcsg[_PLL_NB][PLLCSG_NB]; -+ bool pllcfg_valid[_PLL_NB]; -+ bool pllcsg_set[_PLL_NB]; - int ret; - int i, len; - int lse_css = 0; -@@ -1671,16 +1899,43 @@ static int stm32mp1_clktree(struct udevice *dev) - /* check mandatory field in each pll */ - for (i = 0; i < _PLL_NB; i++) { - char name[12]; -+ ofnode node; - - sprintf(name, "st,pll@%d", i); -- plloff[i] = dev_read_subnode(dev, name); -- if (!ofnode_valid(plloff[i])) -- continue; -- ret = ofnode_read_u32_array(plloff[i], "cfg", -- pllcfg[i], PLLCFG_NB); -- if (ret < 0) { -- debug("field cfg invalid: error %d\n", ret); -- return -FDT_ERR_NOTFOUND; -+ node = dev_read_subnode(dev, name); -+ pllcfg_valid[i] = ofnode_valid(node); -+ pllcsg_set[i] = false; -+ if (pllcfg_valid[i]) { -+ debug("DT for PLL %d @ %s\n", i, name); -+ ret = ofnode_read_u32_array(node, "cfg", -+ pllcfg[i], PLLCFG_NB); -+ if (ret < 0) { -+ debug("field cfg invalid: error %d\n", ret); -+ return -FDT_ERR_NOTFOUND; -+ } -+ pllfracv[i] = ofnode_read_u32_default(node, "frac", 0); -+ -+ ret = ofnode_read_u32_array(node, "csg", pllcsg[i], -+ PLLCSG_NB); -+ if (!ret) { -+ pllcsg_set[i] = true; -+ } else if (ret != -FDT_ERR_NOTFOUND) { -+ debug("invalid csg node for pll@%d res=%d\n", -+ i, ret); -+ return ret; -+ } -+ } else if (i == _PLL1) { -+ /* use OPP for PLL1 for A7 CPU */ -+ debug("DT for PLL %d with OPP\n", i); -+ ret = stm32mp1_pll1_opp(priv, -+ clksrc[CLKSRC_PLL12], -+ pllcfg[i], -+ &pllfracv[i]); -+ if (ret) { -+ debug("PLL %d with OPP error = %d\n", i, ret); -+ return ret; -+ } -+ pllcfg_valid[i] = true; - } - } - -@@ -1693,12 +1948,13 @@ static int stm32mp1_clktree(struct udevice *dev) - * switch ON oscillator found in device-tree, - * HSI already ON after bootrom - */ -- if (priv->osc[_LSI]) -+ if (clk_valid(&priv->osc_clk[_LSI])) - stm32mp1_lsi_set(rcc, 1); - -- if (priv->osc[_LSE]) { -- int bypass, digbyp, lsedrv; -- struct udevice *dev = priv->osc_dev[_LSE]; -+ if (clk_valid(&priv->osc_clk[_LSE])) { -+ int bypass, digbyp; -+ u32 lsedrv; -+ struct udevice *dev = priv->osc_clk[_LSE].dev; - - bypass = dev_read_bool(dev, "st,bypass"); - digbyp = dev_read_bool(dev, "st,digbypass"); -@@ -1709,9 +1965,9 @@ static int stm32mp1_clktree(struct udevice *dev) - stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); - } - -- if (priv->osc[_HSE]) { -+ if (clk_valid(&priv->osc_clk[_HSE])) { - int bypass, digbyp, css; -- struct udevice *dev = priv->osc_dev[_HSE]; -+ struct udevice *dev = priv->osc_clk[_HSE].dev; - - bypass = dev_read_bool(dev, "st,bypass"); - digbyp = dev_read_bool(dev, "st,digbypass"); -@@ -1736,8 +1992,8 @@ static int stm32mp1_clktree(struct udevice *dev) - - /* configure HSIDIV */ - debug("configure HSIDIV\n"); -- if (priv->osc[_HSI]) { -- stm32mp1_hsidiv(rcc, priv->osc[_HSI]); -+ if (clk_valid(&priv->osc_clk[_HSI])) { -+ stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI])); - stgen_config(priv); - } - -@@ -1765,36 +2021,25 @@ static int stm32mp1_clktree(struct udevice *dev) - /* configure and start PLLs */ - debug("configure PLLs\n"); - for (i = 0; i < _PLL_NB; i++) { -- u32 fracv; -- u32 csg[PLLCSG_NB]; -- -- debug("configure PLL %d @ %d\n", i, -- ofnode_to_offset(plloff[i])); -- if (!ofnode_valid(plloff[i])) -+ if (!pllcfg_valid[i]) - continue; -- -- fracv = ofnode_read_u32_default(plloff[i], "frac", 0); -- pll_config(priv, i, pllcfg[i], fracv); -- ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); -- if (!ret) { -- pll_csg(priv, i, csg); -- } else if (ret != -FDT_ERR_NOTFOUND) { -- debug("invalid csg node for pll@%d res=%d\n", i, ret); -- return ret; -- } -+ debug("configure PLL %d\n", i); -+ pll_config(priv, i, pllcfg[i], pllfracv[i]); -+ if (pllcsg_set[i]) -+ pll_csg(priv, i, pllcsg[i]); - pll_start(priv, i); - } - - /* wait and start PLLs ouptut when ready */ - for (i = 0; i < _PLL_NB; i++) { -- if (!ofnode_valid(plloff[i])) -+ if (!pllcfg_valid[i]) - continue; - debug("output PLL %d\n", i); - pll_output(priv, i, pllcfg[i][PLLCFG_O]); - } - - /* wait LSE ready before to use it */ -- if (priv->osc[_LSE]) -+ if (clk_valid(&priv->osc_clk[_LSE])) - stm32mp1_lse_wait(rcc); - - /* configure with expected clock source */ -@@ -1833,7 +2078,7 @@ static int stm32mp1_clktree(struct udevice *dev) - - debug("oscillator off\n"); - /* switch OFF HSI if not found in device-tree */ -- if (!priv->osc[_HSI]) -+ if (!clk_valid(&priv->osc_clk[_HSI])) - stm32mp1_hsi_set(rcc, 0); - - /* Software Self-Refresh mode (SSR) during DDR initilialization */ -@@ -1931,40 +2176,25 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) - return -EINVAL; - } - --static void stm32mp1_osc_clk_init(const char *name, -- struct stm32mp1_clk_priv *priv, -- int index) --{ -- struct clk clk; -- struct udevice *dev = NULL; -- -- priv->osc[index] = 0; -- clk.id = 0; -- if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { -- if (clk_request(dev, &clk)) -- pr_err("%s request", name); -- else -- priv->osc[index] = clk_get_rate(&clk); -- } -- priv->osc_dev[index] = dev; --} -- - static void stm32mp1_osc_init(struct udevice *dev) - { - struct stm32mp1_clk_priv *priv = dev_get_priv(dev); - int i; - const char *name[NB_OSC] = { -- [_LSI] = "clk-lsi", -- [_LSE] = "clk-lse", -- [_HSI] = "clk-hsi", -- [_HSE] = "clk-hse", -- [_CSI] = "clk-csi", -+ [_LSI] = "lsi", -+ [_LSE] = "lse", -+ [_HSI] = "hsi", -+ [_HSE] = "hse", -+ [_CSI] = "csi", - [_I2S_CKIN] = "i2s_ckin", - }; - - for (i = 0; i < NB_OSC; i++) { -- stm32mp1_osc_clk_init(name[i], priv, i); -- debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); -+ if (clk_get_by_name(dev, name[i], &priv->osc_clk[i])) -+ dev_dbg(dev, "No source clock \"%s\"", name[i]); -+ else -+ dev_dbg(dev, "%s clock rate: %luHz\n", -+ name[i], clk_get_rate(&priv->osc_clk[i])); - } - } - -@@ -2037,6 +2267,8 @@ static int stm32mp1_clk_probe(struct udevice *dev) - /* clock tree init is done only one time, before relocation */ - if (!(gd->flags & GD_FLG_RELOC)) - result = stm32mp1_clktree(dev); -+ if (result) -+ printf("clock tree initialization failed (%d)\n", result); - #endif - - #ifndef CONFIG_SPL_BUILD -diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c -index 945b814..86fe42a 100644 ---- a/drivers/core/of_access.c -+++ b/drivers/core/of_access.c -@@ -170,6 +170,38 @@ const void *of_get_property(const struct device_node *np, const char *name, - return pp ? pp->value : NULL; - } - -+const struct property *of_get_first_property(const struct device_node *np) -+{ -+ if (!np) -+ return NULL; -+ -+ return np->properties; -+} -+ -+const struct property *of_get_next_property(const struct device_node *np, -+ const struct property *property) -+{ -+ if (!np) -+ return NULL; -+ -+ return property->next; -+} -+ -+const void *of_get_property_by_prop(const struct device_node *np, -+ const struct property *property, -+ const char **name, -+ int *lenp) -+{ -+ if (!np || !property) -+ return NULL; -+ if (name) -+ *name = property->name; -+ if (lenp) -+ *lenp = property->length; -+ -+ return property->value; -+} -+ - static const char *of_prop_next_string(struct property *prop, const char *cur) - { - const void *curv = cur; -diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c -index 8f0eab2..cb27562 100644 ---- a/drivers/core/ofnode.c -+++ b/drivers/core/ofnode.c -@@ -536,6 +536,54 @@ const void *ofnode_get_property(ofnode node, const char *propname, int *lenp) - propname, lenp); - } - -+int ofnode_get_first_property(ofnode node, struct ofprop *prop) -+{ -+ prop->node = node; -+ -+ if (ofnode_is_np(node)) { -+ prop->prop = of_get_first_property(ofnode_to_np(prop->node)); -+ if (!prop->prop) -+ return -FDT_ERR_NOTFOUND; -+ } else { -+ prop->offset = -+ fdt_first_property_offset(gd->fdt_blob, -+ ofnode_to_offset(prop->node)); -+ if (prop->offset < 0) -+ return prop->offset; -+ } -+ -+ return 0; -+} -+ -+int ofnode_get_next_property(struct ofprop *prop) -+{ -+ if (ofnode_is_np(prop->node)) { -+ prop->prop = of_get_next_property(ofnode_to_np(prop->node), -+ prop->prop); -+ if (!prop->prop) -+ return -FDT_ERR_NOTFOUND; -+ } else { -+ prop->offset = fdt_next_property_offset(gd->fdt_blob, -+ prop->offset); -+ if (prop->offset < 0) -+ return prop->offset; -+ } -+ -+ return 0; -+} -+ -+const void *ofnode_get_property_by_prop(const struct ofprop *prop, -+ const char **propname, int *lenp) -+{ -+ if (ofnode_is_np(prop->node)) -+ return of_get_property_by_prop(ofnode_to_np(prop->node), -+ prop->prop, propname, lenp); -+ else -+ return fdt_getprop_by_offset(gd->fdt_blob, -+ prop->offset, -+ propname, lenp); -+} -+ - bool ofnode_is_available(ofnode node) - { - if (ofnode_is_np(node)) -diff --git a/drivers/core/read.c b/drivers/core/read.c -index 9602e52..a9f5d14 100644 ---- a/drivers/core/read.c -+++ b/drivers/core/read.c -@@ -238,6 +238,22 @@ const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp) - return ofnode_get_property(dev_ofnode(dev), propname, lenp); - } - -+int dev_read_first_prop(struct udevice *dev, struct ofprop *prop) -+{ -+ return ofnode_get_first_property(dev_ofnode(dev), prop); -+} -+ -+int dev_read_next_prop(struct ofprop *prop) -+{ -+ return ofnode_get_next_property(prop); -+} -+ -+const void *dev_read_prop_by_prop(struct ofprop *prop, -+ const char **propname, int *lenp) -+{ -+ return ofnode_get_property_by_prop(prop, propname, lenp); -+} -+ - int dev_read_alias_seq(struct udevice *dev, int *devnump) - { - ofnode node = dev_ofnode(dev); -diff --git a/drivers/core/root.c b/drivers/core/root.c -index e856438..14df16c 100644 ---- a/drivers/core/root.c -+++ b/drivers/core/root.c -@@ -203,15 +203,6 @@ static int dm_scan_fdt_live(struct udevice *parent, - int ret = 0, err; - - for (np = node_parent->child; np; np = np->sibling) { -- /* "chosen" node isn't a device itself but may contain some: */ -- if (!strcmp(np->name, "chosen")) { -- pr_debug("parsing subnodes of \"chosen\"\n"); -- -- err = dm_scan_fdt_live(parent, np, pre_reloc_only); -- if (err && !ret) -- ret = err; -- continue; -- } - - if (!of_device_is_available(np)) { - pr_debug(" - ignoring disabled device\n"); -@@ -256,21 +247,6 @@ static int dm_scan_fdt_node(struct udevice *parent, const void *blob, - offset = fdt_next_subnode(blob, offset)) { - const char *node_name = fdt_get_name(blob, offset, NULL); - -- /* -- * The "chosen" and "firmware" nodes aren't devices -- * themselves but may contain some: -- */ -- if (!strcmp(node_name, "chosen") || -- !strcmp(node_name, "firmware")) { -- pr_debug("parsing subnodes of \"%s\"\n", node_name); -- -- err = dm_scan_fdt_node(parent, blob, offset, -- pre_reloc_only); -- if (err && !ret) -- ret = err; -- continue; -- } -- - if (!fdtdec_get_is_enabled(blob, offset)) { - pr_debug(" - ignoring disabled device\n"); - continue; -@@ -315,7 +291,8 @@ int dm_scan_fdt(const void *blob, bool pre_reloc_only) - return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only); - } - --static int dm_scan_fdt_ofnode_path(const char *path, bool pre_reloc_only) -+static int dm_scan_fdt_ofnode_path(const void *blob, const char *path, -+ bool pre_reloc_only) - { - ofnode node; - -@@ -327,13 +304,18 @@ static int dm_scan_fdt_ofnode_path(const char *path, bool pre_reloc_only) - if (of_live_active()) - return dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only); - #endif -- return dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node.of_offset, -+ return dm_scan_fdt_node(gd->dm_root, blob, node.of_offset, - pre_reloc_only); - } - - int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only) - { -- int ret; -+ int ret, i; -+ const char * const nodes[] = { -+ "/chosen", -+ "/clocks", -+ "/firmware" -+ }; - - ret = dm_scan_fdt(blob, pre_reloc_only); - if (ret) { -@@ -341,16 +323,16 @@ int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only) - return ret; - } - -- ret = dm_scan_fdt_ofnode_path("/clocks", pre_reloc_only); -- if (ret) { -- debug("scan for /clocks failed: %d\n", ret); -- return ret; -+ /* Some nodes aren't devices themselves but may contain some */ -+ for (i = 0; i < ARRAY_SIZE(nodes); i++) { -+ ret = dm_scan_fdt_ofnode_path(blob, nodes[i], pre_reloc_only); -+ if (ret) { -+ debug("dm_scan_fdt() scan for %s failed: %d\n", -+ nodes[i], ret); -+ return ret; -+ } - } - -- ret = dm_scan_fdt_ofnode_path("/firmware", pre_reloc_only); -- if (ret) -- debug("scan for /firmware failed: %d\n", ret); -- - return ret; - } - #endif -diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig -index 75fe0a1..1783656 100644 ---- a/drivers/dfu/Kconfig -+++ b/drivers/dfu/Kconfig -@@ -68,5 +68,10 @@ config DFU_VIRT - used at board level to manage specific behavior - (OTP update for example). - -+config SET_DFU_ALT_INFO -+ bool "Dynamic set of DFU alternate information" -+ help -+ This option allows to call the function set_dfu_alt_info to -+ dynamically build dfu_alt_info in board. - endif - endmenu -diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig -index 9f85054..a17e488 100644 ---- a/drivers/fastboot/Kconfig -+++ b/drivers/fastboot/Kconfig -@@ -104,6 +104,60 @@ config FASTBOOT_FLASH_NAND_TRIMFFS - When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff - pages. - -+config FASTBOOT_MMC_BOOT_SUPPORT -+ bool "Enable EMMC_BOOT flash/erase" -+ depends on FASTBOOT_FLASH_MMC -+ help -+ The fastboot "flash" and "erase" commands normally does operations -+ on eMMC userdata. Define this to enable the special commands to -+ flash/erase eMMC boot partition. -+ The default target name for updating eMMC boot partition 1/2 is -+ CONFIG_FASTBOOT_MMC_BOOT1_NAME/CONFIG_FASTBOOT_MMC_BOOT2_NAME. -+ -+config FASTBOOT_MMC_BOOT1_NAME -+ string "Target name for updating EMMC_BOOT1" -+ depends on FASTBOOT_MMC_BOOT_SUPPORT -+ default "mmc0boot0" -+ help -+ The fastboot "flash" and "erase" commands support operations on -+ EMMC_BOOT1. This occurs when the specified "EMMC_BOOT1 name" on -+ the "fastboot flash" and "fastboot erase" commands match the value -+ defined here. -+ The default target name for updating EMMC_BOOT1 is "mmc0boot0". -+ -+config FASTBOOT_MMC_BOOT2_NAME -+ string "Target name for updating EMMC_BOOT2" -+ depends on FASTBOOT_MMC_BOOT_SUPPORT -+ default "mmc0boot1" -+ help -+ The fastboot "flash" and "erase" commands support operations on -+ EMMC_BOOT2. This occurs when the specified "EMMC_BOOT2 name" on -+ the "fastboot flash" and "fastboot erase" commands match the value -+ defined here. -+ The default target name for updating EMMC_BOOT2 is "mmc0boot1". -+ -+config FASTBOOT_MMC_USER_SUPPORT -+ bool "Enable eMMC userdata partition flash/erase" -+ depends on FASTBOOT_FLASH_MMC -+ help -+ Define this to enable the support "flash" and "erase" command on -+ eMMC userdata. The "flash" command only update the MBR and GPT -+ header when CONFIG_EFI_PARTITION is supported. -+ The "erase" command erase all the userdata. -+ This occurs when the specified "partition name" on the -+ fastboot command line matches the value CONFIG_FASTBOOT_MMC_USER_NAME. -+ -+config FASTBOOT_MMC_USER_NAME -+ string "Target name for updating EMMC_USER" -+ depends on FASTBOOT_MMC_USER_SUPPORT -+ default "mmc0" -+ help -+ The fastboot "flash" and "erase" command supports EMMC_USER. -+ This occurs when the specified "EMMC_USER name" on the -+ "fastboot flash" and the "fastboot erase" commands match the value -+ defined here. -+ The default target name for erasing EMMC_USER is "mmc0". -+ - config FASTBOOT_GPT_NAME - string "Target name for updating GPT" - depends on FASTBOOT_FLASH_MMC && EFI_PARTITION -@@ -135,6 +189,20 @@ config FASTBOOT_CMD_OEM_FORMAT - relies on the env variable partitions to contain the list of - partitions as required by the gpt command. - -+config FASTBOOT_CMD_OEM_PARTCONF -+ bool "Enable the 'oem partconf' command" -+ depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT -+ help -+ Add support for the "oem partconf" command from a client. This set -+ the mmc boot-partition for the selecting eMMC device. -+ -+config FASTBOOT_CMD_OEM_BOOTBUS -+ bool "Enable the 'oem bootbus' command" -+ depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT -+ help -+ Add support for the "oem bootbus" command from a client. This set -+ the mmc boot configuration for the selecting eMMC device. -+ - endif # FASTBOOT - - endmenu -diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c -index 3c4acfe..842aa5e 100644 ---- a/drivers/fastboot/fb_command.c -+++ b/drivers/fastboot/fb_command.c -@@ -39,6 +39,12 @@ static void reboot_bootloader(char *, char *); - #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) - static void oem_format(char *, char *); - #endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) -+static void oem_partconf(char *, char *); -+#endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) -+static void oem_bootbus(char *, char *); -+#endif - - static const struct { - const char *command; -@@ -88,6 +94,18 @@ static const struct { - .dispatch = oem_format, - }, - #endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) -+ [FASTBOOT_COMMAND_OEM_PARTCONF] = { -+ .command = "oem partconf", -+ .dispatch = oem_partconf, -+ }, -+#endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) -+ [FASTBOOT_COMMAND_OEM_BOOTBUS] = { -+ .command = "oem bootbus", -+ .dispatch = oem_bootbus, -+ }, -+#endif - }; - - /** -@@ -335,3 +353,57 @@ static void oem_format(char *cmd_parameter, char *response) - } - } - #endif -+ -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) -+/** -+ * oem_partconf() - Execute the OEM partconf command -+ * -+ * @cmd_parameter: Pointer to command parameter -+ * @response: Pointer to fastboot response buffer -+ */ -+static void oem_partconf(char *cmd_parameter, char *response) -+{ -+ char cmdbuf[32]; -+ -+ if (!cmd_parameter) { -+ fastboot_fail("Expected command parameter", response); -+ return; -+ } -+ -+ /* execute 'mmc partconfg' command with cmd_parameter arguments*/ -+ snprintf(cmdbuf, sizeof(cmdbuf), "mmc partconf %x %s 0", -+ CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter); -+ printf("Execute: %s\n", cmdbuf); -+ if (run_command(cmdbuf, 0)) -+ fastboot_fail("Cannot set oem partconf", response); -+ else -+ fastboot_okay(NULL, response); -+} -+#endif -+ -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) -+/** -+ * oem_bootbus() - Execute the OEM bootbus command -+ * -+ * @cmd_parameter: Pointer to command parameter -+ * @response: Pointer to fastboot response buffer -+ */ -+static void oem_bootbus(char *cmd_parameter, char *response) -+{ -+ char cmdbuf[32]; -+ -+ if (!cmd_parameter) { -+ fastboot_fail("Expected command parameter", response); -+ return; -+ } -+ -+ /* execute 'mmc bootbus' command with cmd_parameter arguments*/ -+ snprintf(cmdbuf, sizeof(cmdbuf), "mmc bootbus %x %s", -+ CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter); -+ printf("Execute: %s\n", cmdbuf); -+ if (run_command(cmdbuf, 0)) -+ fastboot_fail("Cannot set oem bootbus", response); -+ else -+ fastboot_okay(NULL, response); -+} -+#endif -diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c -index b0b19c5..09ba2f2 100644 ---- a/drivers/fastboot/fb_mmc.c -+++ b/drivers/fastboot/fb_mmc.c -@@ -129,6 +129,82 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info, - fastboot_okay(NULL, response); - } - -+#if defined(CONFIG_FASTBOOT_MMC_BOOT_SUPPORT) || \ -+ defined(CONFIG_FASTBOOT_MMC_USER_SUPPORT) -+static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc) -+{ -+ lbaint_t blks; -+ -+ debug("Start Erasing mmc hwpart[%u]...\n", dev_desc->hwpart); -+ -+ blks = fb_mmc_blk_write(dev_desc, 0, dev_desc->lba, NULL); -+ -+ if (blks != dev_desc->lba) { -+ pr_err("Failed to erase mmc hwpart[%u]\n", dev_desc->hwpart); -+ return 1; -+ } -+ -+ printf("........ erased %lu bytes from mmc hwpart[%u]\n", -+ dev_desc->lba * dev_desc->blksz, dev_desc->hwpart); -+ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT -+static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer, -+ int hwpart, u32 buff_sz, char *response) -+{ -+ lbaint_t blkcnt; -+ lbaint_t blks; -+ unsigned long blksz; -+ -+ // To operate on EMMC_BOOT1/2 (mmc0boot0/1) we first change the hwpart -+ if (blk_dselect_hwpart(dev_desc, hwpart)) { -+ pr_err("Failed to select hwpart\n"); -+ fastboot_fail("Failed to select hwpart", response); -+ return; -+ } -+ -+ if (buffer) { /* flash */ -+ -+ /* determine number of blocks to write */ -+ blksz = dev_desc->blksz; -+ blkcnt = ((buff_sz + (blksz - 1)) & ~(blksz - 1)); -+ blkcnt = lldiv(blkcnt, blksz); -+ -+ if (blkcnt > dev_desc->lba) { -+ pr_err("Image size too large\n"); -+ fastboot_fail("Image size too large", response); -+ return; -+ } -+ -+ debug("Start Flashing Image to EMMC_BOOT%d...\n", hwpart); -+ -+ blks = fb_mmc_blk_write(dev_desc, 0, blkcnt, buffer); -+ -+ if (blks != blkcnt) { -+ pr_err("Failed to write EMMC_BOOT%d\n", hwpart); -+ fastboot_fail("Failed to write EMMC_BOOT part", -+ response); -+ return; -+ } -+ -+ printf("........ wrote %lu bytes to EMMC_BOOT%d\n", -+ blkcnt * blksz, hwpart); -+ } else { /* erase */ -+ if (fb_mmc_erase_mmc_hwpart(dev_desc)) { -+ pr_err("Failed to erase EMMC_BOOT%d\n", hwpart); -+ fastboot_fail("Failed to erase EMMC_BOOT part", -+ response); -+ return; -+ } -+ } -+ -+ fastboot_okay(NULL, response); -+} -+#endif -+ - #ifdef CONFIG_ANDROID_BOOT_IMAGE - /** - * Read Android boot image header from boot partition. -@@ -345,8 +421,26 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, - return; - } - -+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT -+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) { -+ fb_mmc_boot_ops(dev_desc, download_buffer, 1, -+ download_bytes, response); -+ return; -+ } -+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) { -+ fb_mmc_boot_ops(dev_desc, download_buffer, 2, -+ download_bytes, response); -+ return; -+ } -+#endif -+ - #if CONFIG_IS_ENABLED(EFI_PARTITION) -+#ifndef CONFIG_FASTBOOT_MMC_USER_SUPPORT - if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { -+#else -+ if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 || -+ strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { -+#endif - printf("%s: updating MBR, Primary and Backup GPT(s)\n", - __func__); - if (is_valid_gpt_buf(dev_desc, download_buffer)) { -@@ -457,6 +551,30 @@ void fastboot_mmc_erase(const char *cmd, char *response) - return; - } - -+#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT -+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) { -+ /* erase EMMC boot1 */ -+ fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response); -+ return; -+ } -+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) { -+ /* erase EMMC boot2 */ -+ fb_mmc_boot_ops(dev_desc, NULL, 2, 0, response); -+ return; -+ } -+#endif -+ -+#ifdef CONFIG_FASTBOOT_MMC_USER_SUPPORT -+ if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { -+ /* erase EMMC userdata */ -+ if (fb_mmc_erase_mmc_hwpart(dev_desc)) -+ fastboot_fail("Failed to erase EMMC_USER", response); -+ else -+ fastboot_okay(NULL, response); -+ return; -+ } -+#endif -+ - ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info); - if (ret < 0) { - pr_err("cannot find partition: '%s'\n", cmd); -diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c -index 90fbed4..5da28e6 100644 ---- a/drivers/gpio/gpio-uclass.c -+++ b/drivers/gpio/gpio-uclass.c -@@ -19,6 +19,22 @@ - DECLARE_GLOBAL_DATA_PTR; - - /** -+ * gpio_desc_init() - Initialize the GPIO descriptor -+ * -+ * @desc: GPIO descriptor to initialize -+ * @dev: GPIO device -+ * @offset: Offset of device GPIO -+ */ -+static void gpio_desc_init(struct gpio_desc *desc, -+ struct udevice *dev, -+ uint offset) -+{ -+ desc->dev = dev; -+ desc->offset = offset; -+ desc->flags = 0; -+} -+ -+/** - * gpio_to_device() - Convert global GPIO number to device, number - * - * Convert the GPIO number to an entry in the list of GPIOs -@@ -41,9 +57,7 @@ static int gpio_to_device(unsigned int gpio, struct gpio_desc *desc) - uc_priv = dev_get_uclass_priv(dev); - if (gpio >= uc_priv->gpio_base && - gpio < uc_priv->gpio_base + uc_priv->gpio_count) { -- desc->dev = dev; -- desc->offset = gpio - uc_priv->gpio_base; -- desc->flags = 0; -+ gpio_desc_init(desc, dev, gpio - uc_priv->gpio_base); - return 0; - } - } -@@ -85,8 +99,7 @@ int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc) - if (!dev) - return ret ? ret : -EINVAL; - -- desc->dev = dev; -- desc->offset = offset; -+ gpio_desc_init(desc, dev, offset); - - return 0; - } -@@ -127,8 +140,27 @@ int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc, - if (args->args_count < 2) - return 0; - -+ desc->flags = 0; - if (args->args[1] & GPIO_ACTIVE_LOW) -- desc->flags = GPIOD_ACTIVE_LOW; -+ desc->flags |= GPIOD_ACTIVE_LOW; -+ -+ /* -+ * need to test 2 bits for gpio output binding: -+ * OPEN_DRAIN (0x6) = SINGLE_ENDED (0x2) | LINE_OPEN_DRAIN (0x4) -+ * OPEN_SOURCE (0x2) = SINGLE_ENDED (0x2) | LINE_OPEN_SOURCE (0x0) -+ */ -+ if (args->args[1] & GPIO_SINGLE_ENDED) { -+ if (args->args[1] & GPIO_LINE_OPEN_DRAIN) -+ desc->flags |= GPIOD_OPEN_DRAIN; -+ else -+ desc->flags |= GPIOD_OPEN_SOURCE; -+ } -+ -+ if (args->args[1] & GPIO_PULL_UP) -+ desc->flags |= GPIOD_PULL_UP; -+ -+ if (args->args[1] & GPIO_PULL_DOWN) -+ desc->flags |= GPIOD_PULL_DOWN; - - return 0; - } -@@ -463,18 +495,24 @@ int gpio_direction_output(unsigned gpio, int value) - desc.offset, value); - } - --int dm_gpio_get_value(const struct gpio_desc *desc) -+static int _gpio_get_value(const struct gpio_desc *desc) - { - int value; -+ -+ value = gpio_get_ops(desc->dev)->get_value(desc->dev, desc->offset); -+ -+ return desc->flags & GPIOD_ACTIVE_LOW ? !value : value; -+} -+ -+int dm_gpio_get_value(const struct gpio_desc *desc) -+{ - int ret; - - ret = check_reserved(desc, "get_value"); - if (ret) - return ret; - -- value = gpio_get_ops(desc->dev)->get_value(desc->dev, desc->offset); -- -- return desc->flags & GPIOD_ACTIVE_LOW ? !value : value; -+ return _gpio_get_value(desc); - } - - int dm_gpio_set_value(const struct gpio_desc *desc, int value) -@@ -491,71 +529,128 @@ int dm_gpio_set_value(const struct gpio_desc *desc, int value) - return 0; - } - --int dm_gpio_get_open_drain(struct gpio_desc *desc) -+/* check dir flags invalid configuration */ -+static int check_dir_flags(ulong flags) - { -- struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); -- int ret; -+ if ((flags & GPIOD_IS_OUT) && (flags & GPIOD_IS_IN)) { -+ log_debug("%s: flags 0x%lx has GPIOD_IS_OUT and GPIOD_IS_IN\n", -+ __func__, flags); -+ return -EINVAL; -+ } -+ -+ if ((flags & GPIOD_PULL_UP) && (flags & GPIOD_PULL_DOWN)) { -+ log_debug("%s: flags 0x%lx has GPIOD_PULL_UP and GPIOD_PULL_DOWN\n", -+ __func__, flags); -+ return -EINVAL; -+ } -+ -+ if ((flags & GPIOD_OPEN_DRAIN) && (flags & GPIOD_OPEN_SOURCE)) { -+ log_debug("%s: flags 0x%lx has GPIOD_OPEN_DRAIN and GPIOD_OPEN_SOURCE\n", -+ __func__, flags); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int _dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) -+{ -+ struct udevice *dev = desc->dev; -+ struct dm_gpio_ops *ops = gpio_get_ops(dev); -+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); -+ int ret = 0; -+ -+ ret = check_dir_flags(flags); -+ if (ret) { -+ dev_dbg(dev, -+ "%s error: set_dir_flags for gpio %s%d has invalid dir flags 0x%lx\n", -+ desc->dev->name, -+ uc_priv->bank_name ? uc_priv->bank_name : "", -+ desc->offset, flags); - -- ret = check_reserved(desc, "get_open_drain"); -- if (ret) - return ret; -+ } - -- if (ops->set_open_drain) -- return ops->get_open_drain(desc->dev, desc->offset); -- else -- return -ENOSYS; -+ /* GPIOD_ are directly managed by driver in set_dir_flags*/ -+ if (ops->set_dir_flags) { -+ ret = ops->set_dir_flags(dev, desc->offset, flags); -+ } else { -+ if (flags & GPIOD_IS_OUT) { -+ ret = ops->direction_output(dev, desc->offset, -+ GPIOD_FLAGS_OUTPUT(flags)); -+ } else if (flags & GPIOD_IS_IN) { -+ ret = ops->direction_input(dev, desc->offset); -+ } -+ } -+ -+ return ret; - } - --int dm_gpio_set_open_drain(struct gpio_desc *desc, int value) -+int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) - { -- struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); - int ret; - -- ret = check_reserved(desc, "set_open_drain"); -+ ret = check_reserved(desc, "set_dir_flags"); - if (ret) - return ret; - -- if (ops->set_open_drain) -- ret = ops->set_open_drain(desc->dev, desc->offset, value); -- else -- return 0; /* feature not supported -> ignore setting */ -+ /* combine the requested flags (for IN/OUT) and the descriptor flags */ -+ flags |= desc->flags; -+ ret = _dm_gpio_set_dir_flags(desc, flags); -+ -+ /* update the descriptor flags */ -+ if (ret) -+ desc->flags = flags; - - return ret; - } - --int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) -+int dm_gpio_set_dir(struct gpio_desc *desc) - { -- struct udevice *dev = desc->dev; -- struct dm_gpio_ops *ops = gpio_get_ops(dev); - int ret; - - ret = check_reserved(desc, "set_dir"); - if (ret) - return ret; - -- if (flags & GPIOD_IS_OUT) { -- int value = flags & GPIOD_IS_OUT_ACTIVE ? 1 : 0; -+ return _dm_gpio_set_dir_flags(desc, desc->flags); -+} - -- if (flags & GPIOD_ACTIVE_LOW) -- value = !value; -- ret = ops->direction_output(dev, desc->offset, value); -- } else if (flags & GPIOD_IS_IN) { -- ret = ops->direction_input(dev, desc->offset); -- } -+int dm_gpio_get_dir_flags(struct gpio_desc *desc, ulong *flags) -+{ -+ struct udevice *dev = desc->dev; -+ int ret, value; -+ struct dm_gpio_ops *ops = gpio_get_ops(dev); -+ ulong dir_flags; -+ -+ ret = check_reserved(desc, "get_dir_flags"); - if (ret) - return ret; -- /* -- * Update desc->flags here, so that GPIO_ACTIVE_LOW is honoured in -- * futures -- */ -- desc->flags = flags; - -- return 0; --} -+ /* GPIOD_ are directly provided by driver except GPIOD_ACTIVE_LOW */ -+ if (ops->get_dir_flags) { -+ ret = ops->get_dir_flags(dev, desc->offset, &dir_flags); -+ if (ret) -+ return ret; - --int dm_gpio_set_dir(struct gpio_desc *desc) --{ -- return dm_gpio_set_dir_flags(desc, desc->flags); -+ /* GPIOD_ACTIVE_LOW is saved in desc->flags */ -+ value = dir_flags & GPIOD_IS_OUT_ACTIVE ? 1 : 0; -+ if (desc->flags & GPIOD_ACTIVE_LOW) -+ value = !value; -+ dir_flags &= ~(GPIOD_ACTIVE_LOW | GPIOD_IS_OUT_ACTIVE); -+ dir_flags |= (desc->flags & GPIOD_ACTIVE_LOW); -+ if (value) -+ dir_flags |= GPIOD_IS_OUT_ACTIVE; -+ } else { -+ dir_flags = desc->flags; -+ /* only GPIOD_IS_OUT_ACTIVE is provided by uclass */ -+ dir_flags &= ~GPIOD_IS_OUT_ACTIVE; -+ if ((desc->flags & GPIOD_IS_OUT) && _gpio_get_value(desc)) -+ dir_flags |= GPIOD_IS_OUT_ACTIVE; -+ } -+ *flags = dir_flags; -+ -+ return 0; - } - - /** -@@ -804,9 +899,7 @@ static int gpio_request_tail(int ret, const char *nodename, - struct gpio_desc *desc, int flags, - bool add_index, struct udevice *gpio_dev) - { -- desc->dev = gpio_dev; -- desc->offset = 0; -- desc->flags = 0; -+ gpio_desc_init(desc, gpio_dev, 0); - if (ret) - goto err; - -@@ -830,7 +923,7 @@ static int gpio_request_tail(int ret, const char *nodename, - debug("%s: dm_gpio_requestf failed\n", __func__); - goto err; - } -- ret = dm_gpio_set_dir_flags(desc, flags | desc->flags); -+ ret = dm_gpio_set_dir_flags(desc, flags); - if (ret) { - debug("%s: dm_gpio_set_dir failed\n", __func__); - goto err; -@@ -1053,14 +1146,14 @@ static int gpio_post_bind(struct udevice *dev) - ops->get_value += gd->reloc_off; - if (ops->set_value) - ops->set_value += gd->reloc_off; -- if (ops->get_open_drain) -- ops->get_open_drain += gd->reloc_off; -- if (ops->set_open_drain) -- ops->set_open_drain += gd->reloc_off; - if (ops->get_function) - ops->get_function += gd->reloc_off; - if (ops->xlate) - ops->xlate += gd->reloc_off; -+ if (ops->set_dir_flags) -+ ops->set_dir_flags += gd->reloc_off; -+ if (ops->get_dir_flags) -+ ops->get_dir_flags += gd->reloc_off; - - reloc_done++; - } -diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c -index c273c2c..c23f5b5 100644 ---- a/drivers/gpio/mpc8xxx_gpio.c -+++ b/drivers/gpio/mpc8xxx_gpio.c -@@ -144,26 +144,6 @@ static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio) - return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio)); - } - --static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio) --{ -- struct mpc8xxx_gpio_data *data = dev_get_priv(dev); -- -- return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio)); --} -- --static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio, -- int value) --{ -- struct mpc8xxx_gpio_data *data = dev_get_priv(dev); -- -- if (value) -- mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio)); -- else -- mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio)); -- -- return 0; --} -- - static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) - { - struct mpc8xxx_gpio_data *data = dev_get_priv(dev); -@@ -240,8 +220,6 @@ static const struct dm_gpio_ops gpio_mpc8xxx_ops = { - .direction_output = mpc8xxx_gpio_direction_output, - .get_value = mpc8xxx_gpio_get_value, - .set_value = mpc8xxx_gpio_set_value, -- .get_open_drain = mpc8xxx_gpio_get_open_drain, -- .set_open_drain = mpc8xxx_gpio_set_open_drain, - .get_function = mpc8xxx_gpio_get_function, - }; - -diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c -index 2ef5c67..bf6287f 100644 ---- a/drivers/gpio/sandbox.c -+++ b/drivers/gpio/sandbox.c -@@ -8,43 +8,43 @@ - #include - #include - #include -+#include - #include -+#include - #include -+#include - --/* Flags for each GPIO */ --#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */ --#define GPIOF_HIGH (1 << 1) /* Currently set high */ --#define GPIOF_ODR (1 << 2) /* Currently set to open drain mode */ - - struct gpio_state { - const char *label; /* label given by requester */ -- u8 flags; /* flags (GPIOF_...) */ -+ ulong dir_flags; /* dir_flags (GPIOD_...) */ - }; - --/* Access routines for GPIO state */ --static u8 *get_gpio_flags(struct udevice *dev, unsigned offset) -+/* Access routines for GPIO dir flags */ -+static ulong *get_gpio_dir_flags(struct udevice *dev, unsigned int offset) - { - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct gpio_state *state = dev_get_priv(dev); - - if (offset >= uc_priv->gpio_count) { -- static u8 invalid_flags; -+ static ulong invalid_dir_flags; - printf("sandbox_gpio: error: invalid gpio %u\n", offset); -- return &invalid_flags; -+ return &invalid_dir_flags; - } - -- return &state[offset].flags; -+ return &state[offset].dir_flags; -+ - } - --static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag) -+static int get_gpio_flag(struct udevice *dev, unsigned int offset, ulong flag) - { -- return (*get_gpio_flags(dev, offset) & flag) != 0; -+ return (*get_gpio_dir_flags(dev, offset) & flag) != 0; - } - --static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, -+static int set_gpio_flag(struct udevice *dev, unsigned int offset, ulong flag, - int value) - { -- u8 *gpio = get_gpio_flags(dev, offset); -+ ulong *gpio = get_gpio_dir_flags(dev, offset); - - if (value) - *gpio |= flag; -@@ -60,34 +60,40 @@ static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, - - int sandbox_gpio_get_value(struct udevice *dev, unsigned offset) - { -- if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) -+ if (get_gpio_flag(dev, offset, GPIOD_IS_OUT)) - debug("sandbox_gpio: get_value on output gpio %u\n", offset); -- return get_gpio_flag(dev, offset, GPIOF_HIGH); -+ return get_gpio_flag(dev, offset, GPIOD_IS_OUT_ACTIVE); - } - - int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value) - { -- return set_gpio_flag(dev, offset, GPIOF_HIGH, value); -+ return set_gpio_flag(dev, offset, GPIOD_IS_OUT_ACTIVE, value); - } - --int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset) -+int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset) - { -- return get_gpio_flag(dev, offset, GPIOF_ODR); -+ return get_gpio_flag(dev, offset, GPIOD_IS_OUT); - } - --int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value) -+int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output) - { -- return set_gpio_flag(dev, offset, GPIOF_ODR, value); -+ set_gpio_flag(dev, offset, GPIOD_IS_OUT, output); -+ set_gpio_flag(dev, offset, GPIOD_IS_IN, !(output)); -+ -+ return 0; - } - --int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset) -+ulong sandbox_gpio_get_dir_flags(struct udevice *dev, unsigned int offset) - { -- return get_gpio_flag(dev, offset, GPIOF_OUTPUT); -+ return *get_gpio_dir_flags(dev, offset); - } - --int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output) -+int sandbox_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong flags) - { -- return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output); -+ *get_gpio_dir_flags(dev, offset) = flags; -+ -+ return 0; - } - - /* -@@ -134,33 +140,14 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value) - return sandbox_gpio_set_value(dev, offset, value); - } - --/* read GPIO ODR value of port 'offset' */ --static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset) --{ -- debug("%s: offset:%u\n", __func__, offset); -- -- return sandbox_gpio_get_open_drain(dev, offset); --} -- --/* write GPIO ODR value to port 'offset' */ --static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value) --{ -- debug("%s: offset:%u, value = %d\n", __func__, offset, value); -- -- if (!sandbox_gpio_get_direction(dev, offset)) { -- printf("sandbox_gpio: error: set_open_drain on input gpio %u\n", -- offset); -- return -1; -- } -- -- return sandbox_gpio_set_open_drain(dev, offset, value); --} -- - static int sb_gpio_get_function(struct udevice *dev, unsigned offset) - { -- if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) -+ if (get_gpio_flag(dev, offset, GPIOD_IS_OUT)) - return GPIOF_OUTPUT; -- return GPIOF_INPUT; -+ if (get_gpio_flag(dev, offset, GPIOD_IS_IN)) -+ return GPIOF_INPUT; -+ -+ return GPIOF_INPUT; /*GPIO is not configurated */ - } - - static int sb_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, -@@ -169,27 +156,54 @@ static int sb_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, - desc->offset = args->args[0]; - if (args->args_count < 2) - return 0; -- if (args->args[1] & GPIO_ACTIVE_LOW) -- desc->flags |= GPIOD_ACTIVE_LOW; -- if (args->args[1] & 2) -+ /* treat generic binding with gpio uclass */ -+ gpio_xlate_offs_flags(dev, desc, args); -+ -+ /* sandbox test specific, not defined in gpio.h */ -+ if (args->args[1] & GPIO_IN) - desc->flags |= GPIOD_IS_IN; -- if (args->args[1] & 4) -+ -+ if (args->args[1] & GPIO_OUT) - desc->flags |= GPIOD_IS_OUT; -- if (args->args[1] & 8) -+ -+ if (args->args[1] & GPIO_OUT_ACTIVE) - desc->flags |= GPIOD_IS_OUT_ACTIVE; - - return 0; - } - -+static int sb_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong flags) -+{ -+ ulong *dir_flags; -+ -+ debug("%s: offset:%u, dir_flags = %lx\n", __func__, offset, flags); -+ -+ dir_flags = get_gpio_dir_flags(dev, offset); -+ -+ *dir_flags = flags; -+ -+ return 0; -+} -+ -+static int sb_gpio_get_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong *flags) -+{ -+ debug("%s: offset:%u\n", __func__, offset); -+ *flags = *get_gpio_dir_flags(dev, offset); -+ -+ return 0; -+} -+ - static const struct dm_gpio_ops gpio_sandbox_ops = { - .direction_input = sb_gpio_direction_input, - .direction_output = sb_gpio_direction_output, - .get_value = sb_gpio_get_value, - .set_value = sb_gpio_set_value, -- .get_open_drain = sb_gpio_get_open_drain, -- .set_open_drain = sb_gpio_set_open_drain, - .get_function = sb_gpio_get_function, - .xlate = sb_gpio_xlate, -+ .set_dir_flags = sb_gpio_set_dir_flags, -+ .get_dir_flags = sb_gpio_get_dir_flags, - }; - - static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev) -@@ -237,3 +251,198 @@ U_BOOT_DRIVER(gpio_sandbox) = { - .remove = gpio_sandbox_remove, - .ops = &gpio_sandbox_ops, - }; -+ -+/* pincontrol: used only to check GPIO pin configuration (pinmux command) */ -+ -+struct sb_pinctrl_priv { -+ int pinctrl_ngpios; -+ struct list_head gpio_dev; -+}; -+ -+struct sb_gpio_bank { -+ struct udevice *gpio_dev; -+ struct list_head list; -+}; -+ -+static int sb_populate_gpio_dev_list(struct udevice *dev) -+{ -+ struct sb_pinctrl_priv *priv = dev_get_priv(dev); -+ struct udevice *gpio_dev; -+ struct udevice *child; -+ struct sb_gpio_bank *gpio_bank; -+ int ret; -+ -+ /* -+ * parse pin-controller sub-nodes (ie gpio bank nodes) and fill -+ * a list with all gpio device reference which belongs to the -+ * current pin-controller. This list is used to find pin_name and -+ * pin muxing -+ */ -+ list_for_each_entry(child, &dev->child_head, sibling_node) { -+ ret = uclass_get_device_by_name(UCLASS_GPIO, child->name, -+ &gpio_dev); -+ if (ret < 0) -+ continue; -+ -+ gpio_bank = malloc(sizeof(*gpio_bank)); -+ if (!gpio_bank) { -+ dev_err(dev, "Not enough memory\n"); -+ return -ENOMEM; -+ } -+ -+ gpio_bank->gpio_dev = gpio_dev; -+ list_add_tail(&gpio_bank->list, &priv->gpio_dev); -+ } -+ -+ return 0; -+} -+ -+static int sb_pinctrl_get_pins_count(struct udevice *dev) -+{ -+ struct sb_pinctrl_priv *priv = dev_get_priv(dev); -+ struct gpio_dev_priv *uc_priv; -+ struct sb_gpio_bank *gpio_bank; -+ -+ /* -+ * if get_pins_count has already been executed once on this -+ * pin-controller, no need to run it again -+ */ -+ if (priv->pinctrl_ngpios) -+ return priv->pinctrl_ngpios; -+ -+ if (list_empty(&priv->gpio_dev)) -+ sb_populate_gpio_dev_list(dev); -+ /* -+ * walk through all banks to retrieve the pin-controller -+ * pins number -+ */ -+ list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { -+ uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); -+ -+ priv->pinctrl_ngpios += uc_priv->gpio_count; -+ } -+ -+ return priv->pinctrl_ngpios; -+} -+ -+static struct udevice *sb_pinctrl_get_gpio_dev(struct udevice *dev, -+ unsigned int selector, -+ unsigned int *idx) -+{ -+ struct sb_pinctrl_priv *priv = dev_get_priv(dev); -+ struct sb_gpio_bank *gpio_bank; -+ struct gpio_dev_priv *uc_priv; -+ int pin_count = 0; -+ -+ if (list_empty(&priv->gpio_dev)) -+ sb_populate_gpio_dev_list(dev); -+ -+ /* look up for the bank which owns the requested pin */ -+ list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { -+ uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); -+ -+ if (selector < (pin_count + uc_priv->gpio_count)) { -+ /* -+ * we found the bank, convert pin selector to -+ * gpio bank index -+ */ -+ *idx = selector - pin_count; -+ -+ return gpio_bank->gpio_dev; -+ } -+ pin_count += uc_priv->gpio_count; -+ } -+ -+ return NULL; -+} -+ -+static const char *sb_pinctrl_get_pin_name(struct udevice *dev, -+ unsigned int selector) -+{ -+ struct gpio_dev_priv *uc_priv; -+ struct udevice *gpio_dev; -+ unsigned int gpio_idx; -+ static char pin_name[PINNAME_SIZE]; -+ -+ /* look up for the bank which owns the requested pin */ -+ gpio_dev = sb_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); -+ if (!gpio_dev) { -+ snprintf(pin_name, PINNAME_SIZE, "Error"); -+ } else { -+ uc_priv = dev_get_uclass_priv(gpio_dev); -+ -+ snprintf(pin_name, PINNAME_SIZE, "%s%d", -+ uc_priv->bank_name, -+ gpio_idx); -+ } -+ -+ return pin_name; -+} -+ -+static char *get_dir_flags_string(ulong flags) -+{ -+ if (flags & GPIOD_OPEN_DRAIN) -+ return "drive-open-drain"; -+ if (flags & GPIOD_OPEN_SOURCE) -+ return "drive-open-source"; -+ if (flags & GPIOD_PULL_UP) -+ return "bias-pull-up"; -+ if (flags & GPIOD_PULL_DOWN) -+ return "bias-pull-down"; -+ return "."; -+} -+ -+static int sb_pinctrl_get_pin_muxing(struct udevice *dev, -+ unsigned int selector, -+ char *buf, int size) -+{ -+ struct udevice *gpio_dev; -+ unsigned int gpio_idx; -+ ulong dir_flags; -+ int function; -+ -+ /* look up for the bank which owns the requested pin */ -+ gpio_dev = sb_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); -+ if (!gpio_dev) { -+ snprintf(buf, size, "Error"); -+ } else { -+ function = sb_gpio_get_function(gpio_dev, gpio_idx); -+ dir_flags = *get_gpio_dir_flags(gpio_dev, gpio_idx); -+ -+ snprintf(buf, size, "gpio %s %s", -+ function == GPIOF_OUTPUT ? "output" : "input", -+ get_dir_flags_string(dir_flags)); -+ } -+ -+ return 0; -+} -+ -+static int sandbox_pinctrl_probe(struct udevice *dev) -+{ -+ struct sb_pinctrl_priv *priv = dev_get_priv(dev); -+ -+ INIT_LIST_HEAD(&priv->gpio_dev); -+ -+ return 0; -+} -+ -+static struct pinctrl_ops sandbox_pinctrl_gpio_ops = { -+ .get_pin_name = sb_pinctrl_get_pin_name, -+ .get_pins_count = sb_pinctrl_get_pins_count, -+ .get_pin_muxing = sb_pinctrl_get_pin_muxing, -+}; -+ -+static const struct udevice_id sandbox_pinctrl_gpio_match[] = { -+ { .compatible = "sandbox,pinctrl-gpio" }, -+ { /* sentinel */ } -+}; -+ -+U_BOOT_DRIVER(sandbox_pinctrl_gpio) = { -+ .name = "sandbox_pinctrl_gpio", -+ .id = UCLASS_PINCTRL, -+ .of_match = sandbox_pinctrl_gpio_match, -+ .ops = &sandbox_pinctrl_gpio_ops, -+ .bind = dm_scan_fdt_dev, -+ .probe = sandbox_pinctrl_probe, -+ .priv_auto_alloc_size = sizeof(struct sb_pinctrl_priv), -+}; -diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c -index 302a434..a7c89a4 100644 ---- a/drivers/gpio/stm32_gpio.c -+++ b/drivers/gpio/stm32_gpio.c -@@ -19,7 +19,62 @@ - #define MODE_BITS_MASK 3 - #define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16)) - --#ifndef CONFIG_SPL_BUILD -+#define PUPD_BITS(gpio_pin) (gpio_pin * 2) -+#define PUPD_MASK 3 -+ -+#define OTYPE_BITS(gpio_pin) (gpio_pin) -+#define OTYPE_MSK 1 -+ -+static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs, -+ int idx, -+ int mode) -+{ -+ int bits_index; -+ int mask; -+ -+ bits_index = MODE_BITS(idx); -+ mask = MODE_BITS_MASK << bits_index; -+ -+ clrsetbits_le32(®s->moder, mask, mode << bits_index); -+} -+ -+static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx) -+{ -+ return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK; -+} -+ -+static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs, -+ int idx, -+ enum stm32_gpio_otype otype) -+{ -+ int bits; -+ -+ bits = OTYPE_BITS(idx); -+ clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits); -+} -+ -+static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs, -+ int idx) -+{ -+ return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK; -+} -+ -+static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs, -+ int idx, -+ enum stm32_gpio_pupd pupd) -+{ -+ int bits; -+ -+ bits = PUPD_BITS(idx); -+ clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits); -+} -+ -+static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs, -+ int idx) -+{ -+ return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK; -+} -+ - /* - * convert gpio offset to gpio index taking into account gpio holes - * into gpio bank -@@ -45,18 +100,13 @@ static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) - { - struct stm32_gpio_priv *priv = dev_get_priv(dev); - struct stm32_gpio_regs *regs = priv->regs; -- int bits_index; -- int mask; - int idx; - - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; - -- bits_index = MODE_BITS(idx); -- mask = MODE_BITS_MASK << bits_index; -- -- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index); -+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); - - return 0; - } -@@ -66,18 +116,13 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, - { - struct stm32_gpio_priv *priv = dev_get_priv(dev); - struct stm32_gpio_regs *regs = priv->regs; -- int bits_index; -- int mask; - int idx; - - idx = stm32_offset_to_index(dev, offset); - if (idx < 0) - return idx; - -- bits_index = MODE_BITS(idx); -- mask = MODE_BITS_MASK << bits_index; -- -- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index); -+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT); - - writel(BSRR_BIT(idx, value), ®s->bsrr); - -@@ -139,14 +184,88 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) - return GPIOF_FUNC; - } - -+static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong flags) -+{ -+ struct stm32_gpio_priv *priv = dev_get_priv(dev); -+ struct stm32_gpio_regs *regs = priv->regs; -+ int idx; -+ -+ idx = stm32_offset_to_index(dev, offset); -+ if (idx < 0) -+ return idx; -+ -+ if (flags & GPIOD_IS_OUT) { -+ int value = GPIOD_FLAGS_OUTPUT(flags); -+ -+ if (flags & GPIOD_OPEN_DRAIN) -+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD); -+ else -+ stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP); -+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT); -+ writel(BSRR_BIT(idx, value), ®s->bsrr); -+ -+ } else if (flags & GPIOD_IS_IN) { -+ stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); -+ if (flags & GPIOD_PULL_UP) -+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); -+ else if (flags & GPIOD_PULL_DOWN) -+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); -+ } -+ -+ return 0; -+} -+ -+static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong *flags) -+{ -+ struct stm32_gpio_priv *priv = dev_get_priv(dev); -+ struct stm32_gpio_regs *regs = priv->regs; -+ int idx; -+ ulong dir_flags = 0; -+ -+ idx = stm32_offset_to_index(dev, offset); -+ if (idx < 0) -+ return idx; -+ -+ switch (stm32_gpio_get_moder(regs, idx)) { -+ case STM32_GPIO_MODE_OUT: -+ dir_flags |= GPIOD_IS_OUT; -+ if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD) -+ dir_flags |= GPIOD_OPEN_DRAIN; -+ if (readl(®s->idr) & BIT(idx)) -+ dir_flags |= GPIOD_IS_OUT_ACTIVE; -+ break; -+ case STM32_GPIO_MODE_IN: -+ dir_flags |= GPIOD_IS_IN; -+ switch (stm32_gpio_get_pupd(regs, idx)) { -+ case STM32_GPIO_PUPD_UP: -+ dir_flags |= GPIOD_PULL_UP; -+ break; -+ case STM32_GPIO_PUPD_DOWN: -+ dir_flags |= GPIOD_PULL_DOWN; -+ break; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ *flags = dir_flags; -+ -+ return 0; -+} -+ - static const struct dm_gpio_ops gpio_stm32_ops = { - .direction_input = stm32_gpio_direction_input, - .direction_output = stm32_gpio_direction_output, - .get_value = stm32_gpio_get_value, - .set_value = stm32_gpio_set_value, - .get_function = stm32_gpio_get_function, -+ .set_dir_flags = stm32_gpio_set_dir_flags, -+ .get_dir_flags = stm32_gpio_get_dir_flags, - }; --#endif - - static int gpio_stm32_probe(struct udevice *dev) - { -@@ -161,7 +280,6 @@ static int gpio_stm32_probe(struct udevice *dev) - - priv->regs = (struct stm32_gpio_regs *)addr; - --#ifndef CONFIG_SPL_BUILD - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct ofnode_phandle_args args; - const char *name; -@@ -194,7 +312,7 @@ static int gpio_stm32_probe(struct udevice *dev) - dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n", - (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count, - priv->gpio_range); --#endif -+ - ret = clk_get_by_index(dev, 0, &clk); - if (ret < 0) - return ret; -@@ -214,9 +332,7 @@ U_BOOT_DRIVER(gpio_stm32) = { - .name = "gpio_stm32", - .id = UCLASS_GPIO, - .probe = gpio_stm32_probe, --#ifndef CONFIG_SPL_BUILD - .ops = &gpio_stm32_ops, --#endif - .flags = DM_UC_FLAG_SEQ_ALIAS, - .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv), - }; -diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c -index 2b18735..7321f80 100644 ---- a/drivers/i2c/stm32f7_i2c.c -+++ b/drivers/i2c/stm32f7_i2c.c -@@ -10,6 +10,7 @@ - #include - - #include -+#include - #include - - /* STM32 I2C registers */ -@@ -115,17 +116,6 @@ struct stm32_i2c_regs { - - #define STM32_NSEC_PER_SEC 1000000000L - --#define STANDARD_RATE 100000 --#define FAST_RATE 400000 --#define FAST_PLUS_RATE 1000000 -- --enum stm32_i2c_speed { -- STM32_I2C_SPEED_STANDARD, /* 100 kHz */ -- STM32_I2C_SPEED_FAST, /* 400 kHz */ -- STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ -- STM32_I2C_SPEED_END, --}; -- - /** - * struct stm32_i2c_spec - private i2c specification timing - * @rate: I2C bus speed (Hz) -@@ -155,7 +145,6 @@ struct stm32_i2c_spec { - - /** - * struct stm32_i2c_setup - private I2C timing setup parameters -- * @speed: I2C speed mode (standard, Fast Plus) - * @speed_freq: I2C speed frequency (Hz) - * @clock_src: I2C clock source frequency (Hz) - * @rise_time: Rise time (ns) -@@ -164,7 +153,6 @@ struct stm32_i2c_spec { - * @analog_filter: Analog filter delay (On/Off) - */ - struct stm32_i2c_setup { -- enum stm32_i2c_speed speed; - u32 speed_freq; - u32 clock_src; - u32 rise_time; -@@ -194,12 +182,13 @@ struct stm32_i2c_priv { - struct stm32_i2c_regs *regs; - struct clk clk; - struct stm32_i2c_setup *setup; -- int speed; -+ u32 speed; - }; - - static const struct stm32_i2c_spec i2c_specs[] = { -- [STM32_I2C_SPEED_STANDARD] = { -- .rate = STANDARD_RATE, -+ /* Standard speed - 100 KHz */ -+ [IC_SPEED_MODE_STANDARD] = { -+ .rate = I2C_SPEED_STANDARD_RATE, - .rate_min = 8000, - .rate_max = 120000, - .fall_max = 300, -@@ -210,8 +199,9 @@ static const struct stm32_i2c_spec i2c_specs[] = { - .l_min = 4700, - .h_min = 4000, - }, -- [STM32_I2C_SPEED_FAST] = { -- .rate = FAST_RATE, -+ /* Fast speed - 400 KHz */ -+ [IC_SPEED_MODE_FAST] = { -+ .rate = I2C_SPEED_FAST_RATE, - .rate_min = 320000, - .rate_max = 480000, - .fall_max = 300, -@@ -222,8 +212,9 @@ static const struct stm32_i2c_spec i2c_specs[] = { - .l_min = 1300, - .h_min = 600, - }, -- [STM32_I2C_SPEED_FAST_PLUS] = { -- .rate = FAST_PLUS_RATE, -+ /* Fast Plus Speed - 1 MHz */ -+ [IC_SPEED_MODE_FAST_PLUS] = { -+ .rate = I2C_SPEED_FAST_PLUS_RATE, - .rate_min = 800000, - .rate_max = 1200000, - .fall_max = 100, -@@ -484,6 +475,7 @@ static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, - } - - static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, -+ const struct stm32_i2c_spec *specs, - struct list_head *solutions) - { - struct stm32_i2c_timings *v; -@@ -500,13 +492,13 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, - af_delay_max = setup->analog_filter ? - STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; - -- sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time - -+ sdadel_min = specs->hddat_min + setup->fall_time - - af_delay_min - (setup->dnf + 3) * i2cclk; - -- sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - -+ sdadel_max = specs->vddat_max - setup->rise_time - - af_delay_max - (setup->dnf + 4) * i2cclk; - -- scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; -+ scldel_min = setup->rise_time + specs->sudat_min; - - if (sdadel_min < 0) - sdadel_min = 0; -@@ -558,6 +550,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, - } - - static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, -+ const struct stm32_i2c_spec *specs, - struct list_head *solutions, - struct stm32_i2c_timings *s) - { -@@ -580,8 +573,8 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, - dnf_delay = setup->dnf * i2cclk; - - tsync = af_delay_min + dnf_delay + (2 * i2cclk); -- clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; -- clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; -+ clk_max = STM32_NSEC_PER_SEC / specs->rate_min; -+ clk_min = STM32_NSEC_PER_SEC / specs->rate_max; - - /* - * Among Prescaler possibilities discovered above figures out SCL Low -@@ -599,7 +592,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, - for (l = 0; l < STM32_SCLL_MAX; l++) { - u32 tscl_l = (l + 1) * prescaler + tsync; - -- if ((tscl_l < i2c_specs[setup->speed].l_min) || -+ if (tscl_l < specs->l_min || - (i2cclk >= - ((tscl_l - af_delay_min - dnf_delay) / 4))) { - continue; -@@ -611,7 +604,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, - setup->rise_time + setup->fall_time; - - if ((tscl >= clk_min) && (tscl <= clk_max) && -- (tscl_h >= i2c_specs[setup->speed].h_min) && -+ (tscl_h >= specs->h_min) && - (i2cclk < tscl_h)) { - u32 clk_error; - -@@ -640,26 +633,40 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, - return ret; - } - -+static const struct stm32_i2c_spec *get_specs(u32 rate) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(i2c_specs); i++) -+ if (rate <= i2c_specs[i].rate) -+ return &i2c_specs[i]; -+ -+ /* NOT REACHED */ -+ return ERR_PTR(-EINVAL); -+} -+ - static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, - struct stm32_i2c_setup *setup, - struct stm32_i2c_timings *output) - { -+ const struct stm32_i2c_spec *specs; - struct stm32_i2c_timings *v, *_v; - struct list_head solutions; - int ret; - -- if (setup->speed >= STM32_I2C_SPEED_END) { -- pr_err("%s: speed out of bound {%d/%d}\n", __func__, -- setup->speed, STM32_I2C_SPEED_END - 1); -+ specs = get_specs(setup->speed_freq); -+ if (specs == ERR_PTR(-EINVAL)) { -+ pr_err("%s: speed out of bound {%d}\n", __func__, -+ setup->speed_freq); - return -EINVAL; - } - -- if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || -- (setup->fall_time > i2c_specs[setup->speed].fall_max)) { -+ if (setup->rise_time > specs->rise_max || -+ setup->fall_time > specs->fall_max) { - pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", - __func__, -- setup->rise_time, i2c_specs[setup->speed].rise_max, -- setup->fall_time, i2c_specs[setup->speed].fall_max); -+ setup->rise_time, specs->rise_max, -+ setup->fall_time, specs->fall_max); - return -EINVAL; - } - -@@ -669,18 +676,12 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, - return -EINVAL; - } - -- if (setup->speed_freq > i2c_specs[setup->speed].rate) { -- pr_err("%s: Freq {%d/%d}\n", __func__, -- setup->speed_freq, i2c_specs[setup->speed].rate); -- return -EINVAL; -- } -- - INIT_LIST_HEAD(&solutions); -- ret = stm32_i2c_compute_solutions(setup, &solutions); -+ ret = stm32_i2c_compute_solutions(setup, specs, &solutions); - if (ret) - goto exit; - -- ret = stm32_i2c_choose_solution(setup, &solutions, output); -+ ret = stm32_i2c_choose_solution(setup, specs, &solutions, output); - if (ret) - goto exit; - -@@ -699,14 +700,24 @@ exit: - return ret; - } - -+static u32 get_lower_rate(u32 rate) -+{ -+ int i; -+ -+ for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--) -+ if (rate > i2c_specs[i].rate) -+ return i2c_specs[i].rate; -+ -+ return i2c_specs[0].rate; -+} -+ - static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, - struct stm32_i2c_timings *timing) - { - struct stm32_i2c_setup *setup = i2c_priv->setup; - int ret = 0; - -- setup->speed = i2c_priv->speed; -- setup->speed_freq = i2c_specs[setup->speed].rate; -+ setup->speed_freq = i2c_priv->speed; - setup->clock_src = clk_get_rate(&i2c_priv->clk); - - if (!setup->clock_src) { -@@ -719,13 +730,11 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, - if (ret) { - debug("%s: failed to compute I2C timings.\n", - __func__); -- if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) { -- i2c_priv->speed--; -- setup->speed = i2c_priv->speed; -+ if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) { - setup->speed_freq = -- i2c_specs[setup->speed].rate; -+ get_lower_rate(setup->speed_freq); - debug("%s: downgrade I2C Speed Freq to (%i)\n", -- __func__, i2c_specs[setup->speed].rate); -+ __func__, setup->speed_freq); - } else { - break; - } -@@ -737,13 +746,15 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, - return ret; - } - -- debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__, -- setup->speed, setup->speed_freq, setup->clock_src); -+ debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__, -+ setup->speed_freq, setup->clock_src); - debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, - setup->rise_time, setup->fall_time); - debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, - setup->analog_filter ? "On" : "Off", setup->dnf); - -+ i2c_priv->speed = setup->speed_freq; -+ - return 0; - } - -@@ -783,21 +794,13 @@ static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) - { - struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); - -- switch (speed) { -- case STANDARD_RATE: -- i2c_priv->speed = STM32_I2C_SPEED_STANDARD; -- break; -- case FAST_RATE: -- i2c_priv->speed = STM32_I2C_SPEED_FAST; -- break; -- case FAST_PLUS_RATE: -- i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS; -- break; -- default: -+ if (speed > I2C_SPEED_FAST_PLUS_RATE) { - debug("%s: Speed %d not supported\n", __func__, speed); - return -EINVAL; - } - -+ i2c_priv->speed = speed; -+ - return stm32_i2c_hw_config(i2c_priv); - } - -@@ -867,6 +870,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { - - static const struct udevice_id stm32_i2c_of_match[] = { - { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, -+ { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32f7_setup }, - {} - }; - -diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig -index 85c2a82..dbb3d81 100644 ---- a/drivers/mailbox/Kconfig -+++ b/drivers/mailbox/Kconfig -@@ -47,4 +47,11 @@ config ZYNQMP_IPI - help - This enables support for the Xilinx ZynqMP Inter Processor Interrupt - communication controller. -+ -+config ARM_SMC_MAILBOX -+ bool "Enable Arm SMC mailbox support" -+ depends on DM_MAILBOX && ARM_SMCCC -+ help -+ Mailbox notification through an Arm SMC or HVC calls. -+ - endmenu -diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile -index d2ace8c..7a56a45 100644 ---- a/drivers/mailbox/Makefile -+++ b/drivers/mailbox/Makefile -@@ -3,6 +3,7 @@ - # Copyright (c) 2016, NVIDIA CORPORATION. - # - -+obj-$(CONFIG_ARM_SMC_MAILBOX) += arm-smc-mbox.o - obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o - obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o - obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o -diff --git a/drivers/mailbox/arm-smc-mbox.c b/drivers/mailbox/arm-smc-mbox.c -new file mode 100644 -index 0000000..37f595a ---- /dev/null -+++ b/drivers/mailbox/arm-smc-mbox.c -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019, Linaro Limited -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#define ARM_SMC_METHOD 0 -+#define ARM_HVC_METHOD 1 -+ -+typedef void (invoke_fn_t)(unsigned long); -+ -+struct smc_pdata { -+ unsigned long func_id; -+ invoke_fn_t *invoke_fn; -+}; -+ -+/* Simple wrapper functions to be able to use a function pointer */ -+static void smccc_smc(unsigned long a0) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(a0, 0, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static void smccc_hvc(unsigned long a0) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_hvc(a0, 0, 0, 0, 0, 0, 0, 0, &res); -+} -+ -+static int smc_mbox_send(struct mbox_chan *chan, const void *data) -+{ -+ struct smc_pdata *pdata = dev_get_platdata(chan->dev); -+ -+ /* -+ * This mailbox invokes secure world for a channel event. -+ * Message is already in the channel's shared memory. -+ */ -+ pdata->invoke_fn(pdata->func_id); -+ -+ return 0; -+} -+ -+static int smc_mbox_recv(struct mbox_chan *chan, void *data) -+{ -+ /* Mbox owner already got the return message from shared memory */ -+ return 0; -+} -+ -+static int smc_mbox_request(struct mbox_chan *chan) -+{ -+ return 0; -+} -+ -+static int smc_mbox_free(struct mbox_chan *chan) -+{ -+ return 0; -+} -+ -+static int smc_mbox_of_xlate(struct mbox_chan *chan, -+ struct ofnode_phandle_args *args) -+{ -+ if (args->args_count) -+ dev_warn(chan->dev, "Expect no argument to smc-mbox cells\n"); -+ -+ chan->id = 0; -+ -+ return 0; -+} -+ -+static int smc_mbox_ofdata_to_platdata(struct udevice *dev) -+{ -+ ulong compat_data = dev_get_driver_data(dev); -+ struct smc_pdata *pdata = dev_get_platdata(dev); -+ u32 func_id; -+ -+ if (dev_read_u32(dev, "arm,func-id", &func_id)) { -+ dev_err(dev, "Missing property arm,func-id\n"); -+ return -EINVAL; -+ } -+ -+ pdata->func_id = func_id; -+ -+ if (compat_data == ARM_SMC_METHOD) -+ pdata->invoke_fn = smccc_smc; -+ else -+ pdata->invoke_fn = smccc_hvc; -+ -+ return 0; -+} -+ -+static const struct udevice_id smc_mbox_ids[] = { -+ { .compatible = "arm,smc-mbox", .data = ARM_SMC_METHOD, }, -+ { .compatible = "arm,hvc-mbox", .data = ARM_HVC_METHOD, }, -+ { } -+}; -+ -+struct mbox_ops smc_mbox_ops = { -+ .of_xlate = smc_mbox_of_xlate, -+ .request = smc_mbox_request, -+ .free = smc_mbox_free, -+ .send = smc_mbox_send, -+ .recv = smc_mbox_recv, -+}; -+ -+U_BOOT_DRIVER(smc_mbox) = { -+ .name = "arm_smc_mbox", -+ .id = UCLASS_MAILBOX, -+ .of_match = smc_mbox_ids, -+ .ofdata_to_platdata = smc_mbox_ofdata_to_platdata, -+ .platdata_auto_alloc_size = sizeof(struct smc_pdata), -+ .ops = &smc_mbox_ops, -+}; -diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index 82bb093..547e144 100644 ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -439,4 +439,16 @@ config K3_AVS0 - optimized voltage from the efuse, so that it can be programmed - to the PMIC on board. - -+config SCMI_AGENT -+ bool "Enable SCMI support" -+ select OF_TRANSLATE -+ help -+ An SCMI agent communicates with a related SCMI server located -+ in another sub-system, as a companion micro controller or a -+ companion host in the CPU system. -+ -+ Communications between agent (client) and the SCMI server are -+ based on message exchange, for example through a mailbox device -+ and some piece of identified shared memory. -+ - endmenu -diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile -index 55976d6..df7b3ed 100644 ---- a/drivers/misc/Makefile -+++ b/drivers/misc/Makefile -@@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o - obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o - obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o - obj-$(CONFIG_K3_AVS0) += k3_avs.o -+obj-$(CONFIG_SCMI_AGENT) += scmi_agent.o -diff --git a/drivers/misc/scmi_agent.c b/drivers/misc/scmi_agent.c -new file mode 100644 -index 0000000..d36e460 ---- /dev/null -+++ b/drivers/misc/scmi_agent.c -@@ -0,0 +1,337 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. -+ * Copyright (C) 2019 Linaro Limited. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct error_code { -+ int scmi; -+ int errno; -+}; -+ -+static const struct error_code scmi_linux_errmap[] = { -+ { .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, }, -+ { .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, }, -+ { .scmi = SCMI_DENIED, .errno = -EACCES, }, -+ { .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, }, -+ { .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, }, -+ { .scmi = SCMI_BUSY, .errno = -EBUSY, }, -+ { .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, }, -+ { .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, }, -+ { .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, }, -+ { .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, }, -+}; -+ -+int scmi_to_linux_errno(int32_t scmi_code) -+{ -+ int n; -+ -+ if (scmi_code == 0) -+ return 0; -+ -+ for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++) -+ if (scmi_code == scmi_linux_errmap[n].scmi) -+ return scmi_linux_errmap[1].errno; -+ -+ return -EPROTO; -+} -+ -+struct method_ops { -+ int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); -+ int (*remove_agent)(struct udevice *dev); -+}; -+ -+struct scmi_agent { -+ struct method_ops *method_ops; -+ void *method_priv; -+}; -+ -+/* -+ * Shared Memory based Transport (SMT) message buffer management -+ * -+ * SMT uses 28 byte header prior message payload to handle the state of -+ * the communication channel realized by the shared memory area and -+ * to define SCMI protocol information the payload relates to. -+ */ -+struct scmi_smt_header { -+ __le32 reserved; -+ __le32 channel_status; -+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1) -+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0) -+ __le32 reserved1[2]; -+ __le32 flags; -+#define SCMI_SHMEM_FLAG_INTR_ENABLED BIT(0) -+ __le32 length; -+ __le32 msg_header; -+ u8 msg_payload[0]; -+}; -+ -+#define SMT_HEADER_TOKEN(token) (((token) << 18) & GENMASK(31, 18)) -+#define SMT_HEADER_PROTOCOL_ID(proto) (((proto) << 10) & GENMASK(17, 10)) -+#define SMT_HEADER_MESSAGE_TYPE(type) (((type) << 18) & GENMASK(9, 8)) -+#define SMT_HEADER_MESSAGE_ID(id) ((id) & GENMASK(7, 0)) -+ -+struct scmi_shm_buf { -+ u8 *buf; -+ size_t size; -+}; -+ -+static int get_shm_buffer(struct udevice *dev, struct scmi_shm_buf *shm) -+{ -+ int rc; -+ struct ofnode_phandle_args args; -+ struct resource resource; -+ fdt32_t faddr; -+ phys_addr_t paddr; -+ -+ rc = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args); -+ if (rc) -+ return rc; -+ -+ rc = ofnode_read_resource(args.node, 0, &resource); -+ if (rc) -+ return rc; -+ -+ faddr = cpu_to_fdt32(resource.start); -+ paddr = ofnode_translate_address(args.node, &faddr); -+ -+ shm->size = resource_size(&resource); -+ if (shm->size < sizeof(struct scmi_smt_header)) { -+ dev_err(dev, "Shared memory buffer too small\n"); -+ return -EINVAL; -+ } -+ -+ shm->buf = devm_ioremap(dev, paddr, shm->size); -+ if (!shm->buf) -+ return -ENOMEM; -+ -+ if (dcache_status()) -+ mmu_set_region_dcache_behaviour((uintptr_t)shm->buf, -+ shm->size, DCACHE_OFF); -+ -+ return 0; -+} -+ -+/* -+ * Mailbox support -+ */ -+struct scmi_mbox_channel { -+ struct scmi_shm_buf shm_buf; -+ struct mbox_chan mbox; -+ ulong timeout_us; -+}; -+ -+static int mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) -+{ -+ struct scmi_agent *agent = dev_get_priv(dev); -+ struct scmi_mbox_channel *chan = agent->method_priv; -+ struct scmi_smt_header *hdr = (void *)chan->shm_buf.buf; -+ int rc; -+ -+ /* Basic check-up */ -+ if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { -+ dev_dbg(dev, "Channel busy\n"); -+ return -EBUSY; -+ } -+ -+ if ((!msg->in_msg && msg->in_msg_sz) || -+ (!msg->out_msg && msg->out_msg_sz)) -+ return -EINVAL; -+ -+ if (chan->shm_buf.size < (sizeof(*hdr) + msg->in_msg_sz) || -+ chan->shm_buf.size < (sizeof(*hdr) + msg->out_msg_sz)) { -+ dev_dbg(dev, "Buffer too small\n"); -+ return -ETOOSMALL; -+ } -+ -+ /* Load message in shared memory */ -+ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; -+ hdr->length = msg->in_msg_sz + sizeof(hdr->msg_header); -+ hdr->msg_header = SMT_HEADER_TOKEN(0) | -+ SMT_HEADER_MESSAGE_TYPE(0) | -+ SMT_HEADER_PROTOCOL_ID(msg->protocol_id) | -+ SMT_HEADER_MESSAGE_ID(msg->message_id); -+ -+ memcpy(hdr->msg_payload, msg->in_msg, msg->in_msg_sz); -+ -+ /* Give shm addr to mbox in case it is meaningful */ -+ rc = mbox_send(&chan->mbox, hdr); -+ if (rc) { -+ dev_err(dev, "Message send failed: %d\n", rc); -+ goto out; -+ } -+ -+ /* Receive the response */ -+ rc = mbox_recv(&chan->mbox, hdr, chan->timeout_us); -+ if (rc) { -+ dev_err(dev, "Response failed: %d, abort\n", rc); -+ goto out; -+ } -+ -+ /* Check the statuses */ -+ if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { -+ dev_err(dev, "Channel unexpectedly busy, reset channel\n"); -+ rc = -ECOMM; -+ goto out; -+ } -+ -+ if (hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR) { -+ dev_err(dev, "Channel error reported, reset channel\n"); -+ rc = -ECOMM; -+ goto out; -+ } -+ -+ if (hdr->length > msg->out_msg_sz + sizeof(hdr->msg_header)) { -+ dev_err(dev, "Buffer to small\n"); -+ rc = -ETOOSMALL; -+ goto out; -+ } -+ -+ /* Get the data */ -+ msg->out_msg_sz = hdr->length - sizeof(hdr->msg_header); -+ memcpy(msg->out_msg, hdr->msg_payload, msg->out_msg_sz); -+ -+out: -+ /* Free channel for further communication */ -+ hdr->channel_status |= SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; -+ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; -+ -+ return rc; -+} -+ -+struct method_ops mbox_channel_ops = { -+ .process_msg = mbox_process_msg, -+}; -+ -+static int probe_smc_mailbox_channel(struct udevice *dev) -+{ -+ struct scmi_agent *agent = dev_get_priv(dev); -+ struct scmi_mbox_channel *chan; -+ int rc; -+ -+ chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL); -+ if (!chan) -+ return -ENOMEM; -+ -+ chan->timeout_us = 10000; -+ -+ rc = mbox_get_by_index(dev, 0, &chan->mbox); -+ if (rc) { -+ dev_err(dev, "Failed to find mailbox: %d\n", rc); -+ goto out; -+ } -+ -+ rc = get_shm_buffer(dev, &chan->shm_buf); -+ if (rc) -+ dev_err(dev, "Failed to get shm resources: %d\n", rc); -+ -+out: -+ if (rc) { -+ devm_kfree(dev, chan); -+ } else { -+ agent->method_ops = &mbox_channel_ops; -+ agent->method_priv = (void *)chan; -+ } -+ -+ return rc; -+} -+ -+/* -+ * Exported functions by the SCMI agent -+ */ -+ -+int scmi_agent_process_msg(struct udevice *dev, struct scmi_msg *msg) -+{ -+ struct scmi_agent *agent = dev_get_priv(dev); -+ -+ return agent->method_ops->process_msg(dev, msg); -+} -+ -+static int scmi_agent_remove(struct udevice *dev) -+{ -+ struct scmi_agent *agent = dev_get_priv(dev); -+ -+ if (agent->method_ops->remove_agent) -+ return agent->method_ops->remove_agent(dev); -+ -+ return 0; -+} -+ -+static int scmi_agent_probe(struct udevice *dev) -+{ -+ /* Only mailbox method supported for now */ -+ return probe_smc_mailbox_channel(dev); -+} -+ -+static int scmi_agent_bind(struct udevice *dev) -+{ -+ int rc = 0; -+ ofnode node; -+ struct driver *drv; -+ -+ dev_for_each_subnode(node, dev) { -+ u32 protocol_id; -+ -+ if (!ofnode_is_available(node)) -+ continue; -+ -+ if (ofnode_read_u32(node, "reg", &protocol_id)) -+ continue; -+ -+ switch (protocol_id) { -+ case SCMI_PROTOCOL_ID_CLOCK: -+ drv = DM_GET_DRIVER(scmi_clock); -+ break; -+ case SCMI_PROTOCOL_ID_RESET_DOMAIN: -+ drv = DM_GET_DRIVER(scmi_reset_domain); -+ break; -+ default: -+ dev_info(dev, "Ignore unsupported SCMI protocol %u\n", -+ protocol_id); -+ continue; -+ } -+ -+ rc = device_bind_ofnode(dev, drv, ofnode_get_name(node), -+ NULL, node, NULL); -+ if (rc) -+ break; -+ } -+ -+ if (rc) -+ device_unbind(dev); -+ -+ return rc; -+} -+ -+static const struct udevice_id scmi_agent_ids[] = { -+ { .compatible = "arm,scmi", }, -+ { } -+}; -+ -+U_BOOT_DRIVER(scmi_agent) = { -+ .name = "scmi-agent", -+ .id = UCLASS_NOP, -+ .of_match = scmi_agent_ids, -+ .priv_auto_alloc_size = sizeof(struct scmi_agent), -+ .bind = scmi_agent_bind, -+ .probe = scmi_agent_probe, -+ .remove = scmi_agent_remove, -+ .flags = DM_FLAG_OS_PREPARE, -+}; -diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c -index 0a7a2fe..9ad0504 100644 ---- a/drivers/mmc/stm32_sdmmc2.c -+++ b/drivers/mmc/stm32_sdmmc2.c -@@ -673,7 +673,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) - cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; -- cfg->name = "STM32 SDMMC2"; -+ cfg->name = "STM32 SD/MMC"; - - cfg->host_caps = 0; - if (cfg->f_max > 25000000) -diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig -index 5e7571c..348b43e 100644 ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -22,6 +22,13 @@ config MTD_NOR_FLASH - help - Enable support for parallel NOR flash. - -+config SYS_MTDPARTS_RUNTIME -+ bool "Allow MTDPARTS to be configured at runtime" -+ depends on MTD -+ help -+ This option allows to call the function board_mtdparts_default to -+ dynamically build the variables mtdids and mtdparts at runtime. -+ - config FLASH_CFI_DRIVER - bool "Enable CFI Flash driver" - help -diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c -index 4632111..fad7810 100644 ---- a/drivers/net/dwc_eth_qos.c -+++ b/drivers/net/dwc_eth_qos.c -@@ -305,6 +305,8 @@ struct eqos_priv { - struct clk clk_slave_bus; - struct mii_dev *mii; - struct phy_device *phy; -+ int phyaddr; -+ u32 max_speed; - void *descs; - struct eqos_desc *tx_descs; - struct eqos_desc *rx_descs; -@@ -693,6 +695,29 @@ static int eqos_start_resets_tegra186(struct udevice *dev) - - static int eqos_start_resets_stm32(struct udevice *dev) - { -+ struct eqos_priv *eqos = dev_get_priv(dev); -+ int ret; -+ -+ debug("%s(dev=%p):\n", __func__, dev); -+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { -+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); -+ if (ret < 0) { -+ pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", -+ ret); -+ return ret; -+ } -+ -+ udelay(2); -+ -+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); -+ if (ret < 0) { -+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", -+ ret); -+ return ret; -+ } -+ } -+ debug("%s: OK\n", __func__); -+ - return 0; - } - -@@ -708,6 +733,18 @@ static int eqos_stop_resets_tegra186(struct udevice *dev) - - static int eqos_stop_resets_stm32(struct udevice *dev) - { -+ struct eqos_priv *eqos = dev_get_priv(dev); -+ int ret; -+ -+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { -+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); -+ if (ret < 0) { -+ pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", -+ ret); -+ return ret; -+ } -+ } -+ - return 0; - } - -@@ -1045,12 +1082,21 @@ static int eqos_start(struct udevice *dev) - * don't need to reconnect/reconfigure again - */ - if (!eqos->phy) { -- eqos->phy = phy_connect(eqos->mii, -1, dev, -+ eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev, - eqos->config->interface(dev)); - if (!eqos->phy) { - pr_err("phy_connect() failed"); - goto err_stop_resets; - } -+ -+ if (eqos->max_speed) { -+ ret = phy_set_supported(eqos->phy, eqos->max_speed); -+ if (ret) { -+ pr_err("phy_set_supported() failed: %d", ret); -+ goto err_shutdown_phy; -+ } -+ } -+ - ret = phy_config(eqos->phy); - if (ret < 0) { - pr_err("phy_config() failed: %d", ret); -@@ -1603,6 +1649,9 @@ static int eqos_probe_resources_stm32(struct udevice *dev) - struct eqos_priv *eqos = dev_get_priv(dev); - int ret; - phy_interface_t interface; -+ struct ofnode_phandle_args phandle_args; -+ /* Hardcode for now */ -+ eqos->phyaddr = -1; - - debug("%s(dev=%p):\n", __func__, dev); - -@@ -1617,6 +1666,8 @@ static int eqos_probe_resources_stm32(struct udevice *dev) - if (ret) - return -EINVAL; - -+ eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); -+ - ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); - if (ret) { - pr_err("clk_get_by_name(master_bus) failed: %d", ret); -@@ -1640,6 +1691,23 @@ static int eqos_probe_resources_stm32(struct udevice *dev) - if (ret) - pr_warn("No phy clock provided %d", ret); - -+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, -+ &phandle_args); -+ if (!ret) { -+ /* search "reset-gpios" in phy node */ -+ ret = gpio_request_by_name_nodev(phandle_args.node, -+ "reset-gpios", 0, -+ &eqos->phy_reset_gpio, -+ GPIOD_IS_OUT | -+ GPIOD_IS_OUT_ACTIVE); -+ if (ret) -+ pr_warn("gpio_request_by_name(phy reset) not provided %d", -+ ret); -+ -+ eqos->phyaddr = ofnode_read_u32_default(phandle_args.node, -+ "reg", -1); -+ } -+ - debug("%s: OK\n", __func__); - return 0; - -@@ -1703,6 +1771,9 @@ static int eqos_remove_resources_stm32(struct udevice *dev) - if (clk_valid(&eqos->clk_ck)) - clk_free(&eqos->clk_ck); - -+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) -+ dm_gpio_free(dev, &eqos->phy_reset_gpio); -+ - debug("%s: OK\n", __func__); - return 0; - } -diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c -index 6f11190..c122608 100644 ---- a/drivers/phy/phy-stm32-usbphyc.c -+++ b/drivers/phy/phy-stm32-usbphyc.c -@@ -260,7 +260,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) - return 0; - - if (usbphyc_phy->vdd) { -- ret = regulator_set_enable(usbphyc_phy->vdd, false); -+ ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false); - if (ret) - return ret; - } -diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c -index e201a90..363985b 100644 ---- a/drivers/phy/phy-uclass.c -+++ b/drivers/phy/phy-uclass.c -@@ -109,56 +109,86 @@ int generic_phy_get_by_name(struct udevice *dev, const char *phy_name, - int generic_phy_init(struct phy *phy) - { - struct phy_ops const *ops; -+ int ret; - - if (!phy) - return 0; - ops = phy_dev_ops(phy->dev); - -- return ops->init ? ops->init(phy) : 0; -+ ret = ops->init ? ops->init(phy) : 0; -+ if (ret) -+ dev_err(phy->dev, "PHY: Failed to init %s: %d.\n", -+ phy->dev->name, ret); -+ -+ return ret; - } - - int generic_phy_reset(struct phy *phy) - { - struct phy_ops const *ops; -+ int ret; - - if (!phy) - return 0; - ops = phy_dev_ops(phy->dev); - -- return ops->reset ? ops->reset(phy) : 0; -+ ret = ops->reset ? ops->reset(phy) : 0; -+ if (ret) -+ dev_err(phy->dev, "PHY: Failed to reset %s: %d.\n", -+ phy->dev->name, ret); -+ -+ return ret; - } - - int generic_phy_exit(struct phy *phy) - { - struct phy_ops const *ops; -+ int ret; - - if (!phy) - return 0; - ops = phy_dev_ops(phy->dev); - -- return ops->exit ? ops->exit(phy) : 0; -+ ret = ops->exit ? ops->exit(phy) : 0; -+ if (ret) -+ dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n", -+ phy->dev->name, ret); -+ -+ return ret; - } - - int generic_phy_power_on(struct phy *phy) - { - struct phy_ops const *ops; -+ int ret; - - if (!phy) - return 0; - ops = phy_dev_ops(phy->dev); - -- return ops->power_on ? ops->power_on(phy) : 0; -+ ret = ops->power_on ? ops->power_on(phy) : 0; -+ if (ret) -+ dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n", -+ phy->dev->name, ret); -+ -+ return ret; - } - - int generic_phy_power_off(struct phy *phy) - { - struct phy_ops const *ops; -+ int ret; - - if (!phy) - return 0; - ops = phy_dev_ops(phy->dev); - -- return ops->power_off ? ops->power_off(phy) : 0; -+ ret = ops->power_off ? ops->power_off(phy) : 0; -+ if (ret) -+ dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n", -+ phy->dev->name, ret); -+ -+ return ret; - } - - UCLASS_DRIVER(phy) = { -diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c -index eecf0f5..9c4f73b 100644 ---- a/drivers/pinctrl/pinctrl-generic.c -+++ b/drivers/pinctrl/pinctrl-generic.c -@@ -8,8 +8,6 @@ - #include - #include - --DECLARE_GLOBAL_DATA_PTR; -- - /** - * pinctrl_pin_name_to_selector() - return the pin selector for a pin - * -@@ -243,18 +241,14 @@ static int pinctrl_generic_set_state_one(struct udevice *dev, - struct udevice *config, - bool is_group, unsigned selector) - { -- const void *fdt = gd->fdt_blob; -- int node_offset = dev_of_offset(config); - const char *propname; - const void *value; -- int prop_offset, len, func_selector, param, ret; -+ struct ofprop property; -+ int len, func_selector, param, ret; - u32 arg, default_val; - -- for (prop_offset = fdt_first_property_offset(fdt, node_offset); -- prop_offset > 0; -- prop_offset = fdt_next_property_offset(fdt, prop_offset)) { -- value = fdt_getprop_by_offset(fdt, prop_offset, -- &propname, &len); -+ dev_for_each_property(property, config) { -+ value = dev_read_prop_by_prop(&property, &propname, &len); - if (!value) - return -EINVAL; - -@@ -298,19 +292,17 @@ static int pinctrl_generic_set_state_one(struct udevice *dev, - static int pinctrl_generic_set_state_subnode(struct udevice *dev, - struct udevice *config) - { -- const void *fdt = gd->fdt_blob; -- int node = dev_of_offset(config); - const char *subnode_target_type = "pins"; - bool is_group = false; - const char *name; - int strings_count, selector, i, ret; - -- strings_count = fdt_stringlist_count(fdt, node, subnode_target_type); -+ strings_count = dev_read_string_count(config, subnode_target_type); - if (strings_count < 0) { - subnode_target_type = "groups"; - is_group = true; -- strings_count = fdt_stringlist_count(fdt, node, -- subnode_target_type); -+ strings_count = dev_read_string_count(config, -+ subnode_target_type); - if (strings_count < 0) { - /* skip this node; may contain config child nodes */ - return 0; -@@ -318,10 +310,10 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev, - } - - for (i = 0; i < strings_count; i++) { -- name = fdt_stringlist_get(fdt, node, subnode_target_type, i, -- NULL); -- if (!name) -- return -EINVAL; -+ ret = dev_read_string_index(config, subnode_target_type, i, -+ &name); -+ if (ret) -+ return ret; - - if (is_group) - selector = pinctrl_group_name_to_selector(dev, name); -diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c -index 0786afe..3ee75fb 100644 ---- a/drivers/pinctrl/pinctrl-sandbox.c -+++ b/drivers/pinctrl/pinctrl-sandbox.c -@@ -14,7 +14,11 @@ static const char * const sandbox_pins[] = { - "SDA", - "TX", - "RX", -- "W1" -+ "W1", -+ "GPIO0", -+ "GPIO1", -+ "GPIO2", -+ "GPIO3", - }; - - static const char * const sandbox_pins_muxing[] = { -@@ -23,6 +27,10 @@ static const char * const sandbox_pins_muxing[] = { - "Uart TX", - "Uart RX", - "1-wire gpio", -+ "gpio", -+ "gpio", -+ "gpio", -+ "gpio", - }; - - static const char * const sandbox_groups[] = { -@@ -38,6 +46,10 @@ static const char * const sandbox_functions[] = { - "serial", - "spi", - "w1", -+ "gpio", -+ "gpio", -+ "gpio", -+ "gpio", - }; - - static const struct pinconf_param sandbox_conf_params[] = { -@@ -54,6 +66,10 @@ static const struct pinconf_param sandbox_conf_params[] = { - { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, - }; - -+/* bitfield used to save param and value of each pin/selector */ -+static unsigned int sandbox_pins_param[ARRAY_SIZE(sandbox_pins)]; -+static unsigned int sandbox_pins_value[ARRAY_SIZE(sandbox_pins)]; -+ - static int sandbox_get_pins_count(struct udevice *dev) - { - return ARRAY_SIZE(sandbox_pins); -@@ -68,8 +84,25 @@ static int sandbox_get_pin_muxing(struct udevice *dev, - unsigned int selector, - char *buf, int size) - { -+ const struct pinconf_param *p; -+ int i; -+ - snprintf(buf, size, "%s", sandbox_pins_muxing[selector]); - -+ if (sandbox_pins_param[selector]) { -+ for (i = 0, p = sandbox_conf_params; -+ i < ARRAY_SIZE(sandbox_conf_params); -+ i++, p++) { -+ if ((sandbox_pins_param[selector] & BIT(p->param)) && -+ (!!(sandbox_pins_value[selector] & BIT(p->param)) == -+ p->default_value)) { -+ strncat(buf, " ", size); -+ strncat(buf, p->property, size); -+ } -+ } -+ } -+ strncat(buf, ".", size); -+ - return 0; - } - -@@ -102,6 +135,9 @@ static int sandbox_pinmux_set(struct udevice *dev, unsigned pin_selector, - pin_selector, sandbox_get_pin_name(dev, pin_selector), - func_selector, sandbox_get_function_name(dev, func_selector)); - -+ sandbox_pins_param[pin_selector] = 0; -+ sandbox_pins_value[pin_selector] = 0; -+ - return 0; - } - -@@ -123,6 +159,12 @@ static int sandbox_pinconf_set(struct udevice *dev, unsigned pin_selector, - pin_selector, sandbox_get_pin_name(dev, pin_selector), - param, argument); - -+ sandbox_pins_param[pin_selector] |= BIT(param); -+ if (argument) -+ sandbox_pins_value[pin_selector] |= BIT(param); -+ else -+ sandbox_pins_value[pin_selector] &= ~BIT(param); -+ - return 0; - } - -diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c -index 1dfc97d..6d8f989 100644 ---- a/drivers/pinctrl/pinctrl-single.c -+++ b/drivers/pinctrl/pinctrl-single.c -@@ -9,8 +9,6 @@ - #include - #include - --DECLARE_GLOBAL_DATA_PTR; -- - struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ -@@ -117,13 +115,11 @@ static int single_configure_bits(struct udevice *dev, - static int single_set_state(struct udevice *dev, - struct udevice *config) - { -- const void *fdt = gd->fdt_blob; - const struct single_fdt_pin_cfg *prop; - const struct single_fdt_bits_cfg *prop_bits; - int len; - -- prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins", -- &len); -+ prop = dev_read_prop(dev, "pinctrl-single,pins", &len); - - if (prop) { - dev_dbg(dev, "configuring pins for %s\n", config->name); -@@ -136,9 +132,7 @@ static int single_set_state(struct udevice *dev, - } - - /* pinctrl-single,pins not found so check for pinctrl-single,bits */ -- prop_bits = fdt_getprop(fdt, dev_of_offset(config), -- "pinctrl-single,bits", -- &len); -+ prop_bits = dev_read_prop(dev, "pinctrl-single,bits", &len); - if (prop_bits) { - dev_dbg(dev, "configuring pins for %s\n", config->name); - if (len % sizeof(struct single_fdt_bits_cfg)) { -@@ -160,27 +154,24 @@ static int single_ofdata_to_platdata(struct udevice *dev) - int res; - struct single_pdata *pdata = dev->platdata; - -- pdata->width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), -- "pinctrl-single,register-width", 0); -+ pdata->width = -+ dev_read_u32_default(dev, "pinctrl-single,register-width", 0); - -- res = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), -- "reg", of_reg, 2); -+ res = dev_read_u32_array(dev, "reg", of_reg, 2); - if (res) - return res; - pdata->offset = of_reg[1] - pdata->width / 8; - -- addr = devfdt_get_addr(dev); -+ addr = dev_read_addr(dev); - if (addr == FDT_ADDR_T_NONE) { - dev_dbg(dev, "no valid base register address\n"); - return -EINVAL; - } - pdata->base = addr; - -- pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), -- "pinctrl-single,function-mask", -- 0xffffffff); -- pdata->bits_per_mux = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), -- "pinctrl-single,bit-per-mux"); -+ pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask", -+ 0xffffffff); -+ pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); - - return 0; - } -diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c -index 0b5a043..b7987d5 100644 ---- a/drivers/pinctrl/pinctrl-stmfx.c -+++ b/drivers/pinctrl/pinctrl-stmfx.c -@@ -71,17 +71,61 @@ static int stmfx_write(struct udevice *dev, uint offset, unsigned int val) - return dm_i2c_reg_write(dev_get_parent(dev), offset, val); - } - --static int stmfx_gpio_get(struct udevice *dev, unsigned int offset) -+static int stmfx_read_reg(struct udevice *dev, u8 reg_base, uint offset) - { -- u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); -+ u8 reg = reg_base + get_reg(offset); - u32 mask = get_mask(offset); - int ret; - - ret = stmfx_read(dev, reg); -+ if (ret < 0) -+ return ret; - - return ret < 0 ? ret : !!(ret & mask); - } - -+static int stmfx_write_reg(struct udevice *dev, u8 reg_base, uint offset, -+ uint val) -+{ -+ u8 reg = reg_base + get_reg(offset); -+ u32 mask = get_mask(offset); -+ int ret; -+ -+ ret = stmfx_read(dev, reg); -+ if (ret < 0) -+ return ret; -+ ret = (ret & ~mask) | (val ? mask : 0); -+ -+ return stmfx_write(dev, reg, ret); -+} -+ -+static int stmfx_conf_set_pupd(struct udevice *dev, -+ unsigned int offset, uint pupd) -+{ -+ return stmfx_write_reg(dev, STMFX_REG_GPIO_PUPD, offset, pupd); -+} -+ -+static int stmfx_conf_get_pupd(struct udevice *dev, unsigned int offset) -+{ -+ return stmfx_read_reg(dev, STMFX_REG_GPIO_PUPD, offset); -+} -+ -+static int stmfx_conf_set_type(struct udevice *dev, -+ unsigned int offset, uint type) -+{ -+ return stmfx_write_reg(dev, STMFX_REG_GPIO_TYPE, offset, type); -+} -+ -+static int stmfx_conf_get_type(struct udevice *dev, unsigned int offset) -+{ -+ return stmfx_read_reg(dev, STMFX_REG_GPIO_TYPE, offset); -+} -+ -+static int stmfx_gpio_get(struct udevice *dev, unsigned int offset) -+{ -+ return stmfx_read_reg(dev, STMFX_REG_GPIO_STATE, offset); -+} -+ - static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value) - { - u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; -@@ -92,50 +136,103 @@ static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value) - - static int stmfx_gpio_get_function(struct udevice *dev, unsigned int offset) - { -- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); -- u32 mask = get_mask(offset); -- int ret; -- -- ret = stmfx_read(dev, reg); -+ int ret = stmfx_read_reg(dev, STMFX_REG_GPIO_DIR, offset); - - if (ret < 0) - return ret; - /* On stmfx, gpio pins direction is (0)input, (1)output. */ - -- return ret & mask ? GPIOF_OUTPUT : GPIOF_INPUT; -+ return ret ? GPIOF_OUTPUT : GPIOF_INPUT; - } - - static int stmfx_gpio_direction_input(struct udevice *dev, unsigned int offset) - { -- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); -- u32 mask = get_mask(offset); -- int ret; -+ return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 0); -+} - -- ret = stmfx_read(dev, reg); -+static int stmfx_gpio_direction_output(struct udevice *dev, -+ unsigned int offset, int value) -+{ -+ int ret = stmfx_gpio_set(dev, offset, value); - if (ret < 0) - return ret; - -- ret &= ~mask; -+ return stmfx_write_reg(dev, STMFX_REG_GPIO_DIR, offset, 1); -+} - -- return stmfx_write(dev, reg, ret & ~mask); -+static int stmfx_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong flags) -+{ -+ int ret = -ENOTSUPP; -+ -+ if (flags & GPIOD_IS_OUT) { -+ if (flags & GPIOD_OPEN_SOURCE) -+ return -ENOTSUPP; -+ if (flags & GPIOD_OPEN_DRAIN) -+ ret = stmfx_conf_set_type(dev, offset, 0); -+ else /* PUSH-PULL */ -+ ret = stmfx_conf_set_type(dev, offset, 1); -+ if (ret) -+ return ret; -+ ret = stmfx_gpio_direction_output(dev, offset, -+ GPIOD_FLAGS_OUTPUT(flags)); -+ } else if (flags & GPIOD_IS_IN) { -+ ret = stmfx_gpio_direction_input(dev, offset); -+ if (ret) -+ return ret; -+ if (flags & GPIOD_PULL_UP) { -+ ret = stmfx_conf_set_type(dev, offset, 1); -+ if (ret) -+ return ret; -+ ret = stmfx_conf_set_pupd(dev, offset, 1); -+ } else if (flags & GPIOD_PULL_DOWN) { -+ ret = stmfx_conf_set_type(dev, offset, 1); -+ if (ret) -+ return ret; -+ ret = stmfx_conf_set_pupd(dev, offset, 0); -+ } -+ } -+ -+ return ret; - } - --static int stmfx_gpio_direction_output(struct udevice *dev, -- unsigned int offset, int value) -+static int stmfx_gpio_get_dir_flags(struct udevice *dev, unsigned int offset, -+ ulong *flags) - { -- u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); -- u32 mask = get_mask(offset); -+ ulong dir_flags = 0; - int ret; - -- ret = stmfx_gpio_set(dev, offset, value); -- if (ret < 0) -- return ret; -- -- ret = stmfx_read(dev, reg); -- if (ret < 0) -- return ret; -+ if (stmfx_gpio_get_function(dev, offset) == GPIOF_OUTPUT) { -+ dir_flags |= GPIOD_IS_OUT; -+ ret = stmfx_conf_get_type(dev, offset); -+ if (ret < 0) -+ return ret; -+ if (ret == 0) -+ dir_flags |= GPIOD_OPEN_DRAIN; -+ /* 1 = push-pull (default), open source not supported */ -+ ret = stmfx_gpio_get(dev, offset); -+ if (ret < 0) -+ return ret; -+ if (ret) -+ dir_flags |= GPIOD_IS_OUT_ACTIVE; -+ } else { -+ dir_flags |= GPIOD_IS_IN; -+ ret = stmfx_conf_get_type(dev, offset); -+ if (ret < 0) -+ return ret; -+ if (ret == 1) { -+ ret = stmfx_conf_get_pupd(dev, offset); -+ if (ret < 0) -+ return ret; -+ if (ret == 1) -+ dir_flags |= GPIOD_PULL_UP; -+ else -+ dir_flags |= GPIOD_PULL_DOWN; -+ } -+ } -+ *flags = dir_flags; - -- return stmfx_write(dev, reg, ret | mask); -+ return 0; - } - - static int stmfx_gpio_probe(struct udevice *dev) -@@ -166,6 +263,8 @@ static const struct dm_gpio_ops stmfx_gpio_ops = { - .get_function = stmfx_gpio_get_function, - .direction_input = stmfx_gpio_direction_input, - .direction_output = stmfx_gpio_direction_output, -+ .set_dir_flags = stmfx_gpio_set_dir_flags, -+ .get_dir_flags = stmfx_gpio_get_dir_flags, - }; - - U_BOOT_DRIVER(stmfx_gpio) = { -@@ -187,36 +286,6 @@ static const struct pinconf_param stmfx_pinctrl_conf_params[] = { - { "output-low", PIN_CONFIG_OUTPUT, 0 }, - }; - --static int stmfx_pinctrl_set_pupd(struct udevice *dev, -- unsigned int pin, u32 pupd) --{ -- u8 reg = STMFX_REG_GPIO_PUPD + get_reg(pin); -- u32 mask = get_mask(pin); -- int ret; -- -- ret = stmfx_read(dev, reg); -- if (ret < 0) -- return ret; -- ret = (ret & ~mask) | (pupd ? mask : 0); -- -- return stmfx_write(dev, reg, ret); --} -- --static int stmfx_pinctrl_set_type(struct udevice *dev, -- unsigned int pin, u32 type) --{ -- u8 reg = STMFX_REG_GPIO_TYPE + get_reg(pin); -- u32 mask = get_mask(pin); -- int ret; -- -- ret = stmfx_read(dev, reg); -- if (ret < 0) -- return ret; -- ret = (ret & ~mask) | (type ? mask : 0); -- -- return stmfx_write(dev, reg, ret); --} -- - static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin, - unsigned int param, unsigned int arg) - { -@@ -232,22 +301,22 @@ static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin, - case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_DRIVE_PUSH_PULL: -- ret = stmfx_pinctrl_set_type(dev, pin, 0); -+ ret = stmfx_conf_set_type(dev, pin, 0); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- ret = stmfx_pinctrl_set_type(dev, pin, 1); -+ ret = stmfx_conf_set_type(dev, pin, 1); - if (ret) - return ret; -- ret = stmfx_pinctrl_set_pupd(dev, pin, 0); -+ ret = stmfx_conf_set_pupd(dev, pin, 0); - break; - case PIN_CONFIG_BIAS_PULL_UP: -- ret = stmfx_pinctrl_set_type(dev, pin, 1); -+ ret = stmfx_conf_set_type(dev, pin, 1); - if (ret) - return ret; -- ret = stmfx_pinctrl_set_pupd(dev, pin, 1); -+ ret = stmfx_conf_set_pupd(dev, pin, 1); - break; - case PIN_CONFIG_DRIVE_OPEN_DRAIN: -- ret = stmfx_pinctrl_set_type(dev, pin, 1); -+ ret = stmfx_conf_set_type(dev, pin, 1); - break; - case PIN_CONFIG_OUTPUT: - ret = stmfx_gpio_direction_output(plat->gpio, pin, arg); -@@ -286,6 +355,34 @@ static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, - return pin_name; - } - -+static const char *stmfx_pinctrl_get_pin_conf(struct udevice *dev, -+ unsigned int pin, int func) -+{ -+ int pupd, type; -+ -+ type = stmfx_conf_get_type(dev, pin); -+ if (type < 0) -+ return ""; -+ -+ if (func == GPIOF_OUTPUT) { -+ if (type) -+ return "drive-open-drain"; -+ else -+ return ""; /* default: push-pull*/ -+ } -+ if (!type) -+ return ""; /* default: bias-disable*/ -+ -+ pupd = stmfx_conf_get_pupd(dev, pin); -+ if (pupd < 0) -+ return ""; -+ -+ if (pupd) -+ return "bias-pull-up"; -+ else -+ return "bias-pull-down"; -+} -+ - static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev, - unsigned int selector, - char *buf, int size) -@@ -297,7 +394,9 @@ static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev, - if (func < 0) - return func; - -- snprintf(buf, size, "%s", func == GPIOF_INPUT ? "input" : "output"); -+ snprintf(buf, size, "%s ", func == GPIOF_INPUT ? "input" : "output"); -+ -+ strncat(buf, stmfx_pinctrl_get_pin_conf(dev, selector, func), size); - - return 0; - } -@@ -351,11 +450,12 @@ static int stmfx_chip_init(struct udevice *dev) - int ret; - struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); - -- id = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID); -- if (id < 0) { -- dev_err(dev, "error reading chip id: %d\n", id); -+ ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID); -+ if (ret < 0) { -+ dev_err(dev, "error reading chip id: %d\n", ret); - return ret; - } -+ id = (u8)ret; - /* - * Check that ID is the complement of the I2C address: - * STMFX I2C address follows the 7-bit format (MSB), that's why -diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c -index 3a235ae..4511cd7 100644 ---- a/drivers/pinctrl/pinctrl_stm32.c -+++ b/drivers/pinctrl/pinctrl_stm32.c -@@ -39,6 +39,17 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { - "alt function", - }; - -+static const char * const pinmux_output[] = { -+ [STM32_GPIO_PUPD_NO] = "bias-disable", -+ [STM32_GPIO_PUPD_UP] = "bias-pull-up", -+ [STM32_GPIO_PUPD_DOWN] = "bias-pull-down", -+}; -+ -+static const char * const pinmux_input[] = { -+ [STM32_GPIO_OTYPE_PP] = "drive-push-pull", -+ [STM32_GPIO_OTYPE_OD] = "drive-open-drain", -+}; -+ - static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) - { - struct stm32_gpio_priv *priv = dev_get_priv(dev); -@@ -176,10 +187,12 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, - int size) - { - struct udevice *gpio_dev; -+ struct stm32_gpio_priv *priv; - const char *label; - int mode; - int af_num; - unsigned int gpio_idx; -+ u32 pupd, otype; - - /* look up for the bank which owns the requested pin */ - gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); -@@ -188,9 +201,9 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, - return -ENODEV; - - mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label); -- - dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", - selector, gpio_idx, mode); -+ priv = dev_get_priv(gpio_dev); - - - switch (mode) { -@@ -205,9 +218,17 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, - snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num); - break; - case GPIOF_OUTPUT: -+ pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & -+ PUPD_MASK; -+ snprintf(buf, size, "%s %s %s", -+ pinmux_mode[mode], pinmux_output[pupd], -+ label ? label : ""); -+ break; - case GPIOF_INPUT: -- snprintf(buf, size, "%s %s", -- pinmux_mode[mode], label ? label : ""); -+ otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; -+ snprintf(buf, size, "%s %s %s", -+ pinmux_mode[mode], pinmux_input[otype], -+ label ? label : ""); - break; - } - -diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c -index 645528e..c8ff6a1 100644 ---- a/drivers/power/regulator/stm32-vrefbuf.c -+++ b/drivers/power/regulator/stm32-vrefbuf.c -@@ -41,8 +41,20 @@ static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable) - u32 val; - int ret; - -- clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ | STM32_ENVR, -- enable ? STM32_ENVR : STM32_HIZ); -+ if (enable && !(readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR)) { -+ /* -+ * There maybe an overshoot: -+ * - when disabling, then re-enabling vrefbuf too quickly -+ * - or upon platform reset as external capacitor maybe slow -+ * discharging (VREFBUF is HiZ at reset by default). -+ * So force active discharge (HiZ=0) for 1ms before enabling. -+ */ -+ clrbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ); -+ udelay(1000); -+ } -+ -+ clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR, -+ enable ? STM32_ENVR : 0); - if (!enable) - return 0; - -diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c -index d765a46..11b14ae 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_ddr.c -+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c -@@ -639,7 +639,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) - start_sw_done(ctl); - /* quasi-dynamic register update*/ - setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); -- clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); -+ clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN | -+ DDRCTRL_PWRCTL_SELFREF_EN); - clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - wait_sw_done_ack(ctl); - } -@@ -652,6 +653,8 @@ void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, - clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); - if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) - setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); -+ if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN)) -+ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); - setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - wait_sw_done_ack(ctl); - } -@@ -668,14 +671,34 @@ void stm32mp1_ddr_init(struct ddr_info *priv, - { - u32 pir; - int ret = -EINVAL; -+ char bus_width; -+ -+ switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { -+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER: -+ bus_width = 8; -+ break; -+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: -+ bus_width = 16; -+ break; -+ default: -+ bus_width = 32; -+ break; -+ } -+ - - if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) - ret = board_ddr_power_init(STM32MP_DDR3); -- else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) -- ret = board_ddr_power_init(STM32MP_LPDDR2); -- else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) -- ret = board_ddr_power_init(STM32MP_LPDDR3); -- -+ else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) { -+ if (bus_width == 32) -+ ret = board_ddr_power_init(STM32MP_LPDDR2_32); -+ else -+ ret = board_ddr_power_init(STM32MP_LPDDR2_16); -+ } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) { -+ if (bus_width == 32) -+ ret = board_ddr_power_init(STM32MP_LPDDR3_32); -+ else -+ ret = board_ddr_power_init(STM32MP_LPDDR3_16); -+ } - if (ret) - panic("ddr power init failed\n"); - -@@ -746,7 +769,8 @@ start: - */ - set_reg(priv, REGPHY_REG, &config->p_reg); - set_reg(priv, REGPHY_TIMING, &config->p_timing); -- set_reg(priv, REGPHY_CAL, &config->p_cal); -+ if (config->p_cal_present) -+ set_reg(priv, REGPHY_CAL, &config->p_cal); - - if (INTERACTIVE(STEP_PHY_INIT)) - goto start; -@@ -781,13 +805,16 @@ start: - - wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); - -- debug("DDR DQS training : "); -+ if (config->p_cal_present) { -+ debug("DDR DQS training skipped.\n"); -+ } else { -+ debug("DDR DQS training : "); - /* 8. Disable Auto refresh and power down by setting - * - RFSHCTL3.dis_au_refresh = 1 - * - PWRCTL.powerdown_en = 0 - * - DFIMISC.dfiinit_complete_en = 0 - */ -- stm32mp1_refresh_disable(priv->ctl); -+ stm32mp1_refresh_disable(priv->ctl); - - /* 9. Program PUBL PGCR to enable refresh during training and rank to train - * not done => keep the programed value in PGCR -@@ -795,14 +822,15 @@ start: - - /* 10. configure PUBL PIR register to specify which training step to run */ - /* warning : RVTRN is not supported by this PUBL */ -- stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); -+ stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); - - /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ -- ddrphy_idone_wait(priv->phy); -+ ddrphy_idone_wait(priv->phy); - - /* 12. set back registers in step 8 to the orginal values if desidered */ -- stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, -- config->c_reg.pwrctl); -+ stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, -+ config->c_reg.pwrctl); -+ } /* if (config->p_cal_present) */ - - /* enable uMCTL2 AXI port 0 and 1 */ - setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); -diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h -index 52b748f..4998f04 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_ddr.h -+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h -@@ -170,6 +170,7 @@ struct stm32mp1_ddr_config { - struct stm32mp1_ddrphy_reg p_reg; - struct stm32mp1_ddrphy_timing p_timing; - struct stm32mp1_ddrphy_cal p_cal; -+ bool p_cal_present; - }; - - int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed); -diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h -index 9d33186..afd93c5 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h -+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h -@@ -260,6 +260,7 @@ struct stm32mp1_ddrphy { - - #define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) - -+#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) - #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) - #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) - -diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c -index cc9b2e7..805c9dd 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_interactive.c -+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c -@@ -106,7 +106,7 @@ static void stm32mp1_do_usage(void) - "help displays help\n" - "info displays DDR information\n" - "info changes DDR information\n" -- " with = step, name, size or speed\n" -+ " with = step, name, size, speed or cal\n" - "freq displays the DDR PHY frequency in kHz\n" - "freq changes the DDR PHY frequency\n" - "param [type|reg] prints input parameters\n" -@@ -160,6 +160,7 @@ static void stm32mp1_do_info(struct ddr_info *priv, - printf("name = %s\n", config->info.name); - printf("size = 0x%x\n", config->info.size); - printf("speed = %d kHz\n", config->info.speed); -+ printf("cal = %d\n", config->p_cal_present); - return; - } - -@@ -208,6 +209,16 @@ static void stm32mp1_do_info(struct ddr_info *priv, - } - return; - } -+ if (!strcmp(argv[1], "cal")) { -+ if (strict_strtoul(argv[2], 10, &value) < 0 || -+ (value != 0 && value != 1)) { -+ printf("invalid value %s\n", argv[2]); -+ } else { -+ config->p_cal_present = value; -+ printf("cal = %d\n", config->p_cal_present); -+ } -+ return; -+ } - printf("argument %s invalid\n", argv[1]); - } - -@@ -367,7 +378,6 @@ bool stm32mp1_ddr_interactive(void *priv, - enum stm32mp1_ddr_interact_step step, - const struct stm32mp1_ddr_config *config) - { -- const char *prompt = "DDR>"; - char buffer[CONFIG_SYS_CBSIZE]; - char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ - int argc; -@@ -403,13 +413,12 @@ bool stm32mp1_ddr_interactive(void *priv, - } - - printf("%d:%s\n", step, step_str[step]); -- printf("%s\n", prompt); - - if (next_step > step) - return false; - - while (next_step == step) { -- cli_readline_into_buffer(prompt, buffer, 0); -+ cli_readline_into_buffer("DDR>", buffer, 0); - argc = cli_simple_parse_line(buffer, argv); - if (!argc) - continue; -diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c -index a362cf9..c54f314 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_ram.c -+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c -@@ -64,18 +64,22 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) - struct clk axidcg; - struct stm32mp1_ddr_config config; - --#define PARAM(x, y) \ -- { x,\ -- offsetof(struct stm32mp1_ddr_config, y),\ -- sizeof(config.y) / sizeof(u32)} -+#define PARAM(x, y, z) \ -+ { .name = x, \ -+ .offset = offsetof(struct stm32mp1_ddr_config, y), \ -+ .size = sizeof(config.y) / sizeof(u32), \ -+ .present = z, \ -+ } - --#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) --#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) -+#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL) -+#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL) -+#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present) - - const struct { - const char *name; /* name in DT */ - const u32 offset; /* offset in config struct */ - const u32 size; /* size of parameters */ -+ bool * const present; /* presence indication for opt */ - } param[] = { - CTL_PARAM(reg), - CTL_PARAM(timing), -@@ -83,7 +87,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) - CTL_PARAM(perf), - PHY_PARAM(reg), - PHY_PARAM(timing), -- PHY_PARAM(cal) -+ PHY_PARAM_OPT(cal) - }; - - config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); -@@ -102,11 +106,25 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) - param[idx].size); - debug("%s: %s[0x%x] = %d\n", __func__, - param[idx].name, param[idx].size, ret); -- if (ret) { -+ if (ret && -+ (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) { - pr_err("%s: Cannot read %s, error=%d\n", - __func__, param[idx].name, ret); - return -EINVAL; - } -+ if (param[idx].present) { -+ /* save presence of optional parameters */ -+ *param[idx].present = true; -+ if (ret == -FDT_ERR_NOTFOUND) { -+ *param[idx].present = false; -+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE -+ /* reset values if used later */ -+ memset((void *)((u32)&config + -+ param[idx].offset), -+ 0, param[idx].size * sizeof(u32)); -+#endif -+ } -+ } - } - - ret = clk_get_by_name(dev, "axidcg", &axidcg); -diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c -index 581ee48..cc7b429 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_tests.c -+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c -@@ -14,7 +14,7 @@ - DECLARE_GLOBAL_DATA_PTR; - - static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, -- size_t *bufsize, size_t default_size) -+ size_t *bufsize, size_t default_size, size_t min_size) - { - unsigned long value; - -@@ -24,8 +24,9 @@ static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, - arg_nb, argv[arg_nb]); - return -1; - } -- if (value > STM32_DDR_SIZE || value == 0) { -- sprintf(string, "invalid size %s", argv[arg_nb]); -+ if (value > STM32_DDR_SIZE || value < min_size) { -+ sprintf(string, "invalid size %s (min=%d)", -+ argv[arg_nb], min_size); - return -1; - } - if (value & 0x3) { -@@ -438,7 +439,7 @@ static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl, - u32 bufsize; - u32 error; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (!is_power_of_2(bufsize)) { - sprintf(string, "size 0x%x is not a power of 2", -@@ -467,7 +468,7 @@ static enum test_result test_memdevice(struct stm32mp1_ddrctl *ctl, - size_t bufsize; - u32 error; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (get_addr(string, argc, argv, 1, &addr)) - return TEST_ERROR; -@@ -509,7 +510,7 @@ static enum test_result test_sso(struct stm32mp1_ddrctl *ctl, - u32 error = 0; - u32 data; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (get_addr(string, argc, argv, 1, &addr)) - return TEST_ERROR; -@@ -581,7 +582,7 @@ static enum test_result test_random(struct stm32mp1_ddrctl *ctl, - u32 error = 0; - unsigned int seed; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 8 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -741,7 +742,7 @@ static enum test_result test_noise_burst(struct stm32mp1_ddrctl *ctl, - int i; - enum test_result res = TEST_PASSED; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128)) - return TEST_ERROR; - if (get_pattern(string, argc, argv, 1, &pattern, 0xFFFFFFFF)) - return TEST_ERROR; -@@ -917,7 +918,7 @@ static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl, - const u32 **patterns; - u32 bufsize; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128)) - return TEST_ERROR; - - switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { -@@ -1004,7 +1005,7 @@ static enum test_result test_checkboard(struct stm32mp1_ddrctl *ctl, - - u32 checkboard[2] = {0x55555555, 0xAAAAAAAA}; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -1039,7 +1040,7 @@ static enum test_result test_blockseq(struct stm32mp1_ddrctl *ctl, - u32 bufsize, nb_loop, loop = 0, addr, value; - int i; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -1073,7 +1074,7 @@ static enum test_result test_walkbit0(struct stm32mp1_ddrctl *ctl, - u32 bufsize, nb_loop, loop = 0, addr, value; - int i; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -1111,7 +1112,7 @@ static enum test_result test_walkbit1(struct stm32mp1_ddrctl *ctl, - u32 bufsize, nb_loop, loop = 0, addr, value; - int i; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -1153,7 +1154,7 @@ static enum test_result test_bitspread(struct stm32mp1_ddrctl *ctl, - u32 bufsize, nb_loop, loop = 0, addr, bitspread[4]; - int i, j; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -@@ -1200,7 +1201,7 @@ static enum test_result test_bitflip(struct stm32mp1_ddrctl *ctl, - - u32 bitflip[4]; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32)) - return TEST_ERROR; - if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) - return TEST_ERROR; -diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c -index 4e1c1fa..3013b7b 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_tuning.c -+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c -@@ -8,6 +8,8 @@ - #include - #include - #include -+#include -+#include - - #include "stm32mp1_ddr_regs.h" - #include "stm32mp1_ddr.h" -@@ -75,6 +77,133 @@ static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl) - return nb_bytes; - } - -+static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl) -+{ -+ /* Count bank address bits */ -+ u8 bits = 0; -+ u32 reg, val; -+ -+ reg = readl(&ctl->addrmap1); -+ /* addrmap1.addrmap_bank_b1 */ -+ val = (reg & GENMASK(5, 0)) >> 0; -+ if (val <= 31) -+ bits++; -+ /* addrmap1.addrmap_bank_b2 */ -+ val = (reg & GENMASK(13, 8)) >> 8; -+ if (val <= 31) -+ bits++; -+ /* addrmap1.addrmap_bank_b3 */ -+ val = (reg & GENMASK(21, 16)) >> 16; -+ if (val <= 31) -+ bits++; -+ -+ return bits; -+} -+ -+static u8 get_nb_col(struct stm32mp1_ddrctl *ctl) -+{ -+ u8 bits; -+ u32 reg, val; -+ -+ /* Count column address bits, start at 2 for b0 and b1 (fixed) */ -+ bits = 2; -+ -+ reg = readl(&ctl->addrmap2); -+ /* addrmap2.addrmap_col_b2 */ -+ val = (reg & GENMASK(3, 0)) >> 0; -+ if (val <= 7) -+ bits++; -+ /* addrmap2.addrmap_col_b3 */ -+ val = (reg & GENMASK(11, 8)) >> 8; -+ if (val <= 7) -+ bits++; -+ /* addrmap2.addrmap_col_b4 */ -+ val = (reg & GENMASK(19, 16)) >> 16; -+ if (val <= 7) -+ bits++; -+ /* addrmap2.addrmap_col_b5 */ -+ val = (reg & GENMASK(27, 24)) >> 24; -+ if (val <= 7) -+ bits++; -+ -+ reg = readl(&ctl->addrmap3); -+ /* addrmap3.addrmap_col_b6 */ -+ val = (reg & GENMASK(3, 0)) >> 0; -+ if (val <= 7) -+ bits++; -+ /* addrmap3.addrmap_col_b7 */ -+ val = (reg & GENMASK(11, 8)) >> 8; -+ if (val <= 7) -+ bits++; -+ /* addrmap3.addrmap_col_b8 */ -+ val = (reg & GENMASK(19, 16)) >> 16; -+ if (val <= 7) -+ bits++; -+ /* addrmap3.addrmap_col_b9 */ -+ val = (reg & GENMASK(27, 24)) >> 24; -+ if (val <= 7) -+ bits++; -+ -+ reg = readl(&ctl->addrmap4); -+ /* addrmap4.addrmap_col_b10 */ -+ val = (reg & GENMASK(3, 0)) >> 0; -+ if (val <= 7) -+ bits++; -+ /* addrmap4.addrmap_col_b11 */ -+ val = (reg & GENMASK(11, 8)) >> 8; -+ if (val <= 7) -+ bits++; -+ -+ return bits; -+} -+ -+static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) -+{ -+ /* Count row address bits */ -+ u8 bits = 0; -+ u32 reg, val; -+ -+ reg = readl(&ctl->addrmap5); -+ /* addrmap5.addrmap_row_b0 */ -+ val = (reg & GENMASK(3, 0)) >> 0; -+ if (val <= 11) -+ bits++; -+ /* addrmap5.addrmap_row_b1 */ -+ val = (reg & GENMASK(11, 8)) >> 8; -+ if (val <= 11) -+ bits++; -+ /* addrmap5.addrmap_row_b2_10 */ -+ val = (reg & GENMASK(19, 16)) >> 16; -+ if (val <= 11) -+ bits += 9; -+ else -+ printf("warning: addrmap5.addrmap_row_b2_10 not supported\n"); -+ /* addrmap5.addrmap_row_b11 */ -+ val = (reg & GENMASK(27, 24)) >> 24; -+ if (val <= 11) -+ bits++; -+ -+ reg = readl(&ctl->addrmap6); -+ /* addrmap6.addrmap_row_b12 */ -+ val = (reg & GENMASK(3, 0)) >> 0; -+ if (val <= 7) -+ bits++; -+ /* addrmap6.addrmap_row_b13 */ -+ val = (reg & GENMASK(11, 8)) >> 8; -+ if (val <= 7) -+ bits++; -+ /* addrmap6.addrmap_row_b14 */ -+ val = (reg & GENMASK(19, 16)) >> 16; -+ if (val <= 7) -+ bits++; -+ /* addrmap6.addrmap_row_b15 */ -+ val = (reg & GENMASK(27, 24)) >> 24; -+ if (val <= 7) -+ bits++; -+ -+ return bits; -+} -+ - static void itm_soft_reset(struct stm32mp1_ddrphy *phy) - { - stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); -@@ -169,8 +298,13 @@ static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy, - } - - /* Basic BIST configuration for data lane tests. */ --static void config_BIST(struct stm32mp1_ddrphy *phy) -+static void config_BIST(struct stm32mp1_ddrctl *ctl, -+ struct stm32mp1_ddrphy *phy) - { -+ u8 nb_bank = get_nb_bank(ctl); -+ u8 nb_row = get_nb_row(ctl); -+ u8 nb_col = get_nb_col(ctl); -+ - /* Selects the SDRAM bank address to be used during BIST. */ - u32 bbank = 0; - /* Selects the SDRAM row address to be used during BIST. */ -@@ -190,18 +324,20 @@ static void config_BIST(struct stm32mp1_ddrphy *phy) - * must be 0 with single rank - */ - u32 brank = 0; -+ - /* Specifies the maximum SDRAM bank address to be used during - * BIST before the address & increments to the next rank. - */ -- u32 bmbank = 1; -+ u32 bmbank = (1 << nb_bank) - 1; - /* Specifies the maximum SDRAM row address to be used during - * BIST before the address & increments to the next bank. - */ -- u32 bmrow = 0x7FFF; /* To check */ -+ u32 bmrow = (1 << nb_row) - 1; - /* Specifies the maximum SDRAM column address to be used during - * BIST before the address & increments to the next row. - */ -- u32 bmcol = 0x3FF; /* To check */ -+ u32 bmcol = (1 << nb_col) - 1; -+ - u32 bmode_conf = 0x00000001; /* DRam mode */ - u32 bdxen_conf = 0x00000001; /* BIST on Data byte */ - u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */ -@@ -223,8 +359,6 @@ static void config_BIST(struct stm32mp1_ddrphy *phy) - - writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0); - writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1); -- -- /* To check this line : */ - writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2); - } - -@@ -246,6 +380,8 @@ static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte, - bool result = true; /* BIST_SUCCESS */ - u32 cnt = 0; - u32 error = 0; -+ u32 val; -+ int ret; - - bist->test_result = true; - -@@ -266,7 +402,7 @@ run: - writel(rand(), &phy->bistlsr); - - /* some delay to reset BIST */ -- mdelay(1); -+ udelay(10); - - /*Perform BIST Run*/ - clrsetbits_le32(&phy->bistrr, -@@ -274,27 +410,29 @@ run: - 0x00000001); - /* Write BISTRR.BINST = 3?b001; */ - -- /* Wait for a number of CTL clocks before reading BIST register*/ -- /* Wait 300 ctl_clk cycles; ... IS it really needed?? */ -- /* Perform BIST Instruction Stop*/ -- /* Write BISTRR.BINST = 3?b010;*/ -- -- /* poll on BISTGSR.BDONE. If 0, wait. ++TODO Add timeout */ -- while (!(readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDDONE)) -- ; -- -- /*Check if received correct number of words*/ -- /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */ -- if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) == -- readl(&phy->bistwcr)) { -- /*Determine if there is a data comparison error*/ -- /* if (Read BISTGSR.BDXERR = 1?b0) */ -- if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR) -- result = false; /* BIST_FAIL; */ -- else -- result = true; /* BIST_SUCCESS; */ -- } else { -+ /* poll on BISTGSR.BDONE and wait max 1000 us */ -+ ret = readl_poll_timeout(&phy->bistgsr, val, -+ val & DDRPHYC_BISTGSR_BDDONE, 1000); -+ -+ if (ret < 0) { -+ printf("warning: BIST timeout\n"); - result = false; /* BIST_FAIL; */ -+ /*Perform BIST Stop */ -+ clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002); -+ } else { -+ /*Check if received correct number of words*/ -+ /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */ -+ if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) -+ == readl(&phy->bistwcr)) { -+ /*Determine if there is a data comparison error*/ -+ /* if (Read BISTGSR.BDXERR = 1?b0) */ -+ if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR) -+ result = false; /* BIST_FAIL; */ -+ else -+ result = true; /* BIST_SUCCESS; */ -+ } else { -+ result = false; /* BIST_FAIL; */ -+ } - } - - /* loop while success */ -@@ -394,7 +532,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* Config the BIST block */ -- config_BIST(phy); -+ config_BIST(ctl, phy); - pr_debug("BIST Config done.\n"); - - /* Train each byte */ -@@ -807,7 +945,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* Config the BIST block */ -- config_BIST(phy); -+ config_BIST(ctl, phy); - - for (byte = 0; byte < nb_bytes; byte++) { - if (ctrlc()) { -@@ -1182,15 +1320,17 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, - dqs_gate_values[byte][0], - dqs_gate_values[byte][1]); - pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n"); -- set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]); -- set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]); - } - } else { - /* if intermitant, restore defaut values */ - pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n"); -- set_r0dgsl_delay(phy, byte, 0); -- set_r0dgps_delay(phy, byte, 2); -+ dqs_gate_values[byte][0] = 0; -+ dqs_gate_values[byte][1] = 2; - } -+ set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]); -+ set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]); -+ printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n", -+ byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]); - - /* return 0 if intermittent or if both left_bound - * and right_bound are not found -@@ -1227,7 +1367,7 @@ static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl, - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* config the bist block */ -- config_BIST(phy); -+ config_BIST(ctl, phy); - - for (byte = 0; byte < nb_bytes; byte++) { - if (ctrlc()) { -@@ -1281,11 +1421,16 @@ static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl, - { - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); -+ u32 derateen = readl(&ctl->derateen); - enum test_result res; - -+ writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); -+ - res = read_dqs_gating(ctl, phy, string); -+ - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); -+ writel(derateen, &ctl->derateen); - - return res; - } -@@ -1296,11 +1441,16 @@ static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl, - { - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); -+ u32 derateen = readl(&ctl->derateen); - enum test_result res; - -+ writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); -+ - res = bit_deskew(ctl, phy, string); -+ - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); -+ writel(derateen, &ctl->derateen); - - return res; - } -@@ -1311,11 +1461,16 @@ static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl, - { - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); -+ u32 derateen = readl(&ctl->derateen); - enum test_result res; - -+ writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); -+ - res = eye_training(ctl, phy, string); -+ - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); -+ writel(derateen, &ctl->derateen); - - return res; - } -diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c -index e8026cd..5384812 100644 ---- a/drivers/remoteproc/rproc-elf-loader.c -+++ b/drivers/remoteproc/rproc-elf-loader.c -@@ -8,6 +8,39 @@ - #include - #include - -+/** -+ * struct resource_table - firmware resource table header -+ * @ver: version number -+ * @num: number of resource entries -+ * @reserved: reserved (must be zero) -+ * @offset: array of offsets pointing at the various resource entries -+ * -+ * A resource table is essentially a list of system resources required -+ * by the remote processor. It may also include configuration entries. -+ * If needed, the remote processor firmware should contain this table -+ * as a dedicated ".resource_table" ELF section. -+ * -+ * Some resources entries are mere announcements, where the host is informed -+ * of specific remoteproc configuration. Other entries require the host to -+ * do something (e.g. allocate a system resource). Sometimes a negotiation -+ * is expected, where the firmware requests a resource, and once allocated, -+ * the host should provide back its details (e.g. address of an allocated -+ * memory region). -+ * -+ * The header of the resource table, as expressed by this structure, -+ * contains a version number (should we need to change this format in the -+ * future), the number of available resource entries, and their offsets -+ * in the table. -+ * -+ * Immediately following this header are the resource entries themselves. -+ */ -+struct resource_table { -+ u32 ver; -+ u32 num; -+ u32 reserved[2]; -+ u32 offset[0]; -+} __packed; -+ - /* Basic function to verify ELF32 image format */ - int rproc_elf32_sanity_check(ulong addr, ulong size) - { -@@ -276,3 +309,239 @@ ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr) - else - return rproc_elf32_get_boot_addr(addr); - } -+ -+/* -+ * Search for the resource table in an ELF32 image. -+ * Returns the address of the resource table section if found, NULL if there is -+ * no resource table section, or error pointer. -+ */ -+static Elf32_Shdr *rproc_elf32_find_rsc_table(struct udevice *dev, -+ ulong fw_addr, ulong fw_size) -+{ -+ int ret; -+ unsigned int i; -+ const char *name_table; -+ struct resource_table *table; -+ const u8 *elf_data = (void *)fw_addr; -+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)fw_addr; -+ Elf32_Shdr *shdr; -+ -+ ret = rproc_elf32_sanity_check(fw_addr, fw_size); -+ if (ret) { -+ pr_debug("Invalid ELF32 Image %d\n", ret); -+ return ERR_PTR(ret); -+ } -+ -+ /* look for the resource table and handle it */ -+ shdr = (Elf32_Shdr *)(elf_data + ehdr->e_shoff); -+ name_table = (const char *)(elf_data + -+ shdr[ehdr->e_shstrndx].sh_offset); -+ -+ for (i = 0; i < ehdr->e_shnum; i++, shdr++) { -+ u32 size = shdr->sh_size; -+ u32 offset = shdr->sh_offset; -+ -+ if (strcmp(name_table + shdr->sh_name, ".resource_table")) -+ continue; -+ -+ table = (struct resource_table *)(elf_data + offset); -+ -+ /* make sure we have the entire table */ -+ if (offset + size > fw_size) { -+ pr_debug("resource table truncated\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ /* make sure table has at least the header */ -+ if (sizeof(*table) > size) { -+ pr_debug("header-less resource table\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ /* we don't support any version beyond the first */ -+ if (table->ver != 1) { -+ pr_debug("unsupported fw ver: %d\n", table->ver); -+ return ERR_PTR(-EPROTONOSUPPORT); -+ } -+ -+ /* make sure reserved bytes are zeroes */ -+ if (table->reserved[0] || table->reserved[1]) { -+ pr_debug("non zero reserved bytes\n"); -+ return ERR_PTR(-EBADF); -+ } -+ -+ /* make sure the offsets array isn't truncated */ -+ if (table->num * sizeof(table->offset[0]) + -+ sizeof(*table) > size) { -+ pr_debug("resource table incomplete\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ return shdr; -+ } -+ -+ return NULL; -+} -+ -+/* Load the resource table from an ELF32 image */ -+int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size) -+{ -+ const struct dm_rproc_ops *ops; -+ Elf32_Shdr *shdr; -+ void *src, *dst; -+ -+ shdr = rproc_elf32_find_rsc_table(dev, fw_addr, fw_size); -+ if (!shdr) -+ return -ENODATA; -+ if (IS_ERR(shdr)) -+ return PTR_ERR(shdr); -+ -+ ops = rproc_get_ops(dev); -+ *rsc_addr = (ulong)shdr->sh_addr; -+ *rsc_size = (ulong)shdr->sh_size; -+ -+ src = (void *)fw_addr + shdr->sh_offset; -+ if (ops->device_to_virt) -+ dst = (void *)ops->device_to_virt(dev, *rsc_addr, *rsc_size); -+ else -+ dst = (void *)rsc_addr; -+ -+ dev_dbg(dev, "Loading resource table to 0x%8lx (%ld bytes)\n", -+ (ulong)dst, *rsc_size); -+ -+ memcpy(dst, src, *rsc_size); -+ flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), -+ roundup((unsigned long)dst + *rsc_size, -+ ARCH_DMA_MINALIGN) - -+ rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); -+ -+ return 0; -+} -+ -+/* -+ * Search for the resource table in an ELF64 image. -+ * Returns the address of the resource table section if found, NULL if there is -+ * no resource table section, or error pointer. -+ */ -+static Elf64_Shdr *rproc_elf64_find_rsc_table(struct udevice *dev, -+ ulong fw_addr, ulong fw_size) -+{ -+ int ret; -+ unsigned int i; -+ const char *name_table; -+ struct resource_table *table; -+ const u8 *elf_data = (void *)fw_addr; -+ Elf64_Ehdr *ehdr = (Elf64_Ehdr *)fw_addr; -+ Elf64_Shdr *shdr; -+ -+ ret = rproc_elf64_sanity_check(fw_addr, fw_size); -+ if (ret) { -+ pr_debug("Invalid ELF64 Image %d\n", ret); -+ return ERR_PTR(ret); -+ } -+ -+ /* look for the resource table and handle it */ -+ shdr = (Elf64_Shdr *)(elf_data + ehdr->e_shoff); -+ name_table = (const char *)(elf_data + -+ shdr[ehdr->e_shstrndx].sh_offset); -+ -+ for (i = 0; i < ehdr->e_shnum; i++, shdr++) { -+ u64 size = shdr->sh_size; -+ u64 offset = shdr->sh_offset; -+ -+ if (strcmp(name_table + shdr->sh_name, ".resource_table")) -+ continue; -+ -+ table = (struct resource_table *)(elf_data + offset); -+ -+ /* make sure we have the entire table */ -+ if (offset + size > fw_size) { -+ pr_debug("resource table truncated\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ /* make sure table has at least the header */ -+ if (sizeof(*table) > size) { -+ pr_debug("header-less resource table\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ /* we don't support any version beyond the first */ -+ if (table->ver != 1) { -+ pr_debug("unsupported fw ver: %d\n", table->ver); -+ return ERR_PTR(-EPROTONOSUPPORT); -+ } -+ -+ /* make sure reserved bytes are zeroes */ -+ if (table->reserved[0] || table->reserved[1]) { -+ pr_debug("non zero reserved bytes\n"); -+ return ERR_PTR(-EBADF); -+ } -+ -+ /* make sure the offsets array isn't truncated */ -+ if (table->num * sizeof(table->offset[0]) + -+ sizeof(*table) > size) { -+ pr_debug("resource table incomplete\n"); -+ return ERR_PTR(-ENOSPC); -+ } -+ -+ return shdr; -+ } -+ -+ return NULL; -+} -+ -+/* Load the resource table from an ELF64 image */ -+int rproc_elf64_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size) -+{ -+ const struct dm_rproc_ops *ops; -+ Elf64_Shdr *shdr; -+ void *src, *dst; -+ -+ shdr = rproc_elf64_find_rsc_table(dev, fw_addr, fw_size); -+ if (!shdr) -+ return -ENODATA; -+ if (IS_ERR(shdr)) -+ return PTR_ERR(shdr); -+ -+ ops = rproc_get_ops(dev); -+ *rsc_addr = (ulong)shdr->sh_addr; -+ *rsc_size = (ulong)shdr->sh_size; -+ -+ src = (void *)fw_addr + shdr->sh_offset; -+ if (ops->device_to_virt) -+ dst = (void *)ops->device_to_virt(dev, *rsc_addr, *rsc_size); -+ else -+ dst = (void *)rsc_addr; -+ -+ dev_dbg(dev, "Loading resource table to 0x%8lx (%ld bytes)\n", -+ (ulong)dst, *rsc_size); -+ -+ memcpy(dst, src, *rsc_size); -+ flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), -+ roundup((unsigned long)dst + *rsc_size, -+ ARCH_DMA_MINALIGN) - -+ rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); -+ -+ return 0; -+} -+ -+/* Load the resource table from an ELF32 or ELF64 image */ -+int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size) -+ -+{ -+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)fw_addr; -+ -+ if (!fw_addr) -+ return -EFAULT; -+ -+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64) -+ return rproc_elf64_load_rsc_table(dev, fw_addr, fw_size, -+ rsc_addr, rsc_size); -+ else -+ return rproc_elf32_load_rsc_table(dev, fw_addr, fw_size, -+ rsc_addr, rsc_size); -+} -diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c -index 40bba37..b8e62e5 100644 ---- a/drivers/remoteproc/stm32_copro.c -+++ b/drivers/remoteproc/stm32_copro.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #define RCC_GCR_HOLD_BOOT 0 - #define RCC_GCR_RELEASE_BOOT 1 -@@ -22,14 +23,16 @@ - * @hold_boot_regmap: regmap for remote processor reset hold boot - * @hold_boot_offset: offset of the register controlling the hold boot setting - * @hold_boot_mask: bitmask of the register for the hold boot field -- * @is_running: is the remote processor running -+ * @secured_soc: TZEN flag (register protection) -+ * @rsc_table_addr: resource table address - */ - struct stm32_copro_privdata { - struct reset_ctl reset_ctl; - struct regmap *hold_boot_regmap; - uint hold_boot_offset; - uint hold_boot_mask; -- bool is_running; -+ bool secured_soc; -+ ulong rsc_table_addr; - }; - - /** -@@ -42,6 +45,7 @@ static int stm32_copro_probe(struct udevice *dev) - struct stm32_copro_privdata *priv; - struct regmap *regmap; - const fdt32_t *cell; -+ uint tz_offset, tz_mask, tzen; - int len, ret; - - priv = dev_get_priv(dev); -@@ -69,6 +73,31 @@ static int stm32_copro_probe(struct udevice *dev) - return ret; - } - -+ regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-tz"); -+ if (IS_ERR(regmap)) { -+ dev_dbg(dev, "unable to find tz regmap (%ld)\n", -+ PTR_ERR(regmap)); -+ return -EINVAL; -+ } -+ -+ cell = dev_read_prop(dev, "st,syscfg-tz", &len); -+ if (3 * sizeof(fdt32_t) - len > 0) { -+ dev_dbg(dev, "tz offset and mask not available\n"); -+ return -EINVAL; -+ } -+ -+ tz_offset = fdtdec_get_number(cell + 1, 1); -+ -+ tz_mask = fdtdec_get_number(cell + 2, 1); -+ -+ ret = regmap_read(regmap, tz_offset, &tzen); -+ if (ret) { -+ dev_dbg(dev, "failed to read soc secure state\n"); -+ return ret; -+ } -+ -+ priv->secured_soc = !!(tzen & tz_mask); -+ - dev_dbg(dev, "probed\n"); - - return 0; -@@ -90,6 +119,11 @@ static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold) - - val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT; - -+ if (priv->secured_soc) { -+ return stm32_smc_exec(STM32_SMC_RCC, STM32_SMC_REG_WRITE, -+ priv->hold_boot_offset, val); -+ } -+ - /* - * Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured. - * To be updated when the code for this SMC service is available which -@@ -141,6 +175,7 @@ static void *stm32_copro_device_to_virt(struct udevice *dev, ulong da, - static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) - { - struct stm32_copro_privdata *priv; -+ ulong rsc_table_size; - int ret; - - priv = dev_get_priv(dev); -@@ -155,6 +190,12 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) - return ret; - } - -+ if (rproc_elf32_load_rsc_table(dev, addr, size, &priv->rsc_table_addr, -+ &rsc_table_size)) { -+ priv->rsc_table_addr = 0; -+ dev_warn(dev, "No valid resource table for this firmware\n"); -+ } -+ - return rproc_elf32_load_image(dev, addr, size); - } - -@@ -180,7 +221,12 @@ static int stm32_copro_start(struct udevice *dev) - * rebooting autonomously - */ - ret = stm32_copro_set_hold_boot(dev, true); -- priv->is_running = !ret; -+ writel(ret ? TAMP_COPRO_STATE_OFF : TAMP_COPRO_STATE_CRUN, -+ TAMP_COPRO_STATE); -+ if (!ret) -+ /* Store rsc_address in bkp register */ -+ writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); -+ - return ret; - } - -@@ -206,7 +252,7 @@ static int stm32_copro_reset(struct udevice *dev) - return ret; - } - -- priv->is_running = false; -+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); - - return 0; - } -@@ -224,14 +270,11 @@ static int stm32_copro_stop(struct udevice *dev) - /** - * stm32_copro_is_running() - Is the STM32 remote processor running - * @dev: corresponding STM32 remote processor device -- * @return 1 if the remote processor is running, 0 otherwise -+ * @return 0 if the remote processor is running, 1 otherwise - */ - static int stm32_copro_is_running(struct udevice *dev) - { -- struct stm32_copro_privdata *priv; -- -- priv = dev_get_priv(dev); -- return priv->is_running; -+ return (readl(TAMP_COPRO_STATE) == TAMP_COPRO_STATE_OFF); - } - - static const struct dm_rproc_ops stm32_copro_ops = { -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 75ccd65..4c92c49 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -148,4 +148,12 @@ config RESET_IMX7 - help - Support for reset controller on i.MX7/8 SoCs. - -+config RESET_SCMI -+ bool "Enable SCMI reset domain driver" -+ select SCMI_AGENT -+ help -+ Enable this option if you want to support reset controller -+ devices exposed by a SCMI agent based on SCMI reset domain -+ protocol communication with a SCMI server. -+ - endmenu -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index 0a044d5..1ce9760 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o - obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o - obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o - obj-$(CONFIG_RESET_IMX7) += reset-imx7.o -+obj-$(CONFIG_RESET_SCMI) += reset-scmi.o -diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c -new file mode 100644 -index 0000000..8f4c895 ---- /dev/null -+++ b/drivers/reset/reset-scmi.c -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Linaro Limited -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum scmi_reset_domain_message_id { -+ SCMI_RESET_DOMAIN_RESET = 0x4, -+}; -+ -+#define SCMI_RD_RESET_FLAG_ASSERT BIT(1) -+#define SCMI_RD_RESET_FLAG_DEASSERT 0 -+ -+struct scmi_rd_reset_in { -+ u32 domain_id; -+ u32 flags; -+ u32 reset_state; -+}; -+ -+struct scmi_rd_reset_out { -+ s32 status; -+}; -+ -+static int scmi_reset_set_state(struct reset_ctl *rst, int assert_not_deassert) -+{ -+ struct scmi_rd_reset_in in = { -+ .domain_id = rst->id, -+ .flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : -+ SCMI_RD_RESET_FLAG_DEASSERT, -+ .reset_state = 0, -+ }; -+ struct scmi_rd_reset_out out; -+ struct scmi_msg scmi_msg = { -+ .protocol_id = SCMI_PROTOCOL_ID_RESET_DOMAIN, -+ .message_id = SCMI_RESET_DOMAIN_RESET, -+ .in_msg = (u8 *)&in, -+ .in_msg_sz = sizeof(in), -+ .out_msg = (u8 *)&out, -+ .out_msg_sz = sizeof(out), -+ }; -+ int rc; -+ -+ rc = scmi_agent_process_msg(rst->dev->parent, &scmi_msg); -+ if (rc) -+ return rc; -+ -+ return scmi_to_linux_errno(out.status); -+} -+ -+static int scmi_reset_assert(struct reset_ctl *rst) -+{ -+ return scmi_reset_set_state(rst, SCMI_RD_RESET_FLAG_ASSERT); -+} -+ -+static int scmi_reset_deassert(struct reset_ctl *rst) -+{ -+ return scmi_reset_set_state(rst, SCMI_RD_RESET_FLAG_DEASSERT); -+} -+ -+static int scmi_reset_request(struct reset_ctl *reset_ctl) -+{ -+ return 0; -+} -+ -+static int scmi_reset_free(struct reset_ctl *reset_ctl) -+{ -+ return 0; -+} -+ -+static const struct reset_ops scmi_reset_domain_ops = { -+ .request = scmi_reset_request, -+ .free = scmi_reset_free, -+ .rst_assert = scmi_reset_assert, -+ .rst_deassert = scmi_reset_deassert, -+}; -+ -+U_BOOT_DRIVER(scmi_reset_domain) = { -+ .name = "scmi_reset_domain", -+ .id = UCLASS_RESET, -+ .ops = &scmi_reset_domain_ops, -+}; -diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c -index 7f870f2..8a0009b 100644 ---- a/drivers/tee/optee/core.c -+++ b/drivers/tee/optee/core.c -@@ -510,7 +510,7 @@ static bool is_optee_api(optee_invoke_fn *invoke_fn) - res.a2 == OPTEE_MSG_UID_2 && res.a3 == OPTEE_MSG_UID_3; - } - --static void print_os_revision(optee_invoke_fn *invoke_fn) -+static void print_os_revision(struct udevice *dev, optee_invoke_fn *invoke_fn) - { - union { - struct arm_smccc_res smccc; -@@ -525,11 +525,12 @@ static void print_os_revision(optee_invoke_fn *invoke_fn) - &res.smccc); - - if (res.result.build_id) -- debug("OP-TEE revision %lu.%lu (%08lx)\n", res.result.major, -- res.result.minor, res.result.build_id); -+ dev_info(dev, "OP-TEE: revision %lu.%lu (%08lx)\n", -+ res.result.major, res.result.minor, -+ res.result.build_id); - else -- debug("OP-TEE revision %lu.%lu\n", res.result.major, -- res.result.minor); -+ dev_info(dev, "OP-TEE: revision %lu.%lu\n", -+ res.result.major, res.result.minor); - } - - static bool api_revision_is_compatible(optee_invoke_fn *invoke_fn) -@@ -624,7 +625,7 @@ static int optee_probe(struct udevice *dev) - return -ENOENT; - } - -- print_os_revision(pdata->invoke_fn); -+ print_os_revision(dev, pdata->invoke_fn); - - if (!api_revision_is_compatible(pdata->invoke_fn)) { - debug("%s: OP-TEE api revision mismatch\n", __func__); -diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c -index 77c555e..988cf02 100644 ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -864,8 +864,8 @@ int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) - for (i = 0; i < count; i++) { - ret = generic_phy_init(&usb_phys[i]); - if (ret) { -- pr_err("Can't init USB PHY%d for %s\n", -- i, dev->name); -+ pr_debug("Can't init USB PHY%d for %s\n", -+ i, dev->name); - goto phys_init_err; - } - } -@@ -873,8 +873,8 @@ int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) - for (i = 0; i < count; i++) { - ret = generic_phy_power_on(&usb_phys[i]); - if (ret) { -- pr_err("Can't power USB PHY%d for %s\n", -- i, dev->name); -+ pr_debug("Can't power USB PHY%d for %s\n", -+ i, dev->name); - goto phys_poweron_err; - } - } -@@ -910,8 +910,8 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) - ret = generic_phy_power_off(&usb_phys[i]); - ret |= generic_phy_exit(&usb_phys[i]); - if (ret) { -- pr_err("Can't shutdown USB PHY%d for %s\n", -- i, dev->name); -+ pr_debug("Can't shutdown USB PHY%d for %s\n", -+ i, dev->name); - } - } - -diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c -index 35f4147..35495e4 100644 ---- a/drivers/usb/gadget/dwc2_udc_otg.c -+++ b/drivers/usb/gadget/dwc2_udc_otg.c -@@ -980,7 +980,7 @@ int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys) - for (i = 0; i < count; i++) { - ret = generic_phy_init(&usb_phys[i]); - if (ret) { -- dev_err(dev, "Can't init USB PHY%d for %s\n", -+ dev_dbg(dev, "Can't init USB PHY%d for %s\n", - i, dev->name); - goto phys_init_err; - } -@@ -989,7 +989,7 @@ int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys) - for (i = 0; i < count; i++) { - ret = generic_phy_power_on(&usb_phys[i]); - if (ret) { -- dev_err(dev, "Can't power USB PHY%d for %s\n", -+ dev_dbg(dev, "Can't power USB PHY%d for %s\n", - i, dev->name); - goto phys_poweron_err; - } -@@ -1027,7 +1027,7 @@ void dwc2_phy_shutdown(struct udevice *dev, struct phy *usb_phys, int num_phys) - ret = generic_phy_power_off(&usb_phys[i]); - ret |= generic_phy_exit(&usb_phys[i]); - if (ret) { -- dev_err(dev, "Can't shutdown USB PHY%d for %s\n", -+ dev_dbg(dev, "Can't shutdown USB PHY%d for %s\n", - i, dev->name); - } - } -diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c -index e9e1600..7a51b53 100644 ---- a/drivers/usb/gadget/g_dnl.c -+++ b/drivers/usb/gadget/g_dnl.c -@@ -89,6 +89,14 @@ static struct usb_gadget_strings *g_dnl_composite_strings[] = { - NULL, - }; - -+void g_dnl_set_product(const char *s) -+{ -+ if (s) -+ g_dnl_string_defs[1].s = s; -+ else -+ g_dnl_string_defs[1].s = product; -+} -+ - static int g_dnl_unbind(struct usb_composite_dev *cdev) - { - struct usb_gadget *gadget = cdev->gadget; -diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c -index b9c56f7..2fbb8b8 100644 ---- a/drivers/usb/host/dwc2.c -+++ b/drivers/usb/host/dwc2.c -@@ -5,13 +5,15 @@ - */ - - #include -+#include - #include - #include - #include --#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -36,6 +38,8 @@ struct dwc2_priv { - #ifdef CONFIG_DM_REGULATOR - struct udevice *vbus_supply; - #endif -+ struct phy phy; -+ struct clk_bulk clks; - #else - uint8_t *aligned_buffer; - uint8_t *status_buffer; -@@ -1146,6 +1150,8 @@ static int dwc2_reset(struct udevice *dev) - return ret; - } - -+ /* force reset to clear all IP register */ -+ reset_assert_bulk(&priv->resets); - ret = reset_deassert_bulk(&priv->resets); - if (ret) { - reset_release_bulk(&priv->resets); -@@ -1212,6 +1218,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) - if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) - mdelay(1000); - -+ printf("USB DWC2\n"); -+ - return 0; - } - -@@ -1321,13 +1329,113 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) - return 0; - } - -+static int dwc2_setup_phy(struct udevice *dev) -+{ -+ struct dwc2_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ ret = generic_phy_get_by_index(dev, 0, &priv->phy); -+ if (ret) { -+ if (ret == -ENOENT) -+ return 0; /* no PHY, nothing to do */ -+ dev_err(dev, "Failed to get USB PHY: %d.\n", ret); -+ return ret; -+ } -+ -+ ret = generic_phy_init(&priv->phy); -+ if (ret) { -+ dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret); -+ return ret; -+ } -+ -+ ret = generic_phy_power_on(&priv->phy); -+ if (ret) { -+ dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret); -+ generic_phy_exit(&priv->phy); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int dwc2_shutdown_phy(struct udevice *dev) -+{ -+ struct dwc2_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */ -+ if (!generic_phy_valid(&priv->phy)) -+ return 0; /* no PHY, nothing to do */ -+ -+ ret = generic_phy_power_off(&priv->phy); -+ if (ret) { -+ dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); -+ return ret; -+ } -+ -+ ret = generic_phy_exit(&priv->phy); -+ if (ret) { -+ dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int dwc2_clk_init(struct udevice *dev) -+{ -+ struct dwc2_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ ret = clk_get_bulk(dev, &priv->clks); -+ if (ret == -ENOSYS || ret == -ENOENT) -+ return 0; -+ if (ret) -+ return ret; -+ -+ ret = clk_enable_bulk(&priv->clks); -+ if (ret) { -+ clk_release_bulk(&priv->clks); -+ return ret; -+ } -+ -+ return 0; -+} -+ - static int dwc2_usb_probe(struct udevice *dev) - { - struct dwc2_priv *priv = dev_get_priv(dev); - struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); -+ int ret; - - bus_priv->desc_before_addr = true; - -+ ret = dwc2_clk_init(dev); -+ if (ret) -+ return ret; -+ -+ ret = dwc2_setup_phy(dev); -+ if (ret) -+ return ret; -+ -+ if (CONFIG_IS_ENABLED(ARCH_STM32MP) && -+ device_is_compatible(dev, "st,stm32mp1-hsotg")) { -+ struct udevice *usb33d_supply; -+ -+ ret = device_get_supply_regulator(dev, "usb33d-supply", -+ &usb33d_supply); -+ if (ret) { -+ dev_err(dev, -+ "can't get voltage level detector supply\n"); -+ } else { -+ ret = regulator_set_enable(usb33d_supply, true); -+ if (ret) { -+ dev_err(dev, -+ "can't enable voltage level detector supply\n"); -+ } -+ } -+ } -+ - return dwc2_init_common(dev, priv); - } - -@@ -1340,9 +1448,17 @@ static int dwc2_usb_remove(struct udevice *dev) - if (ret) - return ret; - -+ ret = dwc2_shutdown_phy(dev); -+ if (ret) { -+ dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret); -+ return ret; -+ } -+ - dwc2_uninit_common(priv->regs); - - reset_release_bulk(&priv->resets); -+ clk_disable_bulk(&priv->clks); -+ clk_release_bulk(&priv->clks); - - return 0; - } -diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c -index ef20c3c..0c31775 100644 ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -1698,13 +1698,13 @@ int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index) - } else { - ret = generic_phy_init(phy); - if (ret) { -- dev_err(dev, "failed to init usb phy\n"); -+ dev_dbg(dev, "failed to init usb phy\n"); - return ret; - } - - ret = generic_phy_power_on(phy); - if (ret) { -- dev_err(dev, "failed to power on usb phy\n"); -+ dev_dbg(dev, "failed to power on usb phy\n"); - return generic_phy_exit(phy); - } - } -@@ -1722,13 +1722,13 @@ int ehci_shutdown_phy(struct udevice *dev, struct phy *phy) - if (generic_phy_valid(phy)) { - ret = generic_phy_power_off(phy); - if (ret) { -- dev_err(dev, "failed to power off usb phy\n"); -+ dev_dbg(dev, "failed to power off usb phy\n"); - return ret; - } - - ret = generic_phy_exit(phy); - if (ret) { -- dev_err(dev, "failed to power off usb phy\n"); -+ dev_dbg(dev, "failed to power off usb phy\n"); - return ret; - } - } -diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c -index 916ea0b..e8cf26a 100644 ---- a/drivers/usb/host/ohci-generic.c -+++ b/drivers/usb/host/ohci-generic.c -@@ -38,13 +38,13 @@ static int ohci_setup_phy(struct udevice *dev, int index) - } else { - ret = generic_phy_init(&priv->phy); - if (ret) { -- dev_err(dev, "failed to init usb phy\n"); -+ dev_dbg(dev, "failed to init usb phy\n"); - return ret; - } - - ret = generic_phy_power_on(&priv->phy); - if (ret) { -- dev_err(dev, "failed to power on usb phy\n"); -+ dev_dbg(dev, "failed to power on usb phy\n"); - return generic_phy_exit(&priv->phy); - } - } -@@ -60,13 +60,13 @@ static int ohci_shutdown_phy(struct udevice *dev) - if (generic_phy_valid(&priv->phy)) { - ret = generic_phy_power_off(&priv->phy); - if (ret) { -- dev_err(dev, "failed to power off usb phy\n"); -+ dev_dbg(dev, "failed to power off usb phy\n"); - return ret; - } - - ret = generic_phy_exit(&priv->phy); - if (ret) { -- dev_err(dev, "failed to power off usb phy\n"); -+ dev_dbg(dev, "failed to power off usb phy\n"); - return ret; - } - } -diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c -index 45eecfe..3b36ab3 100644 ---- a/drivers/usb/musb-new/sunxi.c -+++ b/drivers/usb/musb-new/sunxi.c -@@ -252,7 +252,7 @@ static int sunxi_musb_enable(struct musb *musb) - - ret = generic_phy_power_on(&glue->phy); - if (ret) { -- pr_err("failed to power on USB PHY\n"); -+ pr_debug("failed to power on USB PHY\n"); - return ret; - } - } -@@ -276,7 +276,7 @@ static void sunxi_musb_disable(struct musb *musb) - if (is_host_enabled(musb)) { - ret = generic_phy_power_off(&glue->phy); - if (ret) { -- pr_err("failed to power off USB PHY\n"); -+ pr_debug("failed to power off USB PHY\n"); - return; - } - } -@@ -310,7 +310,7 @@ static int sunxi_musb_init(struct musb *musb) - - ret = generic_phy_init(&glue->phy); - if (ret) { -- dev_err(dev, "failed to init USB PHY\n"); -+ dev_dbg(dev, "failed to init USB PHY\n"); - goto err_rst; - } - -@@ -347,7 +347,7 @@ static int sunxi_musb_exit(struct musb *musb) - if (generic_phy_valid(&glue->phy)) { - ret = generic_phy_exit(&glue->phy); - if (ret) { -- dev_err(dev, "failed to power off usb phy\n"); -+ dev_dbg(dev, "failed to power off usb phy\n"); - return ret; - } - } -diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c -index 89d9cfd..629bf76 100644 ---- a/drivers/video/orisetech_otm8009a.c -+++ b/drivers/video/orisetech_otm8009a.c -@@ -60,9 +60,6 @@ - struct otm8009a_panel_priv { - struct udevice *reg; - struct gpio_desc reset; -- unsigned int lanes; -- enum mipi_dsi_pixel_format format; -- unsigned long mode_flags; - }; - - static const struct display_timing default_timing = { -@@ -291,17 +288,8 @@ static int otm8009a_panel_enable_backlight(struct udevice *dev) - static int otm8009a_panel_get_display_timing(struct udevice *dev, - struct display_timing *timings) - { -- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); -- struct mipi_dsi_device *device = plat->device; -- struct otm8009a_panel_priv *priv = dev_get_priv(dev); -- - memcpy(timings, &default_timing, sizeof(*timings)); - -- /* fill characteristics of DSI data link */ -- device->lanes = priv->lanes; -- device->format = priv->format; -- device->mode_flags = priv->mode_flags; -- - return 0; - } - -@@ -333,6 +321,7 @@ static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev) - static int otm8009a_panel_probe(struct udevice *dev) - { - struct otm8009a_panel_priv *priv = dev_get_priv(dev); -+ struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); - int ret; - - if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) { -@@ -348,9 +337,10 @@ static int otm8009a_panel_probe(struct udevice *dev) - dm_gpio_set_value(&priv->reset, false); - mdelay(10); /* >5ms */ - -- priv->lanes = 2; -- priv->format = MIPI_DSI_FMT_RGB888; -- priv->mode_flags = MIPI_DSI_MODE_VIDEO | -+ /* fill characteristics of DSI data link */ -+ plat->lanes = 2; -+ plat->format = MIPI_DSI_FMT_RGB888; -+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM; - -diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c -index 91555e2..76b0ed2 100644 ---- a/drivers/video/raydium-rm68200.c -+++ b/drivers/video/raydium-rm68200.c -@@ -73,9 +73,6 @@ struct rm68200_panel_priv { - struct udevice *reg; - struct udevice *backlight; - struct gpio_desc reset; -- unsigned int lanes; -- enum mipi_dsi_pixel_format format; -- unsigned long mode_flags; - }; - - static const struct display_timing default_timing = { -@@ -257,17 +254,8 @@ static int rm68200_panel_enable_backlight(struct udevice *dev) - static int rm68200_panel_get_display_timing(struct udevice *dev, - struct display_timing *timings) - { -- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); -- struct mipi_dsi_device *device = plat->device; -- struct rm68200_panel_priv *priv = dev_get_priv(dev); -- - memcpy(timings, &default_timing, sizeof(*timings)); - -- /* fill characteristics of DSI data link */ -- device->lanes = priv->lanes; -- device->format = priv->format; -- device->mode_flags = priv->mode_flags; -- - return 0; - } - -@@ -306,6 +294,7 @@ static int rm68200_panel_ofdata_to_platdata(struct udevice *dev) - static int rm68200_panel_probe(struct udevice *dev) - { - struct rm68200_panel_priv *priv = dev_get_priv(dev); -+ struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev); - int ret; - - if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) { -@@ -320,9 +309,10 @@ static int rm68200_panel_probe(struct udevice *dev) - dm_gpio_set_value(&priv->reset, false); - mdelay(10); - -- priv->lanes = 2; -- priv->format = MIPI_DSI_FMT_RGB888; -- priv->mode_flags = MIPI_DSI_MODE_VIDEO | -+ /* fill characteristics of DSI data link */ -+ plat->lanes = 2; -+ plat->format = MIPI_DSI_FMT_RGB888; -+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM; - -diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c -index 12895a8..022ae96 100644 ---- a/drivers/video/stm32/stm32_dsi.c -+++ b/drivers/video/stm32/stm32_dsi.c -@@ -268,7 +268,6 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, - u32 val; - - /* Update lane capabilities according to hw version */ -- dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; - dsi->lane_min_kbps = LANE_MIN_KBPS; - dsi->lane_max_kbps = LANE_MAX_KBPS; - if (dsi->hw_version == HWVER_131) { -@@ -351,6 +350,9 @@ static int stm32_dsi_attach(struct udevice *dev) - - mplat = dev_get_platdata(priv->panel); - mplat->device = &priv->device; -+ device->lanes = mplat->lanes; -+ device->format = mplat->format; -+ device->mode_flags = mplat->mode_flags; - - ret = panel_get_display_timing(priv->panel, &timings); - if (ret) { -@@ -472,6 +474,17 @@ static int stm32_dsi_probe(struct udevice *dev) - /* Reset */ - reset_deassert(&rst); - -+ /* check hardware version */ -+ priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION; -+ if (priv->hw_version != HWVER_130 && -+ priv->hw_version != HWVER_131) { -+ dev_err(dev, "bad dsi hardware version\n"); -+ clk_disable(&clk); -+ if (IS_ENABLED(CONFIG_DM_REGULATOR)) -+ regulator_set_enable(priv->vdd_reg, false); -+ return -ENODEV; -+ } -+ - return 0; - err_clk: - clk_disable(&clk); -diff --git a/env/mmc.c b/env/mmc.c -index b24c35c..f64c993 100644 ---- a/env/mmc.c -+++ b/env/mmc.c -@@ -24,14 +24,25 @@ - - DECLARE_GLOBAL_DATA_PTR; - -+#if !defined(CONFIG_SYS_MMC_ENV_DEV) -+#define CONFIG_SYS_MMC_ENV_DEV 0 -+#endif -+ -+__weak int mmc_get_env_dev(void) -+{ -+ return CONFIG_SYS_MMC_ENV_DEV; -+} -+ - #if CONFIG_IS_ENABLED(OF_CONTROL) --static inline int mmc_offset_try_partition(const char *str, s64 *val) -+static inline int mmc_offset_try_partition(const char *str, int copy, s64 *val) - { - disk_partition_t info; - struct blk_desc *desc; - int len, i, ret; -+ char dev_str[4]; - -- ret = blk_get_device_by_str("mmc", STR(CONFIG_SYS_MMC_ENV_DEV), &desc); -+ snprintf(dev_str, sizeof(dev_str), "%d", mmc_get_env_dev()); -+ ret = blk_get_device_by_str("mmc", dev_str, &desc); - if (ret < 0) - return (ret); - -@@ -45,10 +56,10 @@ static inline int mmc_offset_try_partition(const char *str, s64 *val) - } - - /* round up to info.blksz */ -- len = (CONFIG_ENV_SIZE + info.blksz - 1) & ~(info.blksz - 1); -+ len = DIV_ROUND_UP(CONFIG_ENV_SIZE, info.blksz); - - /* use the top of the partion for the environment */ -- *val = (info.start + info.size - 1) - len / info.blksz; -+ *val = (info.start + info.size - (1 + copy) * len) * info.blksz; - - return 0; - } -@@ -73,7 +84,7 @@ static inline s64 mmc_offset(int copy) - str = fdtdec_get_config_string(gd->fdt_blob, dt_prop.partition); - if (str) { - /* try to place the environment at end of the partition */ -- err = mmc_offset_try_partition(str, &val); -+ err = mmc_offset_try_partition(str, copy, &val); - if (!err) - return val; - } -@@ -114,11 +125,6 @@ __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) - return 0; - } - --__weak int mmc_get_env_dev(void) --{ -- return CONFIG_SYS_MMC_ENV_DEV; --} -- - #ifdef CONFIG_SYS_MMC_ENV_PART - __weak uint mmc_get_env_part(struct mmc *mmc) - { -diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h -index d6cf187..ec48770 100644 ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -117,11 +117,14 @@ struct udevice; - struct gpio_desc { - struct udevice *dev; /* Device, NULL for invalid GPIO */ - unsigned long flags; --#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ --#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ --#define GPIOD_IS_IN (1 << 2) /* GPIO is an input */ --#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ --#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ -+#define GPIOD_IS_OUT BIT(1) /* GPIO is an output */ -+#define GPIOD_IS_IN BIT(2) /* GPIO is an input */ -+#define GPIOD_ACTIVE_LOW BIT(3) /* GPIO is active when value is low */ -+#define GPIOD_IS_OUT_ACTIVE BIT(4) /* set output active */ -+#define GPIOD_OPEN_DRAIN BIT(5) /* GPIO is open drain type */ -+#define GPIOD_OPEN_SOURCE BIT(6) /* GPIO is open source type */ -+#define GPIOD_PULL_UP BIT(7) /* GPIO has pull-up enabled */ -+#define GPIOD_PULL_DOWN BIT(8) /* GPIO has pull-down enabled */ - - uint offset; /* GPIO offset within the device */ - /* -@@ -130,6 +133,12 @@ struct gpio_desc { - */ - }; - -+/* helper to compute the value of the gpio output */ -+#define GPIOD_FLAGS_OUTPUT_MASK (GPIOD_ACTIVE_LOW | GPIOD_IS_OUT_ACTIVE) -+#define GPIOD_FLAGS_OUTPUT(flags) \ -+ (((((flags) & GPIOD_FLAGS_OUTPUT_MASK) == GPIOD_IS_OUT_ACTIVE) || \ -+ (((flags) & GPIOD_FLAGS_OUTPUT_MASK) == GPIOD_ACTIVE_LOW))) -+ - /** - * dm_gpio_is_valid() - Check if a GPIO is valid - * -@@ -254,8 +263,6 @@ struct dm_gpio_ops { - int value); - int (*get_value)(struct udevice *dev, unsigned offset); - int (*set_value)(struct udevice *dev, unsigned offset, int value); -- int (*get_open_drain)(struct udevice *dev, unsigned offset); -- int (*set_open_drain)(struct udevice *dev, unsigned offset, int value); - /** - * get_function() Get the GPIO function - * -@@ -290,6 +297,37 @@ struct dm_gpio_ops { - */ - int (*xlate)(struct udevice *dev, struct gpio_desc *desc, - struct ofnode_phandle_args *args); -+ -+ /** -+ * set_dir_flags() - Set GPIO dir flags -+ * -+ * This function should set up the GPIO configuration according to the -+ * information provide by the direction flags bitfield. -+ * -+ * This method is optional. -+ * -+ * @dev: GPIO device -+ * @offset: GPIO offset within that device -+ * @flags: GPIO configuration to use -+ * @return 0 if OK, -ve on error -+ */ -+ int (*set_dir_flags)(struct udevice *dev, unsigned int offset, -+ ulong flags); -+ -+ /** -+ * get_dir_flags() - Get GPIO dir flags -+ * -+ * This function return the GPIO direction flags used. -+ * -+ * This method is optional. -+ * -+ * @dev: GPIO device -+ * @offset: GPIO offset within that device -+ * @flags: place to put the used direction flags by GPIO -+ * @return 0 if OK, -ve on error -+ */ -+ int (*get_dir_flags)(struct udevice *dev, unsigned int offset, -+ ulong *flags); - }; - - /** -@@ -587,63 +625,41 @@ int dm_gpio_get_value(const struct gpio_desc *desc); - int dm_gpio_set_value(const struct gpio_desc *desc, int value); - - /** -- * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active -- * -- * This checks if open-drain-mode for a GPIO is enabled or not. This method is -- * optional. -- * -- * @desc: GPIO description containing device, offset and flags, -- * previously returned by gpio_request_by_name() -- * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or -- * -ve on error -- */ --int dm_gpio_get_open_drain(struct gpio_desc *desc); -- --/** -- * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off -- * -- * This enables or disables open-drain mode for a GPIO. This method is -- * optional; if the driver does not support it, nothing happens when the method -- * is called. -+ * dm_gpio_set_dir() - Set the direction for a GPIO - * -- * In open-drain mode, instead of actively driving the output (Push-pull -- * output), the GPIO's pin is connected to the collector (for a NPN transistor) -- * or the drain (for a MOSFET) of a transistor, respectively. The pin then -- * either forms an open circuit or a connection to ground, depending on the -- * state of the transistor. -+ * This sets up the direction according to the GPIO flags: desc->flags. - * - * @desc: GPIO description containing device, offset and flags, - * previously returned by gpio_request_by_name() - * @return 0 if OK, -ve on error - */ --int dm_gpio_set_open_drain(struct gpio_desc *desc, int value); -+int dm_gpio_set_dir(struct gpio_desc *desc); - - /** -- * dm_gpio_set_dir() - Set the direction for a GPIO -+ * dm_gpio_set_dir_flags() - Set direction using description and added flags - * -- * This sets up the direction according tot the provided flags. It will do -- * nothing unless the direction is actually specified. -+ * This sets up the direction according to the provided flags and the GPIO -+ * description (desc->flags) which include direction information. -+ * Note that desc->flags is updated by this function. - * - * @desc: GPIO description containing device, offset and flags, - * previously returned by gpio_request_by_name() -- * @return 0 if OK, -ve on error -+ * @flags: New flags to use -+ * @return 0 if OK, -ve on error, in which case desc->flags is not updated - */ --int dm_gpio_set_dir(struct gpio_desc *desc); -+int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); - - /** -- * dm_gpio_set_dir_flags() - Set direction using specific flags -+ * dm_gpio_get_dir_flags() - Get direction flags - * -- * This is like dm_gpio_set_dir() except that the flags value is provided -- * instead of being used from desc->flags. This is needed because in many -- * cases the GPIO description does not include direction information. -- * Note that desc->flags is updated by this function. -+ * read the current direction flags - * - * @desc: GPIO description containing device, offset and flags, - * previously returned by gpio_request_by_name() -- * @flags: New flags to use -+ * @flags: place to put the used flags - * @return 0 if OK, -ve on error, in which case desc->flags is not updated - */ --int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); -+int dm_gpio_get_dir_flags(struct gpio_desc *desc, ulong *flags); - - /** - * gpio_get_number() - Get the global GPIO number of a GPIO -diff --git a/include/clk.h b/include/clk.h -index a5ee53d..950b5da 100644 ---- a/include/clk.h -+++ b/include/clk.h -@@ -9,6 +9,7 @@ - #define _CLK_H_ - - #include -+#include - #include - #include - -@@ -221,6 +222,8 @@ static inline int clk_get_by_index(struct udevice *dev, int index, - - static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) - { -+ if (bulk) -+ bulk->count = 0; - return -ENOSYS; - } - -@@ -272,6 +275,7 @@ static inline int clk_release_bulk(struct clk_bulk *bulk) - return clk_release_all(bulk->clks, bulk->count); - } - -+#if CONFIG_IS_ENABLED(CLK) - /** - * clk_request - Request a clock by provider-specific ID. - * -@@ -393,19 +397,6 @@ int clk_disable_bulk(struct clk_bulk *bulk); - */ - bool clk_is_match(const struct clk *p, const struct clk *q); - --int soc_clk_dump(void); -- --/** -- * clk_valid() - check if clk is valid -- * -- * @clk: the clock to check -- * @return true if valid, or false -- */ --static inline bool clk_valid(struct clk *clk) --{ -- return clk && !!clk->dev; --} -- - /** - * clk_get_by_id() - Get the clock by its ID - * -@@ -425,6 +416,93 @@ int clk_get_by_id(ulong id, struct clk **clkp); - * @return true on binded, or false on no - */ - bool clk_dev_binded(struct clk *clk); -+ -+#else /* CONFIG_IS_ENABLED(CLK) */ -+ -+static inline int clk_request(struct udevice *dev, struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline int clk_free(struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline ulong clk_get_rate(struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline struct clk *clk_get_parent(struct clk *clk) -+{ -+ return ERR_PTR(-ENOSYS); -+} -+ -+static inline long long clk_get_parent_rate(struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline ulong clk_set_rate(struct clk *clk, ulong rate) -+{ -+ return -ENOSYS; -+} -+ -+static inline int clk_set_parent(struct clk *clk, struct clk *parent) -+{ -+ return -ENOSYS; -+} -+ -+static inline int clk_enable(struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline int clk_enable_bulk(struct clk_bulk *bulk) -+{ -+ return bulk && bulk->count == 0 ? 0 : -ENOSYS; -+} -+ -+static inline int clk_disable(struct clk *clk) -+{ -+ return -ENOSYS; -+} -+ -+static inline int clk_disable_bulk(struct clk_bulk *bulk) -+{ -+ return bulk && bulk->count == 0 ? 0 : -ENOSYS; -+} -+ -+static inline bool clk_is_match(const struct clk *p, const struct clk *q) -+{ -+ return false; -+} -+ -+static inline int clk_get_by_id(ulong id, struct clk **clkp) -+{ -+ return -ENOSYS; -+} -+ -+static inline bool clk_dev_binded(struct clk *clk) -+{ -+ return false; -+} -+#endif /* CONFIG_IS_ENABLED(CLK) */ -+ -+/** -+ * clk_valid() - check if clk is valid -+ * -+ * @clk: the clock to check -+ * @return true if valid, or false -+ */ -+static inline bool clk_valid(struct clk *clk) -+{ -+ return clk && !!clk->dev; -+} -+ -+int soc_clk_dump(void); -+ - #endif - - #define clk_prepare_enable(clk) clk_enable(clk) -diff --git a/include/configs/odroid.h b/include/configs/odroid.h -index 77fca32..5d78825 100644 ---- a/include/configs/odroid.h -+++ b/include/configs/odroid.h -@@ -64,7 +64,6 @@ - ""PARTS_BOOT" part 0 1;" \ - ""PARTS_ROOT" part 0 2\0" \ - --#define CONFIG_SET_DFU_ALT_INFO - #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) - - #define CONFIG_DFU_ALT_BOOT_EMMC \ -diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h -index 47c3054..564319c 100644 ---- a/include/configs/odroid_xu3.h -+++ b/include/configs/odroid_xu3.h -@@ -76,7 +76,6 @@ - - /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ - #define CONFIG_MISC_COMMON --#define CONFIG_SET_DFU_ALT_INFO - #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) - - /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ -diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h -index 4ad7dc1..8dc30be 100644 ---- a/include/configs/omap3_igep00x0.h -+++ b/include/configs/omap3_igep00x0.h -@@ -71,8 +71,6 @@ - - #endif - --#define CONFIG_SYS_MTDPARTS_RUNTIME -- - /* OneNAND config */ - #define CONFIG_USE_ONENAND_BOARD_INIT - #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h -index 7a17222..a715031 100644 ---- a/include/configs/stm32f429-evaluation.h -+++ b/include/configs/stm32f429-evaluation.h -@@ -7,6 +7,11 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - -+#include -+ -+/* For booting Linux, use the first 16MB of memory */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_16M -+ - #define CONFIG_SYS_FLASH_BASE 0x08000000 - - #define CONFIG_SYS_INIT_SP_ADDR 0x10010000 -@@ -40,12 +45,10 @@ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00008000\0" \ - "fdtfile=stm32429i-eval.dtb\0" \ -- "fdt_addr_r=0x00700000\0" \ -- "scriptaddr=0x00800000\0" \ -- "pxefile_addr_r=0x00800000\0" \ -- "fdt_high=0xffffffffffffffff\0" \ -- "initrd_high=0xffffffffffffffff\0" \ -- "ramdisk_addr_r=0x00900000\0" \ -+ "fdt_addr_r=0x00408000\0" \ -+ "scriptaddr=0x00418000\0" \ -+ "pxefile_addr_r=0x00428000\0" \ -+ "ramdisk_addr_r=0x00438000\0" \ - BOOTENV - - /* -diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h -index 463f1c4..8212fb6 100644 ---- a/include/configs/stm32f469-discovery.h -+++ b/include/configs/stm32f469-discovery.h -@@ -7,6 +7,11 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - -+#include -+ -+/* For booting Linux, use the first 12MB of memory */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M -+ - #define CONFIG_SYS_FLASH_BASE 0x08000000 - - #define CONFIG_SYS_INIT_SP_ADDR 0x10010000 -@@ -40,12 +45,10 @@ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00008000\0" \ - "fdtfile=stm32f469-disco.dtb\0" \ -- "fdt_addr_r=0x00700000\0" \ -- "scriptaddr=0x00800000\0" \ -- "pxefile_addr_r=0x00800000\0" \ -- "fdt_high=0xffffffffffffffff\0" \ -- "initrd_high=0xffffffffffffffff\0" \ -- "ramdisk_addr_r=0x00900000\0" \ -+ "fdt_addr_r=0x00408000\0" \ -+ "scriptaddr=0x00418000\0" \ -+ "pxefile_addr_r=0x00428000\0" \ -+ "ramdisk_addr_r=0x00438000\0" \ - BOOTENV - - /* -diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h -index 337b999..45343d2 100644 ---- a/include/configs/stm32f746-disco.h -+++ b/include/configs/stm32f746-disco.h -@@ -7,6 +7,11 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - -+#include -+ -+/* For booting Linux, use the first 6MB of memory */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M -+ - #define CONFIG_SYS_FLASH_BASE 0x08000000 - #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 - -@@ -48,12 +53,10 @@ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xC0008000\0" \ - "fdtfile=stm32f746-disco.dtb\0" \ -- "fdt_addr_r=0xC0500000\0" \ -- "scriptaddr=0xC0008000\0" \ -- "pxefile_addr_r=0xC0008000\0" \ -- "fdt_high=0xffffffffffffffff\0" \ -- "initrd_high=0xffffffffffffffff\0" \ -- "ramdisk_addr_r=0xC0600000\0" \ -+ "fdt_addr_r=0xC0408000\0" \ -+ "scriptaddr=0xC0418000\0" \ -+ "pxefile_addr_r=0xC0428000\0" \ -+ "ramdisk_addr_r=0xC0438000\0" \ - BOOTENV - - /* -diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h -index 74c69eb..39c93ee 100644 ---- a/include/configs/stm32h743-disco.h -+++ b/include/configs/stm32h743-disco.h -@@ -8,6 +8,10 @@ - #define __CONFIG_H - - #include -+#include -+ -+/* For booting Linux, use the first 16MB of memory */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_16M - - #define CONFIG_SYS_FLASH_BASE 0x08000000 - #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -@@ -35,12 +39,10 @@ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xD0008000\0" \ - "fdtfile=stm32h743i-disco.dtb\0" \ -- "fdt_addr_r=0xD0700000\0" \ -- "scriptaddr=0xD0800000\0" \ -- "pxefile_addr_r=0xD0800000\0" \ -- "fdt_high=0xffffffffffffffff\0" \ -- "initrd_high=0xffffffffffffffff\0" \ -- "ramdisk_addr_r=0xD0900000\0" \ -+ "fdt_addr_r=0xD0408000\0" \ -+ "scriptaddr=0xD0418000\0" \ -+ "pxefile_addr_r=0xD0428000\0" \ -+ "ramdisk_addr_r=0xD0438000\0" \ - BOOTENV - - /* -diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h -index b7c8492..8eb94c1 100644 ---- a/include/configs/stm32h743-eval.h -+++ b/include/configs/stm32h743-eval.h -@@ -8,6 +8,10 @@ - #define __CONFIG_H - - #include -+#include -+ -+/* For booting Linux, use the first 16MB of memory */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_16M - - #define CONFIG_SYS_FLASH_BASE 0x08000000 - #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -@@ -35,12 +39,10 @@ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xD0008000\0" \ - "fdtfile=stm32h743i-eval.dtb\0" \ -- "fdt_addr_r=0xD0700000\0" \ -- "scriptaddr=0xD0800000\0" \ -- "pxefile_addr_r=0xD0800000\0" \ -- "fdt_high=0xffffffffffffffff\0" \ -- "initrd_high=0xffffffffffffffff\0" \ -- "ramdisk_addr_r=0xD0900000\0" \ -+ "fdt_addr_r=0xD0408000\0" \ -+ "scriptaddr=0xD0418000\0" \ -+ "pxefile_addr_r=0xD0428000\0" \ -+ "ramdisk_addr_r=0xD0438000\0" \ - BOOTENV - - /* -diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h -index d42a786..7b4fe48 100644 ---- a/include/configs/stm32mp1.h -+++ b/include/configs/stm32mp1.h -@@ -23,27 +23,30 @@ - #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - --#ifdef CONFIG_STM32MP1_OPTEE --#define CONFIG_SYS_MEM_TOP_HIDE SZ_32M --#endif /* CONFIG_STM32MP1_OPTEE */ -- - /* - * Console I/O buffer size - */ - #define CONFIG_SYS_CBSIZE SZ_1K - - /* -- * Needed by "loadb" -+ * default load address used for command tftp, bootm , loadb, ... - */ --#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE -+#define CONFIG_LOADADDR 0xc2000000 -+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - - /* ATAGs */ - #define CONFIG_CMDLINE_TAG - #define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_INITRD_TAG - -+/* -+ * For booting Linux, use the first 256 MB of memory, since this is -+ * the maximum mapped by the Linux kernel during initialization. -+ */ -+#define CONFIG_SYS_BOOTMAPSZ SZ_256M -+ - /* Extend size of kernel image for uncompression */ --#define CONFIG_SYS_BOOTM_LEN SZ_32M -+#define CONFIG_SYS_BOOTM_LEN SZ_32M - - /* SPL support */ - #ifdef CONFIG_SPL -@@ -70,6 +73,11 @@ - #define CONFIG_SYS_NAND_ONFI_DETECTION - #define CONFIG_SYS_MAX_NAND_DEVICE 1 - -+/* SPI FLASH support */ -+#if defined(CONFIG_SPL_BUILD) -+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 -+#endif -+ - /* Ethernet need */ - #ifdef CONFIG_DWC_ETH_QOS - #define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ -@@ -78,13 +86,6 @@ - #define CONFIG_SYS_AUTOLOAD "no" - #endif - --/* Dynamic MTD partition support */ --#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) --#define CONFIG_SYS_MTDPARTS_RUNTIME --#endif -- --#define CONFIG_SET_DFU_ALT_INFO -- - #ifdef CONFIG_DM_VIDEO - #define CONFIG_VIDEO_BMP_RLE8 - #define CONFIG_BMP_16BPP -@@ -98,20 +99,44 @@ - - #if !defined(CONFIG_SPL_BUILD) - --#define BOOT_TARGET_DEVICES(func) \ -- func(MMC, mmc, 1) \ -- func(UBIFS, ubifs, 0) \ -- func(MMC, mmc, 0) \ -- func(MMC, mmc, 2) \ -- func(PXE, pxe, na) -+#ifdef CONFIG_CMD_MMC -+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) -+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) -+#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2) -+#else -+#define BOOT_TARGET_MMC0(func) -+#define BOOT_TARGET_MMC1(func) -+#define BOOT_TARGET_MMC2(func) -+#endif -+ -+#ifdef CONFIG_NET -+#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -+#else -+#define BOOT_TARGET_PXE(func) -+#endif -+ -+#ifdef CONFIG_CMD_UBIFS -+#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0) -+#else -+#define BOOT_TARGET_UBIFS(func) -+#endif -+ -+#define BOOT_TARGET_DEVICES(func) \ -+ BOOT_TARGET_MMC1(func) \ -+ BOOT_TARGET_UBIFS(func) \ -+ BOOT_TARGET_MMC0(func) \ -+ BOOT_TARGET_MMC2(func) \ -+ BOOT_TARGET_PXE(func) - - /* - * bootcmd for stm32mp1: -+ * CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" - * for serial/usb: execute the stm32prog command - * for mmc boot (eMMC, SD card), boot only on the same device -- * for nand boot, boot with on ubifs partition on nand -- * for nor boot, use the default order -+ * for nand or spi-nand boot, boot with on ubifs partition on UBI partition -+ * for nor boot, use SD card = mmc0 - */ -+ - #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ - "echo \"Boot over ${boot_device}${boot_instance}!\";" \ - "if test ${boot_device} = serial || test ${boot_device} = usb;" \ -@@ -120,65 +145,86 @@ - "run env_check;" \ - "if test ${boot_device} = mmc;" \ - "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ -- "if test ${boot_device} = nand;" \ -+ "if test ${boot_device} = nand ||" \ -+ " test ${boot_device} = spi-nand ;" \ - "then env set boot_targets ubifs0; fi;" \ -+ "if test ${boot_device} = nor;" \ -+ "then env set boot_targets mmc0; fi;" \ - "run distro_bootcmd;" \ - "fi;\0" - --#include -+/* DTIMG command added only for Android distribution */ -+#ifdef CONFIG_CMD_DTIMG -+/* -+ * bootcmd for android on MMC: -+ * CONFIG_BOOTCOMMAND="run bootcmd_android" -+ * overidde DISTRO script "mmc_boot" to boot android on mmc -+ * using system_${suffix} partition (with "_a") by default -+ * - display splash screen -+ * - load device tree form dtimg -+ * - load kernel and set bootargs -+ * - start kernel -+ */ - --#ifdef CONFIG_STM32MP1_OPTEE --/* with OPTEE: define specific MTD partitions = teeh, teed, teex */ --#define STM32MP_MTDPARTS \ -- "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \ -- "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0" \ -- "mtdparts_spi-nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),"\ -- "512k(teeh),512k(teed),512k(teex),-(UBI)\0" -- --#else /* CONFIG_STM32MP1_OPTEE */ --#define STM32MP_MTDPARTS \ -- "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \ -- "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" \ -- "mtdparts_spi-nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" -- --#endif /* CONFIG_STM32MP1_OPTEE */ -- --#ifndef CONFIG_SYS_MTDPARTS_RUNTIME --#undef STM32MP_MTDPARTS --#define STM32MP_MTDPARTS --#endif -+#define STM32MP_ANDROID \ -+ "suffix=a\0" \ -+ "dtimg_addr=0xc4500000\0" \ -+ "android_mmc_splash="\ -+ "if part start mmc ${devnum} splash splash_start && " \ -+ "part size mmc ${devnum} splash splash_size;"\ -+ "then " \ -+ "mmc read ${splashimage} ${splash_start} ${splash_size};" \ -+ "cls; bmp display ${splashimage} m m;" \ -+ "fi\0" \ -+ "android_mmc_fdt="\ -+ "if part start mmc ${devnum} dt_${suffix} dt_start &&" \ -+ "part size mmc ${devnum} dt_${suffix} dt_size;"\ -+ "then " \ -+ "mmc read ${dtimg_addr} ${dt_start} ${dt_size};" \ -+ "dtimg getindex ${dtimg_addr} ${board_id} ${board_rev}" \ -+ " dt_index;" \ -+ "dtimg start ${dtimg_addr} ${dt_index} fdt_addr_r;"\ -+ "fi\0" \ -+ "android_mmc_kernel="\ -+ "if part start mmc ${devnum} boot_${suffix} boot_start &&" \ -+ "part size mmc ${devnum} boot_${suffix} boot_size;"\ -+ "then " \ -+ "mmc read ${kernel_addr_r} ${boot_start} ${boot_size};" \ -+ "part nb mmc ${devnum} system_${suffix} rootpart_nb;" \ -+ "env set bootargs" \ -+ "root=/dev/mmcblk${devnum}p${rootpart_nb} " \ -+ "androidboot.serialno=${serial#} " \ -+ "androidboot.slot_suffix=_${suffix};"\ -+ "fi\0" \ -+ "android_mmc_boot="\ -+ "mmc dev ${devnum};"\ -+ "run android_mmc_splash;" \ -+ "run android_mmc_fdt;" \ -+ "run android_mmc_kernel;" \ -+ "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \ -+ "bootcmd_android=" \ -+ "env set mmc_boot run android_mmc_boot;" \ -+ "run bootcmd_stm32mp\0" -+ -+#else -+#define STM32MP_ANDROID -+#endif/* CONFIG_CMD_DTIMG */ - --#define STM32MP_DFU_ALT_RAM \ -- "dfu_alt_info_ram=ram 0=" \ -- "uImage ram ${kernel_addr_r} 0x2000000;" \ -- "devicetree.dtb ram ${fdt_addr_r} 0x100000;" \ -- "uramdisk.image.gz ram ${ramdisk_addr_r} 0x10000000\0" -- --#ifdef CONFIG_SET_DFU_ALT_INFO --#define STM32MP_DFU_ALT_INFO \ -- "dfu_alt_info_nor0=mtd nor0=" \ -- "nor_fsbl1 part 1;nor_fsbl2 part 2;" \ -- "nor_ssbl part 3;nor_env part 4\0" \ -- "dfu_alt_info_nand0=mtd nand0="\ -- "nand_fsbl part 1;nand_ssbl1 part 2;" \ -- "nand_ssbl2 part 3;nand_UBI partubi 4\0" \ -- "dfu_alt_info_spi-nand0=mtd spi-nand0="\ -- "spi-nand_fsbl part 1;spi-nand_ssbl1 part 2;" \ -- "spi-nand_ssbl2 part 3;spi-nand_UBI partubi 4\0" \ -- "dfu_alt_info_mmc0=mmc 0=" \ -- "sdcard_fsbl1 part 0 1;sdcard_fsbl2 part 0 2;" \ -- "sdcard_ssbl part 0 3;sdcard_bootfs part 0 4;" \ -- "sdcard_vendorfs part 0 5;sdcard_rootfs part 0 6;" \ -- "sdcard_userfs part 0 7\0" \ -- "dfu_alt_info_mmc1=mmc 1=" \ -- "emmc_fsbl1 raw 0x0 0x200 mmcpart 1;" \ -- "emmc_fsbl2 raw 0x0 0x200 mmcpart 2;emmc_ssbl part 1 1;" \ -- "emmc_bootfs part 1 2;emmc_vendorfs part 1 3;" \ -- "emmc_rootfs part 1 4;emmc_userfs part 1 5\0" -+#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT -+/* eMMC default partitions for fastboot command: oem format */ -+#define PARTS_DEFAULT \ -+ "partitions=" \ -+ "name=ssbl,size=2M;" \ -+ "name=bootfs,size=64MB,bootable;" \ -+ "name=vendorfs,size=16M;" \ -+ "name=rootfs,size=746M;" \ -+ "name=userfs,size=-\0" - #else --#define STM32MP_DFU_ALT_INFO -+#define PARTS_DEFAULT - #endif - -+#include -+ - /* - * memory layout for 32M uncompressed/compressed kernel, - * 1M fdt, 1M script, 1M pxe and 1M for splashimage -@@ -192,16 +238,18 @@ - "pxefile_addr_r=0xc4200000\0" \ - "splashimage=0xc4300000\0" \ - "ramdisk_addr_r=0xc4400000\0" \ -- "fdt_high=0xffffffff\0" \ -- "initrd_high=0xffffffff\0" \ - "altbootcmd=run bootcmd\0" \ -- "env_default=1\0" \ -- "env_check=if test $env_default -eq 1;"\ -- " then env set env_default 0;env save;fi\0" \ -+ "env_check=" \ -+ "env exists env_ver || env set env_ver ${ver};" \ -+ "if env info -p -d -q; then env save; fi;" \ -+ "if test \"$env_ver\" != \"$ver\"; then" \ -+ " echo \"*** Warning: old environment ${env_ver}\";" \ -+ " echo '* set default: env default -a; env save; reset';" \ -+ " echo '* update current: env set env_ver ${ver}; env save';" \ -+ "fi;\0" \ - STM32MP_BOOTCMD \ -- STM32MP_MTDPARTS \ -- STM32MP_DFU_ALT_RAM \ -- STM32MP_DFU_ALT_INFO \ -+ STM32MP_ANDROID \ -+ PARTS_DEFAULT \ - BOOTENV \ - "boot_net_usb_start=true\0" - -diff --git a/include/dfu.h b/include/dfu.h -index 5649663..bb512a8 100644 ---- a/include/dfu.h -+++ b/include/dfu.h -@@ -205,6 +205,9 @@ void dfu_initiated_callback(struct dfu_entity *dfu); - */ - void dfu_flush_callback(struct dfu_entity *dfu); - -+int dfu_transaction_initiate(struct dfu_entity *dfu, bool read); -+void dfu_transaction_cleanup(struct dfu_entity *dfu); -+ - /* - * dfu_defer_flush - pointer to store dfu_entity for deferred flashing. - * It should be NULL when not used. -diff --git a/include/dm/of_access.h b/include/dm/of_access.h -index 13fedb7..1eb1ce1 100644 ---- a/include/dm/of_access.h -+++ b/include/dm/of_access.h -@@ -104,6 +104,46 @@ const void *of_get_property(const struct device_node *np, const char *name, - int *lenp); - - /** -+ * of_get_first_property()- get to the pointer of the first property -+ * -+ * Get pointer to the first property of the node, it is used to iterate -+ * and read all the property with of_get_next_property_by_prop(). -+ * -+ * @np: Pointer to device node -+ * @return pointer to property or NULL if not found -+ */ -+const struct property *of_get_first_property(const struct device_node *np); -+ -+/** -+ * of_get_next_property() - get to the pointer of the next property -+ * -+ * Get pointer to the next property of the node, it is used to iterate -+ * and read all the property with of_get_property_by_prop(). -+ * -+ * @np: Pointer to device node -+ * @property: pointer of the current property -+ * @return pointer to next property or NULL if not found -+ */ -+const struct property *of_get_next_property(const struct device_node *np, -+ const struct property *property); -+ -+/** -+ * of_get_property_by_prop() - get a property value of a node property -+ * -+ * Get value for the property identified by node and property pointer. -+ * -+ * @node: node to read -+ * @property: pointer of the property to read -+ * @propname: place to property name on success -+ * @lenp: place to put length on success -+ * @return pointer to property value or NULL if error -+ */ -+const void *of_get_property_by_prop(const struct device_node *np, -+ const struct property *property, -+ const char **name, -+ int *lenp); -+ -+/** - * of_device_is_compatible() - Check if the node matches given constraints - * @device: pointer to node - * @compat: required compatible string, NULL or "" for any match -diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h -index 5c4cbf0..9ee5556 100644 ---- a/include/dm/ofnode.h -+++ b/include/dm/ofnode.h -@@ -59,6 +59,31 @@ struct ofnode_phandle_args { - }; - - /** -+ * ofprop - reference to a property of a device tree node -+ * -+ * This struct hold the reference on one property of one node, -+ * using struct ofnode and an offset within the flat device tree or either -+ * a pointer to a struct property in the live device tree. -+ * -+ * Thus we can reference arguments in both the live tree and the flat tree. -+ * -+ * The property reference can also hold a null reference. This corresponds to -+ * a struct property NULL pointer or an offset of -1. -+ * -+ * @node: Pointer to device node -+ * @offset: Pointer into flat device tree, used for flat tree. -+ * @prop: Pointer to property, used for live treee. -+ */ -+ -+struct ofprop { -+ ofnode node; -+ union { -+ int offset; -+ const struct property *prop; -+ }; -+}; -+ -+/** - * _ofnode_to_np() - convert an ofnode to a live DT node pointer - * - * This cannot be called if the reference contains an offset. -@@ -543,7 +568,7 @@ int ofnode_decode_display_timing(ofnode node, int index, - struct display_timing *config); - - /** -- * ofnode_get_property()- - get a pointer to the value of a node property -+ * ofnode_get_property() - get a pointer to the value of a node property - * - * @node: node to read - * @propname: property to read -@@ -553,6 +578,42 @@ int ofnode_decode_display_timing(ofnode node, int index, - const void *ofnode_get_property(ofnode node, const char *propname, int *lenp); - - /** -+ * ofnode_get_first_property()- get the reference of the first property -+ * -+ * Get reference to the first property of the node, it is used to iterate -+ * and read all the property with ofnode_get_property_by_prop(). -+ * -+ * @node: node to read -+ * @prop: place to put argument reference -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+int ofnode_get_first_property(ofnode node, struct ofprop *prop); -+ -+/** -+ * ofnode_get_next_property() - get the reference of the next property -+ * -+ * Get reference to the next property of the node, it is used to iterate -+ * and read all the property with ofnode_get_property_by_prop(). -+ * -+ * @prop: reference of current argument and place to put reference of next one -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+int ofnode_get_next_property(struct ofprop *prop); -+ -+/** -+ * ofnode_get_property_by_prop() - get a pointer to the value of a property -+ * -+ * Get value for the property identified by the provided reference. -+ * -+ * @prop: reference on property -+ * @propname: If non-NULL, place to property name on success, -+ * @lenp: If non-NULL, place to put length on success -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+const void *ofnode_get_property_by_prop(const struct ofprop *prop, -+ const char **propname, int *lenp); -+ -+/** - * ofnode_is_available() - check if a node is marked available - * - * @node: node to check -diff --git a/include/dm/read.h b/include/dm/read.h -index d37fcb5..3c6bed7 100644 ---- a/include/dm/read.h -+++ b/include/dm/read.h -@@ -466,6 +466,42 @@ int dev_read_phandle(struct udevice *dev); - const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp); - - /** -+ * dev_read_first_prop()- get the reference of the first property -+ * -+ * Get reference to the first property of the node, it is used to iterate -+ * and read all the property with dev_read_prop_by_prop(). -+ * -+ * @dev: device to check -+ * @prop: place to put argument reference -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+int dev_read_first_prop(struct udevice *dev, struct ofprop *prop); -+ -+/** -+ * ofnode_get_next_property() - get the reference of the next property -+ * -+ * Get reference to the next property of the node, it is used to iterate -+ * and read all the property with dev_read_prop_by_prop(). -+ * -+ * @prop: reference of current argument and place to put reference of next one -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+int dev_read_next_prop(struct ofprop *prop); -+ -+/** -+ * dev_read_prop_by_prop() - get a pointer to the value of a property -+ * -+ * Get value for the property identified by the provided reference. -+ * -+ * @prop: reference on property -+ * @propname: If non-NULL, place to property name on success, -+ * @lenp: If non-NULL, place to put length on success -+ * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found -+ */ -+const void *dev_read_prop_by_prop(struct ofprop *prop, -+ const char **propname, int *lenp); -+ -+/** - * dev_read_alias_seq() - Get the alias sequence number of a node - * - * This works out whether a node is pointed to by an alias, and if so, the -@@ -812,6 +848,23 @@ static inline const void *dev_read_prop(struct udevice *dev, - return ofnode_get_property(dev_ofnode(dev), propname, lenp); - } - -+static inline int dev_read_first_prop(struct udevice *dev, struct ofprop *prop) -+{ -+ return ofnode_get_first_property(dev_ofnode(dev), prop); -+} -+ -+static inline int dev_read_next_prop(struct ofprop *prop) -+{ -+ return ofnode_get_next_property(prop); -+} -+ -+static inline const void *dev_read_prop_by_prop(struct ofprop *prop, -+ const char **propname, -+ int *lenp) -+{ -+ return ofnode_get_property_by_prop(prop, propname, lenp); -+} -+ - static inline int dev_read_alias_seq(struct udevice *dev, int *devnump) - { - return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name, -@@ -889,4 +942,18 @@ static inline int dev_read_alias_highest_id(const char *stem) - ofnode_valid(subnode); \ - subnode = ofnode_next_subnode(subnode)) - -+/** -+ * dev_for_each_property() - Helper function to iterate through property -+ * -+ * This creates a for() loop which works through the property in a device's -+ * device-tree node. -+ * -+ * @prop: struct ofprop holding the current property -+ * @dev: device to use for interation (struct udevice *) -+ */ -+#define dev_for_each_property(prop, dev) \ -+ for (int ret_prop = dev_read_first_prop(dev, &prop); \ -+ !ret_prop; \ -+ ret_prop = dev_read_next_prop(&prop)) -+ - #endif -diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h -index 4cdaf13..ec7b1a9 100644 ---- a/include/dt-bindings/clock/stm32mp1-clks.h -+++ b/include/dt-bindings/clock/stm32mp1-clks.h -@@ -179,6 +179,12 @@ - #define DAC12_K 168 - #define ETHPTP_K 169 - -+#define PCLK1 170 -+#define PCLK2 171 -+#define PCLK3 172 -+#define PCLK4 173 -+#define PCLK5 174 -+ - /* PLL */ - #define PLL1 176 - #define PLL2 177 -@@ -248,4 +254,31 @@ - - #define STM32MP1_LAST_CLK 232 - -+/* SCMI clock identifiers */ -+#define CK_SCMI0_HSE 0 -+#define CK_SCMI0_HSI 1 -+#define CK_SCMI0_CSI 2 -+#define CK_SCMI0_LSE 3 -+#define CK_SCMI0_LSI 4 -+#define CK_SCMI0_PLL2_Q 5 -+#define CK_SCMI0_PLL2_R 6 -+#define CK_SCMI0_MPU 7 -+#define CK_SCMI0_AXI 8 -+#define CK_SCMI0_BSEC 9 -+#define CK_SCMI0_CRYP1 10 -+#define CK_SCMI0_GPIOZ 11 -+#define CK_SCMI0_HASH1 12 -+#define CK_SCMI0_I2C4 13 -+#define CK_SCMI0_I2C6 14 -+#define CK_SCMI0_IWDG1 15 -+#define CK_SCMI0_RNG1 16 -+#define CK_SCMI0_RTC 17 -+#define CK_SCMI0_RTCAPB 18 -+#define CK_SCMI0_SPI6 19 -+#define CK_SCMI0_USART1 20 -+ -+#define CK_SCMI1_PLL3_Q 0 -+#define CK_SCMI1_PLL3_R 1 -+#define CK_SCMI1_MCU 2 -+ - #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ -diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h -index 2cc10ae..c029467 100644 ---- a/include/dt-bindings/gpio/gpio.h -+++ b/include/dt-bindings/gpio/gpio.h -@@ -33,4 +33,10 @@ - #define GPIO_PERSISTENT 0 - #define GPIO_TRANSITORY 8 - -+/* Bit 4 express pull up */ -+#define GPIO_PULL_UP 16 -+ -+/* Bit 5 express pull down */ -+#define GPIO_PULL_DOWN 32 -+ - #endif -diff --git a/include/dt-bindings/gpio/sandbox-gpio.h b/include/dt-bindings/gpio/sandbox-gpio.h -new file mode 100644 -index 0000000..e4bfdb3 ---- /dev/null -+++ b/include/dt-bindings/gpio/sandbox-gpio.h -@@ -0,0 +1,24 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * This header provides constants for binding sandbox,gpio -+ * -+ */ -+#ifndef _DT_BINDINGS_GPIO_SANDBOX_GPIO_H -+#define _DT_BINDINGS_GPIO_SANDBOX_GPIO_H -+ -+/* -+ * Add a specific binding for sandbox gpio. -+ * The value need to be after the generic defines of -+ * dt-bindings/gpio/gpio.h -+ */ -+ -+/* Bit 16 express GPIO input mode */ -+#define GPIO_IN 0x10000 -+ -+/* Bit 17 express GPIO output mode */ -+#define GPIO_OUT 0x20000 -+ -+/* Bit 18 express GPIO output is active */ -+#define GPIO_OUT_ACTIVE 0x40000 -+ -+#endif -diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h -index 06e8476..a1efc30 100644 ---- a/include/dt-bindings/mfd/stm32h7-rcc.h -+++ b/include/dt-bindings/mfd/stm32h7-rcc.h -@@ -13,7 +13,6 @@ - #define STM32H7_RCC_AHB3_QUADSPI 14 - #define STM32H7_RCC_AHB3_SDMMC1 16 - #define STM32H7_RCC_AHB3_CPU 31 --#define STM32H7_RCC_AHB3_CPU1 31 - - #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h -index e6fb8ad..370a25a 100644 ---- a/include/dt-bindings/pinctrl/stm32-pinfunc.h -+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h -@@ -26,6 +26,7 @@ - #define AF14 0xf - #define AF15 0x10 - #define ANALOG 0x11 -+#define RSVD 0x12 - - /* define Pins number*/ - #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) -diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h -index f0c3aae..bc71924 100644 ---- a/include/dt-bindings/reset/stm32mp1-resets.h -+++ b/include/dt-bindings/reset/stm32mp1-resets.h -@@ -105,4 +105,17 @@ - #define GPIOJ_R 19785 - #define GPIOK_R 19786 - -+/* SCMI reset domain identifiers */ -+#define RST_SCMI0_SPI6 0 -+#define RST_SCMI0_I2C4 1 -+#define RST_SCMI0_I2C6 2 -+#define RST_SCMI0_USART1 3 -+#define RST_SCMI0_STGEN 4 -+#define RST_SCMI0_GPIOZ 5 -+#define RST_SCMI0_CRYP1 6 -+#define RST_SCMI0_HASH1 7 -+#define RST_SCMI0_RNG1 8 -+#define RST_SCMI0_MDMA 9 -+#define RST_SCMI0_MCU 10 -+ - #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ -diff --git a/include/dt-bindings/rtc/rtc-stm32.h b/include/dt-bindings/rtc/rtc-stm32.h -new file mode 100644 -index 0000000..4373c4d ---- /dev/null -+++ b/include/dt-bindings/rtc/rtc-stm32.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * This header provides constants for STM32_RTC bindings. -+ */ -+ -+#ifndef _DT_BINDINGS_RTC_RTC_STM32_H -+#define _DT_BINDINGS_RTC_RTC_STM32_H -+ -+#define RTC_OUT1 0 -+#define RTC_OUT2 1 -+#define RTC_OUT2_RMP 2 -+ -+#endif -diff --git a/include/dt-bindings/soc/stm32-hdp.h b/include/dt-bindings/soc/stm32-hdp.h -new file mode 100644 -index 0000000..d986653 ---- /dev/null -+++ b/include/dt-bindings/soc/stm32-hdp.h -@@ -0,0 +1,108 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -+/* -+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved -+ * Author: Roullier Christophe -+ * for STMicroelectronics. -+ */ -+ -+#ifndef _DT_BINDINGS_STM32_HDP_H -+#define _DT_BINDINGS_STM32_HDP_H -+ -+#define STM32_HDP(port, value) ((value) << ((port) * 4)) -+ -+/* define HDP Pins number*/ -+#define HDP0_PWR_PWRWAKE_SYS 0 -+#define HDP0_CM4_SLEEPDEEP 1 -+#define HDP0_PWR_STDBY_WKUP 2 -+#define HDP0_PWR_ENCOMP_VDDCORE 3 -+#define HDP0_BSEC_OUT_SEC_NIDEN 4 -+#define HDP0_RCC_CM4_SLEEPDEEP 6 -+#define HDP0_GPU_DBG7 7 -+#define HDP0_DDRCTRL_LP_REQ 8 -+#define HDP0_PWR_DDR_RET_ENABLE_N 9 -+#define HDP0_GPOVAL_0 15 -+ -+#define HDP1_PWR_PWRWAKE_MCU 0 -+#define HDP1_CM4_HALTED 1 -+#define HDP1_CA7_NAXIERRIRQ 2 -+#define HDP1_PWR_OKIN_MR 3 -+#define HDP1_BSEC_OUT_SEC_DBGEN 4 -+#define HDP1_EXTI_SYS_WAKEUP 5 -+#define HDP1_RCC_PWRDS_MPU 6 -+#define HDP1_GPU_DBG6 7 -+#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ 8 -+#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR 9 -+#define HDP1_GPOVAL_1 15 -+ -+#define HDP2_PWR_PWRWAKE_MPU 0 -+#define HDP2_CM4_RXEV 1 -+#define HDP2_CA7_NPMUIRQ1 2 -+#define HDP2_CA7_NFIQOUT1 3 -+#define HDP2_BSEC_IN_RSTCORE_N 4 -+#define HDP2_EXTI_C2_WAKEUP 5 -+#define HDP2_RCC_PWRDS_MCU 6 -+#define HDP2_GPU_DBG5 7 -+#define HDP2_DDRCTRL_DFI_INIT_COMPLETE 8 -+#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH 9 -+#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ 10 -+#define HDP2_GPOVAL_2 15 -+ -+#define HDP3_PWR_SEL_VTH_VDD_CORE 0 -+#define HDP3_CM4_TXEV 1 -+#define HDP3_CA7_NPMUIRQ0 2 -+#define HDP3_CA7_NFIQOUT0 3 -+#define HDP3_BSEC_OUT_SEC_DFTLOCK 4 -+#define HDP3_EXTI_C1_WAKEUP 5 -+#define HDP3_RCC_PWRDS_SYS 6 -+#define HDP3_GPU_DBG4 7 -+#define HDP3_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE0 8 -+#define HDP3_DDRCTRL_CACTIVE_1 9 -+#define HDP3_GPOVAL_3 15 -+ -+#define HDP4_PWR_PDDS 0 -+#define HDP4_CM4_SLEEPING 1 -+#define HDP4_CA7_NRESET1 2 -+#define HDP4_CA7_NIRQOUT1 3 -+#define HDP4_BSEC_OUT_SEC_DFTEN 4 -+#define HDP4_BSEC_OUT_SEC_DBGSWENABLE 5 -+#define HDP4_ETH_OUT_PMT_INTR_O 6 -+#define HDP4_GPU_DBG3 7 -+#define HDP4_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE1 8 -+#define HDP4_DDRCTRL_CACTIVE_0 9 -+#define HDP4_GPOVAL_4 15 -+ -+#define HDP5_CA7_STANDBYWFIL2 0 -+#define HDP5_PWR_VTH_VDDCORE_ACK 1 -+#define HDP5_CA7_NRESET0 2 -+#define HDP5_CA7_NIRQOUT0 3 -+#define HDP5_BSEC_IN_PWROK 4 -+#define HDP5_BSEC_OUT_SEC_DEVICEEN 5 -+#define HDP5_ETH_OUT_LPI_INTR_O 6 -+#define HDP5_GPU_DBG2 7 -+#define HDP5_DDRCTRL_CACTIVE_DDRC 8 -+#define HDP5_DDRCTRL_WR_CREDIT_CNT 9 -+#define HDP5_GPOVAL_5 15 -+ -+#define HDP6_CA7_STANDBYWFI1 0 -+#define HDP6_CA7_STANDBYWFE1 1 -+#define HDP6_CA7_EVENT0 2 -+#define HDP6_CA7_DBGACK1 3 -+#define HDP6_BSEC_OUT_SEC_SPNIDEN 5 -+#define HDP6_ETH_OUT_MAC_SPEED_O1 6 -+#define HDP6_GPU_DBG1 7 -+#define HDP6_DDRCTRL_CSYSACK_DDRC 8 -+#define HDP6_DDRCTRL_LPR_CREDIT_CNT 9 -+#define HDP6_GPOVAL_6 15 -+ -+#define HDP7_CA7_STANDBYWFI0 0 -+#define HDP7_CA7_STANDBYWFE0 1 -+#define HDP7_CA7_DBGACK0 3 -+#define HDP7_BSEC_OUT_FUSE_OK 4 -+#define HDP7_BSEC_OUT_SEC_SPIDEN 5 -+#define HDP7_ETH_OUT_MAC_SPEED_O0 6 -+#define HDP7_GPU_DBG0 7 -+#define HDP7_DDRCTRL_CSYSREQ_DDRC 8 -+#define HDP7_DDRCTRL_HPR_CREDIT_CNT 9 -+#define HDP7_GPOVAL_7 15 -+ -+#endif /* _DT_BINDINGS_STM32_HDP_H */ -diff --git a/include/env_internal.h b/include/env_internal.h -index 90a4df8..3f13a90 100644 ---- a/include/env_internal.h -+++ b/include/env_internal.h -@@ -209,6 +209,37 @@ struct env_driver { - - extern struct hsearch_data env_htab; - -+/** -+ * env_ext4_get_intf() - Provide the interface for env in EXT4 -+ * -+ * It is a weak function allowing board to overidde the default interface for -+ * U-Boot env in EXT4: CONFIG_ENV_EXT4_INTERFACE -+ * -+ * @return string of interface, empty if not supported -+ */ -+const char *env_ext4_get_intf(void); -+ -+/** -+ * env_ext4_get_dev_part() - Provide the device and partition for env in EXT4 -+ * -+ * It is a weak function allowing board to overidde the default device and -+ * partition used for U-Boot env in EXT4: CONFIG_ENV_EXT4_DEVICE_AND_PART -+ * -+ * @return string of device and partition -+ */ -+const char *env_ext4_get_dev_part(void); -+ -+/** -+ * env_get_location()- Provide the best location for the U-Boot environment -+ * -+ * It is a weak function allowing board to overidde the environment location -+ * -+ * @op: operations performed on the environment -+ * @prio: priority between the multiple environments, 0 being the -+ * highest priority -+ * @return an enum env_location value on success, or -ve error code. -+ */ -+enum env_location env_get_location(enum env_operation op, int prio); - #endif /* DO_DEPS_ONLY */ - - #endif /* _ENV_INTERNAL_H_ */ -diff --git a/include/fastboot.h b/include/fastboot.h -index 1933b1d..966ffc6 100644 ---- a/include/fastboot.h -+++ b/include/fastboot.h -@@ -36,6 +36,12 @@ enum { - #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) - FASTBOOT_COMMAND_OEM_FORMAT, - #endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) -+ FASTBOOT_COMMAND_OEM_PARTCONF, -+#endif -+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) -+ FASTBOOT_COMMAND_OEM_BOOTBUS, -+#endif - - FASTBOOT_COMMAND_COUNT - }; -diff --git a/include/g_dnl.h b/include/g_dnl.h -index 6d461c7..836ee60 100644 ---- a/include/g_dnl.h -+++ b/include/g_dnl.h -@@ -38,6 +38,7 @@ int g_dnl_board_usb_cable_connected(void); - int g_dnl_register(const char *s); - void g_dnl_unregister(void); - void g_dnl_set_serialnumber(char *); -+void g_dnl_set_product(const char *s); - - bool g_dnl_detach(void); - void g_dnl_trigger_detach(void); -diff --git a/include/i2c.h b/include/i2c.h -index 33570f5..6642480 100644 ---- a/include/i2c.h -+++ b/include/i2c.h -@@ -30,6 +30,32 @@ enum dm_i2c_chip_flags { - DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ - }; - -+/** enum i2c_speed_mode - standard I2C speed modes */ -+enum i2c_speed_mode { -+ IC_SPEED_MODE_STANDARD, -+ IC_SPEED_MODE_FAST, -+ IC_SPEED_MODE_FAST_PLUS, -+ IC_SPEED_MODE_HIGH, -+ IC_SPEED_MODE_FAST_ULTRA, -+ -+ IC_SPEED_MODE_COUNT, -+}; -+ -+/** enum i2c_speed_rate - standard I2C speeds in Hz */ -+enum i2c_speed_rate { -+ I2C_SPEED_STANDARD_RATE = 100000, -+ I2C_SPEED_FAST_RATE = 400000, -+ I2C_SPEED_FAST_PLUS_RATE = 1000000, -+ I2C_SPEED_HIGH_RATE = 3400000, -+ I2C_SPEED_FAST_ULTRA_RATE = 5000000, -+}; -+ -+/** enum i2c_address_mode - available address modes */ -+enum i2c_address_mode { -+ I2C_MODE_7_BIT, -+ I2C_MODE_10_BIT -+}; -+ - struct udevice; - /** - * struct dm_i2c_chip - information about an i2c chip -diff --git a/include/image-android-dt.h b/include/image-android-dt.h -index 9a3aa8f..f9abe85 100644 ---- a/include/image-android-dt.h -+++ b/include/image-android-dt.h -@@ -17,4 +17,6 @@ bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, - void android_dt_print_contents(ulong hdr_addr); - #endif - -+int android_dt_get_index(ulong hdr_addr, u32 board_id, u32 board_rev); -+ - #endif /* IMAGE_ANDROID_DT_H */ -diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h -index f4a63b4..52a7a87 100644 ---- a/include/mipi_dsi.h -+++ b/include/mipi_dsi.h -@@ -220,9 +220,15 @@ static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) - /** - * struct mipi_dsi_panel_plat - DSI panel platform data - * @device: DSI peripheral device -+ * @lanes: number of active data lanes -+ * @format: pixel format for video mode -+ * @mode_flags: DSI operation mode related flags - */ - struct mipi_dsi_panel_plat { - struct mipi_dsi_device *device; -+ unsigned int lanes; -+ enum mipi_dsi_pixel_format format; -+ unsigned long mode_flags; - }; - - /** -diff --git a/include/mtd.h b/include/mtd.h -index 65fcd3c..b0f8693 100644 ---- a/include/mtd.h -+++ b/include/mtd.h -@@ -11,4 +11,6 @@ - int mtd_probe(struct udevice *dev); - int mtd_probe_devices(void); - -+void board_mtdparts_default(const char **mtdids, const char **mtdparts); -+ - #endif /* _MTD_H_ */ -diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h -index dc8b5a7..1493a67 100644 ---- a/include/power/stpmic1.h -+++ b/include/power/stpmic1.h -@@ -37,6 +37,7 @@ - #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT) - - #define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24) -+#define STPMIC1_BUCK2_1250000V STPMIC1_BUCK_VOUT(26) - #define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30) - - #define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39) -diff --git a/include/remoteproc.h b/include/remoteproc.h -index 046cd9e..a903acb 100644 ---- a/include/remoteproc.h -+++ b/include/remoteproc.h -@@ -277,6 +277,64 @@ int rproc_elf_load_image(struct udevice *dev, unsigned long addr, ulong size); - * image. - */ - ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr); -+ -+/** -+ * rproc_elf32_load_rsc_table() - load the resource table from an ELF32 image -+ * -+ * Search for the resource table in an ELF32 image, and if found, copy it to -+ * device memory. -+ * -+ * @dev: device loading the resource table -+ * @fw_addr: ELF image address -+ * @fw_size: size of the ELF image -+ * @rsc_addr: pointer to the found resource table address. Updated on -+ * operation success -+ * @rsc_size: pointer to the found resource table size. Updated on operation -+ * success -+ * -+ * @return 0 if a valid resource table is successfully loaded, -ENODATA if there -+ * is no resource table (which is optional), or another appropriate error value. -+ */ -+int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size); -+/** -+ * rproc_elf64_load_rsc_table() - load the resource table from an ELF64 image -+ * -+ * Search for the resource table in an ELF64 image, and if found, copy it to -+ * device memory. -+ * -+ * @dev: device loading the resource table -+ * @fw_addr: ELF image address -+ * @fw_size: size of the ELF image -+ * @rsc_addr: pointer to the found resource table address. Updated on -+ * operation success -+ * @rsc_size: pointer to the found resource table size. Updated on operation -+ * success -+ * -+ * @return 0 if a valid resource table is successfully loaded, -ENODATA if there -+ * is no resource table (which is optional), or another appropriate error value. -+ */ -+int rproc_elf64_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size); -+/** -+ * rproc_elf_load_rsc_table() - load the resource table from an ELF image -+ * -+ * Auto detects if the image is ELF32 or ELF64 image and search accordingly for -+ * the resource table, and if found, copy it to device memory. -+ * -+ * @dev: device loading the resource table -+ * @fw_addr: ELF image address -+ * @fw_size: size of the ELF image -+ * @rsc_addr: pointer to the found resource table address. Updated on -+ * operation success -+ * @rsc_size: pointer to the found resource table size. Updated on operation -+ * success -+ * -+ * @return 0 if a valid resource table is successfully loaded, -ENODATA if there -+ * is no resource table (which is optional), or another appropriate error value. -+ */ -+int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, ulong *rsc_size); - #else - static inline int rproc_init(void) { return -ENOSYS; } - static inline int rproc_dev_init(int id) { return -ENOSYS; } -@@ -304,6 +362,18 @@ static inline int rproc_elf_load_image(struct udevice *dev, ulong addr, - { return -ENOSYS; } - static inline ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr) - { return 0; } -+static inline int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, -+ ulong *rsc_size) -+{ return -ENOSYS; } -+static inline int rproc_elf64_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, -+ ulong *rsc_size) -+{ return -ENOSYS; } -+static inline int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, -+ ulong fw_size, ulong *rsc_addr, -+ ulong *rsc_size) -+{ return -ENOSYS; } - #endif - - #endif /* _RPROC_H_ */ -diff --git a/include/scmi_agent.h b/include/scmi_agent.h -new file mode 100644 -index 0000000..78fcc3b ---- /dev/null -+++ b/include/scmi_agent.h -@@ -0,0 +1,82 @@ -+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -+/* -+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. -+ * Copyright (C) 2019, Linaro Limited -+ */ -+#ifndef SCMI_AGENT_H -+#define SCMI_AGENT_H -+ -+#include -+ -+/** -+ * An SCMI agent represent on communication path from a device driver to -+ * the remote SCMI server which driver sends messages to and receives -+ * response messages from. -+ */ -+struct scmi_agent; -+ -+enum scmi_std_protocol { -+ SCMI_PROTOCOL_ID_BASE = 0x10, -+ SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, -+ SCMI_PROTOCOL_ID_SYSTEM = 0x12, -+ SCMI_PROTOCOL_ID_PERF = 0x13, -+ SCMI_PROTOCOL_ID_CLOCK = 0x14, -+ SCMI_PROTOCOL_ID_SENSOR = 0x15, -+ SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, -+}; -+ -+enum scmi_status_code { -+ SCMI_SUCCESS = 0, -+ SCMI_NOT_SUPPORTED = -1, -+ SCMI_INVALID_PARAMETERS = -2, -+ SCMI_DENIED = -3, -+ SCMI_NOT_FOUND = -4, -+ SCMI_OUT_OF_RANGE = -5, -+ SCMI_BUSY = -6, -+ SCMI_COMMS_ERROR = -7, -+ SCMI_GENERIC_ERROR = -8, -+ SCMI_HARDWARE_ERROR = -9, -+ SCMI_PROTOCOL_ERROR = -10, -+}; -+ -+/* -+ * struct scmi_msg - Context of a SCMI message sent and the response received -+ * -+ * @protocol_id: SCMI protocol ID -+ * @message_id: SCMI message ID for a defined protocol ID -+ * @in_msg: pointer to the message payload sent by the driver -+ * @in_msg_sz: byte size of the message payload sent -+ * @out_msg: pointer to buffer to store response message payload -+ * @out_msg_size: Byte size of the response buffer or payload -+ */ -+struct scmi_msg { -+ unsigned int protocol_id; -+ unsigned int message_id; -+ u8 *in_msg; -+ size_t in_msg_sz; -+ u8 *out_msg; -+ size_t out_msg_sz; -+}; -+ -+/** -+ * scmi_send_and_process_msg() - send and process a SCMI message -+ * -+ * Send a message to a SCMI server through a target SCMI agent device. -+ * Caller sets scmi_msg::out_msg_sz to the output message buffer size. -+ * On return, scmi_msg::out_msg_sz stores the response payload size. -+ * -+ * @dev: SCMI agent device -+ * @msg: Message structure reference -+ * @return 0 on success, a negative errno otherwise -+ */ -+int scmi_agent_process_msg(struct udevice *dev, struct scmi_msg *msg); -+ -+/** -+ * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code -+ * -+ * @scmi_errno: SCMI error code value -+ * @return 0 for successful status and a negative errno otherwise -+ */ -+int scmi_to_linux_errno(int32_t scmi_errno); -+ -+#endif /* SCMI_AGENT_H */ -diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c -index 560041b..be03aea 100644 ---- a/lib/libfdt/fdt_ro.c -+++ b/lib/libfdt/fdt_ro.c -@@ -183,8 +183,8 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) - if (fdt_chk_extra() && !re) - return -FDT_ERR_BADOFFSET; - -- *address = fdt64_ld(&re->address); -- *size = fdt64_ld(&re->size); -+ *address = fdt64_to_cpu(re->address); -+ *size = fdt64_to_cpu(re->size); - return 0; - } - -@@ -194,7 +194,7 @@ int fdt_num_mem_rsv(const void *fdt) - const struct fdt_reserve_entry *re; - - for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) { -- if (fdt64_ld(&re->size) == 0) -+ if (fdt64_to_cpu(re->size) == 0) - return i; - } - return -FDT_ERR_TRUNCATED; -@@ -372,7 +372,7 @@ static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, - prop = fdt_offset_ptr_(fdt, offset); - - if (lenp) -- *lenp = fdt32_ld(&prop->len); -+ *lenp = fdt32_to_cpu(prop->len); - - return prop; - } -@@ -410,7 +410,7 @@ static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, - offset = -FDT_ERR_INTERNAL; - break; - } -- if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff), -+ if (fdt_string_eq_(fdt, fdt32_to_cpu(prop->nameoff), - name, namelen)) { - if (poffset) - *poffset = offset; -@@ -463,7 +463,7 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, - - /* Handle realignment */ - if (fdt_chk_version() && fdt_version(fdt) < 0x10 && -- (poffset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) -+ (poffset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8) - return prop->data + 4; - return prop->data; - } -@@ -481,7 +481,7 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, - int namelen; - - if (fdt_chk_extra()) { -- name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff), -+ name = fdt_get_string(fdt, fdt32_to_cpu(prop->nameoff), - &namelen); - if (!name) { - if (lenp) -@@ -490,13 +490,13 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, - } - *namep = name; - } else { -- *namep = fdt_string(fdt, fdt32_ld(&prop->nameoff)); -+ *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); - } - } - - /* Handle realignment */ - if (fdt_chk_version() && fdt_version(fdt) < 0x10 && -- (offset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) -+ (offset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8) - return prop->data + 4; - return prop->data; - } -@@ -521,7 +521,7 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) - return 0; - } - -- return fdt32_ld(php); -+ return fdt32_to_cpu(*php); - } - - const char *fdt_get_alias_namelen(const void *fdt, -diff --git a/lib/optee/optee.c b/lib/optee/optee.c -index c883c49..79b058a 100644 ---- a/lib/optee/optee.c -+++ b/lib/optee/optee.c -@@ -91,7 +91,7 @@ static int optee_copy_firmware_node(const void *old_blob, void *fdt_blob) - - offs = fdt_add_subnode(fdt_blob, offs, "optee"); - if (offs < 0) -- return ret; -+ return offs; - - /* copy the compatible property */ - prop = fdt_getprop(old_blob, old_offs, "compatible", &len); -diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt -index cf1808e..db089be 100644 ---- a/scripts/config_whitelist.txt -+++ b/scripts/config_whitelist.txt -@@ -1547,7 +1547,6 @@ CONFIG_SETUP_MEMORY_TAGS - CONFIG_SET_BIST - CONFIG_SET_BOOTARGS - CONFIG_SET_DFU_ALT_BUF_LEN --CONFIG_SET_DFU_ALT_INFO - CONFIG_SFIO - CONFIG_SF_DATAFLASH - CONFIG_SGI_IP28 -@@ -3228,7 +3227,6 @@ CONFIG_SYS_MRAM_SIZE - CONFIG_SYS_MSC0_VAL - CONFIG_SYS_MSC1_VAL - CONFIG_SYS_MSC2_VAL --CONFIG_SYS_MTDPARTS_RUNTIME - CONFIG_SYS_MX5_CLK32 - CONFIG_SYS_MX5_HCLK - CONFIG_SYS_MX6_CLK32 -diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c -index e398815..d9d52e0 100644 ---- a/scripts/dtc/libfdt/fdt_ro.c -+++ b/scripts/dtc/libfdt/fdt_ro.c -@@ -179,8 +179,8 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) - if (fdt_chk_extra() && !re) - return -FDT_ERR_BADOFFSET; - -- *address = fdt64_ld(&re->address); -- *size = fdt64_ld(&re->size); -+ *address = fdt64_to_cpu(re->address); -+ *size = fdt64_to_cpu(re->size); - return 0; - } - -@@ -190,7 +190,7 @@ int fdt_num_mem_rsv(const void *fdt) - const struct fdt_reserve_entry *re; - - for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) { -- if (fdt64_ld(&re->size) == 0) -+ if (fdt64_to_cpu(re->size) == 0) - return i; - } - return -FDT_ERR_TRUNCATED; -@@ -368,7 +368,7 @@ static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, - prop = fdt_offset_ptr_(fdt, offset); - - if (lenp) -- *lenp = fdt32_ld(&prop->len); -+ *lenp = fdt32_to_cpu(prop->len); - - return prop; - } -@@ -406,7 +406,7 @@ static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, - offset = -FDT_ERR_INTERNAL; - break; - } -- if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff), -+ if (fdt_string_eq_(fdt, fdt32_to_cpu(prop->nameoff), - name, namelen)) { - if (poffset) - *poffset = offset; -@@ -459,7 +459,7 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, - - /* Handle realignment */ - if (fdt_chk_version() && fdt_version(fdt) < 0x10 && -- (poffset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) -+ (poffset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8) - return prop->data + 4; - return prop->data; - } -@@ -477,7 +477,7 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, - int namelen; - - if (fdt_chk_extra()) { -- name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff), -+ name = fdt_get_string(fdt, fdt32_to_cpu(prop->nameoff), - &namelen); - if (!name) { - if (lenp) -@@ -486,13 +486,13 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, - } - *namep = name; - } else { -- *namep = fdt_string(fdt, fdt32_ld(&prop->nameoff)); -+ *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); - } - } - - /* Handle realignment */ - if (fdt_chk_version() && fdt_version(fdt) < 0x10 && -- (offset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) -+ (offset + sizeof(*prop)) % 8 && fdt32_to_cpu(prop->len) >= 8) - return prop->data + 4; - return prop->data; - } -@@ -517,7 +517,7 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) - return 0; - } - -- return fdt32_ld(php); -+ return fdt32_to_cpu(*php); - } - - const char *fdt_get_alias_namelen(const void *fdt, -diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h -index 36fadcd..fa63fff 100644 ---- a/scripts/dtc/libfdt/libfdt.h -+++ b/scripts/dtc/libfdt/libfdt.h -@@ -117,23 +117,6 @@ static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) - - uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); - --/* -- * Alignment helpers: -- * These helpers access words from a device tree blob. They're -- * built to work even with unaligned pointers on platforms (ike -- * ARM) that don't like unaligned loads and stores -- */ -- --static inline uint32_t fdt32_ld(const fdt32_t *p) --{ -- const uint8_t *bp = (const uint8_t *)p; -- -- return ((uint32_t)bp[0] << 24) -- | ((uint32_t)bp[1] << 16) -- | ((uint32_t)bp[2] << 8) -- | bp[3]; --} -- - static inline void fdt32_st(void *property, uint32_t value) - { - uint8_t *bp = (uint8_t *)property; -@@ -144,20 +127,6 @@ static inline void fdt32_st(void *property, uint32_t value) - bp[3] = value & 0xff; - } - --static inline uint64_t fdt64_ld(const fdt64_t *p) --{ -- const uint8_t *bp = (const uint8_t *)p; -- -- return ((uint64_t)bp[0] << 56) -- | ((uint64_t)bp[1] << 48) -- | ((uint64_t)bp[2] << 40) -- | ((uint64_t)bp[3] << 32) -- | ((uint64_t)bp[4] << 24) -- | ((uint64_t)bp[5] << 16) -- | ((uint64_t)bp[6] << 8) -- | bp[7]; --} -- - static inline void fdt64_st(void *property, uint64_t value) - { - uint8_t *bp = (uint8_t *)property; -@@ -232,7 +201,7 @@ int fdt_next_subnode(const void *fdt, int offset); - /* General functions */ - /**********************************************************************/ - #define fdt_get_header(fdt, field) \ -- (fdt32_ld(&((const struct fdt_header *)(fdt))->field)) -+ (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) - #define fdt_magic(fdt) (fdt_get_header(fdt, magic)) - #define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) - #define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) -diff --git a/test/dm/Makefile b/test/dm/Makefile -index 0c2fd5c..6a1af15 100644 ---- a/test/dm/Makefile -+++ b/test/dm/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_LED) += led.o - obj-$(CONFIG_DM_MAILBOX) += mailbox.o - obj-$(CONFIG_DM_MMC) += mmc.o - obj-y += ofnode.o -+obj-y += ofread.o - obj-$(CONFIG_OSD) += osd.o - obj-$(CONFIG_DM_VIDEO) += panel.o - obj-$(CONFIG_DM_PCI) += pci.o -diff --git a/test/dm/gpio.c b/test/dm/gpio.c -index bb4b20c..5992d93 100644 ---- a/test/dm/gpio.c -+++ b/test/dm/gpio.c -@@ -23,9 +23,9 @@ static int dm_test_gpio(struct unit_test_state *uts) - char buf[80]; - - /* -- * We expect to get 3 banks. One is anonymous (just numbered) and -- * comes from platdata. The other two are named a (20 gpios) -- * and b (10 gpios) and come from the device tree. See -+ * We expect to get 4 banks. One is anonymous (just numbered) and -+ * comes from platdata. The other are named a (20 gpios), -+ * b (10 gpios) and c (10 gpios) and come from the device tree. See - * test/dm/test.dts. - */ - ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio)); -@@ -73,11 +73,16 @@ static int dm_test_gpio(struct unit_test_state *uts) - ut_asserteq(1, ops->get_value(dev, offset)); - - /* Make it an open drain output, and reset it */ -- ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset)); -- ut_assertok(ops->set_open_drain(dev, offset, 1)); -- ut_asserteq(1, sandbox_gpio_get_open_drain(dev, offset)); -- ut_assertok(ops->set_open_drain(dev, offset, 0)); -- ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset)); -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE, -+ sandbox_gpio_get_dir_flags(dev, offset)); -+ ut_assertok(ops->set_dir_flags(dev, offset, -+ GPIOD_IS_OUT | GPIOD_OPEN_DRAIN)); -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_OPEN_DRAIN, -+ sandbox_gpio_get_dir_flags(dev, offset)); -+ ut_assertok(ops->set_dir_flags(dev, offset, -+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE, -+ sandbox_gpio_get_dir_flags(dev, offset)); - - /* Make it an input */ - ut_assertok(ops->direction_input(dev, offset)); -@@ -214,11 +219,14 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) - desc_list2, - ARRAY_SIZE(desc_list2), - 0)); -+ ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_a, 4, NULL)); - ut_assertok(gpio_free_list(dev, desc_list, 3)); -+ ut_asserteq(GPIOF_UNUSED, gpio_get_function(gpio_a, 4, NULL)); - ut_asserteq(3, gpio_request_list_by_name(dev, "test-gpios", desc_list, - ARRAY_SIZE(desc_list), - GPIOD_IS_OUT | - GPIOD_IS_OUT_ACTIVE)); -+ ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_a, 4, NULL)); - ut_asserteq_ptr(gpio_a, desc_list[0].dev); - ut_asserteq(1, desc_list[0].offset); - ut_asserteq_ptr(gpio_a, desc_list[1].dev); -@@ -228,10 +236,14 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) - ut_asserteq(1, dm_gpio_get_value(desc_list)); - ut_assertok(gpio_free_list(dev, desc_list, 3)); - -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE, -+ sandbox_gpio_get_dir_flags(gpio_a, 1)); - ut_asserteq(6, gpio_request_list_by_name(dev, "test2-gpios", desc_list, - ARRAY_SIZE(desc_list), 0)); -- /* This was set to output previously, so still will be */ -- ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_a, 1, NULL)); -+ -+ /* This was set to output previously but flags resetted to 0 = INPUT */ -+ ut_asserteq(0, sandbox_gpio_get_dir_flags(gpio_a, 1)); -+ ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_a, 1, NULL)); - - /* Active low should invert the input value */ - ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_b, 6, NULL)); -@@ -243,7 +255,42 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) - ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_b, 9, NULL)); - ut_asserteq(1, dm_gpio_get_value(&desc_list[5])); - -- - return 0; - } - DM_TEST(dm_test_gpio_phandles, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -+ -+/* Check the gpio pin configuration get from device tree information */ -+static int dm_test_gpio_get_dir_flags(struct unit_test_state *uts) -+{ -+ struct gpio_desc desc_list[6]; -+ struct udevice *dev; -+ ulong flags; -+ -+ ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev)); -+ -+ ut_asserteq(6, gpio_request_list_by_name(dev, "test3-gpios", desc_list, -+ ARRAY_SIZE(desc_list), 0)); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[0], &flags)); -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_OPEN_DRAIN, flags); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[1], &flags)); -+ ut_asserteq(GPIOD_IS_OUT | GPIOD_OPEN_SOURCE, flags); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[2], &flags)); -+ ut_asserteq(GPIOD_IS_OUT, flags); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[3], &flags)); -+ ut_asserteq(GPIOD_IS_IN | GPIOD_PULL_UP, flags); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[4], &flags)); -+ ut_asserteq(GPIOD_IS_IN | GPIOD_PULL_DOWN, flags); -+ -+ ut_assertok(dm_gpio_get_dir_flags(&desc_list[5], &flags)); -+ ut_asserteq(GPIOD_IS_IN, flags); -+ -+ ut_assertok(gpio_free_list(dev, desc_list, 6)); -+ -+ return 0; -+} -+DM_TEST(dm_test_gpio_get_dir_flags, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -diff --git a/test/dm/ofread.c b/test/dm/ofread.c -new file mode 100644 -index 0000000..f2a1382 ---- /dev/null -+++ b/test/dm/ofread.c -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+ -+static int dm_test_ofnode_get_property_by_prop(struct unit_test_state *uts) -+{ -+ ofnode node; -+ struct ofprop prop; -+ const void *value; -+ const char *propname; -+ int res, len, count = 0; -+ -+ node = ofnode_path("/cros-ec/flash"); -+ for (res = ofnode_get_first_property(node, &prop); -+ !res; -+ res = ofnode_get_next_property(&prop)) { -+ value = ofnode_get_property_by_prop(&prop, &propname, &len); -+ ut_assertnonnull(value); -+ switch (count) { -+ case 0: -+ ut_asserteq_str("image-pos", propname); -+ ut_asserteq(4, len); -+ break; -+ case 1: -+ ut_asserteq_str("size", propname); -+ ut_asserteq(4, len); -+ break; -+ case 2: -+ ut_asserteq_str("erase-value", propname); -+ ut_asserteq(4, len); -+ break; -+ case 3: -+ /* only for platdata */ -+ ut_asserteq_str("name", propname); -+ ut_asserteq(6, len); -+ ut_asserteq_str("flash", value); -+ break; -+ default: -+ break; -+ } -+ count++; -+ } -+ -+ return 0; -+} -+DM_TEST(dm_test_ofnode_get_property_by_prop, -+ DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c -index 1d9a9b3..4067596 100644 ---- a/test/dm/remoteproc.c -+++ b/test/dm/remoteproc.c -@@ -103,8 +103,8 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) - 0x00, 0x00, 0x00, 0x08, - /* phoff (program header offset @ 0x40)*/ - 0x40, 0x00, 0x00, 0x00, -- /* shoff (section header offset : none) */ -- 0x00, 0x00, 0x00, 0x00, -+ /* shoff (section header offset @ 0x90) */ -+ 0x90, 0x00, 0x00, 0x00, - /* flags */ - 0x00, 0x00, 0x00, 0x00, - /* ehsize (elf header size = 0x34) */ -@@ -113,16 +113,17 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) - 0x20, 0x00, - /* phnum (program header number : 1) */ - 0x01, 0x00, -- /* shentsize (section heade size : none) */ -- 0x00, 0x00, -- /* shnum (section header number: none) */ -- 0x00, 0x00, -- /* shstrndx (section header name section index: none) */ -- 0x00, 0x00, -+ /* shentsize (section header size : 40 bytes) */ -+ 0x28, 0x00, -+ /* shnum (section header number: 3) */ -+ 0x02, 0x00, -+ /* shstrndx (section header name section index: 1) */ -+ 0x01, 0x00, - /* padding */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, -+ - /* @0x40 - PROGRAM HEADER TABLE - */ - /* type : PT_LOAD */ - 0x01, 0x00, 0x00, 0x00, -@@ -140,14 +141,63 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) - 0x05, 0x00, 0x00, 0x00, - /* padding */ - 0x00, 0x00, 0x00, 0x00, -+ -+ /* @0x60 - RESOURCE TABLE SECTION - */ -+ /* version */ -+ 0x01, 0x00, 0x00, 0x00, -+ /* num (0, no entries) */ -+ 0x00, 0x00, 0x00, 0x00, -+ /* Reserved */ -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ -+ /* @0x70 - SECTION'S NAMES SECTION - */ -+ /* section 0 name (".shrtrtab") */ -+ 0x2e, 0x73, 0x68, 0x73, 0x74, 0x72, 0x74, 0x61, 0x62, 0x00, -+ /* section 1 name (".resource_table") */ -+ 0x2e, 0x72, 0x65, 0x73, 0x6f, 0x75, 0x72, 0x63, 0x65, 0x5f, -+ 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, -+ /* padding */ -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ -+ /* @0x90 - SECTION HEADER TABLE - */ -+ /* Section 0 : resource table header */ -+ /* sh_name - index into section header string table section */ -+ 0x0a, 0x00, 0x00, 0x00, -+ /* sh_type and sh_flags */ -+ 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, -+ /* sh_addr = where the resource table has to be copied to */ -+ 0x00, 0x00, 0x00, 0x00, -+ /* sh_offset = 0x60 */ -+ 0x60, 0x00, 0x00, 0x00, -+ /* sh_size = 16 bytes */ -+ 0x10, 0x00, 0x00, 0x00, -+ /* sh_link, sh_info, sh_addralign, sh_entsize */ -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ /* Section 1 : section's names section header */ -+ /* sh_name - index into section header string table section */ -+ 0x00, 0x00, 0x00, 0x00, -+ /* sh_type and sh_flags */ -+ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ /* sh_addr */ -+ 0x00, 0x00, 0x00, 0x00, -+ /* sh_offset = 0x70 */ -+ 0x70, 0x00, 0x00, 0x00, -+ /* sh_size = 27 bytes */ -+ 0x1b, 0x00, 0x00, 0x00, -+ /* sh_link, sh_info, sh_addralign, sh_entsize */ -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - unsigned int size = ARRAY_SIZE(valid_elf32); - struct udevice *dev; -- phys_addr_t loaded_firmware_paddr; -- void *loaded_firmware; -- u32 loaded_firmware_size; -+ phys_addr_t loaded_firmware_paddr, loaded_rsc_table_paddr; -+ void *loaded_firmware, *loaded_rsc_table; -+ u32 loaded_firmware_size, rsc_table_size; -+ ulong rsc_addr, rsc_size; - Elf32_Ehdr *ehdr = (Elf32_Ehdr *)valid_elf32; - Elf32_Phdr *phdr = (Elf32_Phdr *)(valid_elf32 + ehdr->e_phoff); -+ Elf32_Shdr *shdr = (Elf32_Shdr *)(valid_elf32 + ehdr->e_shoff); - - ut_assertok(uclass_get_device(UCLASS_REMOTEPROC, 0, &dev)); - -@@ -178,6 +228,25 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) - 0x08000000); - unmap_physmem(loaded_firmware, MAP_NOCACHE); - -+ /* Resource table */ -+ shdr->sh_addr = CONFIG_SYS_SDRAM_BASE; -+ rsc_table_size = shdr->sh_size; -+ -+ loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET; -+ loaded_rsc_table = map_physmem(loaded_rsc_table_paddr, -+ rsc_table_size, MAP_NOCACHE); -+ ut_assertnonnull(loaded_rsc_table); -+ memset(loaded_rsc_table, 0, rsc_table_size); -+ -+ /* Load and verify */ -+ ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size, -+ &rsc_addr, &rsc_size)); -+ ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE); -+ ut_asserteq(rsc_size, rsc_table_size); -+ ut_assertok(memcmp(loaded_firmware, valid_elf32 + shdr->sh_offset, -+ shdr->sh_size)); -+ unmap_physmem(loaded_firmware, MAP_NOCACHE); -+ - /* Invalid ELF Magic */ - valid_elf32[0] = 0; - ut_asserteq(-EPROTONOSUPPORT, -diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c -index 1fb8b5c..0997d2b 100644 ---- a/test/dm/test-fdt.c -+++ b/test/dm/test-fdt.c -@@ -196,7 +196,7 @@ static int dm_test_fdt(struct unit_test_state *uts) - int ret; - int i; - -- ret = dm_scan_fdt(gd->fdt_blob, false); -+ ret = dm_extended_scan_fdt(gd->fdt_blob, false); - ut_assert(!ret); - - ret = uclass_get(UCLASS_TEST_FDT, &uc); -@@ -227,7 +227,7 @@ static int dm_test_alias_highest_id(struct unit_test_state *uts) - ut_asserteq(5, ret); - - ret = dev_read_alias_highest_id("gpio"); -- ut_asserteq(2, ret); -+ ut_asserteq(3, ret); - - ret = dev_read_alias_highest_id("pci"); - ut_asserteq(2, ret); -diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py -index 6ff38f1..cbdb410 100644 ---- a/test/py/tests/test_env.py -+++ b/test/py/tests/test_env.py -@@ -336,3 +336,47 @@ def test_env_import_whitelist_delete(state_test_env): - unset_var(state_test_env, 'foo2') - unset_var(state_test_env, 'foo3') - unset_var(state_test_env, 'foo4') -+ -+@pytest.mark.boardspec('sandbox') -+@pytest.mark.buildconfigspec('cmd_nvedit_info') -+def test_env_info(state_test_env): -+ -+ """Test 'env info' command with several options. -+ """ -+ c = state_test_env.u_boot_console -+ -+ response = c.run_command('env info') -+ assert 'env_valid = invalid' in response -+ assert 'env_ready = true' in response -+ assert 'env_use_default = true' in response -+ -+ response = c.run_command('env info -p -d') -+ assert 'Default environment is used' in response -+ assert 'Environment cannot be persisted' in response -+ -+ response = c.run_command('env info -p -d -q') -+ assert response == "" -+ -+@pytest.mark.boardspec('sandbox') -+@pytest.mark.buildconfigspec('cmd_nvedit_info') -+@pytest.mark.buildconfigspec('cmd_echo') -+def test_env_info_quiet(state_test_env): -+ -+ """Test 'env info' quiet command result with several options for test. -+ """ -+ c = state_test_env.u_boot_console -+ -+ response = c.run_command('env info -d -q') -+ assert response == "" -+ response = c.run_command('echo $?') -+ assert response == "0" -+ -+ response = c.run_command('env info -p -q') -+ assert response == "" -+ response = c.run_command('echo $?') -+ assert response == "1" -+ -+ response = c.run_command('env info -d -p -q') -+ assert response == "" -+ response = c.run_command('echo $?') -+ assert response == "1" -diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py -index 25394f1..4e6df99 100644 ---- a/test/py/tests/test_pinmux.py -+++ b/test/py/tests/test_pinmux.py -@@ -22,11 +22,21 @@ def test_pinmux_usage_2(u_boot_console): - def test_pinmux_status_all(u_boot_console): - """Test that 'pinmux status -a' displays pin's muxing.""" - output = u_boot_console.run_command('pinmux status -a') -- assert ('SCL : I2C SCL' in output) -- assert ('SDA : I2C SDA' in output) -- assert ('TX : Uart TX' in output) -- assert ('RX : Uart RX' in output) -- assert ('W1 : 1-wire gpio' in output) -+ -+ assert ('pinctrl-gpio:' in output) -+ assert ('a5 : gpio output .' in output) -+ assert ('a6 : gpio output .' in output) -+ -+ assert ('pinctrl:' in output) -+ assert ('SCL : I2C SCL.' in output) -+ assert ('SDA : I2C SDA.' in output) -+ assert ('TX : Uart TX.' in output) -+ assert ('RX : Uart RX.' in output) -+ assert ('W1 : 1-wire gpio.' in output) -+ assert ('GPIO0 : gpio bias-pull-up input-disable.' in output) -+ assert ('GPIO1 : gpio drive-open-drain.' in output) -+ assert ('GPIO2 : gpio bias-pull-down input-enable.' in output) -+ assert ('GPIO3 : gpio bias-disable.' in output) - - @pytest.mark.buildconfigspec('cmd_pinmux') - @pytest.mark.boardspec('sandbox') -@@ -59,8 +69,16 @@ def test_pinmux_status(u_boot_console): - """Test that 'pinmux status' displays selected pincontroller's pin - muxing descriptions.""" - output = u_boot_console.run_command('pinmux status') -- assert ('SCL : I2C SCL' in output) -- assert ('SDA : I2C SDA' in output) -- assert ('TX : Uart TX' in output) -- assert ('RX : Uart RX' in output) -- assert ('W1 : 1-wire gpio' in output) -+ -+ assert (not 'pinctrl-gpio:' in output) -+ assert (not 'pinctrl:' in output) -+ -+ assert ('SCL : I2C SCL.' in output) -+ assert ('SDA : I2C SDA.' in output) -+ assert ('TX : Uart TX.' in output) -+ assert ('RX : Uart RX.' in output) -+ assert ('W1 : 1-wire gpio.' in output) -+ assert ('GPIO0 : gpio bias-pull-up input-disable.' in output) -+ assert ('GPIO1 : gpio drive-open-drain.' in output) -+ assert ('GPIO2 : gpio bias-pull-down input-enable.' in output) -+ assert ('GPIO3 : gpio bias-disable.' in output) -diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c -index 8f44f59..2a8058f 100644 ---- a/tools/fdtgrep.c -+++ b/tools/fdtgrep.c -@@ -805,7 +805,7 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) - * we do another pass to actually record them. - */ - for (i = 0; i < 2; i++) { -- region = malloc(count * sizeof(struct fdt_region)); -+ region = realloc(region, count * sizeof(struct fdt_region)); - if (!region) { - fprintf(stderr, "Out of memory for %d regions\n", - count); -@@ -823,8 +823,10 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) - } - if (count <= max_regions) - break; -+ } -+ if (count > max_regions) { - free(region); -- fprintf(stderr, "Internal error with fdtgrep_find_region)(\n"); -+ fprintf(stderr, "Internal error with fdtgrep_find_region()\n"); - return -1; - } - -diff --git a/tools/stm32image.c b/tools/stm32image.c -index ff3ec5f..18357c0 100644 ---- a/tools/stm32image.c -+++ b/tools/stm32image.c -@@ -45,7 +45,7 @@ static void stm32image_default_header(struct stm32_header *ptr) - ptr->magic_number = HEADER_MAGIC; - ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1; - ptr->option_flags = HEADER_DEFAULT_OPTION; -- ptr->ecdsa_algorithm = 1; -+ ptr->ecdsa_algorithm = cpu_to_le32(1); - ptr->binary_type = HEADER_TYPE_UBOOT; - } - -@@ -131,7 +131,8 @@ static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, - stm32hdr->image_entry_point = cpu_to_le32(params->ep); - stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size - - sizeof(struct stm32_header)); -- stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size); -+ stm32hdr->image_checksum = -+ cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size)); - } - - /* --- -2.7.4 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.10-stm32mp-r1-MISC-DRIVERS.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.10-stm32mp-r1-MISC-DRIVERS.patch new file mode 100644 index 0000000..235985d --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0003-ARM-v2020.10-stm32mp-r1-MISC-DRIVERS.patch @@ -0,0 +1,5003 @@ +From 9e9811305959e8d853a54714eb43ae21fe5d3e1d Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Tue, 16 Mar 2021 08:17:59 +0100 +Subject: [PATCH 3/5] ARM v2020.10-stm32mp-r1 MISC-DRIVERS + +Signed-off-by: Romuald JEANNE +--- + common/Kconfig | 2 +- + common/cli_readline.c | 6 + + common/image-fdt.c | 23 +- + doc/device-tree-bindings/arm/arm,scmi.txt | 197 +++++++++ + .../phy/phy-stm32-usbphyc.txt | 2 + + drivers/clk/Kconfig | 8 + + drivers/clk/Makefile | 1 + + drivers/clk/clk_scmi.c | 99 +++++ + drivers/clk/clk_stm32mp1.c | 63 +-- + drivers/core/ofnode.c | 10 + + drivers/dfu/dfu_mtd.c | 9 +- + drivers/firmware/Kconfig | 2 + + drivers/firmware/Makefile | 1 + + drivers/firmware/scmi/Kconfig | 19 + + drivers/firmware/scmi/Makefile | 5 + + drivers/firmware/scmi/mailbox_agent.c | 102 +++++ + drivers/firmware/scmi/sandbox-scmi_agent.c | 410 ++++++++++++++++++ + drivers/firmware/scmi/sandbox-scmi_devices.c | 113 +++++ + drivers/firmware/scmi/scmi_agent-uclass.c | 119 +++++ + drivers/firmware/scmi/smccc_agent.c | 89 ++++ + drivers/firmware/scmi/smt.c | 139 ++++++ + drivers/firmware/scmi/smt.h | 86 ++++ + drivers/gpio/stm32_gpio.c | 28 +- + drivers/mtd/nand/core.c | 2 + + drivers/mtd/nand/spi/core.c | 3 + + drivers/mtd/spi/spi-nor-core.c | 3 + + drivers/phy/phy-stm32-usbphyc.c | 33 +- + drivers/pinctrl/pinctrl-stmfx.c | 12 +- + drivers/pinctrl/pinctrl_stm32.c | 37 +- + drivers/remoteproc/Kconfig | 8 + + drivers/remoteproc/Makefile | 1 + + drivers/remoteproc/rproc-optee.c | 219 ++++++++++ + drivers/remoteproc/stm32_copro.c | 207 ++++++--- + drivers/reset/Kconfig | 8 + + drivers/reset/Makefile | 1 + + drivers/reset/reset-scmi.c | 81 ++++ + drivers/reset/stm32-reset.c | 17 +- + drivers/spi/stm32_qspi.c | 2 + + drivers/usb/gadget/dwc2_udc_otg.c | 61 ++- + drivers/usb/gadget/dwc2_udc_otg_regs.h | 2 + + drivers/video/dw_mipi_dsi.c | 62 ++- + drivers/video/stm32/stm32_dsi.c | 3 + + env/ext4.c | 3 +- + env/mmc.c | 6 +- + env/sf.c | 32 +- + include/configs/10m50_devboard.h | 5 - + include/configs/3c120_devboard.h | 5 - + include/configs/sandbox.h | 2 - + include/configs/stm32mp1.h | 1 - + include/configs/x86-common.h | 2 - + include/dm/ofnode.h | 11 + + include/dm/uclass-id.h | 1 + + include/dt-bindings/clock/stm32mp1-clks.h | 33 ++ + include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 + + include/dt-bindings/reset/stm32mp1-resets.h | 15 + + include/dt-bindings/rtc/rtc-stm32.h | 13 + + include/dt-bindings/soc/stm32-hdp.h | 108 +++++ + include/env_internal.h | 1 + + include/fdtdec.h | 5 +- + include/image.h | 2 +- + include/lmb.h | 29 +- + include/mipi_dsi.h | 17 + + include/rproc_optee.h | 127 ++++++ + include/scmi_agent-uclass.h | 24 + + include/scmi_agent.h | 68 +++ + include/scmi_protocols.h | 179 ++++++++ + include/usb/dwc2_udc.h | 1 + + lib/Kconfig | 23 + + lib/fdtdec.c | 10 +- + lib/lmb.c | 108 +++-- + lib/optee/optee.c | 2 +- + scripts/config_whitelist.txt | 1 - + test/dm/Makefile | 1 + + test/dm/fdtdec.c | 9 +- + test/dm/ofnode.c | 12 + + test/dm/scmi.c | 203 +++++++++ + test/lib/lmb.c | 89 ++++ + 77 files changed, 3162 insertions(+), 282 deletions(-) + create mode 100644 doc/device-tree-bindings/arm/arm,scmi.txt + create mode 100644 drivers/clk/clk_scmi.c + create mode 100644 drivers/firmware/scmi/Kconfig + create mode 100644 drivers/firmware/scmi/Makefile + create mode 100644 drivers/firmware/scmi/mailbox_agent.c + create mode 100644 drivers/firmware/scmi/sandbox-scmi_agent.c + create mode 100644 drivers/firmware/scmi/sandbox-scmi_devices.c + create mode 100644 drivers/firmware/scmi/scmi_agent-uclass.c + create mode 100644 drivers/firmware/scmi/smccc_agent.c + create mode 100644 drivers/firmware/scmi/smt.c + create mode 100644 drivers/firmware/scmi/smt.h + create mode 100644 drivers/remoteproc/rproc-optee.c + create mode 100644 drivers/reset/reset-scmi.c + create mode 100644 include/dt-bindings/rtc/rtc-stm32.h + create mode 100644 include/dt-bindings/soc/stm32-hdp.h + create mode 100644 include/rproc_optee.h + create mode 100644 include/scmi_agent-uclass.h + create mode 100644 include/scmi_agent.h + create mode 100644 include/scmi_protocols.h + create mode 100644 test/dm/scmi.c + +diff --git a/common/Kconfig b/common/Kconfig +index 9c20a9738e..7099bbf902 100644 +--- a/common/Kconfig ++++ b/common/Kconfig +@@ -416,7 +416,7 @@ config USE_PREBOOT + config PREBOOT + string "preboot default value" + depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE +- default "usb start" if USB_KEYBOARD || USB_STORAGE ++ default "usb start" if USB_KEYBOARD + default "" + help + This is the default of "preboot" environment variable. +diff --git a/common/cli_readline.c b/common/cli_readline.c +index 1f1e28c6d8..491863303a 100644 +--- a/common/cli_readline.c ++++ b/common/cli_readline.c +@@ -15,6 +15,12 @@ + #include + #include + ++#ifdef CONFIG_SPL_BUILD ++#undef CONFIG_CMDLINE_EDITING ++#undef CONFIG_AUTO_COMPLETE ++#undef CONFIG_SHOW_ACTIVITY ++#endif ++ + DECLARE_GLOBAL_DATA_PTR; + + static const char erase_seq[] = "\b \b"; /* erase sequence */ +diff --git a/common/image-fdt.c b/common/image-fdt.c +index 3d6935ad40..55b3593762 100644 +--- a/common/image-fdt.c ++++ b/common/image-fdt.c +@@ -74,18 +74,20 @@ static const image_header_t *image_get_fdt(ulong fdt_addr) + #endif + + static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, +- uint64_t size) ++ uint64_t size, enum lmb_flags flags) + { + long ret; + +- ret = lmb_reserve(lmb, addr, size); ++ ret = lmb_reserve_flags(lmb, addr, size, flags); + if (ret >= 0) { +- debug(" reserving fdt memory region: addr=%llx size=%llx\n", +- (unsigned long long)addr, (unsigned long long)size); ++ debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", ++ (unsigned long long)addr, ++ (unsigned long long)size, flags); + } else { + puts("ERROR: reserving fdt memory region failed "); +- printf("(addr=%llx size=%llx)\n", +- (unsigned long long)addr, (unsigned long long)size); ++ printf("(addr=%llx size=%llx flags=%x)\n", ++ (unsigned long long)addr, ++ (unsigned long long)size, flags); + } + } + +@@ -105,6 +107,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) + int i, total, ret; + int nodeoffset, subnode; + struct fdt_resource res; ++ enum lmb_flags flags; + + if (fdt_check_header(fdt_blob) != 0) + return; +@@ -114,7 +117,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) + for (i = 0; i < total; i++) { + if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) + continue; +- boot_fdt_reserve_region(lmb, addr, size); ++ boot_fdt_reserve_region(lmb, addr, size, LMB_NONE); + } + + /* process reserved-memory */ +@@ -126,9 +129,13 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) + ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, + &res); + if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) { ++ flags = LMB_NONE; ++ if (fdtdec_get_bool(fdt_blob, subnode, ++ "no-map")) ++ flags = LMB_NOMAP; + addr = res.start; + size = res.end - res.start + 1; +- boot_fdt_reserve_region(lmb, addr, size); ++ boot_fdt_reserve_region(lmb, addr, size, flags); + } + + subnode = fdt_next_subnode(fdt_blob, subnode); +diff --git a/doc/device-tree-bindings/arm/arm,scmi.txt b/doc/device-tree-bindings/arm/arm,scmi.txt +new file mode 100644 +index 0000000000..1f293ea24c +--- /dev/null ++++ b/doc/device-tree-bindings/arm/arm,scmi.txt +@@ -0,0 +1,197 @@ ++System Control and Management Interface (SCMI) Message Protocol ++---------------------------------------------------------- ++ ++The SCMI is intended to allow agents such as OSPM to manage various functions ++that are provided by the hardware platform it is running on, including power ++and performance functions. ++ ++This binding is intended to define the interface the firmware implementing ++the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control ++and Management Interface Platform Design Document")[0] provide for OSPM in ++the device tree. ++ ++Required properties: ++ ++The scmi node with the following properties shall be under the /firmware/ node. ++ ++- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports ++- mboxes: List of phandle and mailbox channel specifiers. It should contain ++ exactly one or two mailboxes, one for transmitting messages("tx") ++ and another optional for receiving the notifications("rx") if ++ supported. ++- shmem : List of phandle pointing to the shared memory(SHM) area as per ++ generic mailbox client binding. ++- #address-cells : should be '1' if the device has sub-nodes, maps to ++ protocol identifier for a given sub-node. ++- #size-cells : should be '0' as 'reg' property doesn't have any size ++ associated with it. ++- arm,smc-id : SMC id required when using smc or hvc transports ++ ++Optional properties: ++ ++- mbox-names: shall be "tx" or "rx" depending on mboxes entries. ++ ++See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details ++about the generic mailbox controller and client driver bindings. ++ ++The mailbox is the only permitted method of calling the SCMI firmware. ++Mailbox doorbell is used as a mechanism to alert the presence of a ++messages and/or notification. ++ ++Each protocol supported shall have a sub-node with corresponding compatible ++as described in the following sections. If the platform supports dedicated ++communication channel for a particular protocol, the 3 properties namely: ++mboxes, mbox-names and shmem shall be present in the sub-node corresponding ++to that protocol. ++ ++Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol ++------------------------------------------------------------ ++ ++This binding uses the common clock binding[1]. ++ ++Required properties: ++- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. ++ ++Power domain bindings for the power domains based on SCMI Message Protocol ++------------------------------------------------------------ ++ ++This binding for the SCMI power domain providers uses the generic power ++domain binding[2]. ++ ++Required properties: ++ - #power-domain-cells : Should be 1. Contains the device or the power ++ domain ID value used by SCMI commands. ++ ++Sensor bindings for the sensors based on SCMI Message Protocol ++-------------------------------------------------------------- ++SCMI provides an API to access the various sensors on the SoC. ++ ++Required properties: ++- #thermal-sensor-cells: should be set to 1. This property follows the ++ thermal device tree bindings[3]. ++ ++ Valid cell values are raw identifiers (Sensor ID) ++ as used by the firmware. Refer to platform details ++ for your implementation for the IDs to use. ++ ++Reset signal bindings for the reset domains based on SCMI Message Protocol ++------------------------------------------------------------ ++ ++This binding for the SCMI reset domain providers uses the generic reset ++signal binding[5]. ++ ++Required properties: ++ - #reset-cells : Should be 1. Contains the reset domain ID value used ++ by SCMI commands. ++ ++SRAM and Shared Memory for SCMI ++------------------------------- ++ ++A small area of SRAM is reserved for SCMI communication between application ++processors and SCP. ++ ++The properties should follow the generic mmio-sram description found in [4] ++ ++Each sub-node represents the reserved area for SCMI. ++ ++Required sub-node properties: ++- reg : The base offset and size of the reserved area with the SRAM ++- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based ++ shared memory ++ ++[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html ++[1] Documentation/devicetree/bindings/clock/clock-bindings.txt ++[2] Documentation/devicetree/bindings/power/power-domain.yaml ++[3] Documentation/devicetree/bindings/thermal/thermal.txt ++[4] Documentation/devicetree/bindings/sram/sram.yaml ++[5] Documentation/devicetree/bindings/reset/reset.txt ++ ++Example: ++ ++sram@50000000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0x50000000 0x0 0x10000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x0 0x50000000 0x10000>; ++ ++ cpu_scp_lpri: scp-shmem@0 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x200>; ++ }; ++ ++ cpu_scp_hpri: scp-shmem@200 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x200 0x200>; ++ }; ++}; ++ ++mailbox@40000000 { ++ .... ++ #mbox-cells = <1>; ++ reg = <0x0 0x40000000 0x0 0x10000>; ++}; ++ ++firmware { ++ ++ ... ++ ++ scmi { ++ compatible = "arm,scmi"; ++ mboxes = <&mailbox 0 &mailbox 1>; ++ mbox-names = "tx", "rx"; ++ shmem = <&cpu_scp_lpri &cpu_scp_hpri>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ scmi_devpd: protocol@11 { ++ reg = <0x11>; ++ #power-domain-cells = <1>; ++ }; ++ ++ scmi_dvfs: protocol@13 { ++ reg = <0x13>; ++ #clock-cells = <1>; ++ }; ++ ++ scmi_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ ++ scmi_sensors0: protocol@15 { ++ reg = <0x15>; ++ #thermal-sensor-cells = <1>; ++ }; ++ ++ scmi_reset: protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <1>; ++ }; ++ }; ++}; ++ ++cpu@0 { ++ ... ++ reg = <0 0>; ++ clocks = <&scmi_dvfs 0>; ++}; ++ ++hdlcd@7ff60000 { ++ ... ++ reg = <0 0x7ff60000 0 0x1000>; ++ clocks = <&scmi_clk 4>; ++ power-domains = <&scmi_devpd 1>; ++ resets = <&scmi_reset 10>; ++}; ++ ++thermal-zones { ++ soc_thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <1000>; ++ /* sensor ID */ ++ thermal-sensors = <&scmi_sensors0 3>; ++ ... ++ }; ++}; +diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt +index da98407403..edfe4b426c 100644 +--- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt ++++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt +@@ -45,6 +45,8 @@ Required properties: + - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY + port#1 and must be <1> for PHY port#2, to select USB controller + ++Optional properties: ++- vbus-supply: phandle to the regulator providing 5V vbus to the USB connector + + Example: + usbphyc: usb-phy@5a006000 { +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index 6003e140b5..4dfbad7986 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -159,6 +159,14 @@ config CLK_CDCE9XX + Enable the clock synthesizer driver for CDCE913/925/937/949 + series of chips. + ++config CLK_SCMI ++ bool "Enable SCMI clock driver" ++ depends on SCMI_FIRMWARE ++ help ++ Enable this option if you want to support clock devices exposed ++ by a SCMI agent based on SCMI clock protocol communication ++ with a SCMI server. ++ + source "drivers/clk/analogbits/Kconfig" + source "drivers/clk/at91/Kconfig" + source "drivers/clk/exynos/Kconfig" +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index cda4b4b605..d1e295ac7c 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o + obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o + obj-$(CONFIG_CLK_OWL) += owl/ + obj-$(CONFIG_CLK_RENESAS) += renesas/ ++obj-$(CONFIG_CLK_SCMI) += clk_scmi.o + obj-$(CONFIG_CLK_SIFIVE) += sifive/ + obj-$(CONFIG_ARCH_SUNXI) += sunxi/ + obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o +diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c +new file mode 100644 +index 0000000000..93a4819501 +--- /dev/null ++++ b/drivers/clk/clk_scmi.c +@@ -0,0 +1,99 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019-2020 Linaro Limited ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int scmi_clk_gate(struct clk *clk, int enable) ++{ ++ struct scmi_clk_state_in in = { ++ .clock_id = clk->id, ++ .attributes = enable, ++ }; ++ struct scmi_clk_state_out out; ++ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, ++ SCMI_CLOCK_CONFIG_SET, ++ in, out); ++ int ret; ++ ++ ret = devm_scmi_process_msg(clk->dev->parent, &msg); ++ if (ret) ++ return ret; ++ ++ return scmi_to_linux_errno(out.status); ++} ++ ++static int scmi_clk_enable(struct clk *clk) ++{ ++ return scmi_clk_gate(clk, 1); ++} ++ ++static int scmi_clk_disable(struct clk *clk) ++{ ++ return scmi_clk_gate(clk, 0); ++} ++ ++static ulong scmi_clk_get_rate(struct clk *clk) ++{ ++ struct scmi_clk_rate_get_in in = { ++ .clock_id = clk->id, ++ }; ++ struct scmi_clk_rate_get_out out; ++ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, ++ SCMI_CLOCK_RATE_GET, ++ in, out); ++ int ret; ++ ++ ret = devm_scmi_process_msg(clk->dev->parent, &msg); ++ if (ret < 0) ++ return ret; ++ ++ ret = scmi_to_linux_errno(out.status); ++ if (ret < 0) ++ return ret; ++ ++ return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb); ++} ++ ++static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) ++{ ++ struct scmi_clk_rate_set_in in = { ++ .clock_id = clk->id, ++ .flags = SCMI_CLK_RATE_ROUND_CLOSEST, ++ .rate_lsb = (u32)rate, ++ .rate_msb = (u32)((u64)rate >> 32), ++ }; ++ struct scmi_clk_rate_set_out out; ++ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, ++ SCMI_CLOCK_RATE_SET, ++ in, out); ++ int ret; ++ ++ ret = devm_scmi_process_msg(clk->dev->parent, &msg); ++ if (ret < 0) ++ return ret; ++ ++ ret = scmi_to_linux_errno(out.status); ++ if (ret < 0) ++ return ret; ++ ++ return scmi_clk_get_rate(clk); ++} ++ ++static const struct clk_ops scmi_clk_ops = { ++ .enable = scmi_clk_enable, ++ .disable = scmi_clk_disable, ++ .get_rate = scmi_clk_get_rate, ++ .set_rate = scmi_clk_set_rate, ++}; ++ ++U_BOOT_DRIVER(scmi_clock) = { ++ .name = "scmi_clk", ++ .id = UCLASS_CLK, ++ .ops = &scmi_clk_ops, ++}; +diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c +index c8840b9e5f..efa402da52 100644 +--- a/drivers/clk/clk_stm32mp1.c ++++ b/drivers/clk/clk_stm32mp1.c +@@ -246,7 +246,7 @@ DECLARE_GLOBAL_DATA_PTR; + enum stm32mp1_parent_id { + /* + * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved +- * they are used as index in osc[] as entry point ++ * they are used as index in osc_clk[] as clock reference + */ + _HSI, + _HSE, +@@ -426,8 +426,7 @@ struct stm32mp1_clk_data { + struct stm32mp1_clk_priv { + fdt_addr_t base; + const struct stm32mp1_clk_data *data; +- ulong osc[NB_OSC]; +- struct udevice *osc_dev[NB_OSC]; ++ struct clk osc_clk[NB_OSC]; + }; + + #define STM32MP1_CLK(off, b, idx, s) \ +@@ -546,6 +545,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), ++ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), + +@@ -785,7 +785,7 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) + return 0; + } + +- return priv->osc[idx]; ++ return clk_get_rate(&priv->osc_clk[idx]); + } + + static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) +@@ -1546,7 +1546,7 @@ static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) + break; + + if (hsidiv == 4) { +- pr_err("clk-hsi frequency invalid"); ++ pr_err("hsi frequency invalid"); + return -1; + } + +@@ -1953,13 +1953,13 @@ static int stm32mp1_clktree(struct udevice *dev) + * switch ON oscillator found in device-tree, + * HSI already ON after bootrom + */ +- if (priv->osc[_LSI]) ++ if (clk_valid(&priv->osc_clk[_LSI])) + stm32mp1_lsi_set(rcc, 1); + +- if (priv->osc[_LSE]) { ++ if (clk_valid(&priv->osc_clk[_LSE])) { + int bypass, digbyp; + u32 lsedrv; +- struct udevice *dev = priv->osc_dev[_LSE]; ++ struct udevice *dev = priv->osc_clk[_LSE].dev; + + bypass = dev_read_bool(dev, "st,bypass"); + digbyp = dev_read_bool(dev, "st,digbypass"); +@@ -1970,9 +1970,9 @@ static int stm32mp1_clktree(struct udevice *dev) + stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); + } + +- if (priv->osc[_HSE]) { ++ if (clk_valid(&priv->osc_clk[_HSE])) { + int bypass, digbyp, css; +- struct udevice *dev = priv->osc_dev[_HSE]; ++ struct udevice *dev = priv->osc_clk[_HSE].dev; + + bypass = dev_read_bool(dev, "st,bypass"); + digbyp = dev_read_bool(dev, "st,digbypass"); +@@ -1997,8 +1997,8 @@ static int stm32mp1_clktree(struct udevice *dev) + + /* configure HSIDIV */ + debug("configure HSIDIV\n"); +- if (priv->osc[_HSI]) { +- stm32mp1_hsidiv(rcc, priv->osc[_HSI]); ++ if (clk_valid(&priv->osc_clk[_HSI])) { ++ stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI])); + stgen_config(priv); + } + +@@ -2044,7 +2044,7 @@ static int stm32mp1_clktree(struct udevice *dev) + } + + /* wait LSE ready before to use it */ +- if (priv->osc[_LSE]) ++ if (clk_valid(&priv->osc_clk[_LSE])) + stm32mp1_lse_wait(rcc); + + /* configure with expected clock source */ +@@ -2083,7 +2083,7 @@ static int stm32mp1_clktree(struct udevice *dev) + + debug("oscillator off\n"); + /* switch OFF HSI if not found in device-tree */ +- if (!priv->osc[_HSI]) ++ if (!clk_valid(&priv->osc_clk[_HSI])) + stm32mp1_hsi_set(rcc, 0); + + /* Software Self-Refresh mode (SSR) during DDR initilialization */ +@@ -2181,40 +2181,25 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) + return -EINVAL; + } + +-static void stm32mp1_osc_clk_init(const char *name, +- struct stm32mp1_clk_priv *priv, +- int index) +-{ +- struct clk clk; +- struct udevice *dev = NULL; +- +- priv->osc[index] = 0; +- clk.id = 0; +- if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { +- if (clk_request(dev, &clk)) +- pr_err("%s request", name); +- else +- priv->osc[index] = clk_get_rate(&clk); +- } +- priv->osc_dev[index] = dev; +-} +- + static void stm32mp1_osc_init(struct udevice *dev) + { + struct stm32mp1_clk_priv *priv = dev_get_priv(dev); + int i; + const char *name[NB_OSC] = { +- [_LSI] = "clk-lsi", +- [_LSE] = "clk-lse", +- [_HSI] = "clk-hsi", +- [_HSE] = "clk-hse", +- [_CSI] = "clk-csi", ++ [_LSI] = "lsi", ++ [_LSE] = "lse", ++ [_HSI] = "hsi", ++ [_HSE] = "hse", ++ [_CSI] = "csi", + [_I2S_CKIN] = "i2s_ckin", + }; + + for (i = 0; i < NB_OSC; i++) { +- stm32mp1_osc_clk_init(name[i], priv, i); +- debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); ++ if (clk_get_by_name(dev, name[i], &priv->osc_clk[i])) ++ dev_dbg(dev, "No source clock \"%s\"", name[i]); ++ else ++ dev_dbg(dev, "%s clock rate: %luHz\n", ++ name[i], clk_get_rate(&priv->osc_clk[i])); + } + } + +diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c +index d02d8d33fe..2b848cc870 100644 +--- a/drivers/core/ofnode.c ++++ b/drivers/core/ofnode.c +@@ -226,6 +226,16 @@ int ofnode_read_u32_array(ofnode node, const char *propname, + } + } + ++bool ofnode_is_enabled(ofnode node) ++{ ++ if (ofnode_is_np(node)) { ++ return of_device_is_available(ofnode_to_np(node)); ++ } else { ++ return fdtdec_get_is_enabled(gd->fdt_blob, ++ ofnode_to_offset(node)); ++ } ++} ++ + ofnode ofnode_first_subnode(ofnode node) + { + assert(ofnode_valid(node)); +diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c +index 36cd4e945b..8c6c342a75 100644 +--- a/drivers/dfu/dfu_mtd.c ++++ b/drivers/dfu/dfu_mtd.c +@@ -190,7 +190,7 @@ static int dfu_flush_medium_mtd(struct dfu_entity *dfu) + int ret; + + /* in case of ubi partition, erase rest of the partition */ +- if (dfu->data.nand.ubi) { ++ if (dfu->data.mtd.ubi) { + struct erase_info erase_op = {}; + + erase_op.mtd = dfu->data.mtd.info; +@@ -228,7 +228,7 @@ static unsigned int dfu_polltimeout_mtd(struct dfu_entity *dfu) + * ubi partition, as sectors which are not used need + * to be erased + */ +- if (dfu->data.nand.ubi) ++ if (dfu->data.mtd.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +@@ -238,7 +238,6 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) + { + char *st; + struct mtd_info *mtd; +- bool has_pages; + int ret, part; + + mtd = get_mtd_device_nm(devstr); +@@ -248,9 +247,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) + + dfu->dev_type = DFU_DEV_MTD; + dfu->data.mtd.info = mtd; +- +- has_pages = mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; +- dfu->max_buf_size = has_pages ? mtd->erasesize : 0; ++ dfu->max_buf_size = mtd->erasesize; + + st = strsep(&s, " "); + if (!strcmp(st, "raw")) { +diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig +index b70a206355..ef958b3a7a 100644 +--- a/drivers/firmware/Kconfig ++++ b/drivers/firmware/Kconfig +@@ -36,3 +36,5 @@ config ZYNQMP_FIRMWARE + various platform management services. + Say yes to enable ZynqMP firmware interface driver. + If in doubt, say N. ++ ++source "drivers/firmware/scmi/Kconfig" +diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile +index a0c250a473..7ce83d72bd 100644 +--- a/drivers/firmware/Makefile ++++ b/drivers/firmware/Makefile +@@ -3,3 +3,4 @@ obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o + obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o + obj-$(CONFIG_SANDBOX) += firmware-sandbox.o + obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o ++obj-$(CONFIG_SCMI_FIRMWARE) += scmi/ +diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig +new file mode 100644 +index 0000000000..c3a109beac +--- /dev/null ++++ b/drivers/firmware/scmi/Kconfig +@@ -0,0 +1,19 @@ ++config SCMI_FIRMWARE ++ bool "Enable SCMI support" ++ select FIRMWARE ++ select OF_TRANSLATE ++ depends on SANDBOX || DM_MAILBOX || ARM_SMCCC ++ help ++ System Control and Management Interface (SCMI) is a communication ++ protocol that defines standard interfaces for power, performance ++ and system management. The SCMI specification is available at ++ https://developer.arm.com/architectures/system-architectures/software-standards/scmi ++ ++ An SCMI agent communicates with a related SCMI server firmware ++ located in another sub-system, as a companion micro controller ++ or a companion host in the CPU system. ++ ++ Communications between agent (client) and the SCMI server are ++ based on message exchange. Messages can be exchange over tranport ++ channels as a mailbox device or an Arm SMCCC service with some ++ piece of identified shared memory. +diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile +new file mode 100644 +index 0000000000..e1e0224066 +--- /dev/null ++++ b/drivers/firmware/scmi/Makefile +@@ -0,0 +1,5 @@ ++obj-y += scmi_agent-uclass.o ++obj-y += smt.o ++obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o ++obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o ++obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o +diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c +new file mode 100644 +index 0000000000..7d9fb3622e +--- /dev/null ++++ b/drivers/firmware/scmi/mailbox_agent.c +@@ -0,0 +1,102 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 Linaro Limited. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "smt.h" ++ ++#define TIMEOUT_US_10MS 10000 ++ ++/** ++ * struct scmi_mbox_channel - Description of an SCMI mailbox transport ++ * @smt: Shared memory buffer ++ * @mbox: Mailbox channel description ++ * @timeout_us: Timeout in microseconds for the mailbox transfer ++ */ ++struct scmi_mbox_channel { ++ struct scmi_smt smt; ++ struct mbox_chan mbox; ++ ulong timeout_us; ++}; ++ ++static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) ++{ ++ struct scmi_mbox_channel *chan = dev_get_priv(dev); ++ int ret; ++ ++ ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); ++ if (ret) ++ return ret; ++ ++ /* Give shm addr to mbox in case it is meaningful */ ++ ret = mbox_send(&chan->mbox, chan->smt.buf); ++ if (ret) { ++ dev_err(dev, "Message send failed: %d\n", ret); ++ goto out; ++ } ++ ++ /* Receive the response */ ++ ret = mbox_recv(&chan->mbox, chan->smt.buf, chan->timeout_us); ++ if (ret) { ++ dev_err(dev, "Response failed: %d, abort\n", ret); ++ goto out; ++ } ++ ++ ret = scmi_read_resp_from_smt(dev, &chan->smt, msg); ++ ++out: ++ scmi_clear_smt_channel(&chan->smt); ++ ++ return ret; ++} ++ ++int scmi_mbox_probe(struct udevice *dev) ++{ ++ struct scmi_mbox_channel *chan = dev_get_priv(dev); ++ int ret; ++ ++ chan->timeout_us = TIMEOUT_US_10MS; ++ ++ ret = mbox_get_by_index(dev, 0, &chan->mbox); ++ if (ret) { ++ dev_err(dev, "Failed to find mailbox: %d\n", ret); ++ goto out; ++ } ++ ++ ret = scmi_dt_get_smt_buffer(dev, &chan->smt); ++ if (ret) ++ dev_err(dev, "Failed to get shm resources: %d\n", ret); ++ ++out: ++ if (ret) ++ devm_kfree(dev, chan); ++ ++ return ret; ++} ++ ++static const struct udevice_id scmi_mbox_ids[] = { ++ { .compatible = "arm,scmi" }, ++ { } ++}; ++ ++static const struct scmi_agent_ops scmi_mbox_ops = { ++ .process_msg = scmi_mbox_process_msg, ++}; ++ ++U_BOOT_DRIVER(scmi_mbox) = { ++ .name = "scmi-over-mailbox", ++ .id = UCLASS_SCMI_AGENT, ++ .of_match = scmi_mbox_ids, ++ .priv_auto_alloc_size = sizeof(struct scmi_mbox_channel), ++ .probe = scmi_mbox_probe, ++ .ops = &scmi_mbox_ops, ++}; +diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c +new file mode 100644 +index 0000000000..5b6a4232af +--- /dev/null ++++ b/drivers/firmware/scmi/sandbox-scmi_agent.c +@@ -0,0 +1,410 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020, Linaro Limited ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * The sandbox SCMI agent driver simulates to some extend a SCMI message ++ * processing. It simulates few of the SCMI services for some of the ++ * SCMI protocols embedded in U-Boot. Currently: ++ * - SCMI clock protocol: emulate 2 agents each exposing few clocks ++ * - SCMI reset protocol: emulate 1 agents each exposing a reset ++ * ++ * Agent #0 simulates 2 clocks and 1 reset domain. ++ * See IDs in scmi0_clk[]/scmi0_reset[] and "sandbox-scmi-agent@0" in test.dts. ++ * ++ * Agent #1 simulates 1 clock. ++ * See IDs in scmi1_clk[] and "sandbox-scmi-agent@1" in test.dts. ++ * ++ * All clocks are default disabled and reset levels down. ++ * ++ * This Driver exports sandbox_scmi_service_ct() for the test sequence to ++ * get the state of the simulated services (clock state, rate, ...) and ++ * check back-end device state reflects the request send through the ++ * various uclass devices, as clocks and reset controllers. ++ */ ++ ++#define SANDBOX_SCMI_AGENT_COUNT 2 ++ ++static struct sandbox_scmi_clk scmi0_clk[] = { ++ { .id = 7, .rate = 1000 }, ++ { .id = 3, .rate = 333 }, ++}; ++ ++static struct sandbox_scmi_reset scmi0_reset[] = { ++ { .id = 3 }, ++}; ++ ++static struct sandbox_scmi_clk scmi1_clk[] = { ++ { .id = 1, .rate = 44 }, ++}; ++ ++/* The list saves to simulted end devices references for test purpose */ ++struct sandbox_scmi_agent *sandbox_scmi_agent_list[SANDBOX_SCMI_AGENT_COUNT]; ++ ++static struct sandbox_scmi_service sandbox_scmi_service_state = { ++ .agent = sandbox_scmi_agent_list, ++ .agent_count = SANDBOX_SCMI_AGENT_COUNT, ++}; ++ ++struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) ++{ ++ return &sandbox_scmi_service_state; ++} ++ ++static void debug_print_agent_state(struct udevice *dev, char *str) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ ++ dev_dbg(dev, "Dump sandbox_scmi_agent %u: %s\n", agent->idx, str); ++ dev_dbg(dev, " scmi%u_clk (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n", ++ agent->idx, ++ agent->clk_count, ++ agent->clk_count ? agent->clk[0].enabled : -1, ++ agent->clk_count ? agent->clk[0].rate : -1, ++ agent->clk_count > 1 ? agent->clk[1].enabled : -1, ++ agent->clk_count > 1 ? agent->clk[1].rate : -1, ++ agent->clk_count > 2 ? agent->clk[2].enabled : -1, ++ agent->clk_count > 2 ? agent->clk[2].rate : -1); ++ dev_dbg(dev, " scmi%u_reset (%zu): %d, %d, ...\n", ++ agent->idx, ++ agent->reset_count, ++ agent->reset_count ? agent->reset[0].asserted : -1, ++ agent->reset_count > 1 ? agent->reset[1].asserted : -1); ++}; ++ ++static struct sandbox_scmi_clk *get_scmi_clk_state(uint agent_id, uint clock_id) ++{ ++ struct sandbox_scmi_clk *target = NULL; ++ size_t target_count = 0; ++ size_t n; ++ ++ switch (agent_id) { ++ case 0: ++ target = scmi0_clk; ++ target_count = ARRAY_SIZE(scmi0_clk); ++ break; ++ case 1: ++ target = scmi1_clk; ++ target_count = ARRAY_SIZE(scmi1_clk); ++ break; ++ default: ++ return NULL; ++ } ++ ++ for (n = 0; n < target_count; n++) ++ if (target[n].id == clock_id) ++ return target + n; ++ ++ return NULL; ++} ++ ++static struct sandbox_scmi_reset *get_scmi_reset_state(uint agent_id, ++ uint reset_id) ++{ ++ size_t n; ++ ++ if (agent_id == 0) { ++ for (n = 0; n < ARRAY_SIZE(scmi0_reset); n++) ++ if (scmi0_reset[n].id == reset_id) ++ return scmi0_reset + n; ++ } ++ ++ return NULL; ++} ++ ++/* ++ * Sandbox SCMI agent ops ++ */ ++ ++static int sandbox_scmi_clock_rate_set(struct udevice *dev, ++ struct scmi_msg *msg) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ struct scmi_clk_rate_set_in *in = NULL; ++ struct scmi_clk_rate_set_out *out = NULL; ++ struct sandbox_scmi_clk *clk_state = NULL; ++ ++ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || ++ !msg->out_msg || msg->out_msg_sz < sizeof(*out)) ++ return -EINVAL; ++ ++ in = (struct scmi_clk_rate_set_in *)msg->in_msg; ++ out = (struct scmi_clk_rate_set_out *)msg->out_msg; ++ ++ clk_state = get_scmi_clk_state(agent->idx, in->clock_id); ++ if (!clk_state) { ++ dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); ++ ++ out->status = SCMI_NOT_FOUND; ++ } else { ++ u64 rate = ((u64)in->rate_msb << 32) + in->rate_lsb; ++ ++ clk_state->rate = (ulong)rate; ++ ++ out->status = SCMI_SUCCESS; ++ } ++ ++ return 0; ++} ++ ++static int sandbox_scmi_clock_rate_get(struct udevice *dev, ++ struct scmi_msg *msg) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ struct scmi_clk_rate_get_in *in = NULL; ++ struct scmi_clk_rate_get_out *out = NULL; ++ struct sandbox_scmi_clk *clk_state = NULL; ++ ++ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || ++ !msg->out_msg || msg->out_msg_sz < sizeof(*out)) ++ return -EINVAL; ++ ++ in = (struct scmi_clk_rate_get_in *)msg->in_msg; ++ out = (struct scmi_clk_rate_get_out *)msg->out_msg; ++ ++ clk_state = get_scmi_clk_state(agent->idx, in->clock_id); ++ if (!clk_state) { ++ dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); ++ ++ out->status = SCMI_NOT_FOUND; ++ } else { ++ out->rate_msb = (u32)((u64)clk_state->rate >> 32); ++ out->rate_lsb = (u32)clk_state->rate; ++ ++ out->status = SCMI_SUCCESS; ++ } ++ ++ return 0; ++} ++ ++static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ struct scmi_clk_state_in *in = NULL; ++ struct scmi_clk_state_out *out = NULL; ++ struct sandbox_scmi_clk *clk_state = NULL; ++ ++ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || ++ !msg->out_msg || msg->out_msg_sz < sizeof(*out)) ++ return -EINVAL; ++ ++ in = (struct scmi_clk_state_in *)msg->in_msg; ++ out = (struct scmi_clk_state_out *)msg->out_msg; ++ ++ clk_state = get_scmi_clk_state(agent->idx, in->clock_id); ++ if (!clk_state) { ++ dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); ++ ++ out->status = SCMI_NOT_FOUND; ++ } else if (in->attributes > 1) { ++ out->status = SCMI_PROTOCOL_ERROR; ++ } else { ++ clk_state->enabled = in->attributes; ++ ++ out->status = SCMI_SUCCESS; ++ } ++ ++ return 0; ++} ++ ++static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ struct scmi_rd_attr_in *in = NULL; ++ struct scmi_rd_attr_out *out = NULL; ++ struct sandbox_scmi_reset *reset_state = NULL; ++ ++ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || ++ !msg->out_msg || msg->out_msg_sz < sizeof(*out)) ++ return -EINVAL; ++ ++ in = (struct scmi_rd_attr_in *)msg->in_msg; ++ out = (struct scmi_rd_attr_out *)msg->out_msg; ++ ++ reset_state = get_scmi_reset_state(agent->idx, in->domain_id); ++ if (!reset_state) { ++ dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id); ++ ++ out->status = SCMI_NOT_FOUND; ++ } else { ++ memset(out, 0, sizeof(*out)); ++ snprintf(out->name, sizeof(out->name), "rd%u", in->domain_id); ++ ++ out->status = SCMI_SUCCESS; ++ } ++ ++ return 0; ++} ++ ++static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ struct scmi_rd_reset_in *in = NULL; ++ struct scmi_rd_reset_out *out = NULL; ++ struct sandbox_scmi_reset *reset_state = NULL; ++ ++ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || ++ !msg->out_msg || msg->out_msg_sz < sizeof(*out)) ++ return -EINVAL; ++ ++ in = (struct scmi_rd_reset_in *)msg->in_msg; ++ out = (struct scmi_rd_reset_out *)msg->out_msg; ++ ++ reset_state = get_scmi_reset_state(agent->idx, in->domain_id); ++ if (!reset_state) { ++ dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id); ++ ++ out->status = SCMI_NOT_FOUND; ++ } else if (in->reset_state > 1) { ++ dev_err(dev, "Invalid reset domain input attribute value\n"); ++ ++ out->status = SCMI_INVALID_PARAMETERS; ++ } else { ++ if (in->flags & SCMI_RD_RESET_FLAG_CYCLE) { ++ if (in->flags & SCMI_RD_RESET_FLAG_ASYNC) { ++ out->status = SCMI_NOT_SUPPORTED; ++ } else { ++ /* Ends deasserted whatever current state */ ++ reset_state->asserted = false; ++ out->status = SCMI_SUCCESS; ++ } ++ } else { ++ reset_state->asserted = in->flags & ++ SCMI_RD_RESET_FLAG_ASSERT; ++ ++ out->status = SCMI_SUCCESS; ++ } ++ } ++ ++ return 0; ++} ++ ++static int sandbox_scmi_test_process_msg(struct udevice *dev, ++ struct scmi_msg *msg) ++{ ++ switch (msg->protocol_id) { ++ case SCMI_PROTOCOL_ID_CLOCK: ++ switch (msg->message_id) { ++ case SCMI_CLOCK_RATE_SET: ++ return sandbox_scmi_clock_rate_set(dev, msg); ++ case SCMI_CLOCK_RATE_GET: ++ return sandbox_scmi_clock_rate_get(dev, msg); ++ case SCMI_CLOCK_CONFIG_SET: ++ return sandbox_scmi_clock_gate(dev, msg); ++ default: ++ break; ++ } ++ break; ++ case SCMI_PROTOCOL_ID_RESET_DOMAIN: ++ switch (msg->message_id) { ++ case SCMI_RESET_DOMAIN_ATTRIBUTES: ++ return sandbox_scmi_rd_attribs(dev, msg); ++ case SCMI_RESET_DOMAIN_RESET: ++ return sandbox_scmi_rd_reset(dev, msg); ++ default: ++ break; ++ } ++ break; ++ case SCMI_PROTOCOL_ID_BASE: ++ case SCMI_PROTOCOL_ID_POWER_DOMAIN: ++ case SCMI_PROTOCOL_ID_SYSTEM: ++ case SCMI_PROTOCOL_ID_PERF: ++ case SCMI_PROTOCOL_ID_SENSOR: ++ *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED; ++ return 0; ++ default: ++ break; ++ } ++ ++ dev_err(dev, "%s(%s): Unhandled protocol_id %#x/message_id %#x\n", ++ __func__, dev->name, msg->protocol_id, msg->message_id); ++ ++ if (msg->out_msg_sz < sizeof(u32)) ++ return -EINVAL; ++ ++ /* Intentionnaly report unhandled IDs through the SCMI return code */ ++ *(u32 *)msg->out_msg = SCMI_PROTOCOL_ERROR; ++ return 0; ++} ++ ++static int sandbox_scmi_test_remove(struct udevice *dev) ++{ ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ ++ debug_print_agent_state(dev, "removed"); ++ ++ /* We only need to dereference the agent in the context */ ++ sandbox_scmi_service_ctx()->agent[agent->idx] = NULL; ++ ++ return 0; ++} ++ ++static int sandbox_scmi_test_probe(struct udevice *dev) ++{ ++ static const char basename[] = "sandbox-scmi-agent@"; ++ struct sandbox_scmi_agent *agent = dev_get_priv(dev); ++ const size_t basename_size = sizeof(basename) - 1; ++ ++ if (strncmp(basename, dev->name, basename_size)) ++ return -ENOENT; ++ ++ switch (dev->name[basename_size]) { ++ case '0': ++ *agent = (struct sandbox_scmi_agent){ ++ .idx = 0, ++ .clk = scmi0_clk, ++ .clk_count = ARRAY_SIZE(scmi0_clk), ++ .reset = scmi0_reset, ++ .reset_count = ARRAY_SIZE(scmi0_reset), ++ }; ++ break; ++ case '1': ++ *agent = (struct sandbox_scmi_agent){ ++ .idx = 1, ++ .clk = scmi1_clk, ++ .clk_count = ARRAY_SIZE(scmi1_clk), ++ }; ++ break; ++ default: ++ dev_err(dev, "%s(): Unexpected agent ID %s\n", ++ __func__, dev->name + basename_size); ++ return -ENOENT; ++ } ++ ++ debug_print_agent_state(dev, "probed"); ++ ++ /* Save reference for tests purpose */ ++ sandbox_scmi_service_ctx()->agent[agent->idx] = agent; ++ ++ return 0; ++}; ++ ++static const struct udevice_id sandbox_scmi_test_ids[] = { ++ { .compatible = "sandbox,scmi-agent" }, ++ { } ++}; ++ ++struct scmi_agent_ops sandbox_scmi_test_ops = { ++ .process_msg = sandbox_scmi_test_process_msg, ++}; ++ ++U_BOOT_DRIVER(sandbox_scmi_agent) = { ++ .name = "sandbox-scmi_agent", ++ .id = UCLASS_SCMI_AGENT, ++ .of_match = sandbox_scmi_test_ids, ++ .priv_auto_alloc_size = sizeof(struct sandbox_scmi_agent), ++ .probe = sandbox_scmi_test_probe, ++ .remove = sandbox_scmi_test_remove, ++ .ops = &sandbox_scmi_test_ops, ++}; +diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c +new file mode 100644 +index 0000000000..c69967bf69 +--- /dev/null ++++ b/drivers/firmware/scmi/sandbox-scmi_devices.c +@@ -0,0 +1,113 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020, Linaro Limited ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * Simulate to some extent a SCMI exchange. ++ * This drivers gets SCMI resources and offers API function to the ++ * SCMI test sequence manipulate the resources, currently clock ++ * and reset controllers. ++ */ ++ ++#define SCMI_TEST_DEVICES_CLK_COUNT 3 ++#define SCMI_TEST_DEVICES_RD_COUNT 1 ++ ++/* ++ * struct sandbox_scmi_device_priv - Storage for device handles used by test ++ * @clk: Array of clock instances used by tests ++ * @reset_clt: Array of the reset controller instances used by tests ++ * @devices: Resources exposed by sandbox_scmi_devices_ctx() ++ */ ++struct sandbox_scmi_device_priv { ++ struct clk clk[SCMI_TEST_DEVICES_CLK_COUNT]; ++ struct reset_ctl reset_ctl[SCMI_TEST_DEVICES_RD_COUNT]; ++ struct sandbox_scmi_devices devices; ++}; ++ ++struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev) ++{ ++ struct sandbox_scmi_device_priv *priv = dev_get_priv(dev); ++ ++ if (priv) ++ return &priv->devices; ++ ++ return NULL; ++} ++ ++static int sandbox_scmi_devices_remove(struct udevice *dev) ++{ ++ struct sandbox_scmi_devices *devices = sandbox_scmi_devices_ctx(dev); ++ int ret = 0; ++ size_t n; ++ ++ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { ++ int ret2 = reset_free(devices->reset + n); ++ ++ if (ret2 && !ret) ++ ret = ret2; ++ } ++ ++ return ret; ++} ++ ++static int sandbox_scmi_devices_probe(struct udevice *dev) ++{ ++ struct sandbox_scmi_device_priv *priv = dev_get_priv(dev); ++ int ret; ++ size_t n; ++ ++ priv->devices = (struct sandbox_scmi_devices){ ++ .clk = priv->clk, ++ .clk_count = SCMI_TEST_DEVICES_CLK_COUNT, ++ .reset = priv->reset_ctl, ++ .reset_count = SCMI_TEST_DEVICES_RD_COUNT, ++ }; ++ ++ for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) { ++ ret = clk_get_by_index(dev, n, priv->devices.clk + n); ++ if (ret) { ++ dev_err(dev, "%s: Failed on clk %zu\n", __func__, n); ++ return ret; ++ } ++ } ++ ++ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { ++ ret = reset_get_by_index(dev, n, priv->devices.reset + n); ++ if (ret) { ++ dev_err(dev, "%s: Failed on reset %zu\n", __func__, n); ++ goto err_reset; ++ } ++ } ++ ++ return 0; ++ ++err_reset: ++ for (; n > 0; n--) ++ reset_free(priv->devices.reset + n - 1); ++ ++ return ret; ++} ++ ++static const struct udevice_id sandbox_scmi_devices_ids[] = { ++ { .compatible = "sandbox,scmi-devices" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sandbox_scmi_devices) = { ++ .name = "sandbox-scmi_devices", ++ .id = UCLASS_MISC, ++ .of_match = sandbox_scmi_devices_ids, ++ .priv_auto_alloc_size = sizeof(struct sandbox_scmi_device_priv), ++ .remove = sandbox_scmi_devices_remove, ++ .probe = sandbox_scmi_devices_probe, ++}; +diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c +new file mode 100644 +index 0000000000..77160b1999 +--- /dev/null ++++ b/drivers/firmware/scmi/scmi_agent-uclass.c +@@ -0,0 +1,119 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 Linaro Limited. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/** ++ * struct error_code - Helper structure for SCMI error code conversion ++ * @scmi: SCMI error code ++ * @errno: Related standard error number ++ */ ++struct error_code { ++ int scmi; ++ int errno; ++}; ++ ++static const struct error_code scmi_linux_errmap[] = { ++ { .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, }, ++ { .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, }, ++ { .scmi = SCMI_DENIED, .errno = -EACCES, }, ++ { .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, }, ++ { .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, }, ++ { .scmi = SCMI_BUSY, .errno = -EBUSY, }, ++ { .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, }, ++ { .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, }, ++ { .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, }, ++ { .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, }, ++}; ++ ++int scmi_to_linux_errno(s32 scmi_code) ++{ ++ int n; ++ ++ if (!scmi_code) ++ return 0; ++ ++ for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++) ++ if (scmi_code == scmi_linux_errmap[n].scmi) ++ return scmi_linux_errmap[1].errno; ++ ++ return -EPROTO; ++} ++ ++/* ++ * SCMI agent devices binds devices of various uclasses depeding on ++ * the FDT description. scmi_bind_protocol() is a generic bind sequence ++ * called by the uclass at bind stage, that is uclass post_bind. ++ */ ++static int scmi_bind_protocols(struct udevice *dev) ++{ ++ int ret = 0; ++ ofnode node; ++ ++ dev_for_each_subnode(node, dev) { ++ struct driver *drv = NULL; ++ u32 protocol_id; ++ ++ if (!ofnode_is_available(node)) ++ continue; ++ ++ if (ofnode_read_u32(node, "reg", &protocol_id)) ++ continue; ++ ++ switch (protocol_id) { ++ case SCMI_PROTOCOL_ID_CLOCK: ++ if (IS_ENABLED(CONFIG_CLK_SCMI)) ++ drv = DM_GET_DRIVER(scmi_clock); ++ break; ++ case SCMI_PROTOCOL_ID_RESET_DOMAIN: ++ if (IS_ENABLED(CONFIG_RESET_SCMI)) ++ drv = DM_GET_DRIVER(scmi_reset_domain); ++ break; ++ default: ++ break; ++ } ++ ++ if (!drv) { ++ dev_dbg(dev, "Ignore unsupported SCMI protocol %#x\n", ++ protocol_id); ++ continue; ++ } ++ ++ ret = device_bind_ofnode(dev, drv, ofnode_get_name(node), ++ NULL, node, NULL); ++ if (ret) ++ break; ++ } ++ ++ return ret; ++} ++ ++static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev) ++{ ++ return (const struct scmi_agent_ops *)dev->driver->ops; ++} ++ ++int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg) ++{ ++ const struct scmi_agent_ops *ops = transport_dev_ops(dev); ++ ++ if (ops->process_msg) ++ return ops->process_msg(dev, msg); ++ ++ return -EPROTONOSUPPORT; ++} ++ ++UCLASS_DRIVER(scmi_agent) = { ++ .id = UCLASS_SCMI_AGENT, ++ .name = "scmi_agent", ++ .post_bind = scmi_bind_protocols, ++}; +diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c +new file mode 100644 +index 0000000000..85dbf9195e +--- /dev/null ++++ b/drivers/firmware/scmi/smccc_agent.c +@@ -0,0 +1,89 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 Linaro Limited. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "smt.h" ++ ++#define SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) ++ ++/** ++ * struct scmi_smccc_channel - Description of an SCMI SMCCC transport ++ * @func_id: SMCCC function ID used by the SCMI transport ++ * @smt: Shared memory buffer ++ */ ++struct scmi_smccc_channel { ++ ulong func_id; ++ struct scmi_smt smt; ++}; ++ ++static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) ++{ ++ struct scmi_smccc_channel *chan = dev_get_priv(dev); ++ struct arm_smccc_res res; ++ int ret; ++ ++ ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); ++ if (ret) ++ return ret; ++ ++ arm_smccc_smc(chan->func_id, 0, 0, 0, 0, 0, 0, 0, &res); ++ if (res.a0 == SMCCC_RET_NOT_SUPPORTED) ++ ret = -ENXIO; ++ else ++ ret = scmi_read_resp_from_smt(dev, &chan->smt, msg); ++ ++ scmi_clear_smt_channel(&chan->smt); ++ ++ return ret; ++} ++ ++static int scmi_smccc_probe(struct udevice *dev) ++{ ++ struct scmi_smccc_channel *chan = dev_get_priv(dev); ++ u32 func_id; ++ int ret; ++ ++ if (dev_read_u32(dev, "arm,smc-id", &func_id)) { ++ dev_err(dev, "Missing property func-id\n"); ++ return -EINVAL; ++ } ++ ++ chan->func_id = func_id; ++ ++ ret = scmi_dt_get_smt_buffer(dev, &chan->smt); ++ if (ret) { ++ dev_err(dev, "Failed to get smt resources: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct udevice_id scmi_smccc_ids[] = { ++ { .compatible = "arm,scmi-smc" }, ++ { } ++}; ++ ++static const struct scmi_agent_ops scmi_smccc_ops = { ++ .process_msg = scmi_smccc_process_msg, ++}; ++ ++U_BOOT_DRIVER(scmi_smccc) = { ++ .name = "scmi-over-smccc", ++ .id = UCLASS_SCMI_AGENT, ++ .of_match = scmi_smccc_ids, ++ .priv_auto_alloc_size = sizeof(struct scmi_smccc_channel), ++ .probe = scmi_smccc_probe, ++ .ops = &scmi_smccc_ops, ++}; +diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c +new file mode 100644 +index 0000000000..ce8fe49939 +--- /dev/null ++++ b/drivers/firmware/scmi/smt.c +@@ -0,0 +1,139 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. ++ * Copyright (C) 2019-2020 Linaro Limited. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "smt.h" ++ ++/** ++ * Get shared memory configuration defined by the referred DT phandle ++ * Return with a errno compliant value. ++ */ ++int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt) ++{ ++ int ret; ++ struct ofnode_phandle_args args; ++ struct resource resource; ++ fdt32_t faddr; ++ phys_addr_t paddr; ++ ++ ret = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ ret = ofnode_read_resource(args.node, 0, &resource); ++ if (ret) ++ return ret; ++ ++ faddr = cpu_to_fdt32(resource.start); ++ paddr = ofnode_translate_address(args.node, &faddr); ++ ++ smt->size = resource_size(&resource); ++ if (smt->size < sizeof(struct scmi_smt_header)) { ++ dev_err(dev, "Shared memory buffer too small\n"); ++ return -EINVAL; ++ } ++ ++ smt->buf = devm_ioremap(dev, paddr, smt->size); ++ if (!smt->buf) ++ return -ENOMEM; ++ ++#ifdef CONFIG_ARM ++ if (dcache_status()) ++ mmu_set_region_dcache_behaviour((uintptr_t)smt->buf, ++ smt->size, DCACHE_OFF); ++#endif ++ ++ return 0; ++} ++ ++/** ++ * Write SCMI message @msg into a SMT shared buffer @smt. ++ * Return 0 on success and with a negative errno in case of error. ++ */ ++int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt, ++ struct scmi_msg *msg) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ if ((!msg->in_msg && msg->in_msg_sz) || ++ (!msg->out_msg && msg->out_msg_sz)) ++ return -EINVAL; ++ ++ if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { ++ dev_dbg(dev, "Channel busy\n"); ++ return -EBUSY; ++ } ++ ++ if (smt->size < (sizeof(*hdr) + msg->in_msg_sz) || ++ smt->size < (sizeof(*hdr) + msg->out_msg_sz)) { ++ dev_dbg(dev, "Buffer too small\n"); ++ return -ETOOSMALL; ++ } ++ ++ /* Load message in shared memory */ ++ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; ++ hdr->length = msg->in_msg_sz + sizeof(hdr->msg_header); ++ hdr->msg_header = SMT_HEADER_TOKEN(0) | ++ SMT_HEADER_MESSAGE_TYPE(0) | ++ SMT_HEADER_PROTOCOL_ID(msg->protocol_id) | ++ SMT_HEADER_MESSAGE_ID(msg->message_id); ++ ++ memcpy_toio(hdr->msg_payload, msg->in_msg, msg->in_msg_sz); ++ ++ return 0; ++} ++ ++/** ++ * Read SCMI message from a SMT shared buffer @smt and copy it into @msg. ++ * Return 0 on success and with a negative errno in case of error. ++ */ ++int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt, ++ struct scmi_msg *msg) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { ++ dev_err(dev, "Channel unexpectedly busy\n"); ++ return -EBUSY; ++ } ++ ++ if (hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR) { ++ dev_err(dev, "Channel error reported, reset channel\n"); ++ return -ECOMM; ++ } ++ ++ if (hdr->length > msg->out_msg_sz + sizeof(hdr->msg_header)) { ++ dev_err(dev, "Buffer to small\n"); ++ return -ETOOSMALL; ++ } ++ ++ /* Get the data */ ++ msg->out_msg_sz = hdr->length - sizeof(hdr->msg_header); ++ memcpy_fromio(msg->out_msg, hdr->msg_payload, msg->out_msg_sz); ++ ++ return 0; ++} ++ ++/** ++ * Clear SMT flags in shared buffer to allow further message exchange ++ */ ++void scmi_clear_smt_channel(struct scmi_smt *smt) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; ++} +diff --git a/drivers/firmware/scmi/smt.h b/drivers/firmware/scmi/smt.h +new file mode 100644 +index 0000000000..a8c0987bd3 +--- /dev/null ++++ b/drivers/firmware/scmi/smt.h +@@ -0,0 +1,86 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. ++ * Copyright (C) 2019-2020 Linaro Limited. ++ */ ++#ifndef SCMI_SMT_H ++#define SCMI_SMT_H ++ ++#include ++ ++/** ++ * struct scmi_smt_header - Description of the shared memory message buffer ++ * ++ * SMT stands for Shared Memory based Transport. ++ * SMT uses 28 byte header prior message payload to handle the state of ++ * the communication channel realized by the shared memory area and ++ * to define SCMI protocol information the payload relates to. ++ */ ++struct scmi_smt_header { ++ __le32 reserved; ++ __le32 channel_status; ++#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1) ++#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0) ++ __le32 reserved1[2]; ++ __le32 flags; ++#define SCMI_SHMEM_FLAG_INTR_ENABLED BIT(0) ++ __le32 length; ++ __le32 msg_header; ++ u8 msg_payload[0]; ++}; ++ ++#define SMT_HEADER_TOKEN(token) (((token) << 18) & GENMASK(31, 18)) ++#define SMT_HEADER_PROTOCOL_ID(proto) (((proto) << 10) & GENMASK(17, 10)) ++#define SMT_HEADER_MESSAGE_TYPE(type) (((type) << 18) & GENMASK(9, 8)) ++#define SMT_HEADER_MESSAGE_ID(id) ((id) & GENMASK(7, 0)) ++ ++/** ++ * struct scmi_smt - Description of a SMT memory buffer ++ * @buf: Shared memory base address ++ * @size: Shared memory byte size ++ */ ++struct scmi_smt { ++ u8 *buf; ++ size_t size; ++}; ++ ++static inline bool scmi_smt_channel_is_free(struct scmi_smt *smt) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ return hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; ++} ++ ++static inline bool scmi_smt_channel_reports_error(struct scmi_smt *smt) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ return hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; ++} ++ ++static inline void scmi_smt_get_channel(struct scmi_smt *smt) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; ++} ++ ++static inline void scmi_smt_put_channel(struct scmi_smt *smt) ++{ ++ struct scmi_smt_header *hdr = (void *)smt->buf; ++ ++ hdr->channel_status |= SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; ++ hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; ++} ++ ++int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt); ++ ++int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt, ++ struct scmi_msg *msg); ++ ++int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt, ++ struct scmi_msg *msg); ++ ++void scmi_clear_smt_channel(struct scmi_smt *smt); ++ ++#endif /* SCMI_SMT_H */ +diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c +index 5bff27f75b..5597247164 100644 +--- a/drivers/gpio/stm32_gpio.c ++++ b/drivers/gpio/stm32_gpio.c +@@ -210,11 +210,11 @@ static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, + + } else if (flags & GPIOD_IS_IN) { + stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN); +- if (flags & GPIOD_PULL_UP) +- stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); +- else if (flags & GPIOD_PULL_DOWN) +- stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); + } ++ if (flags & GPIOD_PULL_UP) ++ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP); ++ else if (flags & GPIOD_PULL_DOWN) ++ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN); + + return 0; + } +@@ -241,16 +241,16 @@ static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset, + break; + case STM32_GPIO_MODE_IN: + dir_flags |= GPIOD_IS_IN; +- switch (stm32_gpio_get_pupd(regs, idx)) { +- case STM32_GPIO_PUPD_UP: +- dir_flags |= GPIOD_PULL_UP; +- break; +- case STM32_GPIO_PUPD_DOWN: +- dir_flags |= GPIOD_PULL_DOWN; +- break; +- default: +- break; +- } ++ break; ++ default: ++ break; ++ } ++ switch (stm32_gpio_get_pupd(regs, idx)) { ++ case STM32_GPIO_PUPD_UP: ++ dir_flags |= GPIOD_PULL_UP; ++ break; ++ case STM32_GPIO_PUPD_DOWN: ++ dir_flags |= GPIOD_PULL_DOWN; + break; + default: + break; +diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c +index 6fbd24ba74..ef7f5f07d5 100644 +--- a/drivers/mtd/nand/core.c ++++ b/drivers/mtd/nand/core.c +@@ -10,6 +10,7 @@ + #define pr_fmt(fmt) "nand: " fmt + + #include ++#include + #ifndef __UBOOT__ + #include + #include +@@ -164,6 +165,7 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo) + nanddev_offs_to_pos(nand, einfo->addr, &pos); + nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last); + while (nanddev_pos_cmp(&pos, &last) <= 0) { ++ WATCHDOG_RESET(); + ret = nanddev_erase(nand, &pos); + if (ret) { + einfo->fail_addr = nanddev_pos_to_offs(nand, &pos); +diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c +index 93371fdde0..dbf2db6d00 100644 +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -578,6 +579,7 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, + #endif + + nanddev_io_for_each_page(nand, from, ops, &iter) { ++ WATCHDOG_RESET(); + ret = spinand_select_target(spinand, iter.req.pos.target); + if (ret) + break; +@@ -629,6 +631,7 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, + #endif + + nanddev_io_for_each_page(nand, to, ops, &iter) { ++ WATCHDOG_RESET(); + ret = spinand_select_target(spinand, iter.req.pos.target); + if (ret) + break; +diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c +index 0113e70037..81de0de0c5 100644 +--- a/drivers/mtd/spi/spi-nor-core.c ++++ b/drivers/mtd/spi/spi-nor-core.c +@@ -11,6 +11,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -565,6 +566,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) + len = instr->len; + + while (len) { ++ WATCHDOG_RESET(); + #ifdef CONFIG_SPI_FLASH_BAR + ret = write_bar(nor, addr); + if (ret < 0) +@@ -1249,6 +1251,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, + for (i = 0; i < len; ) { + ssize_t written; + loff_t addr = to + i; ++ WATCHDOG_RESET(); + + /* + * If page_size is a power of two, the offset can be quickly +diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c +index c6d3048602..d4a82f73f4 100644 +--- a/drivers/phy/phy-stm32-usbphyc.c ++++ b/drivers/phy/phy-stm32-usbphyc.c +@@ -59,6 +59,7 @@ struct stm32_usbphyc { + struct udevice *vdda1v8; + struct stm32_usbphyc_phy { + struct udevice *vdd; ++ struct udevice *vbus; + bool init; + bool powered; + } phys[MAX_PHYS]; +@@ -244,6 +245,11 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) + if (ret) + return ret; + } ++ if (usbphyc_phy->vbus) { ++ ret = regulator_set_enable(usbphyc_phy->vbus, true); ++ if (ret) ++ return ret; ++ } + + usbphyc_phy->powered = true; + +@@ -262,6 +268,11 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) + if (stm32_usbphyc_is_powered(usbphyc)) + return 0; + ++ if (usbphyc_phy->vbus) { ++ ret = regulator_set_enable(usbphyc_phy->vbus, false); ++ if (ret) ++ return ret; ++ } + if (usbphyc_phy->vdd) { + ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false); + if (ret) +@@ -271,7 +282,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) + return 0; + } + +-static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, ++static int stm32_usbphyc_get_regulator(ofnode node, + char *supply_name, + struct udevice **regulator) + { +@@ -281,19 +292,14 @@ static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, + ret = ofnode_parse_phandle_with_args(node, supply_name, + NULL, 0, 0, + ®ulator_phandle); +- if (ret) { +- dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret); ++ if (ret) + return ret; +- } + + ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, + regulator_phandle.node, + regulator); +- +- if (ret) { +- dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret); ++ if (ret) + return ret; +- } + + return 0; + } +@@ -380,10 +386,17 @@ static int stm32_usbphyc_probe(struct udevice *dev) + + usbphyc_phy->init = false; + usbphyc_phy->powered = false; +- ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply", ++ ret = stm32_usbphyc_get_regulator(node, "phy-supply", + &usbphyc_phy->vdd); +- if (ret) ++ if (ret) { ++ dev_err(dev, "Can't get phy-supply regulator\n"); + return ret; ++ } ++ ++ ret = stm32_usbphyc_get_regulator(node, "vbus-supply", ++ &usbphyc_phy->vbus); ++ if (ret) ++ usbphyc_phy->vbus = NULL; + + node = dev_read_next_subnode(node); + } +diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c +index c2ea82770e..fbbd479575 100644 +--- a/drivers/pinctrl/pinctrl-stmfx.c ++++ b/drivers/pinctrl/pinctrl-stmfx.c +@@ -346,15 +346,14 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev) + * STMFX pins[15:0] are called "gpio[15:0]" + * and STMFX pins[23:16] are called "agpio[7:0]" + */ +-#define MAX_PIN_NAME_LEN 7 +-static char pin_name[MAX_PIN_NAME_LEN]; ++static char pin_name[PINNAME_SIZE]; + static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) + { + if (selector < STMFX_MAX_GPIO) +- snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); ++ snprintf(pin_name, PINNAME_SIZE, "gpio%u", selector); + else +- snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16); ++ snprintf(pin_name, PINNAME_SIZE, "agpio%u", selector - 16); + return pin_name; + } + +@@ -408,8 +407,11 @@ static int stmfx_pinctrl_bind(struct udevice *dev) + { + struct stmfx_pinctrl *plat = dev_get_platdata(dev); + ++ /* subnode name is not explicit: use father name */ ++ device_set_name(dev, dev->parent->name); ++ + return device_bind_driver_to_node(dev->parent, +- "stmfx-gpio", "stmfx-gpio", ++ "stmfx-gpio", dev->parent->name, + dev_ofnode(dev), &plat->gpio); + }; + +diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c +index 71fa29a389..35a6acbe2c 100644 +--- a/drivers/pinctrl/pinctrl_stm32.c ++++ b/drivers/pinctrl/pinctrl_stm32.c +@@ -45,15 +45,15 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { + "alt function", + }; + +-static const char * const pinmux_output[] = { +- [STM32_GPIO_PUPD_NO] = "bias-disable", +- [STM32_GPIO_PUPD_UP] = "bias-pull-up", +- [STM32_GPIO_PUPD_DOWN] = "bias-pull-down", ++static const char * const pinmux_bias[] = { ++ [STM32_GPIO_PUPD_NO] = "", ++ [STM32_GPIO_PUPD_UP] = "pull-up", ++ [STM32_GPIO_PUPD_DOWN] = "pull-down", + }; + +-static const char * const pinmux_input[] = { +- [STM32_GPIO_OTYPE_PP] = "drive-push-pull", +- [STM32_GPIO_OTYPE_OD] = "drive-open-drain", ++static const char * const pinmux_otype[] = { ++ [STM32_GPIO_OTYPE_PP] = "push-pull", ++ [STM32_GPIO_OTYPE_OD] = "open-drain", + }; + + static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) +@@ -210,7 +210,8 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, + dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", + selector, gpio_idx, mode); + priv = dev_get_priv(gpio_dev); +- ++ pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; ++ otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; + + switch (mode) { + case GPIOF_UNKNOWN: +@@ -221,20 +222,17 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, + break; + case GPIOF_FUNC: + af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); +- snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num); ++ snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num, ++ pinmux_otype[otype], pinmux_bias[pupd]); + break; + case GPIOF_OUTPUT: +- pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & +- PUPD_MASK; +- snprintf(buf, size, "%s %s %s", +- pinmux_mode[mode], pinmux_output[pupd], +- label ? label : ""); ++ snprintf(buf, size, "%s %s %s %s", ++ pinmux_mode[mode], pinmux_otype[otype], ++ pinmux_bias[pupd], label ? label : ""); + break; + case GPIOF_INPUT: +- otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; +- snprintf(buf, size, "%s %s %s", +- pinmux_mode[mode], pinmux_input[otype], +- label ? label : ""); ++ snprintf(buf, size, "%s %s %s", pinmux_mode[mode], ++ pinmux_bias[pupd], label ? label : ""); + break; + } + +@@ -401,6 +399,9 @@ static int stm32_pinctrl_bind(struct udevice *dev) + dev_for_each_subnode(node, dev) { + debug("%s: bind %s\n", __func__, ofnode_get_name(node)); + ++ if (!ofnode_is_enabled(node)) ++ continue; ++ + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + continue; +diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig +index 7c2e4804b5..3e1c9ed54f 100644 +--- a/drivers/remoteproc/Kconfig ++++ b/drivers/remoteproc/Kconfig +@@ -12,6 +12,14 @@ config REMOTEPROC + bool + depends on DM + ++config REMOTEPROC_OPTEE ++ bool "Support for the remoteproc in OPTEE" ++ depends on REMOTEPROC ++ depends on OPTEE ++ help ++ Say y here to support remote processor firmware management by the ++ trusted execution environment. ++ + # Please keep the configuration alphabetically sorted. + config K3_SYSTEM_CONTROLLER + bool "Support for TI' K3 System Controller" +diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile +index 69ae7bd1e8..d6c5f54fb7 100644 +--- a/drivers/remoteproc/Makefile ++++ b/drivers/remoteproc/Makefile +@@ -5,6 +5,7 @@ + # + + obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o ++obj-$(CONFIG_REMOTEPROC_OPTEE) += rproc-optee.o + + # Remote proc drivers - Please keep this list alphabetically sorted. + obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o +diff --git a/drivers/remoteproc/rproc-optee.c b/drivers/remoteproc/rproc-optee.c +new file mode 100644 +index 0000000000..07d2811e22 +--- /dev/null ++++ b/drivers/remoteproc/rproc-optee.c +@@ -0,0 +1,219 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved ++ * Authors: Arnaud Pouliquen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TA_REMOTEPROC_UUID { 0x80a4c275, 0x0a47, 0x4905, \ ++ { 0x82, 0x85, 0x14, 0x86, 0xa9, 0x77, 0x1a, 0x08} } ++ ++/* The function IDs implemented in the associated TA */ ++ ++/* ++ * Authentication of the firmware and load in the remote processor memory. ++ * ++ * [in] params[0].value.a: unique 32bit identifier of the firmware ++ * [in] params[1].memref: buffer containing the image of the firmware ++ */ ++#define TA_RPROC_FW_CMD_LOAD_FW 1 ++ ++/* ++ * Start the remote processor. ++ * ++ * [in] params[0].value.a: unique 32bit identifier of the firmware ++ */ ++#define TA_RPROC_FW_CMD_START_FW 2 ++ ++/* ++ * Stop the remote processor. ++ * ++ * [in] params[0].value.a: unique 32bit identifier of the firmware ++ */ ++#define TA_RPROC_FW_CMD_STOP_FW 3 ++ ++/* ++ * Return the physical address of the resource table, or 0 if not found ++ * No check is done to verify that the address returned is accessible by the ++ * non secure world. If the resource table is loaded in a protected memory, ++ * then accesses from non-secure world will likely fail. ++ * ++ * [in] params[0].value.a: unique 32bit identifier of the firmware ++ * [out] params[1].value.a: 32bit LSB resource table memory address ++ * [out] params[1].value.b: 32bit MSB resource table memory address ++ * [out] params[2].value.a: 32bit LSB resource table memory size ++ * [out] params[2].value.b: 32bit MSB resource table memory size ++ */ ++#define TA_RPROC_FW_CMD_GET_RSC_TABLE 4 ++ ++/* ++ * Get remote processor firmware core dump. If found, return either ++ * TEE_SUCCESS on successful completion or TEE_ERROR_SHORT_BUFFER if output ++ * buffer is too short to store the core dump. ++ * ++ * [in] params[0].value.a: unique 32bit identifier of the firmware ++ * [out] params[1].memref: Core dump, if found ++ */ ++#define TA_RPROC_FW_CMD_GET_COREDUMP 5 ++ ++static void prepare_args(struct rproc_optee *trproc, int cmd, ++ struct tee_invoke_arg *arg, uint num_param, ++ struct tee_param *param) ++{ ++ memset(arg, 0, sizeof(*arg)); ++ memset(param, 0, num_param * sizeof(*param)); ++ ++ arg->func = cmd; ++ arg->session = trproc->session; ++ ++ param[0] = (struct tee_param) { ++ .attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT, ++ .u.value.a = trproc->fw_id, ++ }; ++} ++ ++int rproc_optee_load(struct rproc_optee *trproc, ulong addr, ulong size) ++{ ++ struct tee_invoke_arg arg; ++ struct tee_param param[2]; ++ struct tee_shm *fw_shm; ++ int rc; ++ ++ rc = tee_shm_register(trproc->tee, (void *)addr, size, 0, &fw_shm); ++ if (rc) ++ return rc; ++ ++ prepare_args(trproc, TA_RPROC_FW_CMD_LOAD_FW, &arg, 2, param); ++ ++ /* Provide the address and size of the firmware image */ ++ param[1] = (struct tee_param){ ++ .attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT, ++ .u.memref = { ++ .shm = fw_shm, ++ .size = size, ++ .shm_offs = 0, ++ }, ++ }; ++ ++ rc = tee_invoke_func(trproc->tee, &arg, 2, param); ++ if (rc < 0 || arg.ret != 0) { ++ dev_err(trproc->tee, ++ "TA_RPROC_FW_CMD_LOAD_FW invoke failed TEE err: %x, err:%x\n", ++ arg.ret, rc); ++ if (!rc) ++ rc = -EIO; ++ } ++ ++ tee_shm_free(fw_shm); ++ ++ return rc; ++} ++ ++int rproc_optee_get_rsc_table(struct rproc_optee *trproc, phys_addr_t *rsc_addr, ++ phys_size_t *rsc_size) ++{ ++ struct tee_invoke_arg arg; ++ struct tee_param param[3]; ++ int rc; ++ ++ prepare_args(trproc, TA_RPROC_FW_CMD_GET_RSC_TABLE, &arg, 3, param); ++ ++ param[1].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT; ++ param[2].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT; ++ ++ rc = tee_invoke_func(trproc->tee, &arg, 3, param); ++ if (rc < 0 || arg.ret != 0) { ++ dev_err(trproc->tee, ++ "TA_RPROC_FW_CMD_GET_RSC_TABLE invoke failed TEE err: %x, err:%x\n", ++ arg.ret, rc); ++ if (!rc) ++ rc = -EIO; ++ ++ return rc; ++ } ++ ++ *rsc_size = (phys_size_t) ++ (param[2].u.value.b << 32 | param[2].u.value.a); ++ *rsc_addr = (phys_addr_t) ++ (param[1].u.value.b << 32 | param[1].u.value.a); ++ ++ return 0; ++} ++ ++int rproc_optee_start(struct rproc_optee *trproc) ++{ ++ struct tee_invoke_arg arg; ++ struct tee_param param; ++ int rc; ++ ++ prepare_args(trproc, TA_RPROC_FW_CMD_START_FW, &arg, 1, ¶m); ++ ++ rc = tee_invoke_func(trproc->tee, &arg, 1, ¶m); ++ if (rc < 0 || arg.ret != 0) { ++ dev_err(trproc->tee, ++ "TA_RPROC_FW_CMD_START_FW invoke failed TEE err: %x, err:%x\n", ++ arg.ret, rc); ++ if (!rc) ++ rc = -EIO; ++ } ++ ++ return rc; ++} ++ ++int rproc_optee_stop(struct rproc_optee *trproc) ++{ ++ struct tee_invoke_arg arg; ++ struct tee_param param; ++ int rc; ++ ++ prepare_args(trproc, TA_RPROC_FW_CMD_STOP_FW, &arg, 1, ¶m); ++ ++ rc = tee_invoke_func(trproc->tee, &arg, 1, ¶m); ++ if (rc < 0 || arg.ret != 0) { ++ dev_err(trproc->tee, ++ "TA_RPROC_FW_CMD_STOP_FW invoke failed TEE err: %x, err:%x\n", ++ arg.ret, rc); ++ if (!rc) ++ rc = -EIO; ++ } ++ ++ return rc; ++} ++ ++int rproc_optee_open(struct rproc_optee *trproc) ++{ ++ struct udevice *tee = NULL; ++ const struct tee_optee_ta_uuid uuid = TA_REMOTEPROC_UUID; ++ struct tee_open_session_arg arg = { }; ++ int rc; ++ ++ if (!trproc) ++ return -EINVAL; ++ ++ tee = tee_find_device(tee, NULL, NULL, NULL); ++ if (!tee) ++ return -ENODEV; ++ ++ tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); ++ rc = tee_open_session(tee, &arg, 0, NULL); ++ if (!rc) { ++ trproc->tee = tee; ++ trproc->session = arg.session; ++ } ++ ++ return 0; ++} ++ ++int rproc_optee_close(struct rproc_optee *trproc) ++{ ++ if (!trproc->tee) ++ return -ENODEV; ++ ++ return tee_close_session(trproc->tee, trproc->session); ++} +diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c +index 33b574b1bd..55d7303c55 100644 +--- a/drivers/remoteproc/stm32_copro.c ++++ b/drivers/remoteproc/stm32_copro.c +@@ -8,30 +8,24 @@ + #include + #include + #include +-#include + #include ++#include + #include +-#include + #include + #include + #include + +-#define RCC_GCR_HOLD_BOOT 0 +-#define RCC_GCR_RELEASE_BOOT 1 ++#define STM32MP15_M4_FW_ID 0 + + /** + * struct stm32_copro_privdata - power processor private data + * @reset_ctl: reset controller handle +- * @hold_boot_regmap: regmap for remote processor reset hold boot +- * @hold_boot_offset: offset of the register controlling the hold boot setting +- * @hold_boot_mask: bitmask of the register for the hold boot field ++ * @hold_boot: hold boot controller handle + * @rsc_table_addr: resource table address + */ + struct stm32_copro_privdata { + struct reset_ctl reset_ctl; +- struct regmap *hold_boot_regmap; +- uint hold_boot_offset; +- uint hold_boot_mask; ++ struct reset_ctl hold_boot; + ulong rsc_table_addr; + }; + +@@ -43,32 +37,19 @@ struct stm32_copro_privdata { + static int stm32_copro_probe(struct udevice *dev) + { + struct stm32_copro_privdata *priv; +- struct regmap *regmap; +- const fdt32_t *cell; +- int len, ret; ++ int ret; + + priv = dev_get_priv(dev); + +- regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-holdboot"); +- if (IS_ERR(regmap)) { +- dev_err(dev, "unable to find holdboot regmap (%ld)\n", +- PTR_ERR(regmap)); +- return PTR_ERR(regmap); +- } +- +- cell = dev_read_prop(dev, "st,syscfg-holdboot", &len); +- if (len < 3 * sizeof(fdt32_t)) { +- dev_err(dev, "holdboot offset and mask not available\n"); +- return -EINVAL; ++ ret = reset_get_by_name(dev, "mcu_rst", &priv->reset_ctl); ++ if (ret) { ++ dev_err(dev, "failed to get reset (%d)\n", ret); ++ return ret; + } + +- priv->hold_boot_regmap = regmap; +- priv->hold_boot_offset = fdtdec_get_number(cell + 1, 1); +- priv->hold_boot_mask = fdtdec_get_number(cell + 2, 1); +- +- ret = reset_get_by_index(dev, 0, &priv->reset_ctl); ++ ret = reset_get_by_name(dev, "hold_boot", &priv->hold_boot); + if (ret) { +- dev_err(dev, "failed to get reset (%d)\n", ret); ++ dev_err(dev, "failed to get hold boot (%d)\n", ret); + return ret; + } + +@@ -78,32 +59,29 @@ static int stm32_copro_probe(struct udevice *dev) + } + + /** +- * stm32_copro_set_hold_boot() - Hold boot bit management ++ * stm32_copro_optee_probe() - Open a session toward rproc trusted application + * @dev: corresponding STM32 remote processor device +- * @hold: hold boot value + * @return 0 if all went ok, else corresponding -ve error + */ +-static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold) ++static int stm32_copro_optee_probe(struct udevice *dev) + { +- struct stm32_copro_privdata *priv; +- uint val; +- int ret; ++ struct rproc_optee *trproc = dev_get_priv(dev); + +- priv = dev_get_priv(dev); ++ trproc->fw_id = (u32)dev_get_driver_data(dev); + +- val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT; ++ return rproc_optee_open(trproc); ++} + +- /* +- * Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured. +- * To be updated when the code for this SMC service is available which +- * is not the case for the time being. +- */ +- ret = regmap_update_bits(priv->hold_boot_regmap, priv->hold_boot_offset, +- priv->hold_boot_mask, val); +- if (ret) +- dev_err(dev, "failed to set hold boot\n"); ++/** ++ * stm32_copro_optee_remove() - Close the rproc trusted application session ++ * @dev: corresponding STM32 remote processor device ++ * @return 0 if all went ok, else corresponding -ve error ++ */ ++static int stm32_copro_optee_remove(struct udevice *dev) ++{ ++ struct rproc_optee *trproc = dev_get_priv(dev); + +- return ret; ++ return rproc_optee_close(trproc); + } + + /** +@@ -149,9 +127,11 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) + + priv = dev_get_priv(dev); + +- ret = stm32_copro_set_hold_boot(dev, true); +- if (ret) ++ ret = reset_assert(&priv->hold_boot); ++ if (ret) { ++ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); + return ret; ++ } + + ret = reset_assert(&priv->reset_ctl); + if (ret) { +@@ -168,6 +148,18 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) + return rproc_elf32_load_image(dev, addr, size); + } + ++/** ++ * stm32_copro_optee_load() - Request OP−TEE to load the remote processor firmware ++ * @dev: corresponding OP-TEE remote processor device ++ * @return 0 if all went ok, else corresponding -ve error ++ */ ++static int stm32_copro_optee_load(struct udevice *dev, ulong addr, ulong size) ++{ ++ struct rproc_optee *trproc = dev_get_priv(dev); ++ ++ return rproc_optee_load(trproc, addr, size); ++} ++ + /** + * stm32_copro_start() - Start the STM32 remote processor + * @dev: corresponding STM32 remote processor device +@@ -180,23 +172,54 @@ static int stm32_copro_start(struct udevice *dev) + + priv = dev_get_priv(dev); + +- /* move hold boot from true to false start the copro */ +- ret = stm32_copro_set_hold_boot(dev, false); +- if (ret) ++ ret = reset_deassert(&priv->hold_boot); ++ if (ret) { ++ dev_err(dev, "Unable to deassert hold boot (ret=%d)\n", ret); + return ret; ++ } + + /* + * Once copro running, reset hold boot flag to avoid copro +- * rebooting autonomously ++ * rebooting autonomously (error should never occur) + */ +- ret = stm32_copro_set_hold_boot(dev, true); +- writel(ret ? TAMP_COPRO_STATE_OFF : TAMP_COPRO_STATE_CRUN, +- TAMP_COPRO_STATE); +- if (!ret) +- /* Store rsc_address in bkp register */ +- writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); +- +- return ret; ++ ret = reset_assert(&priv->hold_boot); ++ if (ret) ++ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); ++ ++ /* indicates that copro is running */ ++ writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE); ++ /* Store rsc_address in bkp register */ ++ writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); ++ ++ return 0; ++} ++ ++/** ++ * stm32_copro_optee_start() - Request OP−TEE to start the STM32 remote processor ++ * @dev: corresponding OP-TEE remote processor device ++ * @return 0 if all went ok, else corresponding -ve error ++ */ ++static int stm32_copro_optee_start(struct udevice *dev) ++{ ++ struct rproc_optee *trproc = dev_get_priv(dev); ++ phys_addr_t rsc_addr; ++ phys_size_t rsc_size; ++ int ret; ++ ++ ret = rproc_optee_get_rsc_table(trproc, &rsc_addr, &rsc_size); ++ if (ret) ++ return ret; ++ ++ ret = rproc_optee_start(trproc); ++ if (ret) ++ return ret; ++ ++ /* indicates that copro is running */ ++ writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE); ++ /* Store rsc_address in bkp register */ ++ writel(rsc_addr, TAMP_COPRO_RSC_TBL_ADDRESS); ++ ++ return 0; + } + + /** +@@ -211,9 +234,11 @@ static int stm32_copro_reset(struct udevice *dev) + + priv = dev_get_priv(dev); + +- ret = stm32_copro_set_hold_boot(dev, true); +- if (ret) ++ ret = reset_assert(&priv->hold_boot); ++ if (ret) { ++ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); + return ret; ++ } + + ret = reset_assert(&priv->reset_ctl); + if (ret) { +@@ -236,6 +261,35 @@ static int stm32_copro_stop(struct udevice *dev) + return stm32_copro_reset(dev); + } + ++/** ++ * stm32_copro_optee_reset() - Request OP−TEE to reset the STM32 remote processor ++ * @dev: corresponding STM32 remote processor device ++ * @return 0 if all went ok, else corresponding -ve error ++ */ ++static int stm32_copro_optee_reset(struct udevice *dev) ++{ ++ struct rproc_optee *trproc = dev_get_priv(dev); ++ int ret; ++ ++ ret = rproc_optee_stop(trproc); ++ if (ret) ++ return ret; ++ ++ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); ++ ++ return 0; ++} ++ ++/** ++ * stm32_copro_optee_stop() - Request OP−TEE to stop the STM32 remote processor ++ * @dev: corresponding STM32 remote processor device ++ * @return 0 if all went ok, else corresponding -ve error ++ */ ++static int stm32_copro_optee_stop(struct udevice *dev) ++{ ++ return stm32_copro_optee_reset(dev); ++} ++ + /** + * stm32_copro_is_running() - Is the STM32 remote processor running + * @dev: corresponding STM32 remote processor device +@@ -268,3 +322,28 @@ U_BOOT_DRIVER(stm32_copro) = { + .probe = stm32_copro_probe, + .priv_auto_alloc_size = sizeof(struct stm32_copro_privdata), + }; ++ ++static const struct dm_rproc_ops stm32_copro_optee_ops = { ++ .load = stm32_copro_optee_load, ++ .start = stm32_copro_optee_start, ++ .stop = stm32_copro_optee_stop, ++ .reset = stm32_copro_optee_reset, ++ .is_running = stm32_copro_is_running, ++ .device_to_virt = stm32_copro_device_to_virt, ++}; ++ ++static const struct udevice_id stm32_copro_optee_ids[] = { ++ { .compatible = "st,stm32mp1-m4_optee", .data = STM32MP15_M4_FW_ID }, ++ {} ++}; ++ ++U_BOOT_DRIVER(stm32_copro_optee) = { ++ .name = "stm32_m4_proc_optee", ++ .of_match = stm32_copro_optee_ids, ++ .id = UCLASS_REMOTEPROC, ++ .ops = &stm32_copro_optee_ops, ++ .probe = stm32_copro_optee_probe, ++ .remove = stm32_copro_optee_remove, ++ .priv_auto_alloc_size = sizeof(struct rproc_optee), ++ .flags = DM_FLAG_OS_PREPARE, ++}; +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 253902ff57..ee5be0bc2f 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -173,4 +173,12 @@ config RESET_RASPBERRYPI + relevant. This driver provides a reset controller capable of + interfacing with RPi4's co-processor and model these firmware + initialization routines as reset lines. ++ ++config RESET_SCMI ++ bool "Enable SCMI reset domain driver" ++ select SCMI_FIRMWARE ++ help ++ Enable this option if you want to support reset controller ++ devices exposed by a SCMI agent based on SCMI reset domain ++ protocol communication with a SCMI server. + endmenu +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index 3c7f066ae3..625ec7168e 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -26,3 +26,4 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o + obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o + obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o + obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o ++obj-$(CONFIG_RESET_SCMI) += reset-scmi.o +diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c +new file mode 100644 +index 0000000000..1bff8075ee +--- /dev/null ++++ b/drivers/reset/reset-scmi.c +@@ -0,0 +1,81 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019-2020 Linaro Limited ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) ++{ ++ struct scmi_rd_reset_in in = { ++ .domain_id = rst->id, ++ .flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0, ++ .reset_state = 0, ++ }; ++ struct scmi_rd_reset_out out; ++ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN, ++ SCMI_RESET_DOMAIN_RESET, ++ in, out); ++ int ret; ++ ++ ret = devm_scmi_process_msg(rst->dev->parent, &msg); ++ if (ret) ++ return ret; ++ ++ return scmi_to_linux_errno(out.status); ++} ++ ++static int scmi_reset_assert(struct reset_ctl *rst) ++{ ++ return scmi_reset_set_level(rst, true); ++} ++ ++static int scmi_reset_deassert(struct reset_ctl *rst) ++{ ++ return scmi_reset_set_level(rst, false); ++} ++ ++static int scmi_reset_request(struct reset_ctl *rst) ++{ ++ struct scmi_rd_attr_in in = { ++ .domain_id = rst->id, ++ }; ++ struct scmi_rd_attr_out out; ++ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN, ++ SCMI_RESET_DOMAIN_ATTRIBUTES, ++ in, out); ++ int ret; ++ ++ /* ++ * We don't really care about the attribute, just check ++ * the reset domain exists. ++ */ ++ ret = devm_scmi_process_msg(rst->dev->parent, &msg); ++ if (ret) ++ return ret; ++ ++ return scmi_to_linux_errno(out.status); ++} ++ ++static int scmi_reset_rfree(struct reset_ctl *rst) ++{ ++ return 0; ++} ++ ++static const struct reset_ops scmi_reset_domain_ops = { ++ .request = scmi_reset_request, ++ .rfree = scmi_reset_rfree, ++ .rst_assert = scmi_reset_assert, ++ .rst_deassert = scmi_reset_deassert, ++}; ++ ++U_BOOT_DRIVER(scmi_reset_domain) = { ++ .name = "scmi_reset_domain", ++ .id = UCLASS_RESET, ++ .ops = &scmi_reset_domain_ops, ++}; +diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c +index 64a11cfcfc..20c36a99eb 100644 +--- a/drivers/reset/stm32-reset.c ++++ b/drivers/reset/stm32-reset.c +@@ -14,6 +14,9 @@ + #include + #include + ++/* offset of register without set/clear management */ ++#define RCC_MP_GCR_OFFSET 0x10C ++ + /* reset clear offset for STM32MP RCC */ + #define RCC_CL 0x4 + +@@ -40,8 +43,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) + reset_ctl->id, bank, offset); + + if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) +- /* reset assert is done in rcc set register */ +- writel(BIT(offset), priv->base + bank); ++ if (bank != RCC_MP_GCR_OFFSET) ++ /* reset assert is done in rcc set register */ ++ writel(BIT(offset), priv->base + bank); ++ else ++ clrbits_le32(priv->base + bank, BIT(offset)); + else + setbits_le32(priv->base + bank, BIT(offset)); + +@@ -57,8 +63,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) + reset_ctl->id, bank, offset); + + if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) +- /* reset deassert is done in rcc clr register */ +- writel(BIT(offset), priv->base + bank + RCC_CL); ++ if (bank != RCC_MP_GCR_OFFSET) ++ /* reset deassert is done in rcc clr register */ ++ writel(BIT(offset), priv->base + bank + RCC_CL); ++ else ++ setbits_le32(priv->base + bank, BIT(offset)); + else + clrbits_le32(priv->base + bank, BIT(offset)); + +diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c +index a53b941410..72a169e196 100644 +--- a/drivers/spi/stm32_qspi.c ++++ b/drivers/spi/stm32_qspi.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -169,6 +170,7 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv, + static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr) + { + *val = readb(addr); ++ WATCHDOG_RESET(); + } + + static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr) +diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c +index eaa5dcb9b1..a025b36400 100644 +--- a/drivers/usb/gadget/dwc2_udc_otg.c ++++ b/drivers/usb/gadget/dwc2_udc_otg.c +@@ -1014,6 +1014,9 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) + platdata->force_b_session_valid = + dev_read_bool(dev, "u-boot,force-b-session-valid"); + ++ platdata->force_vbus_detection = ++ dev_read_bool(dev, "u-boot,force-vbus-detection"); ++ + /* force platdata according compatible */ + drvdata = dev_get_driver_data(dev); + if (drvdata) { +@@ -1106,31 +1109,45 @@ static int dwc2_udc_otg_probe(struct udevice *dev) + if (ret) + return ret; + +- if (CONFIG_IS_ENABLED(DM_REGULATOR) && +- platdata->activate_stm_id_vb_detection && +- !platdata->force_b_session_valid) { +- ret = device_get_supply_regulator(dev, "usb33d-supply", +- &priv->usb33d_supply); +- if (ret) { +- dev_err(dev, "can't get voltage level detector supply\n"); +- return ret; ++ if (platdata->activate_stm_id_vb_detection) { ++ if (CONFIG_IS_ENABLED(DM_REGULATOR) && ++ (!platdata->force_b_session_valid || ++ platdata->force_vbus_detection)) { ++ ret = device_get_supply_regulator(dev, "usb33d-supply", ++ &priv->usb33d_supply); ++ if (ret) { ++ dev_err(dev, "can't get voltage level detector supply\n"); ++ return ret; ++ } ++ ret = regulator_set_enable(priv->usb33d_supply, true); ++ if (ret) { ++ dev_err(dev, "can't enable voltage level detector supply\n"); ++ return ret; ++ } + } +- ret = regulator_set_enable(priv->usb33d_supply, true); +- if (ret) { +- dev_err(dev, "can't enable voltage level detector supply\n"); +- return ret; ++ ++ if (platdata->force_b_session_valid && ++ !platdata->force_vbus_detection) { ++ /* Override VBUS detection: enable then value*/ ++ setbits_le32(&usbotg_reg->gotgctl, VB_VALOEN); ++ setbits_le32(&usbotg_reg->gotgctl, VB_VALOVAL); ++ } else { ++ /* Enable VBUS sensing */ ++ setbits_le32(&usbotg_reg->ggpio, ++ GGPIO_STM32_OTG_GCCFG_VBDEN); ++ } ++ if (platdata->force_b_session_valid) { ++ /* Override B session bits: enable then value */ ++ setbits_le32(&usbotg_reg->gotgctl, A_VALOEN | B_VALOEN); ++ setbits_le32(&usbotg_reg->gotgctl, ++ A_VALOVAL | B_VALOVAL); ++ } else { ++ /* Enable ID detection */ ++ setbits_le32(&usbotg_reg->ggpio, ++ GGPIO_STM32_OTG_GCCFG_IDEN); + } +- /* Enable vbus sensing */ +- setbits_le32(&usbotg_reg->ggpio, +- GGPIO_STM32_OTG_GCCFG_VBDEN | +- GGPIO_STM32_OTG_GCCFG_IDEN); + } + +- if (platdata->force_b_session_valid) +- /* Override B session bits : value and enable */ +- setbits_le32(&usbotg_reg->gotgctl, +- A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL); +- + ret = dwc2_udc_probe(platdata); + if (ret) + return ret; +@@ -1160,7 +1177,7 @@ static int dwc2_udc_otg_remove(struct udevice *dev) + static const struct udevice_id dwc2_udc_otg_ids[] = { + { .compatible = "snps,dwc2" }, + { .compatible = "brcm,bcm2835-usb" }, +- { .compatible = "st,stm32mp1-hsotg", ++ { .compatible = "st,stm32mp15-hsotg", + .data = (ulong)dwc2_set_stm32mp1_hsotg_params }, + {}, + }; +diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h +index 2eda5c3720..9ca6f42375 100644 +--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h ++++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h +@@ -94,6 +94,8 @@ struct dwc2_usbotg_reg { + #define B_VALOEN BIT(6) + #define A_VALOVAL BIT(5) + #define A_VALOEN BIT(4) ++#define VB_VALOVAL BIT(3) ++#define VB_VALOEN BIT(2) + + /* DWC2_UDC_OTG_GOTINT */ + #define GOTGINT_SES_END_DET (1<<2) +diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c +index b7bfbb5e50..1303d99e56 100644 +--- a/drivers/video/dw_mipi_dsi.c ++++ b/drivers/video/dw_mipi_dsi.c +@@ -314,7 +314,8 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) + val, !(val & GEN_CMD_FULL), + CMD_PKT_STATUS_TIMEOUT_US); + if (ret) { +- dev_err(dsi->dev, "failed to get available command FIFO\n"); ++ dev_err(dsi->dsi_host.dev, ++ "failed to get available command FIFO\n"); + return ret; + } + +@@ -325,7 +326,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) + val, (val & mask) == mask, + CMD_PKT_STATUS_TIMEOUT_US); + if (ret) { +- dev_err(dsi->dev, "failed to write command FIFO\n"); ++ dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n"); + return ret; + } + +@@ -357,7 +358,7 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, + val, !(val & GEN_PLD_W_FULL), + CMD_PKT_STATUS_TIMEOUT_US); + if (ret) { +- dev_err(dsi->dev, ++ dev_err(dsi->dsi_host.dev, + "failed to get available write payload FIFO\n"); + return ret; + } +@@ -380,7 +381,7 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, + val, !(val & GEN_RD_CMD_BUSY), + CMD_PKT_STATUS_TIMEOUT_US); + if (ret) { +- dev_err(dsi->dev, "Timeout during read operation\n"); ++ dev_err(dsi->dsi_host.dev, "Timeout during read operation\n"); + return ret; + } + +@@ -390,7 +391,8 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, + val, !(val & GEN_PLD_R_EMPTY), + CMD_PKT_STATUS_TIMEOUT_US); + if (ret) { +- dev_err(dsi->dev, "Read payload FIFO is empty\n"); ++ dev_err(dsi->dsi_host.dev, ++ "Read payload FIFO is empty\n"); + return ret; + } + +@@ -411,7 +413,7 @@ static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, + + ret = mipi_dsi_create_packet(&packet, msg); + if (ret) { +- dev_err(dsi->dev, "failed to create packet: %d\n", ret); ++ dev_err(host->dev, "failed to create packet: %d\n", ret); + return ret; + } + +@@ -483,15 +485,27 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, + + static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi) + { ++ const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; ++ unsigned int esc_rate; ++ u32 esc_clk_division; ++ + /* + * The maximum permitted escape clock is 20MHz and it is derived from +- * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: ++ * lanebyteclk, which is running at "lane_mbps / 8". ++ */ ++ if (phy_ops->get_esc_clk_rate) ++ phy_ops->get_esc_clk_rate(dsi->device, &esc_rate); ++ else ++ esc_rate = 20; /* Default to 20MHz */ ++ ++ /* ++ * We want: + * +- * (lane_mbps >> 3) / esc_clk_division < 20 ++ * (lane_mbps >> 3) / esc_clk_division < X + * which is: +- * (lane_mbps >> 3) / 20 > esc_clk_division ++ * (lane_mbps >> 3) / X > esc_clk_division + */ +- u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; ++ esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; + + dsi_write(dsi, DSI_PWR_UP, RESET); + +@@ -643,8 +657,13 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, + + static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) + { ++ const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; ++ struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40}; + u32 hw_version; + ++ if (phy_ops->get_timing) ++ phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing); ++ + /* + * TODO dw drv improvements + * data & clock lane timers should be computed according to panel +@@ -656,16 +675,16 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) + hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; + + if (hw_version >= HWVER_131) { +- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) | +- PHY_LP2HS_TIME_V131(0x40)); ++ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) | ++ PHY_LP2HS_TIME_V131(timing.data_lp2hs)); + dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); + } else { +- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) | +- PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000)); ++ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) | ++ PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000)); + } + +- dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) +- | PHY_CLKLP2HS_TIME(0x40)); ++ dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp) ++ | PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); + } + + static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) +@@ -702,13 +721,15 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) + ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, + val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); + if (ret) +- dev_warn(dsi->dev, "failed to wait phy lock state\n"); ++ dev_dbg(dsi->dsi_host.dev, ++ "failed to wait phy lock state\n"); + + ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, + val, val & PHY_STOP_STATE_CLK_LANE, + PHY_STATUS_TIMEOUT_US); + if (ret) +- dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n"); ++ dev_dbg(dsi->dsi_host.dev, ++ "failed to wait phy clk lane stop state\n"); + } + + static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) +@@ -729,7 +750,7 @@ static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi, + ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes, + device->format, &dsi->lane_mbps); + if (ret) +- dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n"); ++ dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n"); + + dw_mipi_dsi_init_pll(dsi); + dw_mipi_dsi_dpi_config(dsi, timings); +@@ -748,7 +769,7 @@ static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi, + + ret = phy_ops->init(dsi->device); + if (ret) +- dev_warn(dsi->dev, "Phy init() failed\n"); ++ dev_warn(dsi->dsi_host.dev, "Phy init() failed\n"); + + dw_mipi_dsi_dphy_enable(dsi); + +@@ -776,6 +797,7 @@ static int dw_mipi_dsi_init(struct udevice *dev, + dsi->phy_ops = phy_ops; + dsi->max_data_lanes = max_data_lanes; + dsi->device = device; ++ dsi->dsi_host.dev = (struct device *)dev; + dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; + device->host = &dsi->dsi_host; + +diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c +index 283151398b..6c027b6388 100644 +--- a/drivers/video/stm32/stm32_dsi.c ++++ b/drivers/video/stm32/stm32_dsi.c +@@ -482,6 +482,9 @@ static int stm32_dsi_probe(struct udevice *dev) + if (priv->hw_version != HWVER_130 && + priv->hw_version != HWVER_131) { + dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version); ++ dev_dbg(dev, "remove and unbind all DSI child\n"); ++ device_chld_remove(dev, NULL, DM_REMOVE_NORMAL); ++ device_chld_unbind(dev, NULL); + ret = -ENODEV; + goto err_clk; + } +diff --git a/env/ext4.c b/env/ext4.c +index f823b69409..e03aa9d7da 100644 +--- a/env/ext4.c ++++ b/env/ext4.c +@@ -173,6 +173,5 @@ U_BOOT_ENV_LOCATION(ext4) = { + ENV_NAME("EXT4") + .load = env_ext4_load, + .save = ENV_SAVE_PTR(env_ext4_save), +- .erase = CONFIG_IS_ENABLED(CMD_ERASEENV) ? env_ext4_erase : +- NULL, ++ .erase = ENV_ERASE_PTR(env_ext4_erase), + }; +diff --git a/env/mmc.c b/env/mmc.c +index ba872701b0..7838874f4d 100644 +--- a/env/mmc.c ++++ b/env/mmc.c +@@ -237,7 +237,6 @@ fini: + return ret; + } + +-#if defined(CONFIG_CMD_ERASEENV) + static inline int erase_env(struct mmc *mmc, unsigned long size, + unsigned long offset) + { +@@ -283,7 +282,6 @@ static int env_mmc_erase(void) + + return ret; + } +-#endif /* CONFIG_CMD_ERASEENV */ + #endif /* CONFIG_CMD_SAVEENV && !CONFIG_SPL_BUILD */ + + static inline int read_env(struct mmc *mmc, unsigned long size, +@@ -398,8 +396,6 @@ U_BOOT_ENV_LOCATION(mmc) = { + .load = env_mmc_load, + #ifndef CONFIG_SPL_BUILD + .save = env_save_ptr(env_mmc_save), +-#if defined(CONFIG_CMD_ERASEENV) +- .erase = env_mmc_erase, +-#endif ++ .erase = ENV_ERASE_PTR(env_mmc_erase) + #endif + }; +diff --git a/env/sf.c b/env/sf.c +index 937778aa37..5f31b9dd2f 100644 +--- a/env/sf.c ++++ b/env/sf.c +@@ -27,9 +27,18 @@ + #define INITENV + #endif + ++#define OFFSET_INVALID (~(u32)0) ++ + #ifdef CONFIG_ENV_OFFSET_REDUND ++#define ENV_OFFSET_REDUND CONFIG_ENV_OFFSET_REDUND ++ + static ulong env_offset = CONFIG_ENV_OFFSET; + static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND; ++ ++#else ++ ++#define ENV_OFFSET_REDUND OFFSET_INVALID ++ + #endif /* CONFIG_ENV_OFFSET_REDUND */ + + DECLARE_GLOBAL_DATA_PTR; +@@ -279,6 +288,26 @@ out: + } + #endif + ++static int env_sf_erase(void) ++{ ++ int ret; ++ env_t env; ++ ++ ret = setup_flash_device(); ++ if (ret) ++ return ret; ++ ++ memset(&env, 0, sizeof(env_t)); ++ ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, &env); ++ if (ret) ++ return ret; ++ ++ if (ENV_OFFSET_REDUND != OFFSET_INVALID) ++ ret = spi_flash_write(env_flash, ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, &env); ++ ++ return ret; ++} ++ + #if CONFIG_ENV_ADDR != 0x0 + __weak void *env_sf_get_env_addr(void) + { +@@ -307,7 +336,8 @@ U_BOOT_ENV_LOCATION(sf) = { + .location = ENVL_SPI_FLASH, + ENV_NAME("SPIFlash") + .load = env_sf_load, +- .save = CONFIG_IS_ENABLED(SAVEENV) ? ENV_SAVE_PTR(env_sf_save) : NULL, ++ .save = ENV_SAVE_PTR(env_sf_save), ++ .erase = ENV_ERASE_PTR(env_sf_erase), + #if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0) + .init = env_sf_init, + #endif +diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h +index 768b4a6dfc..3ffc744928 100644 +--- a/include/configs/10m50_devboard.h ++++ b/include/configs/10m50_devboard.h +@@ -34,11 +34,6 @@ + */ + #define CONFIG_BOOTP_BOOTFILESIZE + +-/* +- * FDT options +- */ +-#define CONFIG_LMB +- + /* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. +diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h +index 30bbd716b2..3f065ff315 100644 +--- a/include/configs/3c120_devboard.h ++++ b/include/configs/3c120_devboard.h +@@ -34,11 +34,6 @@ + */ + #define CONFIG_BOOTP_BOOTFILESIZE + +-/* +- * FDT options +- */ +-#define CONFIG_LMB +- + /* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. +diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h +index 5554313810..d0a8d9b9d5 100644 +--- a/include/configs/sandbox.h ++++ b/include/configs/sandbox.h +@@ -22,8 +22,6 @@ + #define CONFIG_SYS_TIMER_RATE 1000000 + #endif + +-#define CONFIG_LMB +- + #define CONFIG_HOST_MAX_DEVICES 4 + + /* +diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h +index b937233797..32d0723d62 100644 +--- a/include/configs/stm32mp1.h ++++ b/include/configs/stm32mp1.h +@@ -148,7 +148,6 @@ + * and the ramdisk at the end. + */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +- "bootdelay=1\0" \ + "kernel_addr_r=0xc2000000\0" \ + "fdt_addr_r=0xc4000000\0" \ + "scriptaddr=0xc4100000\0" \ +diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h +index 641ed2c5ec..f186dd6b82 100644 +--- a/include/configs/x86-common.h ++++ b/include/configs/x86-common.h +@@ -16,8 +16,6 @@ + */ + #define CONFIG_PHYSMEM + +-#define CONFIG_LMB +- + #define CONFIG_SYS_BOOTM_LEN (16 << 20) + + /* SATA AHCI storage */ +diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h +index 8df2facf99..833b0be839 100644 +--- a/include/dm/ofnode.h ++++ b/include/dm/ofnode.h +@@ -344,6 +344,17 @@ const char *ofnode_read_string(ofnode node, const char *propname); + */ + int ofnode_read_u32_array(ofnode node, const char *propname, + u32 *out_values, size_t sz); ++/** ++ * ofnode_is_enabled() - Checks whether a node is enabled. ++ * This looks for a 'status' property. If this exists, then returns true if ++ * the status is 'okay' and false otherwise. If there is no status property, ++ * it returns true on the assumption that anything mentioned should be enabled ++ * by default. ++ * ++ * @node: node to examine ++ * @return false (not enabled) or true (enabled) ++ */ ++bool ofnode_is_enabled(ofnode node); + + /** + * ofnode_read_bool() - read a boolean value from a property +diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h +index 4ec5fa6670..88f10c4622 100644 +--- a/include/dm/uclass-id.h ++++ b/include/dm/uclass-id.h +@@ -94,6 +94,7 @@ enum uclass_id { + UCLASS_RESET, /* Reset controller device */ + UCLASS_RNG, /* Random Number Generator */ + UCLASS_RTC, /* Real time clock device */ ++ UCLASS_SCMI_AGENT, /* Interface with an SCMI server */ + UCLASS_SCSI, /* SCSI device */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SIMPLE_BUS, /* Bus with child devices */ +diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h +index 4cdaf13582..ec7b1a9320 100644 +--- a/include/dt-bindings/clock/stm32mp1-clks.h ++++ b/include/dt-bindings/clock/stm32mp1-clks.h +@@ -179,6 +179,12 @@ + #define DAC12_K 168 + #define ETHPTP_K 169 + ++#define PCLK1 170 ++#define PCLK2 171 ++#define PCLK3 172 ++#define PCLK4 173 ++#define PCLK5 174 ++ + /* PLL */ + #define PLL1 176 + #define PLL2 177 +@@ -248,4 +254,31 @@ + + #define STM32MP1_LAST_CLK 232 + ++/* SCMI clock identifiers */ ++#define CK_SCMI0_HSE 0 ++#define CK_SCMI0_HSI 1 ++#define CK_SCMI0_CSI 2 ++#define CK_SCMI0_LSE 3 ++#define CK_SCMI0_LSI 4 ++#define CK_SCMI0_PLL2_Q 5 ++#define CK_SCMI0_PLL2_R 6 ++#define CK_SCMI0_MPU 7 ++#define CK_SCMI0_AXI 8 ++#define CK_SCMI0_BSEC 9 ++#define CK_SCMI0_CRYP1 10 ++#define CK_SCMI0_GPIOZ 11 ++#define CK_SCMI0_HASH1 12 ++#define CK_SCMI0_I2C4 13 ++#define CK_SCMI0_I2C6 14 ++#define CK_SCMI0_IWDG1 15 ++#define CK_SCMI0_RNG1 16 ++#define CK_SCMI0_RTC 17 ++#define CK_SCMI0_RTCAPB 18 ++#define CK_SCMI0_SPI6 19 ++#define CK_SCMI0_USART1 20 ++ ++#define CK_SCMI1_PLL3_Q 0 ++#define CK_SCMI1_PLL3_R 1 ++#define CK_SCMI1_MCU 2 ++ + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ +diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h +index e6fb8ada3f..370a25a936 100644 +--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h ++++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h +@@ -26,6 +26,7 @@ + #define AF14 0xf + #define AF15 0x10 + #define ANALOG 0x11 ++#define RSVD 0x12 + + /* define Pins number*/ + #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) +diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h +index f0c3aaef67..f3a0ed3178 100644 +--- a/include/dt-bindings/reset/stm32mp1-resets.h ++++ b/include/dt-bindings/reset/stm32mp1-resets.h +@@ -7,6 +7,7 @@ + #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ + #define _DT_BINDINGS_STM32MP1_RESET_H_ + ++#define MCU_HOLD_BOOT_R 2144 + #define LTDC_R 3072 + #define DSI_R 3076 + #define DDRPERFM_R 3080 +@@ -105,4 +106,18 @@ + #define GPIOJ_R 19785 + #define GPIOK_R 19786 + ++/* SCMI reset domain identifiers */ ++#define RST_SCMI0_SPI6 0 ++#define RST_SCMI0_I2C4 1 ++#define RST_SCMI0_I2C6 2 ++#define RST_SCMI0_USART1 3 ++#define RST_SCMI0_STGEN 4 ++#define RST_SCMI0_GPIOZ 5 ++#define RST_SCMI0_CRYP1 6 ++#define RST_SCMI0_HASH1 7 ++#define RST_SCMI0_RNG1 8 ++#define RST_SCMI0_MDMA 9 ++#define RST_SCMI0_MCU 10 ++#define RST_SCMI0_MCU_HOLD_BOOT 11 ++ + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ +diff --git a/include/dt-bindings/rtc/rtc-stm32.h b/include/dt-bindings/rtc/rtc-stm32.h +new file mode 100644 +index 0000000000..4373c4dea5 +--- /dev/null ++++ b/include/dt-bindings/rtc/rtc-stm32.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * This header provides constants for STM32_RTC bindings. ++ */ ++ ++#ifndef _DT_BINDINGS_RTC_RTC_STM32_H ++#define _DT_BINDINGS_RTC_RTC_STM32_H ++ ++#define RTC_OUT1 0 ++#define RTC_OUT2 1 ++#define RTC_OUT2_RMP 2 ++ ++#endif +diff --git a/include/dt-bindings/soc/stm32-hdp.h b/include/dt-bindings/soc/stm32-hdp.h +new file mode 100644 +index 0000000000..d986653272 +--- /dev/null ++++ b/include/dt-bindings/soc/stm32-hdp.h +@@ -0,0 +1,108 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ ++/* ++ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved ++ * Author: Roullier Christophe ++ * for STMicroelectronics. ++ */ ++ ++#ifndef _DT_BINDINGS_STM32_HDP_H ++#define _DT_BINDINGS_STM32_HDP_H ++ ++#define STM32_HDP(port, value) ((value) << ((port) * 4)) ++ ++/* define HDP Pins number*/ ++#define HDP0_PWR_PWRWAKE_SYS 0 ++#define HDP0_CM4_SLEEPDEEP 1 ++#define HDP0_PWR_STDBY_WKUP 2 ++#define HDP0_PWR_ENCOMP_VDDCORE 3 ++#define HDP0_BSEC_OUT_SEC_NIDEN 4 ++#define HDP0_RCC_CM4_SLEEPDEEP 6 ++#define HDP0_GPU_DBG7 7 ++#define HDP0_DDRCTRL_LP_REQ 8 ++#define HDP0_PWR_DDR_RET_ENABLE_N 9 ++#define HDP0_GPOVAL_0 15 ++ ++#define HDP1_PWR_PWRWAKE_MCU 0 ++#define HDP1_CM4_HALTED 1 ++#define HDP1_CA7_NAXIERRIRQ 2 ++#define HDP1_PWR_OKIN_MR 3 ++#define HDP1_BSEC_OUT_SEC_DBGEN 4 ++#define HDP1_EXTI_SYS_WAKEUP 5 ++#define HDP1_RCC_PWRDS_MPU 6 ++#define HDP1_GPU_DBG6 7 ++#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ 8 ++#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR 9 ++#define HDP1_GPOVAL_1 15 ++ ++#define HDP2_PWR_PWRWAKE_MPU 0 ++#define HDP2_CM4_RXEV 1 ++#define HDP2_CA7_NPMUIRQ1 2 ++#define HDP2_CA7_NFIQOUT1 3 ++#define HDP2_BSEC_IN_RSTCORE_N 4 ++#define HDP2_EXTI_C2_WAKEUP 5 ++#define HDP2_RCC_PWRDS_MCU 6 ++#define HDP2_GPU_DBG5 7 ++#define HDP2_DDRCTRL_DFI_INIT_COMPLETE 8 ++#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH 9 ++#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ 10 ++#define HDP2_GPOVAL_2 15 ++ ++#define HDP3_PWR_SEL_VTH_VDD_CORE 0 ++#define HDP3_CM4_TXEV 1 ++#define HDP3_CA7_NPMUIRQ0 2 ++#define HDP3_CA7_NFIQOUT0 3 ++#define HDP3_BSEC_OUT_SEC_DFTLOCK 4 ++#define HDP3_EXTI_C1_WAKEUP 5 ++#define HDP3_RCC_PWRDS_SYS 6 ++#define HDP3_GPU_DBG4 7 ++#define HDP3_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE0 8 ++#define HDP3_DDRCTRL_CACTIVE_1 9 ++#define HDP3_GPOVAL_3 15 ++ ++#define HDP4_PWR_PDDS 0 ++#define HDP4_CM4_SLEEPING 1 ++#define HDP4_CA7_NRESET1 2 ++#define HDP4_CA7_NIRQOUT1 3 ++#define HDP4_BSEC_OUT_SEC_DFTEN 4 ++#define HDP4_BSEC_OUT_SEC_DBGSWENABLE 5 ++#define HDP4_ETH_OUT_PMT_INTR_O 6 ++#define HDP4_GPU_DBG3 7 ++#define HDP4_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE1 8 ++#define HDP4_DDRCTRL_CACTIVE_0 9 ++#define HDP4_GPOVAL_4 15 ++ ++#define HDP5_CA7_STANDBYWFIL2 0 ++#define HDP5_PWR_VTH_VDDCORE_ACK 1 ++#define HDP5_CA7_NRESET0 2 ++#define HDP5_CA7_NIRQOUT0 3 ++#define HDP5_BSEC_IN_PWROK 4 ++#define HDP5_BSEC_OUT_SEC_DEVICEEN 5 ++#define HDP5_ETH_OUT_LPI_INTR_O 6 ++#define HDP5_GPU_DBG2 7 ++#define HDP5_DDRCTRL_CACTIVE_DDRC 8 ++#define HDP5_DDRCTRL_WR_CREDIT_CNT 9 ++#define HDP5_GPOVAL_5 15 ++ ++#define HDP6_CA7_STANDBYWFI1 0 ++#define HDP6_CA7_STANDBYWFE1 1 ++#define HDP6_CA7_EVENT0 2 ++#define HDP6_CA7_DBGACK1 3 ++#define HDP6_BSEC_OUT_SEC_SPNIDEN 5 ++#define HDP6_ETH_OUT_MAC_SPEED_O1 6 ++#define HDP6_GPU_DBG1 7 ++#define HDP6_DDRCTRL_CSYSACK_DDRC 8 ++#define HDP6_DDRCTRL_LPR_CREDIT_CNT 9 ++#define HDP6_GPOVAL_6 15 ++ ++#define HDP7_CA7_STANDBYWFI0 0 ++#define HDP7_CA7_STANDBYWFE0 1 ++#define HDP7_CA7_DBGACK0 3 ++#define HDP7_BSEC_OUT_FUSE_OK 4 ++#define HDP7_BSEC_OUT_SEC_SPIDEN 5 ++#define HDP7_ETH_OUT_MAC_SPEED_O0 6 ++#define HDP7_GPU_DBG0 7 ++#define HDP7_DDRCTRL_CSYSREQ_DDRC 8 ++#define HDP7_DDRCTRL_HPR_CREDIT_CNT 9 ++#define HDP7_GPOVAL_7 15 ++ ++#endif /* _DT_BINDINGS_STM32_HDP_H */ +diff --git a/include/env_internal.h b/include/env_internal.h +index b26dc6239c..67fd729ba0 100644 +--- a/include/env_internal.h ++++ b/include/env_internal.h +@@ -207,6 +207,7 @@ struct env_driver { + #endif + + #define ENV_SAVE_PTR(x) (CONFIG_IS_ENABLED(SAVEENV) ? (x) : NULL) ++#define ENV_ERASE_PTR(x) (CONFIG_IS_ENABLED(CMD_ERASEENV) ? (x) : NULL) + + extern struct hsearch_data env_htab; + +diff --git a/include/fdtdec.h b/include/fdtdec.h +index 152eb07b9e..62d1660973 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -1029,7 +1029,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) + * }; + * uint32_t phandle; + * +- * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); ++ * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); + * + * This results in the following subnode being added to the top-level + * /reserved-memory node: +@@ -1056,11 +1056,12 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) + * @param carveout information about the carveout region + * @param phandlep return location for the phandle of the carveout region + * can be NULL if no phandle should be added ++ * @param no_map add "no-map" property if true + * @return 0 on success or a negative error code on failure + */ + int fdtdec_add_reserved_memory(void *blob, const char *basename, + const struct fdt_memory *carveout, +- uint32_t *phandlep); ++ uint32_t *phandlep, bool no_map); + + /** + * fdtdec_get_carveout() - reads a carveout from an FDT +diff --git a/include/image.h b/include/image.h +index 9a5a87dbf8..c2df0b3aa5 100644 +--- a/include/image.h ++++ b/include/image.h +@@ -430,7 +430,7 @@ typedef struct bootm_headers { + #define BOOTM_STATE_OS_GO (0x00000400) + int state; + +-#ifdef CONFIG_LMB ++#if defined(CONFIG_LMB) && !defined(USE_HOSTCC) + struct lmb lmb; /* for memory mgmt */ + #endif + } bootm_headers_t; +diff --git a/include/lmb.h b/include/lmb.h +index e9f19b16ea..f839359178 100644 +--- a/include/lmb.h ++++ b/include/lmb.h +@@ -12,22 +12,33 @@ + * Copyright (C) 2001 Peter Bergner, IBM Corp. + */ + +-#define MAX_LMB_REGIONS 8 ++/** ++ * enum lmb_flags - definition of memory region attributes ++ * @LMB_NONE: no special request ++ * @LMB_NOMAP: don't add to mmu configuration ++ */ ++enum lmb_flags { ++ LMB_NONE = 0x0, /* No special request */ ++ LMB_NOMAP = 0x4, /* don't add to mmu config */ ++}; + + struct lmb_property { + phys_addr_t base; + phys_size_t size; ++ enum lmb_flags flags; + }; + + struct lmb_region { +- unsigned long cnt; +- phys_size_t size; +- struct lmb_property region[MAX_LMB_REGIONS+1]; ++ unsigned long cnt; /* number of regions */ ++ unsigned long max; /* size of the allocated array */ ++ struct lmb_property *region; + }; + + struct lmb { + struct lmb_region memory; + struct lmb_region reserved; ++ struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS + 1]; ++ struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS + 1]; + }; + + extern void lmb_init(struct lmb *lmb); +@@ -37,6 +48,8 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, + phys_size_t size, void *fdt_blob); + extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); + extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); ++extern long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, ++ phys_size_t size, enum lmb_flags flags); + extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); + extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, + phys_addr_t max_addr); +@@ -46,6 +59,7 @@ extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, + phys_size_t size); + extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); + extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); ++extern int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); + extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); + + extern void lmb_dump_all(struct lmb *lmb); +@@ -60,6 +74,13 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) + void board_lmb_reserve(struct lmb *lmb); + void arch_lmb_reserve(struct lmb *lmb); + ++/* Low level functions */ ++ ++static inline bool lmb_is_nomap(struct lmb_property *m) ++{ ++ return !!(m->flags & LMB_NOMAP); ++} ++ + #endif /* __KERNEL__ */ + + #endif /* _LINUX_LMB_H */ +diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h +index c8a7d3daef..4ca05f71e2 100644 +--- a/include/mipi_dsi.h ++++ b/include/mipi_dsi.h +@@ -96,6 +96,20 @@ struct mipi_dsi_host_ops { + const struct mipi_dsi_msg *msg); + }; + ++/** ++ * struct mipi_dsi_phy_timing - DSI host phy timings ++ * @data_hs2lp: High Speed to Low Speed Data Transition Time ++ * @data_lp2hs: Low Speed to High Speed Data Transition Time ++ * @clk_hs2lp: High Speed to Low Speed Clock Transition Time ++ * @clk_lp2hs: Low Speed to High Speed Clock Transition Time ++ */ ++struct mipi_dsi_phy_timing { ++ u16 data_hs2lp; ++ u16 data_lp2hs; ++ u16 clk_hs2lp; ++ u16 clk_lp2hs; ++}; ++ + /** + * struct mipi_dsi_phy_ops - DSI host physical operations + * @init: initialized host physical part +@@ -107,6 +121,9 @@ struct mipi_dsi_phy_ops { + int (*get_lane_mbps)(void *priv_data, struct display_timing *timings, + u32 lanes, u32 format, unsigned int *lane_mbps); + void (*post_set_mode)(void *priv_data, unsigned long mode_flags); ++ int (*get_timing)(void *priv_data, unsigned int lane_mbps, ++ struct mipi_dsi_phy_timing *timing); ++ void (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate); + }; + + /** +diff --git a/include/rproc_optee.h b/include/rproc_optee.h +new file mode 100644 +index 0000000000..13193bbe77 +--- /dev/null ++++ b/include/rproc_optee.h +@@ -0,0 +1,127 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved ++ */ ++ ++#ifndef _RPROC_OPTEE_H_ ++#define _RPROC_OPTEE_H_ ++ ++/** ++ * struct rproc_optee - TEE remoteproc structure ++ * @tee: TEE device ++ * @fw_id: Identifier of the target firmware ++ * @session: TEE session identifier ++ */ ++struct rproc_optee { ++ struct udevice *tee; ++ u32 fw_id; ++ u32 session; ++}; ++ ++#if IS_ENABLED(CONFIG_REMOTEPROC_OPTEE) ++ ++/** ++ * rproc_optee_open() - open a rproc tee session ++ * ++ * Open a session towards the trusted application in charge of the remote ++ * processor. ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * ++ * @return 0 if the session is opened, or an appropriate error value. ++ */ ++int rproc_optee_open(struct rproc_optee *trproc); ++ ++/** ++ * rproc_optee_close() - close a rproc tee session ++ * ++ * Close the trusted application session in charge of the remote processor. ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * ++ * @return 0 on success, or an appropriate error value. ++ */ ++int rproc_optee_close(struct rproc_optee *trproc); ++ ++/** ++ * rproc_optee_start() - Request OP-TEE to start a remote processor ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * ++ * @return 0 on success, or an appropriate error value. ++ */ ++int rproc_optee_start(struct rproc_optee *trproc); ++ ++/** ++ * rproc_optee_stop() - Request OP-TEE to stop a remote processor ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * ++ * @return 0 on success, or an appropriate error value. ++ */ ++int rproc_optee_stop(struct rproc_optee *trproc); ++ ++/** ++ * rproc_optee_get_rsc_table() - Request OP-TEE the resource table ++ * ++ * Get the address and the size of the resource table. If no resource table is ++ * found, the size and address are null. ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * @rsc_addr: out the physical address of the resource table returned ++ * @rsc_size: out the size of the resource table ++ * ++ * @return 0 on success, or an appropriate error value. ++ */ ++int rproc_optee_get_rsc_table(struct rproc_optee *trproc, phys_addr_t *rsc_addr, ++ phys_size_t *rsc_size); ++ ++/** ++ * rproc_optee_load() - load an signed ELF image ++ * ++ * @trproc: OPTEE remoteproc context structure ++ * @addr: valid ELF image address ++ * @size: size of the image ++ * ++ * @return 0 if the image is successfully loaded, else appropriate error value. ++ */ ++int rproc_optee_load(struct rproc_optee *trproc, ulong addr, ulong size); ++ ++#else ++ ++static inline int rproc_optee_open(struct rproc_optee *trproc) ++{ ++ return -ENOSYS; ++} ++ ++static inline int rproc_optee_close(struct rproc_optee *trproc) ++{ ++ return -ENOSYS; ++} ++ ++static inline int rproc_optee_start(struct rproc_optee *trproc) ++{ ++ return -ENOSYS; ++} ++ ++static inline int rproc_optee_stop(struct rproc_optee *trproc) ++{ ++ return -ENOSYS; ++} ++ ++static inline int rproc_optee_get_rsc_table(struct rproc_optee *trproc, ++ phys_addr_t *rsc_addr, ++ phys_size_t *rsc_size) ++{ ++ return -ENOSYS; ++} ++ ++static inline int rproc_optee_load(struct rproc_optee *trproc, ulong addr, ++ ulong size) ++{ ++ return -ENOSYS; ++} ++ ++#endif ++ ++#endif /* _RPROC_OPTEE_H_ */ +diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h +new file mode 100644 +index 0000000000..a501d1b482 +--- /dev/null ++++ b/include/scmi_agent-uclass.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2019-2020 Linaro Limited. ++ */ ++#ifndef _SCMI_AGENT_UCLASS_H ++#define _SCMI_AGENT_UCLASS_H ++ ++struct udevice; ++struct scmi_msg; ++ ++/** ++ * struct scmi_transport_ops - The functions that a SCMI transport layer must implement. ++ */ ++struct scmi_agent_ops { ++ /* ++ * process_msg - Request transport to get the SCMI message processed ++ * ++ * @agent: Agent using the transport ++ * @msg: SCMI message to be transmitted ++ */ ++ int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); ++}; ++ ++#endif /* _SCMI_TRANSPORT_UCLASS_H */ +diff --git a/include/scmi_agent.h b/include/scmi_agent.h +new file mode 100644 +index 0000000000..f1be9ff209 +--- /dev/null ++++ b/include/scmi_agent.h +@@ -0,0 +1,68 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* ++ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. ++ * Copyright (C) 2019-2020, Linaro Limited ++ * ++ * An SCMI agent device represent on communication path from a ++ * device driver to the remote SCMI server which driver sends ++ * messages to and receives response messages from. ++ */ ++#ifndef SCMI_AGENT_H ++#define SCMI_AGENT_H ++ ++#include ++ ++struct udevice; ++ ++/* ++ * struct scmi_msg - Context of a SCMI message sent and the response received ++ * ++ * @protocol_id: SCMI protocol ID ++ * @message_id: SCMI message ID for a defined protocol ID ++ * @in_msg: Pointer to the message payload sent by the driver ++ * @in_msg_sz: Byte size of the message payload sent ++ * @out_msg: Pointer to buffer to store response message payload ++ * @out_msg_sz: Byte size of the response buffer and response payload ++ */ ++struct scmi_msg { ++ unsigned int protocol_id; ++ unsigned int message_id; ++ u8 *in_msg; ++ size_t in_msg_sz; ++ u8 *out_msg; ++ size_t out_msg_sz; ++}; ++ ++/* Helper macro to match a message on input/output array references */ ++#define SCMI_MSG_IN(_protocol, _message, _in_array, _out_array) \ ++ (struct scmi_msg){ \ ++ .protocol_id = (_protocol), \ ++ .message_id = (_message), \ ++ .in_msg = (uint8_t *)&(_in_array), \ ++ .in_msg_sz = sizeof(_in_array), \ ++ .out_msg = (uint8_t *)&(_out_array), \ ++ .out_msg_sz = sizeof(_out_array), \ ++ } ++ ++/** ++ * scmi_send_and_process_msg() - send and process a SCMI message ++ * ++ * Send a message to a SCMI server through a target SCMI agent device. ++ * Caller sets scmi_msg::out_msg_sz to the output message buffer size. ++ * On return, scmi_msg::out_msg_sz stores the response payload size. ++ * ++ * @dev: SCMI agent device ++ * @msg: Message structure reference ++ * @return 0 on success and a negative errno on failure ++ */ ++int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg); ++ ++/** ++ * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code ++ * ++ * @scmi_errno: SCMI error code value ++ * @return 0 for successful status and a negative errno otherwise ++ */ ++int scmi_to_linux_errno(s32 scmi_errno); ++ ++#endif /* SCMI_H */ +diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h +new file mode 100644 +index 0000000000..ccab97c96c +--- /dev/null ++++ b/include/scmi_protocols.h +@@ -0,0 +1,179 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* ++ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. ++ * Copyright (C) 2019-2020, Linaro Limited ++ */ ++#ifndef _SCMI_PROTOCOLS_H ++#define _SCMI_PROTOCOLS_H ++ ++#include ++#include ++ ++/* ++ * Subset the SCMI protocols definition ++ * based on SCMI specification v2.0 (DEN0056B) ++ * https://developer.arm.com/docs/den0056/b ++ */ ++ ++enum scmi_std_protocol { ++ SCMI_PROTOCOL_ID_BASE = 0x10, ++ SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, ++ SCMI_PROTOCOL_ID_SYSTEM = 0x12, ++ SCMI_PROTOCOL_ID_PERF = 0x13, ++ SCMI_PROTOCOL_ID_CLOCK = 0x14, ++ SCMI_PROTOCOL_ID_SENSOR = 0x15, ++ SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, ++}; ++ ++enum scmi_status_code { ++ SCMI_SUCCESS = 0, ++ SCMI_NOT_SUPPORTED = -1, ++ SCMI_INVALID_PARAMETERS = -2, ++ SCMI_DENIED = -3, ++ SCMI_NOT_FOUND = -4, ++ SCMI_OUT_OF_RANGE = -5, ++ SCMI_BUSY = -6, ++ SCMI_COMMS_ERROR = -7, ++ SCMI_GENERIC_ERROR = -8, ++ SCMI_HARDWARE_ERROR = -9, ++ SCMI_PROTOCOL_ERROR = -10, ++}; ++ ++/* ++ * SCMI Clock Protocol ++ */ ++ ++enum scmi_clock_message_id { ++ SCMI_CLOCK_RATE_SET = 0x5, ++ SCMI_CLOCK_RATE_GET = 0x6, ++ SCMI_CLOCK_CONFIG_SET = 0x7, ++}; ++ ++#define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0) ++#define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1)) ++#define SCMI_CLK_RATE_ROUND_DOWN 0 ++#define SCMI_CLK_RATE_ROUND_UP BIT(2) ++#define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3) ++ ++/** ++ * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command ++ * @clock_id: SCMI clock ID ++ * @attributes: Attributes of the targets clock state ++ */ ++struct scmi_clk_state_in { ++ u32 clock_id; ++ u32 attributes; ++}; ++ ++/** ++ * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command ++ * @status: SCMI command status ++ */ ++struct scmi_clk_state_out { ++ s32 status; ++}; ++ ++/** ++ * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command ++ * @clock_id: SCMI clock ID ++ * @attributes: Attributes of the targets clock state ++ */ ++struct scmi_clk_rate_get_in { ++ u32 clock_id; ++}; ++ ++/** ++ * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command ++ * @status: SCMI command status ++ * @rate_lsb: 32bit LSB of the clock rate in Hertz ++ * @rate_msb: 32bit MSB of the clock rate in Hertz ++ */ ++struct scmi_clk_rate_get_out { ++ s32 status; ++ u32 rate_lsb; ++ u32 rate_msb; ++}; ++ ++/** ++ * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command ++ * @clock_id: SCMI clock ID ++ * @flags: Flags for the clock rate set request ++ * @rate_lsb: 32bit LSB of the clock rate in Hertz ++ * @rate_msb: 32bit MSB of the clock rate in Hertz ++ */ ++struct scmi_clk_rate_set_in { ++ u32 clock_id; ++ u32 flags; ++ u32 rate_lsb; ++ u32 rate_msb; ++}; ++ ++/** ++ * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command ++ * @status: SCMI command status ++ */ ++struct scmi_clk_rate_set_out { ++ s32 status; ++}; ++ ++/* ++ * SCMI Reset Domain Protocol ++ */ ++ ++enum scmi_reset_domain_message_id { ++ SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3, ++ SCMI_RESET_DOMAIN_RESET = 0x4, ++}; ++ ++#define SCMI_RD_NAME_LEN 16 ++ ++#define SCMI_RD_ATTRIBUTES_FLAG_ASYNC BIT(31) ++#define SCMI_RD_ATTRIBUTES_FLAG_NOTIF BIT(30) ++ ++#define SCMI_RD_RESET_FLAG_ASYNC BIT(2) ++#define SCMI_RD_RESET_FLAG_ASSERT BIT(1) ++#define SCMI_RD_RESET_FLAG_CYCLE BIT(0) ++ ++/** ++ * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message ++ * @domain_id: SCMI reset domain ID ++ */ ++struct scmi_rd_attr_in { ++ u32 domain_id; ++}; ++ ++/** ++ * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response ++ * @status: SCMI command status ++ * @attributes: Retrieved attributes of the reset domain ++ * @latency: Reset cycle max lantency ++ * @name: Reset domain name ++ */ ++struct scmi_rd_attr_out { ++ s32 status; ++ u32 attributes; ++ u32 latency; ++ char name[SCMI_RD_NAME_LEN]; ++}; ++ ++/** ++ * struct scmi_rd_reset_in - Message payload for RESET command ++ * @domain_id: SCMI reset domain ID ++ * @flags: Flags for the reset request ++ * @reset_state: Reset target state ++ */ ++struct scmi_rd_reset_in { ++ u32 domain_id; ++ u32 flags; ++ u32 reset_state; ++}; ++ ++/** ++ * struct scmi_rd_reset_out - Response payload for RESET command ++ * @status: SCMI command status ++ */ ++struct scmi_rd_reset_out { ++ s32 status; ++}; ++ ++#endif /* _SCMI_PROTOCOLS_H */ +diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h +index a2af381a66..aa37e957b4 100644 +--- a/include/usb/dwc2_udc.h ++++ b/include/usb/dwc2_udc.h +@@ -28,6 +28,7 @@ struct dwc2_plat_otg_data { + unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS]; + unsigned char tx_fifo_sz_nb; + bool force_b_session_valid; ++ bool force_vbus_detection; + bool activate_stm_id_vb_detection; + }; + +diff --git a/lib/Kconfig b/lib/Kconfig +index 8efb154f73..c27204c520 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -684,4 +684,27 @@ config LIB_ELF + Supoort basic elf loading/validating functions. + This supports fir 32 bit and 64 bit versions. + ++config LMB ++ bool "Enable the logical memory blocks library (lmb)" ++ default y if ARC || ARM || M68K || MICROBLAZE || MIPS || NDS32 || \ ++ NIOS2 || PPC || RISCV || SANDBOX || SH || X86 || XTENSA ++ help ++ Support the library logical memory blocks. ++ ++config LMB_MEMORY_REGIONS ++ int "Number of memory regions in lmb lib" ++ depends on LMB ++ default 8 ++ help ++ Define the number of supported memory regions in the library logical ++ memory blocks. ++ ++config LMB_RESERVED_REGIONS ++ int "Number of reserved regions in lmb lib" ++ depends on LMB ++ default 8 ++ help ++ Define the number of supported reserved regions in the library logical ++ memory blocks. ++ + endmenu +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index 5f41f58a63..f16a85c8c5 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1319,7 +1319,7 @@ static int fdtdec_init_reserved_memory(void *blob) + + int fdtdec_add_reserved_memory(void *blob, const char *basename, + const struct fdt_memory *carveout, +- uint32_t *phandlep) ++ uint32_t *phandlep, bool no_map) + { + fdt32_t cells[4] = {}, *ptr = cells; + uint32_t upper, lower, phandle; +@@ -1419,6 +1419,12 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, + if (err < 0) + return err; + ++ if (no_map) { ++ err = fdt_setprop(blob, node, "no-map", NULL, 0); ++ if (err < 0) ++ return err; ++ } ++ + /* return the phandle for the new node for the caller to use */ + if (phandlep) + *phandlep = phandle; +@@ -1484,7 +1490,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, + fdt32_t value; + void *prop; + +- err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle); ++ err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false); + if (err < 0) { + debug("failed to add reserved memory: %d\n", err); + return err; +diff --git a/lib/lmb.c b/lib/lmb.c +index 75082f3559..6729c341b0 100644 +--- a/lib/lmb.c ++++ b/lib/lmb.c +@@ -14,32 +14,32 @@ + + #define LMB_ALLOC_ANYWHERE 0 + +-void lmb_dump_all_force(struct lmb *lmb) ++static void lmb_dump_region(struct lmb_region *rgn, char *name) + { +- unsigned long i; ++ unsigned long long base, size, end; ++ enum lmb_flags flags; ++ int i; + +- printf("lmb_dump_all:\n"); +- printf(" memory.cnt = 0x%lx\n", lmb->memory.cnt); +- printf(" memory.size = 0x%llx\n", +- (unsigned long long)lmb->memory.size); +- for (i = 0; i < lmb->memory.cnt; i++) { +- printf(" memory.reg[0x%lx].base = 0x%llx\n", i, +- (unsigned long long)lmb->memory.region[i].base); +- printf(" .size = 0x%llx\n", +- (unsigned long long)lmb->memory.region[i].size); +- } ++ printf(" %s.cnt = 0x%lx\n", name, rgn->cnt); + +- printf("\n reserved.cnt = 0x%lx\n", lmb->reserved.cnt); +- printf(" reserved.size = 0x%llx\n", +- (unsigned long long)lmb->reserved.size); +- for (i = 0; i < lmb->reserved.cnt; i++) { +- printf(" reserved.reg[0x%lx].base = 0x%llx\n", i, +- (unsigned long long)lmb->reserved.region[i].base); +- printf(" .size = 0x%llx\n", +- (unsigned long long)lmb->reserved.region[i].size); ++ for (i = 0; i < rgn->cnt; i++) { ++ base = rgn->region[i].base; ++ size = rgn->region[i].size; ++ end = base + size - 1; ++ flags = rgn->region[i].flags; ++ ++ printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n", ++ name, i, base, end, size, flags); + } + } + ++void lmb_dump_all_force(struct lmb *lmb) ++{ ++ printf("lmb_dump_all:\n"); ++ lmb_dump_region(&lmb->memory, "memory"); ++ lmb_dump_region(&lmb->reserved, "reserved"); ++} ++ + void lmb_dump_all(struct lmb *lmb) + { + #ifdef DEBUG +@@ -85,6 +85,7 @@ static void lmb_remove_region(struct lmb_region *rgn, unsigned long r) + for (i = r; i < rgn->cnt - 1; i++) { + rgn->region[i].base = rgn->region[i + 1].base; + rgn->region[i].size = rgn->region[i + 1].size; ++ rgn->region[i].flags = rgn->region[i + 1].flags; + } + rgn->cnt--; + } +@@ -99,10 +100,14 @@ static void lmb_coalesce_regions(struct lmb_region *rgn, unsigned long r1, + + void lmb_init(struct lmb *lmb) + { ++ /* Hookup the initial arrays */ ++ lmb->memory.region = lmb->memory_regions; ++ lmb->memory.max = ARRAY_SIZE(lmb->memory_regions) - 1; + lmb->memory.cnt = 0; +- lmb->memory.size = 0; ++ ++ lmb->reserved.region = lmb->reserved_regions; ++ lmb->reserved.max = ARRAY_SIZE(lmb->reserved_regions) - 1; + lmb->reserved.cnt = 0; +- lmb->reserved.size = 0; + } + + static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob) +@@ -146,7 +151,8 @@ void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, + } + + /* This routine called with relocation disabled. */ +-static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) ++static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, ++ phys_size_t size, enum lmb_flags flags) + { + unsigned long coalesced = 0; + long adjacent, i; +@@ -154,6 +160,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + if (rgn->cnt == 0) { + rgn->region[0].base = base; + rgn->region[0].size = size; ++ rgn->region[0].flags = flags; + rgn->cnt = 1; + return 0; + } +@@ -162,18 +169,27 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + for (i = 0; i < rgn->cnt; i++) { + phys_addr_t rgnbase = rgn->region[i].base; + phys_size_t rgnsize = rgn->region[i].size; ++ phys_size_t rgnflags = rgn->region[i].flags; + +- if ((rgnbase == base) && (rgnsize == size)) +- /* Already have this region, so we're done */ +- return 0; ++ if (rgnbase == base && rgnsize == size) { ++ if (flags == rgnflags) ++ /* Already have this region, so we're done */ ++ return 0; ++ else ++ return -1; /* regions with new flags */ ++ } + + adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); + if (adjacent > 0) { ++ if (flags != rgnflags) ++ break; + rgn->region[i].base -= size; + rgn->region[i].size += size; + coalesced++; + break; + } else if (adjacent < 0) { ++ if (flags != rgnflags) ++ break; + rgn->region[i].size += size; + coalesced++; + break; +@@ -184,13 +200,15 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + } + + if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) { +- lmb_coalesce_regions(rgn, i, i + 1); +- coalesced++; ++ if (rgn->region[i].flags == rgn->region[i + 1].flags) { ++ lmb_coalesce_regions(rgn, i, i + 1); ++ coalesced++; ++ } + } + + if (coalesced) + return coalesced; +- if (rgn->cnt >= MAX_LMB_REGIONS) ++ if (rgn->cnt >= rgn->max) + return -1; + + /* Couldn't coalesce the LMB, so add it to the sorted table. */ +@@ -198,9 +216,11 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + if (base < rgn->region[i].base) { + rgn->region[i + 1].base = rgn->region[i].base; + rgn->region[i + 1].size = rgn->region[i].size; ++ rgn->region[i + 1].flags = rgn->region[i].flags; + } else { + rgn->region[i + 1].base = base; + rgn->region[i + 1].size = size; ++ rgn->region[i + 1].flags = flags; + break; + } + } +@@ -208,6 +228,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + if (base < rgn->region[0].base) { + rgn->region[0].base = base; + rgn->region[0].size = size; ++ rgn->region[0].flags = flags; + } + + rgn->cnt++; +@@ -215,6 +236,12 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t + return 0; + } + ++static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, ++ phys_size_t size) ++{ ++ return lmb_add_region_flags(rgn, base, size, LMB_NONE); ++} ++ + /* This routine may be called with relocation disabled. */ + long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) + { +@@ -269,14 +296,21 @@ long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) + * beginging of the hole and add the region after hole. + */ + rgn->region[i].size = base - rgn->region[i].base; +- return lmb_add_region(rgn, end + 1, rgnend - end); ++ return lmb_add_region_flags(rgn, end + 1, rgnend - end, ++ rgn->region[i].flags); + } + +-long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) ++long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size, ++ enum lmb_flags flags) + { + struct lmb_region *_rgn = &(lmb->reserved); + +- return lmb_add_region(_rgn, base, size); ++ return lmb_add_region_flags(_rgn, base, size, flags); ++} ++ ++long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) ++{ ++ return lmb_reserve_flags(lmb, base, size, LMB_NONE); + } + + static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, +@@ -411,7 +445,7 @@ phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr) + return 0; + } + +-int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) ++int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags) + { + int i; + +@@ -419,11 +453,17 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) + phys_addr_t upper = lmb->reserved.region[i].base + + lmb->reserved.region[i].size - 1; + if ((addr >= lmb->reserved.region[i].base) && (addr <= upper)) +- return 1; ++ return !!((lmb->reserved.region[i].flags & flags) ++ == flags); + } + return 0; + } + ++int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) ++{ ++ return lmb_is_reserved_flags(lmb, addr, LMB_NONE); ++} ++ + __weak void board_lmb_reserve(struct lmb *lmb) + { + /* please define platform specific board_lmb_reserve() */ +diff --git a/lib/optee/optee.c b/lib/optee/optee.c +index 457d4cca8a..9e6606568f 100644 +--- a/lib/optee/optee.c ++++ b/lib/optee/optee.c +@@ -192,7 +192,7 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) + ret = fdtdec_add_reserved_memory(new_blob, + nodename, + &carveout, +- NULL); ++ NULL, true); + free(oldname); + + if (ret < 0) +diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index 093e432efc..bb6aef5ce4 100644 +--- a/scripts/config_whitelist.txt ++++ b/scripts/config_whitelist.txt +@@ -970,7 +970,6 @@ CONFIG_LG4573 + CONFIG_LINUX + CONFIG_LINUX_RESET_VEC + CONFIG_LITTLETON_LCD +-CONFIG_LMB + CONFIG_LMS283GF05 + CONFIG_LOADADDR + CONFIG_LOADCMD +diff --git a/test/dm/Makefile b/test/dm/Makefile +index 864c8d0b4c..70ba1b6695 100644 +--- a/test/dm/Makefile ++++ b/test/dm/Makefile +@@ -80,4 +80,5 @@ obj-$(CONFIG_DM_RNG) += rng.o + obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o + obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o + obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o ++obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o + endif +diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c +index 716993f706..017157a2ec 100644 +--- a/test/dm/fdtdec.c ++++ b/test/dm/fdtdec.c +@@ -80,7 +80,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) + resv.start = 0x1000; + resv.end = 0x1fff; + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", +- &resv, &phandle)); ++ &resv, &phandle, false)); + + /* Test /reserve-memory and its subnode should exist */ + parent = fdt_path_offset(blob, "/reserved-memory"); +@@ -101,10 +101,13 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) + resv.start = 0x2000; + resv.end = 0x2fff; + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", +- &resv, &phandle1)); ++ &resv, &phandle1, true)); + subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1"); + ut_assert(subnode > 0); + ++ /* check that no-map property is present */ ++ ut_assert(fdt_getprop(blob, subnode, "no-map", NULL) > 0); ++ + /* phandles must be different */ + ut_assert(phandle != phandle1); + +@@ -115,7 +118,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) + resv.start = 0x1000; + resv.end = 0x1fff; + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", +- &resv, &phandle1)); ++ &resv, &phandle1, false)); + subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2"); + ut_assert(subnode < 0); + +diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c +index 8bfb706602..9a34fdd7a2 100644 +--- a/test/dm/ofnode.c ++++ b/test/dm/ofnode.c +@@ -136,3 +136,15 @@ static int dm_test_ofnode_get_child_count(struct unit_test_state *uts) + } + DM_TEST(dm_test_ofnode_get_child_count, + UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); ++ ++static int dm_test_ofnode_is_enabled(struct unit_test_state *uts) ++{ ++ ofnode root_node = ofnode_path("/"); ++ ofnode node = ofnode_path("/usb@0"); ++ ++ ut_assert(ofnode_is_enabled(root_node)); ++ ut_assert(!ofnode_is_enabled(node)); ++ ++ return 0; ++} ++DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +diff --git a/test/dm/scmi.c b/test/dm/scmi.c +new file mode 100644 +index 0000000000..be60b44b3b +--- /dev/null ++++ b/test/dm/scmi.c +@@ -0,0 +1,203 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020, Linaro Limited ++ * ++ * Tests scmi_agent uclass and the SCMI drivers implemented in other ++ * uclass devices probe when a SCMI server exposes resources. ++ * ++ * Note in test.dts the protocol@10 node in agent 1. Protocol 0x10 is not ++ * implemented in U-Boot SCMI components but the implementation is exepected ++ * to not complain on unknown protocol IDs, as long as it is not used. Note ++ * in test.dts tests that SCMI drivers probing does not fail for such an ++ * unknown SCMI protocol ID. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ut_assert_scmi_state_preprobe(struct unit_test_state *uts) ++{ ++ struct sandbox_scmi_service *scmi_ctx = sandbox_scmi_service_ctx(); ++ ++ ut_assertnonnull(scmi_ctx); ++ if (scmi_ctx->agent_count) ++ ut_asserteq(2, scmi_ctx->agent_count); ++ ++ return 0; ++} ++ ++static int ut_assert_scmi_state_postprobe(struct unit_test_state *uts, ++ struct udevice *dev) ++{ ++ struct sandbox_scmi_devices *scmi_devices; ++ struct sandbox_scmi_service *scmi_ctx; ++ ++ /* Device references to check context against test sequence */ ++ scmi_devices = sandbox_scmi_devices_ctx(dev); ++ ++ ut_assertnonnull(scmi_devices); ++ if (IS_ENABLED(CONFIG_CLK_SCMI)) ++ ut_asserteq(3, scmi_devices->clk_count); ++ if (IS_ENABLED(CONFIG_RESET_SCMI)) ++ ut_asserteq(1, scmi_devices->reset_count); ++ ++ /* State of the simulated SCMI server exposed */ ++ scmi_ctx = sandbox_scmi_service_ctx(); ++ ++ ut_asserteq(2, scmi_ctx->agent_count); ++ ++ ut_assertnonnull(scmi_ctx->agent[0]); ++ ut_asserteq(2, scmi_ctx->agent[0]->clk_count); ++ ut_assertnonnull(scmi_ctx->agent[0]->clk); ++ ut_asserteq(1, scmi_ctx->agent[0]->reset_count); ++ ut_assertnonnull(scmi_ctx->agent[0]->reset); ++ ++ ut_assertnonnull(scmi_ctx->agent[1]); ++ ut_assertnonnull(scmi_ctx->agent[1]->clk); ++ ut_asserteq(1, scmi_ctx->agent[1]->clk_count); ++ ++ return 0; ++} ++ ++static int load_sandbox_scmi_test_devices(struct unit_test_state *uts, ++ struct udevice **dev) ++{ ++ int ret; ++ ++ ret = ut_assert_scmi_state_preprobe(uts); ++ if (ret) ++ return ret; ++ ++ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_scmi", ++ dev)); ++ ut_assertnonnull(*dev); ++ ++ return ut_assert_scmi_state_postprobe(uts, *dev); ++} ++ ++static int release_sandbox_scmi_test_devices(struct unit_test_state *uts, ++ struct udevice *dev) ++{ ++ ut_assertok(device_remove(dev, DM_REMOVE_NORMAL)); ++ ++ /* Not sure test devices are fully removed, agent may not be visible */ ++ return 0; ++} ++ ++/* ++ * Test SCMI states when loading and releasing resources ++ * related to SCMI drivers. ++ */ ++static int dm_test_scmi_sandbox_agent(struct unit_test_state *uts) ++{ ++ struct udevice *dev = NULL; ++ int ret; ++ ++ ret = load_sandbox_scmi_test_devices(uts, &dev); ++ if (!ret) ++ ret = release_sandbox_scmi_test_devices(uts, dev); ++ ++ return ret; ++} ++ ++DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT); ++ ++static int dm_test_scmi_clocks(struct unit_test_state *uts) ++{ ++ struct sandbox_scmi_devices *scmi_devices; ++ struct sandbox_scmi_service *scmi_ctx; ++ struct udevice *dev = NULL; ++ int ret_dev; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_CLK_SCMI)) ++ return 0; ++ ++ ret = load_sandbox_scmi_test_devices(uts, &dev); ++ if (ret) ++ return ret; ++ ++ scmi_devices = sandbox_scmi_devices_ctx(dev); ++ scmi_ctx = sandbox_scmi_service_ctx(); ++ ++ /* Test SCMI clocks rate manipulation */ ++ ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0])); ++ ut_asserteq(333, clk_get_rate(&scmi_devices->clk[1])); ++ ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2])); ++ ++ ret_dev = clk_set_rate(&scmi_devices->clk[1], 1088); ++ ut_assert(!ret_dev || ret_dev == 1088); ++ ++ ut_asserteq(1000, scmi_ctx->agent[0]->clk[0].rate); ++ ut_asserteq(1088, scmi_ctx->agent[0]->clk[1].rate); ++ ut_asserteq(44, scmi_ctx->agent[1]->clk[0].rate); ++ ++ ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0])); ++ ut_asserteq(1088, clk_get_rate(&scmi_devices->clk[1])); ++ ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2])); ++ ++ /* restore original rate for further tests */ ++ ret_dev = clk_set_rate(&scmi_devices->clk[1], 333); ++ ut_assert(!ret_dev || ret_dev == 333); ++ ++ /* Test SCMI clocks gating manipulation */ ++ ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); ++ ut_assert(!scmi_ctx->agent[0]->clk[1].enabled); ++ ut_assert(!scmi_ctx->agent[1]->clk[0].enabled); ++ ++ ut_asserteq(0, clk_enable(&scmi_devices->clk[1])); ++ ut_asserteq(0, clk_enable(&scmi_devices->clk[2])); ++ ++ ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); ++ ut_assert(scmi_ctx->agent[0]->clk[1].enabled); ++ ut_assert(scmi_ctx->agent[1]->clk[0].enabled); ++ ++ ut_assertok(clk_disable(&scmi_devices->clk[1])); ++ ut_assertok(clk_disable(&scmi_devices->clk[2])); ++ ++ ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); ++ ut_assert(!scmi_ctx->agent[0]->clk[1].enabled); ++ ut_assert(!scmi_ctx->agent[1]->clk[0].enabled); ++ ++ return release_sandbox_scmi_test_devices(uts, dev); ++} ++ ++DM_TEST(dm_test_scmi_clocks, UT_TESTF_SCAN_FDT); ++ ++static int dm_test_scmi_resets(struct unit_test_state *uts) ++{ ++ struct sandbox_scmi_devices *scmi_devices; ++ struct sandbox_scmi_service *scmi_ctx; ++ struct udevice *dev = NULL; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_RESET_SCMI)) ++ return 0; ++ ++ ret = load_sandbox_scmi_test_devices(uts, &dev); ++ if (ret) ++ return ret; ++ ++ scmi_devices = sandbox_scmi_devices_ctx(dev); ++ scmi_ctx = sandbox_scmi_service_ctx(); ++ ++ /* Test SCMI resect controller manipulation */ ++ ut_assert(!scmi_ctx->agent[0]->reset[0].asserted) ++ ++ ut_assertok(reset_assert(&scmi_devices->reset[0])); ++ ut_assert(scmi_ctx->agent[0]->reset[0].asserted) ++ ++ ut_assertok(reset_deassert(&scmi_devices->reset[0])); ++ ut_assert(!scmi_ctx->agent[0]->reset[0].asserted); ++ ++ return release_sandbox_scmi_test_devices(uts, dev); ++} ++ ++DM_TEST(dm_test_scmi_resets, UT_TESTF_SCAN_FDT); +diff --git a/test/lib/lmb.c b/test/lib/lmb.c +index 644ee78758..d7bd826190 100644 +--- a/test/lib/lmb.c ++++ b/test/lib/lmb.c +@@ -659,3 +659,92 @@ static int lib_test_lmb_get_free_size(struct unit_test_state *uts) + + DM_TEST(lib_test_lmb_get_free_size, + UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); ++ ++static int lib_test_lmb_flags(struct unit_test_state *uts) ++{ ++ const phys_addr_t ram = 0x40000000; ++ const phys_size_t ram_size = 0x20000000; ++ struct lmb lmb; ++ long ret; ++ ++ lmb_init(&lmb); ++ ++ ret = lmb_add(&lmb, ram, ram_size); ++ ut_asserteq(ret, 0); ++ ++ /* reserve, same flag */ ++ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 0); ++ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, ++ 0, 0, 0, 0); ++ ++ /* reserve again, same flag */ ++ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 0); ++ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, ++ 0, 0, 0, 0); ++ ++ /* reserve again, new flag */ ++ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NONE); ++ ut_asserteq(ret, -1); ++ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, ++ 0, 0, 0, 0); ++ ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); ++ ++ /* merge after */ ++ ret = lmb_reserve_flags(&lmb, 0x40020000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 1); ++ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x20000, ++ 0, 0, 0, 0); ++ ++ /* merge before */ ++ ret = lmb_reserve_flags(&lmb, 0x40000000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 1); ++ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x30000, ++ 0, 0, 0, 0); ++ ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); ++ ++ ret = lmb_reserve_flags(&lmb, 0x40030000, 0x10000, LMB_NONE); ++ ut_asserteq(ret, 0); ++ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, ++ 0x40030000, 0x10000, 0, 0); ++ ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); ++ ++ /* test that old API use LMB_NONE */ ++ ret = lmb_reserve(&lmb, 0x40040000, 0x10000); ++ ut_asserteq(ret, 1); ++ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, ++ 0x40030000, 0x20000, 0, 0); ++ ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); ++ ++ ret = lmb_reserve_flags(&lmb, 0x40070000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 0); ++ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, ++ 0x40030000, 0x20000, 0x40070000, 0x10000); ++ ++ ret = lmb_reserve_flags(&lmb, 0x40050000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 0); ++ ASSERT_LMB(&lmb, ram, ram_size, 4, 0x40000000, 0x30000, ++ 0x40030000, 0x20000, 0x40050000, 0x10000); ++ ++ /* merge with 2 adjacent regions */ ++ ret = lmb_reserve_flags(&lmb, 0x40060000, 0x10000, LMB_NOMAP); ++ ut_asserteq(ret, 2); ++ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, ++ 0x40030000, 0x20000, 0x40050000, 0x30000); ++ ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); ++ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1); ++ ++ return 0; ++} ++ ++DM_TEST(lib_test_lmb_flags, ++ UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.01-stm32mp-r1-DEVICETREE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.01-stm32mp-r1-DEVICETREE.patch deleted file mode 100644 index 07a0a5f..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.01-stm32mp-r1-DEVICETREE.patch +++ /dev/null @@ -1,14427 +0,0 @@ -From 362734e9999cbf5ffe6a8b2f81d29a51c011feff Mon Sep 17 00:00:00 2001 -From: Romuald JEANNE -Date: Fri, 5 Jun 2020 13:45:44 +0200 -Subject: [PATCH 4/5] ARM v2020.01-stm32mp-r1 DEVICETREE - ---- - arch/arm/dts/Makefile | 15 +- - arch/arm/dts/stm32mp15-ddr.dtsi | 7 +- - arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 49 +- - arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 49 +- - arch/arm/dts/stm32mp15-no-scmi.dtsi | 157 ++ - arch/arm/dts/stm32mp15-pinctrl.dtsi | 1426 +++++++++++++++ - arch/arm/dts/stm32mp15-u-boot.dtsi | 231 +++ - arch/arm/dts/stm32mp151.dtsi | 1997 ++++++++++++++++++++++ - arch/arm/dts/stm32mp153.dtsi | 54 + - arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi | 524 ++++++ - arch/arm/dts/stm32mp157-m4-srm.dtsi | 442 +++++ - arch/arm/dts/stm32mp157-pinctrl.dtsi | 1036 ----------- - arch/arm/dts/stm32mp157-u-boot.dtsi | 153 -- - arch/arm/dts/stm32mp157.dtsi | 32 + - arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 32 +- - arch/arm/dts/stm32mp157a-avenger96.dts | 20 +- - arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 56 +- - arch/arm/dts/stm32mp157a-dk1.dts | 488 +----- - arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 207 +++ - arch/arm/dts/stm32mp157a-ed1.dts | 52 + - arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi | 69 + - arch/arm/dts/stm32mp157a-ev1.dts | 86 + - arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 6 - - arch/arm/dts/stm32mp157c-dk2.dts | 122 +- - arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 202 +-- - arch/arm/dts/stm32mp157c-ed1.dts | 324 +--- - arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 49 +- - arch/arm/dts/stm32mp157c-ev1.dts | 300 +--- - arch/arm/dts/stm32mp157c.dtsi | 1592 ----------------- - arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157d-dk1.dts | 44 + - arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157d-ed1.dts | 52 + - arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157d-ev1.dts | 86 + - arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157f-dk2.dts | 185 ++ - arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157f-ed1.dts | 56 + - arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp157f-ev1.dts | 86 + - arch/arm/dts/stm32mp157xaa-pinctrl.dtsi | 90 - - arch/arm/dts/stm32mp157xab-pinctrl.dtsi | 62 - - arch/arm/dts/stm32mp157xac-pinctrl.dtsi | 78 - - arch/arm/dts/stm32mp157xad-pinctrl.dtsi | 62 - - arch/arm/dts/stm32mp15xa.dtsi | 13 + - arch/arm/dts/stm32mp15xc.dtsi | 20 + - arch/arm/dts/stm32mp15xd.dtsi | 42 + - arch/arm/dts/stm32mp15xf.dtsi | 20 + - arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi | 6 + - arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 88 + - arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 249 +++ - arch/arm/dts/stm32mp15xx-dhcom.dtsi | 379 ++++ - arch/arm/dts/stm32mp15xx-dkx.dtsi | 768 +++++++++ - arch/arm/dts/stm32mp15xx-edx.dtsi | 408 +++++ - arch/arm/dts/stm32mp15xx-evx.dtsi | 680 ++++++++ - arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi | 85 + - arch/arm/dts/stm32mp15xxab-pinctrl.dtsi | 57 + - arch/arm/dts/stm32mp15xxac-pinctrl.dtsi | 73 + - arch/arm/dts/stm32mp15xxad-pinctrl.dtsi | 57 + - 60 files changed, 9051 insertions(+), 4508 deletions(-) - create mode 100644 arch/arm/dts/stm32mp15-no-scmi.dtsi - create mode 100644 arch/arm/dts/stm32mp15-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp15-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp151.dtsi - create mode 100644 arch/arm/dts/stm32mp153.dtsi - create mode 100644 arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp157-m4-srm.dtsi - delete mode 100644 arch/arm/dts/stm32mp157-pinctrl.dtsi - delete mode 100644 arch/arm/dts/stm32mp157-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157.dtsi - create mode 100644 arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157a-ed1.dts - create mode 100644 arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157a-ev1.dts - delete mode 100644 arch/arm/dts/stm32mp157c.dtsi - create mode 100644 arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157d-dk1.dts - create mode 100644 arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157d-ed1.dts - create mode 100644 arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157d-ev1.dts - create mode 100644 arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157f-dk2.dts - create mode 100644 arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157f-ed1.dts - create mode 100644 arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp157f-ev1.dts - delete mode 100644 arch/arm/dts/stm32mp157xaa-pinctrl.dtsi - delete mode 100644 arch/arm/dts/stm32mp157xab-pinctrl.dtsi - delete mode 100644 arch/arm/dts/stm32mp157xac-pinctrl.dtsi - delete mode 100644 arch/arm/dts/stm32mp157xad-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp15xa.dtsi - create mode 100644 arch/arm/dts/stm32mp15xc.dtsi - create mode 100644 arch/arm/dts/stm32mp15xd.dtsi - create mode 100644 arch/arm/dts/stm32mp15xf.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts - create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-dhcom.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-dkx.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-edx.dtsi - create mode 100644 arch/arm/dts/stm32mp15xx-evx.dtsi - create mode 100644 arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp15xxab-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp15xxac-pinctrl.dtsi - create mode 100644 arch/arm/dts/stm32mp15xxad-pinctrl.dtsi - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 0127a91..c3fd89b 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -823,12 +823,21 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb - - dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb - --dtb-$(CONFIG_TARGET_STM32MP1) += \ -- stm32mp157a-dk1.dtb \ -+dtb-$(CONFIG_STM32MP15x) += \ - stm32mp157a-avenger96.dtb \ -+ stm32mp157a-dk1.dtb \ -+ stm32mp157a-ed1.dtb \ -+ stm32mp157a-ev1.dtb \ - stm32mp157c-dk2.dtb \ - stm32mp157c-ed1.dtb \ -- stm32mp157c-ev1.dtb -+ stm32mp157c-ev1.dtb \ -+ stm32mp157d-dk1.dtb \ -+ stm32mp157d-ed1.dtb \ -+ stm32mp157d-ev1.dtb \ -+ stm32mp157f-dk2.dtb \ -+ stm32mp157f-ed1.dtb \ -+ stm32mp157f-ev1.dtb \ -+ stm32mp15xx-dhcom-pdk2.dtb - - dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb - dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ -diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi -index 479b700..cc604c0 100644 ---- a/arch/arm/dts/stm32mp15-ddr.dtsi -+++ b/arch/arm/dts/stm32mp15-ddr.dtsi -@@ -5,7 +5,7 @@ - - / { - soc { -- ddr: ddr@5A003000 { -+ ddr: ddr@5a003000 { - u-boot,dm-pre-reloc; - - compatible = "st,stm32mp1-ddr"; -@@ -31,6 +31,7 @@ - st,mem-speed = ; - st,mem-size = ; - -+#ifndef CONFIG_STM32MP1_TRUSTED - st,ctl-reg = < - DDR_MSTR - DDR_MRCTRL0 -@@ -133,6 +134,7 @@ - DDR_MR3 - >; - -+#ifdef DDR_PHY_CAL_SKIP - st,phy-cal = < - DDR_DX0DLLCR - DDR_DX0DQTR -@@ -147,6 +149,9 @@ - DDR_DX3DQTR - DDR_DX3DQSTR - >; -+#endif -+ -+#endif - - status = "okay"; - }; -diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi -index 11e8f2b..c0fc1f7 100644 ---- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi -+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi -@@ -1,24 +1,23 @@ - // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause - /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved -+ */ -+ -+/* -+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs -+ * DDR type: DDR3 / DDR3L -+ * DDR width: 16bits -+ * DDR density: 4Gb -+ * System frequency: 533000Khz -+ * Relaxed Timing Mode: false -+ * Address mapping type: RBC - * -- * STM32MP157C DK1/DK2 BOARD configuration -- * 1x DDR3L 4Gb, 16-bit, 533MHz. -- * Reference used NT5CC256M16DP-DI from NANYA -- * -- * DDR type / Platform DDR3/3L -- * freq 533MHz -- * width 16 -- * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G -- * DDR density 4 -- * timing mode optimized -- * Scheduling/QoS options : type = 2 -- * address mapping : RBC -- * Tc > + 85C : N -+ * Save Date: 2020.02.20, save Time: 18:45:20 - */ --#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" --#define DDR_MEM_SPEED 533000 --#define DDR_MEM_SIZE 0x20000000 -+ -+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" -+#define DDR_MEM_SPEED 533000 -+#define DDR_MEM_SIZE 0x20000000 - - #define DDR_MSTR 0x00041401 - #define DDR_MRCTRL0 0x00000010 -@@ -50,15 +49,6 @@ - #define DDR_DFIUPD1 0x00000000 - #define DDR_DFIUPD2 0x00000000 - #define DDR_DFIPHYMSTR 0x00000000 --#define DDR_ADDRMAP1 0x00070707 --#define DDR_ADDRMAP2 0x00000000 --#define DDR_ADDRMAP3 0x1F000000 --#define DDR_ADDRMAP4 0x00001F1F --#define DDR_ADDRMAP5 0x06060606 --#define DDR_ADDRMAP6 0x0F060606 --#define DDR_ADDRMAP9 0x00000000 --#define DDR_ADDRMAP10 0x00000000 --#define DDR_ADDRMAP11 0x00000000 - #define DDR_ODTCFG 0x06000600 - #define DDR_ODTMAP 0x00000001 - #define DDR_SCHED 0x00000C01 -@@ -83,6 +73,15 @@ - #define DDR_PCFGQOS1_1 0x00800040 - #define DDR_PCFGWQOS0_1 0x01100C03 - #define DDR_PCFGWQOS1_1 0x01000200 -+#define DDR_ADDRMAP1 0x00070707 -+#define DDR_ADDRMAP2 0x00000000 -+#define DDR_ADDRMAP3 0x1F000000 -+#define DDR_ADDRMAP4 0x00001F1F -+#define DDR_ADDRMAP5 0x06060606 -+#define DDR_ADDRMAP6 0x0F060606 -+#define DDR_ADDRMAP9 0x00000000 -+#define DDR_ADDRMAP10 0x00000000 -+#define DDR_ADDRMAP11 0x00000000 - #define DDR_PGCR 0x01442E02 - #define DDR_PTR0 0x0022AA5B - #define DDR_PTR1 0x04841104 -diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi -index 4b70b60..fc226d2 100644 ---- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi -+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi -@@ -1,24 +1,23 @@ - // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause - /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved -+ */ -+ -+/* -+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs -+ * DDR type: DDR3 / DDR3L -+ * DDR width: 32bits -+ * DDR density: 8Gb -+ * System frequency: 533000Khz -+ * Relaxed Timing Mode: false -+ * Address mapping type: RBC - * -- * STM32MP157C ED1 BOARD configuration -- * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. -- * Reference used NT5CC256M16DP-DI from NANYA -- * -- * DDR type / Platform DDR3/3L -- * freq 533MHz -- * width 32 -- * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G -- * DDR density 8 -- * timing mode optimized -- * Scheduling/QoS options : type = 2 -- * address mapping : RBC -- * Tc > + 85C : N -+ * Save Date: 2020.02.20, save Time: 18:49:33 - */ --#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45" --#define DDR_MEM_SPEED 533000 --#define DDR_MEM_SIZE 0x40000000 -+ -+#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" -+#define DDR_MEM_SPEED 533000 -+#define DDR_MEM_SIZE 0x40000000 - - #define DDR_MSTR 0x00040401 - #define DDR_MRCTRL0 0x00000010 -@@ -50,15 +49,6 @@ - #define DDR_DFIUPD1 0x00000000 - #define DDR_DFIUPD2 0x00000000 - #define DDR_DFIPHYMSTR 0x00000000 --#define DDR_ADDRMAP1 0x00080808 --#define DDR_ADDRMAP2 0x00000000 --#define DDR_ADDRMAP3 0x00000000 --#define DDR_ADDRMAP4 0x00001F1F --#define DDR_ADDRMAP5 0x07070707 --#define DDR_ADDRMAP6 0x0F070707 --#define DDR_ADDRMAP9 0x00000000 --#define DDR_ADDRMAP10 0x00000000 --#define DDR_ADDRMAP11 0x00000000 - #define DDR_ODTCFG 0x06000600 - #define DDR_ODTMAP 0x00000001 - #define DDR_SCHED 0x00000C01 -@@ -83,6 +73,15 @@ - #define DDR_PCFGQOS1_1 0x00800040 - #define DDR_PCFGWQOS0_1 0x01100C03 - #define DDR_PCFGWQOS1_1 0x01000200 -+#define DDR_ADDRMAP1 0x00080808 -+#define DDR_ADDRMAP2 0x00000000 -+#define DDR_ADDRMAP3 0x00000000 -+#define DDR_ADDRMAP4 0x00001F1F -+#define DDR_ADDRMAP5 0x07070707 -+#define DDR_ADDRMAP6 0x0F070707 -+#define DDR_ADDRMAP9 0x00000000 -+#define DDR_ADDRMAP10 0x00000000 -+#define DDR_ADDRMAP11 0x00000000 - #define DDR_PGCR 0x01442E02 - #define DDR_PTR0 0x0022AA5B - #define DDR_PTR1 0x04841104 -diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi -new file mode 100644 -index 0000000..3bb96ab ---- /dev/null -+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi -@@ -0,0 +1,157 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved -+ * Author: Gabriel Fernandez for STMicroelectronics. -+ */ -+ -+/ { -+ -+ clocks { -+ clk_hse: clk-hse { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ }; -+ -+ clk_hsi: clk-hsi { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <64000000>; -+ }; -+ -+ clk_lse: clk-lse { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ }; -+ -+ clk_lsi: clk-lsi { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+ }; -+ -+ clk_csi: clk-csi { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <4000000>; -+ }; -+ }; -+ -+ cpus { -+ cpu0: cpu@0 { -+ clocks = <&rcc CK_MPU>; -+ }; -+ -+ cpu1: cpu@1 { -+ clocks = <&rcc CK_MPU>; -+ }; -+ }; -+ -+ soc { -+ m_can1: can@4400e000 { -+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -+ }; -+ -+ m_can2: can@4400f000 { -+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -+ }; -+ -+ cryp1: cryp@54001000 { -+ clocks = <&rcc CRYP1>; -+ resets = <&rcc CRYP1_R>; -+ }; -+ }; -+ -+ mlahb { -+ m4_rproc: m4@10000000 { -+ resets = <&rcc MCU_R>; -+ -+ m4_system_resources { -+ m4_cec: cec@40016000 { -+ clocks = <&rcc CEC_K>, <&rcc CK_LSE>; -+ }; -+ -+ m4_m_can1: can@4400e000 { -+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -+ }; -+ -+ m4_m_can2: can@4400f000 { -+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -+ }; -+ }; -+ }; -+ }; -+ -+ firmware { -+ /delete-node/ scmi-0; -+ /delete-node/ scmi-1; -+ }; -+ /delete-node/ sram@2ffff000; -+ /delete-node/ mailbox-0; -+ /delete-node/ mailbox-1; -+}; -+ -+&cec { -+ clocks = <&rcc CEC_K>, <&clk_lse>; -+}; -+ -+&ddrperfm { -+ clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>; -+}; -+ -+&dsi { -+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; -+}; -+ -+&gpioz { -+ clocks = <&rcc GPIOZ>; -+}; -+ -+&hash1 { -+ clocks = <&rcc HASH1>; -+ resets = <&rcc HASH1_R>; -+}; -+ -+&i2c4 { -+ clocks = <&rcc I2C4_K>; -+ resets = <&rcc I2C4_R>; -+}; -+ -+&i2c6 { -+ clocks = <&rcc I2C6_K>; -+ resets = <&rcc I2C6_R>; -+}; -+ -+&iwdg2 { -+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>; -+}; -+ -+&mdma1 { -+ clocks = <&rcc MDMA>; -+ resets = <&rcc MDMA_R>; -+}; -+ -+&rcc { -+ compatible = "st,stm32mp1-rcc", "syscon"; -+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; -+}; -+ -+&rng1 { -+ clocks = <&rcc RNG1_K>; -+ resets = <&rcc RNG1_R>; -+}; -+ -+&rtc { -+ clocks = <&rcc RTCAPB>, <&rcc RTC>; -+}; -+ -+&spi6 { -+ clocks = <&rcc SPI6_K>; -+ resets = <&rcc SPI6_R>; -+}; -+ -+&usart1 { -+ clocks = <&rcc USART1_K>; -+ resets = <&rcc USART1_R>; -+}; -diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi -new file mode 100644 -index 0000000..b8e82ad ---- /dev/null -+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi -@@ -0,0 +1,1426 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -+ * Author: Ludovic Barre for STMicroelectronics. -+ */ -+#include -+ -+&pinctrl { -+ adc1_in6_pins_a: adc1-in6 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ adc12_ain_pins_a: adc12-ain-0 { -+ pins { -+ pinmux = , /* ADC1 in13 */ -+ , /* ADC1 in6 */ -+ , /* ADC2 in2 */ -+ ; /* ADC2 in6 */ -+ }; -+ }; -+ -+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { -+ pins { -+ pinmux = , /* ADC12 in18 */ -+ ; /* ADC12 in19 */ -+ }; -+ }; -+ -+ cec_pins_a: cec-0 { -+ pins { -+ pinmux = ; -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ cec_pins_sleep_a: cec-sleep-0 { -+ pins { -+ pinmux = ; /* HDMI_CEC */ -+ }; -+ }; -+ -+ cec_pins_b: cec-1 { -+ pins { -+ pinmux = ; -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ cec_pins_sleep_b: cec-sleep-1 { -+ pins { -+ pinmux = ; /* HDMI_CEC */ -+ }; -+ }; -+ -+ dac_ch1_pins_a: dac-ch1 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ dac_ch2_pins_a: dac-ch2 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ dcmi_pins_a: dcmi-0 { -+ pins { -+ pinmux = ,/* DCMI_HSYNC */ -+ ,/* DCMI_VSYNC */ -+ ,/* DCMI_PIXCLK */ -+ ,/* DCMI_D0 */ -+ ,/* DCMI_D1 */ -+ ,/* DCMI_D2 */ -+ ,/* DCMI_D3 */ -+ ,/* DCMI_D4 */ -+ ,/* DCMI_D5 */ -+ ,/* DCMI_D6 */ -+ ,/* DCMI_D7 */ -+ ,/* DCMI_D8 */ -+ ,/* DCMI_D9 */ -+ ,/* DCMI_D10 */ -+ ;/* DCMI_D11 */ -+ bias-disable; -+ }; -+ }; -+ -+ dcmi_sleep_pins_a: dcmi-sleep-0 { -+ pins { -+ pinmux = ,/* DCMI_HSYNC */ -+ ,/* DCMI_VSYNC */ -+ ,/* DCMI_PIXCLK */ -+ ,/* DCMI_D0 */ -+ ,/* DCMI_D1 */ -+ ,/* DCMI_D2 */ -+ ,/* DCMI_D3 */ -+ ,/* DCMI_D4 */ -+ ,/* DCMI_D5 */ -+ ,/* DCMI_D6 */ -+ ,/* DCMI_D7 */ -+ ,/* DCMI_D8 */ -+ ,/* DCMI_D9 */ -+ ,/* DCMI_D10 */ -+ ;/* DCMI_D11 */ -+ }; -+ }; -+ -+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_CKOUT */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_CKOUT */ -+ }; -+ }; -+ -+ dfsdm_data1_pins_a: dfsdm-data1-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA1 */ -+ }; -+ }; -+ -+ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA1 */ -+ }; -+ }; -+ -+ dfsdm_data3_pins_a: dfsdm-data3-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA3 */ -+ }; -+ }; -+ -+ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA3 */ -+ }; -+ }; -+ -+ ethernet0_rgmii_pins_a: rgmii-0 { -+ pins1 { -+ pinmux = , /* ETH_RGMII_CLK125 */ -+ , /* ETH_RGMII_GTX_CLK */ -+ , /* ETH_RGMII_TXD0 */ -+ , /* ETH_RGMII_TXD1 */ -+ , /* ETH_RGMII_TXD2 */ -+ , /* ETH_RGMII_TXD3 */ -+ , /* ETH_RGMII_TX_CTL */ -+ ; /* ETH_MDC */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <2>; -+ }; -+ pins2 { -+ pinmux = ; /* ETH_MDIO */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins3 { -+ pinmux = , /* ETH_RGMII_RXD0 */ -+ , /* ETH_RGMII_RXD1 */ -+ , /* ETH_RGMII_RXD2 */ -+ , /* ETH_RGMII_RXD3 */ -+ , /* ETH_RGMII_RX_CLK */ -+ ; /* ETH_RGMII_RX_CTL */ -+ bias-disable; -+ }; -+ }; -+ -+ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { -+ pins1 { -+ pinmux = , /* ETH_RGMII_CLK125 */ -+ , /* ETH_RGMII_GTX_CLK */ -+ , /* ETH_RGMII_TXD0 */ -+ , /* ETH_RGMII_TXD1 */ -+ , /* ETH_RGMII_TXD2 */ -+ , /* ETH_RGMII_TXD3 */ -+ , /* ETH_RGMII_TX_CTL */ -+ , /* ETH_MDIO */ -+ , /* ETH_MDC */ -+ , /* ETH_RGMII_RXD0 */ -+ , /* ETH_RGMII_RXD1 */ -+ , /* ETH_RGMII_RXD2 */ -+ , /* ETH_RGMII_RXD3 */ -+ , /* ETH_RGMII_RX_CLK */ -+ ; /* ETH_RGMII_RX_CTL */ -+ }; -+ }; -+ -+ fmc_pins_a: fmc-0 { -+ pins1 { -+ pinmux = , /* FMC_NOE */ -+ , /* FMC_NWE */ -+ , /* FMC_A16_FMC_CLE */ -+ , /* FMC_A17_FMC_ALE */ -+ , /* FMC_D0 */ -+ , /* FMC_D1 */ -+ , /* FMC_D2 */ -+ , /* FMC_D3 */ -+ , /* FMC_D4 */ -+ , /* FMC_D5 */ -+ , /* FMC_D6 */ -+ , /* FMC_D7 */ -+ ; /* FMC_NE2_FMC_NCE */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ pins2 { -+ pinmux = ; /* FMC_NWAIT */ -+ bias-pull-up; -+ }; -+ }; -+ -+ fmc_sleep_pins_a: fmc-sleep-0 { -+ pins { -+ pinmux = , /* FMC_NOE */ -+ , /* FMC_NWE */ -+ , /* FMC_A16_FMC_CLE */ -+ , /* FMC_A17_FMC_ALE */ -+ , /* FMC_D0 */ -+ , /* FMC_D1 */ -+ , /* FMC_D2 */ -+ , /* FMC_D3 */ -+ , /* FMC_D4 */ -+ , /* FMC_D5 */ -+ , /* FMC_D6 */ -+ , /* FMC_D7 */ -+ , /* FMC_NWAIT */ -+ ; /* FMC_NE2_FMC_NCE */ -+ }; -+ }; -+ -+ hdp0_pins_a: hdp0-0 { -+ pins { -+ pinmux = ; /* HDP0 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <2>; -+ }; -+ }; -+ -+ hdp0_pins_sleep_a: hdp0-sleep-0 { -+ pins { -+ pinmux = ; /* HDP0 */ -+ }; -+ }; -+ -+ hdp6_pins_a: hdp6-0 { -+ pins { -+ pinmux = ; /* HDP6 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <2>; -+ }; -+ }; -+ -+ hdp6_pins_sleep_a: hdp6-sleep-0 { -+ pins { -+ pinmux = ; /* HDP6 */ -+ }; -+ }; -+ -+ hdp7_pins_a: hdp7-0 { -+ pins { -+ pinmux = ; /* HDP7 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <2>; -+ }; -+ }; -+ -+ hdp7_pins_sleep_a: hdp7-sleep-0 { -+ pins { -+ pinmux = ; /* HDP7 */ -+ }; -+ }; -+ -+ i2c1_pins_a: i2c1-0 { -+ pins { -+ pinmux = , /* I2C1_SCL */ -+ ; /* I2C1_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c1_pins_sleep_a: i2c1-1 { -+ pins { -+ pinmux = , /* I2C1_SCL */ -+ ; /* I2C1_SDA */ -+ }; -+ }; -+ -+ i2c1_pins_b: i2c1-2 { -+ pins { -+ pinmux = , /* I2C1_SCL */ -+ ; /* I2C1_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c1_pins_sleep_b: i2c1-3 { -+ pins { -+ pinmux = , /* I2C1_SCL */ -+ ; /* I2C1_SDA */ -+ }; -+ }; -+ -+ i2c2_pins_a: i2c2-0 { -+ pins { -+ pinmux = , /* I2C2_SCL */ -+ ; /* I2C2_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c2_pins_sleep_a: i2c2-1 { -+ pins { -+ pinmux = , /* I2C2_SCL */ -+ ; /* I2C2_SDA */ -+ }; -+ }; -+ -+ i2c2_pins_b1: i2c2-2 { -+ pins { -+ pinmux = ; /* I2C2_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c2_pins_sleep_b1: i2c2-3 { -+ pins { -+ pinmux = ; /* I2C2_SDA */ -+ }; -+ }; -+ -+ i2c5_pins_a: i2c5-0 { -+ pins { -+ pinmux = , /* I2C5_SCL */ -+ ; /* I2C5_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c5_pins_sleep_a: i2c5-1 { -+ pins { -+ pinmux = , /* I2C5_SCL */ -+ ; /* I2C5_SDA */ -+ -+ }; -+ }; -+ -+ i2s2_pins_a: i2s2-0 { -+ pins { -+ pinmux = , /* I2S2_SDO */ -+ , /* I2S2_WS */ -+ ; /* I2S2_CK */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ }; -+ -+ i2s2_pins_sleep_a: i2s2-1 { -+ pins { -+ pinmux = , /* I2S2_SDO */ -+ , /* I2S2_WS */ -+ ; /* I2S2_CK */ -+ }; -+ }; -+ -+ ltdc_pins_a: ltdc-a-0 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ }; -+ -+ ltdc_pins_sleep_a: ltdc-a-1 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ }; -+ }; -+ -+ ltdc_pins_b: ltdc-b-0 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ }; -+ -+ ltdc_pins_sleep_b: ltdc-b-1 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ }; -+ }; -+ -+ m_can1_pins_a: m-can1-0 { -+ pins1 { -+ pinmux = ; /* CAN1_TX */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* CAN1_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ m_can1_sleep_pins_a: m_can1-sleep-0 { -+ pins { -+ pinmux = , /* CAN1_TX */ -+ ; /* CAN1_RX */ -+ }; -+ }; -+ -+ pwm1_pins_a: pwm1-0 { -+ pins { -+ pinmux = , /* TIM1_CH1 */ -+ , /* TIM1_CH2 */ -+ ; /* TIM1_CH4 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm1_sleep_pins_a: pwm1-sleep-0 { -+ pins { -+ pinmux = , /* TIM1_CH1 */ -+ , /* TIM1_CH2 */ -+ ; /* TIM1_CH4 */ -+ }; -+ }; -+ -+ pwm2_pins_a: pwm2-0 { -+ pins { -+ pinmux = ; /* TIM2_CH4 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm2_sleep_pins_a: pwm2-sleep-0 { -+ pins { -+ pinmux = ; /* TIM2_CH4 */ -+ }; -+ }; -+ -+ pwm3_pins_a: pwm3-0 { -+ pins { -+ pinmux = ; /* TIM3_CH2 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm3_sleep_pins_a: pwm3-sleep-0 { -+ pins { -+ pinmux = ; /* TIM3_CH2 */ -+ }; -+ }; -+ -+ pwm4_pins_a: pwm4-0 { -+ pins { -+ pinmux = , /* TIM4_CH3 */ -+ ; /* TIM4_CH4 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm4_sleep_pins_a: pwm4-sleep-0 { -+ pins { -+ pinmux = , /* TIM4_CH3 */ -+ ; /* TIM4_CH4 */ -+ }; -+ }; -+ -+ pwm4_pins_b: pwm4-1 { -+ pins { -+ pinmux = ; /* TIM4_CH2 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm4_sleep_pins_b: pwm4-sleep-1 { -+ pins { -+ pinmux = ; /* TIM4_CH2 */ -+ }; -+ }; -+ -+ pwm5_pins_a: pwm5-0 { -+ pins { -+ pinmux = ; /* TIM5_CH2 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm5_sleep_pins_a: pwm5-sleep-0 { -+ pins { -+ pinmux = ; /* TIM5_CH2 */ -+ }; -+ }; -+ -+ pwm8_pins_a: pwm8-0 { -+ pins { -+ pinmux = ; /* TIM8_CH4 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm8_sleep_pins_a: pwm8-sleep-0 { -+ pins { -+ pinmux = ; /* TIM8_CH4 */ -+ }; -+ }; -+ -+ pwm12_pins_a: pwm12-0 { -+ pins { -+ pinmux = ; /* TIM12_CH1 */ -+ bias-pull-down; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ pwm12_sleep_pins_a: pwm12-sleep-0 { -+ pins { -+ pinmux = ; /* TIM12_CH1 */ -+ }; -+ }; -+ -+ qspi_clk_pins_a: qspi-clk-0 { -+ pins { -+ pinmux = ; /* QSPI_CLK */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <3>; -+ }; -+ }; -+ -+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { -+ pins { -+ pinmux = ; /* QSPI_CLK */ -+ }; -+ }; -+ -+ qspi_bk1_pins_a: qspi-bk1-0 { -+ pins1 { -+ pinmux = , /* QSPI_BK1_IO0 */ -+ , /* QSPI_BK1_IO1 */ -+ , /* QSPI_BK1_IO2 */ -+ ; /* QSPI_BK1_IO3 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ pins2 { -+ pinmux = ; /* QSPI_BK1_NCS */ -+ bias-pull-up; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ }; -+ -+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { -+ pins { -+ pinmux = , /* QSPI_BK1_IO0 */ -+ , /* QSPI_BK1_IO1 */ -+ , /* QSPI_BK1_IO2 */ -+ , /* QSPI_BK1_IO3 */ -+ ; /* QSPI_BK1_NCS */ -+ }; -+ }; -+ -+ qspi_bk2_pins_a: qspi-bk2-0 { -+ pins1 { -+ pinmux = , /* QSPI_BK2_IO0 */ -+ , /* QSPI_BK2_IO1 */ -+ , /* QSPI_BK2_IO2 */ -+ ; /* QSPI_BK2_IO3 */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ pins2 { -+ pinmux = ; /* QSPI_BK2_NCS */ -+ bias-pull-up; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ }; -+ -+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { -+ pins { -+ pinmux = , /* QSPI_BK2_IO0 */ -+ , /* QSPI_BK2_IO1 */ -+ , /* QSPI_BK2_IO2 */ -+ , /* QSPI_BK2_IO3 */ -+ ; /* QSPI_BK2_NCS */ -+ }; -+ }; -+ -+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { -+ pins { -+ pinmux = ; /* RTC_OUT2_RMP */ -+ }; -+ }; -+ -+ sai2a_pins_a: sai2a-0 { -+ pins { -+ pinmux = , /* SAI2_SCK_A */ -+ , /* SAI2_SD_A */ -+ , /* SAI2_FS_A */ -+ ; /* SAI2_MCLK_A */ -+ slew-rate = <0>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ }; -+ -+ sai2a_sleep_pins_a: sai2a-1 { -+ pins { -+ pinmux = , /* SAI2_SCK_A */ -+ , /* SAI2_SD_A */ -+ , /* SAI2_FS_A */ -+ ; /* SAI2_MCLK_A */ -+ }; -+ }; -+ -+ sai2b_pins_a: sai2b-0 { -+ pins1 { -+ pinmux = , /* SAI2_SCK_B */ -+ , /* SAI2_FS_B */ -+ ; /* SAI2_MCLK_B */ -+ slew-rate = <0>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* SAI2_SD_B */ -+ bias-disable; -+ }; -+ }; -+ -+ sai2b_sleep_pins_a: sai2b-1 { -+ pins { -+ pinmux = , /* SAI2_SD_B */ -+ , /* SAI2_SCK_B */ -+ , /* SAI2_FS_B */ -+ ; /* SAI2_MCLK_B */ -+ }; -+ }; -+ -+ sai2b_pins_b: sai2b-2 { -+ pins { -+ pinmux = ; /* SAI2_SD_B */ -+ bias-disable; -+ }; -+ }; -+ -+ sai2b_sleep_pins_b: sai2b-3 { -+ pins { -+ pinmux = ; /* SAI2_SD_B */ -+ }; -+ }; -+ -+ sai4a_pins_a: sai4a-0 { -+ pins { -+ pinmux = ; /* SAI4_SD_A */ -+ slew-rate = <0>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ }; -+ -+ sai4a_sleep_pins_a: sai4a-1 { -+ pins { -+ pinmux = ; /* SAI4_SD_A */ -+ }; -+ }; -+ -+ sdmmc1_b4_pins_a: sdmmc1-b4-0 { -+ pins1 { -+ pinmux = , /* SDMMC1_D0 */ -+ , /* SDMMC1_D1 */ -+ , /* SDMMC1_D2 */ -+ , /* SDMMC1_D3 */ -+ ; /* SDMMC1_CMD */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC1_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ }; -+ -+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { -+ pins1 { -+ pinmux = , /* SDMMC1_D0 */ -+ , /* SDMMC1_D1 */ -+ , /* SDMMC1_D2 */ -+ ; /* SDMMC1_D3 */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC1_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins3 { -+ pinmux = ; /* SDMMC1_CMD */ -+ slew-rate = <1>; -+ drive-open-drain; -+ bias-disable; -+ }; -+ }; -+ -+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { -+ pins { -+ pinmux = , /* SDMMC1_D0 */ -+ , /* SDMMC1_D1 */ -+ , /* SDMMC1_D2 */ -+ , /* SDMMC1_D3 */ -+ , /* SDMMC1_CK */ -+ ; /* SDMMC1_CMD */ -+ }; -+ }; -+ -+ sdmmc1_dir_pins_a: sdmmc1-dir-0 { -+ pins1 { -+ pinmux = , /* SDMMC1_D0DIR */ -+ , /* SDMMC1_D123DIR */ -+ ; /* SDMMC1_CDIR */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins2{ -+ pinmux = ; /* SDMMC1_CKIN */ -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { -+ pins { -+ pinmux = , /* SDMMC1_D0DIR */ -+ , /* SDMMC1_D123DIR */ -+ , /* SDMMC1_CDIR */ -+ ; /* SDMMC1_CKIN */ -+ }; -+ }; -+ -+ sdmmc2_b4_pins_a: sdmmc2-b4-0 { -+ pins1 { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ , /* SDMMC2_D3 */ -+ ; /* SDMMC2_CMD */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC2_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { -+ pins1 { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ ; /* SDMMC2_D3 */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC2_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins3 { -+ pinmux = ; /* SDMMC2_CMD */ -+ slew-rate = <1>; -+ drive-open-drain; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { -+ pins { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ , /* SDMMC2_D3 */ -+ , /* SDMMC2_CK */ -+ ; /* SDMMC2_CMD */ -+ }; -+ }; -+ -+ sdmmc2_b4_pins_b: sdmmc2-b4-1 { -+ pins1 { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ , /* SDMMC2_D3 */ -+ ; /* SDMMC2_CMD */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC2_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ }; -+ -+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { -+ pins1 { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ ; /* SDMMC2_D3 */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC2_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-disable; -+ }; -+ pins3 { -+ pinmux = ; /* SDMMC2_CMD */ -+ slew-rate = <1>; -+ drive-open-drain; -+ bias-disable; -+ }; -+ }; -+ -+ sdmmc2_d47_pins_a: sdmmc2-d47-0 { -+ pins { -+ pinmux = , /* SDMMC2_D4 */ -+ , /* SDMMC2_D5 */ -+ , /* SDMMC2_D6 */ -+ ; /* SDMMC2_D7 */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { -+ pins { -+ pinmux = , /* SDMMC2_D4 */ -+ , /* SDMMC2_D5 */ -+ , /* SDMMC2_D6 */ -+ ; /* SDMMC2_D7 */ -+ }; -+ }; -+ -+ sdmmc3_b4_pins_a: sdmmc3-b4-0 { -+ pins1 { -+ pinmux = , /* SDMMC3_D0 */ -+ , /* SDMMC3_D1 */ -+ , /* SDMMC3_D2 */ -+ , /* SDMMC3_D3 */ -+ ; /* SDMMC3_CMD */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC3_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { -+ pins1 { -+ pinmux = , /* SDMMC3_D0 */ -+ , /* SDMMC3_D1 */ -+ , /* SDMMC3_D2 */ -+ ; /* SDMMC3_D3 */ -+ slew-rate = <1>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins2 { -+ pinmux = ; /* SDMMC3_CK */ -+ slew-rate = <2>; -+ drive-push-pull; -+ bias-pull-up; -+ }; -+ pins3 { -+ pinmux = ; /* SDMMC2_CMD */ -+ slew-rate = <1>; -+ drive-open-drain; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { -+ pins { -+ pinmux = , /* SDMMC3_D0 */ -+ , /* SDMMC3_D1 */ -+ , /* SDMMC3_D2 */ -+ , /* SDMMC3_D3 */ -+ , /* SDMMC3_CK */ -+ ; /* SDMMC3_CMD */ -+ }; -+ }; -+ -+ spdifrx_pins_a: spdifrx-0 { -+ pins { -+ pinmux = ; /* SPDIF_IN1 */ -+ bias-disable; -+ }; -+ }; -+ -+ spdifrx_sleep_pins_a: spdifrx-1 { -+ pins { -+ pinmux = ; /* SPDIF_IN1 */ -+ }; -+ }; -+ -+ spi2_pins_a: spi2-0 { -+ pins1 { -+ pinmux = , /* SPI2_SCK */ -+ , /* SPI2_NSS */ -+ ; /* SPI2_MOSI */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <3>; -+ }; -+ pins2 { -+ pinmux = ; /* SPI2_MISO */ -+ bias-disable; -+ }; -+ }; -+ -+ spi4_pins_a: spi4-0 { -+ pins1 { -+ pinmux = , /* SPI4_SCK */ -+ ; /* SPI4_MOSI */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ -+ pins2 { -+ pinmux = ; /* SPI4_MISO */ -+ bias-disable; -+ }; -+ }; -+ -+ spi4_sleep_pins_a: spi4-sleep-0 { -+ pins { -+ pinmux = , /* SPI4_SCK */ -+ , /* SPI4_MISO */ -+ ; /* SPI4_MOSI */ -+ }; -+ }; -+ -+ spi5_pins_a: spi5-0 { -+ pins1 { -+ pinmux = , /* SPI5_SCK */ -+ ; /* SPI5_MOSI */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ -+ pins2 { -+ pinmux = ; /* SPI5_MISO */ -+ bias-disable; -+ }; -+ }; -+ -+ spi5_sleep_pins_a: spi5-sleep-0 { -+ pins { -+ pinmux = , /* SPI5_SCK */ -+ , /* SPI5_MISO */ -+ ; /* SPI5_MOSI */ -+ }; -+ }; -+ -+ stusb1600_pins_a: stusb1600-0 { -+ pins { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ }; -+ -+ uart4_pins_a: uart4-0 { -+ pins1 { -+ pinmux = ; /* UART4_TX */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = ; /* UART4_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ uart4_idle_pins_a: uart4-idle-0 { -+ pins1 { -+ pinmux = ; /* UART4_TX */ -+ }; -+ pins2 { -+ pinmux = ; /* UART4_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ uart4_sleep_pins_a: uart4-sleep-0 { -+ pins { -+ pinmux = , /* UART4_TX */ -+ ; /* UART4_RX */ -+ }; -+ }; -+ -+ uart4_pins_b: uart4-1 { -+ pins1 { -+ pinmux = ; /* UART4_TX */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = ; /* UART4_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ uart7_pins_a: uart7-0 { -+ pins1 { -+ pinmux = ; /* UART4_TX */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = , /* UART4_RX */ -+ , /* UART4_CTS */ -+ ; /* UART4_RTS */ -+ bias-disable; -+ }; -+ }; -+ -+ uart7_pins_b: uart7-1 { -+ pins1 { -+ pinmux = ; /* USART7_TX */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = ; /* USART7_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ uart7_idle_pins_b: uart7-idle-1 { -+ pins1 { -+ pinmux = ; /* USART7_TX */ -+ }; -+ pins2 { -+ pinmux = ; /* USART7_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ uart7_sleep_pins_b: uart7-sleep-1 { -+ pins { -+ pinmux = , /* USART7_TX */ -+ ; /* USART7_RX */ -+ }; -+ }; -+ -+ usart2_pins_a: usart2-0 { -+ pins1 { -+ pinmux = , /* USART2_TX */ -+ ; /* USART2_RTS */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <3>; -+ }; -+ pins2 { -+ pinmux = , /* USART2_RX */ -+ ; /* USART2_CTS_NSS */ -+ bias-disable; -+ }; -+ }; -+ -+ usart2_idle_pins_a: usart2-idle-0 { -+ pins1 { -+ pinmux = , /* USART2_TX */ -+ , /* USART2_RTS */ -+ ; /* USART2_CTS_NSS */ -+ }; -+ pins2 { -+ pinmux = ; /* USART2_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ usart2_sleep_pins_a: usart2-sleep-0 { -+ pins { -+ pinmux = , /* USART2_TX */ -+ , /* USART2_RTS */ -+ , /* USART2_RX */ -+ ; /* USART2_CTS_NSS */ -+ }; -+ }; -+ -+ usart3_pins_a: usart3-0 { -+ pins1 { -+ pinmux = , /* USART3_TX */ -+ ; /* USART3_RTS */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = , /* USART3_RX */ -+ ; /* USART3_CTS_NSS */ -+ bias-disable; -+ }; -+ }; -+ -+ usart3_idle_pins_a: usart3-idle-0 { -+ pins1 { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ ; /* USART3_CTS_NSS */ -+ }; -+ pins2 { -+ pinmux = ; /* USART3_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ usart3_sleep_pins_a: usart3-sleep-0 { -+ pins { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ , /* USART3_CTS_NSS */ -+ ; /* USART3_RX */ -+ }; -+ }; -+ -+ usart3_pins_b: usart3-1 { -+ pins1 { -+ pinmux = , /* USART3_TX */ -+ ; /* USART3_RTS */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <0>; -+ }; -+ pins2 { -+ pinmux = , /* USART3_RX */ -+ ; /* USART3_CTS_NSS */ -+ bias-disable; -+ }; -+ }; -+ -+ usart3_idle_pins_b: usart3-idle-1 { -+ pins1 { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ ; /* USART3_CTS_NSS */ -+ }; -+ pins2 { -+ pinmux = ; /* USART3_RX */ -+ bias-disable; -+ }; -+ }; -+ -+ usart3_sleep_pins_b: usart3-sleep-1 { -+ pins { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ , /* USART3_CTS_NSS */ -+ ; /* USART3_RX */ -+ }; -+ }; -+ -+ usbotg_hs_pins_a: usbotg_hs-0 { -+ pins { -+ pinmux = ; /* OTG_ID */ -+ }; -+ }; -+ -+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { -+ pins { -+ pinmux = , /* OTG_FS_DM */ -+ ; /* OTG_FS_DP */ -+ }; -+ }; -+}; -+ -+&pinctrl_z { -+ i2c2_pins_b2: i2c2-0 { -+ pins { -+ pinmux = ; /* I2C2_SCL */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c2_pins_sleep_b2: i2c2-1 { -+ pins { -+ pinmux = ; /* I2C2_SCL */ -+ }; -+ }; -+ -+ i2c4_pins_a: i2c4-0 { -+ pins { -+ pinmux = , /* I2C4_SCL */ -+ ; /* I2C4_SDA */ -+ bias-disable; -+ drive-open-drain; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c4_pins_sleep_a: i2c4-1 { -+ pins { -+ pinmux = , /* I2C4_SCL */ -+ ; /* I2C4_SDA */ -+ }; -+ }; -+ -+ spi1_pins_a: spi1-0 { -+ pins1 { -+ pinmux = , /* SPI1_SCK */ -+ ; /* SPI1_MOSI */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <1>; -+ }; -+ -+ pins2 { -+ pinmux = ; /* SPI1_MISO */ -+ bias-disable; -+ }; -+ }; -+ -+ spi1_sleep_pins_a: spi1-sleep-0 { -+ pins { -+ pinmux = , /* SPI1_SCK */ -+ , /* SPI1_MISO */ -+ ; /* SPI1_MOSI */ -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi -new file mode 100644 -index 0000000..823e281 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi -@@ -0,0 +1,231 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2018 -+ */ -+ -+/ { -+ aliases { -+ gpio0 = &gpioa; -+ gpio1 = &gpiob; -+ gpio2 = &gpioc; -+ gpio3 = &gpiod; -+ gpio4 = &gpioe; -+ gpio5 = &gpiof; -+ gpio6 = &gpiog; -+ gpio7 = &gpioh; -+ gpio8 = &gpioi; -+ gpio9 = &gpioj; -+ gpio10 = &gpiok; -+ gpio25 = &gpioz; -+ pinctrl0 = &pinctrl; -+ pinctrl1 = &pinctrl_z; -+ }; -+ -+ /* need PSCI for sysreset during board_f */ -+ psci { -+ u-boot,dm-pre-proper; -+ }; -+ -+ soc { -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&bsec { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioa { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpiob { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioc { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpiod { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioe { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpiof { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpiog { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioh { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioi { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioj { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpiok { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpioz { -+ u-boot,dm-pre-reloc; -+}; -+ -+&iwdg2 { -+ u-boot,dm-pre-reloc; -+}; -+ -+/* pre-reloc probe = reserve video frame buffer in video_reserve() */ -+<dc { -+ u-boot,dm-pre-proper; -+}; -+ -+&pinctrl { -+ u-boot,dm-pre-reloc; -+}; -+ -+&pinctrl_z { -+ u-boot,dm-pre-reloc; -+}; -+ -+&pwr_regulators { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rcc { -+ u-boot,dm-pre-reloc; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+#ifdef CONFIG_STM32MP1_TRUSTED -+&scmi0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi0_clk { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi0_mbox { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi0_reset { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi0_shm { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi1 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi1_clk { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi1_mbox { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi1_shm { -+ u-boot,dm-pre-reloc; -+}; -+ -+&scmi_sram { -+ u-boot,dm-pre-reloc; -+}; -+#endif -+ -+&sdmmc1 { -+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -+}; -+ -+&sdmmc2 { -+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -+}; -+ -+&sdmmc3 { -+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -+}; -+ -+/* NO MORE USE SCMI SUPPORT for BASIC boot chain */ -+#ifndef CONFIG_STM32MP1_TRUSTED -+ -+#include "stm32mp15-no-scmi.dtsi" -+ -+/ { -+ clocks { -+ u-boot,dm-pre-reloc; -+ -+ clk_hse: clk-hse { -+ u-boot,dm-pre-reloc; -+ }; -+ -+ clk_hsi: clk-hsi { -+ u-boot,dm-pre-reloc; -+ }; -+ -+ clk_lse: clk-lse { -+ u-boot,dm-pre-reloc; -+ }; -+ -+ clk_lsi: clk-lsi { -+ u-boot,dm-pre-reloc; -+ }; -+ -+ clk_csi: clk-csi { -+ u-boot,dm-pre-reloc; -+ }; -+ }; -+ -+ reboot { -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&clk_hse { -+ u-boot,dm-pre-reloc; -+}; -+ -+&clk_hsi { -+ u-boot,dm-pre-reloc; -+}; -+ -+&clk_lse { -+ u-boot,dm-pre-reloc; -+}; -+ -+&clk_lsi { -+ u-boot,dm-pre-reloc; -+}; -+ -+&clk_csi { -+ u-boot,dm-pre-reloc; -+}; -+ -+&cpu0_opp_table { -+ u-boot,dm-spl; -+ opp-650000000 { -+ u-boot,dm-spl; -+ }; -+ opp-800000000 { -+ u-boot,dm-spl; -+ }; -+}; -+#endif /* CONFIG_STM32MP1_TRUSTED */ -diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi -new file mode 100644 -index 0000000..c516e2e ---- /dev/null -+++ b/arch/arm/dts/stm32mp151.dtsi -@@ -0,0 +1,1997 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -+ * Author: Ludovic Barre for STMicroelectronics. -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+ -+/ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <0>; -+ clocks = <&scmi0_clk CK_SCMI0_MPU>; -+ clock-names = "cpu"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ nvmem-cells = <&part_number_otp>; -+ nvmem-cell-names = "part_number"; -+ #cooling-cells = <2>; -+ }; -+ }; -+ -+ cpu0_opp_table: cpu0-opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ }; -+ -+ arm-pmu { -+ compatible = "arm,cortex-a7-pmu"; -+ interrupts = ; -+ interrupt-affinity = <&cpu0>; -+ interrupt-parent = <&intc>; -+ }; -+ -+ scmi_sram: sram@2ffff000 { -+ compatible = "mmio-sram"; -+ reg = <0x2ffff000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x2ffff000 0x1000>; -+ -+ scmi0_shm: scmi_shm@0 { -+ reg = <0 0x80>; -+ }; -+ -+ scmi1_shm: scmi_shm@200 { -+ reg = <0x200 0x80>; -+ }; -+ }; -+ -+ scmi0_mbox: mailbox-0 { -+ #mbox-cells = <0>; -+ compatible = "arm,smc-mbox"; -+ arm,func-id = <0x82002000>; -+ }; -+ -+ scmi1_mbox: mailbox-1 { -+ #mbox-cells = <0>; -+ compatible = "arm,smc-mbox"; -+ arm,func-id = <0x82002001>; -+ }; -+ -+ firmware { -+ scmi0: scmi-0 { -+ compatible = "arm,scmi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mboxes = <&scmi0_mbox 0>; -+ mbox-names = "txrx"; -+ shmem = <&scmi0_shm>; -+ -+ scmi0_clk: protocol@14 { -+ reg = <0x14>; -+ #clock-cells = <1>; -+ }; -+ scmi0_reset: protocol@16 { -+ reg = <0x16>; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ scmi1: scmi-1 { -+ compatible = "arm,scmi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ mboxes = <&scmi1_mbox 0>; -+ mbox-names = "txrx"; -+ shmem = <&scmi1_shm>; -+ -+ scmi1_clk: protocol@14 { -+ reg = <0x14>; -+ #clock-cells = <1>; -+ }; -+ }; -+ -+ optee: optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ status = "disabled"; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ intc: interrupt-controller@a0021000 { -+ compatible = "arm,cortex-a7-gic"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0xa0021000 0x1000>, -+ <0xa0022000 0x2000>; -+ }; -+ -+ timer { -+ compatible = "arm,armv7-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-parent = <&intc>; -+ always-on; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&dts>; -+ -+ trips { -+ cpu-crit { -+ temperature = <120000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ }; -+ }; -+ }; -+ -+ booster: regulator-booster { -+ compatible = "st,stm32mp1-booster"; -+ st,syscfg = <&syscfg>; -+ status = "disabled"; -+ }; -+ -+ pm_domain { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32mp157c-pd"; -+ -+ pd_core_ret: core-ret-power-domain@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ #power-domain-cells = <0>; -+ label = "CORE-RETENTION"; -+ -+ pd_core: core-power-domain@2 { -+ reg = <2>; -+ #power-domain-cells = <0>; -+ label = "CORE"; -+ }; -+ }; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&rcc>; -+ offset = <0x404>; -+ mask = <0x1>; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ interrupt-parent = <&intc>; -+ ranges; -+ -+ sram: sram@10000000 { -+ compatible = "mmio-sram"; -+ reg = <0x10000000 0x60000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x10000000 0x60000>; -+ }; -+ -+ timers2: timer@40000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40000000 0x400>; -+ clocks = <&rcc TIM2_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 18 0x400 0x80000001>, -+ <&dmamux1 19 0x400 0x80000001>, -+ <&dmamux1 20 0x400 0x80000001>, -+ <&dmamux1 21 0x400 0x80000001>, -+ <&dmamux1 22 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4", "up"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@1 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <1>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers3: timer@40001000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40001000 0x400>; -+ clocks = <&rcc TIM3_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 23 0x400 0x80000001>, -+ <&dmamux1 24 0x400 0x80000001>, -+ <&dmamux1 25 0x400 0x80000001>, -+ <&dmamux1 26 0x400 0x80000001>, -+ <&dmamux1 27 0x400 0x80000001>, -+ <&dmamux1 28 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@2 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <2>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers4: timer@40002000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40002000 0x400>; -+ clocks = <&rcc TIM4_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 29 0x400 0x80000001>, -+ <&dmamux1 30 0x400 0x80000001>, -+ <&dmamux1 31 0x400 0x80000001>, -+ <&dmamux1 32 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@3 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <3>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers5: timer@40003000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40003000 0x400>; -+ clocks = <&rcc TIM5_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 55 0x400 0x80000001>, -+ <&dmamux1 56 0x400 0x80000001>, -+ <&dmamux1 57 0x400 0x80000001>, -+ <&dmamux1 58 0x400 0x80000001>, -+ <&dmamux1 59 0x400 0x80000001>, -+ <&dmamux1 60 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@4 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <4>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers6: timer@40004000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40004000 0x400>; -+ clocks = <&rcc TIM6_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 69 0x400 0x80000001>; -+ dma-names = "up"; -+ status = "disabled"; -+ -+ timer@5 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <5>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers7: timer@40005000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40005000 0x400>; -+ clocks = <&rcc TIM7_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 70 0x400 0x80000001>; -+ dma-names = "up"; -+ status = "disabled"; -+ -+ timer@6 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <6>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers12: timer@40006000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40006000 0x400>; -+ clocks = <&rcc TIM12_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@11 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <11>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers13: timer@40007000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40007000 0x400>; -+ clocks = <&rcc TIM13_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@12 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <12>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers14: timer@40008000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x40008000 0x400>; -+ clocks = <&rcc TIM14_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@13 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <13>; -+ status = "disabled"; -+ }; -+ }; -+ -+ lptimer1: timer@40009000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-lptimer"; -+ reg = <0x40009000 0x400>; -+ clocks = <&rcc LPTIM1_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm-lp"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ trigger@0 { -+ compatible = "st,stm32-lptimer-trigger"; -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-lptimer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ spi2: spi@4000b000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x4000b000 0x400>; -+ interrupts = ; -+ clocks = <&rcc SPI2_K>; -+ resets = <&rcc SPI2_R>; -+ dmas = <&dmamux1 39 0x400 0x01>, -+ <&dmamux1 40 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ i2s2: audio-controller@4000b000 { -+ compatible = "st,stm32h7-i2s"; -+ #sound-dai-cells = <0>; -+ reg = <0x4000b000 0x400>; -+ interrupts = ; -+ dmas = <&dmamux1 39 0x400 0x01>, -+ <&dmamux1 40 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ spi3: spi@4000c000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x4000c000 0x400>; -+ interrupts = ; -+ clocks = <&rcc SPI3_K>; -+ resets = <&rcc SPI3_R>; -+ dmas = <&dmamux1 61 0x400 0x01>, -+ <&dmamux1 62 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ i2s3: audio-controller@4000c000 { -+ compatible = "st,stm32h7-i2s"; -+ #sound-dai-cells = <0>; -+ reg = <0x4000c000 0x400>; -+ interrupts = ; -+ dmas = <&dmamux1 61 0x400 0x01>, -+ <&dmamux1 62 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ spdifrx: audio-controller@4000d000 { -+ compatible = "st,stm32h7-spdifrx"; -+ #sound-dai-cells = <0>; -+ reg = <0x4000d000 0x400>; -+ clocks = <&rcc SPDIF_K>; -+ clock-names = "kclk"; -+ interrupts = ; -+ dmas = <&dmamux1 93 0x400 0x01>, -+ <&dmamux1 94 0x400 0x01>; -+ dma-names = "rx", "rx-ctrl"; -+ status = "disabled"; -+ }; -+ -+ usart2: serial@4000e000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x4000e000 0x400>; -+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc USART2_K>; -+ resets = <&rcc USART2_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 43 0x400 0x5>, -+ <&dmamux1 44 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ usart3: serial@4000f000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x4000f000 0x400>; -+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc USART3_K>; -+ resets = <&rcc USART3_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 45 0x400 0x5>, -+ <&dmamux1 46 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@40010000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x40010000 0x400>; -+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc UART4_K>; -+ resets = <&rcc UART4_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 63 0x400 0x5>, -+ <&dmamux1 64 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@40011000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x40011000 0x400>; -+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc UART5_K>; -+ resets = <&rcc UART5_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 65 0x400 0x5>, -+ <&dmamux1 66 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@40012000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x40012000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc I2C1_K>; -+ resets = <&rcc I2C1_R>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&dmamux1 33 0x400 0x80000001>, -+ <&dmamux1 34 0x400 0x80000001>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x1>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@40013000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x40013000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc I2C2_K>; -+ resets = <&rcc I2C2_R>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&dmamux1 35 0x400 0x80000001>, -+ <&dmamux1 36 0x400 0x80000001>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x2>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@40014000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x40014000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc I2C3_K>; -+ resets = <&rcc I2C3_R>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&dmamux1 73 0x400 0x80000001>, -+ <&dmamux1 74 0x400 0x80000001>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x4>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@40015000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x40015000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc I2C5_K>; -+ resets = <&rcc I2C5_R>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&dmamux1 115 0x400 0x80000001>, -+ <&dmamux1 116 0x400 0x80000001>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x10>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ cec: cec@40016000 { -+ compatible = "st,stm32-cec"; -+ reg = <0x40016000 0x400>; -+ interrupts = ; -+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; -+ clock-names = "cec", "hdmi-cec"; -+ status = "disabled"; -+ }; -+ -+ dac: dac@40017000 { -+ compatible = "st,stm32h7-dac-core"; -+ reg = <0x40017000 0x400>; -+ clocks = <&rcc DAC12>; -+ clock-names = "pclk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ dac1: dac@1 { -+ compatible = "st,stm32-dac"; -+ #io-channel-cells = <1>; -+ reg = <1>; -+ status = "disabled"; -+ }; -+ -+ dac2: dac@2 { -+ compatible = "st,stm32-dac"; -+ #io-channel-cells = <1>; -+ reg = <2>; -+ status = "disabled"; -+ }; -+ }; -+ -+ uart7: serial@40018000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x40018000 0x400>; -+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc UART7_K>; -+ resets = <&rcc UART7_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 79 0x400 0x5>, -+ <&dmamux1 80 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@40019000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x40019000 0x400>; -+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc UART8_K>; -+ resets = <&rcc UART8_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 81 0x400 0x5>, -+ <&dmamux1 82 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ timers1: timer@44000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x44000000 0x400>; -+ clocks = <&rcc TIM1_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 11 0x400 0x80000001>, -+ <&dmamux1 12 0x400 0x80000001>, -+ <&dmamux1 13 0x400 0x80000001>, -+ <&dmamux1 14 0x400 0x80000001>, -+ <&dmamux1 15 0x400 0x80000001>, -+ <&dmamux1 16 0x400 0x80000001>, -+ <&dmamux1 17 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4", -+ "up", "trig", "com"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@0 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <0>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers8: timer@44001000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x44001000 0x400>; -+ clocks = <&rcc TIM8_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 47 0x400 0x80000001>, -+ <&dmamux1 48 0x400 0x80000001>, -+ <&dmamux1 49 0x400 0x80000001>, -+ <&dmamux1 50 0x400 0x80000001>, -+ <&dmamux1 51 0x400 0x80000001>, -+ <&dmamux1 52 0x400 0x80000001>, -+ <&dmamux1 53 0x400 0x80000001>; -+ dma-names = "ch1", "ch2", "ch3", "ch4", -+ "up", "trig", "com"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@7 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <7>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-timer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ usart6: serial@44003000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x44003000 0x400>; -+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&rcc USART6_K>; -+ resets = <&rcc USART6_R>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ dmas = <&dmamux1 71 0x400 0x5>, -+ <&dmamux1 72 0x400 0x1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@44004000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x44004000 0x400>; -+ interrupts = ; -+ clocks = <&rcc SPI1_K>; -+ resets = <&rcc SPI1_R>; -+ dmas = <&dmamux1 37 0x400 0x01>, -+ <&dmamux1 38 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ i2s1: audio-controller@44004000 { -+ compatible = "st,stm32h7-i2s"; -+ #sound-dai-cells = <0>; -+ reg = <0x44004000 0x400>; -+ interrupts = ; -+ dmas = <&dmamux1 37 0x400 0x01>, -+ <&dmamux1 38 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ spi4: spi@44005000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x44005000 0x400>; -+ interrupts = ; -+ clocks = <&rcc SPI4_K>; -+ resets = <&rcc SPI4_R>; -+ dmas = <&dmamux1 83 0x400 0x01>, -+ <&dmamux1 84 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ timers15: timer@44006000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x44006000 0x400>; -+ clocks = <&rcc TIM15_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 105 0x400 0x80000001>, -+ <&dmamux1 106 0x400 0x80000001>, -+ <&dmamux1 107 0x400 0x80000001>, -+ <&dmamux1 108 0x400 0x80000001>; -+ dma-names = "ch1", "up", "trig", "com"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@14 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <14>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers16: timer@44007000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x44007000 0x400>; -+ clocks = <&rcc TIM16_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 109 0x400 0x80000001>, -+ <&dmamux1 110 0x400 0x80000001>; -+ dma-names = "ch1", "up"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ timer@15 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <15>; -+ status = "disabled"; -+ }; -+ }; -+ -+ timers17: timer@44008000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-timers"; -+ reg = <0x44008000 0x400>; -+ clocks = <&rcc TIM17_K>; -+ clock-names = "int"; -+ dmas = <&dmamux1 111 0x400 0x80000001>, -+ <&dmamux1 112 0x400 0x80000001>; -+ dma-names = "ch1", "up"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ timer@16 { -+ compatible = "st,stm32h7-timer-trigger"; -+ reg = <16>; -+ status = "disabled"; -+ }; -+ }; -+ -+ spi5: spi@44009000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x44009000 0x400>; -+ interrupts = ; -+ clocks = <&rcc SPI5_K>; -+ resets = <&rcc SPI5_R>; -+ dmas = <&dmamux1 85 0x400 0x01>, -+ <&dmamux1 86 0x400 0x01>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ sai1: sai@4400a000 { -+ compatible = "st,stm32h7-sai"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x4400a000 0x400>; -+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; -+ interrupts = ; -+ resets = <&rcc SAI1_R>; -+ status = "disabled"; -+ -+ sai1a: audio-controller@4400a004 { -+ #sound-dai-cells = <0>; -+ -+ compatible = "st,stm32-sai-sub-a"; -+ reg = <0x4 0x1c>; -+ clocks = <&rcc SAI1_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 87 0x400 0x01>; -+ status = "disabled"; -+ }; -+ -+ sai1b: audio-controller@4400a024 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-b"; -+ reg = <0x24 0x1c>; -+ clocks = <&rcc SAI1_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 88 0x400 0x01>; -+ status = "disabled"; -+ }; -+ }; -+ -+ sai2: sai@4400b000 { -+ compatible = "st,stm32h7-sai"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x4400b000 0x400>; -+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; -+ interrupts = ; -+ resets = <&rcc SAI2_R>; -+ status = "disabled"; -+ -+ sai2a: audio-controller@4400b004 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-a"; -+ reg = <0x4 0x1c>; -+ clocks = <&rcc SAI2_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 89 0x400 0x01>; -+ status = "disabled"; -+ }; -+ -+ sai2b: audio-controller@4400b024 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-b"; -+ reg = <0x24 0x1c>; -+ clocks = <&rcc SAI2_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 90 0x400 0x01>; -+ status = "disabled"; -+ }; -+ }; -+ -+ sai3: sai@4400c000 { -+ compatible = "st,stm32h7-sai"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x4400c000 0x400>; -+ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; -+ interrupts = ; -+ resets = <&rcc SAI3_R>; -+ status = "disabled"; -+ -+ sai3a: audio-controller@4400c004 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-a"; -+ reg = <0x04 0x1c>; -+ clocks = <&rcc SAI3_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 113 0x400 0x01>; -+ status = "disabled"; -+ }; -+ -+ sai3b: audio-controller@4400c024 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-b"; -+ reg = <0x24 0x1c>; -+ clocks = <&rcc SAI3_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 114 0x400 0x01>; -+ status = "disabled"; -+ }; -+ }; -+ -+ dfsdm: dfsdm@4400d000 { -+ compatible = "st,stm32mp1-dfsdm"; -+ reg = <0x4400d000 0x800>; -+ clocks = <&rcc DFSDM_K>; -+ clock-names = "dfsdm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ dfsdm0: filter@0 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <0>; -+ interrupts = ; -+ dmas = <&dmamux1 101 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ dfsdm1: filter@1 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <1>; -+ interrupts = ; -+ dmas = <&dmamux1 102 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ dfsdm2: filter@2 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <2>; -+ interrupts = ; -+ dmas = <&dmamux1 103 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ dfsdm3: filter@3 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <3>; -+ interrupts = ; -+ dmas = <&dmamux1 104 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ dfsdm4: filter@4 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <4>; -+ interrupts = ; -+ dmas = <&dmamux1 91 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ dfsdm5: filter@5 { -+ compatible = "st,stm32-dfsdm-adc"; -+ #io-channel-cells = <1>; -+ reg = <5>; -+ interrupts = ; -+ dmas = <&dmamux1 92 0x400 0x01>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ }; -+ -+ dma1: dma@48000000 { -+ compatible = "st,stm32-dma"; -+ reg = <0x48000000 0x400>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ clocks = <&rcc DMA1>; -+ resets = <&rcc DMA1_R>; -+ #dma-cells = <4>; -+ st,mem2mem; -+ dma-requests = <8>; -+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>, -+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>, -+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>, -+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>, -+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>, -+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>, -+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>, -+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>; -+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; -+ }; -+ -+ dma2: dma@48001000 { -+ compatible = "st,stm32-dma"; -+ reg = <0x48001000 0x400>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ clocks = <&rcc DMA2>; -+ resets = <&rcc DMA2_R>; -+ #dma-cells = <4>; -+ st,mem2mem; -+ dma-requests = <8>; -+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>, -+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>, -+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>, -+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>, -+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>, -+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>, -+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>, -+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>; -+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; -+ }; -+ -+ dmamux1: dma-router@48002000 { -+ compatible = "st,stm32h7-dmamux"; -+ reg = <0x48002000 0x40>; -+ #dma-cells = <3>; -+ dma-requests = <128>; -+ dma-masters = <&dma1 &dma2>; -+ dma-channels = <16>; -+ clocks = <&rcc DMAMUX>; -+ resets = <&rcc DMAMUX_R>; -+ }; -+ -+ adc: adc@48003000 { -+ compatible = "st,stm32mp1-adc-core"; -+ reg = <0x48003000 0x400>; -+ interrupts = , -+ ; -+ clocks = <&rcc ADC12>, <&rcc ADC12_K>; -+ clock-names = "bus", "adc"; -+ interrupt-controller; -+ st,syscfg = <&syscfg>; -+ #interrupt-cells = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ adc1: adc@0 { -+ compatible = "st,stm32mp1-adc"; -+ #io-channel-cells = <1>; -+ reg = <0x0>; -+ interrupt-parent = <&adc>; -+ interrupts = <0>; -+ dmas = <&dmamux1 9 0x400 0x80000001>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ -+ adc2: adc@100 { -+ compatible = "st,stm32mp1-adc"; -+ #io-channel-cells = <1>; -+ reg = <0x100>; -+ interrupt-parent = <&adc>; -+ interrupts = <1>; -+ dmas = <&dmamux1 10 0x400 0x80000001>; -+ dma-names = "rx"; -+ status = "disabled"; -+ }; -+ }; -+ -+ sdmmc3: sdmmc@48004000 { -+ compatible = "arm,pl18x", "arm,primecell"; -+ arm,primecell-periphid = <0x00253180>; -+ reg = <0x48004000 0x400>, <0x48005000 0x400>; -+ interrupts = ; -+ interrupt-names = "cmd_irq"; -+ clocks = <&rcc SDMMC3_K>; -+ clock-names = "apb_pclk"; -+ resets = <&rcc SDMMC3_R>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ max-frequency = <120000000>; -+ status = "disabled"; -+ }; -+ -+ usbotg_hs: usb-otg@49000000 { -+ compatible = "st,stm32mp1-hsotg", "snps,dwc2"; -+ reg = <0x49000000 0x10000>; -+ clocks = <&rcc USBO_K>; -+ clock-names = "otg"; -+ resets = <&rcc USBO_R>; -+ reset-names = "dwc2"; -+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>; -+ g-rx-fifo-size = <512>; -+ g-np-tx-fifo-size = <32>; -+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; -+ dr_mode = "otg"; -+ usb33d-supply = <&usb33>; -+ power-domains = <&pd_core>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ hsem: hwspinlock@4c000000 { -+ compatible = "st,stm32-hwspinlock"; -+ #hwlock-cells = <2>; -+ reg = <0x4c000000 0x400>; -+ clocks = <&rcc HSEM>; -+ clock-names = "hsem"; -+ }; -+ -+ ipcc: mailbox@4c001000 { -+ compatible = "st,stm32mp1-ipcc"; -+ #mbox-cells = <1>; -+ reg = <0x4c001000 0x400>; -+ st,proc-id = <0>; -+ interrupts-extended = -+ <&exti 61 1>, -+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "rx", "tx"; -+ clocks = <&rcc IPCC>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ dcmi: dcmi@4c006000 { -+ compatible = "st,stm32-dcmi"; -+ reg = <0x4c006000 0x400>; -+ interrupts = ; -+ resets = <&rcc CAMITF_R>; -+ clocks = <&rcc DCMI>; -+ clock-names = "mclk"; -+ dmas = <&dmamux1 75 0x400 0xe0000001>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ -+ rcc: rcc@50000000 { -+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; -+ reg = <0x50000000 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ interrupts = ; -+ -+ clock-names = "hse", "hsi", "csi", "lse", "lsi"; -+ clocks = <&scmi0_clk CK_SCMI0_HSE>, -+ <&scmi0_clk CK_SCMI0_HSI>, -+ <&scmi0_clk CK_SCMI0_CSI>, -+ <&scmi0_clk CK_SCMI0_LSE>, -+ <&scmi0_clk CK_SCMI0_LSI>; -+ }; -+ -+ pwr_regulators: pwr@50001000 { -+ compatible = "st,stm32mp1,pwr-reg"; -+ reg = <0x50001000 0x10>; -+ st,tzcr = <&rcc 0x0 0x1>; -+ -+ reg11: reg11 { -+ regulator-name = "reg11"; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ }; -+ -+ reg18: reg18 { -+ regulator-name = "reg18"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ usb33: usb33 { -+ regulator-name = "usb33"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ -+ pwr_mcu: pwr_mcu@50001014 { -+ compatible = "syscon"; -+ reg = <0x50001014 0x4>; -+ }; -+ -+ pwr_irq: pwr@50001020 { -+ compatible = "st,stm32mp1-pwr"; -+ reg = <0x50001020 0x100>; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ -+ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>, -+ <&gpioa 2 GPIO_ACTIVE_HIGH>, -+ <&gpioc 13 GPIO_ACTIVE_HIGH>, -+ <&gpioi 8 GPIO_ACTIVE_HIGH>, -+ <&gpioi 11 GPIO_ACTIVE_HIGH>, -+ <&gpioc 1 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ exti: interrupt-controller@5000d000 { -+ compatible = "st,stm32mp1-exti", "syscon"; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x5000d000 0x400>; -+ hwlocks = <&hsem 1 1>; -+ -+ /* exti_pwr is an extra interrupt controller used for -+ * EXTI 55 to 60. It's mapped on pwr interrupt -+ * controller. -+ */ -+ exti_pwr: exti-pwr { -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <&pwr_irq>; -+ st,irq-number = <6>; -+ }; -+ }; -+ -+ syscfg: syscon@50020000 { -+ compatible = "st,stm32mp157-syscfg", "syscon"; -+ reg = <0x50020000 0x400>; -+ clocks = <&rcc SYSCFG>; -+ }; -+ -+ lptimer2: timer@50021000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-lptimer"; -+ reg = <0x50021000 0x400>; -+ clocks = <&rcc LPTIM2_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm-lp"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ trigger@1 { -+ compatible = "st,stm32-lptimer-trigger"; -+ reg = <1>; -+ status = "disabled"; -+ }; -+ -+ counter { -+ compatible = "st,stm32-lptimer-counter"; -+ status = "disabled"; -+ }; -+ }; -+ -+ lptimer3: timer@50022000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32-lptimer"; -+ reg = <0x50022000 0x400>; -+ clocks = <&rcc LPTIM3_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm-lp"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ trigger@2 { -+ compatible = "st,stm32-lptimer-trigger"; -+ reg = <2>; -+ status = "disabled"; -+ }; -+ }; -+ -+ lptimer4: timer@50023000 { -+ compatible = "st,stm32-lptimer"; -+ reg = <0x50023000 0x400>; -+ clocks = <&rcc LPTIM4_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm-lp"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ }; -+ -+ lptimer5: timer@50024000 { -+ compatible = "st,stm32-lptimer"; -+ reg = <0x50024000 0x400>; -+ clocks = <&rcc LPTIM5_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ -+ pwm { -+ compatible = "st,stm32-pwm-lp"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ }; -+ -+ vrefbuf: vrefbuf@50025000 { -+ compatible = "st,stm32-vrefbuf"; -+ reg = <0x50025000 0x8>; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <2500000>; -+ clocks = <&rcc VREF>; -+ status = "disabled"; -+ }; -+ -+ sai4: sai@50027000 { -+ compatible = "st,stm32h7-sai"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x50027000 0x400>; -+ reg = <0x50027000 0x4>, <0x500273f0 0x10>; -+ interrupts = ; -+ resets = <&rcc SAI4_R>; -+ status = "disabled"; -+ -+ sai4a: audio-controller@50027004 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-a"; -+ reg = <0x04 0x1c>; -+ clocks = <&rcc SAI4_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 99 0x400 0x01>; -+ status = "disabled"; -+ }; -+ -+ sai4b: audio-controller@50027024 { -+ #sound-dai-cells = <0>; -+ compatible = "st,stm32-sai-sub-b"; -+ reg = <0x24 0x1c>; -+ clocks = <&rcc SAI4_K>; -+ clock-names = "sai_ck"; -+ dmas = <&dmamux1 100 0x400 0x01>; -+ status = "disabled"; -+ }; -+ }; -+ -+ dts: thermal@50028000 { -+ compatible = "st,stm32-thermal"; -+ reg = <0x50028000 0x100>; -+ interrupts = ; -+ clocks = <&rcc TMPSENS>; -+ clock-names = "pclk"; -+ #thermal-sensor-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ hdp: hdp@5002a000 { -+ compatible = "st,stm32mp1-hdp"; -+ reg = <0x5002a000 0x400>; -+ clocks = <&rcc HDP>; -+ clock-names = "hdp"; -+ status = "disabled"; -+ }; -+ -+ hash1: hash@54002000 { -+ compatible = "st,stm32f756-hash"; -+ reg = <0x54002000 0x400>; -+ interrupts = ; -+ clocks = <&scmi0_clk CK_SCMI0_HASH1>; -+ resets = <&scmi0_reset RST_SCMI0_HASH1>; -+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>; -+ dma-names = "in"; -+ dma-maxburst = <2>; -+ status = "disabled"; -+ }; -+ -+ rng1: rng@54003000 { -+ compatible = "st,stm32-rng"; -+ reg = <0x54003000 0x400>; -+ clocks = <&scmi0_clk CK_SCMI0_RNG1>; -+ resets = <&scmi0_reset RST_SCMI0_RNG1>; -+ status = "disabled"; -+ }; -+ -+ mdma1: dma@58000000 { -+ compatible = "st,stm32h7-mdma"; -+ reg = <0x58000000 0x1000>; -+ interrupts = ; -+ clocks = <&rcc MDMA>; -+ resets = <&scmi0_reset RST_SCMI0_MDMA>; -+ #dma-cells = <6>; -+ dma-channels = <32>; -+ dma-requests = <48>; -+ }; -+ -+ fmc: nand-controller@58002000 { -+ compatible = "st,stm32mp15-fmc2"; -+ reg = <0x58002000 0x1000>, -+ <0x80000000 0x1000>, -+ <0x88010000 0x1000>, -+ <0x88020000 0x1000>, -+ <0x81000000 0x1000>, -+ <0x89010000 0x1000>, -+ <0x89020000 0x1000>; -+ interrupts = ; -+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>, -+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>, -+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>; -+ dma-names = "tx", "rx", "ecc"; -+ clocks = <&rcc FMC_K>; -+ resets = <&rcc FMC_R>; -+ status = "disabled"; -+ }; -+ -+ qspi: spi@58003000 { -+ compatible = "st,stm32f469-qspi"; -+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; -+ reg-names = "qspi", "qspi_mm"; -+ interrupts = ; -+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>, -+ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>; -+ dma-names = "tx", "rx"; -+ clocks = <&rcc QSPI_K>; -+ resets = <&rcc QSPI_R>; -+ status = "disabled"; -+ }; -+ -+ sdmmc1: sdmmc@58005000 { -+ compatible = "arm,pl18x", "arm,primecell"; -+ arm,primecell-periphid = <0x00253180>; -+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>; -+ interrupts = ; -+ interrupt-names = "cmd_irq"; -+ clocks = <&rcc SDMMC1_K>; -+ clock-names = "apb_pclk"; -+ resets = <&rcc SDMMC1_R>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ max-frequency = <120000000>; -+ status = "disabled"; -+ }; -+ -+ sdmmc2: sdmmc@58007000 { -+ compatible = "arm,pl18x", "arm,primecell"; -+ arm,primecell-periphid = <0x00253180>; -+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>; -+ interrupts = ; -+ interrupt-names = "cmd_irq"; -+ clocks = <&rcc SDMMC2_K>; -+ clock-names = "apb_pclk"; -+ resets = <&rcc SDMMC2_R>; -+ cap-sd-highspeed; -+ cap-mmc-highspeed; -+ max-frequency = <120000000>; -+ status = "disabled"; -+ }; -+ -+ crc1: crc@58009000 { -+ compatible = "st,stm32f7-crc"; -+ reg = <0x58009000 0x400>; -+ clocks = <&rcc CRC1>; -+ status = "disabled"; -+ }; -+ -+ stmmac_axi_config_0: stmmac-axi-config { -+ snps,wr_osr_lmt = <0x7>; -+ snps,rd_osr_lmt = <0x7>; -+ snps,blen = <0 0 0 0 16 8 4>; -+ }; -+ -+ ethernet0: ethernet@5800a000 { -+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; -+ reg = <0x5800a000 0x2000>; -+ reg-names = "stmmaceth"; -+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, -+ <&exti 70 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", -+ "eth_wake_irq"; -+ clock-names = "stmmaceth", -+ "mac-clk-tx", -+ "mac-clk-rx", -+ "ethstp"; -+ clocks = <&rcc ETHMAC>, -+ <&rcc ETHTX>, -+ <&rcc ETHRX>, -+ <&rcc ETHSTP>; -+ st,syscon = <&syscfg 0x4>; -+ snps,mixed-burst; -+ snps,pbl = <2>; -+ snps,en-tx-lpi-clockgating; -+ snps,axi-config = <&stmmac_axi_config_0>; -+ snps,tso; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ usbh_ohci: usbh-ohci@5800c000 { -+ compatible = "generic-ohci"; -+ reg = <0x5800c000 0x1000>; -+ clocks = <&rcc USBH>; -+ resets = <&rcc USBH_R>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usbh_ehci: usbh-ehci@5800d000 { -+ compatible = "generic-ehci"; -+ reg = <0x5800d000 0x1000>; -+ clocks = <&rcc USBH>; -+ resets = <&rcc USBH_R>; -+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>; -+ companion = <&usbh_ohci>; -+ power-domains = <&pd_core>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ ltdc: display-controller@5a001000 { -+ compatible = "st,stm32-ltdc"; -+ reg = <0x5a001000 0x400>; -+ interrupts = , -+ ; -+ clocks = <&rcc LTDC_PX>; -+ clock-names = "lcd"; -+ resets = <&rcc LTDC_R>; -+ status = "disabled"; -+ }; -+ -+ iwdg2: watchdog@5a002000 { -+ compatible = "st,stm32mp1-iwdg"; -+ reg = <0x5a002000 0x400>; -+ clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; -+ clock-names = "pclk", "lsi"; -+ status = "disabled"; -+ }; -+ -+ usbphyc: usbphyc@5a006000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #clock-cells = <0>; -+ compatible = "st,stm32mp1-usbphyc"; -+ reg = <0x5a006000 0x1000>; -+ clocks = <&rcc USBPHY_K>; -+ resets = <&rcc USBPHY_R>; -+ vdda1v1-supply = <®11>; -+ vdda1v8-supply = <®18>; -+ status = "disabled"; -+ -+ usbphyc_port0: usb-phy@0 { -+ #phy-cells = <0>; -+ reg = <0>; -+ }; -+ -+ usbphyc_port1: usb-phy@1 { -+ #phy-cells = <1>; -+ reg = <1>; -+ }; -+ }; -+ -+ ddrperfm: perf@5a007000 { -+ compatible = "st,stm32-ddr-pmu"; -+ reg = <0x5a007000 0x400>; -+ clocks = <&rcc DDRPERFM>, <&scmi0_clk CK_SCMI0_PLL2_R>; -+ clock-names = "bus", "ddr"; -+ resets = <&rcc DDRPERFM_R>; -+ }; -+ -+ usart1: serial@5c000000 { -+ compatible = "st,stm32h7-uart"; -+ reg = <0x5c000000 0x400>; -+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&scmi0_clk CK_SCMI0_USART1>; -+ resets = <&scmi0_reset RST_SCMI0_USART1>; -+ wakeup-source; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ spi6: spi@5c001000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32h7-spi"; -+ reg = <0x5c001000 0x400>; -+ interrupts = ; -+ clocks = <&scmi0_clk CK_SCMI0_SPI6>; -+ resets = <&scmi0_reset RST_SCMI0_SPI6>; -+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>, -+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@5c002000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x5c002000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&scmi0_clk CK_SCMI0_I2C4>; -+ resets = <&scmi0_reset RST_SCMI0_I2C4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>, -+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x8>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ rtc: rtc@5c004000 { -+ compatible = "st,stm32mp1-rtc"; -+ reg = <0x5c004000 0x400>; -+ clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, -+ <&scmi0_clk CK_SCMI0_RTC>; -+ clock-names = "pclk", "rtc_ck"; -+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ bsec: nvmem@5c005000 { -+ compatible = "st,stm32mp15-bsec"; -+ reg = <0x5c005000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ part_number_otp: part_number_otp@4 { -+ reg = <0x4 0x1>; -+ }; -+ ts_cal1: calib@5c { -+ reg = <0x5c 0x2>; -+ }; -+ ts_cal2: calib@5e { -+ reg = <0x5e 0x2>; -+ }; -+ }; -+ -+ i2c6: i2c@5c009000 { -+ compatible = "st,stm32mp15-i2c"; -+ reg = <0x5c009000 0x400>; -+ interrupt-names = "event", "error"; -+ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&scmi0_clk CK_SCMI0_I2C6>; -+ resets = <&scmi0_reset RST_SCMI0_I2C6>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>, -+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>; -+ dma-names = "rx", "tx"; -+ power-domains = <&pd_core>; -+ st,syscfg-fmp = <&syscfg 0x4 0x20>; -+ wakeup-source; -+ status = "disabled"; -+ }; -+ -+ tamp: tamp@5c00a000 { -+ compatible = "simple-bus", "syscon", "simple-mfd"; -+ reg = <0x5c00a000 0x400>; -+ -+ reboot-mode { -+ compatible = "syscon-reboot-mode"; -+ offset = <0x150>; /* reg20 */ -+ mask = <0xff>; -+ mode-normal = <0>; -+ mode-fastboot = <0x1>; -+ mode-recovery = <0x2>; -+ mode-stm32cubeprogrammer = <0x3>; -+ mode-ums_mmc0 = <0x10>; -+ mode-ums_mmc1 = <0x11>; -+ mode-ums_mmc2 = <0x12>; -+ }; -+ }; -+ -+ /* -+ * Break node order to solve dependency probe issue between -+ * pinctrl and exti. -+ */ -+ pinctrl: pin-controller@50002000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,stm32mp157-pinctrl"; -+ ranges = <0 0x50002000 0xa400>; -+ interrupt-parent = <&exti>; -+ st,syscfg = <&exti 0x60 0xff>; -+ hwlocks = <&hsem 0 1>; -+ pins-are-numbered; -+ -+ gpioa: gpio@50002000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x0 0x400>; -+ clocks = <&rcc GPIOA>; -+ st,bank-name = "GPIOA"; -+ status = "disabled"; -+ }; -+ -+ gpiob: gpio@50003000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x1000 0x400>; -+ clocks = <&rcc GPIOB>; -+ st,bank-name = "GPIOB"; -+ status = "disabled"; -+ }; -+ -+ gpioc: gpio@50004000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x2000 0x400>; -+ clocks = <&rcc GPIOC>; -+ st,bank-name = "GPIOC"; -+ status = "disabled"; -+ }; -+ -+ gpiod: gpio@50005000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x3000 0x400>; -+ clocks = <&rcc GPIOD>; -+ st,bank-name = "GPIOD"; -+ status = "disabled"; -+ }; -+ -+ gpioe: gpio@50006000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x4000 0x400>; -+ clocks = <&rcc GPIOE>; -+ st,bank-name = "GPIOE"; -+ status = "disabled"; -+ }; -+ -+ gpiof: gpio@50007000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x5000 0x400>; -+ clocks = <&rcc GPIOF>; -+ st,bank-name = "GPIOF"; -+ status = "disabled"; -+ }; -+ -+ gpiog: gpio@50008000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x6000 0x400>; -+ clocks = <&rcc GPIOG>; -+ st,bank-name = "GPIOG"; -+ status = "disabled"; -+ }; -+ -+ gpioh: gpio@50009000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x7000 0x400>; -+ clocks = <&rcc GPIOH>; -+ st,bank-name = "GPIOH"; -+ status = "disabled"; -+ }; -+ -+ gpioi: gpio@5000a000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x8000 0x400>; -+ clocks = <&rcc GPIOI>; -+ st,bank-name = "GPIOI"; -+ status = "disabled"; -+ }; -+ -+ gpioj: gpio@5000b000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x9000 0x400>; -+ clocks = <&rcc GPIOJ>; -+ st,bank-name = "GPIOJ"; -+ status = "disabled"; -+ }; -+ -+ gpiok: gpio@5000c000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0xa000 0x400>; -+ clocks = <&rcc GPIOK>; -+ st,bank-name = "GPIOK"; -+ status = "disabled"; -+ }; -+ }; -+ -+ pinctrl_z: pin-controller-z@54004000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,stm32mp157-z-pinctrl"; -+ ranges = <0 0x54004000 0x400>; -+ pins-are-numbered; -+ interrupt-parent = <&exti>; -+ st,syscfg = <&exti 0x60 0xff>; -+ hwlocks = <&hsem 0 1>; -+ -+ gpioz: gpio@54004000 { -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0 0x400>; -+ clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; -+ st,bank-name = "GPIOZ"; -+ st,bank-ioport = <11>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ mlahb { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ dma-ranges = <0x00000000 0x38000000 0x10000>, -+ <0x10000000 0x10000000 0x60000>, -+ <0x30000000 0x30000000 0x60000>; -+ -+ m4_rproc: m4@10000000 { -+ compatible = "st,stm32mp1-m4"; -+ reg = <0x10000000 0x40000>, -+ <0x30000000 0x40000>, -+ <0x38000000 0x10000>; -+ resets = <&scmi0_reset RST_SCMI0_MCU>; -+ st,syscfg-holdboot = <&rcc 0x10C 0x1>; -+ st,syscfg-tz = <&rcc 0x000 0x1>; -+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; -+ st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>; -+ st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; -+ status = "disabled"; -+ -+ m4_system_resources { -+ compatible = "rproc-srm-core"; -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi -new file mode 100644 -index 0000000..cf16b84 ---- /dev/null -+++ b/arch/arm/dts/stm32mp153.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+#include "stm32mp151.dtsi" -+ -+/ { -+ cpus { -+ cpu1: cpu@1 { -+ compatible = "arm,cortex-a7"; -+ device_type = "cpu"; -+ reg = <1>; -+ clocks = <&scmi0_clk CK_SCMI0_MPU>; -+ clock-names = "cpu"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ }; -+ }; -+ -+ arm-pmu { -+ interrupts = , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>; -+ }; -+ -+ soc { -+ m_can1: can@4400e000 { -+ compatible = "bosch,m_can"; -+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>; -+ reg-names = "m_can", "message_ram"; -+ interrupts = , -+ ; -+ interrupt-names = "int0", "int1"; -+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; -+ clock-names = "hclk", "cclk"; -+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; -+ status = "disabled"; -+ }; -+ -+ m_can2: can@4400f000 { -+ compatible = "bosch,m_can"; -+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>; -+ reg-names = "m_can", "message_ram"; -+ interrupts = , -+ ; -+ interrupt-names = "int0", "int1"; -+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; -+ clock-names = "hclk", "cclk"; -+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi b/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi -new file mode 100644 -index 0000000..b4030e5 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi -@@ -0,0 +1,524 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Fabien Dessenne for STMicroelectronics. -+ */ -+ -+&pinctrl { -+ m4_adc1_in6_pins_a: m4-adc1-in6 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_adc12_ain_pins_a: m4-adc12-ain-0 { -+ pins { -+ pinmux = , /* ADC1 in13 */ -+ , /* ADC1 in6 */ -+ , /* ADC2 in2 */ -+ ; /* ADC2 in6 */ -+ }; -+ }; -+ -+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 { -+ pins { -+ pinmux = , /* ADC12 in18 */ -+ ; /* ADC12 in19 */ -+ }; -+ }; -+ -+ m4_cec_pins_a: m4-cec-0 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_cec_pins_b: m4-cec-1 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_dac_ch1_pins_a: m4-dac-ch1 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_dac_ch2_pins_a: m4-dac-ch2 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_dcmi_pins_a: m4-dcmi-0 { -+ pins { -+ pinmux = ,/* DCMI_HSYNC */ -+ ,/* DCMI_VSYNC */ -+ ,/* DCMI_PIXCLK */ -+ ,/* DCMI_D0 */ -+ ,/* DCMI_D1 */ -+ ,/* DCMI_D2 */ -+ ,/* DCMI_D3 */ -+ ,/* DCMI_D4 */ -+ ,/* DCMI_D5 */ -+ ,/* DCMI_D6 */ -+ ,/* DCMI_D7 */ -+ ,/* DCMI_D8 */ -+ ,/* DCMI_D9 */ -+ ,/* DCMI_D10 */ -+ ;/* DCMI_D11 */ -+ }; -+ }; -+ -+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_CKOUT */ -+ }; -+ }; -+ -+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA1 */ -+ }; -+ }; -+ -+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 { -+ pins { -+ pinmux = ; /* DFSDM_DATA3 */ -+ }; -+ }; -+ -+ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 { -+ pins { -+ pinmux = , /* ETH_RGMII_CLK125 */ -+ , /* ETH_RGMII_GTX_CLK */ -+ , /* ETH_RGMII_TXD0 */ -+ , /* ETH_RGMII_TXD1 */ -+ , /* ETH_RGMII_TXD2 */ -+ , /* ETH_RGMII_TXD3 */ -+ , /* ETH_RGMII_TX_CTL */ -+ , /* ETH_MDC */ -+ , /* ETH_MDIO */ -+ , /* ETH_RGMII_RXD0 */ -+ , /* ETH_RGMII_RXD1 */ -+ , /* ETH_RGMII_RXD2 */ -+ , /* ETH_RGMII_RXD3 */ -+ , /* ETH_RGMII_RX_CLK */ -+ ; /* ETH_RGMII_RX_CTL */ -+ }; -+ }; -+ -+ m4_fmc_pins_a: m4-fmc-0 { -+ pins { -+ pinmux = , /* FMC_NOE */ -+ , /* FMC_NWE */ -+ , /* FMC_A16_FMC_CLE */ -+ , /* FMC_A17_FMC_ALE */ -+ , /* FMC_D0 */ -+ , /* FMC_D1 */ -+ , /* FMC_D2 */ -+ , /* FMC_D3 */ -+ , /* FMC_D4 */ -+ , /* FMC_D5 */ -+ , /* FMC_D6 */ -+ , /* FMC_D7 */ -+ , /* FMC_NE2_FMC_NCE */ -+ ; /* FMC_NWAIT */ -+ }; -+ }; -+ -+ m4_hdp0_pins_a: m4-hdp0-0 { -+ pins { -+ pinmux = ; /* HDP0 */ -+ }; -+ }; -+ -+ m4_hdp6_pins_a: m4-hdp6-0 { -+ pins { -+ pinmux = ; /* HDP6 */ -+ }; -+ }; -+ -+ m4_hdp7_pins_a: m4-hdp7-0 { -+ pins { -+ pinmux = ; /* HDP7 */ -+ }; -+ }; -+ -+ m4_i2c1_pins_a: m4-i2c1-0 { -+ pins { -+ pinmux = , /* I2C1_SCL */ -+ ; /* I2C1_SDA */ -+ }; -+ }; -+ -+ m4_i2c2_pins_a: m4-i2c2-0 { -+ pins { -+ pinmux = , /* I2C2_SCL */ -+ ; /* I2C2_SDA */ -+ }; -+ }; -+ -+ m4_i2c5_pins_a: m4-i2c5-0 { -+ pins { -+ pinmux = , /* I2C5_SCL */ -+ ; /* I2C5_SDA */ -+ }; -+ }; -+ -+ m4_i2s2_pins_a: m4-i2s2-0 { -+ pins { -+ pinmux = , /* I2S2_SDO */ -+ , /* I2S2_WS */ -+ ; /* I2S2_CK */ -+ }; -+ }; -+ -+ m4_ltdc_pins_a: m4-ltdc-a-0 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ }; -+ }; -+ -+ m4_ltdc_pins_b: m4-ltdc-b-0 { -+ pins { -+ pinmux = , /* LCD_CLK */ -+ , /* LCD_HSYNC */ -+ , /* LCD_VSYNC */ -+ , /* LCD_DE */ -+ , /* LCD_R0 */ -+ , /* LCD_R1 */ -+ , /* LCD_R2 */ -+ , /* LCD_R3 */ -+ , /* LCD_R4 */ -+ , /* LCD_R5 */ -+ , /* LCD_R6 */ -+ , /* LCD_R7 */ -+ , /* LCD_G0 */ -+ , /* LCD_G1 */ -+ , /* LCD_G2 */ -+ , /* LCD_G3 */ -+ , /* LCD_G4 */ -+ , /* LCD_G5 */ -+ , /* LCD_G6 */ -+ , /* LCD_G7 */ -+ , /* LCD_B0 */ -+ , /* LCD_B1 */ -+ , /* LCD_B2 */ -+ , /* LCD_B3 */ -+ , /* LCD_B4 */ -+ , /* LCD_B5 */ -+ , /* LCD_B6 */ -+ ; /* LCD_B7 */ -+ }; -+ }; -+ -+ m4_m_can1_pins_a: m4-m-can1-0 { -+ pins { -+ pinmux = , /* CAN1_TX */ -+ ; /* CAN1_RX */ -+ }; -+ }; -+ -+ m4_pwm1_pins_a: m4-pwm1-0 { -+ pins { -+ pinmux = , /* TIM1_CH1 */ -+ , /* TIM1_CH2 */ -+ ; /* TIM1_CH4 */ -+ }; -+ }; -+ -+ m4_pwm2_pins_a: m4-pwm2-0 { -+ pins { -+ pinmux = ; /* TIM2_CH4 */ -+ }; -+ }; -+ -+ m4_pwm3_pins_a: m4-pwm3-0 { -+ pins { -+ pinmux = ; /* TIM3_CH2 */ -+ }; -+ }; -+ -+ m4_pwm4_pins_a: m4-pwm4-0 { -+ pins { -+ pinmux = , /* TIM4_CH3 */ -+ ; /* TIM4_CH4 */ -+ }; -+ }; -+ -+ m4_pwm4_pins_b: m4-pwm4-1 { -+ pins { -+ pinmux = ; /* TIM4_CH2 */ -+ }; -+ }; -+ -+ m4_pwm5_pins_a: m4-pwm5-0 { -+ pins { -+ pinmux = ; /* TIM5_CH2 */ -+ }; -+ }; -+ -+ m4_pwm8_pins_a: m4-pwm8-0 { -+ pins { -+ pinmux = ; /* TIM8_CH4 */ -+ }; -+ }; -+ -+ m4_pwm12_pins_a: m4-pwm12-0 { -+ pins { -+ pinmux = ; /* TIM12_CH1 */ -+ }; -+ }; -+ -+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 { -+ pins { -+ pinmux = , /* QSPI_BK1_IO0 */ -+ , /* QSPI_BK1_IO1 */ -+ , /* QSPI_BK1_IO2 */ -+ , /* QSPI_BK1_IO3 */ -+ ; /* QSPI_BK1_NCS */ -+ }; -+ }; -+ -+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 { -+ pins { -+ pinmux = , /* QSPI_BK2_IO0 */ -+ , /* QSPI_BK2_IO1 */ -+ , /* QSPI_BK2_IO2 */ -+ , /* QSPI_BK2_IO3 */ -+ ; /* QSPI_BK2_NCS */ -+ }; -+ }; -+ -+ m4_qspi_clk_pins_a: m4-qspi-clk-0 { -+ pins { -+ pinmux = ; /* QSPI_CLK */ -+ }; -+ }; -+ -+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 { -+ pins { -+ pinmux = ; /* RTC_OUT2_RMP */ -+ }; -+ }; -+ -+ m4_sai2a_pins_a: m4-sai2a-0 { -+ pins { -+ pinmux = , /* SAI2_SCK_A */ -+ , /* SAI2_SD_A */ -+ , /* SAI2_FS_A */ -+ ; /* SAI2_MCLK_A */ -+ }; -+ }; -+ -+ m4_sai2b_pins_a: m4-sai2b-0 { -+ pins { -+ pinmux = , /* SAI2_SCK_B */ -+ , /* SAI2_FS_B */ -+ , /* SAI2_MCLK_B */ -+ ; /* SAI2_SD_B */ -+ }; -+ }; -+ -+ m4_sai2b_pins_b: m4-sai2b-2 { -+ pins { -+ pinmux = ; /* SAI2_SD_B */ -+ }; -+ }; -+ -+ m4_sai4a_pins_a: m4-sai4a-0 { -+ pins { -+ pinmux = ; /* SAI4_SD_A */ -+ }; -+ }; -+ -+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 { -+ pins { -+ pinmux = , /* SDMMC1_D0 */ -+ , /* SDMMC1_D1 */ -+ , /* SDMMC1_D2 */ -+ , /* SDMMC1_D3 */ -+ , /* SDMMC1_CMD */ -+ ; /* SDMMC1_CK */ -+ }; -+ }; -+ -+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 { -+ pins { -+ pinmux = , /* SDMMC1_D0DIR */ -+ , /* SDMMC1_D123DIR */ -+ , /* SDMMC1_CDIR */ -+ ; /* SDMMC1_CKIN */ -+ }; -+ }; -+ -+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 { -+ pins { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ , /* SDMMC2_D3 */ -+ , /* SDMMC2_CMD */ -+ ; /* SDMMC2_CK */ -+ }; -+ }; -+ -+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 { -+ pins { -+ pinmux = , /* SDMMC2_D0 */ -+ , /* SDMMC2_D1 */ -+ , /* SDMMC2_D2 */ -+ , /* SDMMC2_D3 */ -+ , /* SDMMC2_CMD */ -+ ; /* SDMMC2_CK */ -+ }; -+ }; -+ -+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 { -+ pins { -+ pinmux = , /* SDMMC2_D4 */ -+ , /* SDMMC2_D5 */ -+ , /* SDMMC2_D6 */ -+ ; /* SDMMC2_D7 */ -+ }; -+ }; -+ -+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 { -+ pins { -+ pinmux = , /* SDMMC3_D0 */ -+ , /* SDMMC3_D1 */ -+ , /* SDMMC3_D2 */ -+ , /* SDMMC3_D3 */ -+ , /* SDMMC3_CMD */ -+ ; /* SDMMC3_CK */ -+ }; -+ }; -+ -+ m4_spdifrx_pins_a: m4-spdifrx-0 { -+ pins { -+ pinmux = ; /* SPDIF_IN1 */ -+ }; -+ }; -+ -+ m4_spi4_pins_a: m4-spi4-0 { -+ pins { -+ pinmux = , /* SPI4_SCK */ -+ , /* SPI4_MOSI */ -+ ; /* SPI4_MISO */ -+ }; -+ }; -+ -+ m4_spi5_pins_a: m4-spi5-0 { -+ pins { -+ pinmux = , /* SPI5_SCK */ -+ , /* SPI5_MOSI */ -+ ; /* SPI5_MISO */ -+ }; -+ }; -+ -+ m4_stusb1600_pins_a: m4-stusb1600-0 { -+ pins { -+ pinmux = ; -+ }; -+ }; -+ -+ m4_uart4_pins_a: m4-uart4-0 { -+ pins { -+ pinmux = , /* UART4_TX */ -+ ; /* UART4_RX */ -+ }; -+ }; -+ -+ m4_uart7_pins_a: m4-uart7-0 { -+ pins { -+ pinmux = , /* USART7_TX */ -+ ; /* USART7_RX */ -+ }; -+ }; -+ -+ m4_usart2_pins_a: m4-usart2-0 { -+ pins { -+ pinmux = , /* USART2_TX */ -+ , /* USART2_RTS */ -+ , /* USART2_RX */ -+ ; /* USART2_CTS_NSS */ -+ }; -+ }; -+ -+ m4_usart3_pins_a: m4-usart3-0 { -+ pins { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ , /* USART3_RX */ -+ ; /* USART3_CTS_NSS */ -+ }; -+ }; -+ -+ m4_usart3_pins_b: m4-usart3-1 { -+ pins { -+ pinmux = , /* USART3_TX */ -+ , /* USART3_RTS */ -+ , /* USART3_RX */ -+ ; /* USART3_CTS_NSS */ -+ }; -+ }; -+ -+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 { -+ pins { -+ pinmux = ; /* OTG_ID */ -+ }; -+ }; -+ -+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 { -+ pins { -+ pinmux = , /* OTG_FS_DM */ -+ ; /* OTG_FS_DP */ -+ }; -+ }; -+}; -+ -+&pinctrl_z { -+ m4_i2c4_pins_a: m4-i2c4-0 { -+ pins { -+ pinmux = , /* I2C4_SCL */ -+ ; /* I2C4_SDA */ -+ }; -+ }; -+ -+ m4_spi1_pins_a: m4-spi1-0 { -+ pins { -+ pinmux = , /* SPI1_SCK */ -+ , /* SPI1_MOSI */ -+ ; /* SPI1_MISO */ -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp157-m4-srm.dtsi b/arch/arm/dts/stm32mp157-m4-srm.dtsi -new file mode 100644 -index 0000000..60454ae ---- /dev/null -+++ b/arch/arm/dts/stm32mp157-m4-srm.dtsi -@@ -0,0 +1,442 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Fabien Dessenne for STMicroelectronics. -+ */ -+ -+&m4_rproc { -+ m4_system_resources { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ m4_timers2: timer@40000000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40000000 0x400>; -+ clocks = <&rcc TIM2_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers3: timer@40001000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40001000 0x400>; -+ clocks = <&rcc TIM3_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers4: timer@40002000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40002000 0x400>; -+ clocks = <&rcc TIM4_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers5: timer@40003000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40003000 0x400>; -+ clocks = <&rcc TIM5_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers6: timer@40004000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40004000 0x400>; -+ clocks = <&rcc TIM6_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers7: timer@40005000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40005000 0x400>; -+ clocks = <&rcc TIM7_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers12: timer@40006000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40006000 0x400>; -+ clocks = <&rcc TIM12_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers13: timer@40007000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40007000 0x400>; -+ clocks = <&rcc TIM13_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers14: timer@40008000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40008000 0x400>; -+ clocks = <&rcc TIM14_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_lptimer1: timer@40009000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40009000 0x400>; -+ clocks = <&rcc LPTIM1_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ }; -+ m4_spi2: spi@4000b000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000b000 0x400>; -+ clocks = <&rcc SPI2_K>; -+ status = "disabled"; -+ }; -+ m4_i2s2: audio-controller@4000b000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000b000 0x400>; -+ status = "disabled"; -+ }; -+ m4_spi3: spi@4000c000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000c000 0x400>; -+ clocks = <&rcc SPI3_K>; -+ status = "disabled"; -+ }; -+ m4_i2s3: audio-controller@4000c000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000c000 0x400>; -+ status = "disabled"; -+ }; -+ m4_spdifrx: audio-controller@4000d000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000d000 0x400>; -+ clocks = <&rcc SPDIF_K>; -+ clock-names = "kclk"; -+ status = "disabled"; -+ }; -+ m4_usart2: serial@4000e000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000e000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <27 1>; -+ clocks = <&rcc USART2_K>; -+ status = "disabled"; -+ }; -+ m4_usart3: serial@4000f000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4000f000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <28 1>; -+ clocks = <&rcc USART3_K>; -+ status = "disabled"; -+ }; -+ m4_uart4: serial@40010000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40010000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <30 1>; -+ clocks = <&rcc UART4_K>; -+ status = "disabled"; -+ }; -+ m4_uart5: serial@40011000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40011000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <31 1>; -+ clocks = <&rcc UART5_K>; -+ status = "disabled"; -+ }; -+ m4_i2c1: i2c@40012000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40012000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <21 1>; -+ clocks = <&rcc I2C1_K>; -+ status = "disabled"; -+ }; -+ m4_i2c2: i2c@40013000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40013000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <22 1>; -+ clocks = <&rcc I2C2_K>; -+ status = "disabled"; -+ }; -+ m4_i2c3: i2c@40014000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40014000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <23 1>; -+ clocks = <&rcc I2C3_K>; -+ status = "disabled"; -+ }; -+ m4_i2c5: i2c@40015000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40015000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <25 1>; -+ clocks = <&rcc I2C5_K>; -+ status = "disabled"; -+ }; -+ m4_cec: cec@40016000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40016000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <69 1>; -+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; -+ clock-names = "cec", "hdmi-cec"; -+ status = "disabled"; -+ }; -+ m4_dac: dac@40017000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40017000 0x400>; -+ clocks = <&rcc DAC12>; -+ clock-names = "pclk"; -+ status = "disabled"; -+ }; -+ m4_uart7: serial@40018000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40018000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <32 1>; -+ clocks = <&rcc UART7_K>; -+ status = "disabled"; -+ }; -+ m4_uart8: serial@40019000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x40019000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <33 1>; -+ clocks = <&rcc UART8_K>; -+ status = "disabled"; -+ }; -+ m4_timers1: timer@44000000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44000000 0x400>; -+ clocks = <&rcc TIM1_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers8: timer@44001000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44001000 0x400>; -+ clocks = <&rcc TIM8_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_usart6: serial@44003000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44003000 0x400>; -+ interrupt-parent = <&exti>; -+ interrupts = <29 1>; -+ clocks = <&rcc USART6_K>; -+ status = "disabled"; -+ }; -+ m4_spi1: spi@44004000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44004000 0x400>; -+ clocks = <&rcc SPI1_K>; -+ status = "disabled"; -+ }; -+ m4_i2s1: audio-controller@44004000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44004000 0x400>; -+ status = "disabled"; -+ }; -+ m4_spi4: spi@44005000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44005000 0x400>; -+ clocks = <&rcc SPI4_K>; -+ status = "disabled"; -+ }; -+ m4_timers15: timer@44006000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44006000 0x400>; -+ clocks = <&rcc TIM15_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers16: timer@44007000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44007000 0x400>; -+ clocks = <&rcc TIM16_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_timers17: timer@44008000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44008000 0x400>; -+ clocks = <&rcc TIM17_K>; -+ clock-names = "int"; -+ status = "disabled"; -+ }; -+ m4_spi5: spi@44009000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x44009000 0x400>; -+ clocks = <&rcc SPI5_K>; -+ status = "disabled"; -+ }; -+ m4_sai1: sai@4400a000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400a000 0x4>; -+ clocks = <&rcc SAI1_K>; -+ clock-names = "sai_ck"; -+ status = "disabled"; -+ }; -+ m4_sai2: sai@4400b000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400b000 0x4>; -+ clocks = <&rcc SAI2_K>; -+ clock-names = "sai_ck"; -+ status = "disabled"; -+ }; -+ m4_sai3: sai@4400c000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400c000 0x4>; -+ clocks = <&rcc SAI3_K>; -+ clock-names = "sai_ck"; -+ status = "disabled"; -+ }; -+ m4_dfsdm: dfsdm@4400d000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400d000 0x800>; -+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; -+ clock-names = "dfsdm", "audio"; -+ status = "disabled"; -+ }; -+ m4_m_can1: can@4400e000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>; -+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; -+ clock-names = "hclk", "cclk"; -+ status = "disabled"; -+ }; -+ m4_m_can2: can@4400f000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>; -+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; -+ clock-names = "hclk", "cclk"; -+ status = "disabled"; -+ }; -+ m4_dma1: dma@48000000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x48000000 0x400>; -+ clocks = <&rcc DMA1>; -+ status = "disabled"; -+ }; -+ m4_dma2: dma@48001000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x48001000 0x400>; -+ clocks = <&rcc DMA2>; -+ status = "disabled"; -+ }; -+ m4_dmamux1: dma-router@48002000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x48002000 0x1c>; -+ clocks = <&rcc DMAMUX>; -+ status = "disabled"; -+ }; -+ m4_adc: adc@48003000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x48003000 0x400>; -+ clocks = <&rcc ADC12>, <&rcc ADC12_K>; -+ clock-names = "bus", "adc"; -+ status = "disabled"; -+ }; -+ m4_sdmmc3: sdmmc@48004000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x48004000 0x400>, <0x48005000 0x400>; -+ clocks = <&rcc SDMMC3_K>; -+ status = "disabled"; -+ }; -+ m4_usbotg_hs: usb-otg@49000000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x49000000 0x10000>; -+ clocks = <&rcc USBO_K>; -+ clock-names = "otg"; -+ status = "disabled"; -+ }; -+ m4_hash2: hash@4c002000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4c002000 0x400>; -+ clocks = <&rcc HASH2>; -+ status = "disabled"; -+ }; -+ m4_rng2: rng@4c003000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4c003000 0x400>; -+ clocks = <&rcc RNG2_K>; -+ status = "disabled"; -+ }; -+ m4_crc2: crc@4c004000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4c004000 0x400>; -+ clocks = <&rcc CRC2>; -+ status = "disabled"; -+ }; -+ m4_cryp2: cryp@4c005000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4c005000 0x400>; -+ clocks = <&rcc CRYP2>; -+ status = "disabled"; -+ }; -+ m4_dcmi: dcmi@4c006000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x4c006000 0x400>; -+ clocks = <&rcc DCMI>; -+ clock-names = "mclk"; -+ status = "disabled"; -+ }; -+ m4_lptimer2: timer@50021000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x50021000 0x400>; -+ clocks = <&rcc LPTIM2_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ }; -+ m4_lptimer3: timer@50022000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x50022000 0x400>; -+ clocks = <&rcc LPTIM3_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ }; -+ m4_lptimer4: timer@50023000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x50023000 0x400>; -+ clocks = <&rcc LPTIM4_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ }; -+ m4_lptimer5: timer@50024000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x50024000 0x400>; -+ clocks = <&rcc LPTIM5_K>; -+ clock-names = "mux"; -+ status = "disabled"; -+ }; -+ m4_sai4: sai@50027000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x50027000 0x4>; -+ clocks = <&rcc SAI4_K>; -+ clock-names = "sai_ck"; -+ status = "disabled"; -+ }; -+ m4_qspi: qspi@58003000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; -+ clocks = <&rcc QSPI_K>; -+ status = "disabled"; -+ }; -+ m4_ethernet0: ethernet@5800a000 { -+ compatible = "rproc-srm-dev"; -+ reg = <0x5800a000 0x2000>; -+ clock-names = "stmmaceth", -+ "mac-clk-tx", -+ "mac-clk-rx", -+ "ethstp", -+ "syscfg-clk"; -+ clocks = <&rcc ETHMAC>, -+ <&rcc ETHTX>, -+ <&rcc ETHRX>, -+ <&rcc ETHSTP>, -+ <&rcc SYSCFG>; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi -deleted file mode 100644 -index 0d53396..0000000 ---- a/arch/arm/dts/stm32mp157-pinctrl.dtsi -+++ /dev/null -@@ -1,1036 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -- * Author: Ludovic Barre for STMicroelectronics. -- */ --#include -- --/ { -- soc { -- pinctrl: pin-controller@50002000 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,stm32mp157-pinctrl"; -- ranges = <0 0x50002000 0xa400>; -- interrupt-parent = <&exti>; -- st,syscfg = <&exti 0x60 0xff>; -- hwlocks = <&hwspinlock 0>; -- pins-are-numbered; -- -- gpioa: gpio@50002000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x0 0x400>; -- clocks = <&rcc GPIOA>; -- st,bank-name = "GPIOA"; -- status = "disabled"; -- }; -- -- gpiob: gpio@50003000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x1000 0x400>; -- clocks = <&rcc GPIOB>; -- st,bank-name = "GPIOB"; -- status = "disabled"; -- }; -- -- gpioc: gpio@50004000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x2000 0x400>; -- clocks = <&rcc GPIOC>; -- st,bank-name = "GPIOC"; -- status = "disabled"; -- }; -- -- gpiod: gpio@50005000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x3000 0x400>; -- clocks = <&rcc GPIOD>; -- st,bank-name = "GPIOD"; -- status = "disabled"; -- }; -- -- gpioe: gpio@50006000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x4000 0x400>; -- clocks = <&rcc GPIOE>; -- st,bank-name = "GPIOE"; -- status = "disabled"; -- }; -- -- gpiof: gpio@50007000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x5000 0x400>; -- clocks = <&rcc GPIOF>; -- st,bank-name = "GPIOF"; -- status = "disabled"; -- }; -- -- gpiog: gpio@50008000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x6000 0x400>; -- clocks = <&rcc GPIOG>; -- st,bank-name = "GPIOG"; -- status = "disabled"; -- }; -- -- gpioh: gpio@50009000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x7000 0x400>; -- clocks = <&rcc GPIOH>; -- st,bank-name = "GPIOH"; -- status = "disabled"; -- }; -- -- gpioi: gpio@5000a000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x8000 0x400>; -- clocks = <&rcc GPIOI>; -- st,bank-name = "GPIOI"; -- status = "disabled"; -- }; -- -- gpioj: gpio@5000b000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x9000 0x400>; -- clocks = <&rcc GPIOJ>; -- st,bank-name = "GPIOJ"; -- status = "disabled"; -- }; -- -- gpiok: gpio@5000c000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0xa000 0x400>; -- clocks = <&rcc GPIOK>; -- st,bank-name = "GPIOK"; -- status = "disabled"; -- }; -- -- adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 { -- pins { -- pinmux = , /* ADC12 in18 */ -- ; /* ADC12 in19 */ -- }; -- }; -- -- cec_pins_a: cec-0 { -- pins { -- pinmux = ; -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- cec_pins_sleep_a: cec-sleep-0 { -- pins { -- pinmux = ; /* HDMI_CEC */ -- }; -- }; -- -- cec_pins_b: cec-1 { -- pins { -- pinmux = ; -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- cec_pins_sleep_b: cec-sleep-1 { -- pins { -- pinmux = ; /* HDMI_CEC */ -- }; -- }; -- -- dcmi_pins_a: dcmi-0 { -- pins { -- pinmux = ,/* DCMI_HSYNC */ -- ,/* DCMI_VSYNC */ -- ,/* DCMI_PIXCLK */ -- ,/* DCMI_D0 */ -- ,/* DCMI_D1 */ -- ,/* DCMI_D2 */ -- ,/* DCMI_D3 */ -- ,/* DCMI_D4 */ -- ,/* DCMI_D5 */ -- ,/* DCMI_D6 */ -- ,/* DCMI_D7 */ -- ,/* DCMI_D8 */ -- ,/* DCMI_D9 */ -- ,/* DCMI_D10 */ -- ;/* DCMI_D11 */ -- bias-disable; -- }; -- }; -- -- dcmi_sleep_pins_a: dcmi-sleep-0 { -- pins { -- pinmux = ,/* DCMI_HSYNC */ -- ,/* DCMI_VSYNC */ -- ,/* DCMI_PIXCLK */ -- ,/* DCMI_D0 */ -- ,/* DCMI_D1 */ -- ,/* DCMI_D2 */ -- ,/* DCMI_D3 */ -- ,/* DCMI_D4 */ -- ,/* DCMI_D5 */ -- ,/* DCMI_D6 */ -- ,/* DCMI_D7 */ -- ,/* DCMI_D8 */ -- ,/* DCMI_D9 */ -- ,/* DCMI_D10 */ -- ;/* DCMI_D11 */ -- }; -- }; -- -- ethernet0_rgmii_pins_a: rgmii-0 { -- pins1 { -- pinmux = , /* ETH_RGMII_CLK125 */ -- , /* ETH_RGMII_GTX_CLK */ -- , /* ETH_RGMII_TXD0 */ -- , /* ETH_RGMII_TXD1 */ -- , /* ETH_RGMII_TXD2 */ -- , /* ETH_RGMII_TXD3 */ -- , /* ETH_RGMII_TX_CTL */ -- ; /* ETH_MDC */ -- bias-disable; -- drive-push-pull; -- slew-rate = <2>; -- }; -- pins2 { -- pinmux = ; /* ETH_MDIO */ -- bias-disable; -- drive-push-pull; -- slew-rate = <0>; -- }; -- pins3 { -- pinmux = , /* ETH_RGMII_RXD0 */ -- , /* ETH_RGMII_RXD1 */ -- , /* ETH_RGMII_RXD2 */ -- , /* ETH_RGMII_RXD3 */ -- , /* ETH_RGMII_RX_CLK */ -- ; /* ETH_RGMII_RX_CTL */ -- bias-disable; -- }; -- }; -- -- ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { -- pins1 { -- pinmux = , /* ETH_RGMII_CLK125 */ -- , /* ETH_RGMII_GTX_CLK */ -- , /* ETH_RGMII_TXD0 */ -- , /* ETH_RGMII_TXD1 */ -- , /* ETH_RGMII_TXD2 */ -- , /* ETH_RGMII_TXD3 */ -- , /* ETH_RGMII_TX_CTL */ -- , /* ETH_MDIO */ -- , /* ETH_MDC */ -- , /* ETH_RGMII_RXD0 */ -- , /* ETH_RGMII_RXD1 */ -- , /* ETH_RGMII_RXD2 */ -- , /* ETH_RGMII_RXD3 */ -- , /* ETH_RGMII_RX_CLK */ -- ; /* ETH_RGMII_RX_CTL */ -- }; -- }; -- -- fmc_pins_a: fmc-0 { -- pins1 { -- pinmux = , /* FMC_NOE */ -- , /* FMC_NWE */ -- , /* FMC_A16_FMC_CLE */ -- , /* FMC_A17_FMC_ALE */ -- , /* FMC_D0 */ -- , /* FMC_D1 */ -- , /* FMC_D2 */ -- , /* FMC_D3 */ -- , /* FMC_D4 */ -- , /* FMC_D5 */ -- , /* FMC_D6 */ -- , /* FMC_D7 */ -- ; /* FMC_NE2_FMC_NCE */ -- bias-disable; -- drive-push-pull; -- slew-rate = <1>; -- }; -- pins2 { -- pinmux = ; /* FMC_NWAIT */ -- bias-pull-up; -- }; -- }; -- -- fmc_sleep_pins_a: fmc-sleep-0 { -- pins { -- pinmux = , /* FMC_NOE */ -- , /* FMC_NWE */ -- , /* FMC_A16_FMC_CLE */ -- , /* FMC_A17_FMC_ALE */ -- , /* FMC_D0 */ -- , /* FMC_D1 */ -- , /* FMC_D2 */ -- , /* FMC_D3 */ -- , /* FMC_D4 */ -- , /* FMC_D5 */ -- , /* FMC_D6 */ -- , /* FMC_D7 */ -- , /* FMC_NWAIT */ -- ; /* FMC_NE2_FMC_NCE */ -- }; -- }; -- -- i2c1_pins_a: i2c1-0 { -- pins { -- pinmux = , /* I2C1_SCL */ -- ; /* I2C1_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c1_pins_sleep_a: i2c1-1 { -- pins { -- pinmux = , /* I2C1_SCL */ -- ; /* I2C1_SDA */ -- }; -- }; -- -- i2c1_pins_b: i2c1-2 { -- pins { -- pinmux = , /* I2C1_SCL */ -- ; /* I2C1_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c1_pins_sleep_b: i2c1-3 { -- pins { -- pinmux = , /* I2C1_SCL */ -- ; /* I2C1_SDA */ -- }; -- }; -- -- i2c2_pins_a: i2c2-0 { -- pins { -- pinmux = , /* I2C2_SCL */ -- ; /* I2C2_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c2_pins_sleep_a: i2c2-1 { -- pins { -- pinmux = , /* I2C2_SCL */ -- ; /* I2C2_SDA */ -- }; -- }; -- -- i2c2_pins_b1: i2c2-2 { -- pins { -- pinmux = ; /* I2C2_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c2_pins_sleep_b1: i2c2-3 { -- pins { -- pinmux = ; /* I2C2_SDA */ -- }; -- }; -- -- i2c5_pins_a: i2c5-0 { -- pins { -- pinmux = , /* I2C5_SCL */ -- ; /* I2C5_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c5_pins_sleep_a: i2c5-1 { -- pins { -- pinmux = , /* I2C5_SCL */ -- ; /* I2C5_SDA */ -- -- }; -- }; -- -- i2s2_pins_a: i2s2-0 { -- pins { -- pinmux = , /* I2S2_SDO */ -- , /* I2S2_WS */ -- ; /* I2S2_CK */ -- slew-rate = <1>; -- drive-push-pull; -- bias-disable; -- }; -- }; -- -- i2s2_pins_sleep_a: i2s2-1 { -- pins { -- pinmux = , /* I2S2_SDO */ -- , /* I2S2_WS */ -- ; /* I2S2_CK */ -- }; -- }; -- -- ltdc_pins_a: ltdc-a-0 { -- pins { -- pinmux = , /* LCD_CLK */ -- , /* LCD_HSYNC */ -- , /* LCD_VSYNC */ -- , /* LCD_DE */ -- , /* LCD_R0 */ -- , /* LCD_R1 */ -- , /* LCD_R2 */ -- , /* LCD_R3 */ -- , /* LCD_R4 */ -- , /* LCD_R5 */ -- , /* LCD_R6 */ -- , /* LCD_R7 */ -- , /* LCD_G0 */ -- , /* LCD_G1 */ -- , /* LCD_G2 */ -- , /* LCD_G3 */ -- , /* LCD_G4 */ -- , /* LCD_G5 */ -- , /* LCD_G6 */ -- , /* LCD_G7 */ -- , /* LCD_B0 */ -- , /* LCD_B1 */ -- , /* LCD_B2 */ -- , /* LCD_B3 */ -- , /* LCD_B4 */ -- , /* LCD_B5 */ -- , /* LCD_B6 */ -- ; /* LCD_B7 */ -- bias-disable; -- drive-push-pull; -- slew-rate = <1>; -- }; -- }; -- -- ltdc_pins_sleep_a: ltdc-a-1 { -- pins { -- pinmux = , /* LCD_CLK */ -- , /* LCD_HSYNC */ -- , /* LCD_VSYNC */ -- , /* LCD_DE */ -- , /* LCD_R0 */ -- , /* LCD_R1 */ -- , /* LCD_R2 */ -- , /* LCD_R3 */ -- , /* LCD_R4 */ -- , /* LCD_R5 */ -- , /* LCD_R6 */ -- , /* LCD_R7 */ -- , /* LCD_G0 */ -- , /* LCD_G1 */ -- , /* LCD_G2 */ -- , /* LCD_G3 */ -- , /* LCD_G4 */ -- , /* LCD_G5 */ -- , /* LCD_G6 */ -- , /* LCD_G7 */ -- , /* LCD_B0 */ -- , /* LCD_B1 */ -- , /* LCD_B2 */ -- , /* LCD_B3 */ -- , /* LCD_B4 */ -- , /* LCD_B5 */ -- , /* LCD_B6 */ -- ; /* LCD_B7 */ -- }; -- }; -- -- ltdc_pins_b: ltdc-b-0 { -- pins { -- pinmux = , /* LCD_CLK */ -- , /* LCD_HSYNC */ -- , /* LCD_VSYNC */ -- , /* LCD_DE */ -- , /* LCD_R0 */ -- , /* LCD_R1 */ -- , /* LCD_R2 */ -- , /* LCD_R3 */ -- , /* LCD_R4 */ -- , /* LCD_R5 */ -- , /* LCD_R6 */ -- , /* LCD_R7 */ -- , /* LCD_G0 */ -- , /* LCD_G1 */ -- , /* LCD_G2 */ -- , /* LCD_G3 */ -- , /* LCD_G4 */ -- , /* LCD_G5 */ -- , /* LCD_G6 */ -- , /* LCD_G7 */ -- , /* LCD_B0 */ -- , /* LCD_B1 */ -- , /* LCD_B2 */ -- , /* LCD_B3 */ -- , /* LCD_B4 */ -- , /* LCD_B5 */ -- , /* LCD_B6 */ -- ; /* LCD_B7 */ -- bias-disable; -- drive-push-pull; -- slew-rate = <1>; -- }; -- }; -- -- ltdc_pins_sleep_b: ltdc-b-1 { -- pins { -- pinmux = , /* LCD_CLK */ -- , /* LCD_HSYNC */ -- , /* LCD_VSYNC */ -- , /* LCD_DE */ -- , /* LCD_R0 */ -- , /* LCD_R1 */ -- , /* LCD_R2 */ -- , /* LCD_R3 */ -- , /* LCD_R4 */ -- , /* LCD_R5 */ -- , /* LCD_R6 */ -- , /* LCD_R7 */ -- , /* LCD_G0 */ -- , /* LCD_G1 */ -- , /* LCD_G2 */ -- , /* LCD_G3 */ -- , /* LCD_G4 */ -- , /* LCD_G5 */ -- , /* LCD_G6 */ -- , /* LCD_G7 */ -- , /* LCD_B0 */ -- , /* LCD_B1 */ -- , /* LCD_B2 */ -- , /* LCD_B3 */ -- , /* LCD_B4 */ -- , /* LCD_B5 */ -- , /* LCD_B6 */ -- ; /* LCD_B7 */ -- }; -- }; -- -- m_can1_pins_a: m-can1-0 { -- pins1 { -- pinmux = ; /* CAN1_TX */ -- slew-rate = <1>; -- drive-push-pull; -- bias-disable; -- }; -- pins2 { -- pinmux = ; /* CAN1_RX */ -- bias-disable; -- }; -- }; -- -- m_can1_sleep_pins_a: m_can1-sleep-0 { -- pins { -- pinmux = , /* CAN1_TX */ -- ; /* CAN1_RX */ -- }; -- }; -- -- pwm2_pins_a: pwm2-0 { -- pins { -- pinmux = ; /* TIM2_CH4 */ -- bias-pull-down; -- drive-push-pull; -- slew-rate = <0>; -- }; -- }; -- -- pwm8_pins_a: pwm8-0 { -- pins { -- pinmux = ; /* TIM8_CH4 */ -- bias-pull-down; -- drive-push-pull; -- slew-rate = <0>; -- }; -- }; -- -- pwm12_pins_a: pwm12-0 { -- pins { -- pinmux = ; /* TIM12_CH1 */ -- bias-pull-down; -- drive-push-pull; -- slew-rate = <0>; -- }; -- }; -- -- qspi_clk_pins_a: qspi-clk-0 { -- pins { -- pinmux = ; /* QSPI_CLK */ -- bias-disable; -- drive-push-pull; -- slew-rate = <3>; -- }; -- }; -- -- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { -- pins { -- pinmux = ; /* QSPI_CLK */ -- }; -- }; -- -- qspi_bk1_pins_a: qspi-bk1-0 { -- pins1 { -- pinmux = , /* QSPI_BK1_IO0 */ -- , /* QSPI_BK1_IO1 */ -- , /* QSPI_BK1_IO2 */ -- ; /* QSPI_BK1_IO3 */ -- bias-disable; -- drive-push-pull; -- slew-rate = <3>; -- }; -- pins2 { -- pinmux = ; /* QSPI_BK1_NCS */ -- bias-pull-up; -- drive-push-pull; -- slew-rate = <3>; -- }; -- }; -- -- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { -- pins { -- pinmux = , /* QSPI_BK1_IO0 */ -- , /* QSPI_BK1_IO1 */ -- , /* QSPI_BK1_IO2 */ -- , /* QSPI_BK1_IO3 */ -- ; /* QSPI_BK1_NCS */ -- }; -- }; -- -- qspi_bk2_pins_a: qspi-bk2-0 { -- pins1 { -- pinmux = , /* QSPI_BK2_IO0 */ -- , /* QSPI_BK2_IO1 */ -- , /* QSPI_BK2_IO2 */ -- ; /* QSPI_BK2_IO3 */ -- bias-disable; -- drive-push-pull; -- slew-rate = <3>; -- }; -- pins2 { -- pinmux = ; /* QSPI_BK2_NCS */ -- bias-pull-up; -- drive-push-pull; -- slew-rate = <3>; -- }; -- }; -- -- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { -- pins { -- pinmux = , /* QSPI_BK2_IO0 */ -- , /* QSPI_BK2_IO1 */ -- , /* QSPI_BK2_IO2 */ -- , /* QSPI_BK2_IO3 */ -- ; /* QSPI_BK2_NCS */ -- }; -- }; -- -- sai2a_pins_a: sai2a-0 { -- pins { -- pinmux = , /* SAI2_SCK_A */ -- , /* SAI2_SD_A */ -- , /* SAI2_FS_A */ -- ; /* SAI2_MCLK_A */ -- slew-rate = <0>; -- drive-push-pull; -- bias-disable; -- }; -- }; -- -- sai2a_sleep_pins_a: sai2a-1 { -- pins { -- pinmux = , /* SAI2_SCK_A */ -- , /* SAI2_SD_A */ -- , /* SAI2_FS_A */ -- ; /* SAI2_MCLK_A */ -- }; -- }; -- -- sai2b_pins_a: sai2b-0 { -- pins1 { -- pinmux = , /* SAI2_SCK_B */ -- , /* SAI2_FS_B */ -- ; /* SAI2_MCLK_B */ -- slew-rate = <0>; -- drive-push-pull; -- bias-disable; -- }; -- pins2 { -- pinmux = ; /* SAI2_SD_B */ -- bias-disable; -- }; -- }; -- -- sai2b_sleep_pins_a: sai2b-1 { -- pins { -- pinmux = , /* SAI2_SD_B */ -- , /* SAI2_SCK_B */ -- , /* SAI2_FS_B */ -- ; /* SAI2_MCLK_B */ -- }; -- }; -- -- sai2b_pins_b: sai2b-2 { -- pins { -- pinmux = ; /* SAI2_SD_B */ -- bias-disable; -- }; -- }; -- -- sai2b_sleep_pins_b: sai2b-3 { -- pins { -- pinmux = ; /* SAI2_SD_B */ -- }; -- }; -- -- sai4a_pins_a: sai4a-0 { -- pins { -- pinmux = ; /* SAI4_SD_A */ -- slew-rate = <0>; -- drive-push-pull; -- bias-disable; -- }; -- }; -- -- sai4a_sleep_pins_a: sai4a-1 { -- pins { -- pinmux = ; /* SAI4_SD_A */ -- }; -- }; -- -- sdmmc1_b4_pins_a: sdmmc1-b4-0 { -- pins { -- pinmux = , /* SDMMC1_D0 */ -- , /* SDMMC1_D1 */ -- , /* SDMMC1_D2 */ -- , /* SDMMC1_D3 */ -- , /* SDMMC1_CK */ -- ; /* SDMMC1_CMD */ -- slew-rate = <3>; -- drive-push-pull; -- bias-disable; -- }; -- }; -- -- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { -- pins1 { -- pinmux = , /* SDMMC1_D0 */ -- , /* SDMMC1_D1 */ -- , /* SDMMC1_D2 */ -- , /* SDMMC1_D3 */ -- ; /* SDMMC1_CK */ -- slew-rate = <3>; -- drive-push-pull; -- bias-disable; -- }; -- pins2{ -- pinmux = ; /* SDMMC1_CMD */ -- slew-rate = <3>; -- drive-open-drain; -- bias-disable; -- }; -- }; -- -- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { -- pins { -- pinmux = , /* SDMMC1_D0 */ -- , /* SDMMC1_D1 */ -- , /* SDMMC1_D2 */ -- , /* SDMMC1_D3 */ -- , /* SDMMC1_CK */ -- ; /* SDMMC1_CMD */ -- }; -- }; -- -- sdmmc1_dir_pins_a: sdmmc1-dir-0 { -- pins1 { -- pinmux = , /* SDMMC1_D0DIR */ -- , /* SDMMC1_D123DIR */ -- ; /* SDMMC1_CDIR */ -- slew-rate = <3>; -- drive-push-pull; -- bias-pull-up; -- }; -- pins2{ -- pinmux = ; /* SDMMC1_CKIN */ -- bias-pull-up; -- }; -- }; -- -- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { -- pins { -- pinmux = , /* SDMMC1_D0DIR */ -- , /* SDMMC1_D123DIR */ -- , /* SDMMC1_CDIR */ -- ; /* SDMMC1_CKIN */ -- }; -- }; -- -- sdmmc2_b4_pins_a: sdmmc2-b4-0 { -- pins1 { -- pinmux = , /* SDMMC2_D0 */ -- , /* SDMMC2_D1 */ -- , /* SDMMC2_D2 */ -- , /* SDMMC2_D3 */ -- ; /* SDMMC2_CMD */ -- slew-rate = <1>; -- drive-push-pull; -- bias-pull-up; -- }; -- pins2 { -- pinmux = ; /* SDMMC2_CK */ -- slew-rate = <2>; -- drive-push-pull; -- bias-pull-up; -- }; -- }; -- -- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { -- pins1 { -- pinmux = , /* SDMMC2_D0 */ -- , /* SDMMC2_D1 */ -- , /* SDMMC2_D2 */ -- ; /* SDMMC2_D3 */ -- slew-rate = <1>; -- drive-push-pull; -- bias-pull-up; -- }; -- pins2 { -- pinmux = ; /* SDMMC2_CK */ -- slew-rate = <2>; -- drive-push-pull; -- bias-pull-up; -- }; -- pins3 { -- pinmux = ; /* SDMMC2_CMD */ -- slew-rate = <1>; -- drive-open-drain; -- bias-pull-up; -- }; -- }; -- -- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { -- pins { -- pinmux = , /* SDMMC2_D0 */ -- , /* SDMMC2_D1 */ -- , /* SDMMC2_D2 */ -- , /* SDMMC2_D3 */ -- , /* SDMMC2_CK */ -- ; /* SDMMC2_CMD */ -- }; -- }; -- -- sdmmc2_d47_pins_a: sdmmc2-d47-0 { -- pins { -- pinmux = , /* SDMMC2_D4 */ -- , /* SDMMC2_D5 */ -- , /* SDMMC2_D6 */ -- ; /* SDMMC2_D7 */ -- slew-rate = <1>; -- drive-push-pull; -- bias-pull-up; -- }; -- }; -- -- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { -- pins { -- pinmux = , /* SDMMC2_D4 */ -- , /* SDMMC2_D5 */ -- , /* SDMMC2_D6 */ -- ; /* SDMMC2_D7 */ -- }; -- }; -- -- spdifrx_pins_a: spdifrx-0 { -- pins { -- pinmux = ; /* SPDIF_IN1 */ -- bias-disable; -- }; -- }; -- -- spdifrx_sleep_pins_a: spdifrx-1 { -- pins { -- pinmux = ; /* SPDIF_IN1 */ -- }; -- }; -- -- spi2_pins_a: spi2-0 { -- pins1 { -- pinmux = , /* SPI2_SCK */ -- , /* SPI2_NSS */ -- ; /* SPI2_MOSI */ -- bias-disable; -- drive-push-pull; -- slew-rate = <3>; -- }; -- pins2 { -- pinmux = ; /* SPI2_MISO */ -- bias-disable; -- }; -- }; -- -- stusb1600_pins_a: stusb1600-0 { -- pins { -- pinmux = ; -- bias-pull-up; -- }; -- }; -- -- uart4_pins_a: uart4-0 { -- pins1 { -- pinmux = ; /* UART4_TX */ -- bias-disable; -- drive-push-pull; -- slew-rate = <0>; -- }; -- pins2 { -- pinmux = ; /* UART4_RX */ -- bias-disable; -- }; -- }; -- -- uart4_pins_b: uart4-1 { -- pins1 { -- pinmux = ; /* UART4_TX */ -- bias-disable; -- drive-push-pull; -- slew-rate = <0>; -- }; -- pins2 { -- pinmux = ; /* UART4_RX */ -- bias-disable; -- }; -- }; -- -- uart7_pins_a: uart7-0 { -- pins1 { -- pinmux = ; /* UART4_TX */ -- bias-disable; -- drive-push-pull; -- slew-rate = <0>; -- }; -- pins2 { -- pinmux = , /* UART4_RX */ -- , /* UART4_CTS */ -- ; /* UART4_RTS */ -- bias-disable; -- }; -- }; -- }; -- -- pinctrl_z: pin-controller-z@54004000 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,stm32mp157-z-pinctrl"; -- ranges = <0 0x54004000 0x400>; -- pins-are-numbered; -- interrupt-parent = <&exti>; -- st,syscfg = <&exti 0x60 0xff>; -- hwlocks = <&hwspinlock 0>; -- -- gpioz: gpio@54004000 { -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0 0x400>; -- clocks = <&rcc GPIOZ>; -- st,bank-name = "GPIOZ"; -- st,bank-ioport = <11>; -- status = "disabled"; -- }; -- -- i2c2_pins_b2: i2c2-0 { -- pins { -- pinmux = ; /* I2C2_SCL */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c2_pins_sleep_b2: i2c2-1 { -- pins { -- pinmux = ; /* I2C2_SCL */ -- }; -- }; -- -- i2c4_pins_a: i2c4-0 { -- pins { -- pinmux = , /* I2C4_SCL */ -- ; /* I2C4_SDA */ -- bias-disable; -- drive-open-drain; -- slew-rate = <0>; -- }; -- }; -- -- i2c4_pins_sleep_a: i2c4-1 { -- pins { -- pinmux = , /* I2C4_SCL */ -- ; /* I2C4_SDA */ -- }; -- }; -- -- spi1_pins_a: spi1-0 { -- pins1 { -- pinmux = , /* SPI1_SCK */ -- ; /* SPI1_MOSI */ -- bias-disable; -- drive-push-pull; -- slew-rate = <1>; -- }; -- -- pins2 { -- pinmux = ; /* SPI1_MISO */ -- bias-disable; -- }; -- }; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi -deleted file mode 100644 -index 0d1d387..0000000 ---- a/arch/arm/dts/stm32mp157-u-boot.dtsi -+++ /dev/null -@@ -1,153 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause --/* -- * Copyright : STMicroelectronics 2018 -- */ -- --/ { -- aliases { -- gpio0 = &gpioa; -- gpio1 = &gpiob; -- gpio2 = &gpioc; -- gpio3 = &gpiod; -- gpio4 = &gpioe; -- gpio5 = &gpiof; -- gpio6 = &gpiog; -- gpio7 = &gpioh; -- gpio8 = &gpioi; -- gpio9 = &gpioj; -- gpio10 = &gpiok; -- gpio25 = &gpioz; -- pinctrl0 = &pinctrl; -- pinctrl1 = &pinctrl_z; -- }; -- -- clocks { -- u-boot,dm-pre-reloc; -- }; -- -- /* need PSCI for sysreset during board_f */ -- psci { -- u-boot,dm-pre-proper; -- }; -- -- reboot { -- u-boot,dm-pre-reloc; -- }; -- -- soc { -- u-boot,dm-pre-reloc; -- }; --}; -- --&bsec { -- u-boot,dm-pre-proper; --}; -- --&clk_csi { -- u-boot,dm-pre-reloc; --}; -- --&clk_hsi { -- u-boot,dm-pre-reloc; --}; -- --&clk_hse { -- u-boot,dm-pre-reloc; --}; -- --&clk_lsi { -- u-boot,dm-pre-reloc; --}; -- --&clk_lse { -- u-boot,dm-pre-reloc; --}; -- --&gpioa { -- u-boot,dm-pre-reloc; --}; -- --&gpiob { -- u-boot,dm-pre-reloc; --}; -- --&gpioc { -- u-boot,dm-pre-reloc; --}; -- --&gpiod { -- u-boot,dm-pre-reloc; --}; -- --&gpioe { -- u-boot,dm-pre-reloc; --}; -- --&gpiof { -- u-boot,dm-pre-reloc; --}; -- --&gpiog { -- u-boot,dm-pre-reloc; --}; -- --&gpioh { -- u-boot,dm-pre-reloc; --}; -- --&gpioi { -- u-boot,dm-pre-reloc; --}; -- --&gpioj { -- u-boot,dm-pre-reloc; --}; -- --&gpiok { -- u-boot,dm-pre-reloc; --}; -- --&gpioz { -- u-boot,dm-pre-reloc; --}; -- --&iwdg2 { -- u-boot,dm-pre-reloc; --}; -- --/* pre-reloc probe = reserve video frame buffer in video_reserve() */ --<dc { -- u-boot,dm-pre-proper; --}; -- --&pinctrl { -- u-boot,dm-pre-reloc; --}; -- --&pinctrl_z { -- u-boot,dm-pre-reloc; --}; -- --&pwr { -- u-boot,dm-pre-reloc; --}; -- --&rcc { -- u-boot,dm-pre-reloc; --}; -- --&sdmmc1 { -- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; --}; -- --&sdmmc2 { -- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; --}; -- --&sdmmc3 { -- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; --}; -- --&usbotg_hs { -- compatible = "st,stm32mp1-hsotg", "snps,dwc2"; --}; -diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi -new file mode 100644 -index 0000000..ce1d83a ---- /dev/null -+++ b/arch/arm/dts/stm32mp157.dtsi -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+#include "stm32mp153.dtsi" -+ -+/ { -+ soc { -+ gpu: gpu@59000000 { -+ compatible = "vivante,gc"; -+ reg = <0x59000000 0x800>; -+ interrupts = ; -+ clocks = <&rcc GPU>, <&rcc GPU_K>; -+ clock-names = "bus" ,"core"; -+ resets = <&rcc GPU_R>; -+ status = "disabled"; -+ }; -+ -+ dsi: dsi@5a000000 { -+ compatible = "st,stm32-dsi"; -+ reg = <0x5a000000 0x800>; -+ phy-dsi-supply = <®18>; -+ clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; -+ clock-names = "pclk", "ref", "px_clk"; -+ resets = <&rcc DSI_R>; -+ reset-names = "apb"; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi -index 1104a70..e885b6d 100644 ---- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi -@@ -7,7 +7,7 @@ - */ - - #include --#include "stm32mp157-u-boot.dtsi" -+#include "stm32mp15-u-boot.dtsi" - #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" - - / { -@@ -20,6 +20,7 @@ - config { - u-boot,boot-led = "led1"; - u-boot,error-led = "led4"; -+ u-boot,mmc-env-partition = "ssbl"; - }; - }; - -@@ -91,7 +92,7 @@ - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P -- CLK_FDCAN_PLL4Q -+ CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q -@@ -103,15 +104,10 @@ - CLK_LPTIM45_LSE - >; - -- /* VCO = 1300.0 MHz => P = 650 (CPU) */ -- pll1: st,pll@0 { -- cfg = < 2 80 0 0 0 PQR(1,0,0) >; -- frac = < 0x800 >; -- u-boot,dm-pre-reloc; -- }; -- - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; -@@ -119,6 +115,8 @@ - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; -@@ -126,6 +124,8 @@ - - /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ - pll4: st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; - cfg = < 1 39 3 11 4 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -@@ -137,14 +137,20 @@ - - &sdmmc1_b4_pins_a { - u-boot,dm-spl; -- pins { -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { - u-boot,dm-spl; - }; - }; - - &sdmmc1_dir_pins_a { - u-boot,dm-spl; -- pins { -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { - u-boot,dm-spl; - }; - }; -@@ -188,7 +194,3 @@ - u-boot,force-b-session-valid; - hnp-srp-disable; - }; -- --&v3v3 { -- regulator-always-on; --}; -diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts -index 5b15a4a..941963c 100644 ---- a/arch/arm/dts/stm32mp157a-avenger96.dts -+++ b/arch/arm/dts/stm32mp157a-avenger96.dts -@@ -6,9 +6,10 @@ - - /dts-v1/; - --#include "stm32mp157c.dtsi" --#include "stm32mp157xac-pinctrl.dtsi" --#include -+#include "stm32mp157.dtsi" -+#include "stm32mp15xa.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxac-pinctrl.dtsi" - #include - - / { -@@ -252,14 +253,13 @@ - regulator-name = "vbus_otg"; - interrupts = ; - interrupt-parent = <&pmic>; -- regulator-active-discharge; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - interrupt-parent = <&pmic>; -- regulator-active-discharge; -+ regulator-active-discharge = <1>; - }; - }; - -@@ -282,11 +282,9 @@ - status = "okay"; - }; - --&pwr { -- pwr-regulators { -- vdd-supply = <&vdd>; -- vdd_3v3_usbfs-supply = <&vdd_usb>; -- }; -+&pwr_regulators { -+ vdd-supply = <&vdd>; -+ vdd_3v3_usbfs-supply = <&vdd_usb>; - }; - - &rng1 { -@@ -302,7 +300,7 @@ - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; -- broken-cd; -+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,sig-dir; - st,neg-edge; - st,use-ckin; -diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -index dcaab3e..62d7062 100644 ---- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -@@ -4,7 +4,7 @@ - */ - - #include --#include "stm32mp157-u-boot.dtsi" -+#include "stm32mp15-u-boot.dtsi" - #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" - - / { -@@ -16,6 +16,7 @@ - config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; -+ u-boot,mmc-env-partition = "ssbl"; - st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; -@@ -27,34 +28,14 @@ - default-state = "off"; - status = "okay"; - }; -- -- blue { -- default-state = "on"; -- }; - }; - }; - - &adc { -- pinctrl-names = "default"; -- pinctrl-0 = <&adc12_usb_pwr_pins_a>; -- vdd-supply = <&vdd>; -- vdda-supply = <&vdd>; -- vref-supply = <&vrefbuf>; - status = "okay"; -- adc1: adc@0 { -- /* -- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. -- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: -- * 5 * (56 + 47kOhms) * 5pF => 2.5us. -- * Use arbitrary margin here (e.g. 5µs). -- */ -- st,min-sample-time-nsecs = <5000>; -- /* ANA0, ANA1, USB Type-C CC1 & CC2 */ -- st,adc-channels = <0 1 18 19>; -- status = "okay"; -- }; - }; - -+#ifndef CONFIG_STM32MP1_TRUSTED - &clk_hse { - st,digbypass; - }; -@@ -70,6 +51,10 @@ - }; - }; - -+&i2s2 { -+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+}; -+ - &pmic { - u-boot,dm-pre-reloc; - }; -@@ -127,7 +112,7 @@ - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P -- CLK_FDCAN_PLL4Q -+ CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q -@@ -139,15 +124,10 @@ - CLK_LPTIM45_LSE - >; - -- /* VCO = 1300.0 MHz => P = 650 (CPU) */ -- pll1: st,pll@0 { -- cfg = < 2 80 0 0 0 PQR(1,0,0) >; -- frac = < 0x800 >; -- u-boot,dm-pre-reloc; -- }; -- - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; -@@ -155,6 +135,8 @@ - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; -@@ -162,21 +144,31 @@ - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; - }; - -+&sai2 { -+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+}; -+ - &sdmmc1 { - u-boot,dm-spl; - }; - - &sdmmc1_b4_pins_a { - u-boot,dm-spl; -- pins { -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { - u-boot,dm-spl; - }; - }; -+#endif - - &uart4 { - u-boot,dm-pre-reloc; -@@ -197,4 +189,6 @@ - &usbotg_hs { - u-boot,force-b-session-valid; - hnp-srp-disable; -+ /* TEMP: force peripheral for USB OTG */ -+ dr_mode = "peripheral"; - }; -diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts -index 4652253..baff3f6 100644 ---- a/arch/arm/dts/stm32mp157a-dk1.dts -+++ b/arch/arm/dts/stm32mp157a-dk1.dts -@@ -6,11 +6,11 @@ - - /dts-v1/; - --#include "stm32mp157c.dtsi" --#include "stm32mp157xac-pinctrl.dtsi" --#include --#include -- -+#include "stm32mp157.dtsi" -+#include "stm32mp15xa.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxac-pinctrl.dtsi" -+#include "stm32mp15xx-dkx.dtsi" - / { - model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; - compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; -@@ -18,491 +18,27 @@ - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; -+ serial1 = &usart3; -+ serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - -- memory@c0000000 { -- reg = <0xc0000000 0x20000000>; -- }; -- - reserved-memory { -- #address-cells = <1>; -- #size-cells = <1>; -- ranges; -- -- mcuram2: mcuram2@10000000 { -- compatible = "shared-dma-pool"; -- reg = <0x10000000 0x40000>; -- no-map; -- }; -- -- vdev0vring0: vdev0vring0@10040000 { -- compatible = "shared-dma-pool"; -- reg = <0x10040000 0x1000>; -- no-map; -- }; -- -- vdev0vring1: vdev0vring1@10041000 { -- compatible = "shared-dma-pool"; -- reg = <0x10041000 0x1000>; -- no-map; -- }; -- -- vdev0buffer: vdev0buffer@10042000 { -- compatible = "shared-dma-pool"; -- reg = <0x10042000 0x4000>; -- no-map; -- }; -- -- mcuram: mcuram@30000000 { -- compatible = "shared-dma-pool"; -- reg = <0x30000000 0x40000>; -- no-map; -- }; -- -- retram: retram@38000000 { -- compatible = "shared-dma-pool"; -- reg = <0x38000000 0x10000>; -+ gpu_reserved: gpu@da000000 { -+ reg = <0xda000000 0x4000000>; - no-map; - }; - -- gpu_reserved: gpu@d4000000 { -- reg = <0xd4000000 0x4000000>; -+ optee_memory: optee@0xde000000 { -+ reg = <0xde000000 0x02000000>; - no-map; - }; - }; -- -- led { -- compatible = "gpio-leds"; -- blue { -- label = "heartbeat"; -- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; -- default-state = "off"; -- }; -- }; -- -- sound { -- compatible = "audio-graph-card"; -- label = "STM32MP1-DK"; -- routing = -- "Playback" , "MCLK", -- "Capture" , "MCLK", -- "MICL" , "Mic Bias"; -- dais = <&sai2a_port &sai2b_port>; -- status = "okay"; -- }; --}; -- --&cec { -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&cec_pins_b>; -- pinctrl-1 = <&cec_pins_sleep_b>; -- status = "okay"; --}; -- --ðernet0 { -- status = "okay"; -- pinctrl-0 = <ðernet0_rgmii_pins_a>; -- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; -- pinctrl-names = "default", "sleep"; -- phy-mode = "rgmii-id"; -- max-speed = <1000>; -- phy-handle = <&phy0>; -- -- mdio0 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "snps,dwmac-mdio"; -- phy0: ethernet-phy@0 { -- reg = <0>; -- }; -- }; --}; -- --&gpu { -- contiguous-area = <&gpu_reserved>; -- status = "okay"; --}; -- --&i2c1 { -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&i2c1_pins_a>; -- pinctrl-1 = <&i2c1_pins_sleep_a>; -- i2c-scl-rising-time-ns = <100>; -- i2c-scl-falling-time-ns = <7>; -- status = "okay"; -- /delete-property/dmas; -- /delete-property/dma-names; -- -- hdmi-transmitter@39 { -- compatible = "sil,sii9022"; -- reg = <0x39>; -- iovcc-supply = <&v3v3_hdmi>; -- cvcc12-supply = <&v1v2_hdmi>; -- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; -- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -- interrupt-parent = <&gpiog>; -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <<dc_pins_a>; -- pinctrl-1 = <<dc_pins_sleep_a>; -- status = "okay"; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- sii9022_in: endpoint { -- remote-endpoint = <<dc_ep0_out>; -- }; -- }; -- }; -- }; -- -- cs42l51: cs42l51@4a { -- compatible = "cirrus,cs42l51"; -- reg = <0x4a>; -- #sound-dai-cells = <0>; -- VL-supply = <&v3v3>; -- VD-supply = <&v1v8_audio>; -- VA-supply = <&v1v8_audio>; -- VAHP-supply = <&v1v8_audio>; -- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; -- clocks = <&sai2a>; -- clock-names = "MCLK"; -- status = "okay"; -- -- cs42l51_port: port { -- #address-cells = <1>; -- #size-cells = <0>; -- -- cs42l51_tx_endpoint: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&sai2a_endpoint>; -- frame-master; -- bitclock-master; -- }; -- -- cs42l51_rx_endpoint: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&sai2b_endpoint>; -- frame-master; -- bitclock-master; -- }; -- }; -- }; --}; -- --&i2c4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c4_pins_a>; -- i2c-scl-rising-time-ns = <185>; -- i2c-scl-falling-time-ns = <20>; -- status = "okay"; -- /* spare dmas for other usage */ -- /delete-property/dmas; -- /delete-property/dma-names; -- -- typec: stusb1600@28 { -- compatible = "st,stusb1600"; -- reg = <0x28>; -- interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -- interrupt-parent = <&gpioi>; -- pinctrl-names = "default"; -- pinctrl-0 = <&stusb1600_pins_a>; -- -- status = "okay"; -- -- typec_con: connector { -- compatible = "usb-c-connector"; -- label = "USB-C"; -- power-role = "sink"; -- power-opmode = "default"; -- }; -- }; -- -- pmic: stpmic@33 { -- compatible = "st,stpmic1"; -- reg = <0x33>; -- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; -- interrupt-controller; -- #interrupt-cells = <2>; -- status = "okay"; -- -- regulators { -- compatible = "st,stpmic1-regulators"; -- ldo1-supply = <&v3v3>; -- ldo3-supply = <&vdd_ddr>; -- ldo6-supply = <&v3v3>; -- pwr_sw1-supply = <&bst_out>; -- pwr_sw2-supply = <&bst_out>; -- -- vddcore: buck1 { -- regulator-name = "vddcore"; -- regulator-min-microvolt = <800000>; -- regulator-max-microvolt = <1350000>; -- regulator-always-on; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- vdd_ddr: buck2 { -- regulator-name = "vdd_ddr"; -- regulator-min-microvolt = <1350000>; -- regulator-max-microvolt = <1350000>; -- regulator-always-on; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- vdd: buck3 { -- regulator-name = "vdd"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-always-on; -- st,mask-reset; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- v3v3: buck4 { -- regulator-name = "v3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-always-on; -- regulator-over-current-protection; -- regulator-initial-mode = <0>; -- }; -- -- v1v8_audio: ldo1 { -- regulator-name = "v1v8_audio"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-always-on; -- interrupts = ; -- }; -- -- v3v3_hdmi: ldo2 { -- regulator-name = "v3v3_hdmi"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-always-on; -- interrupts = ; -- }; -- -- vtt_ddr: ldo3 { -- regulator-name = "vtt_ddr"; -- regulator-min-microvolt = <500000>; -- regulator-max-microvolt = <750000>; -- regulator-always-on; -- regulator-over-current-protection; -- }; -- -- vdd_usb: ldo4 { -- regulator-name = "vdd_usb"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- interrupts = ; -- }; -- -- vdda: ldo5 { -- regulator-name = "vdda"; -- regulator-min-microvolt = <2900000>; -- regulator-max-microvolt = <2900000>; -- interrupts = ; -- regulator-boot-on; -- }; -- -- v1v2_hdmi: ldo6 { -- regulator-name = "v1v2_hdmi"; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-always-on; -- interrupts = ; -- }; -- -- vref_ddr: vref_ddr { -- regulator-name = "vref_ddr"; -- regulator-always-on; -- regulator-over-current-protection; -- }; -- -- bst_out: boost { -- regulator-name = "bst_out"; -- interrupts = ; -- }; -- -- vbus_otg: pwr_sw1 { -- regulator-name = "vbus_otg"; -- interrupts = ; -- }; -- -- vbus_sw: pwr_sw2 { -- regulator-name = "vbus_sw"; -- interrupts = ; -- regulator-active-discharge; -- }; -- }; -- -- onkey { -- compatible = "st,stpmic1-onkey"; -- interrupts = , ; -- interrupt-names = "onkey-falling", "onkey-rising"; -- power-off-time-sec = <10>; -- status = "okay"; -- }; -- -- watchdog { -- compatible = "st,stpmic1-wdt"; -- status = "disabled"; -- }; -- }; --}; -- --&ipcc { -- status = "okay"; --}; -- --&iwdg2 { -- timeout-sec = <32>; -- status = "okay"; --}; -- --<dc { -- status = "okay"; -- -- port { -- #address-cells = <1>; -- #size-cells = <0>; -- -- ltdc_ep0_out: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&sii9022_in>; -- }; -- }; --}; -- --&m4_rproc { -- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, -- <&vdev0vring1>, <&vdev0buffer>; -- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; -- mbox-names = "vq0", "vq1", "shutdown"; -- interrupt-parent = <&exti>; -- interrupts = <68 1>; -- status = "okay"; --}; -- --&pwr { -- pwr-regulators { -- vdd-supply = <&vdd>; -- vdd_3v3_usbfs-supply = <&vdd_usb>; -- }; --}; -- --&rng1 { -- status = "okay"; --}; -- --&rtc { -- status = "okay"; --}; -- --&sai2 { -- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -- clock-names = "pclk", "x8k", "x11k"; -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; -- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; -- status = "okay"; -- -- sai2a: audio-controller@4400b004 { -- #clock-cells = <0>; -- dma-names = "tx"; -- clocks = <&rcc SAI2_K>; -- clock-names = "sai_ck"; -- status = "okay"; -- -- sai2a_port: port { -- sai2a_endpoint: endpoint { -- remote-endpoint = <&cs42l51_tx_endpoint>; -- format = "i2s"; -- mclk-fs = <256>; -- dai-tdm-slot-num = <2>; -- dai-tdm-slot-width = <32>; -- }; -- }; -- }; -- -- sai2b: audio-controller@4400b024 { -- dma-names = "rx"; -- st,sync = <&sai2a 2>; -- clocks = <&rcc SAI2_K>, <&sai2a>; -- clock-names = "sai_ck", "MCLK"; -- status = "okay"; -- -- sai2b_port: port { -- sai2b_endpoint: endpoint { -- remote-endpoint = <&cs42l51_rx_endpoint>; -- format = "i2s"; -- mclk-fs = <256>; -- dai-tdm-slot-num = <2>; -- dai-tdm-slot-width = <32>; -- }; -- }; -- }; --}; -- --&sdmmc1 { -- pinctrl-names = "default", "opendrain", "sleep"; -- pinctrl-0 = <&sdmmc1_b4_pins_a>; -- pinctrl-1 = <&sdmmc1_b4_od_pins_a>; -- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; -- broken-cd; -- st,neg-edge; -- bus-width = <4>; -- vmmc-supply = <&v3v3>; -- status = "okay"; --}; -- --&uart4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart4_pins_a>; -- status = "okay"; --}; -- --&usbh_ehci { -- phys = <&usbphyc_port0>; -- phy-names = "usb"; -- status = "okay"; --}; -- --&usbotg_hs { -- dr_mode = "peripheral"; -- phys = <&usbphyc_port1 0>; -- phy-names = "usb2-phy"; -- status = "okay"; --}; -- --&usbphyc { -- status = "okay"; --}; -- --&usbphyc_port0 { -- phy-supply = <&vdd_usb>; --}; -- --&usbphyc_port1 { -- phy-supply = <&vdd_usb>; - }; - --&vrefbuf { -- regulator-min-microvolt = <2500000>; -- regulator-max-microvolt = <2500000>; -- vdda-supply = <&vdd>; -+&optee { - status = "okay"; - }; -diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi -new file mode 100644 -index 0000000..0f163bc ---- /dev/null -+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2018 -+ */ -+ -+#include -+#include "stm32mp15-u-boot.dtsi" -+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" -+ -+/ { -+ aliases { -+ i2c3 = &i2c4; -+ mmc0 = &sdmmc1; -+ mmc1 = &sdmmc2; -+ }; -+ -+ config { -+ u-boot,boot-led = "heartbeat"; -+ u-boot,error-led = "error"; -+ u-boot,mmc-env-partition = "ssbl"; -+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led { -+ red { -+ label = "error"; -+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ status = "okay"; -+ }; -+ }; -+}; -+ -+#ifndef CONFIG_STM32MP1_TRUSTED -+&clk_hse { -+ st,digbypass; -+}; -+ -+&i2c4 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&i2c4_pins_a { -+ u-boot,dm-pre-reloc; -+ pins { -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&pmic { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rcc { -+ st,clksrc = < -+ CLK_MPU_PLL1P -+ CLK_AXI_PLL2P -+ CLK_MCU_PLL3P -+ CLK_PLL12_HSE -+ CLK_PLL3_HSE -+ CLK_PLL4_HSE -+ CLK_RTC_LSE -+ CLK_MCO1_DISABLED -+ CLK_MCO2_DISABLED -+ >; -+ -+ st,clkdiv = < -+ 1 /*MPU*/ -+ 0 /*AXI*/ -+ 0 /*MCU*/ -+ 1 /*APB1*/ -+ 1 /*APB2*/ -+ 1 /*APB3*/ -+ 1 /*APB4*/ -+ 2 /*APB5*/ -+ 23 /*RTC*/ -+ 0 /*MCO1*/ -+ 0 /*MCO2*/ -+ >; -+ -+ st,pkcs = < -+ CLK_CKPER_HSE -+ CLK_FMC_ACLK -+ CLK_QSPI_ACLK -+ CLK_ETH_DISABLED -+ CLK_SDMMC12_PLL4P -+ CLK_DSI_DSIPLL -+ CLK_STGEN_HSE -+ CLK_USBPHY_HSE -+ CLK_SPI2S1_PLL3Q -+ CLK_SPI2S23_PLL3Q -+ CLK_SPI45_HSI -+ CLK_SPI6_HSI -+ CLK_I2C46_HSI -+ CLK_SDMMC3_PLL4P -+ CLK_USBO_USBPHY -+ CLK_ADC_CKPER -+ CLK_CEC_LSE -+ CLK_I2C12_HSI -+ CLK_I2C35_HSI -+ CLK_UART1_HSI -+ CLK_UART24_HSI -+ CLK_UART35_HSI -+ CLK_UART6_HSI -+ CLK_UART78_HSI -+ CLK_SPDIF_PLL4P -+ CLK_FDCAN_PLL4R -+ CLK_SAI1_PLL3Q -+ CLK_SAI2_PLL3Q -+ CLK_SAI3_PLL3Q -+ CLK_SAI4_PLL3Q -+ CLK_RNG1_LSI -+ CLK_RNG2_LSI -+ CLK_LPTIM1_PCLK1 -+ CLK_LPTIM23_PCLK3 -+ CLK_LPTIM45_LSE -+ >; -+ -+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ -+ pll2: st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; -+ cfg = < 2 65 1 0 0 PQR(1,1,1) >; -+ frac = < 0x1400 >; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ -+ pll3: st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; -+ cfg = < 1 33 1 16 36 PQR(1,1,1) >; -+ frac = < 0x1a04 >; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ -+ pll4: st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; -+ cfg = < 3 98 5 7 7 PQR(1,1,1) >; -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&sdmmc1 { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc1_b4_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc1_dir_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc2 { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc2_b4_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc2_d47_pins_a { -+ u-boot,dm-spl; -+ pins { -+ u-boot,dm-spl; -+ }; -+}; -+#endif -+ -+&uart4 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&uart4_pins_a { -+ u-boot,dm-pre-reloc; -+ pins1 { -+ u-boot,dm-pre-reloc; -+ }; -+ pins2 { -+ u-boot,dm-pre-reloc; -+ /* pull-up on rx to avoid floating level */ -+ bias-pull-up; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts -new file mode 100644 -index 0000000..5dca956 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157a-ed1.dts -@@ -0,0 +1,52 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xa.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxaa-pinctrl.dtsi" -+#include "stm32mp157-m4-srm.dtsi" -+#include "stm32mp157-m4-srm-pinctrl.dtsi" -+#include "stm32mp15xx-edx.dtsi" -+ -+/ { -+ model = "STMicroelectronics STM32MP157A eval daughter"; -+ compatible = "st,stm32mp157a-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial0 = &uart4; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@f6000000 { -+ reg = <0xf6000000 0x8000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@fe000000 { -+ reg = <0xfe000000 0x02000000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&cpu1{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&gpu { -+ contiguous-area = <&gpu_reserved>; -+ status = "okay"; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi -new file mode 100644 -index 0000000..f634c4c ---- /dev/null -+++ b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2018 -+ */ -+ -+#include "stm32mp157c-ed1-u-boot.dtsi" -+ -+/ { -+ aliases { -+ gpio26 = &stmfx_pinctrl; -+ i2c1 = &i2c2; -+ i2c4 = &i2c5; -+ pinctrl2 = &stmfx_pinctrl; -+ spi0 = &qspi; -+ usb0 = &usbotg_hs; -+ }; -+}; -+ -+#ifndef CONFIG_STM32MP1_TRUSTED -+&flash0 { -+ u-boot,dm-spl; -+}; -+ -+&qspi { -+ u-boot,dm-spl; -+}; -+ -+&qspi_clk_pins_a { -+ u-boot,dm-spl; -+ pins { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&qspi_bk1_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&qspi_bk2_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sai2 { -+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+}; -+ -+&sai4 { -+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+}; -+ -+#endif -+ -+/* TEMP: force peripheral for USB OTG */ -+&usbotg_hs { -+ dr_mode = "peripheral"; -+}; -+ -diff --git a/arch/arm/dts/stm32mp157a-ev1.dts b/arch/arm/dts/stm32mp157a-ev1.dts -new file mode 100644 -index 0000000..29ecd15 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157a-ev1.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157a-ed1.dts" -+#include "stm32mp15xx-evx.dtsi" -+#include -+#include -+ -+/ { -+ model = "STMicroelectronics STM32MP157A eval daughter on eval mother"; -+ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial1 = &usart3; -+ ethernet0 = ðernet0; -+ }; -+}; -+ -+&dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ dsi_in: endpoint { -+ remote-endpoint = <<dc_ep0_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ dsi_out: endpoint { -+ remote-endpoint = <&dsi_panel_in>; -+ }; -+ }; -+ }; -+ -+ panel_dsi: panel-dsi@0 { -+ compatible = "raydium,rm68200"; -+ reg = <0>; -+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; -+ backlight = <&panel_backlight>; -+ power-supply = <&v3v3>; -+ status = "okay"; -+ -+ port { -+ dsi_panel_in: endpoint { -+ remote-endpoint = <&dsi_out>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ gt9147: goodix_ts@5d { -+ compatible = "goodix,gt9147"; -+ reg = <0x5d>; -+ panel = <&panel_dsi>; -+ pinctrl-0 = <&goodix_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ interrupts = <14 IRQ_TYPE_EDGE_RISING>; -+ interrupt-parent = <&stmfx_pinctrl>; -+ }; -+}; -+ -+&m_can1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&m_can1_pins_a>; -+ pinctrl-1 = <&m_can1_sleep_pins_a>; -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi -index 18ac1e3..06ef3a4 100644 ---- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi -@@ -4,9 +4,3 @@ - */ - - #include "stm32mp157a-dk1-u-boot.dtsi" -- --&i2c1 { -- hdmi-transmitter@39 { -- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts -index 020ea0f..a7d5e86 100644 ---- a/arch/arm/dts/stm32mp157c-dk2.dts -+++ b/arch/arm/dts/stm32mp157c-dk2.dts -@@ -6,18 +6,55 @@ - - /dts-v1/; - --#include "stm32mp157a-dk1.dts" -+#include "stm32mp157.dtsi" -+#include "stm32mp15xc.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxac-pinctrl.dtsi" -+#include "stm32mp15xx-dkx.dtsi" -+#include - - / { - model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; - compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; -+ -+ aliases { -+ ethernet0 = ðernet0; -+ serial0 = &uart4; -+ serial1 = &usart3; -+ serial2 = &uart7; -+ serial3 = &usart2; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@da000000 { -+ reg = <0xda000000 0x4000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@0xde000000 { -+ reg = <0xde000000 0x02000000>; -+ no-map; -+ }; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cryp1 { -+ status="okay"; - }; - - &dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; -- phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; -@@ -38,7 +75,7 @@ - }; - }; - -- panel@0 { -+ panel_otm8009a: panel-otm8009a@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; - reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; -@@ -53,6 +90,31 @@ - }; - }; - -+&i2c1 { -+ touchscreen@2a { -+ compatible = "focaltech,ft6236"; -+ reg = <0x2a>; -+ interrupts = <2 2>; -+ interrupt-parent = <&gpiof>; -+ interrupt-controller; -+ touchscreen-size-x = <480>; -+ touchscreen-size-y = <800>; -+ panel = <&panel_otm8009a>; -+ status = "okay"; -+ }; -+ touchscreen@38 { -+ compatible = "focaltech,ft6236"; -+ reg = <0x38>; -+ interrupts = <2 2>; -+ interrupt-parent = <&gpiof>; -+ interrupt-controller; -+ touchscreen-size-x = <480>; -+ touchscreen-size-y = <800>; -+ panel = <&panel_otm8009a>; -+ status = "okay"; -+ }; -+}; -+ - <dc { - status = "okay"; - -@@ -66,3 +128,57 @@ - }; - }; - }; -+ -+&rtc { -+ st,lsco = ; -+ pinctrl-0 = <&rtc_out2_rmp_pins_a>; -+ pinctrl-names = "default"; -+}; -+ -+/* Wifi */ -+&sdmmc2 { -+ arm,primecell-periphid = <0x10153180>; -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc2_b4_pins_a>; -+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; -+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; -+ non-removable; -+ st,neg-edge; -+ bus-width = <4>; -+ vmmc-supply = <&v3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ -+/* Bluetooth */ -+&usart2 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&usart2_pins_a>; -+ pinctrl-1 = <&usart2_sleep_pins_a>; -+ pinctrl-2 = <&usart2_idle_pins_a>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <3000000>; -+ vbat-supply = <&v3v3>; -+ vddio-supply = <&v3v3>; -+ }; -+}; -+ -+&optee_memory { -+ status = "okay"; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi -index b2ac494..44a689b 100644 ---- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi -@@ -3,204 +3,4 @@ - * Copyright : STMicroelectronics 2018 - */ - --#include --#include "stm32mp157-u-boot.dtsi" --#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" -- --/ { -- aliases { -- i2c3 = &i2c4; -- mmc0 = &sdmmc1; -- mmc1 = &sdmmc2; -- }; -- -- config { -- u-boot,boot-led = "heartbeat"; -- u-boot,error-led = "error"; -- st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -- st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; -- }; -- -- led { -- red { -- label = "error"; -- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -- default-state = "off"; -- status = "okay"; -- }; -- -- blue { -- default-state = "on"; -- }; -- }; --}; -- --&clk_hse { -- st,digbypass; --}; -- --&i2c4 { -- u-boot,dm-pre-reloc; --}; -- --&i2c4_pins_a { -- u-boot,dm-pre-reloc; -- pins { -- u-boot,dm-pre-reloc; -- }; --}; -- --&pmic { -- u-boot,dm-pre-reloc; --}; -- --&rcc { -- st,clksrc = < -- CLK_MPU_PLL1P -- CLK_AXI_PLL2P -- CLK_MCU_PLL3P -- CLK_PLL12_HSE -- CLK_PLL3_HSE -- CLK_PLL4_HSE -- CLK_RTC_LSE -- CLK_MCO1_DISABLED -- CLK_MCO2_DISABLED -- >; -- -- st,clkdiv = < -- 1 /*MPU*/ -- 0 /*AXI*/ -- 0 /*MCU*/ -- 1 /*APB1*/ -- 1 /*APB2*/ -- 1 /*APB3*/ -- 1 /*APB4*/ -- 2 /*APB5*/ -- 23 /*RTC*/ -- 0 /*MCO1*/ -- 0 /*MCO2*/ -- >; -- -- st,pkcs = < -- CLK_CKPER_HSE -- CLK_FMC_ACLK -- CLK_QSPI_ACLK -- CLK_ETH_DISABLED -- CLK_SDMMC12_PLL4P -- CLK_DSI_DSIPLL -- CLK_STGEN_HSE -- CLK_USBPHY_HSE -- CLK_SPI2S1_PLL3Q -- CLK_SPI2S23_PLL3Q -- CLK_SPI45_HSI -- CLK_SPI6_HSI -- CLK_I2C46_HSI -- CLK_SDMMC3_PLL4P -- CLK_USBO_USBPHY -- CLK_ADC_CKPER -- CLK_CEC_LSE -- CLK_I2C12_HSI -- CLK_I2C35_HSI -- CLK_UART1_HSI -- CLK_UART24_HSI -- CLK_UART35_HSI -- CLK_UART6_HSI -- CLK_UART78_HSI -- CLK_SPDIF_PLL4P -- CLK_FDCAN_PLL4Q -- CLK_SAI1_PLL3Q -- CLK_SAI2_PLL3Q -- CLK_SAI3_PLL3Q -- CLK_SAI4_PLL3Q -- CLK_RNG1_LSI -- CLK_RNG2_LSI -- CLK_LPTIM1_PCLK1 -- CLK_LPTIM23_PCLK3 -- CLK_LPTIM45_LSE -- >; -- -- /* VCO = 1300.0 MHz => P = 650 (CPU) */ -- pll1: st,pll@0 { -- cfg = < 2 80 0 0 0 PQR(1,0,0) >; -- frac = < 0x800 >; -- u-boot,dm-pre-reloc; -- }; -- -- /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ -- pll2: st,pll@1 { -- cfg = < 2 65 1 0 0 PQR(1,1,1) >; -- frac = < 0x1400 >; -- u-boot,dm-pre-reloc; -- }; -- -- /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ -- pll3: st,pll@2 { -- cfg = < 1 33 1 16 36 PQR(1,1,1) >; -- frac = < 0x1a04 >; -- u-boot,dm-pre-reloc; -- }; -- -- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ -- pll4: st,pll@3 { -- cfg = < 3 98 5 7 7 PQR(1,1,1) >; -- u-boot,dm-pre-reloc; -- }; --}; -- --&sdmmc1 { -- u-boot,dm-spl; --}; -- --&sdmmc1_b4_pins_a { -- u-boot,dm-spl; -- pins { -- u-boot,dm-spl; -- }; --}; -- --&sdmmc1_dir_pins_a { -- u-boot,dm-spl; -- pins1 { -- u-boot,dm-spl; -- }; -- pins2 { -- u-boot,dm-spl; -- }; --}; -- --&sdmmc2 { -- u-boot,dm-spl; --}; -- --&sdmmc2_b4_pins_a { -- u-boot,dm-spl; -- pins1 { -- u-boot,dm-spl; -- }; -- pins2 { -- u-boot,dm-spl; -- }; --}; -- --&sdmmc2_d47_pins_a { -- u-boot,dm-spl; -- pins { -- u-boot,dm-spl; -- }; --}; -- --&uart4 { -- u-boot,dm-pre-reloc; --}; -- --&uart4_pins_a { -- u-boot,dm-pre-reloc; -- pins1 { -- u-boot,dm-pre-reloc; -- }; -- pins2 { -- u-boot,dm-pre-reloc; -- /* pull-up on rx to avoid floating level */ -- bias-pull-up; -- }; --}; -+#include "stm32mp157a-ed1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts -index bc4d7e1..bf2d7e7 100644 ---- a/arch/arm/dts/stm32mp157c-ed1.dts -+++ b/arch/arm/dts/stm32mp157c-ed1.dts -@@ -1,14 +1,17 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) - /* -- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -- * Author: Ludovic Barre for STMicroelectronics. -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. - */ - /dts-v1/; - --#include "stm32mp157c.dtsi" --#include "stm32mp157xaa-pinctrl.dtsi" --#include --#include -+#include "stm32mp157.dtsi" -+#include "stm32mp15xc.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxaa-pinctrl.dtsi" -+#include "stm32mp157-m4-srm.dtsi" -+#include "stm32mp157-m4-srm-pinctrl.dtsi" -+#include "stm32mp15xx-edx.dtsi" - - / { - model = "STMicroelectronics STM32MP157C eval daughter"; -@@ -18,78 +21,29 @@ - stdout-path = "serial0:115200n8"; - }; - -- memory@c0000000 { -- device_type = "memory"; -- reg = <0xC0000000 0x40000000>; -+ aliases { -+ serial0 = &uart4; - }; - - reserved-memory { -- #address-cells = <1>; -- #size-cells = <1>; -- ranges; -- -- mcuram2: mcuram2@10000000 { -- compatible = "shared-dma-pool"; -- reg = <0x10000000 0x40000>; -- no-map; -- }; -- -- vdev0vring0: vdev0vring0@10040000 { -- compatible = "shared-dma-pool"; -- reg = <0x10040000 0x1000>; -- no-map; -- }; -- -- vdev0vring1: vdev0vring1@10041000 { -- compatible = "shared-dma-pool"; -- reg = <0x10041000 0x1000>; -- no-map; -- }; -- -- vdev0buffer: vdev0buffer@10042000 { -- compatible = "shared-dma-pool"; -- reg = <0x10042000 0x4000>; -- no-map; -- }; -- -- mcuram: mcuram@30000000 { -- compatible = "shared-dma-pool"; -- reg = <0x30000000 0x40000>; -+ gpu_reserved: gpu@f6000000 { -+ reg = <0xf6000000 0x8000000>; - no-map; - }; - -- retram: retram@38000000 { -- compatible = "shared-dma-pool"; -- reg = <0x38000000 0x10000>; -+ optee_memory: optee@fe000000 { -+ reg = <0xfe000000 0x02000000>; - no-map; - }; -- -- gpu_reserved: gpu@e8000000 { -- reg = <0xe8000000 0x8000000>; -- no-map; -- }; -- }; -- -- aliases { -- serial0 = &uart4; - }; -+}; - -- sd_switch: regulator-sd_switch { -- compatible = "regulator-gpio"; -- regulator-name = "sd_switch"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <2900000>; -- regulator-type = "voltage"; -- regulator-always-on; -- -- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; -- gpios-states = <0>; -- states = <1800000 0x1 2900000 0x0>; -- }; -+&cpu1{ -+ cpu-supply = <&vddcore>; - }; - --&dts { -- status = "okay"; -+&cryp1 { -+ status="okay"; - }; - - &gpu { -@@ -97,242 +51,6 @@ - status = "okay"; - }; - --&i2c4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c4_pins_a>; -- i2c-scl-rising-time-ns = <185>; -- i2c-scl-falling-time-ns = <20>; -+&optee { - status = "okay"; -- /* spare dmas for other usage */ -- /delete-property/dmas; -- /delete-property/dma-names; -- -- pmic: stpmic@33 { -- compatible = "st,stpmic1"; -- reg = <0x33>; -- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; -- interrupt-controller; -- #interrupt-cells = <2>; -- status = "okay"; -- -- regulators { -- compatible = "st,stpmic1-regulators"; -- ldo1-supply = <&v3v3>; -- ldo2-supply = <&v3v3>; -- ldo3-supply = <&vdd_ddr>; -- ldo5-supply = <&v3v3>; -- ldo6-supply = <&v3v3>; -- pwr_sw1-supply = <&bst_out>; -- pwr_sw2-supply = <&bst_out>; -- -- vddcore: buck1 { -- regulator-name = "vddcore"; -- regulator-min-microvolt = <800000>; -- regulator-max-microvolt = <1350000>; -- regulator-always-on; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- vdd_ddr: buck2 { -- regulator-name = "vdd_ddr"; -- regulator-min-microvolt = <1350000>; -- regulator-max-microvolt = <1350000>; -- regulator-always-on; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- vdd: buck3 { -- regulator-name = "vdd"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-always-on; -- st,mask-reset; -- regulator-initial-mode = <0>; -- regulator-over-current-protection; -- }; -- -- v3v3: buck4 { -- regulator-name = "v3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-always-on; -- regulator-over-current-protection; -- regulator-initial-mode = <0>; -- }; -- -- vdda: ldo1 { -- regulator-name = "vdda"; -- regulator-min-microvolt = <2900000>; -- regulator-max-microvolt = <2900000>; -- interrupts = ; -- }; -- -- v2v8: ldo2 { -- regulator-name = "v2v8"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <2800000>; -- interrupts = ; -- }; -- -- vtt_ddr: ldo3 { -- regulator-name = "vtt_ddr"; -- regulator-min-microvolt = <500000>; -- regulator-max-microvolt = <750000>; -- regulator-always-on; -- regulator-over-current-protection; -- }; -- -- vdd_usb: ldo4 { -- regulator-name = "vdd_usb"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- interrupts = ; -- }; -- -- vdd_sd: ldo5 { -- regulator-name = "vdd_sd"; -- regulator-min-microvolt = <2900000>; -- regulator-max-microvolt = <2900000>; -- interrupts = ; -- regulator-boot-on; -- }; -- -- v1v8: ldo6 { -- regulator-name = "v1v8"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- interrupts = ; -- }; -- -- vref_ddr: vref_ddr { -- regulator-name = "vref_ddr"; -- regulator-always-on; -- regulator-over-current-protection; -- }; -- -- bst_out: boost { -- regulator-name = "bst_out"; -- interrupts = ; -- }; -- -- vbus_otg: pwr_sw1 { -- regulator-name = "vbus_otg"; -- interrupts = ; -- }; -- -- vbus_sw: pwr_sw2 { -- regulator-name = "vbus_sw"; -- interrupts = ; -- regulator-active-discharge; -- }; -- }; -- -- onkey { -- compatible = "st,stpmic1-onkey"; -- interrupts = , ; -- interrupt-names = "onkey-falling", "onkey-rising"; -- power-off-time-sec = <10>; -- status = "okay"; -- }; -- -- watchdog { -- compatible = "st,stpmic1-wdt"; -- status = "disabled"; -- }; -- }; --}; -- --&ipcc { -- status = "okay"; --}; -- --&iwdg2 { -- timeout-sec = <32>; -- status = "okay"; --}; -- --&m4_rproc { -- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, -- <&vdev0vring1>, <&vdev0buffer>; -- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; -- mbox-names = "vq0", "vq1", "shutdown"; -- interrupt-parent = <&exti>; -- interrupts = <68 1>; -- status = "okay"; --}; -- --&pwr { -- pwr-regulators { -- vdd-supply = <&vdd>; -- vdd_3v3_usbfs-supply = <&vdd_usb>; -- }; --}; -- --&rng1 { -- status = "okay"; --}; -- --&rtc { -- status = "okay"; --}; -- --&sdmmc1 { -- pinctrl-names = "default", "opendrain", "sleep"; -- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; -- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; -- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; -- broken-cd; -- st,sig-dir; -- st,neg-edge; -- st,use-ckin; -- bus-width = <4>; -- vmmc-supply = <&vdd_sd>; -- vqmmc-supply = <&sd_switch>; -- status = "okay"; --}; -- --&sdmmc2 { -- pinctrl-names = "default", "opendrain", "sleep"; -- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; -- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; -- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; -- non-removable; -- no-sd; -- no-sdio; -- st,neg-edge; -- bus-width = <8>; -- vmmc-supply = <&v3v3>; -- vqmmc-supply = <&v3v3>; -- mmc-ddr-3_3v; -- status = "okay"; --}; -- --&timers6 { -- status = "okay"; -- /* spare dmas for other usage */ -- /delete-property/dmas; -- /delete-property/dma-names; -- timer@5 { -- status = "okay"; -- }; --}; -- --&uart4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart4_pins_a>; -- status = "okay"; --}; -- --&usbotg_hs { -- vbus-supply = <&vbus_otg>; --}; -- --&usbphyc_port0 { -- phy-supply = <&vdd_usb>; --}; -- --&usbphyc_port1 { -- phy-supply = <&vdd_usb>; - }; -diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi -index ec60486..cc02806 100644 ---- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi -@@ -3,51 +3,4 @@ - * Copyright : STMicroelectronics 2018 - */ - --#include "stm32mp157c-ed1-u-boot.dtsi" -- --/ { -- aliases { -- gpio26 = &stmfx_pinctrl; -- i2c1 = &i2c2; -- i2c4 = &i2c5; -- pinctrl2 = &stmfx_pinctrl; -- spi0 = &qspi; -- usb0 = &usbotg_hs; -- }; --}; -- --&flash0 { -- u-boot,dm-spl; --}; -- --&qspi { -- u-boot,dm-spl; --}; -- --&qspi_clk_pins_a { -- u-boot,dm-spl; -- pins { -- u-boot,dm-spl; -- }; --}; -- --&qspi_bk1_pins_a { -- u-boot,dm-spl; -- pins1 { -- u-boot,dm-spl; -- }; -- pins2 { -- u-boot,dm-spl; -- }; --}; -- --&qspi_bk2_pins_a { -- u-boot,dm-spl; -- pins1 { -- u-boot,dm-spl; -- }; -- pins2 { -- u-boot,dm-spl; -- }; --}; -- -+#include "stm32mp157a-ev1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts -index 89d29b5..c60727d 100644 ---- a/arch/arm/dts/stm32mp157c-ev1.dts -+++ b/arch/arm/dts/stm32mp157c-ev1.dts -@@ -1,13 +1,14 @@ - // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) - /* -- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -- * Author: Ludovic Barre for STMicroelectronics. -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. - */ - /dts-v1/; - - #include "stm32mp157c-ed1.dts" --#include -+#include "stm32mp15xx-evx.dtsi" - #include -+#include - - / { - model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; -@@ -18,90 +19,14 @@ - }; - - aliases { -- serial0 = &uart4; -+ serial1 = &usart3; - ethernet0 = ðernet0; - }; -- -- clocks { -- clk_ext_camera: clk-ext-camera { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <24000000>; -- }; -- }; -- -- joystick { -- compatible = "gpio-keys"; -- #size-cells = <0>; -- pinctrl-0 = <&joystick_pins>; -- pinctrl-names = "default"; -- button-0 { -- label = "JoySel"; -- linux,code = ; -- interrupt-parent = <&stmfx_pinctrl>; -- interrupts = <0 IRQ_TYPE_EDGE_RISING>; -- }; -- button-1 { -- label = "JoyDown"; -- linux,code = ; -- interrupt-parent = <&stmfx_pinctrl>; -- interrupts = <1 IRQ_TYPE_EDGE_RISING>; -- }; -- button-2 { -- label = "JoyLeft"; -- linux,code = ; -- interrupt-parent = <&stmfx_pinctrl>; -- interrupts = <2 IRQ_TYPE_EDGE_RISING>; -- }; -- button-3 { -- label = "JoyRight"; -- linux,code = ; -- interrupt-parent = <&stmfx_pinctrl>; -- interrupts = <3 IRQ_TYPE_EDGE_RISING>; -- }; -- button-4 { -- label = "JoyUp"; -- linux,code = ; -- interrupt-parent = <&stmfx_pinctrl>; -- interrupts = <4 IRQ_TYPE_EDGE_RISING>; -- }; -- }; -- -- panel_backlight: panel-backlight { -- compatible = "gpio-backlight"; -- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; -- default-on; -- status = "okay"; -- }; --}; -- --&cec { -- pinctrl-names = "default"; -- pinctrl-0 = <&cec_pins_a>; -- status = "okay"; --}; -- --&dcmi { -- status = "okay"; -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&dcmi_pins_a>; -- pinctrl-1 = <&dcmi_sleep_pins_a>; -- -- port { -- dcmi_0: endpoint { -- remote-endpoint = <&ov5640_0>; -- bus-width = <8>; -- hsync-active = <0>; -- vsync-active = <0>; -- pclk-sample = <1>; -- }; -- }; - }; - - &dsi { - #address-cells = <1>; - #size-cells = <0>; -- phy-dsi-supply = <®18>; - status = "okay"; - - ports { -@@ -123,7 +48,7 @@ - }; - }; - -- panel-dsi@0 { -+ panel_dsi: panel-dsi@0 { - compatible = "raydium,rm68200"; - reg = <0>; - reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; -@@ -139,122 +64,17 @@ - }; - }; - --ðernet0 { -- status = "okay"; -- pinctrl-0 = <ðernet0_rgmii_pins_a>; -- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; -- pinctrl-names = "default", "sleep"; -- phy-mode = "rgmii-id"; -- max-speed = <1000>; -- phy-handle = <&phy0>; -- -- mdio0 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "snps,dwmac-mdio"; -- phy0: ethernet-phy@0 { -- reg = <0>; -- }; -- }; --}; -- --&fmc { -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&fmc_pins_a>; -- pinctrl-1 = <&fmc_sleep_pins_a>; -- status = "okay"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- nand@0 { -- reg = <0>; -- nand-on-flash-bbt; -- #address-cells = <1>; -- #size-cells = <1>; -- }; --}; -- - &i2c2 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c2_pins_a>; -- i2c-scl-rising-time-ns = <185>; -- i2c-scl-falling-time-ns = <20>; -- status = "okay"; -- -- ov5640: camera@3c { -- compatible = "ovti,ov5640"; -+ gt9147: goodix_ts@5d { -+ compatible = "goodix,gt9147"; -+ reg = <0x5d>; -+ panel = <&panel_dsi>; -+ pinctrl-0 = <&goodix_pins>; - pinctrl-names = "default"; -- pinctrl-0 = <&ov5640_pins>; -- reg = <0x3c>; -- clocks = <&clk_ext_camera>; -- clock-names = "xclk"; -- DOVDD-supply = <&v2v8>; -- powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>; -- reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>; -- rotation = <180>; - status = "okay"; - -- port { -- ov5640_0: endpoint { -- remote-endpoint = <&dcmi_0>; -- bus-width = <8>; -- data-shift = <2>; /* lines 9:2 are used */ -- hsync-active = <0>; -- vsync-active = <0>; -- pclk-sample = <1>; -- }; -- }; -- }; -- -- stmfx: stmfx@42 { -- compatible = "st,stmfx-0300"; -- reg = <0x42>; -- interrupts = <8 IRQ_TYPE_EDGE_RISING>; -- interrupt-parent = <&gpioi>; -- vdd-supply = <&v3v3>; -- -- stmfx_pinctrl: stmfx-pin-controller { -- compatible = "st,stmfx-0300-pinctrl"; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- gpio-ranges = <&stmfx_pinctrl 0 0 24>; -- -- joystick_pins: joystick { -- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; -- drive-push-pull; -- bias-pull-down; -- }; -- -- ov5640_pins: camera { -- pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */ -- drive-push-pull; -- output-low; -- }; -- }; -- }; --}; -- --&i2c5 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c5_pins_a>; -- i2c-scl-rising-time-ns = <185>; -- i2c-scl-falling-time-ns = <20>; -- status = "okay"; --}; -- --<dc { -- status = "okay"; -- -- port { -- #address-cells = <1>; -- #size-cells = <0>; -- -- ltdc_ep0_out: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&dsi_in>; -- }; -+ interrupts = <14 IRQ_TYPE_EDGE_RISING>; -+ interrupt-parent = <&stmfx_pinctrl>; - }; - }; - -@@ -264,97 +84,3 @@ - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; - }; -- --&qspi { -- pinctrl-names = "default", "sleep"; -- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; -- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; -- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "okay"; -- -- flash0: mx66l51235l@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-rx-bus-width = <4>; -- spi-max-frequency = <108000000>; -- #address-cells = <1>; -- #size-cells = <1>; -- }; -- -- flash1: mx66l51235l@1 { -- compatible = "jedec,spi-nor"; -- reg = <1>; -- spi-rx-bus-width = <4>; -- spi-max-frequency = <108000000>; -- #address-cells = <1>; -- #size-cells = <1>; -- }; --}; -- --&spi1 { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi1_pins_a>; -- status = "disabled"; --}; -- --&timers2 { -- /* spare dmas for other usage (un-delete to enable pwm capture) */ -- /delete-property/dmas; -- /delete-property/dma-names; -- status = "disabled"; -- pwm { -- pinctrl-0 = <&pwm2_pins_a>; -- pinctrl-names = "default"; -- status = "okay"; -- }; -- timer@1 { -- status = "okay"; -- }; --}; -- --&timers8 { -- /delete-property/dmas; -- /delete-property/dma-names; -- status = "disabled"; -- pwm { -- pinctrl-0 = <&pwm8_pins_a>; -- pinctrl-names = "default"; -- status = "okay"; -- }; -- timer@7 { -- status = "okay"; -- }; --}; -- --&timers12 { -- /delete-property/dmas; -- /delete-property/dma-names; -- status = "disabled"; -- pwm { -- pinctrl-0 = <&pwm12_pins_a>; -- pinctrl-names = "default"; -- status = "okay"; -- }; -- timer@11 { -- status = "okay"; -- }; --}; -- --&usbh_ehci { -- phys = <&usbphyc_port0>; -- phy-names = "usb"; -- status = "okay"; --}; -- --&usbotg_hs { -- dr_mode = "peripheral"; -- phys = <&usbphyc_port1 0>; -- phy-names = "usb2-phy"; -- status = "okay"; --}; -- --&usbphyc { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi -deleted file mode 100644 -index 6c670cf..0000000 ---- a/arch/arm/dts/stm32mp157c.dtsi -+++ /dev/null -@@ -1,1592 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -- * Author: Ludovic Barre for STMicroelectronics. -- */ --#include --#include --#include -- --/ { -- #address-cells = <1>; -- #size-cells = <1>; -- -- cpus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- cpu0: cpu@0 { -- compatible = "arm,cortex-a7"; -- device_type = "cpu"; -- reg = <0>; -- }; -- -- cpu1: cpu@1 { -- compatible = "arm,cortex-a7"; -- device_type = "cpu"; -- reg = <1>; -- }; -- }; -- -- psci { -- compatible = "arm,psci-1.0"; -- method = "smc"; -- cpu_off = <0x84000002>; -- cpu_on = <0x84000003>; -- }; -- -- intc: interrupt-controller@a0021000 { -- compatible = "arm,cortex-a7-gic"; -- #interrupt-cells = <3>; -- interrupt-controller; -- reg = <0xa0021000 0x1000>, -- <0xa0022000 0x2000>; -- }; -- -- timer { -- compatible = "arm,armv7-timer"; -- interrupts = , -- , -- , -- ; -- interrupt-parent = <&intc>; -- }; -- -- clocks { -- clk_hse: clk-hse { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <24000000>; -- }; -- -- clk_hsi: clk-hsi { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <64000000>; -- }; -- -- clk_lse: clk-lse { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <32768>; -- }; -- -- clk_lsi: clk-lsi { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <32000>; -- }; -- -- clk_csi: clk-csi { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <4000000>; -- }; -- }; -- -- thermal-zones { -- cpu_thermal: cpu-thermal { -- polling-delay-passive = <0>; -- polling-delay = <0>; -- thermal-sensors = <&dts>; -- -- trips { -- cpu_alert1: cpu-alert1 { -- temperature = <85000>; -- hysteresis = <0>; -- type = "passive"; -- }; -- -- cpu-crit { -- temperature = <120000>; -- hysteresis = <0>; -- type = "critical"; -- }; -- }; -- -- cooling-maps { -- }; -- }; -- }; -- -- booster: regulator-booster { -- compatible = "st,stm32mp1-booster"; -- st,syscfg = <&syscfg>; -- status = "disabled"; -- }; -- -- reboot { -- compatible = "syscon-reboot"; -- regmap = <&rcc>; -- offset = <0x404>; -- mask = <0x1>; -- }; -- -- soc { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- interrupt-parent = <&intc>; -- ranges; -- -- timers2: timer@40000000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40000000 0x400>; -- clocks = <&rcc TIM2_K>; -- clock-names = "int"; -- dmas = <&dmamux1 18 0x400 0x1>, -- <&dmamux1 19 0x400 0x1>, -- <&dmamux1 20 0x400 0x1>, -- <&dmamux1 21 0x400 0x1>, -- <&dmamux1 22 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4", "up"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@1 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <1>; -- status = "disabled"; -- }; -- }; -- -- timers3: timer@40001000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40001000 0x400>; -- clocks = <&rcc TIM3_K>; -- clock-names = "int"; -- dmas = <&dmamux1 23 0x400 0x1>, -- <&dmamux1 24 0x400 0x1>, -- <&dmamux1 25 0x400 0x1>, -- <&dmamux1 26 0x400 0x1>, -- <&dmamux1 27 0x400 0x1>, -- <&dmamux1 28 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@2 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <2>; -- status = "disabled"; -- }; -- }; -- -- timers4: timer@40002000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40002000 0x400>; -- clocks = <&rcc TIM4_K>; -- clock-names = "int"; -- dmas = <&dmamux1 29 0x400 0x1>, -- <&dmamux1 30 0x400 0x1>, -- <&dmamux1 31 0x400 0x1>, -- <&dmamux1 32 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@3 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <3>; -- status = "disabled"; -- }; -- }; -- -- timers5: timer@40003000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40003000 0x400>; -- clocks = <&rcc TIM5_K>; -- clock-names = "int"; -- dmas = <&dmamux1 55 0x400 0x1>, -- <&dmamux1 56 0x400 0x1>, -- <&dmamux1 57 0x400 0x1>, -- <&dmamux1 58 0x400 0x1>, -- <&dmamux1 59 0x400 0x1>, -- <&dmamux1 60 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@4 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <4>; -- status = "disabled"; -- }; -- }; -- -- timers6: timer@40004000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40004000 0x400>; -- clocks = <&rcc TIM6_K>; -- clock-names = "int"; -- dmas = <&dmamux1 69 0x400 0x1>; -- dma-names = "up"; -- status = "disabled"; -- -- timer@5 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <5>; -- status = "disabled"; -- }; -- }; -- -- timers7: timer@40005000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40005000 0x400>; -- clocks = <&rcc TIM7_K>; -- clock-names = "int"; -- dmas = <&dmamux1 70 0x400 0x1>; -- dma-names = "up"; -- status = "disabled"; -- -- timer@6 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <6>; -- status = "disabled"; -- }; -- }; -- -- timers12: timer@40006000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40006000 0x400>; -- clocks = <&rcc TIM12_K>; -- clock-names = "int"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@11 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <11>; -- status = "disabled"; -- }; -- }; -- -- timers13: timer@40007000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40007000 0x400>; -- clocks = <&rcc TIM13_K>; -- clock-names = "int"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@12 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <12>; -- status = "disabled"; -- }; -- }; -- -- timers14: timer@40008000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x40008000 0x400>; -- clocks = <&rcc TIM14_K>; -- clock-names = "int"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@13 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <13>; -- status = "disabled"; -- }; -- }; -- -- lptimer1: timer@40009000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-lptimer"; -- reg = <0x40009000 0x400>; -- clocks = <&rcc LPTIM1_K>; -- clock-names = "mux"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm-lp"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- trigger@0 { -- compatible = "st,stm32-lptimer-trigger"; -- reg = <0>; -- status = "disabled"; -- }; -- -- counter { -- compatible = "st,stm32-lptimer-counter"; -- status = "disabled"; -- }; -- }; -- -- spi2: spi@4000b000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x4000b000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI2_K>; -- resets = <&rcc SPI2_R>; -- dmas = <&dmamux1 39 0x400 0x05>, -- <&dmamux1 40 0x400 0x05>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- i2s2: audio-controller@4000b000 { -- compatible = "st,stm32h7-i2s"; -- #sound-dai-cells = <0>; -- reg = <0x4000b000 0x400>; -- interrupts = ; -- dmas = <&dmamux1 39 0x400 0x01>, -- <&dmamux1 40 0x400 0x01>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- spi3: spi@4000c000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x4000c000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI3_K>; -- resets = <&rcc SPI3_R>; -- dmas = <&dmamux1 61 0x400 0x05>, -- <&dmamux1 62 0x400 0x05>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- i2s3: audio-controller@4000c000 { -- compatible = "st,stm32h7-i2s"; -- #sound-dai-cells = <0>; -- reg = <0x4000c000 0x400>; -- interrupts = ; -- dmas = <&dmamux1 61 0x400 0x01>, -- <&dmamux1 62 0x400 0x01>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- spdifrx: audio-controller@4000d000 { -- compatible = "st,stm32h7-spdifrx"; -- #sound-dai-cells = <0>; -- reg = <0x4000d000 0x400>; -- clocks = <&rcc SPDIF_K>; -- clock-names = "kclk"; -- interrupts = ; -- dmas = <&dmamux1 93 0x400 0x01>, -- <&dmamux1 94 0x400 0x01>; -- dma-names = "rx", "rx-ctrl"; -- status = "disabled"; -- }; -- -- usart2: serial@4000e000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x4000e000 0x400>; -- interrupts = ; -- clocks = <&rcc USART2_K>; -- status = "disabled"; -- }; -- -- usart3: serial@4000f000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x4000f000 0x400>; -- interrupts = ; -- clocks = <&rcc USART3_K>; -- status = "disabled"; -- }; -- -- uart4: serial@40010000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x40010000 0x400>; -- interrupts = ; -- clocks = <&rcc UART4_K>; -- status = "disabled"; -- }; -- -- uart5: serial@40011000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x40011000 0x400>; -- interrupts = ; -- clocks = <&rcc UART5_K>; -- status = "disabled"; -- }; -- -- i2c1: i2c@40012000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x40012000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C1_K>; -- resets = <&rcc I2C1_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c2: i2c@40013000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x40013000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C2_K>; -- resets = <&rcc I2C2_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c3: i2c@40014000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x40014000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C3_K>; -- resets = <&rcc I2C3_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c5: i2c@40015000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x40015000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C5_K>; -- resets = <&rcc I2C5_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- cec: cec@40016000 { -- compatible = "st,stm32-cec"; -- reg = <0x40016000 0x400>; -- interrupts = ; -- clocks = <&rcc CEC_K>, <&clk_lse>; -- clock-names = "cec", "hdmi-cec"; -- status = "disabled"; -- }; -- -- dac: dac@40017000 { -- compatible = "st,stm32h7-dac-core"; -- reg = <0x40017000 0x400>; -- clocks = <&rcc DAC12>; -- clock-names = "pclk"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- dac1: dac@1 { -- compatible = "st,stm32-dac"; -- #io-channels-cells = <1>; -- reg = <1>; -- status = "disabled"; -- }; -- -- dac2: dac@2 { -- compatible = "st,stm32-dac"; -- #io-channels-cells = <1>; -- reg = <2>; -- status = "disabled"; -- }; -- }; -- -- uart7: serial@40018000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x40018000 0x400>; -- interrupts = ; -- clocks = <&rcc UART7_K>; -- status = "disabled"; -- }; -- -- uart8: serial@40019000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x40019000 0x400>; -- interrupts = ; -- clocks = <&rcc UART8_K>; -- status = "disabled"; -- }; -- -- timers1: timer@44000000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x44000000 0x400>; -- clocks = <&rcc TIM1_K>; -- clock-names = "int"; -- dmas = <&dmamux1 11 0x400 0x1>, -- <&dmamux1 12 0x400 0x1>, -- <&dmamux1 13 0x400 0x1>, -- <&dmamux1 14 0x400 0x1>, -- <&dmamux1 15 0x400 0x1>, -- <&dmamux1 16 0x400 0x1>, -- <&dmamux1 17 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4", -- "up", "trig", "com"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@0 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <0>; -- status = "disabled"; -- }; -- }; -- -- timers8: timer@44001000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x44001000 0x400>; -- clocks = <&rcc TIM8_K>; -- clock-names = "int"; -- dmas = <&dmamux1 47 0x400 0x1>, -- <&dmamux1 48 0x400 0x1>, -- <&dmamux1 49 0x400 0x1>, -- <&dmamux1 50 0x400 0x1>, -- <&dmamux1 51 0x400 0x1>, -- <&dmamux1 52 0x400 0x1>, -- <&dmamux1 53 0x400 0x1>; -- dma-names = "ch1", "ch2", "ch3", "ch4", -- "up", "trig", "com"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@7 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <7>; -- status = "disabled"; -- }; -- }; -- -- usart6: serial@44003000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x44003000 0x400>; -- interrupts = ; -- clocks = <&rcc USART6_K>; -- status = "disabled"; -- }; -- -- spi1: spi@44004000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x44004000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI1_K>; -- resets = <&rcc SPI1_R>; -- dmas = <&dmamux1 37 0x400 0x05>, -- <&dmamux1 38 0x400 0x05>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- i2s1: audio-controller@44004000 { -- compatible = "st,stm32h7-i2s"; -- #sound-dai-cells = <0>; -- reg = <0x44004000 0x400>; -- interrupts = ; -- dmas = <&dmamux1 37 0x400 0x01>, -- <&dmamux1 38 0x400 0x01>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- spi4: spi@44005000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x44005000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI4_K>; -- resets = <&rcc SPI4_R>; -- dmas = <&dmamux1 83 0x400 0x05>, -- <&dmamux1 84 0x400 0x05>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- timers15: timer@44006000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x44006000 0x400>; -- clocks = <&rcc TIM15_K>; -- clock-names = "int"; -- dmas = <&dmamux1 105 0x400 0x1>, -- <&dmamux1 106 0x400 0x1>, -- <&dmamux1 107 0x400 0x1>, -- <&dmamux1 108 0x400 0x1>; -- dma-names = "ch1", "up", "trig", "com"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@14 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <14>; -- status = "disabled"; -- }; -- }; -- -- timers16: timer@44007000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x44007000 0x400>; -- clocks = <&rcc TIM16_K>; -- clock-names = "int"; -- dmas = <&dmamux1 109 0x400 0x1>, -- <&dmamux1 110 0x400 0x1>; -- dma-names = "ch1", "up"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- timer@15 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <15>; -- status = "disabled"; -- }; -- }; -- -- timers17: timer@44008000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-timers"; -- reg = <0x44008000 0x400>; -- clocks = <&rcc TIM17_K>; -- clock-names = "int"; -- dmas = <&dmamux1 111 0x400 0x1>, -- <&dmamux1 112 0x400 0x1>; -- dma-names = "ch1", "up"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- timer@16 { -- compatible = "st,stm32h7-timer-trigger"; -- reg = <16>; -- status = "disabled"; -- }; -- }; -- -- spi5: spi@44009000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x44009000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI5_K>; -- resets = <&rcc SPI5_R>; -- dmas = <&dmamux1 85 0x400 0x05>, -- <&dmamux1 86 0x400 0x05>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- sai1: sai@4400a000 { -- compatible = "st,stm32h7-sai"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x4400a000 0x400>; -- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; -- interrupts = ; -- resets = <&rcc SAI1_R>; -- status = "disabled"; -- -- sai1a: audio-controller@4400a004 { -- #sound-dai-cells = <0>; -- -- compatible = "st,stm32-sai-sub-a"; -- reg = <0x4 0x1c>; -- clocks = <&rcc SAI1_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 87 0x400 0x01>; -- status = "disabled"; -- }; -- -- sai1b: audio-controller@4400a024 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-b"; -- reg = <0x24 0x1c>; -- clocks = <&rcc SAI1_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 88 0x400 0x01>; -- status = "disabled"; -- }; -- }; -- -- sai2: sai@4400b000 { -- compatible = "st,stm32h7-sai"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x4400b000 0x400>; -- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; -- interrupts = ; -- resets = <&rcc SAI2_R>; -- status = "disabled"; -- -- sai2a: audio-controller@4400b004 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-a"; -- reg = <0x4 0x1c>; -- clocks = <&rcc SAI2_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 89 0x400 0x01>; -- status = "disabled"; -- }; -- -- sai2b: audio-controller@4400b024 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-b"; -- reg = <0x24 0x1c>; -- clocks = <&rcc SAI2_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 90 0x400 0x01>; -- status = "disabled"; -- }; -- }; -- -- sai3: sai@4400c000 { -- compatible = "st,stm32h7-sai"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x4400c000 0x400>; -- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; -- interrupts = ; -- resets = <&rcc SAI3_R>; -- status = "disabled"; -- -- sai3a: audio-controller@4400c004 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-a"; -- reg = <0x04 0x1c>; -- clocks = <&rcc SAI3_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 113 0x400 0x01>; -- status = "disabled"; -- }; -- -- sai3b: audio-controller@4400c024 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-b"; -- reg = <0x24 0x1c>; -- clocks = <&rcc SAI3_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 114 0x400 0x01>; -- status = "disabled"; -- }; -- }; -- -- dfsdm: dfsdm@4400d000 { -- compatible = "st,stm32mp1-dfsdm"; -- reg = <0x4400d000 0x800>; -- clocks = <&rcc DFSDM_K>; -- clock-names = "dfsdm"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- dfsdm0: filter@0 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <0>; -- interrupts = ; -- dmas = <&dmamux1 101 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- dfsdm1: filter@1 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <1>; -- interrupts = ; -- dmas = <&dmamux1 102 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- dfsdm2: filter@2 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <2>; -- interrupts = ; -- dmas = <&dmamux1 103 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- dfsdm3: filter@3 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <3>; -- interrupts = ; -- dmas = <&dmamux1 104 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- dfsdm4: filter@4 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <4>; -- interrupts = ; -- dmas = <&dmamux1 91 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- dfsdm5: filter@5 { -- compatible = "st,stm32-dfsdm-adc"; -- #io-channel-cells = <1>; -- reg = <5>; -- interrupts = ; -- dmas = <&dmamux1 92 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- }; -- -- m_can1: can@4400e000 { -- compatible = "bosch,m_can"; -- reg = <0x4400e000 0x400>, <0x44011000 0x1400>; -- reg-names = "m_can", "message_ram"; -- interrupts = , -- ; -- interrupt-names = "int0", "int1"; -- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -- clock-names = "hclk", "cclk"; -- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; -- status = "disabled"; -- }; -- -- m_can2: can@4400f000 { -- compatible = "bosch,m_can"; -- reg = <0x4400f000 0x400>, <0x44011000 0x2800>; -- reg-names = "m_can", "message_ram"; -- interrupts = , -- ; -- interrupt-names = "int0", "int1"; -- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; -- clock-names = "hclk", "cclk"; -- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; -- status = "disabled"; -- }; -- -- dma1: dma@48000000 { -- compatible = "st,stm32-dma"; -- reg = <0x48000000 0x400>; -- interrupts = , -- , -- , -- , -- , -- , -- , -- ; -- clocks = <&rcc DMA1>; -- #dma-cells = <4>; -- st,mem2mem; -- dma-requests = <8>; -- }; -- -- dma2: dma@48001000 { -- compatible = "st,stm32-dma"; -- reg = <0x48001000 0x400>; -- interrupts = , -- , -- , -- , -- , -- , -- , -- ; -- clocks = <&rcc DMA2>; -- #dma-cells = <4>; -- st,mem2mem; -- dma-requests = <8>; -- }; -- -- dmamux1: dma-router@48002000 { -- compatible = "st,stm32h7-dmamux"; -- reg = <0x48002000 0x1c>; -- #dma-cells = <3>; -- dma-requests = <128>; -- dma-masters = <&dma1 &dma2>; -- dma-channels = <16>; -- clocks = <&rcc DMAMUX>; -- }; -- -- adc: adc@48003000 { -- compatible = "st,stm32mp1-adc-core"; -- reg = <0x48003000 0x400>; -- interrupts = , -- ; -- clocks = <&rcc ADC12>, <&rcc ADC12_K>; -- clock-names = "bus", "adc"; -- interrupt-controller; -- st,syscfg = <&syscfg>; -- #interrupt-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- -- adc1: adc@0 { -- compatible = "st,stm32mp1-adc"; -- #io-channel-cells = <1>; -- reg = <0x0>; -- interrupt-parent = <&adc>; -- interrupts = <0>; -- dmas = <&dmamux1 9 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- -- adc2: adc@100 { -- compatible = "st,stm32mp1-adc"; -- #io-channel-cells = <1>; -- reg = <0x100>; -- interrupt-parent = <&adc>; -- interrupts = <1>; -- dmas = <&dmamux1 10 0x400 0x01>; -- dma-names = "rx"; -- status = "disabled"; -- }; -- }; -- -- sdmmc3: sdmmc@48004000 { -- compatible = "arm,pl18x", "arm,primecell"; -- arm,primecell-periphid = <0x10153180>; -- reg = <0x48004000 0x400>; -- reg-names = "sdmmc"; -- interrupts = ; -- clocks = <&rcc SDMMC3_K>; -- clock-names = "apb_pclk"; -- resets = <&rcc SDMMC3_R>; -- cap-sd-highspeed; -- cap-mmc-highspeed; -- max-frequency = <120000000>; -- status = "disabled"; -- }; -- -- usbotg_hs: usb-otg@49000000 { -- compatible = "snps,dwc2"; -- reg = <0x49000000 0x10000>; -- clocks = <&rcc USBO_K>; -- clock-names = "otg"; -- resets = <&rcc USBO_R>; -- reset-names = "dwc2"; -- interrupts = ; -- g-rx-fifo-size = <256>; -- g-np-tx-fifo-size = <32>; -- g-tx-fifo-size = <128 128 64 64 64 64 32 32>; -- dr_mode = "otg"; -- usb33d-supply = <&usb33>; -- status = "disabled"; -- }; -- -- hwspinlock: hwspinlock@4c000000 { -- compatible = "st,stm32-hwspinlock"; -- #hwlock-cells = <1>; -- reg = <0x4c000000 0x400>; -- clocks = <&rcc HSEM>; -- clock-names = "hwspinlock"; -- }; -- -- ipcc: mailbox@4c001000 { -- compatible = "st,stm32mp1-ipcc"; -- #mbox-cells = <1>; -- reg = <0x4c001000 0x400>; -- st,proc-id = <0>; -- interrupts-extended = -- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, -- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, -- <&exti 61 1>; -- interrupt-names = "rx", "tx", "wakeup"; -- clocks = <&rcc IPCC>; -- wakeup-source; -- status = "disabled"; -- }; -- -- dcmi: dcmi@4c006000 { -- compatible = "st,stm32-dcmi"; -- reg = <0x4c006000 0x400>; -- interrupts = ; -- resets = <&rcc CAMITF_R>; -- clocks = <&rcc DCMI>; -- clock-names = "mclk"; -- dmas = <&dmamux1 75 0x400 0x0d>; -- dma-names = "tx"; -- status = "disabled"; -- }; -- -- rcc: rcc@50000000 { -- compatible = "st,stm32mp1-rcc", "syscon"; -- reg = <0x50000000 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- -- pwr: pwr@50001000 { -- compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; -- reg = <0x50001000 0x400>; -- system-power-controller; -- interrupts = ; -- st,sysrcc = <&rcc>; -- clocks = <&rcc PLL2_R>; -- clock-names = "phyclk"; -- -- pwr-regulators { -- compatible = "st,stm32mp1,pwr-reg"; -- st,tzcr = <&rcc 0x0 0x1>; -- -- reg11: reg11 { -- regulator-name = "reg11"; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; -- }; -- -- reg18: reg18 { -- regulator-name = "reg18"; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- }; -- -- usb33: usb33 { -- regulator-name = "usb33"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- }; -- }; -- }; -- -- exti: interrupt-controller@5000d000 { -- compatible = "st,stm32mp1-exti", "syscon"; -- interrupt-controller; -- #interrupt-cells = <2>; -- reg = <0x5000d000 0x400>; -- }; -- -- syscfg: syscon@50020000 { -- compatible = "st,stm32mp157-syscfg", "syscon"; -- reg = <0x50020000 0x400>; -- clocks = <&rcc SYSCFG>; -- }; -- -- lptimer2: timer@50021000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-lptimer"; -- reg = <0x50021000 0x400>; -- clocks = <&rcc LPTIM2_K>; -- clock-names = "mux"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm-lp"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- trigger@1 { -- compatible = "st,stm32-lptimer-trigger"; -- reg = <1>; -- status = "disabled"; -- }; -- -- counter { -- compatible = "st,stm32-lptimer-counter"; -- status = "disabled"; -- }; -- }; -- -- lptimer3: timer@50022000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32-lptimer"; -- reg = <0x50022000 0x400>; -- clocks = <&rcc LPTIM3_K>; -- clock-names = "mux"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm-lp"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- trigger@2 { -- compatible = "st,stm32-lptimer-trigger"; -- reg = <2>; -- status = "disabled"; -- }; -- }; -- -- lptimer4: timer@50023000 { -- compatible = "st,stm32-lptimer"; -- reg = <0x50023000 0x400>; -- clocks = <&rcc LPTIM4_K>; -- clock-names = "mux"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm-lp"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- }; -- -- lptimer5: timer@50024000 { -- compatible = "st,stm32-lptimer"; -- reg = <0x50024000 0x400>; -- clocks = <&rcc LPTIM5_K>; -- clock-names = "mux"; -- status = "disabled"; -- -- pwm { -- compatible = "st,stm32-pwm-lp"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- }; -- -- vrefbuf: vrefbuf@50025000 { -- compatible = "st,stm32-vrefbuf"; -- reg = <0x50025000 0x8>; -- regulator-min-microvolt = <1500000>; -- regulator-max-microvolt = <2500000>; -- clocks = <&rcc VREF>; -- status = "disabled"; -- }; -- -- sai4: sai@50027000 { -- compatible = "st,stm32h7-sai"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x50027000 0x400>; -- reg = <0x50027000 0x4>, <0x500273f0 0x10>; -- interrupts = ; -- resets = <&rcc SAI4_R>; -- status = "disabled"; -- -- sai4a: audio-controller@50027004 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-a"; -- reg = <0x04 0x1c>; -- clocks = <&rcc SAI4_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 99 0x400 0x01>; -- status = "disabled"; -- }; -- -- sai4b: audio-controller@50027024 { -- #sound-dai-cells = <0>; -- compatible = "st,stm32-sai-sub-b"; -- reg = <0x24 0x1c>; -- clocks = <&rcc SAI4_K>; -- clock-names = "sai_ck"; -- dmas = <&dmamux1 100 0x400 0x01>; -- status = "disabled"; -- }; -- }; -- -- dts: thermal@50028000 { -- compatible = "st,stm32-thermal"; -- reg = <0x50028000 0x100>; -- interrupts = ; -- clocks = <&rcc TMPSENS>; -- clock-names = "pclk"; -- #thermal-sensor-cells = <0>; -- status = "disabled"; -- }; -- -- cryp1: cryp@54001000 { -- compatible = "st,stm32mp1-cryp"; -- reg = <0x54001000 0x400>; -- interrupts = ; -- clocks = <&rcc CRYP1>; -- resets = <&rcc CRYP1_R>; -- status = "disabled"; -- }; -- -- hash1: hash@54002000 { -- compatible = "st,stm32f756-hash"; -- reg = <0x54002000 0x400>; -- interrupts = ; -- clocks = <&rcc HASH1>; -- resets = <&rcc HASH1_R>; -- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; -- dma-names = "in"; -- dma-maxburst = <2>; -- status = "disabled"; -- }; -- -- rng1: rng@54003000 { -- compatible = "st,stm32-rng"; -- reg = <0x54003000 0x400>; -- clocks = <&rcc RNG1_K>; -- resets = <&rcc RNG1_R>; -- status = "disabled"; -- }; -- -- mdma1: dma@58000000 { -- compatible = "st,stm32h7-mdma"; -- reg = <0x58000000 0x1000>; -- interrupts = ; -- clocks = <&rcc MDMA>; -- #dma-cells = <5>; -- dma-channels = <32>; -- dma-requests = <48>; -- }; -- -- fmc: nand-controller@58002000 { -- compatible = "st,stm32mp15-fmc2"; -- reg = <0x58002000 0x1000>, -- <0x80000000 0x1000>, -- <0x88010000 0x1000>, -- <0x88020000 0x1000>, -- <0x81000000 0x1000>, -- <0x89010000 0x1000>, -- <0x89020000 0x1000>; -- interrupts = ; -- dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, -- <&mdma1 20 0x10 0x12000a08 0x0 0x0>, -- <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; -- dma-names = "tx", "rx", "ecc"; -- clocks = <&rcc FMC_K>; -- resets = <&rcc FMC_R>; -- status = "disabled"; -- }; -- -- qspi: spi@58003000 { -- compatible = "st,stm32f469-qspi"; -- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; -- reg-names = "qspi", "qspi_mm"; -- interrupts = ; -- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, -- <&mdma1 22 0x10 0x100008 0x0 0x0>; -- dma-names = "tx", "rx"; -- clocks = <&rcc QSPI_K>; -- resets = <&rcc QSPI_R>; -- status = "disabled"; -- }; -- -- sdmmc1: sdmmc@58005000 { -- compatible = "arm,pl18x", "arm,primecell"; -- arm,primecell-periphid = <0x10153180>; -- reg = <0x58005000 0x1000>; -- interrupts = ; -- interrupt-names = "cmd_irq"; -- clocks = <&rcc SDMMC1_K>; -- clock-names = "apb_pclk"; -- resets = <&rcc SDMMC1_R>; -- cap-sd-highspeed; -- cap-mmc-highspeed; -- max-frequency = <120000000>; -- }; -- -- sdmmc2: sdmmc@58007000 { -- compatible = "arm,pl18x", "arm,primecell"; -- arm,primecell-periphid = <0x10153180>; -- reg = <0x58007000 0x1000>; -- interrupts = ; -- clocks = <&rcc SDMMC2_K>; -- clock-names = "apb_pclk"; -- resets = <&rcc SDMMC2_R>; -- cap-sd-highspeed; -- cap-mmc-highspeed; -- max-frequency = <120000000>; -- status = "disabled"; -- }; -- -- crc1: crc@58009000 { -- compatible = "st,stm32f7-crc"; -- reg = <0x58009000 0x400>; -- clocks = <&rcc CRC1>; -- status = "disabled"; -- }; -- -- stmmac_axi_config_0: stmmac-axi-config { -- snps,wr_osr_lmt = <0x7>; -- snps,rd_osr_lmt = <0x7>; -- snps,blen = <0 0 0 0 16 8 4>; -- }; -- -- ethernet0: ethernet@5800a000 { -- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; -- reg = <0x5800a000 0x2000>; -- reg-names = "stmmaceth"; -- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; -- interrupt-names = "macirq"; -- clock-names = "stmmaceth", -- "mac-clk-tx", -- "mac-clk-rx", -- "ethstp", -- "syscfg-clk"; -- clocks = <&rcc ETHMAC>, -- <&rcc ETHTX>, -- <&rcc ETHRX>, -- <&rcc ETHSTP>, -- <&rcc SYSCFG>; -- st,syscon = <&syscfg 0x4>; -- snps,mixed-burst; -- snps,pbl = <2>; -- snps,axi-config = <&stmmac_axi_config_0>; -- snps,tso; -- status = "disabled"; -- }; -- -- usbh_ohci: usbh-ohci@5800c000 { -- compatible = "generic-ohci"; -- reg = <0x5800c000 0x1000>; -- clocks = <&rcc USBH>; -- resets = <&rcc USBH_R>; -- interrupts = ; -- status = "disabled"; -- }; -- -- usbh_ehci: usbh-ehci@5800d000 { -- compatible = "generic-ehci"; -- reg = <0x5800d000 0x1000>; -- clocks = <&rcc USBH>; -- resets = <&rcc USBH_R>; -- interrupts = ; -- companion = <&usbh_ohci>; -- status = "disabled"; -- }; -- -- gpu: gpu@59000000 { -- compatible = "vivante,gc"; -- reg = <0x59000000 0x800>; -- interrupts = ; -- clocks = <&rcc GPU>, <&rcc GPU_K>; -- clock-names = "bus" ,"core"; -- resets = <&rcc GPU_R>; -- status = "disabled"; -- }; -- -- dsi: dsi@5a000000 { -- compatible = "st,stm32-dsi"; -- reg = <0x5a000000 0x800>; -- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; -- clock-names = "pclk", "ref", "px_clk"; -- resets = <&rcc DSI_R>; -- reset-names = "apb"; -- status = "disabled"; -- }; -- -- ltdc: display-controller@5a001000 { -- compatible = "st,stm32-ltdc"; -- reg = <0x5a001000 0x400>; -- interrupts = , -- ; -- clocks = <&rcc LTDC_PX>; -- clock-names = "lcd"; -- resets = <&rcc LTDC_R>; -- status = "disabled"; -- }; -- -- iwdg2: watchdog@5a002000 { -- compatible = "st,stm32mp1-iwdg"; -- reg = <0x5a002000 0x400>; -- clocks = <&rcc IWDG2>, <&rcc CK_LSI>; -- clock-names = "pclk", "lsi"; -- status = "disabled"; -- }; -- -- usbphyc: usbphyc@5a006000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32mp1-usbphyc"; -- reg = <0x5a006000 0x1000>; -- clocks = <&rcc USBPHY_K>; -- resets = <&rcc USBPHY_R>; -- vdda1v1-supply = <®11>; -- vdda1v8-supply = <®18>; -- status = "disabled"; -- -- usbphyc_port0: usb-phy@0 { -- #phy-cells = <0>; -- reg = <0>; -- }; -- -- usbphyc_port1: usb-phy@1 { -- #phy-cells = <1>; -- reg = <1>; -- }; -- }; -- -- usart1: serial@5c000000 { -- compatible = "st,stm32h7-uart"; -- reg = <0x5c000000 0x400>; -- interrupts = ; -- clocks = <&rcc USART1_K>; -- status = "disabled"; -- }; -- -- spi6: spi@5c001000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "st,stm32h7-spi"; -- reg = <0x5c001000 0x400>; -- interrupts = ; -- clocks = <&rcc SPI6_K>; -- resets = <&rcc SPI6_R>; -- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, -- <&mdma1 35 0x0 0x40002 0x0 0x0>; -- dma-names = "rx", "tx"; -- status = "disabled"; -- }; -- -- i2c4: i2c@5c002000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x5c002000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C4_K>; -- resets = <&rcc I2C4_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- rtc: rtc@5c004000 { -- compatible = "st,stm32mp1-rtc"; -- reg = <0x5c004000 0x400>; -- clocks = <&rcc RTCAPB>, <&rcc RTC>; -- clock-names = "pclk", "rtc_ck"; -- interrupts = ; -- status = "disabled"; -- }; -- -- bsec: nvmem@5c005000 { -- compatible = "st,stm32mp15-bsec"; -- reg = <0x5c005000 0x400>; -- #address-cells = <1>; -- #size-cells = <1>; -- ts_cal1: calib@5c { -- reg = <0x5c 0x2>; -- }; -- ts_cal2: calib@5e { -- reg = <0x5e 0x2>; -- }; -- }; -- -- i2c6: i2c@5c009000 { -- compatible = "st,stm32f7-i2c"; -- reg = <0x5c009000 0x400>; -- interrupt-names = "event", "error"; -- interrupts = , -- ; -- clocks = <&rcc I2C6_K>; -- resets = <&rcc I2C6_R>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- }; -- -- mlahb { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- dma-ranges = <0x00000000 0x38000000 0x10000>, -- <0x10000000 0x10000000 0x60000>, -- <0x30000000 0x30000000 0x60000>; -- -- m4_rproc: m4@10000000 { -- compatible = "st,stm32mp1-m4"; -- reg = <0x10000000 0x40000>, -- <0x30000000 0x40000>, -- <0x38000000 0x10000>; -- resets = <&rcc MCU_R>; -- st,syscfg-holdboot = <&rcc 0x10C 0x1>; -- st,syscfg-tz = <&rcc 0x000 0x1>; -- status = "disabled"; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi -new file mode 100644 -index 0000000..4f9b7a9 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157a-dk1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts -new file mode 100644 -index 0000000..c7d65a6 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-dk1.dts -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xd.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxac-pinctrl.dtsi" -+#include "stm32mp15xx-dkx.dtsi" -+/ { -+ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board"; -+ compatible = "st,stm32mp157d-dk1", "st,stm32mp157"; -+ -+ aliases { -+ ethernet0 = ðernet0; -+ serial0 = &uart4; -+ serial1 = &usart3; -+ serial2 = &uart7; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@da000000 { -+ reg = <0xda000000 0x4000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@0xde000000 { -+ reg = <0xde000000 0x02000000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi -new file mode 100644 -index 0000000..70d9afc ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157a-ed1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts -new file mode 100644 -index 0000000..ee55ac8 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-ed1.dts -@@ -0,0 +1,52 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xd.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxaa-pinctrl.dtsi" -+#include "stm32mp157-m4-srm.dtsi" -+#include "stm32mp157-m4-srm-pinctrl.dtsi" -+#include "stm32mp15xx-edx.dtsi" -+ -+/ { -+ model = "STMicroelectronics STM32MP157D eval daughter"; -+ compatible = "st,stm32mp157d-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial0 = &uart4; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@f6000000 { -+ reg = <0xf6000000 0x8000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@fe000000 { -+ reg = <0xfe000000 0x02000000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&cpu1{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&gpu { -+ contiguous-area = <&gpu_reserved>; -+ status = "okay"; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi -new file mode 100644 -index 0000000..77168a4 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157a-ev1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157d-ev1.dts b/arch/arm/dts/stm32mp157d-ev1.dts -new file mode 100644 -index 0000000..a4752c1 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157d-ev1.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157d-ed1.dts" -+#include "stm32mp15xx-evx.dtsi" -+#include -+#include -+ -+/ { -+ model = "STMicroelectronics STM32MP157D eval daughter on eval mother"; -+ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial1 = &usart3; -+ ethernet0 = ðernet0; -+ }; -+}; -+ -+&dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ dsi_in: endpoint { -+ remote-endpoint = <<dc_ep0_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ dsi_out: endpoint { -+ remote-endpoint = <&dsi_panel_in>; -+ }; -+ }; -+ }; -+ -+ panel_dsi: panel-dsi@0 { -+ compatible = "raydium,rm68200"; -+ reg = <0>; -+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; -+ backlight = <&panel_backlight>; -+ power-supply = <&v3v3>; -+ status = "okay"; -+ -+ port { -+ dsi_panel_in: endpoint { -+ remote-endpoint = <&dsi_out>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ gt9147: goodix_ts@5d { -+ compatible = "goodix,gt9147"; -+ reg = <0x5d>; -+ panel = <&panel_dsi>; -+ pinctrl-0 = <&goodix_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ interrupts = <14 IRQ_TYPE_EDGE_RISING>; -+ interrupt-parent = <&stmfx_pinctrl>; -+ }; -+}; -+ -+&m_can1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&m_can1_pins_a>; -+ pinctrl-1 = <&m_can1_sleep_pins_a>; -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi -new file mode 100644 -index 0000000..1bed79c ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157c-dk2-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts -new file mode 100644 -index 0000000..b57db30 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-dk2.dts -@@ -0,0 +1,185 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xf.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxac-pinctrl.dtsi" -+#include "stm32mp15xx-dkx.dtsi" -+#include -+ -+/ { -+ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board"; -+ compatible = "st,stm32mp157f-dk2", "st,stm32mp157"; -+ -+ aliases { -+ ethernet0 = ðernet0; -+ serial0 = &uart4; -+ serial1 = &usart3; -+ serial2 = &uart7; -+ serial3 = &usart2; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@da000000 { -+ reg = <0xda000000 0x4000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@0xde000000 { -+ reg = <0xde000000 0x02000000>; -+ no-map; -+ status = "disabled"; -+ }; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&cryp1 { -+ status="okay"; -+}; -+ -+&dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ dsi_in: endpoint { -+ remote-endpoint = <<dc_ep1_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ dsi_out: endpoint { -+ remote-endpoint = <&panel_in>; -+ }; -+ }; -+ }; -+ -+ panel_otm8009a: panel-otm8009a@0 { -+ compatible = "orisetech,otm8009a"; -+ reg = <0>; -+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; -+ power-supply = <&v3v3>; -+ status = "okay"; -+ -+ port { -+ panel_in: endpoint { -+ remote-endpoint = <&dsi_out>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ touchscreen@2a { -+ compatible = "focaltech,ft6236"; -+ reg = <0x2a>; -+ interrupts = <2 2>; -+ interrupt-parent = <&gpiof>; -+ interrupt-controller; -+ touchscreen-size-x = <480>; -+ touchscreen-size-y = <800>; -+ panel = <&panel_otm8009a>; -+ status = "okay"; -+ }; -+ touchscreen@38 { -+ compatible = "focaltech,ft6236"; -+ reg = <0x38>; -+ interrupts = <2 2>; -+ interrupt-parent = <&gpiof>; -+ interrupt-controller; -+ touchscreen-size-x = <480>; -+ touchscreen-size-y = <800>; -+ panel = <&panel_otm8009a>; -+ status = "okay"; -+ }; -+}; -+ -+<dc { -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ltdc_ep1_out: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dsi_in>; -+ }; -+ }; -+}; -+ -+&rtc { -+ st,lsco = ; -+ pinctrl-0 = <&rtc_out2_rmp_pins_a>; -+ pinctrl-names = "default"; -+}; -+ -+/* Wifi */ -+&sdmmc2 { -+ arm,primecell-periphid = <0x10153180>; -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc2_b4_pins_a>; -+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; -+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; -+ non-removable; -+ st,neg-edge; -+ bus-width = <4>; -+ vmmc-supply = <&v3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ -+/* Bluetooth */ -+&usart2 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&usart2_pins_a>; -+ pinctrl-1 = <&usart2_sleep_pins_a>; -+ pinctrl-2 = <&usart2_idle_pins_a>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <3000000>; -+ vbat-supply = <&v3v3>; -+ vddio-supply = <&v3v3>; -+ }; -+}; -+ -+&optee_memory { -+ status = "okay"; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi -new file mode 100644 -index 0000000..2b8d2af ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157c-ed1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts -new file mode 100644 -index 0000000..6538069 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-ed1.dts -@@ -0,0 +1,56 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xf.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxaa-pinctrl.dtsi" -+#include "stm32mp157-m4-srm.dtsi" -+#include "stm32mp157-m4-srm-pinctrl.dtsi" -+#include "stm32mp15xx-edx.dtsi" -+ -+/ { -+ model = "STMicroelectronics STM32MP157F eval daughter"; -+ compatible = "st,stm32mp157f-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial0 = &uart4; -+ }; -+ -+ reserved-memory { -+ gpu_reserved: gpu@f6000000 { -+ reg = <0xf6000000 0x8000000>; -+ no-map; -+ }; -+ -+ optee_memory: optee@0xfe000000 { -+ reg = <0xfe000000 0x02000000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&cpu1{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&cryp1 { -+ status="okay"; -+}; -+ -+&gpu { -+ contiguous-area = <&gpu_reserved>; -+ status = "okay"; -+}; -+ -+&optee { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi -new file mode 100644 -index 0000000..0e415a1 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright : STMicroelectronics 2019 -+ */ -+ -+#include "stm32mp157c-ev1-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp157f-ev1.dts b/arch/arm/dts/stm32mp157f-ev1.dts -new file mode 100644 -index 0000000..0c18333 ---- /dev/null -+++ b/arch/arm/dts/stm32mp157f-ev1.dts -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+/dts-v1/; -+ -+#include "stm32mp157f-ed1.dts" -+#include "stm32mp15xx-evx.dtsi" -+#include -+#include -+ -+/ { -+ model = "STMicroelectronics STM32MP157F eval daughter on eval mother"; -+ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial1 = &usart3; -+ ethernet0 = ðernet0; -+ }; -+}; -+ -+&dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ dsi_in: endpoint { -+ remote-endpoint = <<dc_ep0_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ dsi_out: endpoint { -+ remote-endpoint = <&dsi_panel_in>; -+ }; -+ }; -+ }; -+ -+ panel_dsi: panel-dsi@0 { -+ compatible = "raydium,rm68200"; -+ reg = <0>; -+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; -+ backlight = <&panel_backlight>; -+ power-supply = <&v3v3>; -+ status = "okay"; -+ -+ port { -+ dsi_panel_in: endpoint { -+ remote-endpoint = <&dsi_out>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ gt9147: goodix_ts@5d { -+ compatible = "goodix,gt9147"; -+ reg = <0x5d>; -+ panel = <&panel_dsi>; -+ pinctrl-0 = <&goodix_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ interrupts = <14 IRQ_TYPE_EDGE_RISING>; -+ interrupt-parent = <&stmfx_pinctrl>; -+ }; -+}; -+ -+&m_can1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&m_can1_pins_a>; -+ pinctrl-1 = <&m_can1_sleep_pins_a>; -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi -deleted file mode 100644 -index 875adf5..0000000 ---- a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi -+++ /dev/null -@@ -1,90 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -- * Author: Alexandre Torgue -- */ -- --#include "stm32mp157-pinctrl.dtsi" --/ { -- soc { -- pinctrl: pin-controller@50002000 { -- st,package = ; -- -- gpioa: gpio@50002000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 0 16>; -- }; -- -- gpiob: gpio@50003000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 16 16>; -- }; -- -- gpioc: gpio@50004000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 32 16>; -- }; -- -- gpiod: gpio@50005000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 48 16>; -- }; -- -- gpioe: gpio@50006000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 64 16>; -- }; -- -- gpiof: gpio@50007000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 80 16>; -- }; -- -- gpiog: gpio@50008000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 96 16>; -- }; -- -- gpioh: gpio@50009000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 112 16>; -- }; -- -- gpioi: gpio@5000a000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 128 16>; -- }; -- -- gpioj: gpio@5000b000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 144 16>; -- }; -- -- gpiok: gpio@5000c000 { -- status = "okay"; -- ngpios = <8>; -- gpio-ranges = <&pinctrl 0 160 8>; -- }; -- }; -- -- pinctrl_z: pin-controller-z@54004000 { -- st,package = ; -- -- gpioz: gpio@54004000 { -- status = "okay"; -- ngpios = <8>; -- gpio-ranges = <&pinctrl_z 0 400 8>; -- }; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi -deleted file mode 100644 -index 961fa12..0000000 ---- a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi -+++ /dev/null -@@ -1,62 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -- * Author: Alexandre Torgue -- */ -- --#include "stm32mp157-pinctrl.dtsi" --/ { -- soc { -- pinctrl: pin-controller@50002000 { -- st,package = ; -- -- gpioa: gpio@50002000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 0 16>; -- }; -- -- gpiob: gpio@50003000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 16 16>; -- }; -- -- gpioc: gpio@50004000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 32 16>; -- }; -- -- gpiod: gpio@50005000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 48 16>; -- }; -- -- gpioe: gpio@50006000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 64 16>; -- }; -- -- gpiof: gpio@50007000 { -- status = "okay"; -- ngpios = <6>; -- gpio-ranges = <&pinctrl 6 86 6>; -- }; -- -- gpiog: gpio@50008000 { -- status = "okay"; -- ngpios = <10>; -- gpio-ranges = <&pinctrl 6 102 10>; -- }; -- -- gpioh: gpio@50009000 { -- status = "okay"; -- ngpios = <2>; -- gpio-ranges = <&pinctrl 0 112 2>; -- }; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi -deleted file mode 100644 -index 26600f1..0000000 ---- a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi -+++ /dev/null -@@ -1,78 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -- * Author: Alexandre Torgue -- */ -- --#include "stm32mp157-pinctrl.dtsi" --/ { -- soc { -- pinctrl: pin-controller@50002000 { -- st,package = ; -- -- gpioa: gpio@50002000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 0 16>; -- }; -- -- gpiob: gpio@50003000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 16 16>; -- }; -- -- gpioc: gpio@50004000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 32 16>; -- }; -- -- gpiod: gpio@50005000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 48 16>; -- }; -- -- gpioe: gpio@50006000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 64 16>; -- }; -- -- gpiof: gpio@50007000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 80 16>; -- }; -- -- gpiog: gpio@50008000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 96 16>; -- }; -- -- gpioh: gpio@50009000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 112 16>; -- }; -- -- gpioi: gpio@5000a000 { -- status = "okay"; -- ngpios = <12>; -- gpio-ranges = <&pinctrl 0 128 12>; -- }; -- }; -- -- pinctrl_z: pin-controller-z@54004000 { -- st,package = ; -- -- gpioz: gpio@54004000 { -- status = "okay"; -- ngpios = <8>; -- gpio-ranges = <&pinctrl_z 0 400 8>; -- }; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi -deleted file mode 100644 -index 910113f..0000000 ---- a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi -+++ /dev/null -@@ -1,62 +0,0 @@ --// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --/* -- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -- * Author: Alexandre Torgue -- */ -- --#include "stm32mp157-pinctrl.dtsi" --/ { -- soc { -- pinctrl: pin-controller@50002000 { -- st,package = ; -- -- gpioa: gpio@50002000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 0 16>; -- }; -- -- gpiob: gpio@50003000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 16 16>; -- }; -- -- gpioc: gpio@50004000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 32 16>; -- }; -- -- gpiod: gpio@50005000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 48 16>; -- }; -- -- gpioe: gpio@50006000 { -- status = "okay"; -- ngpios = <16>; -- gpio-ranges = <&pinctrl 0 64 16>; -- }; -- -- gpiof: gpio@50007000 { -- status = "okay"; -- ngpios = <6>; -- gpio-ranges = <&pinctrl 6 86 6>; -- }; -- -- gpiog: gpio@50008000 { -- status = "okay"; -- ngpios = <10>; -- gpio-ranges = <&pinctrl 6 102 10>; -- }; -- -- gpioh: gpio@50009000 { -- status = "okay"; -- ngpios = <2>; -- gpio-ranges = <&pinctrl 0 112 2>; -- }; -- }; -- }; --}; -diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi -new file mode 100644 -index 0000000..5ed7e59 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xa.dtsi -@@ -0,0 +1,13 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+&cpu0_opp_table { -+ opp-650000000 { -+ opp-hz = /bits/ 64 <650000000>; -+ opp-microvolt = <1200000>; -+ opp-supported-hw = <0x1>; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi -new file mode 100644 -index 0000000..adc1568 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xc.dtsi -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+#include "stm32mp15xa.dtsi" -+ -+/ { -+ soc { -+ cryp1: cryp@54001000 { -+ compatible = "st,stm32mp1-cryp"; -+ reg = <0x54001000 0x400>; -+ interrupts = ; -+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>; -+ resets = <&scmi0_reset RST_SCMI0_CRYP1>; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi -new file mode 100644 -index 0000000..faa039e ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xd.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+&cpu0_opp_table { -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1350000>; -+ opp-supported-hw = <0x2>; -+ }; -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1200000>; -+ opp-supported-hw = <0x2>; -+ opp-suspend; -+ }; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu-crit { -+ temperature = <105000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ -+ cpu_alert: cpu-alert { -+ temperature = <950000>; -+ hysteresis = <10000>; -+ type = "passive"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = <&cpu0 1 1>; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi -new file mode 100644 -index 0000000..77f50b9 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xf.dtsi -@@ -0,0 +1,20 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+#include "stm32mp15xd.dtsi" -+ -+/ { -+ soc { -+ cryp1: cryp@54001000 { -+ compatible = "st,stm32mp1-cryp"; -+ reg = <0x54001000 0x400>; -+ interrupts = ; -+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>; -+ resets = <&scmi0_reset RST_SCMI0_CRYP1>; -+ status = "disabled"; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi -new file mode 100644 -index 0000000..12f89b3 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2019 Marek Vasut -+ */ -+ -+#include "stm32mp15xx-dhcom-u-boot.dtsi" -diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts -new file mode 100644 -index 0000000..dd98c7a ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts -@@ -0,0 +1,88 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2019 Marek Vasut -+ */ -+ -+#include "stm32mp15xx-dhcom.dtsi" -+ -+/ { -+ model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; -+ compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; -+ -+ aliases { -+ serial0 = &uart4; -+ ethernet0 = ðernet0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ ethernet_vio: vioregulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vio"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+ðernet0 { -+ status = "okay"; -+ pinctrl-0 = <ðernet0_rmii_pins_a>; -+ pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; -+ pinctrl-names = "default", "sleep"; -+ phy-mode = "rmii"; -+ max-speed = <100>; -+ phy-handle = <&phy0>; -+ st,eth_ref_clk_sel; -+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; -+ -+ mdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ -+ phy0: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ ethernet0_rmii_pins_a: rmii-0 { -+ pins1 { -+ pinmux = , /* ETH1_RMII_TXD0 */ -+ , /* ETH1_RMII_TXD1 */ -+ , /* ETH1_RMII_TX_EN */ -+ , /* ETH1_RMII_REF_CLK */ -+ , /* ETH1_MDIO */ -+ ; /* ETH1_MDC */ -+ bias-disable; -+ drive-push-pull; -+ slew-rate = <2>; -+ }; -+ pins2 { -+ pinmux = , /* ETH1_RMII_RXD0 */ -+ , /* ETH1_RMII_RXD1 */ -+ ; /* ETH1_RMII_CRS_DV */ -+ bias-disable; -+ }; -+ }; -+ -+ ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { -+ pins1 { -+ pinmux = , /* ETH1_RMII_TXD0 */ -+ , /* ETH1_RMII_TXD1 */ -+ , /* ETH1_RMII_TX_EN */ -+ , /* ETH1_MDIO */ -+ , /* ETH1_MDC */ -+ , /* ETH1_RMII_RXD0 */ -+ , /* ETH1_RMII_RXD1 */ -+ , /* ETH1_RMII_REF_CLK */ -+ ; /* ETH1_RMII_CRS_DV */ -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi -new file mode 100644 -index 0000000..62c45de ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi -@@ -0,0 +1,249 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) 2019 Marek Vasut -+ */ -+ -+#include -+#include "stm32mp15-u-boot.dtsi" -+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" -+ -+/ { -+ aliases { -+ i2c1 = &i2c2; -+ i2c3 = &i2c4; -+ i2c4 = &i2c5; -+ mmc0 = &sdmmc1; -+ mmc1 = &sdmmc2; -+ spi0 = &qspi; -+ usb0 = &usbotg_hs; -+ }; -+ -+ config { -+ u-boot,boot-led = "heartbeat"; -+ u-boot,error-led = "error"; -+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led { -+ red { -+ label = "error"; -+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ status = "okay"; -+ }; -+ -+ blue { -+ default-state = "on"; -+ }; -+ }; -+}; -+ -+&i2c4 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&i2c4_pins_a { -+ u-boot,dm-pre-reloc; -+ pins { -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&pmic { -+ u-boot,dm-pre-reloc; -+}; -+ -+&flash0 { -+ u-boot,dm-spl; -+}; -+ -+&qspi { -+ u-boot,dm-spl; -+}; -+ -+&qspi_clk_pins_a { -+ u-boot,dm-spl; -+ pins { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&qspi_bk1_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&qspi_bk2_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&rcc { -+ st,clksrc = < -+ CLK_MPU_PLL1P -+ CLK_AXI_PLL2P -+ CLK_MCU_PLL3P -+ CLK_PLL12_HSE -+ CLK_PLL3_HSE -+ CLK_PLL4_HSE -+ CLK_RTC_LSE -+ CLK_MCO1_DISABLED -+ CLK_MCO2_DISABLED -+ >; -+ -+ st,clkdiv = < -+ 1 /*MPU*/ -+ 0 /*AXI*/ -+ 0 /*MCU*/ -+ 1 /*APB1*/ -+ 1 /*APB2*/ -+ 1 /*APB3*/ -+ 1 /*APB4*/ -+ 2 /*APB5*/ -+ 23 /*RTC*/ -+ 0 /*MCO1*/ -+ 0 /*MCO2*/ -+ >; -+ -+ st,pkcs = < -+ CLK_CKPER_HSE -+ CLK_FMC_ACLK -+ CLK_QSPI_ACLK -+ CLK_ETH_PLL4P -+ CLK_SDMMC12_PLL4P -+ CLK_DSI_DSIPLL -+ CLK_STGEN_HSE -+ CLK_USBPHY_HSE -+ CLK_SPI2S1_PLL3Q -+ CLK_SPI2S23_PLL3Q -+ CLK_SPI45_HSI -+ CLK_SPI6_HSI -+ CLK_I2C46_HSI -+ CLK_SDMMC3_PLL4P -+ CLK_USBO_USBPHY -+ CLK_ADC_CKPER -+ CLK_CEC_LSE -+ CLK_I2C12_HSI -+ CLK_I2C35_HSI -+ CLK_UART1_HSI -+ CLK_UART24_HSI -+ CLK_UART35_HSI -+ CLK_UART6_HSI -+ CLK_UART78_HSI -+ CLK_SPDIF_PLL4P -+ CLK_FDCAN_PLL4R -+ CLK_SAI1_PLL3Q -+ CLK_SAI2_PLL3Q -+ CLK_SAI3_PLL3Q -+ CLK_SAI4_PLL3Q -+ CLK_RNG1_LSI -+ CLK_RNG2_LSI -+ CLK_LPTIM1_PCLK1 -+ CLK_LPTIM23_PCLK3 -+ CLK_LPTIM45_LSE -+ >; -+ -+ /* VCO = 1300.0 MHz => P = 650 (CPU) */ -+ pll1: st,pll@0 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <0>; -+ cfg = < 2 80 0 0 0 PQR(1,0,0) >; -+ frac = < 0x800 >; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ -+ pll2: st,pll@1 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <1>; -+ cfg = < 2 65 1 0 0 PQR(1,1,1) >; -+ frac = < 0x1400 >; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ -+ pll3: st,pll@2 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <2>; -+ cfg = < 1 33 1 16 36 PQR(1,1,1) >; -+ frac = < 0x1a04 >; -+ u-boot,dm-pre-reloc; -+ }; -+ -+ /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ -+ pll4: st,pll@3 { -+ compatible = "st,stm32mp1-pll"; -+ reg = <3>; -+ cfg = < 1 49 11 11 11 PQR(1,1,1) >; -+ u-boot,dm-pre-reloc; -+ }; -+}; -+ -+&sdmmc1 { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc1_b4_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc1_dir_pins_a { -+ u-boot,dm-spl; -+ pins1 { -+ u-boot,dm-spl; -+ }; -+ pins2 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc2 { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc2_b4_pins_a { -+ u-boot,dm-spl; -+ pins { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&sdmmc2_d47_pins_a { -+ u-boot,dm-spl; -+ pins { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&uart4 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&uart4_pins_a { -+ u-boot,dm-pre-reloc; -+ pins1 { -+ u-boot,dm-pre-reloc; -+ }; -+ pins2 { -+ u-boot,dm-pre-reloc; -+ /* pull-up on rx to avoid floating level */ -+ bias-pull-up; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi -new file mode 100644 -index 0000000..31da41b ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi -@@ -0,0 +1,379 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) 2019 Marek Vasut -+ */ -+/dts-v1/; -+ -+#include "stm32mp157.dtsi" -+#include "stm32mp15xc.dtsi" -+#include "stm32mp15-pinctrl.dtsi" -+#include "stm32mp15xxaa-pinctrl.dtsi" -+#include -+#include -+ -+/ { -+ memory@c0000000 { -+ device_type = "memory"; -+ reg = <0xC0000000 0x40000000>; -+ }; -+}; -+ -+&cec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cec_pins_a>; -+ status = "okay"; -+}; -+ -+&dcmi { -+ status = "okay"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&dcmi_pins_a>; -+ pinctrl-1 = <&dcmi_sleep_pins_a>; -+}; -+ -+&dts { -+ status = "okay"; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+}; -+ -+&i2c4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4_pins_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ -+ pmic: stpmic@33 { -+ compatible = "st,stpmic1"; -+ reg = <0x33>; -+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ status = "okay"; -+ -+ regulators { -+ compatible = "st,stpmic1-regulators"; -+ ldo1-supply = <&v3v3>; -+ ldo2-supply = <&v3v3>; -+ ldo3-supply = <&vdd_ddr>; -+ ldo5-supply = <&v3v3>; -+ ldo6-supply = <&v3v3>; -+ pwr_sw1-supply = <&bst_out>; -+ pwr_sw2-supply = <&bst_out>; -+ -+ vddcore: buck1 { -+ regulator-name = "vddcore"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_ddr: buck2 { -+ regulator-name = "vdd_ddr"; -+ regulator-min-microvolt = <1350000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd: buck3 { -+ regulator-name = "vdd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ st,mask-reset; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ v3v3: buck4 { -+ regulator-name = "v3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ regulator-initial-mode = <0>; -+ }; -+ -+ vdda: ldo1 { -+ regulator-name = "vdda"; -+ regulator-min-microvolt = <2900000>; -+ regulator-max-microvolt = <2900000>; -+ interrupts = ; -+ }; -+ -+ v2v8: ldo2 { -+ regulator-name = "v2v8"; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ interrupts = ; -+ }; -+ -+ vtt_ddr: ldo3 { -+ regulator-name = "vtt_ddr"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <750000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_usb: ldo4 { -+ regulator-name = "vdd_usb"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ interrupts = ; -+ }; -+ -+ vdd_sd: ldo5 { -+ regulator-name = "vdd_sd"; -+ regulator-min-microvolt = <2900000>; -+ regulator-max-microvolt = <2900000>; -+ interrupts = ; -+ regulator-boot-on; -+ }; -+ -+ v1v8: ldo6 { -+ regulator-name = "v1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ interrupts = ; -+ }; -+ -+ vref_ddr: vref_ddr { -+ regulator-name = "vref_ddr"; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ bst_out: boost { -+ regulator-name = "bst_out"; -+ interrupts = ; -+ }; -+ -+ vbus_otg: pwr_sw1 { -+ regulator-name = "vbus_otg"; -+ interrupts = ; -+ }; -+ -+ vbus_sw: pwr_sw2 { -+ regulator-name = "vbus_sw"; -+ interrupts = ; -+ regulator-active-discharge; -+ }; -+ }; -+ -+ onkey { -+ compatible = "st,stpmic1-onkey"; -+ interrupts = , ; -+ interrupt-names = "onkey-falling", "onkey-rising"; -+ power-off-time-sec = <10>; -+ status = "okay"; -+ }; -+ -+ watchdog { -+ compatible = "st,stpmic1-wdt"; -+ status = "disabled"; -+ }; -+ }; -+ -+ eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+}; -+ -+&i2c5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c5_pins_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+}; -+ -+&ipcc { -+ status = "okay"; -+}; -+ -+&iwdg2 { -+ timeout-sec = <32>; -+ status = "okay"; -+}; -+ -+&m4_rproc { -+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; -+ mbox-names = "vq0", "vq1", "shutdown"; -+ status = "okay"; -+}; -+ -+&pwr_regulators { -+ vdd-supply = <&vdd>; -+ vdd_3v3_usbfs-supply = <&vdd_usb>; -+}; -+ -+&qspi { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; -+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; -+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ flash0: mx66l51235l@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-rx-bus-width = <4>; -+ spi-max-frequency = <108000000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ -+ flash1: mx66l51235l@1 { -+ compatible = "jedec,spi-nor"; -+ reg = <1>; -+ spi-rx-bus-width = <4>; -+ spi-max-frequency = <108000000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+}; -+ -+&rng1 { -+ status = "okay"; -+}; -+ -+&rtc { -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; -+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; -+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; -+ broken-cd; -+ st,sig-dir; -+ st,neg-edge; -+ st,use-ckin; -+ bus-width = <4>; -+ vmmc-supply = <&vdd_sd>; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ st,sig-dir; -+ st,neg-edge; -+ bus-width = <8>; -+ vmmc-supply = <&v3v3>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins_a>; -+ status = "disabled"; -+}; -+ -+&timers2 { -+ /* spare dmas for other usage (un-delete to enable pwm capture) */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm2_pins_a>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ }; -+ timer@1 { -+ status = "okay"; -+ }; -+}; -+ -+&timers6 { -+ status = "okay"; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ timer@5 { -+ status = "okay"; -+ }; -+}; -+ -+&timers8 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm8_pins_a>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ }; -+ timer@7 { -+ status = "okay"; -+ }; -+}; -+ -+&timers12 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm12_pins_a>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ }; -+ timer@11 { -+ status = "okay"; -+ }; -+}; -+ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart4_pins_a>; -+ status = "okay"; -+}; -+ -+&usbh_ehci { -+ phys = <&usbphyc_port0>; -+ phy-names = "usb"; -+ status = "okay"; -+}; -+ -+&usbotg_hs { -+ dr_mode = "peripheral"; -+ phys = <&usbphyc_port1 0>; -+ phy-names = "usb2-phy"; -+ vbus-supply = <&vbus_otg>; -+ status = "okay"; -+}; -+ -+&usbphyc { -+ status = "okay"; -+}; -+ -+&usbphyc_port0 { -+ phy-supply = <&vdd_usb>; -+}; -+ -+&usbphyc_port1 { -+ phy-supply = <&vdd_usb>; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi -new file mode 100644 -index 0000000..3516938 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi -@@ -0,0 +1,768 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue for STMicroelectronics. -+ */ -+ -+#include "stm32mp157-m4-srm.dtsi" -+#include "stm32mp157-m4-srm-pinctrl.dtsi" -+#include -+ -+/ { -+ memory@c0000000 { -+ device_type = "memory"; -+ reg = <0xc0000000 0x20000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ mcuram2: mcuram2@10000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10000000 0x40000>; -+ no-map; -+ }; -+ -+ vdev0vring0: vdev0vring0@10040000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10040000 0x1000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@10041000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10041000 0x1000>; -+ no-map; -+ }; -+ -+ vdev0buffer: vdev0buffer@10042000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10042000 0x4000>; -+ no-map; -+ }; -+ -+ mcuram: mcuram@30000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x30000000 0x40000>; -+ no-map; -+ }; -+ -+ retram: retram@38000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x38000000 0x10000>; -+ no-map; -+ }; -+ }; -+ -+ led { -+ compatible = "gpio-leds"; -+ blue { -+ label = "heartbeat"; -+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ default-state = "off"; -+ }; -+ }; -+ -+ sound { -+ compatible = "audio-graph-card"; -+ label = "STM32MP1-DK"; -+ routing = -+ "Playback" , "MCLK", -+ "Capture" , "MCLK", -+ "MICL" , "Mic Bias"; -+ dais = <&sai2a_port &sai2b_port &i2s2_port>; -+ status = "okay"; -+ }; -+ -+ usb_phy_tuning: usb-phy-tuning { -+ st,hs-dc-level = <2>; -+ st,fs-rftime-tuning; -+ st,hs-rftime-reduction; -+ st,hs-current-trim = <15>; -+ st,hs-impedance-trim = <1>; -+ st,squelch-level = <3>; -+ st,hs-rx-offset = <2>; -+ st,no-lsfs-sc; -+ }; -+ -+ vin: vin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vin"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&adc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; -+ vdd-supply = <&vdd>; -+ vdda-supply = <&vdd>; -+ vref-supply = <&vrefbuf>; -+ status = "disabled"; -+ adc1: adc@0 { -+ /* -+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. -+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: -+ * 5 * (56 + 47kOhms) * 5pF => 2.5us. -+ * Use arbitrary margin here (e.g. 5us). -+ */ -+ st,min-sample-time-nsecs = <5000>; -+ /* AIN connector, USB Type-C CC1 & CC2 */ -+ st,adc-channels = <0 1 6 13 18 19>; -+ status = "okay"; -+ }; -+ adc2: adc@100 { -+ /* AIN connector, USB Type-C CC1 & CC2 */ -+ st,adc-channels = <0 1 2 6 18 19>; -+ st,min-sample-time-nsecs = <5000>; -+ status = "okay"; -+ }; -+}; -+ -+&cec { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&cec_pins_b>; -+ pinctrl-1 = <&cec_pins_sleep_b>; -+ status = "okay"; -+}; -+ -+&cpu0{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&cpu1{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&crc1 { -+ status = "okay"; -+}; -+ -+&dma1 { -+ sram = <&dma_pool>; -+}; -+ -+&dma2 { -+ sram = <&dma_pool>; -+}; -+ -+&dts { -+ status = "okay"; -+}; -+ -+ðernet0 { -+ status = "okay"; -+ pinctrl-0 = <ðernet0_rgmii_pins_a>; -+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; -+ pinctrl-names = "default", "sleep"; -+ phy-mode = "rgmii-id"; -+ max-speed = <1000>; -+ phy-handle = <&phy0>; -+ -+ mdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+}; -+ -+&gpu { -+ contiguous-area = <&gpu_reserved>; -+ status = "okay"; -+}; -+ -+&hash1 { -+ status = "okay"; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c1_pins_a>; -+ pinctrl-1 = <&i2c1_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <100>; -+ i2c-scl-falling-time-ns = <7>; -+ status = "okay"; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ -+ hdmi-transmitter@39 { -+ compatible = "sil,sii9022"; -+ reg = <0x39>; -+ iovcc-supply = <&v3v3_hdmi>; -+ cvcc12-supply = <&v1v2_hdmi>; -+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; -+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-parent = <&gpiog>; -+ #sound-dai-cells = <0>; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ sii9022_in: endpoint { -+ remote-endpoint = <<dc_ep0_out>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ sii9022_tx_endpoint: endpoint { -+ remote-endpoint = <&i2s2_endpoint>; -+ }; -+ }; -+ }; -+ }; -+ -+ cs42l51: cs42l51@4a { -+ compatible = "cirrus,cs42l51"; -+ reg = <0x4a>; -+ #sound-dai-cells = <0>; -+ VL-supply = <&v3v3>; -+ VD-supply = <&v1v8_audio>; -+ VA-supply = <&v1v8_audio>; -+ VAHP-supply = <&v1v8_audio>; -+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; -+ clocks = <&sai2a>; -+ clock-names = "MCLK"; -+ status = "okay"; -+ -+ cs42l51_port: port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cs42l51_tx_endpoint: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&sai2a_endpoint>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ cs42l51_rx_endpoint: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&sai2b_endpoint>; -+ frame-master; -+ bitclock-master; -+ }; -+ }; -+ }; -+}; -+ -+&i2c4 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c4_pins_a>; -+ pinctrl-1 = <&i2c4_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ clock-frequency = <400000>; -+ status = "okay"; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ -+ stusb1600@28 { -+ compatible = "st,stusb1600"; -+ reg = <0x28>; -+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-parent = <&gpioi>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&stusb1600_pins_a>; -+ status = "okay"; -+ vdd-supply = <&vin>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ power-role = "dual"; -+ power-opmode = "default"; -+ -+ port { -+ con_usbotg_hs_ep: endpoint { -+ remote-endpoint = <&usbotg_hs_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ pmic: stpmic@33 { -+ compatible = "st,stpmic1"; -+ reg = <0x33>; -+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ status = "okay"; -+ -+ regulators { -+ compatible = "st,stpmic1-regulators"; -+ buck1-supply = <&vin>; -+ buck2-supply = <&vin>; -+ buck3-supply = <&vin>; -+ buck4-supply = <&vin>; -+ ldo1-supply = <&v3v3>; -+ ldo2-supply = <&vin>; -+ ldo3-supply = <&vdd_ddr>; -+ ldo4-supply = <&vin>; -+ ldo5-supply = <&vin>; -+ ldo6-supply = <&v3v3>; -+ vref_ddr-supply = <&vin>; -+ boost-supply = <&vin>; -+ pwr_sw1-supply = <&bst_out>; -+ pwr_sw2-supply = <&bst_out>; -+ -+ vddcore: buck1 { -+ regulator-name = "vddcore"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_ddr: buck2 { -+ regulator-name = "vdd_ddr"; -+ regulator-min-microvolt = <1350000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd: buck3 { -+ regulator-name = "vdd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ st,mask-reset; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ v3v3: buck4 { -+ regulator-name = "v3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ regulator-initial-mode = <0>; -+ }; -+ -+ v1v8_audio: ldo1 { -+ regulator-name = "v1v8_audio"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ interrupts = ; -+ }; -+ -+ v3v3_hdmi: ldo2 { -+ regulator-name = "v3v3_hdmi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ interrupts = ; -+ }; -+ -+ vtt_ddr: ldo3 { -+ regulator-name = "vtt_ddr"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <750000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_usb: ldo4 { -+ regulator-name = "vdd_usb"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ interrupts = ; -+ regulator-always-on; -+ }; -+ -+ vdda: ldo5 { -+ regulator-name = "vdda"; -+ regulator-min-microvolt = <2900000>; -+ regulator-max-microvolt = <2900000>; -+ interrupts = ; -+ regulator-boot-on; -+ }; -+ -+ v1v2_hdmi: ldo6 { -+ regulator-name = "v1v2_hdmi"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ interrupts = ; -+ }; -+ -+ vref_ddr: vref_ddr { -+ regulator-name = "vref_ddr"; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ bst_out: boost { -+ regulator-name = "bst_out"; -+ interrupts = ; -+ }; -+ -+ vbus_otg: pwr_sw1 { -+ regulator-name = "vbus_otg"; -+ interrupts = ; -+ }; -+ -+ vbus_sw: pwr_sw2 { -+ regulator-name = "vbus_sw"; -+ interrupts = ; -+ regulator-active-discharge = <1>; -+ }; -+ }; -+ -+ onkey { -+ compatible = "st,stpmic1-onkey"; -+ interrupts = , ; -+ interrupt-names = "onkey-falling", "onkey-rising"; -+ power-off-time-sec = <10>; -+ status = "okay"; -+ }; -+ -+ watchdog { -+ compatible = "st,stpmic1-wdt"; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c5_pins_a>; -+ pinctrl-1 = <&i2c5_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ clock-frequency = <400000>; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+}; -+ -+&i2s2 { -+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+ clock-names = "pclk", "i2sclk", "x8k", "x11k"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2s2_pins_a>; -+ pinctrl-1 = <&i2s2_pins_sleep_a>; -+ status = "okay"; -+ -+ i2s2_port: port { -+ i2s2_endpoint: endpoint { -+ remote-endpoint = <&sii9022_tx_endpoint>; -+ format = "i2s"; -+ mclk-fs = <256>; -+ }; -+ }; -+}; -+ -+&ipcc { -+ status = "okay"; -+}; -+ -+&iwdg2 { -+ timeout-sec = <32>; -+ status = "okay"; -+}; -+ -+<dc { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <<dc_pins_a>; -+ pinctrl-1 = <<dc_pins_sleep_a>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ltdc_ep0_out: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&sii9022_in>; -+ }; -+ }; -+}; -+ -+&m4_rproc { -+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, -+ <&vdev0vring1>, <&vdev0buffer>; -+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; -+ mbox-names = "vq0", "vq1", "shutdown"; -+ interrupt-parent = <&exti>; -+ interrupts = <68 1>; -+ wakeup-source; -+ status = "okay"; -+}; -+ -+&pwr_regulators { -+ vdd-supply = <&vdd>; -+ vdd_3v3_usbfs-supply = <&vdd_usb>; -+}; -+ -+&rng1 { -+ status = "okay"; -+}; -+ -+&rtc { -+ status = "okay"; -+}; -+ -+&sai2 { -+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+ clock-names = "pclk", "x8k", "x11k"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; -+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; -+ status = "okay"; -+ -+ sai2a: audio-controller@4400b004 { -+ #clock-cells = <0>; -+ dma-names = "tx"; -+ clocks = <&rcc SAI2_K>; -+ clock-names = "sai_ck"; -+ status = "okay"; -+ -+ sai2a_port: port { -+ sai2a_endpoint: endpoint { -+ remote-endpoint = <&cs42l51_tx_endpoint>; -+ format = "i2s"; -+ mclk-fs = <256>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <32>; -+ }; -+ }; -+ }; -+ -+ sai2b: audio-controller@4400b024 { -+ dma-names = "rx"; -+ st,sync = <&sai2a 2>; -+ clocks = <&rcc SAI2_K>, <&sai2a>; -+ clock-names = "sai_ck", "MCLK"; -+ status = "okay"; -+ -+ sai2b_port: port { -+ sai2b_endpoint: endpoint { -+ remote-endpoint = <&cs42l51_rx_endpoint>; -+ format = "i2s"; -+ mclk-fs = <256>; -+ dai-tdm-slot-num = <2>; -+ dai-tdm-slot-width = <32>; -+ }; -+ }; -+ }; -+}; -+ -+&sdmmc1 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc1_b4_pins_a>; -+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>; -+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; -+ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ disable-wp; -+ st,neg-edge; -+ bus-width = <4>; -+ vmmc-supply = <&v3v3>; -+ status = "okay"; -+}; -+ -+&sdmmc3 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc3_b4_pins_a>; -+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>; -+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; -+ broken-cd; -+ st,neg-edge; -+ bus-width = <4>; -+ vmmc-supply = <&v3v3>; -+ status = "disabled"; -+}; -+ -+&spi4 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spi4_pins_a>; -+ pinctrl-1 = <&spi4_sleep_pins_a>; -+ status = "disabled"; -+}; -+ -+&spi5 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spi5_pins_a>; -+ pinctrl-1 = <&spi5_sleep_pins_a>; -+ status = "disabled"; -+}; -+ -+&sram { -+ dma_pool: dma_pool@0 { -+ reg = <0x50000 0x10000>; -+ pool; -+ }; -+}; -+ -+&timers1 { -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm1_pins_a>; -+ pinctrl-1 = <&pwm1_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@0 { -+ status = "okay"; -+ }; -+}; -+ -+&timers3 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm3_pins_a>; -+ pinctrl-1 = <&pwm3_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@2 { -+ status = "okay"; -+ }; -+}; -+ -+&timers4 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; -+ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@3 { -+ status = "okay"; -+ }; -+}; -+ -+&timers5 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm5_pins_a>; -+ pinctrl-1 = <&pwm5_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@4 { -+ status = "okay"; -+ }; -+}; -+ -+&timers6 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ timer@5 { -+ status = "okay"; -+ }; -+}; -+ -+&timers12 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm12_pins_a>; -+ pinctrl-1 = <&pwm12_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@11 { -+ status = "okay"; -+ }; -+}; -+ -+&uart4 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&uart4_pins_a>; -+ pinctrl-1 = <&uart4_sleep_pins_a>; -+ pinctrl-2 = <&uart4_idle_pins_a>; -+ pinctrl-3 = <&uart4_pins_a>; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "okay"; -+}; -+ -+&uart7 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&uart7_pins_b>; -+ pinctrl-1 = <&uart7_sleep_pins_b>; -+ pinctrl-2 = <&uart7_idle_pins_b>; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+}; -+ -+&usart3 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&usart3_pins_b>; -+ pinctrl-1 = <&usart3_sleep_pins_b>; -+ pinctrl-2 = <&usart3_idle_pins_b>; -+ uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usbh_ehci { -+ phys = <&usbphyc_port0>; -+ status = "okay"; -+}; -+ -+&usbotg_hs { -+ phys = <&usbphyc_port1 0>; -+ phy-names = "usb2-phy"; -+ usb-role-switch; -+ status = "okay"; -+ -+ port { -+ usbotg_hs_ep: endpoint { -+ remote-endpoint = <&con_usbotg_hs_ep>; -+ }; -+ }; -+}; -+ -+&usbphyc { -+ status = "okay"; -+}; -+ -+&usbphyc_port0 { -+ phy-supply = <&vdd_usb>; -+ st,phy-tuning = <&usb_phy_tuning>; -+}; -+ -+&usbphyc_port1 { -+ phy-supply = <&vdd_usb>; -+ st,phy-tuning = <&usb_phy_tuning>; -+}; -+ -+&vrefbuf { -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ vdda-supply = <&vdd>; -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi -new file mode 100644 -index 0000000..7ed6b14 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi -@@ -0,0 +1,408 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -+ * Author: Ludovic Barre for STMicroelectronics. -+ */ -+ -+#include -+#include -+ -+/ { -+ memory@c0000000 { -+ device_type = "memory"; -+ reg = <0xC0000000 0x40000000>; -+ }; -+ -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ mcuram2: mcuram2@10000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10000000 0x40000>; -+ no-map; -+ }; -+ -+ vdev0vring0: vdev0vring0@10040000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10040000 0x1000>; -+ no-map; -+ }; -+ -+ vdev0vring1: vdev0vring1@10041000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10041000 0x1000>; -+ no-map; -+ }; -+ -+ vdev0buffer: vdev0buffer@10042000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x10042000 0x4000>; -+ no-map; -+ }; -+ -+ mcuram: mcuram@30000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x30000000 0x40000>; -+ no-map; -+ }; -+ -+ retram: retram@38000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0x38000000 0x10000>; -+ no-map; -+ }; -+ }; -+ -+ led { -+ compatible = "gpio-leds"; -+ blue { -+ label = "heartbeat"; -+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ default-state = "off"; -+ }; -+ }; -+ -+ sd_switch: regulator-sd_switch { -+ compatible = "regulator-gpio"; -+ regulator-name = "sd_switch"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <2900000>; -+ regulator-type = "voltage"; -+ regulator-always-on; -+ -+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0>; -+ states = <1800000 0x1 2900000 0x0>; -+ }; -+ -+ vin: vin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vin"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&adc { -+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ -+ pinctrl-0 = <&adc1_in6_pins_a>; -+ pinctrl-names = "default"; -+ vdd-supply = <&vdd>; -+ vdda-supply = <&vdda>; -+ vref-supply = <&vdda>; -+ status = "disabled"; -+ adc1: adc@0 { -+ st,adc-channels = <0 1 6>; -+ /* 16.5 ck_cycles sampling time */ -+ st,min-sample-time-nsecs = <400>; -+ status = "okay"; -+ }; -+}; -+ -+&cpu0{ -+ cpu-supply = <&vddcore>; -+}; -+ -+&crc1 { -+ status = "okay"; -+}; -+ -+&dac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; -+ vref-supply = <&vdda>; -+ status = "disabled"; -+ dac1: dac@1 { -+ status = "okay"; -+ }; -+ dac2: dac@2 { -+ status = "okay"; -+ }; -+}; -+ -+&dma1 { -+ sram = <&dma_pool>; -+}; -+ -+&dma2 { -+ sram = <&dma_pool>; -+}; -+ -+&dts { -+ status = "okay"; -+}; -+ -+&hash1 { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c4_pins_a>; -+ pinctrl-1 = <&i2c4_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ clock-frequency = <400000>; -+ status = "okay"; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ -+ pmic: stpmic@33 { -+ compatible = "st,stpmic1"; -+ reg = <0x33>; -+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ status = "okay"; -+ -+ regulators { -+ compatible = "st,stpmic1-regulators"; -+ buck1-supply = <&vin>; -+ buck2-supply = <&vin>; -+ buck3-supply = <&vin>; -+ buck4-supply = <&vin>; -+ ldo1-supply = <&v3v3>; -+ ldo2-supply = <&v3v3>; -+ ldo3-supply = <&vdd_ddr>; -+ ldo4-supply = <&vin>; -+ ldo5-supply = <&v3v3>; -+ ldo6-supply = <&v3v3>; -+ vref_ddr-supply = <&vin>; -+ boost-supply = <&vin>; -+ pwr_sw1-supply = <&bst_out>; -+ pwr_sw2-supply = <&bst_out>; -+ -+ vddcore: buck1 { -+ regulator-name = "vddcore"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_ddr: buck2 { -+ regulator-name = "vdd_ddr"; -+ regulator-min-microvolt = <1350000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ vdd: buck3 { -+ regulator-name = "vdd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ st,mask-reset; -+ regulator-initial-mode = <0>; -+ regulator-over-current-protection; -+ }; -+ -+ v3v3: buck4 { -+ regulator-name = "v3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ regulator-initial-mode = <0>; -+ }; -+ -+ vdda: ldo1 { -+ regulator-name = "vdda"; -+ regulator-min-microvolt = <2900000>; -+ regulator-max-microvolt = <2900000>; -+ interrupts = ; -+ }; -+ -+ v2v8: ldo2 { -+ regulator-name = "v2v8"; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ interrupts = ; -+ }; -+ -+ vtt_ddr: ldo3 { -+ regulator-name = "vtt_ddr"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <750000>; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ vdd_usb: ldo4 { -+ regulator-name = "vdd_usb"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ interrupts = ; -+ regulator-always-on; -+ }; -+ -+ vdd_sd: ldo5 { -+ regulator-name = "vdd_sd"; -+ regulator-min-microvolt = <2900000>; -+ regulator-max-microvolt = <2900000>; -+ interrupts = ; -+ regulator-boot-on; -+ }; -+ -+ v1v8: ldo6 { -+ regulator-name = "v1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ interrupts = ; -+ }; -+ -+ vref_ddr: vref_ddr { -+ regulator-name = "vref_ddr"; -+ regulator-always-on; -+ regulator-over-current-protection; -+ }; -+ -+ bst_out: boost { -+ regulator-name = "bst_out"; -+ interrupts = ; -+ }; -+ -+ vbus_otg: pwr_sw1 { -+ regulator-name = "vbus_otg"; -+ interrupts = ; -+ }; -+ -+ vbus_sw: pwr_sw2 { -+ regulator-name = "vbus_sw"; -+ interrupts = ; -+ regulator-active-discharge = <1>; -+ }; -+ }; -+ -+ onkey { -+ compatible = "st,stpmic1-onkey"; -+ interrupts = , ; -+ interrupt-names = "onkey-falling", "onkey-rising"; -+ power-off-time-sec = <10>; -+ status = "okay"; -+ }; -+ -+ watchdog { -+ compatible = "st,stpmic1-wdt"; -+ status = "disabled"; -+ }; -+ }; -+}; -+ -+&ipcc { -+ status = "okay"; -+}; -+ -+&iwdg2 { -+ timeout-sec = <32>; -+ status = "okay"; -+}; -+ -+&m4_rproc { -+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, -+ <&vdev0vring1>, <&vdev0buffer>; -+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; -+ mbox-names = "vq0", "vq1", "shutdown"; -+ interrupt-parent = <&exti>; -+ interrupts = <68 1>; -+ wakeup-source; -+ status = "okay"; -+}; -+ -+&pwr_regulators { -+ vdd-supply = <&vdd>; -+ vdd_3v3_usbfs-supply = <&vdd_usb>; -+}; -+ -+&rng1 { -+ status = "okay"; -+}; -+ -+&rtc { -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; -+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; -+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; -+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ disable-wp; -+ st,sig-dir; -+ st,neg-edge; -+ st,use-ckin; -+ bus-width = <4>; -+ vmmc-supply = <&vdd_sd>; -+ vqmmc-supply = <&sd_switch>; -+ sd-uhs-sdr12; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-ddr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; -+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; -+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ st,neg-edge; -+ bus-width = <8>; -+ vmmc-supply = <&v3v3>; -+ vqmmc-supply = <&vdd>; -+ mmc-ddr-3_3v; -+ status = "okay"; -+}; -+ -+&sram { -+ dma_pool: dma_pool@0 { -+ reg = <0x50000 0x10000>; -+ pool; -+ }; -+}; -+ -+&timers6 { -+ status = "okay"; -+ /* spare dmas for other usage */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ timer@5 { -+ status = "okay"; -+ }; -+}; -+ -+&uart4 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&uart4_pins_a>; -+ pinctrl-1 = <&uart4_sleep_pins_a>; -+ pinctrl-2 = <&uart4_idle_pins_a>; -+ pinctrl-3 = <&uart4_pins_a>; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "okay"; -+}; -+ -+&usbotg_hs { -+ vbus-supply = <&vbus_otg>; -+}; -+ -+&usbphyc_port0 { -+ phy-supply = <&vdd_usb>; -+}; -+ -+&usbphyc_port1 { -+ phy-supply = <&vdd_usb>; -+}; -diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi -new file mode 100644 -index 0000000..07cb93d ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi -@@ -0,0 +1,680 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved -+ * Author: Ludovic Barre for STMicroelectronics. -+ */ -+ -+#include -+#include -+ -+/ { -+ clocks { -+ clk_ext_camera: clk-ext-camera { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ }; -+ }; -+ -+ joystick { -+ compatible = "gpio-keys"; -+ #size-cells = <0>; -+ pinctrl-0 = <&joystick_pins>; -+ pinctrl-names = "default"; -+ button-0 { -+ label = "JoySel"; -+ linux,code = ; -+ interrupt-parent = <&stmfx_pinctrl>; -+ interrupts = <0 IRQ_TYPE_EDGE_RISING>; -+ }; -+ button-1 { -+ label = "JoyDown"; -+ linux,code = ; -+ interrupt-parent = <&stmfx_pinctrl>; -+ interrupts = <1 IRQ_TYPE_EDGE_RISING>; -+ }; -+ button-2 { -+ label = "JoyLeft"; -+ linux,code = ; -+ interrupt-parent = <&stmfx_pinctrl>; -+ interrupts = <2 IRQ_TYPE_EDGE_RISING>; -+ }; -+ button-3 { -+ label = "JoyRight"; -+ linux,code = ; -+ interrupt-parent = <&stmfx_pinctrl>; -+ interrupts = <3 IRQ_TYPE_EDGE_RISING>; -+ }; -+ button-4 { -+ label = "JoyUp"; -+ linux,code = ; -+ interrupt-parent = <&stmfx_pinctrl>; -+ interrupts = <4 IRQ_TYPE_EDGE_RISING>; -+ }; -+ }; -+ -+ panel_backlight: panel-backlight { -+ compatible = "gpio-backlight"; -+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; -+ default-on; -+ status = "okay"; -+ }; -+ -+ spdif_out: spdif-out { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dit"; -+ status = "okay"; -+ -+ spdif_out_port: port { -+ spdif_out_endpoint: endpoint { -+ remote-endpoint = <&sai4a_endpoint>; -+ }; -+ }; -+ }; -+ -+ spdif_in: spdif-in { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dir"; -+ status = "okay"; -+ -+ spdif_in_port: port { -+ spdif_in_endpoint: endpoint { -+ remote-endpoint = <&spdifrx_endpoint>; -+ }; -+ }; -+ }; -+ -+ sound { -+ compatible = "audio-graph-card"; -+ label = "STM32MP1-EV"; -+ routing = -+ "AIF1CLK" , "MCLK1", -+ "AIF2CLK" , "MCLK1", -+ "IN1LN" , "MICBIAS2", -+ "DMIC2DAT" , "MICBIAS1", -+ "DMIC1DAT" , "MICBIAS1"; -+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port -+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>; -+ status = "okay"; -+ }; -+ -+ dmic0: dmic-0 { -+ compatible = "dmic-codec"; -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "dmic0"; -+ status = "okay"; -+ -+ port { -+ dmic0_endpoint: endpoint { -+ remote-endpoint = <&dfsdm_endpoint0>; -+ }; -+ }; -+ }; -+ -+ dmic1: dmic-1 { -+ compatible = "dmic-codec"; -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "dmic1"; -+ status = "okay"; -+ -+ port { -+ dmic1_endpoint: endpoint { -+ remote-endpoint = <&dfsdm_endpoint1>; -+ }; -+ }; -+ }; -+ -+ dmic2: dmic-2 { -+ compatible = "dmic-codec"; -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "dmic2"; -+ status = "okay"; -+ -+ port { -+ dmic2_endpoint: endpoint { -+ remote-endpoint = <&dfsdm_endpoint2>; -+ }; -+ }; -+ }; -+ -+ dmic3: dmic-3 { -+ compatible = "dmic-codec"; -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "dmic3"; -+ status = "okay"; -+ -+ port { -+ dmic3_endpoint: endpoint { -+ remote-endpoint = <&dfsdm_endpoint3>; -+ }; -+ }; -+ }; -+ -+ usb_phy_tuning: usb-phy-tuning { -+ st,hs-dc-level = <2>; -+ st,fs-rftime-tuning; -+ st,hs-rftime-reduction; -+ st,hs-current-trim = <15>; -+ st,hs-impedance-trim = <1>; -+ st,squelch-level = <3>; -+ st,hs-rx-offset = <2>; -+ st,no-lsfs-sc; -+ }; -+}; -+ -+&cec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cec_pins_a>; -+ status = "okay"; -+}; -+ -+&dcmi { -+ status = "okay"; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&dcmi_pins_a>; -+ pinctrl-1 = <&dcmi_sleep_pins_a>; -+ -+ port { -+ dcmi_0: endpoint { -+ remote-endpoint = <&ov5640_0>; -+ bus-width = <8>; -+ hsync-active = <0>; -+ vsync-active = <0>; -+ pclk-sample = <1>; -+ pclk-max-frequency = <77000000>; -+ }; -+ }; -+}; -+ -+&dfsdm { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&dfsdm_clkout_pins_a -+ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>; -+ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a -+ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>; -+ spi-max-frequency = <2048000>; -+ -+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; -+ clock-names = "dfsdm", "audio"; -+ status = "okay"; -+ -+ dfsdm0: filter@0 { -+ compatible = "st,stm32-dfsdm-dmic"; -+ st,adc-channels = <3>; -+ st,adc-channel-names = "dmic_u1"; -+ st,adc-channel-types = "SPI_R"; -+ st,adc-channel-clk-src = "CLKOUT"; -+ st,filter-order = <3>; -+ status = "okay"; -+ -+ asoc_pdm0: dfsdm-dai { -+ compatible = "st,stm32h7-dfsdm-dai"; -+ #sound-dai-cells = <0>; -+ io-channels = <&dfsdm0 0>; -+ status = "okay"; -+ -+ dfsdm0_port: port { -+ dfsdm_endpoint0: endpoint { -+ remote-endpoint = <&dmic0_endpoint>; -+ }; -+ }; -+ }; -+ }; -+ -+ dfsdm1: filter@1 { -+ compatible = "st,stm32-dfsdm-dmic"; -+ st,adc-channels = <1>; -+ st,adc-channel-names = "dmic_u2"; -+ st,adc-channel-types = "SPI_F"; -+ st,adc-channel-clk-src = "CLKOUT"; -+ st,filter-order = <3>; -+ status = "okay"; -+ -+ asoc_pdm1: dfsdm-dai { -+ compatible = "st,stm32h7-dfsdm-dai"; -+ #sound-dai-cells = <0>; -+ io-channels = <&dfsdm1 0>; -+ status = "okay"; -+ -+ dfsdm1_port: port { -+ dfsdm_endpoint1: endpoint { -+ remote-endpoint = <&dmic1_endpoint>; -+ }; -+ }; -+ }; -+ }; -+ -+ dfsdm2: filter@2 { -+ compatible = "st,stm32-dfsdm-dmic"; -+ st,adc-channels = <3>; -+ st,adc-channel-names = "dmic_u3"; -+ st,adc-channel-types = "SPI_F"; -+ st,adc-channel-clk-src = "CLKOUT"; -+ st,filter-order = <3>; -+ status = "okay"; -+ -+ asoc_pdm2: dfsdm-dai { -+ compatible = "st,stm32h7-dfsdm-dai"; -+ #sound-dai-cells = <0>; -+ io-channels = <&dfsdm2 0>; -+ status = "okay"; -+ -+ dfsdm2_port: port { -+ dfsdm_endpoint2: endpoint { -+ remote-endpoint = <&dmic2_endpoint>; -+ }; -+ }; -+ }; -+ }; -+ -+ dfsdm3: filter@3 { -+ compatible = "st,stm32-dfsdm-dmic"; -+ st,adc-channels = <1>; -+ st,adc-channel-names = "dmic_u4"; -+ st,adc-channel-types = "SPI_R"; -+ st,adc-channel-clk-src = "CLKOUT"; -+ st,filter-order = <3>; -+ status = "okay"; -+ -+ asoc_pdm3: dfsdm-dai { -+ compatible = "st,stm32h7-dfsdm-dai"; -+ #sound-dai-cells = <0>; -+ io-channels = <&dfsdm3 0>; -+ status = "okay"; -+ -+ dfsdm3_port: port { -+ dfsdm_endpoint3: endpoint { -+ remote-endpoint = <&dmic3_endpoint>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+ðernet0 { -+ status = "okay"; -+ pinctrl-0 = <ðernet0_rgmii_pins_a>; -+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; -+ pinctrl-names = "default", "sleep"; -+ phy-mode = "rgmii-id"; -+ max-speed = <1000>; -+ phy-handle = <&phy0>; -+ -+ mdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+}; -+ -+&fmc { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&fmc_pins_a>; -+ pinctrl-1 = <&fmc_sleep_pins_a>; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ nand@0 { -+ reg = <0>; -+ nand-on-flash-bbt; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+}; -+ -+&hdp { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>; -+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>; -+ status = "disabled"; -+ -+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) | -+ STM32_HDP(6, HDP6_GPOVAL_6) | -+ STM32_HDP(7, HDP7_GPOVAL_7))>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ pinctrl-1 = <&i2c2_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ -+ wm8994: wm8994@1b { -+ compatible = "wlf,wm8994"; -+ #sound-dai-cells = <0>; -+ reg = <0x1b>; -+ status = "okay"; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ DBVDD-supply = <&vdd>; -+ SPKVDD1-supply = <&vdd>; -+ SPKVDD2-supply = <&vdd>; -+ AVDD2-supply = <&v1v8>; -+ CPVDD-supply = <&v1v8>; -+ -+ wlf,ldoena-always-driven; -+ -+ clocks = <&sai2a>; -+ clock-names = "MCLK1"; -+ -+ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8994_tx_port: port@0 { -+ reg = <0>; -+ wm8994_tx_endpoint: endpoint { -+ remote-endpoint = <&sai2a_endpoint>; -+ }; -+ }; -+ -+ wm8994_rx_port: port@1 { -+ reg = <1>; -+ wm8994_rx_endpoint: endpoint { -+ remote-endpoint = <&sai2b_endpoint>; -+ }; -+ }; -+ }; -+ }; -+ -+ ov5640: camera@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ clocks = <&clk_ext_camera>; -+ clock-names = "xclk"; -+ DOVDD-supply = <&v2v8>; -+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; -+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; -+ rotation = <180>; -+ status = "okay"; -+ -+ port { -+ ov5640_0: endpoint { -+ remote-endpoint = <&dcmi_0>; -+ bus-width = <8>; -+ data-shift = <2>; /* lines 9:2 are used */ -+ hsync-active = <0>; -+ vsync-active = <0>; -+ pclk-sample = <1>; -+ pclk-max-frequency = <77000000>; -+ }; -+ }; -+ }; -+ -+ stmfx: stmfx@42 { -+ compatible = "st,stmfx-0300"; -+ reg = <0x42>; -+ interrupts = <8 IRQ_TYPE_EDGE_RISING>; -+ interrupt-parent = <&gpioi>; -+ vdd-supply = <&v3v3>; -+ -+ stmfx_pinctrl: stmfx-pin-controller { -+ compatible = "st,stmfx-0300-pinctrl"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-ranges = <&stmfx_pinctrl 0 0 24>; -+ -+ goodix_pins: goodix { -+ pins = "gpio14"; -+ bias-pull-down; -+ }; -+ -+ joystick_pins: joystick { -+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; -+ bias-pull-down; -+ }; -+ }; -+ }; -+}; -+ -+&i2c4 { -+ pmic: stpmic@33 { -+ regulators { -+ v1v8: ldo6 { -+ regulator-enable-ramp-delay = <300000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&i2c5_pins_a>; -+ pinctrl-1 = <&i2c5_pins_sleep_a>; -+ i2c-scl-rising-time-ns = <185>; -+ i2c-scl-falling-time-ns = <20>; -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "okay"; -+}; -+ -+<dc { -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ltdc_ep0_out: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&dsi_in>; -+ }; -+ }; -+}; -+ -+&qspi { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; -+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; -+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ flash0: mx66l51235l@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-rx-bus-width = <4>; -+ spi-max-frequency = <108000000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ -+ flash1: mx66l51235l@1 { -+ compatible = "jedec,spi-nor"; -+ reg = <1>; -+ spi-rx-bus-width = <4>; -+ spi-max-frequency = <108000000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+}; -+ -+&sai2 { -+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>; -+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>; -+ clock-names = "pclk", "x8k", "x11k"; -+ status = "okay"; -+ -+ sai2a: audio-controller@4400b004 { -+ #clock-cells = <0>; -+ dma-names = "tx"; -+ clocks = <&rcc SAI2_K>; -+ clock-names = "sai_ck"; -+ status = "okay"; -+ -+ sai2a_port: port { -+ sai2a_endpoint: endpoint { -+ remote-endpoint = <&wm8994_tx_endpoint>; -+ format = "i2s"; -+ mclk-fs = <256>; -+ }; -+ }; -+ }; -+ -+ sai2b: audio-controller@4400b024 { -+ dma-names = "rx"; -+ clocks = <&rcc SAI2_K>, <&sai2a>; -+ clock-names = "sai_ck", "MCLK"; -+ status = "okay"; -+ -+ sai2b_port: port { -+ sai2b_endpoint: endpoint { -+ remote-endpoint = <&wm8994_rx_endpoint>; -+ format = "i2s"; -+ mclk-fs = <256>; -+ }; -+ }; -+ }; -+}; -+ -+&sai4 { -+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>; -+ clock-names = "pclk", "x8k", "x11k"; -+ status = "okay"; -+ -+ sai4a: audio-controller@50027004 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&sai4a_pins_a>; -+ pinctrl-1 = <&sai4a_sleep_pins_a>; -+ dma-names = "tx"; -+ clocks = <&rcc SAI4_K>; -+ clock-names = "sai_ck"; -+ st,iec60958; -+ status = "okay"; -+ -+ sai4a_port: port { -+ sai4a_endpoint: endpoint { -+ remote-endpoint = <&spdif_out_endpoint>; -+ }; -+ }; -+ }; -+}; -+ -+&sdmmc3 { -+ pinctrl-names = "default", "opendrain", "sleep"; -+ pinctrl-0 = <&sdmmc3_b4_pins_a>; -+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>; -+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; -+ vmmc-supply = <&v3v3>; -+ broken-cd; -+ st,neg-edge; -+ bus-width = <4>; -+ status = "disabled"; -+}; -+ -+&spdifrx { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spdifrx_pins_a>; -+ pinctrl-1 = <&spdifrx_sleep_pins_a>; -+ status = "okay"; -+ -+ spdifrx_port: port { -+ spdifrx_endpoint: endpoint { -+ remote-endpoint = <&spdif_in_endpoint>; -+ }; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spi1_pins_a>; -+ pinctrl-1 = <&spi1_sleep_pins_a>; -+ status = "disabled"; -+}; -+ -+&timers2 { -+ /* spare dmas for other usage (un-delete to enable pwm capture) */ -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm2_pins_a>; -+ pinctrl-1 = <&pwm2_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@1 { -+ status = "okay"; -+ }; -+}; -+ -+&timers8 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm8_pins_a>; -+ pinctrl-1 = <&pwm8_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@7 { -+ status = "okay"; -+ }; -+}; -+ -+&timers12 { -+ /delete-property/dmas; -+ /delete-property/dma-names; -+ status = "disabled"; -+ pwm { -+ pinctrl-0 = <&pwm12_pins_a>; -+ pinctrl-1 = <&pwm12_sleep_pins_a>; -+ pinctrl-names = "default", "sleep"; -+ status = "okay"; -+ }; -+ timer@11 { -+ status = "okay"; -+ }; -+}; -+ -+&usart3 { -+ pinctrl-names = "default", "sleep", "idle"; -+ pinctrl-0 = <&usart3_pins_a>; -+ pinctrl-1 = <&usart3_sleep_pins_a>; -+ pinctrl-2 = <&usart3_idle_pins_a>; -+ uart-has-rtscts; -+ status = "disabled"; -+}; -+ -+&usbh_ehci { -+ phys = <&usbphyc_port0>; -+ status = "okay"; -+}; -+ -+&usbotg_hs { -+ pinctrl-0 = <&usbotg_hs_pins_a>; -+ pinctrl-names = "default"; -+ phys = <&usbphyc_port1 0>; -+ phy-names = "usb2-phy"; -+ status = "okay"; -+}; -+ -+&usbphyc { -+ status = "okay"; -+}; -+ -+&usbphyc_port0 { -+ st,phy-tuning = <&usb_phy_tuning>; -+}; -+ -+&usbphyc_port1 { -+ st,phy-tuning = <&usb_phy_tuning>; -+}; -diff --git a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi -new file mode 100644 -index 0000000..64e566b ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi -@@ -0,0 +1,85 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue -+ */ -+ -+&pinctrl { -+ st,package = ; -+ -+ gpioa: gpio@50002000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 0 16>; -+ }; -+ -+ gpiob: gpio@50003000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 16 16>; -+ }; -+ -+ gpioc: gpio@50004000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 32 16>; -+ }; -+ -+ gpiod: gpio@50005000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 48 16>; -+ }; -+ -+ gpioe: gpio@50006000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 64 16>; -+ }; -+ -+ gpiof: gpio@50007000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 80 16>; -+ }; -+ -+ gpiog: gpio@50008000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 96 16>; -+ }; -+ -+ gpioh: gpio@50009000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 112 16>; -+ }; -+ -+ gpioi: gpio@5000a000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 128 16>; -+ }; -+ -+ gpioj: gpio@5000b000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 144 16>; -+ }; -+ -+ gpiok: gpio@5000c000 { -+ status = "okay"; -+ ngpios = <8>; -+ gpio-ranges = <&pinctrl 0 160 8>; -+ }; -+}; -+ -+&pinctrl_z { -+ st,package = ; -+ -+ gpioz: gpio@54004000 { -+ status = "okay"; -+ ngpios = <8>; -+ gpio-ranges = <&pinctrl_z 0 400 8>; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi -new file mode 100644 -index 0000000..d29af89 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue -+ */ -+ -+&pinctrl { -+ st,package = ; -+ -+ gpioa: gpio@50002000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 0 16>; -+ }; -+ -+ gpiob: gpio@50003000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 16 16>; -+ }; -+ -+ gpioc: gpio@50004000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 32 16>; -+ }; -+ -+ gpiod: gpio@50005000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 48 16>; -+ }; -+ -+ gpioe: gpio@50006000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 64 16>; -+ }; -+ -+ gpiof: gpio@50007000 { -+ status = "okay"; -+ ngpios = <6>; -+ gpio-ranges = <&pinctrl 6 86 6>; -+ }; -+ -+ gpiog: gpio@50008000 { -+ status = "okay"; -+ ngpios = <10>; -+ gpio-ranges = <&pinctrl 6 102 10>; -+ }; -+ -+ gpioh: gpio@50009000 { -+ status = "okay"; -+ ngpios = <2>; -+ gpio-ranges = <&pinctrl 0 112 2>; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi -new file mode 100644 -index 0000000..5d8199f ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue -+ */ -+ -+&pinctrl { -+ st,package = ; -+ -+ gpioa: gpio@50002000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 0 16>; -+ }; -+ -+ gpiob: gpio@50003000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 16 16>; -+ }; -+ -+ gpioc: gpio@50004000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 32 16>; -+ }; -+ -+ gpiod: gpio@50005000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 48 16>; -+ }; -+ -+ gpioe: gpio@50006000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 64 16>; -+ }; -+ -+ gpiof: gpio@50007000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 80 16>; -+ }; -+ -+ gpiog: gpio@50008000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 96 16>; -+ }; -+ -+ gpioh: gpio@50009000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 112 16>; -+ }; -+ -+ gpioi: gpio@5000a000 { -+ status = "okay"; -+ ngpios = <12>; -+ gpio-ranges = <&pinctrl 0 128 12>; -+ }; -+}; -+ -+&pinctrl_z { -+ st,package = ; -+ -+ gpioz: gpio@54004000 { -+ status = "okay"; -+ ngpios = <8>; -+ gpio-ranges = <&pinctrl_z 0 400 8>; -+ }; -+}; -diff --git a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi -new file mode 100644 -index 0000000..023f540 ---- /dev/null -+++ b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved -+ * Author: Alexandre Torgue -+ */ -+ -+&pinctrl { -+ st,package = ; -+ -+ gpioa: gpio@50002000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 0 16>; -+ }; -+ -+ gpiob: gpio@50003000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 16 16>; -+ }; -+ -+ gpioc: gpio@50004000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 32 16>; -+ }; -+ -+ gpiod: gpio@50005000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 48 16>; -+ }; -+ -+ gpioe: gpio@50006000 { -+ status = "okay"; -+ ngpios = <16>; -+ gpio-ranges = <&pinctrl 0 64 16>; -+ }; -+ -+ gpiof: gpio@50007000 { -+ status = "okay"; -+ ngpios = <6>; -+ gpio-ranges = <&pinctrl 6 86 6>; -+ }; -+ -+ gpiog: gpio@50008000 { -+ status = "okay"; -+ ngpios = <10>; -+ gpio-ranges = <&pinctrl 6 102 10>; -+ }; -+ -+ gpioh: gpio@50009000 { -+ status = "okay"; -+ ngpios = <2>; -+ gpio-ranges = <&pinctrl 0 112 2>; -+ }; -+}; --- -2.7.4 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.10-stm32mp-r1-DEVICETREE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.10-stm32mp-r1-DEVICETREE.patch new file mode 100644 index 0000000..8f55b7c --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2020.10-stm32mp-r1-DEVICETREE.patch @@ -0,0 +1,7289 @@ +From 4b29a8f65f3b9cf38b49f716b1f1bee094048be8 Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Tue, 16 Mar 2021 08:14:20 +0100 +Subject: [PATCH 4/5] ARM v2020.10-stm32mp-r1 DEVICETREE + +Signed-off-by: Romuald JEANNE +--- + arch/arm/dts/Makefile | 10 +- + arch/arm/dts/stm32mp15-ddr.dtsi | 3 +- + .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 2 +- + .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 2 +- + arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi | 524 +++++++++++++ + arch/arm/dts/stm32mp15-m4-srm.dtsi | 442 +++++++++++ + arch/arm/dts/stm32mp15-no-scmi.dtsi | 157 ++++ + arch/arm/dts/stm32mp15-pinctrl.dtsi | 428 +++++++++-- + arch/arm/dts/stm32mp15-u-boot.dtsi | 141 ++-- + arch/arm/dts/stm32mp151.dtsi | 631 +++++++++++----- + arch/arm/dts/stm32mp153.dtsi | 14 +- + arch/arm/dts/stm32mp157.dtsi | 3 +- + arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 21 +- + arch/arm/dts/stm32mp157a-dk1.dts | 4 +- + arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 228 ++++++ + arch/arm/dts/stm32mp157a-ed1.dts | 32 + + arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi | 62 ++ + arch/arm/dts/stm32mp157a-ev1.dts | 88 +++ + arch/arm/dts/stm32mp157c-dk2.dts | 77 +- + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 215 +----- + arch/arm/dts/stm32mp157c-ed1.dts | 355 +-------- + arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 49 +- + arch/arm/dts/stm32mp157c-ev1.dts | 317 +------- + .../dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 + + arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157d-dk1.dts | 28 + + arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157d-ed1.dts | 33 + + arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157d-ev1.dts | 88 +++ + arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157f-dk2.dts | 157 ++++ + arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157f-ed1.dts | 37 + + arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi | 6 + + arch/arm/dts/stm32mp157f-ev1.dts | 89 +++ + arch/arm/dts/stm32mp15xa.dtsi | 13 + + arch/arm/dts/stm32mp15xc.dtsi | 6 +- + arch/arm/dts/stm32mp15xd.dtsi | 42 ++ + arch/arm/dts/stm32mp15xf.dtsi | 20 + + arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 2 + + arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 2 + + arch/arm/dts/stm32mp15xx-dkx.dtsi | 165 ++++- + arch/arm/dts/stm32mp15xx-edx.dtsi | 413 +++++++++++ + arch/arm/dts/stm32mp15xx-evx.dtsi | 686 ++++++++++++++++++ + 45 files changed, 4407 insertions(+), 1219 deletions(-) + create mode 100644 arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi + create mode 100644 arch/arm/dts/stm32mp15-m4-srm.dtsi + create mode 100644 arch/arm/dts/stm32mp15-no-scmi.dtsi + create mode 100644 arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157a-ed1.dts + create mode 100644 arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157a-ev1.dts + create mode 100644 arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157d-dk1.dts + create mode 100644 arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157d-ed1.dts + create mode 100644 arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157d-ev1.dts + create mode 100644 arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157f-dk2.dts + create mode 100644 arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157f-ed1.dts + create mode 100644 arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi + create mode 100644 arch/arm/dts/stm32mp157f-ev1.dts + create mode 100644 arch/arm/dts/stm32mp15xa.dtsi + create mode 100644 arch/arm/dts/stm32mp15xd.dtsi + create mode 100644 arch/arm/dts/stm32mp15xf.dtsi + create mode 100644 arch/arm/dts/stm32mp15xx-edx.dtsi + create mode 100644 arch/arm/dts/stm32mp15xx-evx.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index f8f529435b..83677c3d4f 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -943,13 +943,21 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb + dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb + + dtb-$(CONFIG_STM32MP15x) += \ +- stm32mp157a-dk1.dtb \ + stm32mp157a-avenger96.dtb \ ++ stm32mp157a-dk1.dtb \ ++ stm32mp157a-ed1.dtb \ ++ stm32mp157a-ev1.dtb \ + stm32mp157c-dk2.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ev1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp15xx-dhcom-drc02.dtb \ ++ stm32mp157d-dk1.dtb \ ++ stm32mp157d-ed1.dtb \ ++ stm32mp157d-ev1.dtb \ ++ stm32mp157f-dk2.dtb \ ++ stm32mp157f-ed1.dtb \ ++ stm32mp157f-ev1.dtb \ + stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcor-avenger96.dtb + +diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi +index 2a139c54e9..25898fa8ad 100644 +--- a/arch/arm/dts/stm32mp15-ddr.dtsi ++++ b/arch/arm/dts/stm32mp15-ddr.dtsi +@@ -14,6 +14,7 @@ + st,mem-speed = ; + st,mem-size = ; + ++#ifndef CONFIG_TFABOOT + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 +@@ -133,7 +134,7 @@ + >; + + #endif +- ++#endif + status = "okay"; + }; + }; +diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +index b4787c4735..978331b279 100644 +--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi ++++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +@@ -15,7 +15,7 @@ + * Save Date: 2020.02.20, save Time: 18:45:20 + */ + #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz +-#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" ++#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" + #define DDR_MEM_SPEED 533000 + #define DDR_MEM_SIZE 0x20000000 + +diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +index dc2875ca08..426be21f42 100644 +--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi ++++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +@@ -15,7 +15,7 @@ + * Save Date: 2020.02.20, save Time: 18:49:33 + */ + #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz +-#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" ++#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" + #define DDR_MEM_SPEED 533000 + #define DDR_MEM_SIZE 0x40000000 + +diff --git a/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi +new file mode 100644 +index 0000000000..b4030e5c94 +--- /dev/null ++++ b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi +@@ -0,0 +1,524 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Fabien Dessenne for STMicroelectronics. ++ */ ++ ++&pinctrl { ++ m4_adc1_in6_pins_a: m4-adc1-in6 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_adc12_ain_pins_a: m4-adc12-ain-0 { ++ pins { ++ pinmux = , /* ADC1 in13 */ ++ , /* ADC1 in6 */ ++ , /* ADC2 in2 */ ++ ; /* ADC2 in6 */ ++ }; ++ }; ++ ++ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 { ++ pins { ++ pinmux = , /* ADC12 in18 */ ++ ; /* ADC12 in19 */ ++ }; ++ }; ++ ++ m4_cec_pins_a: m4-cec-0 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_cec_pins_b: m4-cec-1 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_dac_ch1_pins_a: m4-dac-ch1 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_dac_ch2_pins_a: m4-dac-ch2 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_dcmi_pins_a: m4-dcmi-0 { ++ pins { ++ pinmux = ,/* DCMI_HSYNC */ ++ ,/* DCMI_VSYNC */ ++ ,/* DCMI_PIXCLK */ ++ ,/* DCMI_D0 */ ++ ,/* DCMI_D1 */ ++ ,/* DCMI_D2 */ ++ ,/* DCMI_D3 */ ++ ,/* DCMI_D4 */ ++ ,/* DCMI_D5 */ ++ ,/* DCMI_D6 */ ++ ,/* DCMI_D7 */ ++ ,/* DCMI_D8 */ ++ ,/* DCMI_D9 */ ++ ,/* DCMI_D10 */ ++ ;/* DCMI_D11 */ ++ }; ++ }; ++ ++ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_CKOUT */ ++ }; ++ }; ++ ++ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA1 */ ++ }; ++ }; ++ ++ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA3 */ ++ }; ++ }; ++ ++ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 { ++ pins { ++ pinmux = , /* ETH_RGMII_CLK125 */ ++ , /* ETH_RGMII_GTX_CLK */ ++ , /* ETH_RGMII_TXD0 */ ++ , /* ETH_RGMII_TXD1 */ ++ , /* ETH_RGMII_TXD2 */ ++ , /* ETH_RGMII_TXD3 */ ++ , /* ETH_RGMII_TX_CTL */ ++ , /* ETH_MDC */ ++ , /* ETH_MDIO */ ++ , /* ETH_RGMII_RXD0 */ ++ , /* ETH_RGMII_RXD1 */ ++ , /* ETH_RGMII_RXD2 */ ++ , /* ETH_RGMII_RXD3 */ ++ , /* ETH_RGMII_RX_CLK */ ++ ; /* ETH_RGMII_RX_CTL */ ++ }; ++ }; ++ ++ m4_fmc_pins_a: m4-fmc-0 { ++ pins { ++ pinmux = , /* FMC_NOE */ ++ , /* FMC_NWE */ ++ , /* FMC_A16_FMC_CLE */ ++ , /* FMC_A17_FMC_ALE */ ++ , /* FMC_D0 */ ++ , /* FMC_D1 */ ++ , /* FMC_D2 */ ++ , /* FMC_D3 */ ++ , /* FMC_D4 */ ++ , /* FMC_D5 */ ++ , /* FMC_D6 */ ++ , /* FMC_D7 */ ++ , /* FMC_NE2_FMC_NCE */ ++ ; /* FMC_NWAIT */ ++ }; ++ }; ++ ++ m4_hdp0_pins_a: m4-hdp0-0 { ++ pins { ++ pinmux = ; /* HDP0 */ ++ }; ++ }; ++ ++ m4_hdp6_pins_a: m4-hdp6-0 { ++ pins { ++ pinmux = ; /* HDP6 */ ++ }; ++ }; ++ ++ m4_hdp7_pins_a: m4-hdp7-0 { ++ pins { ++ pinmux = ; /* HDP7 */ ++ }; ++ }; ++ ++ m4_i2c1_pins_a: m4-i2c1-0 { ++ pins { ++ pinmux = , /* I2C1_SCL */ ++ ; /* I2C1_SDA */ ++ }; ++ }; ++ ++ m4_i2c2_pins_a: m4-i2c2-0 { ++ pins { ++ pinmux = , /* I2C2_SCL */ ++ ; /* I2C2_SDA */ ++ }; ++ }; ++ ++ m4_i2c5_pins_a: m4-i2c5-0 { ++ pins { ++ pinmux = , /* I2C5_SCL */ ++ ; /* I2C5_SDA */ ++ }; ++ }; ++ ++ m4_i2s2_pins_a: m4-i2s2-0 { ++ pins { ++ pinmux = , /* I2S2_SDO */ ++ , /* I2S2_WS */ ++ ; /* I2S2_CK */ ++ }; ++ }; ++ ++ m4_ltdc_pins_a: m4-ltdc-a-0 { ++ pins { ++ pinmux = , /* LCD_CLK */ ++ , /* LCD_HSYNC */ ++ , /* LCD_VSYNC */ ++ , /* LCD_DE */ ++ , /* LCD_R0 */ ++ , /* LCD_R1 */ ++ , /* LCD_R2 */ ++ , /* LCD_R3 */ ++ , /* LCD_R4 */ ++ , /* LCD_R5 */ ++ , /* LCD_R6 */ ++ , /* LCD_R7 */ ++ , /* LCD_G0 */ ++ , /* LCD_G1 */ ++ , /* LCD_G2 */ ++ , /* LCD_G3 */ ++ , /* LCD_G4 */ ++ , /* LCD_G5 */ ++ , /* LCD_G6 */ ++ , /* LCD_G7 */ ++ , /* LCD_B0 */ ++ , /* LCD_B1 */ ++ , /* LCD_B2 */ ++ , /* LCD_B3 */ ++ , /* LCD_B4 */ ++ , /* LCD_B5 */ ++ , /* LCD_B6 */ ++ ; /* LCD_B7 */ ++ }; ++ }; ++ ++ m4_ltdc_pins_b: m4-ltdc-b-0 { ++ pins { ++ pinmux = , /* LCD_CLK */ ++ , /* LCD_HSYNC */ ++ , /* LCD_VSYNC */ ++ , /* LCD_DE */ ++ , /* LCD_R0 */ ++ , /* LCD_R1 */ ++ , /* LCD_R2 */ ++ , /* LCD_R3 */ ++ , /* LCD_R4 */ ++ , /* LCD_R5 */ ++ , /* LCD_R6 */ ++ , /* LCD_R7 */ ++ , /* LCD_G0 */ ++ , /* LCD_G1 */ ++ , /* LCD_G2 */ ++ , /* LCD_G3 */ ++ , /* LCD_G4 */ ++ , /* LCD_G5 */ ++ , /* LCD_G6 */ ++ , /* LCD_G7 */ ++ , /* LCD_B0 */ ++ , /* LCD_B1 */ ++ , /* LCD_B2 */ ++ , /* LCD_B3 */ ++ , /* LCD_B4 */ ++ , /* LCD_B5 */ ++ , /* LCD_B6 */ ++ ; /* LCD_B7 */ ++ }; ++ }; ++ ++ m4_m_can1_pins_a: m4-m-can1-0 { ++ pins { ++ pinmux = , /* CAN1_TX */ ++ ; /* CAN1_RX */ ++ }; ++ }; ++ ++ m4_pwm1_pins_a: m4-pwm1-0 { ++ pins { ++ pinmux = , /* TIM1_CH1 */ ++ , /* TIM1_CH2 */ ++ ; /* TIM1_CH4 */ ++ }; ++ }; ++ ++ m4_pwm2_pins_a: m4-pwm2-0 { ++ pins { ++ pinmux = ; /* TIM2_CH4 */ ++ }; ++ }; ++ ++ m4_pwm3_pins_a: m4-pwm3-0 { ++ pins { ++ pinmux = ; /* TIM3_CH2 */ ++ }; ++ }; ++ ++ m4_pwm4_pins_a: m4-pwm4-0 { ++ pins { ++ pinmux = , /* TIM4_CH3 */ ++ ; /* TIM4_CH4 */ ++ }; ++ }; ++ ++ m4_pwm4_pins_b: m4-pwm4-1 { ++ pins { ++ pinmux = ; /* TIM4_CH2 */ ++ }; ++ }; ++ ++ m4_pwm5_pins_a: m4-pwm5-0 { ++ pins { ++ pinmux = ; /* TIM5_CH2 */ ++ }; ++ }; ++ ++ m4_pwm8_pins_a: m4-pwm8-0 { ++ pins { ++ pinmux = ; /* TIM8_CH4 */ ++ }; ++ }; ++ ++ m4_pwm12_pins_a: m4-pwm12-0 { ++ pins { ++ pinmux = ; /* TIM12_CH1 */ ++ }; ++ }; ++ ++ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 { ++ pins { ++ pinmux = , /* QSPI_BK1_IO0 */ ++ , /* QSPI_BK1_IO1 */ ++ , /* QSPI_BK1_IO2 */ ++ , /* QSPI_BK1_IO3 */ ++ ; /* QSPI_BK1_NCS */ ++ }; ++ }; ++ ++ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 { ++ pins { ++ pinmux = , /* QSPI_BK2_IO0 */ ++ , /* QSPI_BK2_IO1 */ ++ , /* QSPI_BK2_IO2 */ ++ , /* QSPI_BK2_IO3 */ ++ ; /* QSPI_BK2_NCS */ ++ }; ++ }; ++ ++ m4_qspi_clk_pins_a: m4-qspi-clk-0 { ++ pins { ++ pinmux = ; /* QSPI_CLK */ ++ }; ++ }; ++ ++ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 { ++ pins { ++ pinmux = ; /* RTC_OUT2_RMP */ ++ }; ++ }; ++ ++ m4_sai2a_pins_a: m4-sai2a-0 { ++ pins { ++ pinmux = , /* SAI2_SCK_A */ ++ , /* SAI2_SD_A */ ++ , /* SAI2_FS_A */ ++ ; /* SAI2_MCLK_A */ ++ }; ++ }; ++ ++ m4_sai2b_pins_a: m4-sai2b-0 { ++ pins { ++ pinmux = , /* SAI2_SCK_B */ ++ , /* SAI2_FS_B */ ++ , /* SAI2_MCLK_B */ ++ ; /* SAI2_SD_B */ ++ }; ++ }; ++ ++ m4_sai2b_pins_b: m4-sai2b-2 { ++ pins { ++ pinmux = ; /* SAI2_SD_B */ ++ }; ++ }; ++ ++ m4_sai4a_pins_a: m4-sai4a-0 { ++ pins { ++ pinmux = ; /* SAI4_SD_A */ ++ }; ++ }; ++ ++ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 { ++ pins { ++ pinmux = , /* SDMMC1_D0 */ ++ , /* SDMMC1_D1 */ ++ , /* SDMMC1_D2 */ ++ , /* SDMMC1_D3 */ ++ , /* SDMMC1_CMD */ ++ ; /* SDMMC1_CK */ ++ }; ++ }; ++ ++ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 { ++ pins { ++ pinmux = , /* SDMMC1_D0DIR */ ++ , /* SDMMC1_D123DIR */ ++ , /* SDMMC1_CDIR */ ++ ; /* SDMMC1_CKIN */ ++ }; ++ }; ++ ++ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 { ++ pins { ++ pinmux = , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_CMD */ ++ ; /* SDMMC2_CK */ ++ }; ++ }; ++ ++ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 { ++ pins { ++ pinmux = , /* SDMMC2_D0 */ ++ , /* SDMMC2_D1 */ ++ , /* SDMMC2_D2 */ ++ , /* SDMMC2_D3 */ ++ , /* SDMMC2_CMD */ ++ ; /* SDMMC2_CK */ ++ }; ++ }; ++ ++ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 { ++ pins { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_D7 */ ++ }; ++ }; ++ ++ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 { ++ pins { ++ pinmux = , /* SDMMC3_D0 */ ++ , /* SDMMC3_D1 */ ++ , /* SDMMC3_D2 */ ++ , /* SDMMC3_D3 */ ++ , /* SDMMC3_CMD */ ++ ; /* SDMMC3_CK */ ++ }; ++ }; ++ ++ m4_spdifrx_pins_a: m4-spdifrx-0 { ++ pins { ++ pinmux = ; /* SPDIF_IN1 */ ++ }; ++ }; ++ ++ m4_spi4_pins_a: m4-spi4-0 { ++ pins { ++ pinmux = , /* SPI4_SCK */ ++ , /* SPI4_MOSI */ ++ ; /* SPI4_MISO */ ++ }; ++ }; ++ ++ m4_spi5_pins_a: m4-spi5-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MOSI */ ++ ; /* SPI5_MISO */ ++ }; ++ }; ++ ++ m4_stusb1600_pins_a: m4-stusb1600-0 { ++ pins { ++ pinmux = ; ++ }; ++ }; ++ ++ m4_uart4_pins_a: m4-uart4-0 { ++ pins { ++ pinmux = , /* UART4_TX */ ++ ; /* UART4_RX */ ++ }; ++ }; ++ ++ m4_uart7_pins_a: m4-uart7-0 { ++ pins { ++ pinmux = , /* USART7_TX */ ++ ; /* USART7_RX */ ++ }; ++ }; ++ ++ m4_usart2_pins_a: m4-usart2-0 { ++ pins { ++ pinmux = , /* USART2_TX */ ++ , /* USART2_RTS */ ++ , /* USART2_RX */ ++ ; /* USART2_CTS_NSS */ ++ }; ++ }; ++ ++ m4_usart3_pins_a: m4-usart3-0 { ++ pins { ++ pinmux = , /* USART3_TX */ ++ , /* USART3_RTS */ ++ , /* USART3_RX */ ++ ; /* USART3_CTS_NSS */ ++ }; ++ }; ++ ++ m4_usart3_pins_b: m4-usart3-1 { ++ pins { ++ pinmux = , /* USART3_TX */ ++ , /* USART3_RTS */ ++ , /* USART3_RX */ ++ ; /* USART3_CTS_NSS */ ++ }; ++ }; ++ ++ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 { ++ pins { ++ pinmux = ; /* OTG_ID */ ++ }; ++ }; ++ ++ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 { ++ pins { ++ pinmux = , /* OTG_FS_DM */ ++ ; /* OTG_FS_DP */ ++ }; ++ }; ++}; ++ ++&pinctrl_z { ++ m4_i2c4_pins_a: m4-i2c4-0 { ++ pins { ++ pinmux = , /* I2C4_SCL */ ++ ; /* I2C4_SDA */ ++ }; ++ }; ++ ++ m4_spi1_pins_a: m4-spi1-0 { ++ pins { ++ pinmux = , /* SPI1_SCK */ ++ , /* SPI1_MOSI */ ++ ; /* SPI1_MISO */ ++ }; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp15-m4-srm.dtsi b/arch/arm/dts/stm32mp15-m4-srm.dtsi +new file mode 100644 +index 0000000000..60454aee41 +--- /dev/null ++++ b/arch/arm/dts/stm32mp15-m4-srm.dtsi +@@ -0,0 +1,442 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Fabien Dessenne for STMicroelectronics. ++ */ ++ ++&m4_rproc { ++ m4_system_resources { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ m4_timers2: timer@40000000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40000000 0x400>; ++ clocks = <&rcc TIM2_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers3: timer@40001000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40001000 0x400>; ++ clocks = <&rcc TIM3_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers4: timer@40002000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40002000 0x400>; ++ clocks = <&rcc TIM4_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers5: timer@40003000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40003000 0x400>; ++ clocks = <&rcc TIM5_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers6: timer@40004000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40004000 0x400>; ++ clocks = <&rcc TIM6_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers7: timer@40005000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40005000 0x400>; ++ clocks = <&rcc TIM7_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers12: timer@40006000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40006000 0x400>; ++ clocks = <&rcc TIM12_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers13: timer@40007000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40007000 0x400>; ++ clocks = <&rcc TIM13_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers14: timer@40008000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40008000 0x400>; ++ clocks = <&rcc TIM14_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_lptimer1: timer@40009000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40009000 0x400>; ++ clocks = <&rcc LPTIM1_K>; ++ clock-names = "mux"; ++ status = "disabled"; ++ }; ++ m4_spi2: spi@4000b000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000b000 0x400>; ++ clocks = <&rcc SPI2_K>; ++ status = "disabled"; ++ }; ++ m4_i2s2: audio-controller@4000b000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000b000 0x400>; ++ status = "disabled"; ++ }; ++ m4_spi3: spi@4000c000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000c000 0x400>; ++ clocks = <&rcc SPI3_K>; ++ status = "disabled"; ++ }; ++ m4_i2s3: audio-controller@4000c000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000c000 0x400>; ++ status = "disabled"; ++ }; ++ m4_spdifrx: audio-controller@4000d000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000d000 0x400>; ++ clocks = <&rcc SPDIF_K>; ++ clock-names = "kclk"; ++ status = "disabled"; ++ }; ++ m4_usart2: serial@4000e000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000e000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <27 1>; ++ clocks = <&rcc USART2_K>; ++ status = "disabled"; ++ }; ++ m4_usart3: serial@4000f000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4000f000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <28 1>; ++ clocks = <&rcc USART3_K>; ++ status = "disabled"; ++ }; ++ m4_uart4: serial@40010000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40010000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <30 1>; ++ clocks = <&rcc UART4_K>; ++ status = "disabled"; ++ }; ++ m4_uart5: serial@40011000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40011000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <31 1>; ++ clocks = <&rcc UART5_K>; ++ status = "disabled"; ++ }; ++ m4_i2c1: i2c@40012000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40012000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <21 1>; ++ clocks = <&rcc I2C1_K>; ++ status = "disabled"; ++ }; ++ m4_i2c2: i2c@40013000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40013000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <22 1>; ++ clocks = <&rcc I2C2_K>; ++ status = "disabled"; ++ }; ++ m4_i2c3: i2c@40014000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40014000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <23 1>; ++ clocks = <&rcc I2C3_K>; ++ status = "disabled"; ++ }; ++ m4_i2c5: i2c@40015000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40015000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <25 1>; ++ clocks = <&rcc I2C5_K>; ++ status = "disabled"; ++ }; ++ m4_cec: cec@40016000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40016000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <69 1>; ++ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; ++ clock-names = "cec", "hdmi-cec"; ++ status = "disabled"; ++ }; ++ m4_dac: dac@40017000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40017000 0x400>; ++ clocks = <&rcc DAC12>; ++ clock-names = "pclk"; ++ status = "disabled"; ++ }; ++ m4_uart7: serial@40018000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40018000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <32 1>; ++ clocks = <&rcc UART7_K>; ++ status = "disabled"; ++ }; ++ m4_uart8: serial@40019000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x40019000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <33 1>; ++ clocks = <&rcc UART8_K>; ++ status = "disabled"; ++ }; ++ m4_timers1: timer@44000000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44000000 0x400>; ++ clocks = <&rcc TIM1_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers8: timer@44001000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44001000 0x400>; ++ clocks = <&rcc TIM8_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_usart6: serial@44003000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44003000 0x400>; ++ interrupt-parent = <&exti>; ++ interrupts = <29 1>; ++ clocks = <&rcc USART6_K>; ++ status = "disabled"; ++ }; ++ m4_spi1: spi@44004000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44004000 0x400>; ++ clocks = <&rcc SPI1_K>; ++ status = "disabled"; ++ }; ++ m4_i2s1: audio-controller@44004000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44004000 0x400>; ++ status = "disabled"; ++ }; ++ m4_spi4: spi@44005000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44005000 0x400>; ++ clocks = <&rcc SPI4_K>; ++ status = "disabled"; ++ }; ++ m4_timers15: timer@44006000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44006000 0x400>; ++ clocks = <&rcc TIM15_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers16: timer@44007000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44007000 0x400>; ++ clocks = <&rcc TIM16_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_timers17: timer@44008000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44008000 0x400>; ++ clocks = <&rcc TIM17_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ }; ++ m4_spi5: spi@44009000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x44009000 0x400>; ++ clocks = <&rcc SPI5_K>; ++ status = "disabled"; ++ }; ++ m4_sai1: sai@4400a000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400a000 0x4>; ++ clocks = <&rcc SAI1_K>; ++ clock-names = "sai_ck"; ++ status = "disabled"; ++ }; ++ m4_sai2: sai@4400b000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400b000 0x4>; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ status = "disabled"; ++ }; ++ m4_sai3: sai@4400c000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400c000 0x4>; ++ clocks = <&rcc SAI3_K>; ++ clock-names = "sai_ck"; ++ status = "disabled"; ++ }; ++ m4_dfsdm: dfsdm@4400d000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400d000 0x800>; ++ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; ++ clock-names = "dfsdm", "audio"; ++ status = "disabled"; ++ }; ++ m4_m_can1: can@4400e000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400e000 0x400>, <0x44011000 0x2800>; ++ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ status = "disabled"; ++ }; ++ m4_m_can2: can@4400f000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4400f000 0x400>, <0x44011000 0x2800>; ++ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ status = "disabled"; ++ }; ++ m4_dma1: dma@48000000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x48000000 0x400>; ++ clocks = <&rcc DMA1>; ++ status = "disabled"; ++ }; ++ m4_dma2: dma@48001000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x48001000 0x400>; ++ clocks = <&rcc DMA2>; ++ status = "disabled"; ++ }; ++ m4_dmamux1: dma-router@48002000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x48002000 0x1c>; ++ clocks = <&rcc DMAMUX>; ++ status = "disabled"; ++ }; ++ m4_adc: adc@48003000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x48003000 0x400>; ++ clocks = <&rcc ADC12>, <&rcc ADC12_K>; ++ clock-names = "bus", "adc"; ++ status = "disabled"; ++ }; ++ m4_sdmmc3: sdmmc@48004000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x48004000 0x400>, <0x48005000 0x400>; ++ clocks = <&rcc SDMMC3_K>; ++ status = "disabled"; ++ }; ++ m4_usbotg_hs: usb-otg@49000000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x49000000 0x10000>; ++ clocks = <&rcc USBO_K>; ++ clock-names = "otg"; ++ status = "disabled"; ++ }; ++ m4_hash2: hash@4c002000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4c002000 0x400>; ++ clocks = <&rcc HASH2>; ++ status = "disabled"; ++ }; ++ m4_rng2: rng@4c003000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4c003000 0x400>; ++ clocks = <&rcc RNG2_K>; ++ status = "disabled"; ++ }; ++ m4_crc2: crc@4c004000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4c004000 0x400>; ++ clocks = <&rcc CRC2>; ++ status = "disabled"; ++ }; ++ m4_cryp2: cryp@4c005000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4c005000 0x400>; ++ clocks = <&rcc CRYP2>; ++ status = "disabled"; ++ }; ++ m4_dcmi: dcmi@4c006000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x4c006000 0x400>; ++ clocks = <&rcc DCMI>; ++ clock-names = "mclk"; ++ status = "disabled"; ++ }; ++ m4_lptimer2: timer@50021000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x50021000 0x400>; ++ clocks = <&rcc LPTIM2_K>; ++ clock-names = "mux"; ++ status = "disabled"; ++ }; ++ m4_lptimer3: timer@50022000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x50022000 0x400>; ++ clocks = <&rcc LPTIM3_K>; ++ clock-names = "mux"; ++ status = "disabled"; ++ }; ++ m4_lptimer4: timer@50023000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x50023000 0x400>; ++ clocks = <&rcc LPTIM4_K>; ++ clock-names = "mux"; ++ status = "disabled"; ++ }; ++ m4_lptimer5: timer@50024000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x50024000 0x400>; ++ clocks = <&rcc LPTIM5_K>; ++ clock-names = "mux"; ++ status = "disabled"; ++ }; ++ m4_sai4: sai@50027000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x50027000 0x4>; ++ clocks = <&rcc SAI4_K>; ++ clock-names = "sai_ck"; ++ status = "disabled"; ++ }; ++ m4_qspi: qspi@58003000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; ++ clocks = <&rcc QSPI_K>; ++ status = "disabled"; ++ }; ++ m4_ethernet0: ethernet@5800a000 { ++ compatible = "rproc-srm-dev"; ++ reg = <0x5800a000 0x2000>; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "ethstp", ++ "syscfg-clk"; ++ clocks = <&rcc ETHMAC>, ++ <&rcc ETHTX>, ++ <&rcc ETHRX>, ++ <&rcc ETHSTP>, ++ <&rcc SYSCFG>; ++ status = "disabled"; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi +new file mode 100644 +index 0000000000..94a10b86a1 +--- /dev/null ++++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi +@@ -0,0 +1,157 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved ++ * Author: Gabriel Fernandez for STMicroelectronics. ++ */ ++ ++/ { ++ ++ clocks { ++ clk_hse: clk-hse { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ }; ++ ++ clk_hsi: clk-hsi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <64000000>; ++ }; ++ ++ clk_lse: clk-lse { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ }; ++ ++ clk_lsi: clk-lsi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ }; ++ ++ clk_csi: clk-csi { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <4000000>; ++ }; ++ }; ++ ++ cpus { ++ cpu0: cpu@0 { ++ clocks = <&rcc CK_MPU>; ++ }; ++ ++ cpu1: cpu@1 { ++ clocks = <&rcc CK_MPU>; ++ }; ++ }; ++ ++ reboot { ++ compatible = "syscon-reboot"; ++ regmap = <&rcc>; ++ offset = <0x404>; ++ mask = <0x1>; ++ }; ++ ++ soc { ++ m_can1: can@4400e000 { ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ }; ++ ++ m_can2: can@4400f000 { ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ }; ++ ++ cryp1: cryp@54001000 { ++ clocks = <&rcc CRYP1>; ++ resets = <&rcc CRYP1_R>; ++ }; ++ ++ dsi: dsi@5a000000 { ++ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; ++ }; ++ }; ++ ++ ahb { ++ m4_rproc: m4@10000000 { ++ resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; ++ ++ m4_system_resources { ++ m4_cec: cec@40016000 { ++ clocks = <&rcc CEC_K>, <&rcc CK_LSE>; ++ }; ++ ++ m4_m_can1: can@4400e000 { ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ }; ++ ++ m4_m_can2: can@4400f000 { ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ }; ++ }; ++ }; ++ }; ++ ++ firmware { ++ /delete-node/ scmi0; ++ /delete-node/ scmi1; ++ }; ++ /delete-node/ sram@2ffff000; ++}; ++ ++&cec { ++ clocks = <&rcc CEC_K>, <&clk_lse>; ++}; ++ ++&gpioz { ++ clocks = <&rcc GPIOZ>; ++}; ++ ++&hash1 { ++ clocks = <&rcc HASH1>; ++ resets = <&rcc HASH1_R>; ++}; ++ ++&i2c4 { ++ clocks = <&rcc I2C4_K>; ++ resets = <&rcc I2C4_R>; ++}; ++ ++&i2c6 { ++ clocks = <&rcc I2C6_K>; ++ resets = <&rcc I2C6_R>; ++}; ++ ++&iwdg2 { ++ clocks = <&rcc IWDG2>, <&rcc CK_LSI>; ++}; ++ ++&mdma1 { ++ clocks = <&rcc MDMA>; ++ resets = <&rcc MDMA_R>; ++}; ++ ++&rcc { ++ compatible = "st,stm32mp1-rcc", "syscon"; ++ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; ++}; ++ ++&rng1 { ++ clocks = <&rcc RNG1_K>; ++ resets = <&rcc RNG1_R>; ++}; ++ ++&rtc { ++ clocks = <&rcc RTCAPB>, <&rcc RTC>; ++}; ++ ++&spi6 { ++ clocks = <&rcc SPI6_K>; ++ resets = <&rcc SPI6_R>; ++}; ++ ++&usart1 { ++ clocks = <&rcc USART1_K>; ++}; +diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi +index e9525b5d06..a0b76e238c 100644 +--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi +@@ -118,6 +118,45 @@ + }; + }; + ++ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_CKOUT */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_CKOUT */ ++ }; ++ }; ++ ++ dfsdm_data1_pins_a: dfsdm-data1-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA1 */ ++ }; ++ }; ++ ++ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA1 */ ++ }; ++ }; ++ ++ dfsdm_data3_pins_a: dfsdm-data3-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA3 */ ++ }; ++ }; ++ ++ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 { ++ pins { ++ pinmux = ; /* DFSDM_DATA3 */ ++ }; ++ }; ++ + ethernet0_rgmii_pins_a: rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ +@@ -349,6 +388,51 @@ + }; + }; + ++ hdp0_pins_a: hdp0-0 { ++ pins { ++ pinmux = ; /* HDP0 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ hdp0_pins_sleep_a: hdp0-sleep-0 { ++ pins { ++ pinmux = ; /* HDP0 */ ++ }; ++ }; ++ ++ hdp6_pins_a: hdp6-0 { ++ pins { ++ pinmux = ; /* HDP6 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ hdp6_pins_sleep_a: hdp6-sleep-0 { ++ pins { ++ pinmux = ; /* HDP6 */ ++ }; ++ }; ++ ++ hdp7_pins_a: hdp7-0 { ++ pins { ++ pinmux = ; /* HDP7 */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ }; ++ ++ hdp7_pins_sleep_a: hdp7-sleep-0 { ++ pins { ++ pinmux = ; /* HDP7 */ ++ }; ++ }; ++ + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ +@@ -1051,6 +1135,12 @@ + }; + }; + ++ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { ++ pins { ++ pinmux = ; /* RTC_OUT2_RMP */ ++ }; ++ }; ++ + sai2a_pins_a: sai2a-0 { + pins { + pinmux = , /* SAI2_SCK_A */ +@@ -1147,7 +1237,7 @@ + }; + }; + +- sai2b_pins_c: sai2a-4 { ++ sai2b_pins_c: sai2b-4 { + pins1 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; +@@ -1437,6 +1527,24 @@ + }; + }; + ++ sdmmc2_d47_pins_d: sdmmc2-d47-3 { ++ pins { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_D7 */ ++ }; ++ }; ++ ++ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { ++ pins { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_D7 */ ++ }; ++ }; ++ + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ +@@ -1573,10 +1681,205 @@ + }; + }; + ++ spi4_pins_a: spi4-0 { ++ pins { ++ pinmux = , /* SPI4_SCK */ ++ ; /* SPI4_MOSI */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ pins2 { ++ pinmux = ; /* SPI4_MISO */ ++ bias-disable; ++ }; ++ }; ++ ++ spi4_pins_b: spi4-1 { ++ pins1 { ++ pinmux = , /* SPI4_SCK */ ++ ; /* SPI4_MOSI */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ ++ pins2 { ++ pinmux = ; /* SPI4_MISO */ ++ bias-disable; ++ }; ++ }; ++ ++ spi4_sleep_pins_b: spi4-sleep-1 { ++ pins { ++ pinmux = , /* SPI4_SCK */ ++ , /* SPI4_MISO */ ++ ; /* SPI4_MOSI */ ++ }; ++ }; ++ ++ spi5_pins_a: spi5-0 { ++ pins1 { ++ pinmux = , /* SPI5_SCK */ ++ ; /* SPI5_MOSI */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ ++ pins2 { ++ pinmux = ; /* SPI5_MISO */ ++ bias-disable; ++ }; ++ }; ++ ++ spi5_sleep_pins_a: spi5-sleep-0 { ++ pins { ++ pinmux = , /* SPI5_SCK */ ++ , /* SPI5_MISO */ ++ ; /* SPI5_MOSI */ ++ }; ++ }; ++ + stusb1600_pins_a: stusb1600-0 { +- pins { +- pinmux = ; +- bias-pull-up; ++ pins { ++ pinmux = ; ++ bias-pull-up; ++ }; ++ }; ++ ++ uart4_pins_a: uart4-0 { ++ pins1 { ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart4_idle_pins_a: uart4-idle-0 { ++ pins1 { ++ pinmux = ; /* UART4_TX */ ++ }; ++ pins2 { ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart4_sleep_pins_a: uart4-sleep-0 { ++ pins { ++ pinmux = , /* UART4_TX */ ++ ; /* UART4_RX */ ++ }; ++ }; ++ ++ uart4_pins_b: uart4-1 { ++ pins1 { ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart4_pins_c: uart4-2 { ++ pins1 { ++ pinmux = ; /* UART4_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART4_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart7_pins_a: uart7-0 { ++ pins1 { ++ pinmux = ; /* UART7_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = , /* UART7_RX */ ++ , /* UART7_CTS */ ++ ; /* UART7_RTS */ ++ bias-disable; ++ }; ++ }; ++ ++ uart7_pins_b: uart7-1 { ++ pins1 { ++ pinmux = ; /* UART7_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART7_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart7_pins_c: uart7-2 { ++ pins1 { ++ pinmux = ; /* UART7_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART7_RX */ ++ bias-pull-up; ++ }; ++ }; ++ ++ uart7_idle_pins_c: uart7-idle-2 { ++ pins1 { ++ pinmux = ; /* UART7_TX */ ++ }; ++ pins2 { ++ pinmux = ; /* UART7_RX */ ++ bias-pull-up; ++ }; ++ }; ++ ++ uart7_sleep_pins_c: uart7-sleep-2 { ++ pins { ++ pinmux = , /* UART7_TX */ ++ ; /* UART7_RX */ ++ }; ++ }; ++ ++ uart8_pins_a: uart8-0 { ++ pins1 { ++ pinmux = ; /* UART8_TX */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <0>; ++ }; ++ pins2 { ++ pinmux = ; /* UART8_RX */ ++ bias-disable; ++ }; ++ }; ++ ++ uart8_rtscts_pins_a: uart8rtscts-0 { ++ pins { ++ pinmux = , /* UART8_RTS */ ++ ; /* UART8_CTS */ ++ bias-disable; + }; + }; + +@@ -1628,96 +1931,139 @@ + }; + }; + +- usart3_pins_a: usart3-0 { ++ usart2_pins_c: usart2-2 { + pins1 { +- pinmux = ; /* USART3_TX */ ++ pinmux = , /* USART2_TX */ ++ ; /* USART2_RTS */ + bias-disable; + drive-push-pull; +- slew-rate = <0>; ++ slew-rate = <3>; + }; + pins2 { +- pinmux = ; /* USART3_RX */ ++ pinmux = , /* USART2_RX */ ++ ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + +- uart4_pins_a: uart4-0 { ++ usart2_idle_pins_c: usart2-idle-2 { + pins1 { +- pinmux = ; /* UART4_TX */ ++ pinmux = , /* USART2_TX */ ++ ; /* USART2_CTS_NSS */ ++ }; ++ pins2 { ++ pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; +- slew-rate = <0>; ++ slew-rate = <3>; + }; +- pins2 { +- pinmux = ; /* UART4_RX */ ++ pins3 { ++ pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + +- uart4_pins_b: uart4-1 { ++ usart2_sleep_pins_c: usart2-sleep-2 { ++ pins { ++ pinmux = , /* USART2_TX */ ++ , /* USART2_RTS */ ++ , /* USART2_RX */ ++ ; /* USART2_CTS_NSS */ ++ }; ++ }; ++ ++ usart3_pins_a: usart3-0 { + pins1 { +- pinmux = ; /* UART4_TX */ ++ pinmux = ; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { +- pinmux = ; /* UART4_RX */ ++ pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + +- uart4_pins_c: uart4-2 { ++ usart3_pins_b: usart3-1 { + pins1 { +- pinmux = ; /* UART4_TX */ ++ pinmux = , /* USART3_TX */ ++ ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { +- pinmux = ; /* UART4_RX */ ++ pinmux = , /* USART3_RX */ ++ ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + +- uart7_pins_a: uart7-0 { ++ usart3_idle_pins_b: usart3-idle-1 { + pins1 { +- pinmux = ; /* UART4_TX */ ++ pinmux = , /* USART3_TX */ ++ ; /* USART3_CTS_NSS */ ++ }; ++ pins2 { ++ pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; +- pins2 { +- pinmux = , /* UART4_RX */ +- , /* UART4_CTS */ +- ; /* UART4_RTS */ ++ pins3 { ++ pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + +- uart7_pins_b: uart7-1 { ++ usart3_sleep_pins_b: usart3-sleep-1 { ++ pins { ++ pinmux = , /* USART3_TX */ ++ , /* USART3_RTS */ ++ , /* USART3_CTS_NSS */ ++ ; /* USART3_RX */ ++ }; ++ }; ++ ++ usart3_pins_c: usart3-2 { + pins1 { +- pinmux = ; /* UART7_TX */ ++ pinmux = , /* USART3_TX */ ++ ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { +- pinmux = ; /* UART7_RX */ +- bias-disable; ++ pinmux = , /* USART3_RX */ ++ ; /* USART3_CTS_NSS */ ++ bias-pull-up; + }; + }; + +- uart8_pins_a: uart8-0 { ++ usart3_idle_pins_c: usart3-idle-2 { + pins1 { +- pinmux = ; /* UART8_TX */ ++ pinmux = , /* USART3_TX */ ++ ; /* USART3_CTS_NSS */ ++ }; ++ pins2 { ++ pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; +- pins2 { +- pinmux = ; /* UART8_RX */ +- bias-disable; ++ pins3 { ++ pinmux = ; /* USART3_RX */ ++ bias-pull-up; ++ }; ++ }; ++ ++ usart3_sleep_pins_c: usart3-sleep-2 { ++ pins { ++ pinmux = , /* USART3_TX */ ++ , /* USART3_RTS */ ++ , /* USART3_CTS_NSS */ ++ ; /* USART3_RX */ + }; + }; + +@@ -1783,17 +2129,11 @@ + }; + }; + +- spi4_pins_a: spi4-0 { ++ spi1_sleep_pins_a: spi1-sleep-0 { + pins { +- pinmux = , /* SPI4_SCK */ +- ; /* SPI4_MOSI */ +- bias-disable; +- drive-push-pull; +- slew-rate = <1>; +- }; +- pins2 { +- pinmux = ; /* SPI4_MISO */ +- bias-disable; ++ pinmux = , /* SPI1_SCK */ ++ , /* SPI1_MISO */ ++ ; /* SPI1_MOSI */ + }; + }; + }; +diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi +index 7ec90fe4a3..038ae25530 100644 +--- a/arch/arm/dts/stm32mp15-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15-u-boot.dtsi +@@ -21,23 +21,11 @@ + pinctrl1 = &pinctrl_z; + }; + +- clocks { +- u-boot,dm-pre-reloc; +- }; +- + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; + +- reboot { +- u-boot,dm-pre-reloc; +- compatible = "syscon-reboot"; +- regmap = <&rcc>; +- offset = <0x404>; +- mask = <0x1>; +- }; +- + soc { + u-boot,dm-pre-reloc; + +@@ -72,36 +60,6 @@ + u-boot,dm-pre-reloc; + }; + +-&clk_csi { +- u-boot,dm-pre-reloc; +-}; +- +-&clk_hsi { +- u-boot,dm-pre-reloc; +-}; +- +-&clk_hse { +- u-boot,dm-pre-reloc; +-}; +- +-&clk_lsi { +- u-boot,dm-pre-reloc; +-}; +- +-&clk_lse { +- u-boot,dm-pre-reloc; +-}; +- +-&cpu0_opp_table { +- u-boot,dm-spl; +- opp-650000000 { +- u-boot,dm-spl; +- }; +- opp-800000000 { +- u-boot,dm-spl; +- }; +-}; +- + &gpioa { + u-boot,dm-pre-reloc; + }; +@@ -167,16 +125,44 @@ + u-boot,dm-pre-reloc; + }; + +-&pwr_regulators { ++&rcc { + u-boot,dm-pre-reloc; + }; + +-&rcc { ++#ifdef CONFIG_TFABOOT ++&scmi0 { + u-boot,dm-pre-reloc; +- #address-cells = <1>; +- #size-cells = <0>; + }; + ++&scmi0_clk { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi0_reset { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi0_shm { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi1 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi1_clk { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi1_shm { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scmi_sram { ++ u-boot,dm-pre-reloc; ++}; ++#endif ++ + &sdmmc1 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + }; +@@ -190,7 +176,7 @@ + }; + + &usart1 { +- resets = <&rcc USART1_R>; ++ resets = <&scmi0_reset RST_SCMI0_USART1>; + }; + + &usart2 { +@@ -221,6 +207,63 @@ + resets = <&rcc UART8_R>; + }; + +-&usbotg_hs { +- compatible = "st,stm32mp1-hsotg", "snps,dwc2"; ++/* NO MORE USE SCMI SUPPORT for BASIC boot chain */ ++#ifndef CONFIG_TFABOOT ++ ++#include "stm32mp15-no-scmi.dtsi" ++ ++/ { ++ clocks { ++ u-boot,dm-pre-reloc; ++ ++ clk_hse: clk-hse { ++ u-boot,dm-pre-reloc; ++ }; ++ ++ clk_hsi: clk-hsi { ++ u-boot,dm-pre-reloc; ++ }; ++ ++ clk_lse: clk-lse { ++ u-boot,dm-pre-reloc; ++ }; ++ ++ clk_lsi: clk-lsi { ++ u-boot,dm-pre-reloc; ++ }; ++ ++ clk_csi: clk-csi { ++ u-boot,dm-pre-reloc; ++ }; ++ }; ++ ++ reboot { ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&cpu0_opp_table { ++ u-boot,dm-spl; ++ opp-650000000 { ++ u-boot,dm-spl; ++ }; ++ opp-800000000 { ++ u-boot,dm-spl; ++ }; + }; ++ ++/* only for vdd-supply in sysconf_init() */ ++&pwr_regulators { ++ u-boot,dm-pre-reloc; ++}; ++ ++&rcc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++}; ++ ++&usart1 { ++ resets = <&rcc USART1_R>; ++}; ++ ++#endif /* CONFIG_TFABOOT */ +diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi +index 39d9e545ed..ca71139f3a 100644 +--- a/arch/arm/dts/stm32mp151.dtsi ++++ b/arch/arm/dts/stm32mp151.dtsi +@@ -5,7 +5,10 @@ + */ + #include + #include ++#include + #include ++#include ++ + + / { + #address-cells = <1>; +@@ -17,27 +20,76 @@ + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; +- clock-frequency = <650000000>; + device_type = "cpu"; + reg = <0>; ++ clocks = <&scmi0_clk CK_SCMI0_MPU>; ++ clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; ++ #cooling-cells = <2>; + }; + }; + ++ arm-pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = ; ++ interrupt-affinity = <&cpu0>; ++ interrupt-parent = <&intc>; ++ }; ++ + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; +- opp-650000000 { +- opp-hz = /bits/ 64 <650000000>; +- opp-microvolt = <1200000>; +- opp-supported-hw = <0x1>; ++ }; ++ ++ scmi_sram: sram@2ffff000 { ++ compatible = "mmio-sram"; ++ reg = <0x2ffff000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x2ffff000 0x1000>; ++ ++ scmi0_shm: scmi_shm@0 { ++ reg = <0 0x80>; ++ }; ++ ++ scmi1_shm: scmi_shm@200 { ++ reg = <0x200 0x80>; ++ }; ++ }; ++ ++ firmware { ++ scmi0: scmi0 { ++ compatible = "arm,scmi-smc"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ arm,smc-id = <0x82002000>; ++ shmem = <&scmi0_shm>; ++ ++ scmi0_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ ++ scmi0_reset: protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <1>; ++ }; + }; +- opp-800000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <1350000>; +- opp-supported-hw = <0x2>; ++ ++ scmi1: scmi1 { ++ compatible = "arm,scmi-smc"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ arm,smc-id = <0x82002001>; ++ shmem = <&scmi1_shm>; ++ status = "disabled"; ++ ++ scmi1_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; + }; + }; + +@@ -61,38 +113,7 @@ + , + ; + interrupt-parent = <&intc>; +- }; +- +- clocks { +- clk_hse: clk-hse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- +- clk_hsi: clk-hsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <64000000>; +- }; +- +- clk_lse: clk-lse { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- }; +- +- clk_lsi: clk-lsi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- }; +- +- clk_csi: clk-csi { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <4000000>; +- }; ++ always-on; + }; + + thermal-zones { +@@ -102,12 +123,6 @@ + thermal-sensors = <&dts>; + + trips { +- cpu_alert1: cpu-alert1 { +- temperature = <85000>; +- hysteresis = <0>; +- type = "passive"; +- }; +- + cpu-crit { + temperature = <120000>; + hysteresis = <0>; +@@ -126,6 +141,26 @@ + status = "disabled"; + }; + ++ pm_domain { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32mp157c-pd"; ++ ++ pd_core_ret: core-ret-power-domain@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ #power-domain-cells = <0>; ++ label = "CORE-RETENTION"; ++ ++ pd_core: core-power-domain@2 { ++ reg = <2>; ++ #power-domain-cells = <0>; ++ label = "CORE"; ++ }; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <1>; +@@ -133,6 +168,14 @@ + interrupt-parent = <&intc>; + ranges; + ++ sram: sram@10000000 { ++ compatible = "mmio-sram"; ++ reg = <0x10000000 0x60000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x10000000 0x60000>; ++ }; ++ + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; +@@ -140,11 +183,11 @@ + reg = <0x40000000 0x400>; + clocks = <&rcc TIM2_K>; + clock-names = "int"; +- dmas = <&dmamux1 18 0x400 0x1>, +- <&dmamux1 19 0x400 0x1>, +- <&dmamux1 20 0x400 0x1>, +- <&dmamux1 21 0x400 0x1>, +- <&dmamux1 22 0x400 0x1>; ++ dmas = <&dmamux1 18 0x400 0x80000001>, ++ <&dmamux1 19 0x400 0x80000001>, ++ <&dmamux1 20 0x400 0x80000001>, ++ <&dmamux1 21 0x400 0x80000001>, ++ <&dmamux1 22 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + +@@ -173,12 +216,12 @@ + reg = <0x40001000 0x400>; + clocks = <&rcc TIM3_K>; + clock-names = "int"; +- dmas = <&dmamux1 23 0x400 0x1>, +- <&dmamux1 24 0x400 0x1>, +- <&dmamux1 25 0x400 0x1>, +- <&dmamux1 26 0x400 0x1>, +- <&dmamux1 27 0x400 0x1>, +- <&dmamux1 28 0x400 0x1>; ++ dmas = <&dmamux1 23 0x400 0x80000001>, ++ <&dmamux1 24 0x400 0x80000001>, ++ <&dmamux1 25 0x400 0x80000001>, ++ <&dmamux1 26 0x400 0x80000001>, ++ <&dmamux1 27 0x400 0x80000001>, ++ <&dmamux1 28 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + +@@ -207,10 +250,10 @@ + reg = <0x40002000 0x400>; + clocks = <&rcc TIM4_K>; + clock-names = "int"; +- dmas = <&dmamux1 29 0x400 0x1>, +- <&dmamux1 30 0x400 0x1>, +- <&dmamux1 31 0x400 0x1>, +- <&dmamux1 32 0x400 0x1>; ++ dmas = <&dmamux1 29 0x400 0x80000001>, ++ <&dmamux1 30 0x400 0x80000001>, ++ <&dmamux1 31 0x400 0x80000001>, ++ <&dmamux1 32 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4"; + status = "disabled"; + +@@ -239,12 +282,12 @@ + reg = <0x40003000 0x400>; + clocks = <&rcc TIM5_K>; + clock-names = "int"; +- dmas = <&dmamux1 55 0x400 0x1>, +- <&dmamux1 56 0x400 0x1>, +- <&dmamux1 57 0x400 0x1>, +- <&dmamux1 58 0x400 0x1>, +- <&dmamux1 59 0x400 0x1>, +- <&dmamux1 60 0x400 0x1>; ++ dmas = <&dmamux1 55 0x400 0x80000001>, ++ <&dmamux1 56 0x400 0x80000001>, ++ <&dmamux1 57 0x400 0x80000001>, ++ <&dmamux1 58 0x400 0x80000001>, ++ <&dmamux1 59 0x400 0x80000001>, ++ <&dmamux1 60 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + +@@ -273,7 +316,7 @@ + reg = <0x40004000 0x400>; + clocks = <&rcc TIM6_K>; + clock-names = "int"; +- dmas = <&dmamux1 69 0x400 0x1>; ++ dmas = <&dmamux1 69 0x400 0x80000001>; + dma-names = "up"; + status = "disabled"; + +@@ -291,7 +334,7 @@ + reg = <0x40005000 0x400>; + clocks = <&rcc TIM7_K>; + clock-names = "int"; +- dmas = <&dmamux1 70 0x400 0x1>; ++ dmas = <&dmamux1 70 0x400 0x80000001>; + dma-names = "up"; + status = "disabled"; + +@@ -373,8 +416,11 @@ + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; ++ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + + pwm { +@@ -393,6 +439,11 @@ + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; + }; + + spi2: spi@4000b000 { +@@ -403,9 +454,10 @@ + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; +- dmas = <&dmamux1 39 0x400 0x05>, +- <&dmamux1 40 0x400 0x05>; ++ dmas = <&dmamux1 39 0x400 0x01>, ++ <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -428,9 +480,10 @@ + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; +- dmas = <&dmamux1 61 0x400 0x05>, +- <&dmamux1 62 0x400 0x05>; ++ dmas = <&dmamux1 61 0x400 0x01>, ++ <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -461,32 +514,52 @@ + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 43 0x400 0x15>, ++ <&dmamux1 44 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 45 0x400 0x15>, ++ <&dmamux1 46 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 63 0x400 0x15>, ++ <&dmamux1 64 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 65 0x400 0x15>, ++ <&dmamux1 66 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +@@ -494,14 +567,19 @@ + compatible = "st,stm32mp15-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; ++ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&dmamux1 33 0x400 0x80000001>, ++ <&dmamux1 34 0x400 0x80000001>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +@@ -509,14 +587,19 @@ + compatible = "st,stm32mp15-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; ++ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&dmamux1 35 0x400 0x80000001>, ++ <&dmamux1 36 0x400 0x80000001>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +@@ -524,14 +607,19 @@ + compatible = "st,stm32mp15-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; ++ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&dmamux1 73 0x400 0x80000001>, ++ <&dmamux1 74 0x400 0x80000001>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +@@ -539,14 +627,19 @@ + compatible = "st,stm32mp15-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; ++ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&dmamux1 115 0x400 0x80000001>, ++ <&dmamux1 116 0x400 0x80000001>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +@@ -554,7 +647,7 @@ + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = ; +- clocks = <&rcc CEC_K>, <&clk_lse>; ++ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; +@@ -586,16 +679,26 @@ + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 79 0x400 0x15>, ++ <&dmamux1 80 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 81 0x400 0x15>, ++ <&dmamux1 82 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +@@ -606,13 +709,13 @@ + reg = <0x44000000 0x400>; + clocks = <&rcc TIM1_K>; + clock-names = "int"; +- dmas = <&dmamux1 11 0x400 0x1>, +- <&dmamux1 12 0x400 0x1>, +- <&dmamux1 13 0x400 0x1>, +- <&dmamux1 14 0x400 0x1>, +- <&dmamux1 15 0x400 0x1>, +- <&dmamux1 16 0x400 0x1>, +- <&dmamux1 17 0x400 0x1>; ++ dmas = <&dmamux1 11 0x400 0x80000001>, ++ <&dmamux1 12 0x400 0x80000001>, ++ <&dmamux1 13 0x400 0x80000001>, ++ <&dmamux1 14 0x400 0x80000001>, ++ <&dmamux1 15 0x400 0x80000001>, ++ <&dmamux1 16 0x400 0x80000001>, ++ <&dmamux1 17 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; +@@ -642,13 +745,13 @@ + reg = <0x44001000 0x400>; + clocks = <&rcc TIM8_K>; + clock-names = "int"; +- dmas = <&dmamux1 47 0x400 0x1>, +- <&dmamux1 48 0x400 0x1>, +- <&dmamux1 49 0x400 0x1>, +- <&dmamux1 50 0x400 0x1>, +- <&dmamux1 51 0x400 0x1>, +- <&dmamux1 52 0x400 0x1>, +- <&dmamux1 53 0x400 0x1>; ++ dmas = <&dmamux1 47 0x400 0x80000001>, ++ <&dmamux1 48 0x400 0x80000001>, ++ <&dmamux1 49 0x400 0x80000001>, ++ <&dmamux1 50 0x400 0x80000001>, ++ <&dmamux1 51 0x400 0x80000001>, ++ <&dmamux1 52 0x400 0x80000001>, ++ <&dmamux1 53 0x400 0x80000001>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; +@@ -674,8 +777,13 @@ + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; +- interrupts = ; ++ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; ++ wakeup-source; ++ power-domains = <&pd_core>; ++ dmas = <&dmamux1 71 0x400 0x15>, ++ <&dmamux1 72 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +@@ -687,9 +795,10 @@ + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; +- dmas = <&dmamux1 37 0x400 0x05>, +- <&dmamux1 38 0x400 0x05>; ++ dmas = <&dmamux1 37 0x400 0x01>, ++ <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -712,9 +821,10 @@ + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; +- dmas = <&dmamux1 83 0x400 0x05>, +- <&dmamux1 84 0x400 0x05>; ++ dmas = <&dmamux1 83 0x400 0x01>, ++ <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -725,10 +835,10 @@ + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; +- dmas = <&dmamux1 105 0x400 0x1>, +- <&dmamux1 106 0x400 0x1>, +- <&dmamux1 107 0x400 0x1>, +- <&dmamux1 108 0x400 0x1>; ++ dmas = <&dmamux1 105 0x400 0x80000001>, ++ <&dmamux1 106 0x400 0x80000001>, ++ <&dmamux1 107 0x400 0x80000001>, ++ <&dmamux1 108 0x400 0x80000001>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + +@@ -752,8 +862,8 @@ + reg = <0x44007000 0x400>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; +- dmas = <&dmamux1 109 0x400 0x1>, +- <&dmamux1 110 0x400 0x1>; ++ dmas = <&dmamux1 109 0x400 0x80000001>, ++ <&dmamux1 110 0x400 0x80000001>; + dma-names = "ch1", "up"; + status = "disabled"; + +@@ -776,8 +886,8 @@ + reg = <0x44008000 0x400>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; +- dmas = <&dmamux1 111 0x400 0x1>, +- <&dmamux1 112 0x400 0x1>; ++ dmas = <&dmamux1 111 0x400 0x80000001>, ++ <&dmamux1 112 0x400 0x80000001>; + dma-names = "ch1", "up"; + status = "disabled"; + +@@ -802,9 +912,10 @@ + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; +- dmas = <&dmamux1 85 0x400 0x05>, +- <&dmamux1 86 0x400 0x05>; ++ dmas = <&dmamux1 85 0x400 0x01>, ++ <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -822,7 +933,7 @@ + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x1c>; ++ reg = <0x4 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; +@@ -832,7 +943,7 @@ + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x1c>; ++ reg = <0x24 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; +@@ -853,7 +964,7 @@ + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x1c>; ++ reg = <0x4 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; +@@ -863,7 +974,7 @@ + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x1c>; ++ reg = <0x24 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; +@@ -884,7 +995,7 @@ + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x1c>; ++ reg = <0x04 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; +@@ -894,7 +1005,7 @@ + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x1c>; ++ reg = <0x24 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; +@@ -988,6 +1099,15 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>, ++ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>, ++ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>, ++ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>, ++ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>, ++ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>, ++ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>, ++ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>; ++ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; + }; + + dma2: dma-controller@48001000 { +@@ -1006,11 +1126,20 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>, ++ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>, ++ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>, ++ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>, ++ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>, ++ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>, ++ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>, ++ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>; ++ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; +- reg = <0x48002000 0x1c>; ++ reg = <0x48002000 0x40>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; +@@ -1039,7 +1168,7 @@ + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; +- dmas = <&dmamux1 9 0x400 0x01>; ++ dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + }; +@@ -1050,7 +1179,7 @@ + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; +- dmas = <&dmamux1 10 0x400 0x01>; ++ dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + }; +@@ -1058,7 +1187,7 @@ + + sdmmc3: sdmmc@48004000 { + compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x10153180>; ++ arm,primecell-periphid = <0x00253180>; + reg = <0x48004000 0x400>; + interrupts = ; + interrupt-names = "cmd_irq"; +@@ -1078,21 +1207,23 @@ + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; +- interrupts = ; +- g-rx-fifo-size = <256>; ++ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>; ++ g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <128 128 64 64 64 64 32 32>; ++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + usb33d-supply = <&usb33>; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + }; + +- hwspinlock: hwspinlock@4c000000 { ++ hsem: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; +- #hwlock-cells = <1>; ++ #hwlock-cells = <2>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; +- clock-names = "hwspinlock"; ++ clock-names = "hsem"; + }; + + ipcc: mailbox@4c001000 { +@@ -1101,12 +1232,12 @@ + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = +- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, +- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, +- <&exti 61 1>; +- interrupt-names = "rx", "tx", "wakeup"; ++ <&exti 61 1>, ++ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; + clocks = <&rcc IPCC>; + wakeup-source; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -1117,21 +1248,30 @@ + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; +- dmas = <&dmamux1 75 0x400 0x0d>; ++ dmas = <&dmamux1 75 0x400 0xe0000001>; + dma-names = "tx"; + status = "disabled"; + }; + + rcc: rcc@50000000 { +- compatible = "st,stm32mp1-rcc", "syscon"; ++ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; ++ interrupts = ; ++ ++ clock-names = "hse", "hsi", "csi", "lse", "lsi"; ++ clocks = <&scmi0_clk CK_SCMI0_HSE>, ++ <&scmi0_clk CK_SCMI0_HSI>, ++ <&scmi0_clk CK_SCMI0_CSI>, ++ <&scmi0_clk CK_SCMI0_LSE>, ++ <&scmi0_clk CK_SCMI0_LSI>; + }; + + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; ++ st,tzcr = <&rcc 0x0 0x1>; + + reg11: reg11 { + regulator-name = "reg11"; +@@ -1153,15 +1293,42 @@ + }; + + pwr_mcu: pwr_mcu@50001014 { +- compatible = "syscon"; ++ compatible = "st,stm32mp151-pwr-mcu", "syscon"; + reg = <0x50001014 0x4>; + }; + ++ pwr_irq: pwr@50001020 { ++ compatible = "st,stm32mp1-pwr"; ++ reg = <0x50001020 0x100>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ ++ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>, ++ <&gpioa 2 GPIO_ACTIVE_HIGH>, ++ <&gpioc 13 GPIO_ACTIVE_HIGH>, ++ <&gpioi 8 GPIO_ACTIVE_HIGH>, ++ <&gpioi 11 GPIO_ACTIVE_HIGH>, ++ <&gpioc 1 GPIO_ACTIVE_HIGH>; ++ }; ++ + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; ++ hwlocks = <&hsem 1 1>; ++ ++ /* exti_pwr is an extra interrupt controller used for ++ * EXTI 55 to 60. It's mapped on pwr interrupt ++ * controller. ++ */ ++ exti_pwr: exti-pwr { ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&pwr_irq>; ++ st,irq-number = <6>; ++ }; + }; + + syscfg: syscon@50020000 { +@@ -1175,8 +1342,11 @@ + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; ++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + + pwm { +@@ -1195,6 +1365,11 @@ + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; + }; + + lptimer3: timer@50022000 { +@@ -1202,8 +1377,11 @@ + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; ++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + + pwm { +@@ -1217,13 +1395,21 @@ + reg = <2>; + status = "disabled"; + }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; ++ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + + pwm { +@@ -1231,13 +1417,21 @@ + #pwm-cells = <3>; + status = "disabled"; + }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; ++ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + + pwm { +@@ -1245,6 +1439,11 @@ + #pwm-cells = <3>; + status = "disabled"; + }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; + }; + + vrefbuf: vrefbuf@50025000 { +@@ -1269,7 +1468,7 @@ + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x1c>; ++ reg = <0x04 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; +@@ -1279,7 +1478,7 @@ + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x1c>; ++ reg = <0x24 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; +@@ -1297,13 +1496,21 @@ + status = "disabled"; + }; + ++ hdp: hdp@5002a000 { ++ compatible = "st,stm32mp1-hdp"; ++ reg = <0x5002a000 0x400>; ++ clocks = <&rcc HDP>; ++ clock-names = "hdp"; ++ status = "disabled"; ++ }; ++ + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = ; +- clocks = <&rcc HASH1>; +- resets = <&rcc HASH1_R>; +- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; ++ clocks = <&scmi0_clk CK_SCMI0_HASH1>; ++ resets = <&scmi0_reset RST_SCMI0_HASH1>; ++ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + status = "disabled"; +@@ -1312,8 +1519,8 @@ + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; +- clocks = <&rcc RNG1_K>; +- resets = <&rcc RNG1_R>; ++ clocks = <&scmi0_clk CK_SCMI0_RNG1>; ++ resets = <&scmi0_reset RST_SCMI0_RNG1>; + status = "disabled"; + }; + +@@ -1322,8 +1529,8 @@ + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; +- resets = <&rcc MDMA_R>; +- #dma-cells = <5>; ++ resets = <&scmi0_reset RST_SCMI0_MDMA>; ++ #dma-cells = <6>; + dma-channels = <32>; + dma-requests = <48>; + }; +@@ -1354,9 +1561,9 @@ + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; +- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, +- <&mdma1 20 0x2 0x12000a08 0x0 0x0>, +- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; ++ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>, ++ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>, ++ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; +@@ -1367,17 +1574,19 @@ + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; +- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, +- <&mdma1 22 0x10 0x100008 0x0 0x0>; ++ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>, ++ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "disabled"; + }; + + sdmmc1: sdmmc@58005000 { + compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x10153180>; ++ arm,primecell-periphid = <0x00253180>; + reg = <0x58005000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; +@@ -1392,7 +1601,7 @@ + + sdmmc2: sdmmc@58007000 { + compatible = "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x10153180>; ++ arm,primecell-periphid = <0x00253180>; + reg = <0x58007000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; +@@ -1422,8 +1631,10 @@ + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; ++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, ++ <&exti 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", ++ "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", +@@ -1440,6 +1651,7 @@ + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -1457,8 +1669,10 @@ + reg = <0x5800d000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; +- interrupts = ; ++ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>; + companion = <&usbh_ohci>; ++ power-domains = <&pd_core>; ++ wakeup-source; + status = "disabled"; + }; + +@@ -1481,7 +1695,7 @@ + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; +- clocks = <&rcc IWDG2>, <&rcc CK_LSI>; ++ clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; +@@ -1489,6 +1703,7 @@ + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; ++ #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; +@@ -1508,11 +1723,21 @@ + }; + }; + ++ ddrperfm: perf@5a007000 { ++ compatible = "st,stm32-ddr-pmu"; ++ reg = <0x5a007000 0x400>; ++ clocks = <&rcc DDRPERFM>; ++ resets = <&rcc DDRPERFM_R>; ++ }; ++ + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; +- interrupts = ; +- clocks = <&rcc USART1_K>; ++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&scmi0_clk CK_SCMI0_USART1>; ++ resets = <&scmi0_reset RST_SCMI0_USART1>; ++ wakeup-source; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -1522,11 +1747,12 @@ + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; +- clocks = <&rcc SPI6_K>; +- resets = <&rcc SPI6_R>; +- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, +- <&mdma1 35 0x0 0x40002 0x0 0x0>; ++ clocks = <&scmi0_clk CK_SCMI0_SPI6>; ++ resets = <&scmi0_reset RST_SCMI0_SPI6>; ++ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>, ++ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>; + dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + status = "disabled"; + }; + +@@ -1534,23 +1760,29 @@ + compatible = "st,stm32mp15-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C4_K>; +- resets = <&rcc I2C4_R>; ++ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&scmi0_clk CK_SCMI0_I2C4>; ++ resets = <&scmi0_reset RST_SCMI0_I2C4>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>, ++ <&mdma1 37 0x0 0x40002 0x0 0x0 0>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; +- clocks = <&rcc RTCAPB>, <&rcc RTC>; ++ clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, ++ <&scmi0_clk CK_SCMI0_RTC>; + clock-names = "pclk", "rtc_ck"; +- interrupts = ; ++ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + +@@ -1568,20 +1800,28 @@ + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; ++ ethernet_mac_address: mac@e4 { ++ reg = <0xe4 0x6>; ++ }; + }; + + i2c6: i2c@5c009000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C6_K>; +- resets = <&rcc I2C6_R>; ++ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&scmi0_clk CK_SCMI0_I2C6>; ++ resets = <&scmi0_reset RST_SCMI0_I2C6>; + #address-cells = <1>; + #size-cells = <0>; ++ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>, ++ <&mdma1 39 0x0 0x40002 0x0 0x0 0>; ++ dma-names = "rx", "tx"; ++ power-domains = <&pd_core>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +@@ -1596,7 +1836,7 @@ + ranges = <0 0x50002000 0xa400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; +- hwlocks = <&hwspinlock 0>; ++ hwlocks = <&hsem 0 1>; + pins-are-numbered; + + gpioa: gpio@50002000 { +@@ -1729,7 +1969,7 @@ + pins-are-numbered; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; +- hwlocks = <&hwspinlock 0>; ++ hwlocks = <&hsem 0 1>; + + gpioz: gpio@54004000 { + gpio-controller; +@@ -1737,12 +1977,30 @@ + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; +- clocks = <&rcc GPIOZ>; ++ clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + }; ++ ++ tamp: tamp@5c00a000 { ++ compatible = "simple-bus", "syscon", "simple-mfd"; ++ reg = <0x5c00a000 0x400>; ++ ++ reboot-mode { ++ compatible = "syscon-reboot-mode"; ++ offset = <0x150>; /* reg20 */ ++ mask = <0xff>; ++ mode-normal = <0>; ++ mode-fastboot = <0x1>; ++ mode-recovery = <0x2>; ++ mode-stm32cubeprogrammer = <0x3>; ++ mode-ums_mmc0 = <0x10>; ++ mode-ums_mmc1 = <0x11>; ++ mode-ums_mmc2 = <0x12>; ++ }; ++ }; + }; + + mlahb: ahb { +@@ -1759,11 +2017,18 @@ + reg = <0x10000000 0x40000>, + <0x30000000 0x40000>, + <0x38000000 0x10000>; +- resets = <&rcc MCU_R>; +- st,syscfg-holdboot = <&rcc 0x10C 0x1>; +- st,syscfg-tz = <&rcc 0x000 0x1>; ++ resets = <&scmi0_reset RST_SCMI0_MCU>, ++ <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; ++ reset-names = "mcu_rst", "hold_boot"; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; ++ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; ++ st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; + status = "disabled"; ++ ++ m4_system_resources { ++ compatible = "rproc-srm-core"; ++ status = "disabled"; ++ }; + }; + }; + }; +diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi +index 6d9ab08667..cf16b843c6 100644 +--- a/arch/arm/dts/stm32mp153.dtsi ++++ b/arch/arm/dts/stm32mp153.dtsi +@@ -10,12 +10,20 @@ + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; +- clock-frequency = <650000000>; + device_type = "cpu"; + reg = <1>; ++ clocks = <&scmi0_clk CK_SCMI0_MPU>; ++ clock-names = "cpu"; ++ operating-points-v2 = <&cpu0_opp_table>; + }; + }; + ++ arm-pmu { ++ interrupts = , ++ ; ++ interrupt-affinity = <&cpu0>, <&cpu1>; ++ }; ++ + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; +@@ -24,7 +32,7 @@ + interrupts = , + ; + interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; +@@ -37,7 +45,7 @@ + interrupts = , + ; + interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; +diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi +index 54e73ccea4..8a34964b9d 100644 +--- a/arch/arm/dts/stm32mp157.dtsi ++++ b/arch/arm/dts/stm32mp157.dtsi +@@ -20,7 +20,8 @@ + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; +- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; ++ phy-dsi-supply = <®18>; ++ clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; +diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +index 6787619290..8553570642 100644 +--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +@@ -16,12 +16,18 @@ + config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; +- u-boot,mmc-env-partition = "ssbl"; ++ u-boot,mmc-env-partition = "fip"; + st,adc_usb_pd = <&adc1 18>, <&adc1 19>; + st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + }; + ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ config { ++ u-boot,mmc-env-partition = "ssbl"; ++ }; ++ ++ /* only needed for boot with TF-A, witout FIP support */ + firmware { + optee { + compatible = "linaro,optee-tz"; +@@ -35,9 +41,10 @@ + no-map; + }; + }; ++#endif + + led { +- red { ++ led-red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; +@@ -50,6 +57,7 @@ + status = "okay"; + }; + ++#ifndef CONFIG_TFABOOT + &clk_hse { + st,digbypass; + }; +@@ -65,6 +73,10 @@ + }; + }; + ++&i2s2 { ++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++ + &pmic { + u-boot,dm-pre-reloc; + }; +@@ -161,6 +173,10 @@ + }; + }; + ++&sai2 { ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++ + &sdmmc1 { + u-boot,dm-spl; + }; +@@ -174,6 +190,7 @@ + u-boot,dm-spl; + }; + }; ++#endif + + &uart4 { + u-boot,dm-pre-reloc; +diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts +index d03d4cd260..f415e581a6 100644 +--- a/arch/arm/dts/stm32mp157a-dk1.dts ++++ b/arch/arm/dts/stm32mp157a-dk1.dts +@@ -7,6 +7,7 @@ + /dts-v1/; + + #include "stm32mp157.dtsi" ++#include "stm32mp15xa.dtsi" + #include "stm32mp15-pinctrl.dtsi" + #include "stm32mp15xxac-pinctrl.dtsi" + #include "stm32mp15xx-dkx.dtsi" +@@ -16,8 +17,9 @@ + compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; + + aliases { +- ethernet0 = ðernet0; + serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; + }; + + chosen { +diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi +new file mode 100644 +index 0000000000..f0761901a6 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi +@@ -0,0 +1,228 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2018 ++ */ ++ ++#include ++#include "stm32mp15-u-boot.dtsi" ++#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" ++ ++/ { ++ aliases { ++ i2c3 = &i2c4; ++ mmc0 = &sdmmc1; ++ mmc1 = &sdmmc2; ++ }; ++ ++ config { ++ u-boot,boot-led = "heartbeat"; ++ u-boot,error-led = "error"; ++ u-boot,mmc-env-partition = "fip"; ++ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; ++ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led { ++ led-red { ++ label = "error"; ++ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ status = "okay"; ++ }; ++ }; ++ ++#ifdef CONFIG_STM32MP15x_STM32IMAGE ++ config { ++ u-boot,mmc-env-partition = "ssbl"; ++ }; ++ ++ /* only needed for boot with TF-A, witout FIP support */ ++ firmware { ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; ++ ++ reserved-memory { ++ optee@fe000000 { ++ reg = <0xfe000000 0x02000000>; ++ no-map; ++ }; ++ }; ++#endif ++}; ++ ++#ifndef CONFIG_TFABOOT ++&clk_hse { ++ st,digbypass; ++}; ++ ++&i2c4 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c4_pins_a { ++ u-boot,dm-pre-reloc; ++ pins { ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&pmic { ++ u-boot,dm-pre-reloc; ++}; ++ ++&rcc { ++ st,clksrc = < ++ CLK_MPU_PLL1P ++ CLK_AXI_PLL2P ++ CLK_MCU_PLL3P ++ CLK_PLL12_HSE ++ CLK_PLL3_HSE ++ CLK_PLL4_HSE ++ CLK_RTC_LSE ++ CLK_MCO1_DISABLED ++ CLK_MCO2_DISABLED ++ >; ++ ++ st,clkdiv = < ++ 1 /*MPU*/ ++ 0 /*AXI*/ ++ 0 /*MCU*/ ++ 1 /*APB1*/ ++ 1 /*APB2*/ ++ 1 /*APB3*/ ++ 1 /*APB4*/ ++ 2 /*APB5*/ ++ 23 /*RTC*/ ++ 0 /*MCO1*/ ++ 0 /*MCO2*/ ++ >; ++ ++ st,pkcs = < ++ CLK_CKPER_HSE ++ CLK_FMC_ACLK ++ CLK_QSPI_ACLK ++ CLK_ETH_DISABLED ++ CLK_SDMMC12_PLL4P ++ CLK_DSI_DSIPLL ++ CLK_STGEN_HSE ++ CLK_USBPHY_HSE ++ CLK_SPI2S1_PLL3Q ++ CLK_SPI2S23_PLL3Q ++ CLK_SPI45_HSI ++ CLK_SPI6_HSI ++ CLK_I2C46_HSI ++ CLK_SDMMC3_PLL4P ++ CLK_USBO_USBPHY ++ CLK_ADC_CKPER ++ CLK_CEC_LSE ++ CLK_I2C12_HSI ++ CLK_I2C35_HSI ++ CLK_UART1_HSI ++ CLK_UART24_HSI ++ CLK_UART35_HSI ++ CLK_UART6_HSI ++ CLK_UART78_HSI ++ CLK_SPDIF_PLL4P ++ CLK_FDCAN_PLL4R ++ CLK_SAI1_PLL3Q ++ CLK_SAI2_PLL3Q ++ CLK_SAI3_PLL3Q ++ CLK_SAI4_PLL3Q ++ CLK_RNG1_LSI ++ CLK_RNG2_LSI ++ CLK_LPTIM1_PCLK1 ++ CLK_LPTIM23_PCLK3 ++ CLK_LPTIM45_LSE ++ >; ++ ++ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ ++ pll2: st,pll@1 { ++ compatible = "st,stm32mp1-pll"; ++ reg = <1>; ++ cfg = < 2 65 1 0 0 PQR(1,1,1) >; ++ frac = < 0x1400 >; ++ u-boot,dm-pre-reloc; ++ }; ++ ++ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ ++ pll3: st,pll@2 { ++ compatible = "st,stm32mp1-pll"; ++ reg = <2>; ++ cfg = < 1 33 1 16 36 PQR(1,1,1) >; ++ frac = < 0x1a04 >; ++ u-boot,dm-pre-reloc; ++ }; ++ ++ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ ++ pll4: st,pll@3 { ++ compatible = "st,stm32mp1-pll"; ++ reg = <3>; ++ cfg = < 3 98 5 7 7 PQR(1,1,1) >; ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&sdmmc1 { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc1_b4_pins_a { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&sdmmc1_dir_pins_a { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&sdmmc2 { ++ u-boot,dm-spl; ++}; ++ ++&sdmmc2_b4_pins_a { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&sdmmc2_d47_pins_a { ++ u-boot,dm-spl; ++ pins { ++ u-boot,dm-spl; ++ }; ++}; ++#endif ++ ++&uart4 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&uart4_pins_a { ++ u-boot,dm-pre-reloc; ++ pins1 { ++ u-boot,dm-pre-reloc; ++ }; ++ pins2 { ++ u-boot,dm-pre-reloc; ++ /* pull-up on rx to avoid floating level */ ++ bias-pull-up; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts +new file mode 100644 +index 0000000000..0213ca5c17 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157a-ed1.dts +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xa.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxaa-pinctrl.dtsi" ++#include "stm32mp15xx-edx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157A eval daughter"; ++ compatible = "st,stm32mp157a-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ gpu_reserved: gpu@f6000000 { ++ reg = <0xf6000000 0x8000000>; ++ no-map; ++ }; ++ }; ++}; ++ ++&gpu { ++ contiguous-area = <&gpu_reserved>; ++}; +diff --git a/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi +new file mode 100644 +index 0000000000..0dd2243157 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi +@@ -0,0 +1,62 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2018 ++ */ ++ ++#include "stm32mp157c-ed1-u-boot.dtsi" ++ ++/ { ++ aliases { ++ gpio26 = &stmfx_pinctrl; ++ i2c1 = &i2c2; ++ i2c4 = &i2c5; ++ pinctrl2 = &stmfx_pinctrl; ++ spi0 = &qspi; ++ usb0 = &usbotg_hs; ++ }; ++}; ++ ++#ifndef CONFIG_TFABOOT ++&flash0 { ++ u-boot,dm-spl; ++}; ++ ++&qspi { ++ u-boot,dm-spl; ++}; ++ ++&qspi_clk_pins_a { ++ u-boot,dm-spl; ++ pins { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&qspi_bk1_pins_a { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&qspi_bk2_pins_a { ++ u-boot,dm-spl; ++ pins1 { ++ u-boot,dm-spl; ++ }; ++ pins2 { ++ u-boot,dm-spl; ++ }; ++}; ++&sai2 { ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++ ++&sai4 { ++ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++}; ++#endif ++ +diff --git a/arch/arm/dts/stm32mp157a-ev1.dts b/arch/arm/dts/stm32mp157a-ev1.dts +new file mode 100644 +index 0000000000..11bd88a82f +--- /dev/null ++++ b/arch/arm/dts/stm32mp157a-ev1.dts +@@ -0,0 +1,88 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157a-ed1.dts" ++#include "stm32mp15xx-evx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157A eval daughter on eval mother"; ++ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ }; ++}; ++ ++<dc { ++ status = "okay"; ++ ++ port { ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&dsi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&dsi_panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_dsi: panel-dsi@0 { ++ compatible = "raydium,rm68200"; ++ reg = <0>; ++ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; ++ backlight = <&panel_backlight>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ dsi_panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ gt9147: goodix_ts@5d { ++ compatible = "goodix,gt9147"; ++ reg = <0x5d>; ++ panel = <&panel_dsi>; ++ pinctrl-0 = <&goodix_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ interrupts = <14 IRQ_TYPE_EDGE_RISING>; ++ interrupt-parent = <&stmfx_pinctrl>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts +index 9a8a26710a..1c894f288c 100644 +--- a/arch/arm/dts/stm32mp157c-dk2.dts ++++ b/arch/arm/dts/stm32mp157c-dk2.dts +@@ -11,24 +11,35 @@ + #include "stm32mp15-pinctrl.dtsi" + #include "stm32mp15xxac-pinctrl.dtsi" + #include "stm32mp15xx-dkx.dtsi" ++#include + + / { + model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; + compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; + + aliases { +- ethernet0 = ðernet0; + serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; ++ serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&cryp1 { ++ status = "okay"; + }; + + &dsi { + status = "okay"; +- phy-dsi-supply = <®18>; + + ports { + port@0 { +@@ -46,7 +57,7 @@ + }; + }; + +- panel@0 { ++ panel_otm8009a: panel-otm8009a@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; +@@ -62,6 +73,18 @@ + }; + + &i2c1 { ++ touchscreen@2a { ++ compatible = "focaltech,ft6236"; ++ reg = <0x2a>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; + touchscreen@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; +@@ -70,6 +93,8 @@ + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; + status = "okay"; + }; + }; +@@ -84,3 +109,49 @@ + }; + }; + }; ++ ++&rtc { ++ st,lsco = ; ++ pinctrl-0 = <&rtc_out2_rmp_pins_a>; ++ pinctrl-names = "default"; ++}; ++ ++/* Wifi */ ++&sdmmc2 { ++ arm,primecell-periphid = <0x10153180>; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; ++ non-removable; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* Bluetooth */ ++&usart2 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&usart2_pins_c>; ++ pinctrl-1 = <&usart2_sleep_pins_c>; ++ pinctrl-2 = <&usart2_idle_pins_c>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +index f3002e995b..44a689bbec 100644 +--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +@@ -3,217 +3,4 @@ + * Copyright : STMicroelectronics 2018 + */ + +-#include +-#include "stm32mp15-u-boot.dtsi" +-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" +- +-/ { +- aliases { +- i2c3 = &i2c4; +- mmc0 = &sdmmc1; +- mmc1 = &sdmmc2; +- }; +- +- config { +- u-boot,boot-led = "heartbeat"; +- u-boot,error-led = "error"; +- u-boot,mmc-env-partition = "ssbl"; +- st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; +- st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; +- }; +- +- firmware { +- optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- }; +- +- reserved-memory { +- optee@fe000000 { +- reg = <0xfe000000 0x02000000>; +- no-map; +- }; +- }; +- +- led { +- red { +- label = "error"; +- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; +- default-state = "off"; +- status = "okay"; +- }; +- }; +-}; +- +-&clk_hse { +- st,digbypass; +-}; +- +-&i2c4 { +- u-boot,dm-pre-reloc; +-}; +- +-&i2c4_pins_a { +- u-boot,dm-pre-reloc; +- pins { +- u-boot,dm-pre-reloc; +- }; +-}; +- +-&pmic { +- u-boot,dm-pre-reloc; +-}; +- +-&rcc { +- st,clksrc = < +- CLK_MPU_PLL1P +- CLK_AXI_PLL2P +- CLK_MCU_PLL3P +- CLK_PLL12_HSE +- CLK_PLL3_HSE +- CLK_PLL4_HSE +- CLK_RTC_LSE +- CLK_MCO1_DISABLED +- CLK_MCO2_DISABLED +- >; +- +- st,clkdiv = < +- 1 /*MPU*/ +- 0 /*AXI*/ +- 0 /*MCU*/ +- 1 /*APB1*/ +- 1 /*APB2*/ +- 1 /*APB3*/ +- 1 /*APB4*/ +- 2 /*APB5*/ +- 23 /*RTC*/ +- 0 /*MCO1*/ +- 0 /*MCO2*/ +- >; +- +- st,pkcs = < +- CLK_CKPER_HSE +- CLK_FMC_ACLK +- CLK_QSPI_ACLK +- CLK_ETH_DISABLED +- CLK_SDMMC12_PLL4P +- CLK_DSI_DSIPLL +- CLK_STGEN_HSE +- CLK_USBPHY_HSE +- CLK_SPI2S1_PLL3Q +- CLK_SPI2S23_PLL3Q +- CLK_SPI45_HSI +- CLK_SPI6_HSI +- CLK_I2C46_HSI +- CLK_SDMMC3_PLL4P +- CLK_USBO_USBPHY +- CLK_ADC_CKPER +- CLK_CEC_LSE +- CLK_I2C12_HSI +- CLK_I2C35_HSI +- CLK_UART1_HSI +- CLK_UART24_HSI +- CLK_UART35_HSI +- CLK_UART6_HSI +- CLK_UART78_HSI +- CLK_SPDIF_PLL4P +- CLK_FDCAN_PLL4R +- CLK_SAI1_PLL3Q +- CLK_SAI2_PLL3Q +- CLK_SAI3_PLL3Q +- CLK_SAI4_PLL3Q +- CLK_RNG1_LSI +- CLK_RNG2_LSI +- CLK_LPTIM1_PCLK1 +- CLK_LPTIM23_PCLK3 +- CLK_LPTIM45_LSE +- >; +- +- /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ +- pll2: st,pll@1 { +- compatible = "st,stm32mp1-pll"; +- reg = <1>; +- cfg = < 2 65 1 0 0 PQR(1,1,1) >; +- frac = < 0x1400 >; +- u-boot,dm-pre-reloc; +- }; +- +- /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ +- pll3: st,pll@2 { +- compatible = "st,stm32mp1-pll"; +- reg = <2>; +- cfg = < 1 33 1 16 36 PQR(1,1,1) >; +- frac = < 0x1a04 >; +- u-boot,dm-pre-reloc; +- }; +- +- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ +- pll4: st,pll@3 { +- compatible = "st,stm32mp1-pll"; +- reg = <3>; +- cfg = < 3 98 5 7 7 PQR(1,1,1) >; +- u-boot,dm-pre-reloc; +- }; +-}; +- +-&sdmmc1 { +- u-boot,dm-spl; +-}; +- +-&sdmmc1_b4_pins_a { +- u-boot,dm-spl; +- pins1 { +- u-boot,dm-spl; +- }; +- pins2 { +- u-boot,dm-spl; +- }; +-}; +- +-&sdmmc1_dir_pins_a { +- u-boot,dm-spl; +- pins1 { +- u-boot,dm-spl; +- }; +- pins2 { +- u-boot,dm-spl; +- }; +-}; +- +-&sdmmc2 { +- u-boot,dm-spl; +-}; +- +-&sdmmc2_b4_pins_a { +- u-boot,dm-spl; +- pins1 { +- u-boot,dm-spl; +- }; +- pins2 { +- u-boot,dm-spl; +- }; +-}; +- +-&sdmmc2_d47_pins_a { +- u-boot,dm-spl; +- pins { +- u-boot,dm-spl; +- }; +-}; +- +-&uart4 { +- u-boot,dm-pre-reloc; +-}; +- +-&uart4_pins_a { +- u-boot,dm-pre-reloc; +- pins1 { +- u-boot,dm-pre-reloc; +- }; +- pins2 { +- u-boot,dm-pre-reloc; +- /* pull-up on rx to avoid floating level */ +- bias-pull-up; +- }; +-}; ++#include "stm32mp157a-ed1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts +index 072d646379..d2c24803b9 100644 +--- a/arch/arm/dts/stm32mp157c-ed1.dts ++++ b/arch/arm/dts/stm32mp157c-ed1.dts +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + /* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. + */ + /dts-v1/; + +@@ -9,8 +9,7 @@ + #include "stm32mp15xc.dtsi" + #include "stm32mp15-pinctrl.dtsi" + #include "stm32mp15xxaa-pinctrl.dtsi" +-#include +-#include ++#include "stm32mp15xx-edx.dtsi" + + / { + model = "STMicroelectronics STM32MP157C eval daughter"; +@@ -20,360 +19,18 @@ + stdout-path = "serial0:115200n8"; + }; + +- memory@c0000000 { +- device_type = "memory"; +- reg = <0xC0000000 0x40000000>; +- }; +- + reserved-memory { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mcuram2: mcuram2@10000000 { +- compatible = "shared-dma-pool"; +- reg = <0x10000000 0x40000>; ++ gpu_reserved: gpu@f6000000 { ++ reg = <0xf6000000 0x8000000>; + no-map; + }; +- +- vdev0vring0: vdev0vring0@10040000 { +- compatible = "shared-dma-pool"; +- reg = <0x10040000 0x1000>; +- no-map; +- }; +- +- vdev0vring1: vdev0vring1@10041000 { +- compatible = "shared-dma-pool"; +- reg = <0x10041000 0x1000>; +- no-map; +- }; +- +- vdev0buffer: vdev0buffer@10042000 { +- compatible = "shared-dma-pool"; +- reg = <0x10042000 0x4000>; +- no-map; +- }; +- +- mcuram: mcuram@30000000 { +- compatible = "shared-dma-pool"; +- reg = <0x30000000 0x40000>; +- no-map; +- }; +- +- retram: retram@38000000 { +- compatible = "shared-dma-pool"; +- reg = <0x38000000 0x10000>; +- no-map; +- }; +- +- gpu_reserved: gpu@e8000000 { +- reg = <0xe8000000 0x8000000>; +- no-map; +- }; +- }; +- +- aliases { +- serial0 = &uart4; +- }; +- +- sd_switch: regulator-sd_switch { +- compatible = "regulator-gpio"; +- regulator-name = "sd_switch"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <2900000>; +- regulator-type = "voltage"; +- regulator-always-on; +- +- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- states = <1800000 0x1>, +- <2900000 0x0>; +- }; +-}; +- +-&adc { +- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ +- pinctrl-0 = <&adc1_in6_pins_a>; +- pinctrl-names = "default"; +- vdd-supply = <&vdd>; +- vdda-supply = <&vdda>; +- vref-supply = <&vdda>; +- status = "disabled"; +- adc1: adc@0 { +- st,adc-channels = <0 1 6>; +- /* 16.5 ck_cycles sampling time */ +- st,min-sample-time-nsecs = <400>; +- status = "okay"; +- }; +-}; +- +-&cpu0{ +- cpu-supply = <&vddcore>; +-}; +- +-&cpu1{ +- cpu-supply = <&vddcore>; +-}; +- +-&dac { +- pinctrl-names = "default"; +- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; +- vref-supply = <&vdda>; +- status = "disabled"; +- dac1: dac@1 { +- status = "okay"; +- }; +- dac2: dac@2 { +- status = "okay"; + }; + }; + +-&dts { ++&cryp1 { + status = "okay"; + }; + + &gpu { + contiguous-area = <&gpu_reserved>; + }; +- +-&i2c4 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c4_pins_a>; +- pinctrl-1 = <&i2c4_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- clock-frequency = <400000>; +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- +- pmic: stpmic@33 { +- compatible = "st,stpmic1"; +- reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- status = "okay"; +- +- regulators { +- compatible = "st,stpmic1-regulators"; +- ldo1-supply = <&v3v3>; +- ldo2-supply = <&v3v3>; +- ldo3-supply = <&vdd_ddr>; +- ldo5-supply = <&v3v3>; +- ldo6-supply = <&v3v3>; +- pwr_sw1-supply = <&bst_out>; +- pwr_sw2-supply = <&bst_out>; +- +- vddcore: buck1 { +- regulator-name = "vddcore"; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd_ddr: buck2 { +- regulator-name = "vdd_ddr"; +- regulator-min-microvolt = <1350000>; +- regulator-max-microvolt = <1350000>; +- regulator-always-on; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- vdd: buck3 { +- regulator-name = "vdd"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- st,mask-reset; +- regulator-initial-mode = <0>; +- regulator-over-current-protection; +- }; +- +- v3v3: buck4 { +- regulator-name = "v3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-over-current-protection; +- regulator-initial-mode = <0>; +- }; +- +- vdda: ldo1 { +- regulator-name = "vdda"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- }; +- +- v2v8: ldo2 { +- regulator-name = "v2v8"; +- regulator-min-microvolt = <2800000>; +- regulator-max-microvolt = <2800000>; +- interrupts = ; +- }; +- +- vtt_ddr: ldo3 { +- regulator-name = "vtt_ddr"; +- regulator-min-microvolt = <500000>; +- regulator-max-microvolt = <750000>; +- regulator-always-on; +- regulator-over-current-protection; +- }; +- +- vdd_usb: ldo4 { +- regulator-name = "vdd_usb"; +- interrupts = ; +- }; +- +- vdd_sd: ldo5 { +- regulator-name = "vdd_sd"; +- regulator-min-microvolt = <2900000>; +- regulator-max-microvolt = <2900000>; +- interrupts = ; +- regulator-boot-on; +- }; +- +- v1v8: ldo6 { +- regulator-name = "v1v8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- interrupts = ; +- }; +- +- vref_ddr: vref_ddr { +- regulator-name = "vref_ddr"; +- regulator-always-on; +- }; +- +- bst_out: boost { +- regulator-name = "bst_out"; +- interrupts = ; +- }; +- +- vbus_otg: pwr_sw1 { +- regulator-name = "vbus_otg"; +- interrupts = ; +- }; +- +- vbus_sw: pwr_sw2 { +- regulator-name = "vbus_sw"; +- interrupts = ; +- regulator-active-discharge = <1>; +- }; +- }; +- +- onkey { +- compatible = "st,stpmic1-onkey"; +- interrupts = , ; +- interrupt-names = "onkey-falling", "onkey-rising"; +- power-off-time-sec = <10>; +- status = "okay"; +- }; +- +- watchdog { +- compatible = "st,stpmic1-wdt"; +- status = "disabled"; +- }; +- }; +-}; +- +-&ipcc { +- status = "okay"; +-}; +- +-&iwdg2 { +- timeout-sec = <32>; +- status = "okay"; +-}; +- +-&m4_rproc { +- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, +- <&vdev0vring1>, <&vdev0buffer>; +- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; +- mbox-names = "vq0", "vq1", "shutdown"; +- interrupt-parent = <&exti>; +- interrupts = <68 1>; +- status = "okay"; +-}; +- +-&pwr_regulators { +- vdd-supply = <&vdd>; +- vdd_3v3_usbfs-supply = <&vdd_usb>; +-}; +- +-&rng1 { +- status = "okay"; +-}; +- +-&rtc { +- status = "okay"; +-}; +- +-&sdmmc1 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; +- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; +- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +- disable-wp; +- st,sig-dir; +- st,neg-edge; +- st,use-ckin; +- bus-width = <4>; +- vmmc-supply = <&vdd_sd>; +- vqmmc-supply = <&sd_switch>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-ddr50; +- status = "okay"; +-}; +- +-&sdmmc2 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; +- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; +- non-removable; +- no-sd; +- no-sdio; +- st,neg-edge; +- bus-width = <8>; +- vmmc-supply = <&v3v3>; +- vqmmc-supply = <&vdd>; +- mmc-ddr-3_3v; +- status = "okay"; +-}; +- +-&timers6 { +- status = "okay"; +- /* spare dmas for other usage */ +- /delete-property/dmas; +- /delete-property/dma-names; +- timer@5 { +- status = "okay"; +- }; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins_a>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- vbus-supply = <&vbus_otg>; +-}; +- +-&usbphyc_port0 { +- phy-supply = <&vdd_usb>; +-}; +- +-&usbphyc_port1 { +- phy-supply = <&vdd_usb>; +-}; +diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +index ec60486f41..cc028066ec 100644 +--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +@@ -3,51 +3,4 @@ + * Copyright : STMicroelectronics 2018 + */ + +-#include "stm32mp157c-ed1-u-boot.dtsi" +- +-/ { +- aliases { +- gpio26 = &stmfx_pinctrl; +- i2c1 = &i2c2; +- i2c4 = &i2c5; +- pinctrl2 = &stmfx_pinctrl; +- spi0 = &qspi; +- usb0 = &usbotg_hs; +- }; +-}; +- +-&flash0 { +- u-boot,dm-spl; +-}; +- +-&qspi { +- u-boot,dm-spl; +-}; +- +-&qspi_clk_pins_a { +- u-boot,dm-spl; +- pins { +- u-boot,dm-spl; +- }; +-}; +- +-&qspi_bk1_pins_a { +- u-boot,dm-spl; +- pins1 { +- u-boot,dm-spl; +- }; +- pins2 { +- u-boot,dm-spl; +- }; +-}; +- +-&qspi_bk2_pins_a { +- u-boot,dm-spl; +- pins1 { +- u-boot,dm-spl; +- }; +- pins2 { +- u-boot,dm-spl; +- }; +-}; +- ++#include "stm32mp157a-ev1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts +index 46f81ce92e..e84897ef44 100644 +--- a/arch/arm/dts/stm32mp157c-ev1.dts ++++ b/arch/arm/dts/stm32mp157c-ev1.dts +@@ -1,13 +1,12 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + /* +- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved +- * Author: Ludovic Barre for STMicroelectronics. ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. + */ + /dts-v1/; + + #include "stm32mp157c-ed1.dts" +-#include +-#include ++#include "stm32mp15xx-evx.dtsi" + + / { + model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; +@@ -19,89 +18,30 @@ + + aliases { + serial0 = &uart4; +- ethernet0 = ðernet0; +- }; +- +- clocks { +- clk_ext_camera: clk-ext-camera { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- }; +- }; +- +- joystick { +- compatible = "gpio-keys"; +- pinctrl-0 = <&joystick_pins>; +- pinctrl-names = "default"; +- button-0 { +- label = "JoySel"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <0 IRQ_TYPE_EDGE_RISING>; +- }; +- button-1 { +- label = "JoyDown"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <1 IRQ_TYPE_EDGE_RISING>; +- }; +- button-2 { +- label = "JoyLeft"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <2 IRQ_TYPE_EDGE_RISING>; +- }; +- button-3 { +- label = "JoyRight"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <3 IRQ_TYPE_EDGE_RISING>; +- }; +- button-4 { +- label = "JoyUp"; +- linux,code = ; +- interrupt-parent = <&stmfx_pinctrl>; +- interrupts = <4 IRQ_TYPE_EDGE_RISING>; +- }; +- }; +- +- panel_backlight: panel-backlight { +- compatible = "gpio-backlight"; +- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; +- default-on; +- status = "okay"; ++ serial1 = &usart3; + }; + }; + +-&cec { +- pinctrl-names = "default"; +- pinctrl-0 = <&cec_pins_a>; +- status = "okay"; +-}; +- +-&dcmi { ++<dc { + status = "okay"; +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&dcmi_pins_a>; +- pinctrl-1 = <&dcmi_sleep_pins_a>; + + port { +- dcmi_0: endpoint { +- remote-endpoint = <&ov5640_0>; +- bus-width = <8>; +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dsi_in>; + }; + }; + }; + + &dsi { +- phy-dsi-supply = <®18>; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "okay"; + + ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ + port@0 { + reg = <0>; + dsi_in: endpoint { +@@ -117,7 +57,7 @@ + }; + }; + +- panel-dsi@0 { ++ panel_dsi: panel-dsi@0 { + compatible = "raydium,rm68200"; + reg = <0>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; +@@ -133,229 +73,16 @@ + }; + }; + +-ðernet0 { +- status = "okay"; +- pinctrl-0 = <ðernet0_rgmii_pins_a>; +- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- phy-mode = "rgmii-id"; +- max-speed = <1000>; +- phy-handle = <&phy0>; +- +- mdio0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&fmc { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&fmc_pins_a>; +- pinctrl-1 = <&fmc_sleep_pins_a>; +- status = "okay"; +- +- nand-controller@4,0 { +- status = "okay"; +- +- nand@0 { +- reg = <0>; +- nand-on-flash-bbt; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- }; +-}; +- + &i2c2 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c2_pins_a>; +- pinctrl-1 = <&i2c2_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- clocks = <&clk_ext_camera>; +- clock-names = "xclk"; +- DOVDD-supply = <&v2v8>; +- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; +- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; +- rotation = <180>; +- status = "okay"; +- +- port { +- ov5640_0: endpoint { +- remote-endpoint = <&dcmi_0>; +- bus-width = <8>; +- data-shift = <2>; /* lines 9:2 are used */ +- hsync-active = <0>; +- vsync-active = <0>; +- pclk-sample = <1>; +- }; +- }; +- }; +- +- stmfx: stmfx@42 { +- compatible = "st,stmfx-0300"; +- reg = <0x42>; +- interrupts = <8 IRQ_TYPE_EDGE_RISING>; +- interrupt-parent = <&gpioi>; +- vdd-supply = <&v3v3>; +- +- stmfx_pinctrl: pinctrl { +- compatible = "st,stmfx-0300-pinctrl"; +- gpio-controller; +- #gpio-cells = <2>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-ranges = <&stmfx_pinctrl 0 0 24>; +- +- joystick_pins: joystick-pins { +- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; +- bias-pull-down; +- }; +- }; +- }; +-}; +- +-&i2c5 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&i2c5_pins_a>; +- pinctrl-1 = <&i2c5_sleep_pins_a>; +- i2c-scl-rising-time-ns = <185>; +- i2c-scl-falling-time-ns = <20>; +- status = "okay"; +-}; +- +-<dc { +- status = "okay"; +- +- port { +- ltdc_ep0_out: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&dsi_in>; +- }; +- }; +-}; +- +-&m_can1 { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&m_can1_pins_a>; +- pinctrl-1 = <&m_can1_sleep_pins_a>; +- status = "okay"; +-}; +- +-&qspi { +- pinctrl-names = "default", "sleep"; +- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; +- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; +- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- flash0: mx66l51235l@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <108000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +- +- flash1: mx66l51235l@1 { +- compatible = "jedec,spi-nor"; +- reg = <1>; +- spi-rx-bus-width = <4>; +- spi-max-frequency = <108000000>; +- #address-cells = <1>; +- #size-cells = <1>; +- }; +-}; +- +-&sdmmc3 { +- pinctrl-names = "default", "opendrain", "sleep"; +- pinctrl-0 = <&sdmmc3_b4_pins_a>; +- pinctrl-1 = <&sdmmc3_b4_od_pins_a>; +- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; +- broken-cd; +- st,neg-edge; +- bus-width = <4>; +- vmmc-supply = <&v3v3>; +- status = "disabled"; +-}; +- +-&spi1 { +- pinctrl-names = "default"; +- pinctrl-0 = <&spi1_pins_a>; +- status = "disabled"; +-}; +- +-&timers2 { +- /* spare dmas for other usage (un-delete to enable pwm capture) */ +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm2_pins_a>; +- pinctrl-1 = <&pwm2_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@1 { ++ gt9147: goodix_ts@5d { ++ compatible = "goodix,gt9147"; ++ reg = <0x5d>; ++ panel = <&panel_dsi>; ++ pinctrl-0 = <&goodix_pins>; ++ pinctrl-names = "default"; + status = "okay"; +- }; +-}; + +-&timers8 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm8_pins_a>; +- pinctrl-1 = <&pwm8_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; ++ interrupts = <14 IRQ_TYPE_EDGE_RISING>; ++ interrupt-parent = <&stmfx_pinctrl>; + }; +- timer@7 { +- status = "okay"; +- }; +-}; +- +-&timers12 { +- /delete-property/dmas; +- /delete-property/dma-names; +- status = "disabled"; +- pwm { +- pinctrl-0 = <&pwm12_pins_a>; +- pinctrl-1 = <&pwm12_sleep_pins_a>; +- pinctrl-names = "default", "sleep"; +- status = "okay"; +- }; +- timer@11 { +- status = "okay"; +- }; +-}; +- +-&usbh_ehci { +- phys = <&usbphyc_port0>; +- status = "okay"; +-}; +- +-&usbotg_hs { +- pinctrl-0 = <&usbotg_hs_pins_a>; +- pinctrl-names = "default"; +- phys = <&usbphyc_port1 0>; +- phy-names = "usb2-phy"; +- status = "okay"; +-}; +- +-&usbphyc { +- status = "okay"; + }; +diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +index 6be728846e..042656a773 100644 +--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +@@ -13,9 +13,11 @@ + }; + }; + ++#ifndef CONFIG_TFABOOT + &clk_hse { + st,digbypass; + }; ++#endif + + &i2c2 { + u-boot,dm-pre-reloc; +@@ -32,6 +34,7 @@ + u-boot,dm-pre-reloc; + }; + ++#ifndef CONFIG_TFABOOT + &rcc { + st,clksrc = < + CLK_MPU_PLL1P +@@ -123,3 +126,4 @@ + u-boot,dm-pre-reloc; + }; + }; ++#endif +diff --git a/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi +new file mode 100644 +index 0000000000..4f9b7a99ce +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157a-dk1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts +new file mode 100644 +index 0000000000..bcc012cfff +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-dk1.dts +@@ -0,0 +1,28 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xd.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include "stm32mp15xx-dkx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board"; ++ compatible = "st,stm32mp157d-dk1", "st,stm32mp157"; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi +new file mode 100644 +index 0000000000..70d9afc6b9 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157a-ed1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts +new file mode 100644 +index 0000000000..5aa383d3b5 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-ed1.dts +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xd.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxaa-pinctrl.dtsi" ++#include "stm32mp15xx-edx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157D eval daughter"; ++ compatible = "st,stm32mp157d-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ gpu_reserved: gpu@f6000000 { ++ reg = <0xf6000000 0x8000000>; ++ no-map; ++ }; ++ }; ++}; ++ ++&gpu { ++ contiguous-area = <&gpu_reserved>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi +new file mode 100644 +index 0000000000..77168a4cdb +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157a-ev1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157d-ev1.dts b/arch/arm/dts/stm32mp157d-ev1.dts +new file mode 100644 +index 0000000000..5cb08c7079 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157d-ev1.dts +@@ -0,0 +1,88 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157d-ed1.dts" ++#include "stm32mp15xx-evx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157D eval daughter on eval mother"; ++ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ }; ++}; ++ ++<dc { ++ status = "okay"; ++ ++ port { ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&dsi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&dsi_panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_dsi: panel-dsi@0 { ++ compatible = "raydium,rm68200"; ++ reg = <0>; ++ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; ++ backlight = <&panel_backlight>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ dsi_panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ gt9147: goodix_ts@5d { ++ compatible = "goodix,gt9147"; ++ reg = <0x5d>; ++ panel = <&panel_dsi>; ++ pinctrl-0 = <&goodix_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ interrupts = <14 IRQ_TYPE_EDGE_RISING>; ++ interrupt-parent = <&stmfx_pinctrl>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi +new file mode 100644 +index 0000000000..1bed79cdf4 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157c-dk2-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts +new file mode 100644 +index 0000000000..15a397c4cf +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-dk2.dts +@@ -0,0 +1,157 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xf.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include "stm32mp15xx-dkx.dtsi" ++#include ++ ++/ { ++ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board"; ++ compatible = "st,stm32mp157f-dk2", "st,stm32mp157"; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ serial2 = &uart7; ++ serial3 = &usart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&cryp1 { ++ status = "okay"; ++}; ++ ++&dsi { ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep1_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_otm8009a: panel-otm8009a@0 { ++ compatible = "orisetech,otm8009a"; ++ reg = <0>; ++ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ touchscreen@2a { ++ compatible = "focaltech,ft6236"; ++ reg = <0x2a>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++ touchscreen@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; ++ interrupts = <2 2>; ++ interrupt-parent = <&gpiof>; ++ interrupt-controller; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ panel = <&panel_otm8009a>; ++ vcc-supply = <&v3v3>; ++ status = "okay"; ++ }; ++}; ++ ++<dc { ++ status = "okay"; ++ ++ port { ++ ltdc_ep1_out: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&rtc { ++ st,lsco = ; ++ pinctrl-0 = <&rtc_out2_rmp_pins_a>; ++ pinctrl-names = "default"; ++}; ++ ++/* Wifi */ ++&sdmmc2 { ++ arm,primecell-periphid = <0x10153180>; ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; ++ non-removable; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* Bluetooth */ ++&usart2 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&usart2_pins_c>; ++ pinctrl-1 = <&usart2_sleep_pins_c>; ++ pinctrl-2 = <&usart2_idle_pins_c>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi +new file mode 100644 +index 0000000000..2b8d2afd55 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157c-ed1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts +new file mode 100644 +index 0000000000..29c6833e28 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-ed1.dts +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xf.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxaa-pinctrl.dtsi" ++#include "stm32mp15xx-edx.dtsi" ++ ++/ { ++ model = "STMicroelectronics STM32MP157F eval daughter"; ++ compatible = "st,stm32mp157f-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ gpu_reserved: gpu@f6000000 { ++ reg = <0xf6000000 0x8000000>; ++ no-map; ++ }; ++ }; ++}; ++ ++&cryp1 { ++ status = "okay"; ++}; ++ ++&gpu { ++ contiguous-area = <&gpu_reserved>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi +new file mode 100644 +index 0000000000..0e415a141d +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * Copyright : STMicroelectronics 2019 ++ */ ++ ++#include "stm32mp157c-ev1-u-boot.dtsi" +diff --git a/arch/arm/dts/stm32mp157f-ev1.dts b/arch/arm/dts/stm32mp157f-ev1.dts +new file mode 100644 +index 0000000000..6fe600f813 +--- /dev/null ++++ b/arch/arm/dts/stm32mp157f-ev1.dts +@@ -0,0 +1,89 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++/dts-v1/; ++ ++#include "stm32mp157f-ed1.dts" ++#include "stm32mp15xx-evx.dtsi" ++#include ++ ++/ { ++ model = "STMicroelectronics STM32MP157F eval daughter on eval mother"; ++ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ serial1 = &usart3; ++ }; ++}; ++ ++<dc { ++ status = "okay"; ++ ++ port { ++ ltdc_ep0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dsi_in>; ++ }; ++ }; ++}; ++ ++&dsi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ dsi_in: endpoint { ++ remote-endpoint = <<dc_ep0_out>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ dsi_out: endpoint { ++ remote-endpoint = <&dsi_panel_in>; ++ }; ++ }; ++ }; ++ ++ panel_dsi: panel-dsi@0 { ++ compatible = "raydium,rm68200"; ++ reg = <0>; ++ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; ++ backlight = <&panel_backlight>; ++ power-supply = <&v3v3>; ++ status = "okay"; ++ ++ port { ++ dsi_panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ gt9147: goodix_ts@5d { ++ compatible = "goodix,gt9147"; ++ reg = <0x5d>; ++ panel = <&panel_dsi>; ++ pinctrl-0 = <&goodix_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ interrupts = <14 IRQ_TYPE_EDGE_RISING>; ++ interrupt-parent = <&stmfx_pinctrl>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi +new file mode 100644 +index 0000000000..5ed7e594f4 +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xa.dtsi +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++ ++&cpu0_opp_table { ++ opp-650000000 { ++ opp-hz = /bits/ 64 <650000000>; ++ opp-microvolt = <1200000>; ++ opp-supported-hw = <0x1>; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi +index b06a55a2fa..adc1568a72 100644 +--- a/arch/arm/dts/stm32mp15xc.dtsi ++++ b/arch/arm/dts/stm32mp15xc.dtsi +@@ -4,14 +4,16 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + ++#include "stm32mp15xa.dtsi" ++ + / { + soc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; ++ clocks = <&scmi0_clk CK_SCMI0_CRYP1>; ++ resets = <&scmi0_reset RST_SCMI0_CRYP1>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi +new file mode 100644 +index 0000000000..e2f8b1297c +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xd.dtsi +@@ -0,0 +1,42 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++ ++&cpu0_opp_table { ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1350000>; ++ opp-supported-hw = <0x2>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <1200000>; ++ opp-supported-hw = <0x2>; ++ opp-suspend; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu-crit { ++ temperature = <105000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ ++ cpu_alert: cpu-alert { ++ temperature = <95000>; ++ hysteresis = <10000>; ++ type = "passive"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = <&cpu0 1 1>; ++ }; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi +new file mode 100644 +index 0000000000..77f50b9bda +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xf.dtsi +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved ++ * Author: Alexandre Torgue for STMicroelectronics. ++ */ ++ ++#include "stm32mp15xd.dtsi" ++ ++/ { ++ soc { ++ cryp1: cryp@54001000 { ++ compatible = "st,stm32mp1-cryp"; ++ reg = <0x54001000 0x400>; ++ interrupts = ; ++ clocks = <&scmi0_clk CK_SCMI0_CRYP1>; ++ resets = <&scmi0_reset RST_SCMI0_CRYP1>; ++ status = "disabled"; ++ }; ++ }; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +index 92345b7ba3..c3727a0c4d 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +@@ -171,6 +171,7 @@ + }; + }; + ++#ifndef CONFIG_TFABOOT + &rcc { + st,clksrc = < + CLK_MPU_PLL1P +@@ -262,6 +263,7 @@ + u-boot,dm-pre-reloc; + }; + }; ++#endif + + &sdmmc1 { + u-boot,dm-spl; +diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +index 9d3db20876..e9c5e5adf2 100644 +--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +@@ -70,6 +70,7 @@ + }; + }; + ++#ifndef CONFIG_TFABOOT + &rcc { + st,clksrc = < + CLK_MPU_PLL1P +@@ -161,3 +162,4 @@ + u-boot,dm-pre-reloc; + }; + }; ++#endif +\ No newline at end of file +diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi +index d660dfb74e..acff8755d3 100644 +--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi ++++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi +@@ -4,10 +4,16 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + ++#include "stm32mp15-m4-srm.dtsi" ++#include "stm32mp15-m4-srm-pinctrl.dtsi" + #include + #include + + / { ++ aliases { ++ ethernet0 = ðernet0; ++ }; ++ + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; +@@ -62,7 +68,7 @@ + + led { + compatible = "gpio-leds"; +- blue { ++ led-blue { + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; +@@ -72,7 +78,7 @@ + + sound { + compatible = "audio-graph-card"; +- label = "STM32MP1-DK"; ++ label = "STM32MP15-DK"; + routing = + "Playback" , "MCLK", + "Capture" , "MCLK", +@@ -80,6 +86,25 @@ + dais = <&sai2a_port &sai2b_port &i2s2_port>; + status = "okay"; + }; ++ ++ usb_phy_tuning: usb-phy-tuning { ++ st,hs-dc-level = <2>; ++ st,fs-rftime-tuning; ++ st,hs-rftime-reduction; ++ st,hs-current-trim = <15>; ++ st,hs-impedance-trim = <1>; ++ st,squelch-level = <3>; ++ st,hs-rx-offset = <2>; ++ st,no-lsfs-sc; ++ }; ++ ++ vin: vin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vin"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; + }; + + &adc { +@@ -116,10 +141,6 @@ + status = "okay"; + }; + +-&dts { +- status = "okay"; +-}; +- + &cpu0{ + cpu-supply = <&vddcore>; + }; +@@ -128,6 +149,22 @@ + cpu-supply = <&vddcore>; + }; + ++&crc1 { ++ status = "okay"; ++}; ++ ++&dma1 { ++ sram = <&dma_pool>; ++}; ++ ++&dma2 { ++ sram = <&dma_pool>; ++}; ++ ++&dts { ++ status = "okay"; ++}; ++ + ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; +@@ -136,6 +173,8 @@ + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; ++ nvmem-cells = <ðernet_mac_address>; ++ nvmem-cell-names = "mac-address"; + + mdio0 { + #address-cells = <1>; +@@ -151,6 +190,10 @@ + contiguous-area = <&gpu_reserved>; + }; + ++&hash1 { ++ status = "okay"; ++}; ++ + &i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; +@@ -238,37 +281,52 @@ + /delete-property/dmas; + /delete-property/dma-names; + +- typec: stusb1600@28 { ++ stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; +- + status = "okay"; ++ vdd-supply = <&vin>; + +- typec_con: connector { ++ connector { + compatible = "usb-c-connector"; + label = "USB-C"; +- power-role = "sink"; +- power-opmode = "default"; ++ power-role = "dual"; ++ typec-power-opmode = "default"; ++ ++ port { ++ con_usbotg_hs_ep: endpoint { ++ remote-endpoint = <&usbotg_hs_ep>; ++ }; ++ }; + }; + }; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; +- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; ++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; ++ buck1-supply = <&vin>; ++ buck2-supply = <&vin>; ++ buck3-supply = <&vin>; ++ buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; ++ ldo2-supply = <&vin>; + ldo3-supply = <&vdd_ddr>; ++ ldo4-supply = <&vin>; ++ ldo5-supply = <&vin>; + ldo6-supply = <&v3v3>; ++ vref_ddr-supply = <&vin>; ++ boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + +@@ -357,23 +415,24 @@ + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; ++ regulator-over-current-protection; + }; + +- bst_out: boost { ++ bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; +- }; ++ }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; +- }; ++ }; + +- vbus_sw: pwr_sw2 { ++ vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; +- }; ++ }; + }; + + onkey { +@@ -391,6 +450,19 @@ + }; + }; + ++&i2c5 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c5_pins_a>; ++ pinctrl-1 = <&i2c5_sleep_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ clock-frequency = <400000>; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; ++}; ++ + &i2s2 { + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; +@@ -438,6 +510,7 @@ + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; ++ wakeup-source; + status = "okay"; + }; + +@@ -465,8 +538,6 @@ + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { +@@ -524,6 +595,27 @@ + status = "disabled"; + }; + ++&spi4 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spi4_pins_b>; ++ pinctrl-1 = <&spi4_sleep_pins_b>; ++ status = "disabled"; ++}; ++ ++&spi5 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spi5_pins_a>; ++ pinctrl-1 = <&spi5_sleep_pins_a>; ++ status = "disabled"; ++}; ++ ++&sram { ++ dma_pool: dma_pool@0 { ++ reg = <0x50000 0x10000>; ++ pool; ++ }; ++}; ++ + &timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; +@@ -610,21 +702,50 @@ + }; + + &uart4 { +- pinctrl-names = "default"; ++ pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; ++ pinctrl-1 = <&uart4_sleep_pins_a>; ++ pinctrl-2 = <&uart4_idle_pins_a>; ++ /delete-property/dmas; ++ /delete-property/dma-names; + status = "okay"; + }; + ++&uart7 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&uart7_pins_c>; ++ pinctrl-1 = <&uart7_sleep_pins_c>; ++ pinctrl-2 = <&uart7_idle_pins_c>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; ++}; ++ ++&usart3 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&usart3_pins_c>; ++ pinctrl-1 = <&usart3_sleep_pins_c>; ++ pinctrl-2 = <&usart3_idle_pins_c>; ++ uart-has-rtscts; ++ status = "disabled"; ++}; ++ + &usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + }; + + &usbotg_hs { +- dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; ++ usb-role-switch; + status = "okay"; ++ ++ port { ++ usbotg_hs_ep: endpoint { ++ remote-endpoint = <&con_usbotg_hs_ep>; ++ }; ++ }; + }; + + &usbphyc { +@@ -633,10 +754,12 @@ + + &usbphyc_port0 { + phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; + }; + + &usbphyc_port1 { + phy-supply = <&vdd_usb>; ++ st,phy-tuning = <&usb_phy_tuning>; + }; + + &vrefbuf { +diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi +new file mode 100644 +index 0000000000..3662f449de +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-edx.dtsi +@@ -0,0 +1,413 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved ++ * Author: Ludovic Barre for STMicroelectronics. ++ */ ++ ++#include "stm32mp15-m4-srm.dtsi" ++#include "stm32mp15-m4-srm-pinctrl.dtsi" ++#include ++#include ++ ++/ { ++ memory@c0000000 { ++ device_type = "memory"; ++ reg = <0xC0000000 0x40000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mcuram2: mcuram2@10000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10000000 0x40000>; ++ no-map; ++ }; ++ ++ vdev0vring0: vdev0vring0@10040000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10040000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0vring1: vdev0vring1@10041000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10041000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0buffer: vdev0buffer@10042000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10042000 0x4000>; ++ no-map; ++ }; ++ ++ mcuram: mcuram@30000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x30000000 0x40000>; ++ no-map; ++ }; ++ ++ retram: retram@38000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x38000000 0x10000>; ++ no-map; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ led-blue { ++ label = "heartbeat"; ++ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ }; ++ ++ sd_switch: regulator-sd_switch { ++ compatible = "regulator-gpio"; ++ regulator-name = "sd_switch"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <2900000>; ++ regulator-type = "voltage"; ++ regulator-always-on; ++ ++ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0>; ++ states = <1800000 0x1>, ++ <2900000 0x0>; ++ }; ++ ++ vin: vin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vin"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&adc { ++ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ ++ pinctrl-0 = <&adc1_in6_pins_a>; ++ pinctrl-names = "default"; ++ vdd-supply = <&vdd>; ++ vdda-supply = <&vdda>; ++ vref-supply = <&vdda>; ++ status = "disabled"; ++ adc1: adc@0 { ++ st,adc-channels = <0 1 6>; ++ /* 16.5 ck_cycles sampling time */ ++ st,min-sample-time-nsecs = <400>; ++ status = "okay"; ++ }; ++}; ++ ++&cpu0{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&cpu1{ ++ cpu-supply = <&vddcore>; ++}; ++ ++&crc1 { ++ status = "okay"; ++}; ++ ++&dac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; ++ vref-supply = <&vdda>; ++ status = "disabled"; ++ dac1: dac@1 { ++ status = "okay"; ++ }; ++ dac2: dac@2 { ++ status = "okay"; ++ }; ++}; ++ ++&dma1 { ++ sram = <&dma_pool>; ++}; ++ ++&dma2 { ++ sram = <&dma_pool>; ++}; ++ ++&dts { ++ status = "okay"; ++}; ++ ++&hash1 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c4_pins_a>; ++ pinctrl-1 = <&i2c4_sleep_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ clock-frequency = <400000>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ pmic: stpmic@33 { ++ compatible = "st,stpmic1"; ++ reg = <0x33>; ++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ status = "okay"; ++ regulators { ++ compatible = "st,stpmic1-regulators"; ++ buck1-supply = <&vin>; ++ buck2-supply = <&vin>; ++ buck3-supply = <&vin>; ++ buck4-supply = <&vin>; ++ ldo1-supply = <&v3v3>; ++ ldo2-supply = <&v3v3>; ++ ldo3-supply = <&vdd_ddr>; ++ ldo4-supply = <&vin>; ++ ldo5-supply = <&v3v3>; ++ ldo6-supply = <&v3v3>; ++ vref_ddr-supply = <&vin>; ++ boost-supply = <&vin>; ++ pwr_sw1-supply = <&bst_out>; ++ pwr_sw2-supply = <&bst_out>; ++ ++ vddcore: buck1 { ++ regulator-name = "vddcore"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_ddr: buck2 { ++ regulator-name = "vdd_ddr"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd: buck3 { ++ regulator-name = "vdd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ st,mask-reset; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ v3v3: buck4 { ++ regulator-name = "v3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ regulator-initial-mode = <0>; ++ }; ++ ++ vdda: ldo1 { ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <2900000>; ++ regulator-max-microvolt = <2900000>; ++ interrupts = ; ++ }; ++ ++ v2v8: ldo2 { ++ regulator-name = "v2v8"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ interrupts = ; ++ }; ++ ++ vtt_ddr: ldo3 { ++ regulator-name = "vtt_ddr"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <750000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_usb: ldo4 { ++ regulator-name = "vdd_usb"; ++ interrupts = ; ++ }; ++ ++ vdd_sd: ldo5 { ++ regulator-name = "vdd_sd"; ++ regulator-min-microvolt = <2900000>; ++ regulator-max-microvolt = <2900000>; ++ interrupts = ; ++ regulator-boot-on; ++ }; ++ ++ v1v8: ldo6 { ++ regulator-name = "v1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ interrupts = ; ++ }; ++ ++ vref_ddr: vref_ddr { ++ regulator-name = "vref_ddr"; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ bst_out: boost { ++ regulator-name = "bst_out"; ++ interrupts = ; ++ }; ++ ++ vbus_otg: pwr_sw1 { ++ regulator-name = "vbus_otg"; ++ interrupts = ; ++ }; ++ ++ vbus_sw: pwr_sw2 { ++ regulator-name = "vbus_sw"; ++ interrupts = ; ++ regulator-active-discharge = <1>; ++ }; ++ }; ++ ++ onkey { ++ compatible = "st,stpmic1-onkey"; ++ interrupts = , ; ++ interrupt-names = "onkey-falling", "onkey-rising"; ++ power-off-time-sec = <10>; ++ status = "okay"; ++ }; ++ ++ watchdog { ++ compatible = "st,stpmic1-wdt"; ++ status = "disabled"; ++ }; ++ }; ++}; ++ ++&ipcc { ++ status = "okay"; ++}; ++ ++&iwdg2 { ++ timeout-sec = <32>; ++ status = "okay"; ++}; ++ ++&m4_rproc { ++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, ++ <&vdev0vring1>, <&vdev0buffer>; ++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; ++ mbox-names = "vq0", "vq1", "shutdown"; ++ interrupt-parent = <&exti>; ++ interrupts = <68 1>; ++ wakeup-source; ++ status = "okay"; ++}; ++ ++&pwr_regulators { ++ vdd-supply = <&vdd>; ++ vdd_3v3_usbfs-supply = <&vdd_usb>; ++}; ++ ++&rng1 { ++ status = "okay"; ++}; ++ ++&rtc { ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; ++ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; ++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; ++ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ disable-wp; ++ st,sig-dir; ++ st,neg-edge; ++ st,use-ckin; ++ bus-width = <4>; ++ vmmc-supply = <&vdd_sd>; ++ vqmmc-supply = <&sd_switch>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ st,neg-edge; ++ bus-width = <8>; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&vdd>; ++ mmc-ddr-3_3v; ++ status = "okay"; ++}; ++ ++&sram { ++ dma_pool: dma_pool@0 { ++ reg = <0x50000 0x10000>; ++ pool; ++ }; ++}; ++ ++&timers6 { ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ timer@5 { ++ status = "okay"; ++ }; ++}; ++ ++&uart4 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&uart4_pins_a>; ++ pinctrl-1 = <&uart4_sleep_pins_a>; ++ pinctrl-2 = <&uart4_idle_pins_a>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ vbus-supply = <&vbus_otg>; ++}; ++ ++&usbphyc_port0 { ++ phy-supply = <&vdd_usb>; ++}; ++ ++&usbphyc_port1 { ++ phy-supply = <&vdd_usb>; ++}; +diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi +new file mode 100644 +index 0000000000..47a2c8e5ea +--- /dev/null ++++ b/arch/arm/dts/stm32mp15xx-evx.dtsi +@@ -0,0 +1,686 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved ++ * Author: Ludovic Barre for STMicroelectronics. ++ */ ++ ++#include ++#include ++ ++/ { ++ aliases { ++ ethernet0 = ðernet0; ++ }; ++ ++ clocks { ++ clk_ext_camera: clk-ext-camera { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ joystick { ++ compatible = "gpio-keys"; ++ #size-cells = <0>; ++ pinctrl-0 = <&joystick_pins>; ++ pinctrl-names = "default"; ++ button-0 { ++ label = "JoySel"; ++ linux,code = ; ++ interrupt-parent = <&stmfx_pinctrl>; ++ interrupts = <0 IRQ_TYPE_EDGE_RISING>; ++ }; ++ button-1 { ++ label = "JoyDown"; ++ linux,code = ; ++ interrupt-parent = <&stmfx_pinctrl>; ++ interrupts = <1 IRQ_TYPE_EDGE_RISING>; ++ }; ++ button-2 { ++ label = "JoyLeft"; ++ linux,code = ; ++ interrupt-parent = <&stmfx_pinctrl>; ++ interrupts = <2 IRQ_TYPE_EDGE_RISING>; ++ }; ++ button-3 { ++ label = "JoyRight"; ++ linux,code = ; ++ interrupt-parent = <&stmfx_pinctrl>; ++ interrupts = <3 IRQ_TYPE_EDGE_RISING>; ++ }; ++ button-4 { ++ label = "JoyUp"; ++ linux,code = ; ++ interrupt-parent = <&stmfx_pinctrl>; ++ interrupts = <4 IRQ_TYPE_EDGE_RISING>; ++ }; ++ }; ++ ++ panel_backlight: panel-backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; ++ default-on; ++ status = "okay"; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ status = "okay"; ++ ++ spdif_out_port: port { ++ spdif_out_endpoint: endpoint { ++ remote-endpoint = <&sai4a_endpoint>; ++ }; ++ }; ++ }; ++ ++ spdif_in: spdif-in { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dir"; ++ status = "okay"; ++ ++ spdif_in_port: port { ++ spdif_in_endpoint: endpoint { ++ remote-endpoint = <&spdifrx_endpoint>; ++ }; ++ }; ++ }; ++ ++ sound { ++ compatible = "audio-graph-card"; ++ label = "STM32MP15-EV"; ++ routing = ++ "AIF1CLK" , "MCLK1", ++ "AIF2CLK" , "MCLK1", ++ "IN1LN" , "MICBIAS2", ++ "DMIC2DAT" , "MICBIAS1", ++ "DMIC1DAT" , "MICBIAS1"; ++ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port ++ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>; ++ status = "okay"; ++ }; ++ ++ dmic0: dmic-0 { ++ compatible = "dmic-codec"; ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "dmic0"; ++ status = "okay"; ++ ++ port { ++ dmic0_endpoint: endpoint { ++ remote-endpoint = <&dfsdm_endpoint0>; ++ }; ++ }; ++ }; ++ ++ dmic1: dmic-1 { ++ compatible = "dmic-codec"; ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "dmic1"; ++ status = "okay"; ++ ++ port { ++ dmic1_endpoint: endpoint { ++ remote-endpoint = <&dfsdm_endpoint1>; ++ }; ++ }; ++ }; ++ ++ dmic2: dmic-2 { ++ compatible = "dmic-codec"; ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "dmic2"; ++ status = "okay"; ++ ++ port { ++ dmic2_endpoint: endpoint { ++ remote-endpoint = <&dfsdm_endpoint2>; ++ }; ++ }; ++ }; ++ ++ dmic3: dmic-3 { ++ compatible = "dmic-codec"; ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "dmic3"; ++ status = "okay"; ++ ++ port { ++ dmic3_endpoint: endpoint { ++ remote-endpoint = <&dfsdm_endpoint3>; ++ }; ++ }; ++ }; ++ ++ usb_phy_tuning: usb-phy-tuning { ++ st,hs-dc-level = <2>; ++ st,fs-rftime-tuning; ++ st,hs-rftime-reduction; ++ st,hs-current-trim = <15>; ++ st,hs-impedance-trim = <1>; ++ st,squelch-level = <3>; ++ st,hs-rx-offset = <2>; ++ st,no-lsfs-sc; ++ }; ++}; ++ ++&cec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cec_pins_a>; ++ status = "okay"; ++}; ++ ++&dcmi { ++ status = "okay"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&dcmi_pins_a>; ++ pinctrl-1 = <&dcmi_sleep_pins_a>; ++ ++ port { ++ dcmi_0: endpoint { ++ remote-endpoint = <&ov5640_0>; ++ bus-type = <5>; ++ bus-width = <8>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++}; ++ ++&dfsdm { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&dfsdm_clkout_pins_a ++ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>; ++ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a ++ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>; ++ spi-max-frequency = <2048000>; ++ ++ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; ++ clock-names = "dfsdm", "audio"; ++ status = "okay"; ++ ++ dfsdm0: filter@0 { ++ compatible = "st,stm32-dfsdm-dmic"; ++ st,adc-channels = <3>; ++ st,adc-channel-names = "dmic_u1"; ++ st,adc-channel-types = "SPI_R"; ++ st,adc-channel-clk-src = "CLKOUT"; ++ st,filter-order = <3>; ++ status = "okay"; ++ ++ asoc_pdm0: dfsdm-dai { ++ compatible = "st,stm32h7-dfsdm-dai"; ++ #sound-dai-cells = <0>; ++ io-channels = <&dfsdm0 0>; ++ status = "okay"; ++ ++ dfsdm0_port: port { ++ dfsdm_endpoint0: endpoint { ++ remote-endpoint = <&dmic0_endpoint>; ++ }; ++ }; ++ }; ++ }; ++ ++ dfsdm1: filter@1 { ++ compatible = "st,stm32-dfsdm-dmic"; ++ st,adc-channels = <0>; ++ st,adc-channel-names = "dmic_u2"; ++ st,adc-channel-types = "SPI_F"; ++ st,adc-channel-clk-src = "CLKOUT"; ++ st,filter-order = <3>; ++ st,adc-alt-channel = <1>; ++ status = "okay"; ++ ++ asoc_pdm1: dfsdm-dai { ++ compatible = "st,stm32h7-dfsdm-dai"; ++ #sound-dai-cells = <0>; ++ io-channels = <&dfsdm1 0>; ++ status = "okay"; ++ ++ dfsdm1_port: port { ++ dfsdm_endpoint1: endpoint { ++ remote-endpoint = <&dmic1_endpoint>; ++ }; ++ }; ++ }; ++ }; ++ ++ dfsdm2: filter@2 { ++ compatible = "st,stm32-dfsdm-dmic"; ++ st,adc-channels = <2>; ++ st,adc-channel-names = "dmic_u3"; ++ st,adc-channel-types = "SPI_F"; ++ st,adc-channel-clk-src = "CLKOUT"; ++ st,adc-alt-channel = <1>; ++ st,filter-order = <3>; ++ status = "okay"; ++ ++ asoc_pdm2: dfsdm-dai { ++ compatible = "st,stm32h7-dfsdm-dai"; ++ #sound-dai-cells = <0>; ++ io-channels = <&dfsdm2 0>; ++ status = "okay"; ++ ++ dfsdm2_port: port { ++ dfsdm_endpoint2: endpoint { ++ remote-endpoint = <&dmic2_endpoint>; ++ }; ++ }; ++ }; ++ }; ++ ++ dfsdm3: filter@3 { ++ compatible = "st,stm32-dfsdm-dmic"; ++ st,adc-channels = <1>; ++ st,adc-channel-names = "dmic_u4"; ++ st,adc-channel-types = "SPI_R"; ++ st,adc-channel-clk-src = "CLKOUT"; ++ st,filter-order = <3>; ++ status = "okay"; ++ ++ asoc_pdm3: dfsdm-dai { ++ compatible = "st,stm32h7-dfsdm-dai"; ++ #sound-dai-cells = <0>; ++ io-channels = <&dfsdm3 0>; ++ status = "okay"; ++ ++ dfsdm3_port: port { ++ dfsdm_endpoint3: endpoint { ++ remote-endpoint = <&dmic3_endpoint>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++ðernet0 { ++ status = "okay"; ++ pinctrl-0 = <ðernet0_rgmii_pins_a>; ++ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rgmii-id"; ++ max-speed = <1000>; ++ phy-handle = <&phy0>; ++ nvmem-cells = <ðernet_mac_address>; ++ nvmem-cell-names = "mac-address"; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++}; ++ ++&fmc { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&fmc_pins_a>; ++ pinctrl-1 = <&fmc_sleep_pins_a>; ++ status = "okay"; ++ ++ nand-controller@4,0 { ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ nand-on-flash-bbt; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ }; ++}; ++ ++&hdp { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>; ++ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>; ++ status = "disabled"; ++ ++ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) | ++ STM32_HDP(6, HDP6_GPOVAL_6) | ++ STM32_HDP(7, HDP7_GPOVAL_7))>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ pinctrl-1 = <&i2c2_sleep_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ wm8994: wm8994@1b { ++ compatible = "wlf,wm8994"; ++ #sound-dai-cells = <0>; ++ reg = <0x1b>; ++ status = "okay"; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ DBVDD-supply = <&vdd>; ++ SPKVDD1-supply = <&vdd>; ++ SPKVDD2-supply = <&vdd>; ++ AVDD2-supply = <&v1v8>; ++ CPVDD-supply = <&v1v8>; ++ ++ wlf,ldoena-always-driven; ++ ++ clocks = <&sai2a>; ++ clock-names = "MCLK1"; ++ ++ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wm8994_tx_port: port@0 { ++ reg = <0>; ++ wm8994_tx_endpoint: endpoint { ++ remote-endpoint = <&sai2a_endpoint>; ++ }; ++ }; ++ ++ wm8994_rx_port: port@1 { ++ reg = <1>; ++ wm8994_rx_endpoint: endpoint { ++ remote-endpoint = <&sai2b_endpoint>; ++ }; ++ }; ++ }; ++ }; ++ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&clk_ext_camera>; ++ clock-names = "xclk"; ++ DOVDD-supply = <&v2v8>; ++ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; ++ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; ++ rotation = <180>; ++ status = "okay"; ++ ++ port { ++ ov5640_0: endpoint { ++ remote-endpoint = <&dcmi_0>; ++ bus-width = <8>; ++ data-shift = <2>; /* lines 9:2 are used */ ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ pclk-max-frequency = <77000000>; ++ }; ++ }; ++ }; ++ ++ stmfx: stmfx@42 { ++ compatible = "st,stmfx-0300"; ++ reg = <0x42>; ++ interrupts = <8 IRQ_TYPE_EDGE_RISING>; ++ interrupt-parent = <&gpioi>; ++ vdd-supply = <&v3v3>; ++ ++ stmfx_pinctrl: pinctrl { ++ compatible = "st,stmfx-0300-pinctrl"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ gpio-ranges = <&stmfx_pinctrl 0 0 24>; ++ ++ goodix_pins: goodix { ++ pins = "gpio14"; ++ bias-pull-down; ++ }; ++ ++ joystick_pins: joystick-pins { ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; ++ bias-pull-down; ++ }; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ pmic: stpmic@33 { ++ regulators { ++ v1v8: ldo6 { ++ regulator-enable-ramp-delay = <300000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c5 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c5_pins_a>; ++ pinctrl-1 = <&i2c5_sleep_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "okay"; ++}; ++ ++&m_can1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&m_can1_pins_a>; ++ pinctrl-1 = <&m_can1_sleep_pins_a>; ++ status = "okay"; ++}; ++ ++&qspi { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; ++ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; ++ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash0: mx66l51235l@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-rx-bus-width = <4>; ++ spi-max-frequency = <108000000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ flash1: mx66l51235l@1 { ++ compatible = "jedec,spi-nor"; ++ reg = <1>; ++ spi-rx-bus-width = <4>; ++ spi-max-frequency = <108000000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; ++ ++&sai2 { ++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>; ++ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>; ++ clock-names = "pclk", "x8k", "x11k"; ++ status = "okay"; ++ ++ sai2a: audio-controller@4400b004 { ++ #clock-cells = <0>; ++ dma-names = "tx"; ++ status = "okay"; ++ ++ sai2a_port: port { ++ sai2a_endpoint: endpoint { ++ remote-endpoint = <&wm8994_tx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <256>; ++ }; ++ }; ++ }; ++ ++ sai2b: audio-controller@4400b024 { ++ dma-names = "rx"; ++ clocks = <&rcc SAI2_K>, <&sai2a>; ++ clock-names = "sai_ck", "MCLK"; ++ status = "okay"; ++ ++ sai2b_port: port { ++ sai2b_endpoint: endpoint { ++ remote-endpoint = <&wm8994_rx_endpoint>; ++ format = "i2s"; ++ mclk-fs = <256>; ++ }; ++ }; ++ }; ++}; ++ ++&sai4 { ++ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>; ++ clock-names = "pclk", "x8k", "x11k"; ++ status = "okay"; ++ ++ sai4a: audio-controller@50027004 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&sai4a_pins_a>; ++ pinctrl-1 = <&sai4a_sleep_pins_a>; ++ dma-names = "tx"; ++ st,iec60958; ++ status = "okay"; ++ ++ sai4a_port: port { ++ sai4a_endpoint: endpoint { ++ remote-endpoint = <&spdif_out_endpoint>; ++ }; ++ }; ++ }; ++}; ++ ++&sdmmc3 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc3_b4_pins_a>; ++ pinctrl-1 = <&sdmmc3_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; ++ broken-cd; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ status = "disabled"; ++}; ++ ++&spdifrx { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spdifrx_pins_a>; ++ pinctrl-1 = <&spdifrx_sleep_pins_a>; ++ status = "okay"; ++ ++ spdifrx_port: port { ++ spdifrx_endpoint: endpoint { ++ remote-endpoint = <&spdif_in_endpoint>; ++ }; ++ }; ++}; ++ ++&spi1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&spi1_pins_a>; ++ pinctrl-1 = <&spi1_sleep_pins_a>; ++ status = "disabled"; ++}; ++ ++&timers2 { ++ /* spare dmas for other usage (un-delete to enable pwm capture) */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; ++ pwm { ++ pinctrl-0 = <&pwm2_pins_a>; ++ pinctrl-1 = <&pwm2_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ }; ++ timer@1 { ++ status = "okay"; ++ }; ++}; ++ ++&timers8 { ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; ++ pwm { ++ pinctrl-0 = <&pwm8_pins_a>; ++ pinctrl-1 = <&pwm8_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ }; ++ timer@7 { ++ status = "okay"; ++ }; ++}; ++ ++&timers12 { ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ status = "disabled"; ++ pwm { ++ pinctrl-0 = <&pwm12_pins_a>; ++ pinctrl-1 = <&pwm12_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ status = "okay"; ++ }; ++ timer@11 { ++ status = "okay"; ++ }; ++}; ++ ++&usart3 { ++ pinctrl-names = "default", "sleep", "idle"; ++ pinctrl-0 = <&usart3_pins_b>; ++ pinctrl-1 = <&usart3_sleep_pins_b>; ++ pinctrl-2 = <&usart3_idle_pins_b>; ++ /* ++ * HW flow control USART3_RTS is optional, and isn't default wired to ++ * the connector. SB23 needs to be soldered in order to use it, and R77 ++ * (ETH_CLK) should be removed. ++ */ ++ uart-has-rtscts; ++ status = "disabled"; ++}; ++ ++&usbh_ehci { ++ phys = <&usbphyc_port0>; ++ status = "okay"; ++}; ++ ++&usbotg_hs { ++ pinctrl-0 = <&usbotg_hs_pins_a>; ++ pinctrl-names = "default"; ++ phys = <&usbphyc_port1 0>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usbphyc { ++ status = "okay"; ++}; ++ ++&usbphyc_port0 { ++ st,phy-tuning = <&usb_phy_tuning>; ++ vbus-supply = <&vbus_sw>; ++}; ++ ++&usbphyc_port1 { ++ st,phy-tuning = <&usb_phy_tuning>; ++}; +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.01-stm32mp-r1-CONFIG.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.01-stm32mp-r1-CONFIG.patch deleted file mode 100644 index 110d82b..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.01-stm32mp-r1-CONFIG.patch +++ /dev/null @@ -1,545 +0,0 @@ -From 5731d9684c509e5d8920ad4b94391fd6aa310323 Mon Sep 17 00:00:00 2001 -From: Romuald JEANNE -Date: Fri, 5 Jun 2020 13:46:04 +0200 -Subject: [PATCH 5/5] ARM v2020.01-stm32mp-r1 CONFIG - ---- - configs/stm32mp15_basic_defconfig | 36 +++++--- - configs/stm32mp15_dhcom_basic_defconfig | 141 ++++++++++++++++++++++++++++++++ - configs/stm32mp15_optee_defconfig | 129 ----------------------------- - configs/stm32mp15_trusted_defconfig | 41 +++++++--- - 4 files changed, 194 insertions(+), 153 deletions(-) - create mode 100644 configs/stm32mp15_dhcom_basic_defconfig - delete mode 100644 configs/stm32mp15_optee_defconfig - -diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig -index 713a7e6..cf28217 100644 ---- a/configs/stm32mp15_basic_defconfig -+++ b/configs/stm32mp15_basic_defconfig -@@ -2,8 +2,12 @@ CONFIG_ARM=y - CONFIG_ARCH_STM32MP=y - CONFIG_SYS_MALLOC_F_LEN=0x3000 - CONFIG_SPL_MMC_SUPPORT=y -+CONFIG_ENV_OFFSET=0x280000 - CONFIG_SPL=y --CONFIG_TARGET_STM32MP1=y -+CONFIG_TARGET_ST_STM32MP15x=y -+CONFIG_CMD_STM32PROG=y -+CONFIG_ENV_SECT_SIZE=0x40000 -+CONFIG_ENV_OFFSET_REDUND=0x2C0000 - CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI_SUPPORT=y - # CONFIG_ARMV7_VIRT is not set -@@ -19,11 +23,13 @@ CONFIG_SPL_POWER_SUPPORT=y - CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 - CONFIG_SYS_PROMPT="STM32MP> " - # CONFIG_CMD_BOOTD is not set -+CONFIG_CMD_DTIMG=y - # CONFIG_CMD_ELF is not set - # CONFIG_CMD_IMI is not set - # CONFIG_CMD_XIMG is not set - # CONFIG_CMD_EXPORTENV is not set - # CONFIG_CMD_IMPORTENV is not set -+CONFIG_CMD_ERASEENV=y - CONFIG_CMD_MEMINFO=y - CONFIG_CMD_MEMTEST=y - CONFIG_CMD_ADC=y -@@ -31,10 +37,8 @@ CONFIG_CMD_CLK=y - CONFIG_CMD_DFU=y - CONFIG_CMD_FUSE=y - CONFIG_CMD_GPIO=y --CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y --CONFIG_CMD_MTD=y - CONFIG_CMD_REMOTEPROC=y - CONFIG_CMD_SPI=y - CONFIG_CMD_USB=y -@@ -52,29 +56,31 @@ CONFIG_CMD_UBI=y - CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" - CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" - CONFIG_ENV_IS_NOWHERE=y --CONFIG_ENV_IS_IN_EXT4=y -+CONFIG_ENV_IS_IN_MMC=y - CONFIG_ENV_IS_IN_SPI_FLASH=y - CONFIG_ENV_IS_IN_UBI=y - CONFIG_SYS_REDUNDAND_ENVIRONMENT=y --CONFIG_ENV_EXT4_INTERFACE="mmc" --CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" --CONFIG_ENV_EXT4_FILE="/uboot.env" --CONFIG_ENV_OFFSET_REDUND=0x2C0000 - CONFIG_ENV_UBI_PART="UBI" - CONFIG_ENV_UBI_VOLUME="uboot_config" - CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_STM32_ADC=y --CONFIG_DFU_MMC=y --CONFIG_DFU_RAM=y --CONFIG_DFU_MTD=y --CONFIG_DFU_VIRT=y -+CONFIG_SET_DFU_ALT_INFO=y - CONFIG_USB_FUNCTION_FASTBOOT=y - CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 - CONFIG_FASTBOOT_BUF_SIZE=0x02000000 - CONFIG_FASTBOOT_USB_DEV=1 - CONFIG_FASTBOOT_FLASH=y - CONFIG_FASTBOOT_FLASH_MMC_DEV=1 -+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y -+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" -+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" -+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y -+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y -+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y -+CONFIG_GPIO_HOG=y - CONFIG_DM_HWSPINLOCK=y - CONFIG_HWSPINLOCK_STM32=y - CONFIG_DM_I2C=y -@@ -88,6 +94,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y - CONFIG_STM32_SDMMC2=y - CONFIG_MTD=y - CONFIG_DM_MTD=y -+CONFIG_SYS_MTDPARTS_RUNTIME=y - CONFIG_MTD_RAW_NAND=y - CONFIG_NAND_STM32_FMC2=y - CONFIG_MTD_SPI_NAND=y -@@ -99,6 +106,7 @@ CONFIG_SPI_FLASH_WINBOND=y - # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set - CONFIG_SPI_FLASH_MTD=y - CONFIG_SPL_SPI_FLASH_MTD=y -+CONFIG_PHY_REALTEK=y - CONFIG_DM_ETH=y - CONFIG_DWC_ETH_QOS=y - CONFIG_PHY=y -@@ -113,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y - CONFIG_DM_REGULATOR_GPIO=y - CONFIG_DM_REGULATOR_STM32_VREFBUF=y - CONFIG_DM_REGULATOR_STPMIC1=y -+CONFIG_STM32MP1_DDR_INTERACTIVE=y - CONFIG_REMOTEPROC_STM32_COPRO=y - CONFIG_DM_RTC=y - CONFIG_RTC_STM32=y -@@ -142,4 +151,7 @@ CONFIG_VIDEO_STM32=y - CONFIG_VIDEO_STM32_DSI=y - CONFIG_VIDEO_STM32_MAX_XRES=1280 - CONFIG_VIDEO_STM32_MAX_YRES=800 -+CONFIG_WDT=y -+CONFIG_WDT_STM32MP=y -+CONFIG_ERRNO_STR=y - CONFIG_FDT_FIXUP_PARTITIONS=y -diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig -new file mode 100644 -index 0000000..ed3504d ---- /dev/null -+++ b/configs/stm32mp15_dhcom_basic_defconfig -@@ -0,0 +1,141 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_STM32MP=y -+CONFIG_SYS_MALLOC_F_LEN=0x3000 -+CONFIG_SPL_MMC_SUPPORT=y -+CONFIG_ENV_SIZE=0x4000 -+CONFIG_SPL=y -+CONFIG_TARGET_DH_STM32MP1_PDK2=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+# CONFIG_ARMV7_VIRT is not set -+CONFIG_SPL_TEXT_BASE=0x2FFC2500 -+CONFIG_DISTRO_DEFAULTS=y -+CONFIG_FIT=y -+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -+CONFIG_SYS_PROMPT="STM32MP> " -+# CONFIG_CMD_BOOTD is not set -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_EXPORTENV is not set -+CONFIG_CMD_EEPROM=y -+CONFIG_CMD_MEMINFO=y -+CONFIG_CMD_MEMTEST=y -+CONFIG_CMD_ADC=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DFU=y -+CONFIG_CMD_FUSE=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_REMOTEPROC=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+CONFIG_CMD_BMP=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_TIME=y -+CONFIG_CMD_TIMER=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+CONFIG_CMD_EXT4_WRITE=y -+CONFIG_CMD_MTDPARTS=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2" -+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" -+CONFIG_ENV_IS_IN_SPI_FLASH=y -+CONFIG_USE_ENV_SPI_BUS=y -+CONFIG_ENV_SPI_BUS=0 -+CONFIG_USE_ENV_SPI_CS=y -+CONFIG_ENV_SPI_CS=0 -+CONFIG_USE_ENV_SPI_MAX_HZ=y -+CONFIG_ENV_SPI_MAX_HZ=10000000 -+CONFIG_USE_ENV_SPI_MODE=y -+CONFIG_ENV_SPI_MODE=0x0 -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_IP_DEFRAG=y -+CONFIG_TFTP_BLOCKSIZE=1536 -+CONFIG_STM32_ADC=y -+CONFIG_SPL_BLOCK_CACHE=y -+CONFIG_DFU_MMC=y -+CONFIG_DFU_RAM=y -+CONFIG_DFU_VIRT=y -+CONFIG_SET_DFU_ALT_INFO=y -+CONFIG_GPIO_HOG=y -+CONFIG_DM_HWSPINLOCK=y -+CONFIG_HWSPINLOCK_STM32=y -+CONFIG_DM_I2C=y -+CONFIG_SYS_I2C_STM32F7=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_DM_MAILBOX=y -+CONFIG_STM32_IPCC=y -+CONFIG_I2C_EEPROM=y -+CONFIG_DM_MMC=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_STM32_SDMMC2=y -+CONFIG_MTD=y -+CONFIG_SYS_MTDPARTS_RUNTIME=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPL_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_PHY=y -+CONFIG_PHY_STM32_USBPHYC=y -+CONFIG_PINCONF=y -+# CONFIG_SPL_PINCTRL_FULL is not set -+CONFIG_PINCTRL_STMFX=y -+CONFIG_DM_PMIC=y -+# CONFIG_SPL_PMIC_CHILDREN is not set -+CONFIG_PMIC_STPMIC1=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_REGULATOR_STM32_VREFBUF=y -+CONFIG_DM_REGULATOR_STPMIC1=y -+CONFIG_REMOTEPROC_STM32_COPRO=y -+CONFIG_DM_RTC=y -+CONFIG_RTC_STM32=y -+CONFIG_SERIAL_RX_BUFFER=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_STM32_QSPI=y -+CONFIG_STM32_SPI=y -+CONFIG_USB=y -+CONFIG_DM_USB=y -+CONFIG_DM_USB_GADGET=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="dh" -+CONFIG_USB_GADGET_VENDOR_NUM=0x0483 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_DM_VIDEO=y -+CONFIG_BACKLIGHT_GPIO=y -+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y -+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y -+CONFIG_VIDEO_STM32=y -+CONFIG_VIDEO_STM32_DSI=y -+CONFIG_VIDEO_STM32_MAX_XRES=1280 -+CONFIG_VIDEO_STM32_MAX_YRES=800 -+CONFIG_LZO=y -+CONFIG_FDT_FIXUP_PARTITIONS=y -diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig -deleted file mode 100644 -index f9161fd..0000000 ---- a/configs/stm32mp15_optee_defconfig -+++ /dev/null -@@ -1,129 +0,0 @@ --CONFIG_ARM=y --CONFIG_ARCH_STM32MP=y --CONFIG_SYS_MALLOC_F_LEN=0x3000 --CONFIG_TARGET_STM32MP1=y --CONFIG_STM32MP1_OPTEE=y --CONFIG_DISTRO_DEFAULTS=y --CONFIG_FIT=y --CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" --CONFIG_SYS_PROMPT="STM32MP> " --# CONFIG_CMD_BOOTD is not set --# CONFIG_CMD_ELF is not set --# CONFIG_CMD_IMI is not set --# CONFIG_CMD_XIMG is not set --# CONFIG_CMD_EXPORTENV is not set --# CONFIG_CMD_IMPORTENV is not set --CONFIG_CMD_MEMINFO=y --CONFIG_CMD_MEMTEST=y --CONFIG_CMD_ADC=y --CONFIG_CMD_CLK=y --CONFIG_CMD_DFU=y --CONFIG_CMD_FUSE=y --CONFIG_CMD_GPIO=y --CONFIG_CMD_GPT=y --CONFIG_CMD_I2C=y --CONFIG_CMD_MMC=y --CONFIG_CMD_MTD=y --CONFIG_CMD_REMOTEPROC=y --CONFIG_CMD_SPI=y --CONFIG_CMD_USB=y --CONFIG_CMD_USB_MASS_STORAGE=y --CONFIG_CMD_BMP=y --CONFIG_CMD_CACHE=y --CONFIG_CMD_TIME=y --CONFIG_CMD_TIMER=y --CONFIG_CMD_PMIC=y --CONFIG_CMD_REGULATOR=y --CONFIG_CMD_EXT4_WRITE=y --CONFIG_CMD_MTDPARTS=y --CONFIG_CMD_UBI=y --CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" --CONFIG_ENV_IS_NOWHERE=y --CONFIG_ENV_IS_IN_EXT4=y --CONFIG_ENV_IS_IN_SPI_FLASH=y --CONFIG_ENV_IS_IN_UBI=y --CONFIG_SYS_REDUNDAND_ENVIRONMENT=y --CONFIG_ENV_EXT4_INTERFACE="mmc" --CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" --CONFIG_ENV_EXT4_FILE="/uboot.env" --CONFIG_ENV_OFFSET_REDUND=0x2C0000 --CONFIG_ENV_UBI_PART="UBI" --CONFIG_ENV_UBI_VOLUME="uboot_config" --CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" --CONFIG_SYS_RELOC_GD_ENV_ADDR=y --CONFIG_STM32_ADC=y --CONFIG_DFU_MMC=y --CONFIG_DFU_RAM=y --CONFIG_DFU_MTD=y --CONFIG_DFU_VIRT=y --CONFIG_USB_FUNCTION_FASTBOOT=y --CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 --CONFIG_FASTBOOT_BUF_SIZE=0x02000000 --CONFIG_FASTBOOT_USB_DEV=1 --CONFIG_FASTBOOT_FLASH=y --CONFIG_FASTBOOT_FLASH_MMC_DEV=1 --CONFIG_DM_HWSPINLOCK=y --CONFIG_HWSPINLOCK_STM32=y --CONFIG_DM_I2C=y --CONFIG_SYS_I2C_STM32F7=y --CONFIG_LED=y --CONFIG_LED_GPIO=y --CONFIG_DM_MAILBOX=y --CONFIG_STM32_IPCC=y --CONFIG_DM_MMC=y --CONFIG_SUPPORT_EMMC_BOOT=y --CONFIG_STM32_SDMMC2=y --CONFIG_MTD=y --CONFIG_DM_MTD=y --CONFIG_MTD_RAW_NAND=y --CONFIG_NAND_STM32_FMC2=y --CONFIG_MTD_SPI_NAND=y --CONFIG_DM_SPI_FLASH=y --CONFIG_SPI_FLASH_MACRONIX=y --CONFIG_SPI_FLASH_SPANSION=y --CONFIG_SPI_FLASH_STMICRO=y --CONFIG_SPI_FLASH_WINBOND=y --# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set --CONFIG_SPI_FLASH_MTD=y --CONFIG_DM_ETH=y --CONFIG_DWC_ETH_QOS=y --CONFIG_PHY=y --CONFIG_PHY_STM32_USBPHYC=y --CONFIG_PINCONF=y --CONFIG_PINCTRL_STMFX=y --CONFIG_DM_PMIC=y --CONFIG_PMIC_STPMIC1=y --CONFIG_DM_REGULATOR_FIXED=y --CONFIG_DM_REGULATOR_GPIO=y --CONFIG_DM_REGULATOR_STM32_VREFBUF=y --CONFIG_DM_REGULATOR_STPMIC1=y --CONFIG_REMOTEPROC_STM32_COPRO=y --CONFIG_DM_RTC=y --CONFIG_RTC_STM32=y --CONFIG_SERIAL_RX_BUFFER=y --CONFIG_SPI=y --CONFIG_DM_SPI=y --CONFIG_STM32_QSPI=y --CONFIG_STM32_SPI=y --CONFIG_USB=y --CONFIG_DM_USB=y --CONFIG_DM_USB_GADGET=y --CONFIG_USB_EHCI_HCD=y --CONFIG_USB_EHCI_GENERIC=y --CONFIG_USB_GADGET=y --CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" --CONFIG_USB_GADGET_VENDOR_NUM=0x0483 --CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 --CONFIG_USB_GADGET_DWC2_OTG=y --CONFIG_DM_VIDEO=y --CONFIG_BACKLIGHT_GPIO=y --CONFIG_VIDEO_BPP8=y --CONFIG_VIDEO_BPP16=y --CONFIG_VIDEO_BPP32=y --CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y --CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y --CONFIG_VIDEO_STM32=y --CONFIG_VIDEO_STM32_DSI=y --CONFIG_VIDEO_STM32_MAX_XRES=1280 --CONFIG_VIDEO_STM32_MAX_YRES=800 --CONFIG_FDT_FIXUP_PARTITIONS=y -diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig -index a5ea528..e248b7d 100644 ---- a/configs/stm32mp15_trusted_defconfig -+++ b/configs/stm32mp15_trusted_defconfig -@@ -1,17 +1,23 @@ - CONFIG_ARM=y - CONFIG_ARCH_STM32MP=y - CONFIG_SYS_MALLOC_F_LEN=0x3000 --CONFIG_TARGET_STM32MP1=y -+CONFIG_ENV_OFFSET=0x280000 -+CONFIG_TARGET_ST_STM32MP15x=y -+CONFIG_CMD_STM32PROG=y -+CONFIG_ENV_SECT_SIZE=0x40000 -+CONFIG_ENV_OFFSET_REDUND=0x2C0000 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_FIT=y - CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" - CONFIG_SYS_PROMPT="STM32MP> " - # CONFIG_CMD_BOOTD is not set -+CONFIG_CMD_DTIMG=y - # CONFIG_CMD_ELF is not set - # CONFIG_CMD_IMI is not set - # CONFIG_CMD_XIMG is not set - # CONFIG_CMD_EXPORTENV is not set - # CONFIG_CMD_IMPORTENV is not set -+CONFIG_CMD_ERASEENV=y - CONFIG_CMD_MEMINFO=y - CONFIG_CMD_MEMTEST=y - CONFIG_CMD_ADC=y -@@ -19,10 +25,8 @@ CONFIG_CMD_CLK=y - CONFIG_CMD_DFU=y - CONFIG_CMD_FUSE=y - CONFIG_CMD_GPIO=y --CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y --CONFIG_CMD_MTD=y - CONFIG_CMD_REMOTEPROC=y - CONFIG_CMD_SPI=y - CONFIG_CMD_USB=y -@@ -38,29 +42,32 @@ CONFIG_CMD_MTDPARTS=y - CONFIG_CMD_UBI=y - CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" - CONFIG_ENV_IS_NOWHERE=y --CONFIG_ENV_IS_IN_EXT4=y -+CONFIG_ENV_IS_IN_MMC=y - CONFIG_ENV_IS_IN_SPI_FLASH=y - CONFIG_ENV_IS_IN_UBI=y - CONFIG_SYS_REDUNDAND_ENVIRONMENT=y --CONFIG_ENV_EXT4_INTERFACE="mmc" --CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" --CONFIG_ENV_EXT4_FILE="/uboot.env" --CONFIG_ENV_OFFSET_REDUND=0x2C0000 - CONFIG_ENV_UBI_PART="UBI" - CONFIG_ENV_UBI_VOLUME="uboot_config" - CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_STM32_ADC=y --CONFIG_DFU_MMC=y --CONFIG_DFU_RAM=y --CONFIG_DFU_MTD=y --CONFIG_DFU_VIRT=y -+CONFIG_CLK_SCMI=y -+CONFIG_SET_DFU_ALT_INFO=y - CONFIG_USB_FUNCTION_FASTBOOT=y - CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 - CONFIG_FASTBOOT_BUF_SIZE=0x02000000 - CONFIG_FASTBOOT_USB_DEV=1 - CONFIG_FASTBOOT_FLASH=y - CONFIG_FASTBOOT_FLASH_MMC_DEV=1 -+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y -+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" -+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" -+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y -+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y -+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y -+CONFIG_GPIO_HOG=y - CONFIG_DM_HWSPINLOCK=y - CONFIG_HWSPINLOCK_STM32=y - CONFIG_DM_I2C=y -@@ -69,11 +76,13 @@ CONFIG_LED=y - CONFIG_LED_GPIO=y - CONFIG_DM_MAILBOX=y - CONFIG_STM32_IPCC=y -+CONFIG_ARM_SMC_MAILBOX=y - CONFIG_DM_MMC=y - CONFIG_SUPPORT_EMMC_BOOT=y - CONFIG_STM32_SDMMC2=y - CONFIG_MTD=y - CONFIG_DM_MTD=y -+CONFIG_SYS_MTDPARTS_RUNTIME=y - CONFIG_MTD_RAW_NAND=y - CONFIG_NAND_STM32_FMC2=y - CONFIG_MTD_SPI_NAND=y -@@ -84,6 +93,7 @@ CONFIG_SPI_FLASH_STMICRO=y - CONFIG_SPI_FLASH_WINBOND=y - # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set - CONFIG_SPI_FLASH_MTD=y -+CONFIG_PHY_REALTEK=y - CONFIG_DM_ETH=y - CONFIG_DWC_ETH_QOS=y - CONFIG_PHY=y -@@ -97,6 +107,7 @@ CONFIG_DM_REGULATOR_GPIO=y - CONFIG_DM_REGULATOR_STM32_VREFBUF=y - CONFIG_DM_REGULATOR_STPMIC1=y - CONFIG_REMOTEPROC_STM32_COPRO=y -+CONFIG_RESET_SCMI=y - CONFIG_DM_RTC=y - CONFIG_RTC_STM32=y - CONFIG_SERIAL_RX_BUFFER=y -@@ -104,6 +115,9 @@ CONFIG_SPI=y - CONFIG_DM_SPI=y - CONFIG_STM32_QSPI=y - CONFIG_STM32_SPI=y -+CONFIG_TEE=y -+CONFIG_OPTEE=y -+# CONFIG_OPTEE_TA_AVB is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -@@ -125,4 +139,7 @@ CONFIG_VIDEO_STM32=y - CONFIG_VIDEO_STM32_DSI=y - CONFIG_VIDEO_STM32_MAX_XRES=1280 - CONFIG_VIDEO_STM32_MAX_YRES=800 -+CONFIG_WDT=y -+CONFIG_WDT_STM32MP=y -+CONFIG_ERRNO_STR=y - CONFIG_FDT_FIXUP_PARTITIONS=y --- -2.7.4 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.10-stm32mp-r1-CONFIG.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.10-stm32mp-r1-CONFIG.patch new file mode 100644 index 0000000..b115b74 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-stm32mp/0005-ARM-v2020.10-stm32mp-r1-CONFIG.patch @@ -0,0 +1,165 @@ +From b5b052fb24a4d593ad0e3facfd365e1d33e4083f Mon Sep 17 00:00:00 2001 +From: Romuald JEANNE +Date: Tue, 16 Mar 2021 08:14:57 +0100 +Subject: [PATCH 5/5] ARM v2020.10-stm32mp-r1 CONFIG + +--- + configs/sandbox_defconfig | 4 ++++ + configs/stm32mp15_basic_defconfig | 6 ++++-- + configs/stm32mp15_dhcom_basic_defconfig | 1 + + configs/stm32mp15_dhcor_basic_defconfig | 1 + + configs/stm32mp15_trusted_defconfig | 12 ++++++++---- + 5 files changed, 18 insertions(+), 6 deletions(-) + +diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig +index 6e9f029cc9..a2ebb3c971 100644 +--- a/configs/sandbox_defconfig ++++ b/configs/sandbox_defconfig +@@ -122,6 +122,7 @@ CONFIG_BUTTON=y + CONFIG_BUTTON_GPIO=y + CONFIG_CLK=y + CONFIG_CLK_COMPOSITE_CCF=y ++CONFIG_CLK_SCMI=y + CONFIG_SANDBOX_CLK_CCF=y + CONFIG_CPU=y + CONFIG_DM_DEMO=y +@@ -132,6 +133,8 @@ CONFIG_BOARD_SANDBOX=y + CONFIG_DMA=y + CONFIG_DMA_CHANNELS=y + CONFIG_SANDBOX_DMA=y ++CONFIG_FIRMWARE=y ++CONFIG_SCMI_FIRMWARE=y + CONFIG_GPIO_HOG=y + CONFIG_DM_GPIO_LOOKUP_LABEL=y + CONFIG_PM8916_GPIO=y +@@ -217,6 +220,7 @@ CONFIG_REMOTEPROC_SANDBOX=y + CONFIG_DM_RESET=y + CONFIG_SANDBOX_RESET=y + CONFIG_RESET_SYSCON=y ++CONFIG_RESET_SCMI=y + CONFIG_DM_RNG=y + CONFIG_DM_RTC=y + CONFIG_RTC_RV8803=y +diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig +index a8c4112dbe..c08d06474b 100644 +--- a/configs/stm32mp15_basic_defconfig ++++ b/configs/stm32mp15_basic_defconfig +@@ -18,6 +18,7 @@ CONFIG_SPL_SPI_SUPPORT=y + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y ++CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +@@ -31,8 +32,6 @@ CONFIG_SPL_SPI_FLASH_MTD=y + CONFIG_SYS_PROMPT="STM32MP> " + CONFIG_CMD_ADTIMG=y + # CONFIG_CMD_ELF is not set +-# CONFIG_CMD_EXPORTENV is not set +-# CONFIG_CMD_IMPORTENV is not set + CONFIG_CMD_ERASEENV=y + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y +@@ -69,6 +68,7 @@ CONFIG_ENV_UBI_PART="UBI" + CONFIG_ENV_UBI_VOLUME="uboot_config" + CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=-1 + # CONFIG_SPL_ENV_IS_NOWHERE is not set + # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set + CONFIG_STM32_ADC=y +@@ -121,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y + CONFIG_DM_REGULATOR_STM32_VREFBUF=y + CONFIG_DM_REGULATOR_STPMIC1=y ++CONFIG_STM32MP1_DDR_INTERACTIVE=y + CONFIG_REMOTEPROC_STM32_COPRO=y + CONFIG_DM_RNG=y + CONFIG_RNG_STM32MP1=y +@@ -153,3 +154,4 @@ CONFIG_WDT=y + CONFIG_WDT_STM32MP=y + CONFIG_ERRNO_STR=y + CONFIG_FDT_FIXUP_PARTITIONS=y ++CONFIG_LMB_RESERVED_REGIONS=16 +diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig +index 7668fd01cd..c0282fa9fb 100644 +--- a/configs/stm32mp15_dhcom_basic_defconfig ++++ b/configs/stm32mp15_dhcom_basic_defconfig +@@ -17,6 +17,7 @@ CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its" + # CONFIG_USE_SPL_FIT_GENERATOR is not set ++CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y +diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig +index aa384517c3..ba1be446e7 100644 +--- a/configs/stm32mp15_dhcor_basic_defconfig ++++ b/configs/stm32mp15_dhcor_basic_defconfig +@@ -17,6 +17,7 @@ CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its" + # CONFIG_USE_SPL_FIT_GENERATOR is not set ++CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y +diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig +index 0792884a9d..5b4cfc4ca3 100644 +--- a/configs/stm32mp15_trusted_defconfig ++++ b/configs/stm32mp15_trusted_defconfig +@@ -2,21 +2,20 @@ CONFIG_ARM=y + CONFIG_ARCH_STM32MP=y + CONFIG_TFABOOT=y + CONFIG_SYS_MALLOC_F_LEN=0x3000 +-CONFIG_ENV_OFFSET=0x280000 ++CONFIG_ENV_OFFSET=0x480000 + CONFIG_ENV_SECT_SIZE=0x40000 + CONFIG_TARGET_ST_STM32MP15x=y + CONFIG_CMD_STM32PROG=y + CONFIG_TYPEC_STUSB160X=y +-CONFIG_ENV_OFFSET_REDUND=0x2C0000 ++CONFIG_ENV_OFFSET_REDUND=0x4C0000 + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y ++CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_SYS_PROMPT="STM32MP> " + CONFIG_CMD_ADTIMG=y + # CONFIG_CMD_ELF is not set +-# CONFIG_CMD_EXPORTENV is not set +-# CONFIG_CMD_IMPORTENV is not set + CONFIG_CMD_ERASEENV=y + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y +@@ -51,7 +50,9 @@ CONFIG_ENV_UBI_PART="UBI" + CONFIG_ENV_UBI_VOLUME="uboot_config" + CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=-1 + CONFIG_STM32_ADC=y ++CONFIG_CLK_SCMI=y + CONFIG_SET_DFU_ALT_INFO=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +@@ -99,7 +100,9 @@ CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y + CONFIG_DM_REGULATOR_STM32_VREFBUF=y + CONFIG_DM_REGULATOR_STPMIC1=y ++CONFIG_REMOTEPROC_OPTEE=y + CONFIG_REMOTEPROC_STM32_COPRO=y ++CONFIG_RESET_SCMI=y + CONFIG_DM_RNG=y + CONFIG_RNG_STM32MP1=y + CONFIG_DM_RTC=y +@@ -134,3 +137,4 @@ CONFIG_WDT=y + CONFIG_WDT_STM32MP=y + CONFIG_ERRNO_STR=y + CONFIG_FDT_FIXUP_PARTITIONS=y ++CONFIG_LMB_RESERVED_REGIONS=16 +-- +2.17.1 + diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch deleted file mode 100644 index 5813070..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch +++ /dev/null @@ -1,778 +0,0 @@ -From 1f4593f966441e5ea3477f974eea8043b75c003c Mon Sep 17 00:00:00 2001 -From: Christophe Priouzeau -Date: Tue, 27 Oct 2020 11:47:53 +0100 -Subject: [PATCH 06/10] ARM-v2020.01-stm32mp-r2-DEVICETREE - ---- - arch/arm/dts/stm32mp15-no-scmi.dtsi | 11 ++-- - arch/arm/dts/stm32mp15-pinctrl.dtsi | 8 +-- - arch/arm/dts/stm32mp15-u-boot.dtsi | 57 +++++++++++------ - arch/arm/dts/stm32mp151.dtsi | 81 +++++++++++++++--------- - arch/arm/dts/stm32mp157a-avenger96.dts | 3 + - arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 15 +++++ - arch/arm/dts/stm32mp157a-dk1.dts | 9 --- - arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 14 ++++ - arch/arm/dts/stm32mp157a-ed1.dts | 9 --- - arch/arm/dts/stm32mp157c-dk2.dts | 13 ---- - arch/arm/dts/stm32mp157c-ed1.dts | 9 --- - arch/arm/dts/stm32mp157d-dk1.dts | 9 --- - arch/arm/dts/stm32mp157d-ed1.dts | 9 --- - arch/arm/dts/stm32mp157f-dk2.dts | 14 ---- - arch/arm/dts/stm32mp157f-ed1.dts | 9 --- - arch/arm/dts/stm32mp15xd.dtsi | 2 +- - arch/arm/dts/stm32mp15xx-dkx.dtsi | 2 + - arch/arm/dts/stm32mp15xx-edx.dtsi | 1 - - arch/arm/dts/stm32mp15xx-evx.dtsi | 25 +++++--- - 19 files changed, 147 insertions(+), 153 deletions(-) - -diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi -index 3bb96ab8a2..b58b4b0526 100644 ---- a/arch/arm/dts/stm32mp15-no-scmi.dtsi -+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi -@@ -61,11 +61,15 @@ - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - }; -+ -+ dsi: dsi@5a000000 { -+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; -+ }; - }; - - mlahb { - m4_rproc: m4@10000000 { -- resets = <&rcc MCU_R>; -+ resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; - - m4_system_resources { - m4_cec: cec@40016000 { -@@ -100,10 +104,6 @@ - clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>; - }; - --&dsi { -- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; --}; -- - &gpioz { - clocks = <&rcc GPIOZ>; - }; -@@ -153,5 +153,4 @@ - - &usart1 { - clocks = <&rcc USART1_K>; -- resets = <&rcc USART1_R>; - }; -diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi -index b8e82adeca..9d51384c18 100644 ---- a/arch/arm/dts/stm32mp15-pinctrl.dtsi -+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi -@@ -1225,7 +1225,7 @@ - }; - pins2 { - pinmux = ; /* USART7_RX */ -- bias-disable; -+ bias-pull-up; - }; - }; - -@@ -1235,7 +1235,7 @@ - }; - pins2 { - pinmux = ; /* USART7_RX */ -- bias-disable; -+ bias-pull-up; - }; - }; - -@@ -1329,7 +1329,7 @@ - pins2 { - pinmux = , /* USART3_RX */ - ; /* USART3_CTS_NSS */ -- bias-disable; -+ bias-pull-up; - }; - }; - -@@ -1341,7 +1341,7 @@ - }; - pins2 { - pinmux = ; /* USART3_RX */ -- bias-disable; -+ bias-pull-up; - }; - }; - -diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi -index 823e281906..02f9d836ec 100644 ---- a/arch/arm/dts/stm32mp15-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi -@@ -164,6 +164,38 @@ - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - }; - -+&usart1 { -+ resets = <&scmi0_reset RST_SCMI0_USART1>; -+}; -+ -+&usart2 { -+ resets = <&rcc USART2_R>; -+}; -+ -+&usart3 { -+ resets = <&rcc USART3_R>; -+}; -+ -+&uart4 { -+ resets = <&rcc UART4_R>; -+}; -+ -+&uart5 { -+ resets = <&rcc UART5_R>; -+}; -+ -+&usart6 { -+ resets = <&rcc USART6_R>; -+}; -+ -+&uart7 { -+ resets = <&rcc UART7_R>; -+}; -+ -+&uart8{ -+ resets = <&rcc UART8_R>; -+}; -+ - /* NO MORE USE SCMI SUPPORT for BASIC boot chain */ - #ifndef CONFIG_STM32MP1_TRUSTED - -@@ -172,26 +204,6 @@ - / { - clocks { - u-boot,dm-pre-reloc; -- -- clk_hse: clk-hse { -- u-boot,dm-pre-reloc; -- }; -- -- clk_hsi: clk-hsi { -- u-boot,dm-pre-reloc; -- }; -- -- clk_lse: clk-lse { -- u-boot,dm-pre-reloc; -- }; -- -- clk_lsi: clk-lsi { -- u-boot,dm-pre-reloc; -- }; -- -- clk_csi: clk-csi { -- u-boot,dm-pre-reloc; -- }; - }; - - reboot { -@@ -228,4 +240,9 @@ - u-boot,dm-spl; - }; - }; -+ -+&usart1 { -+ resets = <&rcc USART1_R>; -+}; -+ - #endif /* CONFIG_STM32MP1_TRUSTED */ -diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi -index c516e2ed03..f0211917bb 100644 ---- a/arch/arm/dts/stm32mp151.dtsi -+++ b/arch/arm/dts/stm32mp151.dtsi -@@ -106,12 +106,6 @@ - #clock-cells = <1>; - }; - }; -- -- optee: optee { -- compatible = "linaro,optee-tz"; -- method = "smc"; -- status = "disabled"; -- }; - }; - - psci { -@@ -444,8 +438,11 @@ - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; -+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; -+ power-domains = <&pd_core>; -+ wakeup-source; - status = "disabled"; - - pwm { -@@ -536,7 +533,6 @@ - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; -- resets = <&rcc USART2_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 43 0x400 0x5>, -@@ -550,7 +546,6 @@ - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; -- resets = <&rcc USART3_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 45 0x400 0x5>, -@@ -564,7 +559,6 @@ - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; -- resets = <&rcc UART4_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 63 0x400 0x5>, -@@ -578,7 +572,6 @@ - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; -- resets = <&rcc UART5_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 65 0x400 0x5>, -@@ -701,7 +694,6 @@ - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; -- resets = <&rcc UART7_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 79 0x400 0x5>, -@@ -715,7 +707,6 @@ - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; -- resets = <&rcc UART8_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 81 0x400 0x5>, -@@ -801,7 +792,6 @@ - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; -- resets = <&rcc USART6_R>; - wakeup-source; - power-domains = <&pd_core>; - dmas = <&dmamux1 71 0x400 0x5>, -@@ -1365,8 +1355,11 @@ - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; -+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; -+ power-domains = <&pd_core>; -+ wakeup-source; - status = "disabled"; - - pwm { -@@ -1392,8 +1385,11 @@ - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; -+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; -+ power-domains = <&pd_core>; -+ wakeup-source; - status = "disabled"; - - pwm { -@@ -1412,8 +1408,11 @@ - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; -+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; -+ power-domains = <&pd_core>; -+ wakeup-source; - status = "disabled"; - - pwm { -@@ -1426,8 +1425,11 @@ - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; -+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; -+ power-domains = <&pd_core>; -+ wakeup-source; - status = "disabled"; - - pwm { -@@ -1526,23 +1528,38 @@ - dma-requests = <48>; - }; - -- fmc: nand-controller@58002000 { -- compatible = "st,stm32mp15-fmc2"; -- reg = <0x58002000 0x1000>, -- <0x80000000 0x1000>, -- <0x88010000 0x1000>, -- <0x88020000 0x1000>, -- <0x81000000 0x1000>, -- <0x89010000 0x1000>, -- <0x89020000 0x1000>; -- interrupts = ; -- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>, -- <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>, -- <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>; -- dma-names = "tx", "rx", "ecc"; -+ fmc: memory-controller@58002000 { -+ #address-cells = <2>; -+ #size-cells = <1>; -+ compatible = "st,stm32mp1-fmc2-ebi"; -+ reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; -+ -+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ -+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ -+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ -+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ -+ <4 0 0x80000000 0x10000000>; /* NAND */ -+ -+ nand-controller@4,0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stm32mp1-fmc2-nfc"; -+ reg = <4 0x00000000 0x1000>, -+ <4 0x08010000 0x1000>, -+ <4 0x08020000 0x1000>, -+ <4 0x01000000 0x1000>, -+ <4 0x09010000 0x1000>, -+ <4 0x09020000 0x1000>; -+ interrupts = ; -+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>, -+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>, -+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>; -+ dma-names = "tx", "rx", "ecc"; -+ status = "disabled"; -+ }; - }; - - qspi: spi@58003000 { -@@ -1703,7 +1720,6 @@ - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scmi0_clk CK_SCMI0_USART1>; -- resets = <&scmi0_reset RST_SCMI0_USART1>; - wakeup-source; - power-domains = <&pd_core>; - status = "disabled"; -@@ -1768,6 +1784,9 @@ - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; -+ ethernet_mac_address: mac@e4 { -+ reg = <0xe4 0x6>; -+ }; - }; - - i2c6: i2c@5c009000 { -@@ -1980,9 +1999,9 @@ - reg = <0x10000000 0x40000>, - <0x30000000 0x40000>, - <0x38000000 0x10000>; -- resets = <&scmi0_reset RST_SCMI0_MCU>; -- st,syscfg-holdboot = <&rcc 0x10C 0x1>; -- st,syscfg-tz = <&rcc 0x000 0x1>; -+ resets = <&scmi0_reset RST_SCMI0_MCU>, -+ <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; -+ reset-names = "mcu_rst", "hold_boot"; - st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; - st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>; - st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; -diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts -index 941963ccc2..75efd45179 100644 ---- a/arch/arm/dts/stm32mp157a-avenger96.dts -+++ b/arch/arm/dts/stm32mp157a-avenger96.dts -@@ -92,6 +92,9 @@ - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; -+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <1000>; -+ - phy0: ethernet-phy@7 { - reg = <7>; - }; -diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -index 62d7062885..0edcbe9620 100644 ---- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi -@@ -21,6 +21,7 @@ - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - }; -+ - led { - red { - label = "error"; -@@ -29,6 +30,20 @@ - status = "okay"; - }; - }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+ -+ reserved-memory { -+ optee@de000000 { -+ reg = <0xde000000 0x02000000>; -+ no-map; -+ }; -+ }; - }; - - &adc { -diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts -index baff3f6944..1f265fed2c 100644 ---- a/arch/arm/dts/stm32mp157a-dk1.dts -+++ b/arch/arm/dts/stm32mp157a-dk1.dts -@@ -31,14 +31,5 @@ - reg = <0xda000000 0x4000000>; - no-map; - }; -- -- optee_memory: optee@0xde000000 { -- reg = <0xde000000 0x02000000>; -- no-map; -- }; - }; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi -index 0f163bc566..23affacad0 100644 ---- a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi -+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi -@@ -30,6 +30,20 @@ - status = "okay"; - }; - }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+ -+ reserved-memory { -+ optee@fe000000 { -+ reg = <0xfe000000 0x02000000>; -+ no-map; -+ }; -+ }; - }; - - #ifndef CONFIG_STM32MP1_TRUSTED -diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts -index 5dca956843..e7fad7d394 100644 ---- a/arch/arm/dts/stm32mp157a-ed1.dts -+++ b/arch/arm/dts/stm32mp157a-ed1.dts -@@ -30,11 +30,6 @@ - reg = <0xf6000000 0x8000000>; - no-map; - }; -- -- optee_memory: optee@fe000000 { -- reg = <0xfe000000 0x02000000>; -- no-map; -- }; - }; - }; - -@@ -46,7 +41,3 @@ - contiguous-area = <&gpu_reserved>; - status = "okay"; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts -index a7d5e86a14..ba1d15de2f 100644 ---- a/arch/arm/dts/stm32mp157c-dk2.dts -+++ b/arch/arm/dts/stm32mp157c-dk2.dts -@@ -34,11 +34,6 @@ - reg = <0xda000000 0x4000000>; - no-map; - }; -- -- optee_memory: optee@0xde000000 { -- reg = <0xde000000 0x02000000>; -- no-map; -- }; - }; - - wifi_pwrseq: wifi-pwrseq { -@@ -174,11 +169,3 @@ - vddio-supply = <&v3v3>; - }; - }; -- --&optee_memory { -- status = "okay"; --}; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts -index bf2d7e7b7d..16ddc0e9f8 100644 ---- a/arch/arm/dts/stm32mp157c-ed1.dts -+++ b/arch/arm/dts/stm32mp157c-ed1.dts -@@ -30,11 +30,6 @@ - reg = <0xf6000000 0x8000000>; - no-map; - }; -- -- optee_memory: optee@fe000000 { -- reg = <0xfe000000 0x02000000>; -- no-map; -- }; - }; - }; - -@@ -50,7 +45,3 @@ - contiguous-area = <&gpu_reserved>; - status = "okay"; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts -index c7d65a65e4..aa98012fd3 100644 ---- a/arch/arm/dts/stm32mp157d-dk1.dts -+++ b/arch/arm/dts/stm32mp157d-dk1.dts -@@ -31,14 +31,5 @@ - reg = <0xda000000 0x4000000>; - no-map; - }; -- -- optee_memory: optee@0xde000000 { -- reg = <0xde000000 0x02000000>; -- no-map; -- }; - }; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts -index ee55ac8f33..aaf9adf51c 100644 ---- a/arch/arm/dts/stm32mp157d-ed1.dts -+++ b/arch/arm/dts/stm32mp157d-ed1.dts -@@ -30,11 +30,6 @@ - reg = <0xf6000000 0x8000000>; - no-map; - }; -- -- optee_memory: optee@fe000000 { -- reg = <0xfe000000 0x02000000>; -- no-map; -- }; - }; - }; - -@@ -46,7 +41,3 @@ - contiguous-area = <&gpu_reserved>; - status = "okay"; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts -index b57db3037d..1123d0f3ed 100644 ---- a/arch/arm/dts/stm32mp157f-dk2.dts -+++ b/arch/arm/dts/stm32mp157f-dk2.dts -@@ -34,12 +34,6 @@ - reg = <0xda000000 0x4000000>; - no-map; - }; -- -- optee_memory: optee@0xde000000 { -- reg = <0xde000000 0x02000000>; -- no-map; -- status = "disabled"; -- }; - }; - - wifi_pwrseq: wifi-pwrseq { -@@ -175,11 +169,3 @@ - vddio-supply = <&v3v3>; - }; - }; -- --&optee_memory { -- status = "okay"; --}; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts -index 65380693c8..7ddb96a0ef 100644 ---- a/arch/arm/dts/stm32mp157f-ed1.dts -+++ b/arch/arm/dts/stm32mp157f-ed1.dts -@@ -30,11 +30,6 @@ - reg = <0xf6000000 0x8000000>; - no-map; - }; -- -- optee_memory: optee@0xfe000000 { -- reg = <0xfe000000 0x02000000>; -- no-map; -- }; - }; - }; - -@@ -50,7 +45,3 @@ - contiguous-area = <&gpu_reserved>; - status = "okay"; - }; -- --&optee { -- status = "okay"; --}; -diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi -index faa039ea24..e2f8b1297c 100644 ---- a/arch/arm/dts/stm32mp15xd.dtsi -+++ b/arch/arm/dts/stm32mp15xd.dtsi -@@ -27,7 +27,7 @@ - }; - - cpu_alert: cpu-alert { -- temperature = <950000>; -+ temperature = <95000>; - hysteresis = <10000>; - type = "passive"; - }; -diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi -index 35169385fd..685a82161c 100644 ---- a/arch/arm/dts/stm32mp15xx-dkx.dtsi -+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi -@@ -163,6 +163,8 @@ - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; -+ nvmem-cells = <ðernet_mac_address>; -+ nvmem-cell-names = "mac-address"; - - mdio0 { - #address-cells = <1>; -diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi -index 7ed6b14d77..c67d57cc02 100644 ---- a/arch/arm/dts/stm32mp15xx-edx.dtsi -+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi -@@ -389,7 +389,6 @@ - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; -- pinctrl-3 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi -index 07cb93db93..1a2b49cada 100644 ---- a/arch/arm/dts/stm32mp15xx-evx.dtsi -+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi -@@ -223,11 +223,12 @@ - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-dmic"; -- st,adc-channels = <1>; -+ st,adc-channels = <0>; - st,adc-channel-names = "dmic_u2"; - st,adc-channel-types = "SPI_F"; - st,adc-channel-clk-src = "CLKOUT"; - st,filter-order = <3>; -+ st,adc-alt-channel = <1>; - status = "okay"; - - asoc_pdm1: dfsdm-dai { -@@ -246,10 +247,11 @@ - - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-dmic"; -- st,adc-channels = <3>; -+ st,adc-channels = <2>; - st,adc-channel-names = "dmic_u3"; - st,adc-channel-types = "SPI_F"; - st,adc-channel-clk-src = "CLKOUT"; -+ st,adc-alt-channel = <1>; - st,filter-order = <3>; - status = "okay"; - -@@ -299,6 +301,8 @@ - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; -+ nvmem-cells = <ðernet_mac_address>; -+ nvmem-cell-names = "mac-address"; - - mdio0 { - #address-cells = <1>; -@@ -315,14 +319,16 @@ - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; -- #address-cells = <1>; -- #size-cells = <0>; - -- nand@0 { -- reg = <0>; -- nand-on-flash-bbt; -- #address-cells = <1>; -- #size-cells = <1>; -+ nand-controller@4,0 { -+ status = "okay"; -+ -+ nand@0 { -+ reg = <0>; -+ nand-on-flash-bbt; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; - }; - }; - -@@ -673,6 +679,7 @@ - - &usbphyc_port0 { - st,phy-tuning = <&usb_phy_tuning>; -+ vbus-supply = <&vbus_sw>; - }; - - &usbphyc_port1 { --- -2.17.1 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch deleted file mode 100644 index 1a9d9e5..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch +++ /dev/null @@ -1,529 +0,0 @@ -From 84a856108aaf180a2cfda252a9b952b55062442e Mon Sep 17 00:00:00 2001 -From: Christophe Priouzeau -Date: Tue, 27 Oct 2020 11:48:20 +0100 -Subject: [PATCH 07/10] ARM-v2020.01-stm32mp-r2-MACHINE - ---- - Makefile | 2 +- - arch/arm/Kconfig | 28 ++++++++++ - arch/arm/include/asm/iproc-common/configs.h | 1 - - arch/arm/include/asm/system.h | 11 ++++ - arch/arm/lib/cache-cp15.c | 29 +++++++--- - arch/arm/lib/cache.c | 13 +++-- - arch/arm/mach-stm32mp/Kconfig | 13 +++++ - .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 2 +- - arch/arm/mach-stm32mp/cpu.c | 53 ++++++++++++++++--- - arch/arm/mach-stm32mp/fdt.c | 14 +++-- - .../mach-stm32mp/include/mach/stm32mp1_smc.h | 48 ++++++++++++----- - .../arm/mach-stm32mp/include/mach/sys_proto.h | 2 + - arch/arm/mach-stm32mp/spl.c | 20 +++++++ - 13 files changed, 197 insertions(+), 39 deletions(-) - -diff --git a/Makefile b/Makefile -index 8b390bc5a3..64b0560af5 100644 ---- a/Makefile -+++ b/Makefile -@@ -3,7 +3,7 @@ - VERSION = 2020 - PATCHLEVEL = 01 - SUBLEVEL = --EXTRAVERSION = -stm32mp-r1 -+EXTRAVERSION = -stm32mp-r2 - NAME = - - # *DOCUMENTATION* -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 36c9c2fecd..f04c37c88c 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -329,6 +329,34 @@ config SYS_CACHELINE_SIZE - default 64 if SYS_CACHE_SHIFT_6 - default 32 if SYS_CACHE_SHIFT_5 - -+choice -+ prompt "Select the ARM data write cache policy" -+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ -+ TARGET_BCMNSP || CPU_PXA || RZA1 -+ default SYS_ARM_CACHE_WRITEBACK -+ -+config SYS_ARM_CACHE_WRITEBACK -+ bool "Write-back (WB)" -+ help -+ A write updates the cache only and marks the cache line as dirty. -+ External memory is updated only when the line is evicted or explicitly -+ cleaned. -+ -+config SYS_ARM_CACHE_WRITETHROUGH -+ bool "Write-through (WT)" -+ help -+ A write updates both the cache and the external memory system. -+ This does not mark the cache line as dirty. -+ -+config SYS_ARM_CACHE_WRITEALLOC -+ bool "Write allocation (WA)" -+ help -+ A cache line is allocated on a write miss. This means that executing a -+ store instruction on the processor might cause a burst read to occur. -+ There is a linefill to obtain the data for the cache line, before the -+ write is performed. -+endchoice -+ - config ARCH_CPU_INIT - bool "Enable ARCH_CPU_INIT" - help -diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h -index 96c4f54f4a..4733c0793c 100644 ---- a/arch/arm/include/asm/iproc-common/configs.h -+++ b/arch/arm/include/asm/iproc-common/configs.h -@@ -10,7 +10,6 @@ - - /* Architecture, CPU, chip, etc */ - #define CONFIG_IPROC --#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - - /* Memory Info */ - #define CONFIG_SYS_SDRAM_BASE 0x61000000 -diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h -index a1a5e35ef6..9fd3b321fc 100644 ---- a/arch/arm/include/asm/system.h -+++ b/arch/arm/include/asm/system.h -@@ -447,6 +447,7 @@ static inline void set_dacr(unsigned int val) - - /* options available for data cache on each page */ - enum dcache_option { -+ INVALID_ENTRY = 0, - DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, - DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), - DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), -@@ -468,6 +469,7 @@ enum dcache_option { - - /* options available for data cache on each page */ - enum dcache_option { -+ INVALID_ENTRY = 0, - DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, - DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, - DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, -@@ -477,6 +479,7 @@ enum dcache_option { - #define TTB_SECT_AP (3 << 10) - /* options available for data cache on each page */ - enum dcache_option { -+ INVALID_ENTRY = 0, - DCACHE_OFF = 0x12, - DCACHE_WRITETHROUGH = 0x1a, - DCACHE_WRITEBACK = 0x1e, -@@ -484,6 +487,14 @@ enum dcache_option { - }; - #endif - -+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -+#endif -+ - /* Size of an MMU section */ - enum { - #ifdef CONFIG_ARMV7_LPAE -diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c -index f8d20960da..16067cf8da 100644 ---- a/arch/arm/lib/cache-cp15.c -+++ b/arch/arm/lib/cache-cp15.c -@@ -6,6 +6,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -61,8 +62,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - unsigned long startpt, stoppt; - unsigned long upto, end; - -- end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; -+ /* div by 2 before start + size to avoid phys_addr_t overflow */ -+ end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2) -+ >> (MMU_SECTION_SHIFT - 1); - start = start >> MMU_SECTION_SHIFT; -+ - #ifdef CONFIG_ARMV7_LPAE - debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, - option); -@@ -89,20 +93,29 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - __weak void dram_bank_mmu_setup(int bank) - { - bd_t *bd = gd->bd; -+ struct lmb lmb; - int i; - -+ /* bd->bi_dram is available only after relocation */ -+ if ((gd->flags & GD_FLG_RELOC) == 0) -+ return; -+ -+ /* -+ * don't allow cache on reserved memory tagged 'no-map' in DT -+ * => avoid speculative access to "secure" data -+ */ -+ lmb_init_and_reserve(&lmb, bd, (void *)gd->fdt_blob); -+ - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); - i++) { --#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -- set_section_dcache(i, DCACHE_WRITETHROUGH); --#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -- set_section_dcache(i, DCACHE_WRITEALLOC); --#else -- set_section_dcache(i, DCACHE_WRITEBACK); --#endif -+ if (lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, -+ LMB_NOMAP)) -+ set_section_dcache(i, INVALID_ENTRY); -+ else -+ set_section_dcache(i, DCACHE_DEFAULT_OPTION); - } - } - -diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c -index 007d4ebc49..7f3cfb407c 100644 ---- a/arch/arm/lib/cache.c -+++ b/arch/arm/lib/cache.c -@@ -73,6 +73,15 @@ static unsigned long noncached_start; - static unsigned long noncached_end; - static unsigned long noncached_next; - -+void noncached_set_region(void) -+{ -+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -+ mmu_set_region_dcache_behaviour(noncached_start, -+ noncached_end - noncached_start, -+ DCACHE_OFF); -+#endif -+} -+ - void noncached_init(void) - { - phys_addr_t start, end; -@@ -89,9 +98,7 @@ void noncached_init(void) - noncached_end = end; - noncached_next = start; - --#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -- mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); --#endif -+ noncached_set_region(); - } - - phys_addr_t noncached_alloc(size_t size, size_t align) -diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig -index f9f79437e4..c24717d36d 100644 ---- a/arch/arm/mach-stm32mp/Kconfig -+++ b/arch/arm/mach-stm32mp/Kconfig -@@ -103,6 +103,19 @@ config SYS_TEXT_BASE - config NR_DRAM_BANKS - default 1 - -+config DDR_CACHEABLE_SIZE -+ hex "Size of the DDR marked cacheable in pre-reloc stage" -+ default 0x10000000 if TFABOOT -+ default 0x40000000 -+ help -+ Define the size of the DDR marked as cacheable in U-Boot -+ pre-reloc stage. -+ This option can be useful to avoid speculatif access -+ to secured area of DDR used by TF-A or OP-TEE before U-Boot -+ initialization. -+ The areas marked "no-map" in device tree should be located -+ before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. -+ - config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 - hex "Partition on MMC2 to use to load U-Boot from" - depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION -diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c -index f2f9ed9f36..531df60404 100644 ---- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c -+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c -@@ -560,7 +560,7 @@ static int init_device(struct stm32prog_data *data, - #ifdef CONFIG_MMC - case STM32PROG_MMC: - mmc = find_mmc_device(dev->dev_id); -- if (mmc_init(mmc)) { -+ if (!mmc || mmc_init(mmc)) { - stm32prog_err("mmc device %d not found", dev->dev_id); - return -ENODEV; - } -diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c -index 305534f2ba..aee0f2bf81 100644 ---- a/arch/arm/mach-stm32mp/cpu.c -+++ b/arch/arm/mach-stm32mp/cpu.c -@@ -76,6 +76,12 @@ - #define PKG_SHIFT 27 - #define PKG_MASK GENMASK(2, 0) - -+/* -+ * early TLB into the .data section so that it not get cleared -+ * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) -+ */ -+u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); -+ - #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) - #ifndef CONFIG_STM32MP1_TRUSTED - static void security_init(void) -@@ -142,17 +148,17 @@ static void security_init(void) - /* - * Debug init - */ --static void dbgmcu_init(void) -+void dbgmcu_init(void) - { -- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); -- - /* - * Freeze IWDG2 if Cortex-A7 is in debug mode - * done in TF-A for TRUSTED boot and - * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE - */ -- if (!CONFIG_IS_ENABLED(STM32MP1_TRUSTED) && bsec_dbgswenable()) -+ if (!IS_ENABLED(CONFIG_STM32MP1_TRUSTED) && bsec_dbgswenable()) { -+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); -+ } - } - #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ - -@@ -192,6 +198,33 @@ u32 get_bootmode(void) - TAMP_BOOT_MODE_SHIFT; - } - -+/* -+ * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage -+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation -+ * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 -+ */ -+static void early_enable_caches(void) -+{ -+ /* I-cache is already enabled in start.S: cpu_init_cp15 */ -+ -+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) -+ return; -+ -+ gd->arch.tlb_size = PGTABLE_SIZE; -+ gd->arch.tlb_addr = (unsigned long)&early_tlb; -+ -+ dcache_enable(); -+ -+ if (IS_ENABLED(CONFIG_SPL_BUILD)) -+ mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE, -+ STM32_SYSRAM_SIZE, -+ DCACHE_DEFAULT_OPTION); -+ else -+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, -+ CONFIG_DDR_CACHEABLE_SIZE, -+ DCACHE_DEFAULT_OPTION); -+} -+ - /* - * Early system init - */ -@@ -199,11 +232,12 @@ int arch_cpu_init(void) - { - u32 boot_mode; - -+ early_enable_caches(); -+ - /* early armv7 timer init: needed for polling */ - timer_init(); - - #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -- dbgmcu_init(); - #ifndef CONFIG_STM32MP1_TRUSTED - security_init(); - update_bootmode(); -@@ -231,7 +265,14 @@ int arch_cpu_init(void) - - void enable_caches(void) - { -- /* Enable D-cache. I-cache is already enabled in start.S */ -+ /* I-cache is already enabled in start.S: icache_enable() not needed */ -+ -+ /* deactivate the data cache, early enabled in arch_cpu_init() */ -+ dcache_disable(); -+ /* -+ * update MMU after relocation and enable the data cache -+ * warning: the TLB location udpated in board_f.c::reserve_mmu -+ */ - dcache_enable(); - } - -diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c -index 21b5f09728..8d9a58186d 100644 ---- a/arch/arm/mach-stm32mp/fdt.c -+++ b/arch/arm/mach-stm32mp/fdt.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause - /* -- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved -+ * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved - */ - - #include -@@ -223,19 +223,23 @@ static void stm32_fdt_disable_optee(void *blob) - { - int off, node; - -+ /* Delete "optee" firmware node */ - off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); - if (off >= 0 && fdtdec_get_is_enabled(blob, off)) -- fdt_status_disabled(blob, off); -+ fdt_del_node(blob, off); - -- /* Disabled "optee@..." reserved-memory node */ -+ /* Delete "optee@..." reserved-memory node */ - off = fdt_path_offset(blob, "/reserved-memory/"); - if (off < 0) - return; - for (node = fdt_first_subnode(blob, off); - node >= 0; - node = fdt_next_subnode(blob, node)) { -- if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) -- fdt_status_disabled(blob, node); -+ if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) -+ continue; -+ -+ if (fdt_del_node(blob, node)) -+ printf("Failed to remove optee reserved-memory node\n"); - } - } - -diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -index dea5b4a6b4..d72747ca31 100644 ---- a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -+++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h -@@ -8,27 +8,53 @@ - - #include - -+/* SMC service generic return codes */ -+#define STM32_SMC_OK 0x00000000U -+#define STM32_SMC_NOT_SUPPORTED 0xFFFFFFFFU -+#define STM32_SMC_FAILED 0xFFFFFFFEU -+#define STM32_SMC_INVALID_PARAMS 0xFFFFFFFDU -+ - /* -- * SMC function IDs for STM32 Service queries -+ * SMC function IDs for STM32 Service queries. - * STM32 SMC services use the space between 0x82000000 and 0x8200FFFF - * like this is defined in SMC calling Convention by ARM -- * for SiP (silicon Partner) -- * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html -+ * for SiP (silicon Partner). -+ * https://developer.arm.com/docs/den0028/latest - */ --#define STM32_SMC_VERSION 0x82000000 - - /* Secure Service access from Non-secure */ --#define STM32_SMC_RCC 0x82001000 -+ -+/* -+ * SMC function STM32_SMC_PWR. -+ * -+ * Argument a0: (input) SMCC ID. -+ * (output) Status return code. -+ * Argument a1: (input) Service ID (STM32_SMC_REG_xxx). -+ * Argument a2: (input) Register offset or physical address. -+ * (output) Register read value, if applicable. -+ * Argument a3: (input) Register target value if applicable. -+ */ - #define STM32_SMC_PWR 0x82001001 --#define STM32_SMC_RTC 0x82001002 -+ -+/* -+ * SMC functions STM32_SMC_BSEC. -+ * -+ * Argument a0: (input) SMCC ID. -+ * (output) Status return code. -+ * Argument a1: (input) Service ID (STM32_SMC_READ_xxx/_PROG_xxx/_WRITE_xxx). -+ * (output) OTP read value, if applicable. -+ * Argument a2: (input) OTP index. -+ * Argument a3: (input) OTP value if applicable. -+ */ - #define STM32_SMC_BSEC 0x82001003 - --/* Register access service use for RCC/RTC/PWR */ -+/* Service ID for STM32_SMC_PWR */ -+#define STM32_SMC_REG_READ 0x0 - #define STM32_SMC_REG_WRITE 0x1 - #define STM32_SMC_REG_SET 0x2 - #define STM32_SMC_REG_CLEAR 0x3 - --/* Service for BSEC */ -+/* Service ID for STM32_SMC_BSEC */ - #define STM32_SMC_READ_SHADOW 0x01 - #define STM32_SMC_PROG_OTP 0x02 - #define STM32_SMC_WRITE_SHADOW 0x03 -@@ -37,12 +63,6 @@ - #define STM32_SMC_WRITE_ALL 0x06 - #define STM32_SMC_WRLOCK_OTP 0x07 - --/* SMC error codes */ --#define STM32_SMC_OK 0x0 --#define STM32_SMC_NOT_SUPPORTED -1 --#define STM32_SMC_FAILED -2 --#define STM32_SMC_INVALID_PARAMS -3 -- - #define stm32_smc_exec(svc, op, data1, data2) \ - stm32_smc(svc, op, data1, data2, NULL) - -diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h -index b6ad3c67ae..c5cab9f21b 100644 ---- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h -+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h -@@ -52,3 +52,5 @@ int setup_mac_address(void); - /* board power management : configure vddcore according OPP */ - void board_vddcore_init(u32 voltage_mv); - int board_vddcore_set(void); -+ -+void dbgmcu_init(void); -diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c -index f4b4c3bd82..41f3fd4b7c 100644 ---- a/arch/arm/mach-stm32mp/spl.c -+++ b/arch/arm/mach-stm32mp/spl.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -123,4 +124,23 @@ void board_init_f(ulong dummy) - printf("DRAM init failed: %d\n", ret); - hang(); - } -+ -+ /* -+ * activate cache on DDR only when DDR is fully initialized -+ * to avoid speculative access and issue in get_ram_size() -+ */ -+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) -+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE, -+ CONFIG_DDR_CACHEABLE_SIZE, -+ DCACHE_DEFAULT_OPTION); -+} -+ -+void spl_board_prepare_for_boot(void) -+{ -+ dcache_disable(); -+} -+ -+void spl_board_prepare_for_boot_linux(void) -+{ -+ dcache_disable(); - } --- -2.17.1 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.01-stm32mp-r2-BOARD.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.01-stm32mp-r2-BOARD.patch deleted file mode 100644 index d1780ce..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.01-stm32mp-r2-BOARD.patch +++ /dev/null @@ -1,247 +0,0 @@ -From c4ead8e3640dd3d0810bff2cbd4b6c14c2139a04 Mon Sep 17 00:00:00 2001 -From: Christophe Priouzeau -Date: Tue, 27 Oct 2020 11:48:28 +0100 -Subject: [PATCH 08/10] ARM-v2020.01-stm32mp-r2-BOARD - ---- - board/st/stm32mp1/spl.c | 4 ++ - board/st/stm32mp1/stm32mp1.c | 136 +++++++++++++++++++++++------------ - 2 files changed, 95 insertions(+), 45 deletions(-) - -diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c -index e65ff288ea..058d47e0e7 100644 ---- a/board/st/stm32mp1/spl.c -+++ b/board/st/stm32mp1/spl.c -@@ -12,9 +12,13 @@ - #include - #include - #include -+#include - - void spl_board_init(void) - { -+ /* init DBGMU */ -+ dbgmcu_init(); -+ - /* Keep vdd on during the reset cycle */ - #if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT) - struct udevice *dev; -diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c -index 617d05d209..6dad00600e 100644 ---- a/board/st/stm32mp1/stm32mp1.c -+++ b/board/st/stm32mp1/stm32mp1.c -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -118,7 +119,7 @@ int checkboard(void) - const char *fdt_compat; - int fdt_compat_len; - -- if (CONFIG_IS_ENABLED(STM32MP1_TRUSTED)) -+ if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) - mode = "trusted"; - else - mode = "basic"; -@@ -362,38 +363,14 @@ static void __maybe_unused led_error_blink(u32 nb_blink) - } - - #ifdef CONFIG_ADC --static int board_check_usb_power(void) -+ -+static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV) - { - struct ofnode_phandle_args adc_args; - struct udevice *adc; -- ofnode node; - unsigned int raw; -- int max_uV = 0; -- int min_uV = USB_START_HIGH_THRESHOLD_UV; -- int ret, uV, adc_count; -- u32 nb_blink; -- u8 i; -- node = ofnode_path("/config"); -- if (!ofnode_valid(node)) { -- debug("%s: no /config node?\n", __func__); -- return -ENOENT; -- } -- -- /* -- * Retrieve the ADC channels devices and get measurement -- * for each of them -- */ -- adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", -- "#io-channel-cells"); -- if (adc_count < 0) { -- if (adc_count == -ENOENT) -- return 0; -- -- pr_err("%s: can't find adc channel (%d)\n", __func__, -- adc_count); -- -- return adc_count; -- } -+ int ret, uV; -+ int i; - - for (i = 0; i < adc_count; i++) { - if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd", -@@ -422,10 +399,10 @@ static int board_check_usb_power(void) - } - /* Convert to uV */ - if (!adc_raw_to_uV(adc, raw, &uV)) { -- if (uV > max_uV) -- max_uV = uV; -- if (uV < min_uV) -- min_uV = uV; -+ if (uV > *max_uV) -+ *max_uV = uV; -+ if (uV < *min_uV) -+ *min_uV = uV; - pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__, - adc->name, adc_args.args[0], raw, uV); - } else { -@@ -433,19 +410,62 @@ static int board_check_usb_power(void) - __func__, adc->name, adc_args.args[0]); - } - } -+ return 0; -+} -+ -+static int board_check_usb_power(void) -+{ -+ ofnode node; -+ int max_uV = 0; -+ int min_uV = USB_START_HIGH_THRESHOLD_UV; -+ int adc_count, ret; -+ u32 nb_blink; -+ u8 i; -+ node = ofnode_path("/config"); -+ if (!ofnode_valid(node)) { -+ debug("%s: no /config node?\n", __func__); -+ return -ENOENT; -+ } - - /* -- * If highest value is inside 1.23 Volts and 2.10 Volts, that means -- * board is plugged on an USB-C 3A power supply and boot process can -- * continue. -+ * Retrieve the ADC channels devices and get measurement -+ * for each of them - */ -- if (max_uV > USB_START_LOW_THRESHOLD_UV && -- max_uV <= USB_START_HIGH_THRESHOLD_UV && -- min_uV <= USB_LOW_THRESHOLD_UV) -- return 0; -+ adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", -+ "#io-channel-cells"); -+ if (adc_count < 0) { -+ if (adc_count == -ENOENT) -+ return 0; - -- pr_err("****************************************************\n"); -+ pr_err("%s: can't find adc channel (%d)\n", __func__, -+ adc_count); -+ -+ return adc_count; -+ } -+ -+ /* perform maximum of 2 ADC measurement to detect power supply current */ -+ for (i = 0; i < 2; i++) { -+ ret = adc_measurement(node, adc_count, &min_uV, &max_uV); -+ if (ret) -+ return ret; -+ -+ /* -+ * If highest value is inside 1.23 Volts and 2.10 Volts, that means -+ * board is plugged on an USB-C 3A power supply and boot process can -+ * continue. -+ */ -+ if (max_uV > USB_START_LOW_THRESHOLD_UV && -+ max_uV <= USB_START_HIGH_THRESHOLD_UV && -+ min_uV <= USB_LOW_THRESHOLD_UV) -+ return 0; -+ -+ if (i == 0) { -+ pr_debug("Previous ADC measurements was not the one expected, retry in 20ms\n"); -+ mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */ -+ } -+ } - -+ pr_err("****************************************************\n"); - /* - * If highest and lowest value are either both below - * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that -@@ -737,7 +757,7 @@ int board_init(void) - - int board_late_init(void) - { -- char *boot_device; -+ char *boot_device, *boot_instance; - #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - const void *fdt_compat; - int fdt_compat_len; -@@ -770,7 +790,7 @@ int board_late_init(void) - if (!ret) - ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), - &otp, sizeof(otp)); -- if (!ret && otp) { -+ if (ret > 0 && otp) { - snprintf(buf, sizeof(buf), "0x%04x", otp >> 16); - env_set("board_id", buf); - -@@ -791,6 +811,25 @@ int board_late_init(void) - (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))) - env_set("bootdelay", "0"); - -+ /* define dynamic variables for FASTBOOT and ANDROID bootargs*/ -+ if (CONFIG_IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC) && -+ boot_device && !strcmp(boot_device, "mmc")) { -+ boot_instance = env_get("boot_instance"); -+ env_set("fastboot.boot_instance", boot_instance); -+ } -+ if (CONFIG_IS_ENABLED(OPTEE) && -+ tee_find_device(NULL, NULL, NULL, NULL)) { -+ if (CONFIG_IS_ENABLED(CONFIG_CMD_DTIMG)) -+ env_set("android_bootargs", "androidboot.optee=true"); -+ if (CONFIG_IS_ENABLED(FASTBOOT)) -+ env_set("fastboot.boot_mode", "optee"); -+ } else { -+ if (CONFIG_IS_ENABLED(CONFIG_CMD_DTIMG)) -+ env_set("android_bootargs", ""); -+ if (CONFIG_IS_ENABLED(FASTBOOT)) -+ env_set("fastboot.boot_mode", "trusted"); -+ } -+ - return 0; - } - -@@ -939,12 +978,19 @@ int mmc_get_env_dev(void) - int ft_board_setup(void *blob, bd_t *bd) - { - #ifdef CONFIG_FDT_FIXUP_PARTITIONS -- struct node_info nodes[] = { -+ static const struct node_info nodes[] = { - { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, - { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND}, - { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, -+ { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, - }; -- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -+ char *boot_device; -+ -+ /* Check the boot-source and don't update MTD for serial or usb boot */ -+ boot_device = env_get("boot_device"); -+ if (!boot_device || -+ (strcmp(boot_device, "serial") && strcmp(boot_device, "usb"))) -+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - #endif - - return 0; --- -2.17.1 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch deleted file mode 100644 index effa6db..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch +++ /dev/null @@ -1,4006 +0,0 @@ -From ba1e2d25f9d6e43e9aec9b95895b63ce3150f056 Mon Sep 17 00:00:00 2001 -From: Christophe Priouzeau -Date: Tue, 27 Oct 2020 11:48:55 +0100 -Subject: [PATCH 09/10] ARM-v2020.01-stm32mp-r2-MISC-DRIVERS - ---- - cmd/cache.c | 5 + - common/image-fdt.c | 38 +- - .../phy/phy-stm32-usbphyc.txt | 1 + - drivers/dfu/dfu_mtd.c | 4 +- - drivers/i2c/stm32f7_i2c.c | 74 +- - drivers/memory/Kconfig | 9 + - drivers/memory/Makefile | 1 + - drivers/memory/stm32-fmc2-ebi.c | 1056 +++++++++++++++++ - drivers/mtd/nand/raw/stm32_fmc2_nand.c | 499 ++++---- - drivers/net/dwc_eth_qos.c | 18 +- - drivers/phy/phy-stm32-usbphyc.c | 33 +- - drivers/ram/stm32mp1/stm32mp1_tests.c | 69 +- - drivers/remoteproc/Kconfig | 8 + - drivers/remoteproc/Makefile | 1 + - drivers/remoteproc/rproc-optee.c | 218 ++++ - drivers/remoteproc/stm32_copro.c | 235 ++-- - drivers/reset/stm32-reset.c | 17 +- - drivers/usb/gadget/dwc2_udc_otg.c | 59 +- - drivers/usb/gadget/dwc2_udc_otg_regs.h | 2 + - include/configs/grpeach.h | 1 - - include/configs/pxa-common.h | 2 - - include/configs/stm32mp1.h | 12 +- - include/dt-bindings/reset/stm32mp1-resets.h | 2 + - include/fdtdec.h | 5 +- - include/lmb.h | 21 + - include/rproc_optee.h | 127 ++ - include/usb/dwc2_udc.h | 1 + - lib/fdtdec.c | 10 +- - lib/lmb.c | 62 +- - lib/optee/optee.c | 9 +- - scripts/config_whitelist.txt | 1 - - 31 files changed, 2147 insertions(+), 453 deletions(-) - create mode 100644 drivers/memory/stm32-fmc2-ebi.c - create mode 100644 drivers/remoteproc/rproc-optee.c - create mode 100644 include/rproc_optee.h - -diff --git a/cmd/cache.c b/cmd/cache.c -index 27dcec0931..7678615dd8 100644 ---- a/cmd/cache.c -+++ b/cmd/cache.c -@@ -20,6 +20,10 @@ void __weak invalidate_icache_all(void) - puts("No arch specific invalidate_icache_all available!\n"); - } - -+__weak void noncached_set_region(void) -+{ -+} -+ - static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) - { - switch (argc) { -@@ -64,6 +68,7 @@ static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) - break; - case 1: - dcache_enable(); -+ noncached_set_region(); - break; - case 2: - flush_dcache_all(); -diff --git a/common/image-fdt.c b/common/image-fdt.c -index 48388488d9..8b861c70a2 100644 ---- a/common/image-fdt.c -+++ b/common/image-fdt.c -@@ -71,18 +71,20 @@ static const image_header_t *image_get_fdt(ulong fdt_addr) - #endif - - static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, -- uint64_t size) -+ uint64_t size, enum lmb_flags flags) - { - long ret; - -- ret = lmb_reserve(lmb, addr, size); -+ ret = lmb_reserve_flags(lmb, addr, size, flags); - if (ret >= 0) { -- debug(" reserving fdt memory region: addr=%llx size=%llx\n", -- (unsigned long long)addr, (unsigned long long)size); -+ debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", -+ (unsigned long long)addr, -+ (unsigned long long)size, flags); - } else { - puts("ERROR: reserving fdt memory region failed "); -- printf("(addr=%llx size=%llx)\n", -- (unsigned long long)addr, (unsigned long long)size); -+ printf("(addr=%llx size=%llx flags=%x)\n", -+ (unsigned long long)addr, -+ (unsigned long long)size, flags); - } - } - -@@ -102,6 +104,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) - int i, total, ret; - int nodeoffset, subnode; - struct fdt_resource res; -+ enum lmb_flags flags; - - if (fdt_check_header(fdt_blob) != 0) - return; -@@ -111,7 +114,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) - for (i = 0; i < total; i++) { - if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) - continue; -- boot_fdt_reserve_region(lmb, addr, size); -+ boot_fdt_reserve_region(lmb, addr, size, LMB_NONE); - } - - /* process reserved-memory */ -@@ -123,9 +126,13 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) - ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, - &res); - if (!ret) { -+ flags = LMB_NONE; -+ if (fdtdec_get_bool(fdt_blob, subnode, -+ "no-map")) -+ flags = LMB_NOMAP; - addr = res.start; - size = res.end - res.start + 1; -- boot_fdt_reserve_region(lmb, addr, size); -+ boot_fdt_reserve_region(lmb, addr, size, flags); - } - - subnode = fdt_next_subnode(fdt_blob, subnode); -@@ -543,6 +550,14 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, - printf("ERROR: arch-specific fdt fixup failed\n"); - goto err; - } -+ -+ fdt_ret = optee_copy_fdt_nodes(gd->fdt_blob, blob); -+ if (fdt_ret) { -+ printf("ERROR: transfer of optee nodes to new fdt failed: %s\n", -+ fdt_strerror(fdt_ret)); -+ goto err; -+ } -+ - /* Update ethernet nodes */ - fdt_fixup_ethernet(blob); - if (IMAGE_OF_BOARD_SETUP) { -@@ -562,13 +577,6 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, - } - } - -- fdt_ret = optee_copy_fdt_nodes(gd->fdt_blob, blob); -- if (fdt_ret) { -- printf("ERROR: transfer of optee nodes to new fdt failed: %s\n", -- fdt_strerror(fdt_ret)); -- goto err; -- } -- - /* Delete the old LMB reservation */ - if (lmb) - lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob, -diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -index 156229b2ed..3953489e3a 100644 ---- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -+++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt -@@ -48,6 +48,7 @@ Required properties: - - Optional properties: - - st,phy-tuning : phandle to the usb phy tuning node, see Phy tuning node below -+- vbus-supply: phandle to the regulator providing 5V vbus to the USB connector - - Phy tuning node - =============== -diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c -index 9528a7b4ee..7bc8f8a603 100644 ---- a/drivers/dfu/dfu_mtd.c -+++ b/drivers/dfu/dfu_mtd.c -@@ -189,7 +189,7 @@ static int dfu_flush_medium_mtd(struct dfu_entity *dfu) - int ret; - - /* in case of ubi partition, erase rest of the partition */ -- if (dfu->data.nand.ubi) { -+ if (dfu->data.mtd.ubi) { - struct erase_info erase_op = {}; - - erase_op.mtd = dfu->data.mtd.info; -@@ -227,7 +227,7 @@ static unsigned int dfu_polltimeout_mtd(struct dfu_entity *dfu) - * ubi partition, as sectors which are not used need - * to be erased - */ -- if (dfu->data.nand.ubi) -+ if (dfu->data.mtd.ubi) - return DFU_MANIFEST_POLL_TIMEOUT; - - return DFU_DEFAULT_POLL_TIMEOUT; -diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c -index 7321f80017..d68b7f4807 100644 ---- a/drivers/i2c/stm32f7_i2c.c -+++ b/drivers/i2c/stm32f7_i2c.c -@@ -7,7 +7,9 @@ - #include - #include - #include -+#include - #include -+#include - - #include - #include -@@ -151,6 +153,7 @@ struct stm32_i2c_spec { - * @fall_time: Fall time (ns) - * @dnf: Digital filter coefficient (0-16) - * @analog_filter: Analog filter delay (On/Off) -+ * @fmp_clr_offset: Fast Mode Plus clear register offset from set register - */ - struct stm32_i2c_setup { - u32 speed_freq; -@@ -159,6 +162,7 @@ struct stm32_i2c_setup { - u32 fall_time; - u8 dnf; - bool analog_filter; -+ u32 fmp_clr_offset; - }; - - /** -@@ -178,11 +182,26 @@ struct stm32_i2c_timings { - u8 scll; - }; - -+/** -+ * struct stm32_i2c_priv - private data of the controller -+ * @regs: I2C registers address -+ * @clk: hw i2c clock -+ * @setup: I2C timing setup parameters -+ * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ -+ * @regmap: holds SYSCFG phandle for Fast Mode Plus bit -+ * @regmap_sreg: register address for setting Fast Mode Plus bits -+ * @regmap_creg: register address for clearing Fast Mode Plus bits -+ * @regmap_mask: mask for Fast Mode Plus bits -+ */ - struct stm32_i2c_priv { - struct stm32_i2c_regs *regs; - struct clk clk; - struct stm32_i2c_setup *setup; - u32 speed; -+ struct regmap *regmap; -+ u32 regmap_sreg; -+ u32 regmap_creg; -+ u32 regmap_mask; - }; - - static const struct stm32_i2c_spec i2c_specs[] = { -@@ -234,6 +253,14 @@ static const struct stm32_i2c_setup stm32f7_setup = { - .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, - }; - -+static const struct stm32_i2c_setup stm32mp15_setup = { -+ .rise_time = STM32_I2C_RISE_TIME_DEFAULT, -+ .fall_time = STM32_I2C_FALL_TIME_DEFAULT, -+ .dnf = STM32_I2C_DNF_DEFAULT, -+ .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, -+ .fmp_clr_offset = 0x40, -+}; -+ - static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) - { - struct stm32_i2c_regs *regs = i2c_priv->regs; -@@ -758,6 +785,29 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, - return 0; - } - -+static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv) -+{ -+ int ret; -+ bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE; -+ -+ /* Optional */ -+ if (IS_ERR_OR_NULL(i2c_priv->regmap)) -+ return 0; -+ -+ if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg) -+ ret = regmap_update_bits(i2c_priv->regmap, -+ i2c_priv->regmap_sreg, -+ i2c_priv->regmap_mask, -+ enable ? i2c_priv->regmap_mask : 0); -+ else -+ ret = regmap_write(i2c_priv->regmap, -+ enable ? i2c_priv->regmap_sreg : -+ i2c_priv->regmap_creg, -+ i2c_priv->regmap_mask); -+ -+ return ret; -+} -+ - static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) - { - struct stm32_i2c_regs *regs = i2c_priv->regs; -@@ -772,6 +822,11 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) - /* Disable I2C */ - clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); - -+ /* Setup Fast mode plus if necessary */ -+ ret = stm32_i2c_write_fm_plus_bits(i2c_priv); -+ if (ret) -+ return ret; -+ - /* Timing settings */ - timing |= STM32_I2C_TIMINGR_PRESC(t.presc); - timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); -@@ -847,6 +902,7 @@ static int stm32_ofdata_to_platdata(struct udevice *dev) - { - struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); - u32 rise_time, fall_time; -+ int ret; - - i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); - if (!i2c_priv->setup) -@@ -860,6 +916,22 @@ static int stm32_ofdata_to_platdata(struct udevice *dev) - if (fall_time) - i2c_priv->setup->fall_time = fall_time; - -+ /* Optional */ -+ i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev, -+ "st,syscfg-fmp"); -+ if (!IS_ERR(i2c_priv->regmap)) { -+ u32 fmp[3]; -+ -+ ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3); -+ if (ret) -+ return ret; -+ -+ i2c_priv->regmap_sreg = fmp[1]; -+ i2c_priv->regmap_creg = fmp[1] + -+ i2c_priv->setup->fmp_clr_offset; -+ i2c_priv->regmap_mask = fmp[2]; -+ } -+ - return 0; - } - -@@ -870,7 +942,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { - - static const struct udevice_id stm32_i2c_of_match[] = { - { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, -- { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32f7_setup }, -+ { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup }, - {} - }; - -diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig -index 4fbb5aa217..7271892763 100644 ---- a/drivers/memory/Kconfig -+++ b/drivers/memory/Kconfig -@@ -4,6 +4,15 @@ - - menu "Memory Controller drivers" - -+config STM32_FMC2_EBI -+ bool "Support for FMC2 External Bus Interface on STM32MP SoCs" -+ depends on ARCH_STM32MP -+ help -+ Select this option to enable the STM32 FMC2 External Bus Interface -+ controller. This driver configures the transactions with external -+ devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on -+ SOCs containing the FMC2 External Bus Interface. -+ - config TI_AEMIF - tristate "Texas Instruments AEMIF driver" - depends on ARCH_KEYSTONE -diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile -index 238add0879..fec52efb60 100644 ---- a/drivers/memory/Makefile -+++ b/drivers/memory/Makefile -@@ -1,2 +1,3 @@ - -+obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o - obj-$(CONFIG_TI_AEMIF) += ti-aemif.o -diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c -new file mode 100644 -index 0000000000..d887a1e09d ---- /dev/null -+++ b/drivers/memory/stm32-fmc2-ebi.c -@@ -0,0 +1,1056 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -+/* -+ * Copyright (C) STMicroelectronics 2020 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* FMC2 Controller Registers */ -+#define FMC2_BCR1 0x0 -+#define FMC2_BTR1 0x4 -+#define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) -+#define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) -+#define FMC2_PCSCNTR 0x20 -+#define FMC2_BWTR1 0x104 -+#define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) -+ -+/* Register: FMC2_BCR1 */ -+#define FMC2_BCR1_CCLKEN BIT(20) -+#define FMC2_BCR1_FMC2EN BIT(31) -+ -+/* Register: FMC2_BCRx */ -+#define FMC2_BCR_MBKEN BIT(0) -+#define FMC2_BCR_MUXEN BIT(1) -+#define FMC2_BCR_MTYP GENMASK(3, 2) -+#define FMC2_BCR_MWID GENMASK(5, 4) -+#define FMC2_BCR_FACCEN BIT(6) -+#define FMC2_BCR_BURSTEN BIT(8) -+#define FMC2_BCR_WAITPOL BIT(9) -+#define FMC2_BCR_WAITCFG BIT(11) -+#define FMC2_BCR_WREN BIT(12) -+#define FMC2_BCR_WAITEN BIT(13) -+#define FMC2_BCR_EXTMOD BIT(14) -+#define FMC2_BCR_ASYNCWAIT BIT(15) -+#define FMC2_BCR_CPSIZE GENMASK(18, 16) -+#define FMC2_BCR_CBURSTRW BIT(19) -+#define FMC2_BCR_NBLSET GENMASK(23, 22) -+ -+/* Register: FMC2_BTRx/FMC2_BWTRx */ -+#define FMC2_BXTR_ADDSET GENMASK(3, 0) -+#define FMC2_BXTR_ADDHLD GENMASK(7, 4) -+#define FMC2_BXTR_DATAST GENMASK(15, 8) -+#define FMC2_BXTR_BUSTURN GENMASK(19, 16) -+#define FMC2_BTR_CLKDIV GENMASK(23, 20) -+#define FMC2_BTR_DATLAT GENMASK(27, 24) -+#define FMC2_BXTR_ACCMOD GENMASK(29, 28) -+#define FMC2_BXTR_DATAHLD GENMASK(31, 30) -+ -+/* Register: FMC2_PCSCNTR */ -+#define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) -+#define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) -+ -+#define FMC2_MAX_EBI_CE 4 -+#define FMC2_MAX_BANKS 5 -+ -+#define FMC2_BCR_CPSIZE_0 0x0 -+#define FMC2_BCR_CPSIZE_128 0x1 -+#define FMC2_BCR_CPSIZE_256 0x2 -+#define FMC2_BCR_CPSIZE_512 0x3 -+#define FMC2_BCR_CPSIZE_1024 0x4 -+ -+#define FMC2_BCR_MWID_8 0x0 -+#define FMC2_BCR_MWID_16 0x1 -+ -+#define FMC2_BCR_MTYP_SRAM 0x0 -+#define FMC2_BCR_MTYP_PSRAM 0x1 -+#define FMC2_BCR_MTYP_NOR 0x2 -+ -+#define FMC2_BXTR_EXTMOD_A 0x0 -+#define FMC2_BXTR_EXTMOD_B 0x1 -+#define FMC2_BXTR_EXTMOD_C 0x2 -+#define FMC2_BXTR_EXTMOD_D 0x3 -+ -+#define FMC2_BCR_NBLSET_MAX 0x3 -+#define FMC2_BXTR_ADDSET_MAX 0xf -+#define FMC2_BXTR_ADDHLD_MAX 0xf -+#define FMC2_BXTR_DATAST_MAX 0xff -+#define FMC2_BXTR_BUSTURN_MAX 0xf -+#define FMC2_BXTR_DATAHLD_MAX 0x3 -+#define FMC2_BTR_CLKDIV_MAX 0xf -+#define FMC2_BTR_DATLAT_MAX 0xf -+#define FMC2_PCSCNTR_CSCOUNT_MAX 0xff -+ -+#define FMC2_NSEC_PER_SEC 1000000000L -+ -+enum stm32_fmc2_ebi_bank { -+ FMC2_EBI1 = 0, -+ FMC2_EBI2, -+ FMC2_EBI3, -+ FMC2_EBI4, -+ FMC2_NAND -+}; -+ -+enum stm32_fmc2_ebi_register_type { -+ FMC2_REG_BCR = 1, -+ FMC2_REG_BTR, -+ FMC2_REG_BWTR, -+ FMC2_REG_PCSCNTR -+}; -+ -+enum stm32_fmc2_ebi_transaction_type { -+ FMC2_ASYNC_MODE_1_SRAM = 0, -+ FMC2_ASYNC_MODE_1_PSRAM, -+ FMC2_ASYNC_MODE_A_SRAM, -+ FMC2_ASYNC_MODE_A_PSRAM, -+ FMC2_ASYNC_MODE_2_NOR, -+ FMC2_ASYNC_MODE_B_NOR, -+ FMC2_ASYNC_MODE_C_NOR, -+ FMC2_ASYNC_MODE_D_NOR, -+ FMC2_SYNC_READ_SYNC_WRITE_PSRAM, -+ FMC2_SYNC_READ_ASYNC_WRITE_PSRAM, -+ FMC2_SYNC_READ_SYNC_WRITE_NOR, -+ FMC2_SYNC_READ_ASYNC_WRITE_NOR -+}; -+ -+enum stm32_fmc2_ebi_buswidth { -+ FMC2_BUSWIDTH_8 = 8, -+ FMC2_BUSWIDTH_16 = 16 -+}; -+ -+enum stm32_fmc2_ebi_cpsize { -+ FMC2_CPSIZE_0 = 0, -+ FMC2_CPSIZE_128 = 128, -+ FMC2_CPSIZE_256 = 256, -+ FMC2_CPSIZE_512 = 512, -+ FMC2_CPSIZE_1024 = 1024 -+}; -+ -+struct stm32_fmc2_ebi { -+ struct clk clk; -+ fdt_addr_t io_base; -+ u8 bank_assigned; -+}; -+ -+/* -+ * struct stm32_fmc2_prop - STM32 FMC2 EBI property -+ * @name: the device tree binding name of the property -+ * @bprop: indicate that it is a boolean property -+ * @mprop: indicate that it is a mandatory property -+ * @reg_type: the register that have to be modified -+ * @reg_mask: the bit that have to be modified in the selected register -+ * in case of it is a boolean property -+ * @reset_val: the default value that have to be set in case the property -+ * has not been defined in the device tree -+ * @check: this callback ckecks that the property is compliant with the -+ * transaction type selected -+ * @calculate: this callback is called to calculate for exemple a timing -+ * set in nanoseconds in the device tree in clock cycles or in -+ * clock period -+ * @set: this callback applies the values in the registers -+ */ -+struct stm32_fmc2_prop { -+ const char *name; -+ bool bprop; -+ bool mprop; -+ int reg_type; -+ u32 reg_mask; -+ u32 reset_val; -+ int (*check)(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, int cs); -+ u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup); -+ int (*set)(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup); -+}; -+ -+static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ -+ if (bcr & FMC2_BCR_MTYP) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ -+ if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ -+ if (bcr & FMC2_BCR_BURSTEN) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ -+ if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); -+ -+ if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ u32 bxtr = prop->reg_type == FMC2_REG_BWTR ? -+ readl(ebi->io_base + FMC2_BWTR(cs)) : -+ readl(ebi->io_base + FMC2_BTR(cs)); -+ u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); -+ -+ if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) && -+ ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr; -+ -+ if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ if (cs) -+ return -EINVAL; -+ -+ return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); -+} -+ -+static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi, -+ int cs, u32 setup) -+{ -+ unsigned long hclk = clk_get_rate(&ebi->clk); -+ unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); -+ -+ return DIV_ROUND_UP(setup * 1000, hclkp); -+} -+ -+static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, -+ int cs, u32 setup) -+{ -+ u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); -+ u32 bcr = readl(ebi->io_base + FMC2_BCR1); -+ u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ? -+ readl(ebi->io_base + FMC2_BTR1) : -+ readl(ebi->io_base + FMC2_BTR(cs)); -+ u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; -+ -+ return DIV_ROUND_UP(nb_clk_cycles, clk_period); -+} -+ -+static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) -+{ -+ switch (reg_type) { -+ case FMC2_REG_BCR: -+ *reg = FMC2_BCR(cs); -+ break; -+ case FMC2_REG_BTR: -+ *reg = FMC2_BTR(cs); -+ break; -+ case FMC2_REG_BWTR: -+ *reg = FMC2_BWTR(cs); -+ break; -+ case FMC2_REG_PCSCNTR: -+ *reg = FMC2_PCSCNTR; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 reg; -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ clrsetbits_le32(ebi->io_base + reg, prop->reg_mask, -+ setup ? prop->reg_mask : 0); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 bcr_mask, bcr = FMC2_BCR_WREN; -+ u32 btr_mask, btr = 0; -+ u32 bwtr_mask, bwtr = 0; -+ -+ bwtr_mask = FMC2_BXTR_ACCMOD; -+ btr_mask = FMC2_BXTR_ACCMOD; -+ bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN | -+ FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN | -+ FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW; -+ -+ switch (setup) { -+ case FMC2_ASYNC_MODE_1_SRAM: -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); -+ /* -+ * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ break; -+ case FMC2_ASYNC_MODE_1_PSRAM: -+ /* -+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); -+ break; -+ case FMC2_ASYNC_MODE_A_SRAM: -+ /* -+ * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); -+ bcr |= FMC2_BCR_EXTMOD; -+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); -+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); -+ break; -+ case FMC2_ASYNC_MODE_A_PSRAM: -+ /* -+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); -+ bcr |= FMC2_BCR_EXTMOD; -+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); -+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); -+ break; -+ case FMC2_ASYNC_MODE_2_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN; -+ break; -+ case FMC2_ASYNC_MODE_B_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; -+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); -+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); -+ break; -+ case FMC2_ASYNC_MODE_C_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; -+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); -+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); -+ break; -+ case FMC2_ASYNC_MODE_D_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, -+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; -+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); -+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); -+ break; -+ case FMC2_SYNC_READ_SYNC_WRITE_PSRAM: -+ /* -+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); -+ bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; -+ break; -+ case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM: -+ /* -+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); -+ bcr |= FMC2_BCR_BURSTEN; -+ break; -+ case FMC2_SYNC_READ_SYNC_WRITE_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; -+ break; -+ case FMC2_SYNC_READ_ASYNC_WRITE_NOR: -+ /* -+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, -+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 -+ */ -+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); -+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN; -+ break; -+ default: -+ /* Type of transaction not supported */ -+ return -EINVAL; -+ } -+ -+ if (bcr & FMC2_BCR_EXTMOD) -+ clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs), -+ bwtr_mask, bwtr); -+ clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr); -+ clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val; -+ -+ switch (setup) { -+ case FMC2_BUSWIDTH_8: -+ val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8); -+ break; -+ case FMC2_BUSWIDTH_16: -+ val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16); -+ break; -+ default: -+ /* Buswidth not supported */ -+ return -EINVAL; -+ } -+ -+ clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val; -+ -+ switch (setup) { -+ case FMC2_CPSIZE_0: -+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0); -+ break; -+ case FMC2_CPSIZE_128: -+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128); -+ break; -+ case FMC2_CPSIZE_256: -+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256); -+ break; -+ case FMC2_CPSIZE_512: -+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512); -+ break; -+ case FMC2_CPSIZE_1024: -+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024); -+ break; -+ default: -+ /* Cpsize not supported */ -+ return -EINVAL; -+ } -+ -+ clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val; -+ -+ val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX); -+ val = FIELD_PREP(FMC2_BCR_NBLSET, val); -+ clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ u32 bxtr = prop->reg_type == FMC2_REG_BWTR ? -+ readl(ebi->io_base + FMC2_BWTR(cs)) : -+ readl(ebi->io_base + FMC2_BTR(cs)); -+ u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN) -+ val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX); -+ else -+ val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX); -+ val = FIELD_PREP(FMC2_BXTR_ADDSET, val); -+ clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val, reg; -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX); -+ val = FIELD_PREP(FMC2_BXTR_ADDHLD, val); -+ clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val, reg; -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX); -+ val = FIELD_PREP(FMC2_BXTR_DATAST, val); -+ clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val, reg; -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0; -+ val = FIELD_PREP(FMC2_BXTR_BUSTURN, val); -+ clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val, reg; -+ int ret; -+ -+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); -+ if (ret) -+ return ret; -+ -+ if (prop->reg_type == FMC2_REG_BWTR) -+ val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0; -+ else -+ val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX); -+ val = FIELD_PREP(FMC2_BXTR_DATAHLD, val); -+ clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val; -+ -+ val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; -+ val = FIELD_PREP(FMC2_BTR_CLKDIV, val); -+ clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 val; -+ -+ val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0; -+ val = FIELD_PREP(FMC2_BTR_DATLAT, val); -+ clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, -+ const struct stm32_fmc2_prop *prop, -+ int cs, u32 setup) -+{ -+ u32 old_val, new_val, pcscntr; -+ -+ if (setup < 1) -+ return 0; -+ -+ pcscntr = readl(ebi->io_base + FMC2_PCSCNTR); -+ -+ /* Enable counter for the bank */ -+ setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs)); -+ -+ new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); -+ old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); -+ if (old_val && new_val > old_val) -+ /* Keep current counter value */ -+ return 0; -+ -+ new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); -+ clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR, -+ FMC2_PCSCNTR_CSCOUNT, new_val); -+ -+ return 0; -+} -+ -+static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { -+ /* st,fmc2-ebi-cs-trans-type must be the first property */ -+ { -+ .name = "st,fmc2-ebi-cs-transaction-type", -+ .mprop = true, -+ .set = stm32_fmc2_ebi_set_trans_type, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-cclk-enable", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR1_CCLKEN, -+ .check = stm32_fmc2_ebi_check_cclk, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-mux-enable", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR_MUXEN, -+ .check = stm32_fmc2_ebi_check_mux, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-buswidth", -+ .reset_val = FMC2_BUSWIDTH_16, -+ .set = stm32_fmc2_ebi_set_buswidth, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-waitpol-high", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR_WAITPOL, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-waitcfg-enable", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR_WAITCFG, -+ .check = stm32_fmc2_ebi_check_waitcfg, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-wait-enable", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR_WAITEN, -+ .check = stm32_fmc2_ebi_check_sync_trans, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-asyncwait-enable", -+ .bprop = true, -+ .reg_type = FMC2_REG_BCR, -+ .reg_mask = FMC2_BCR_ASYNCWAIT, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .set = stm32_fmc2_ebi_set_bit_field, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-cpsize", -+ .check = stm32_fmc2_ebi_check_cpsize, -+ .set = stm32_fmc2_ebi_set_cpsize, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_bl_setup, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-address-setup-ns", -+ .reg_type = FMC2_REG_BTR, -+ .reset_val = FMC2_BXTR_ADDSET_MAX, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_address_setup, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-address-hold-ns", -+ .reg_type = FMC2_REG_BTR, -+ .reset_val = FMC2_BXTR_ADDHLD_MAX, -+ .check = stm32_fmc2_ebi_check_address_hold, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_address_hold, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-data-setup-ns", -+ .reg_type = FMC2_REG_BTR, -+ .reset_val = FMC2_BXTR_DATAST_MAX, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_data_setup, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-bus-turnaround-ns", -+ .reg_type = FMC2_REG_BTR, -+ .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_bus_turnaround, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-data-hold-ns", -+ .reg_type = FMC2_REG_BTR, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_data_hold, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-clk-period-ns", -+ .reset_val = FMC2_BTR_CLKDIV_MAX + 1, -+ .check = stm32_fmc2_ebi_check_clk_period, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_clk_period, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-data-latency-ns", -+ .check = stm32_fmc2_ebi_check_sync_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clk_period, -+ .set = stm32_fmc2_ebi_set_data_latency, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-write-address-setup-ns", -+ .reg_type = FMC2_REG_BWTR, -+ .reset_val = FMC2_BXTR_ADDSET_MAX, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_address_setup, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-write-address-hold-ns", -+ .reg_type = FMC2_REG_BWTR, -+ .reset_val = FMC2_BXTR_ADDHLD_MAX, -+ .check = stm32_fmc2_ebi_check_address_hold, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_address_hold, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-write-data-setup-ns", -+ .reg_type = FMC2_REG_BWTR, -+ .reset_val = FMC2_BXTR_DATAST_MAX, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_data_setup, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", -+ .reg_type = FMC2_REG_BWTR, -+ .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_bus_turnaround, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-write-data-hold-ns", -+ .reg_type = FMC2_REG_BWTR, -+ .check = stm32_fmc2_ebi_check_async_trans, -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_data_hold, -+ }, -+ { -+ .name = "st,fmc2-ebi-cs-max-low-pulse-ns", -+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, -+ .set = stm32_fmc2_ebi_set_max_low_pulse, -+ }, -+}; -+ -+static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, -+ ofnode node, -+ const struct stm32_fmc2_prop *prop, -+ int cs) -+{ -+ u32 setup = 0; -+ -+ if (!prop->set) { -+ pr_err("property %s is not well defined\n", prop->name); -+ return -EINVAL; -+ } -+ -+ if (prop->check && prop->check(ebi, prop, cs)) -+ /* Skip this property */ -+ return 0; -+ -+ if (prop->bprop) { -+ bool bprop; -+ -+ bprop = ofnode_read_bool(node, prop->name); -+ if (prop->mprop && !bprop) { -+ pr_err("mandatory property %s not defined in the device tree\n", -+ prop->name); -+ return -EINVAL; -+ } -+ -+ if (bprop) -+ setup = 1; -+ } else { -+ u32 val; -+ int ret; -+ -+ ret = ofnode_read_u32(node, prop->name, &val); -+ if (prop->mprop && ret) { -+ pr_err("mandatory property %s not defined in the device tree\n", -+ prop->name); -+ return ret; -+ } -+ -+ if (ret) -+ setup = prop->reset_val; -+ else if (prop->calculate) -+ setup = prop->calculate(ebi, cs, val); -+ else -+ setup = val; -+ } -+ -+ return prop->set(ebi, prop, cs, setup); -+} -+ -+static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs) -+{ -+ setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN); -+} -+ -+static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs) -+{ -+ clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN); -+} -+ -+/* NWAIT signal can not be connected to EBI controller and NAND controller */ -+static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) -+{ -+ unsigned int cs; -+ u32 bcr; -+ -+ for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { -+ if (!(ebi->bank_assigned & BIT(cs))) -+ continue; -+ -+ bcr = readl(ebi->io_base + FMC2_BCR(cs)); -+ if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && -+ ebi->bank_assigned & BIT(FMC2_NAND)) -+ return true; -+ } -+ -+ return false; -+} -+ -+static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) -+{ -+ setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN); -+} -+ -+static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, -+ ofnode node, u32 cs) -+{ -+ unsigned int i; -+ int ret; -+ -+ stm32_fmc2_ebi_disable_bank(ebi, cs); -+ -+ for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) { -+ const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i]; -+ -+ ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs); -+ if (ret) { -+ pr_err("property %s could not be set: %d\n", -+ p->name, ret); -+ return ret; -+ } -+ } -+ -+ stm32_fmc2_ebi_enable_bank(ebi, cs); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_parse_dt(struct udevice *dev, -+ struct stm32_fmc2_ebi *ebi) -+{ -+ ofnode child; -+ bool child_found = false; -+ u32 bank; -+ int ret; -+ -+ dev_for_each_subnode(child, dev) { -+ ret = ofnode_read_u32(child, "reg", &bank); -+ if (ret) { -+ pr_err("could not retrieve reg property: %d\n", ret); -+ return ret; -+ } -+ -+ if (bank >= FMC2_MAX_BANKS) { -+ pr_err("invalid reg value: %d\n", bank); -+ return -EINVAL; -+ } -+ -+ if (ebi->bank_assigned & BIT(bank)) { -+ pr_err("bank already assigned: %d\n", bank); -+ return -EINVAL; -+ } -+ -+ if (bank < FMC2_MAX_EBI_CE) { -+ ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); -+ if (ret) { -+ pr_err("setup chip select %d failed: %d\n", -+ bank, ret); -+ return ret; -+ } -+ } -+ -+ ebi->bank_assigned |= BIT(bank); -+ child_found = true; -+ } -+ -+ if (!child_found) { -+ pr_warn("no subnodes found, disable the driver.\n"); -+ return -ENODEV; -+ } -+ -+ if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) { -+ pr_err("NWAIT signal connected to EBI and NAND controllers\n"); -+ return -EINVAL; -+ } -+ -+ stm32_fmc2_ebi_enable(ebi); -+ -+ return 0; -+} -+ -+static int stm32_fmc2_ebi_probe(struct udevice *dev) -+{ -+ struct stm32_fmc2_ebi *ebi = dev_get_priv(dev); -+ struct reset_ctl reset; -+ int ret; -+ -+ ebi->io_base = dev_read_addr(dev); -+ if (ebi->io_base == FDT_ADDR_T_NONE) -+ return -EINVAL; -+ -+ ret = clk_get_by_index(dev, 0, &ebi->clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_enable(&ebi->clk); -+ if (ret) -+ return ret; -+ -+ ret = reset_get_by_index(dev, 0, &reset); -+ if (!ret) { -+ reset_assert(&reset); -+ udelay(2); -+ reset_deassert(&reset); -+ } -+ -+ return stm32_fmc2_ebi_parse_dt(dev, ebi); -+} -+ -+static const struct udevice_id stm32_fmc2_ebi_match[] = { -+ {.compatible = "st,stm32mp1-fmc2-ebi"}, -+ { /* Sentinel */ } -+}; -+ -+U_BOOT_DRIVER(stm32_fmc2_ebi) = { -+ .name = "stm32_fmc2_ebi", -+ .id = UCLASS_NOP, -+ .of_match = stm32_fmc2_ebi_match, -+ .probe = stm32_fmc2_ebi_probe, -+ .priv_auto_alloc_size = sizeof(struct stm32_fmc2_ebi), -+ .bind = dm_scan_fdt_dev, -+}; -diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c -index f3179cc21f..9897976947 100644 ---- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c -+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -56,20 +57,16 @@ - /* Register: FMC2_PCR */ - #define FMC2_PCR_PWAITEN BIT(1) - #define FMC2_PCR_PBKEN BIT(2) --#define FMC2_PCR_PWID_MASK GENMASK(5, 4) --#define FMC2_PCR_PWID(x) (((x) & 0x3) << 4) -+#define FMC2_PCR_PWID GENMASK(5, 4) - #define FMC2_PCR_PWID_BUSWIDTH_8 0 - #define FMC2_PCR_PWID_BUSWIDTH_16 1 - #define FMC2_PCR_ECCEN BIT(6) - #define FMC2_PCR_ECCALG BIT(8) --#define FMC2_PCR_TCLR_MASK GENMASK(12, 9) --#define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9) -+#define FMC2_PCR_TCLR GENMASK(12, 9) - #define FMC2_PCR_TCLR_DEFAULT 0xf --#define FMC2_PCR_TAR_MASK GENMASK(16, 13) --#define FMC2_PCR_TAR(x) (((x) & 0xf) << 13) -+#define FMC2_PCR_TAR GENMASK(16, 13) - #define FMC2_PCR_TAR_DEFAULT 0xf --#define FMC2_PCR_ECCSS_MASK GENMASK(19, 17) --#define FMC2_PCR_ECCSS(x) (((x) & 0x7) << 17) -+#define FMC2_PCR_ECCSS GENMASK(19, 17) - #define FMC2_PCR_ECCSS_512 1 - #define FMC2_PCR_ECCSS_2048 3 - #define FMC2_PCR_BCHECC BIT(24) -@@ -79,17 +76,17 @@ - #define FMC2_SR_NWRF BIT(6) - - /* Register: FMC2_PMEM */ --#define FMC2_PMEM_MEMSET(x) (((x) & 0xff) << 0) --#define FMC2_PMEM_MEMWAIT(x) (((x) & 0xff) << 8) --#define FMC2_PMEM_MEMHOLD(x) (((x) & 0xff) << 16) --#define FMC2_PMEM_MEMHIZ(x) (((x) & 0xff) << 24) -+#define FMC2_PMEM_MEMSET GENMASK(7, 0) -+#define FMC2_PMEM_MEMWAIT GENMASK(15, 8) -+#define FMC2_PMEM_MEMHOLD GENMASK(23, 16) -+#define FMC2_PMEM_MEMHIZ GENMASK(31, 24) - #define FMC2_PMEM_DEFAULT 0x0a0a0a0a - - /* Register: FMC2_PATT */ --#define FMC2_PATT_ATTSET(x) (((x) & 0xff) << 0) --#define FMC2_PATT_ATTWAIT(x) (((x) & 0xff) << 8) --#define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16) --#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24) -+#define FMC2_PATT_ATTSET GENMASK(7, 0) -+#define FMC2_PATT_ATTWAIT GENMASK(15, 8) -+#define FMC2_PATT_ATTHOLD GENMASK(23, 16) -+#define FMC2_PATT_ATTHIZ GENMASK(31, 24) - #define FMC2_PATT_DEFAULT 0x0a0a0a0a - - /* Register: FMC2_BCHISR */ -@@ -102,31 +99,28 @@ - /* Register: FMC2_BCHDSR0 */ - #define FMC2_BCHDSR0_DUE BIT(0) - #define FMC2_BCHDSR0_DEF BIT(1) --#define FMC2_BCHDSR0_DEN_MASK GENMASK(7, 4) --#define FMC2_BCHDSR0_DEN_SHIFT 4 -+#define FMC2_BCHDSR0_DEN GENMASK(7, 4) - - /* Register: FMC2_BCHDSR1 */ --#define FMC2_BCHDSR1_EBP1_MASK GENMASK(12, 0) --#define FMC2_BCHDSR1_EBP2_MASK GENMASK(28, 16) --#define FMC2_BCHDSR1_EBP2_SHIFT 16 -+#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0) -+#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16) - - /* Register: FMC2_BCHDSR2 */ --#define FMC2_BCHDSR2_EBP3_MASK GENMASK(12, 0) --#define FMC2_BCHDSR2_EBP4_MASK GENMASK(28, 16) --#define FMC2_BCHDSR2_EBP4_SHIFT 16 -+#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0) -+#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16) - - /* Register: FMC2_BCHDSR3 */ --#define FMC2_BCHDSR3_EBP5_MASK GENMASK(12, 0) --#define FMC2_BCHDSR3_EBP6_MASK GENMASK(28, 16) --#define FMC2_BCHDSR3_EBP6_SHIFT 16 -+#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0) -+#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16) - - /* Register: FMC2_BCHDSR4 */ --#define FMC2_BCHDSR4_EBP7_MASK GENMASK(12, 0) --#define FMC2_BCHDSR4_EBP8_MASK GENMASK(28, 16) --#define FMC2_BCHDSR4_EBP8_SHIFT 16 -+#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) -+#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) - - #define FMC2_NSEC_PER_SEC 1000000000L - -+#define FMC2_TIMEOUT_5S 5000000 -+ - enum stm32_fmc2_ecc { - FMC2_ECC_HAM = 1, - FMC2_ECC_BCH4 = 4, -@@ -160,10 +154,10 @@ struct stm32_fmc2_nfc { - struct nand_hw_control base; - struct stm32_fmc2_nand nand; - struct nand_ecclayout ecclayout; -- void __iomem *io_base; -- void __iomem *data_base[FMC2_MAX_CE]; -- void __iomem *cmd_base[FMC2_MAX_CE]; -- void __iomem *addr_base[FMC2_MAX_CE]; -+ fdt_addr_t io_base; -+ fdt_addr_t data_base[FMC2_MAX_CE]; -+ fdt_addr_t cmd_base[FMC2_MAX_CE]; -+ fdt_addr_t addr_base[FMC2_MAX_CE]; - struct clk clk; - - u8 cs_assigned; -@@ -175,47 +169,42 @@ static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base) - return container_of(base, struct stm32_fmc2_nfc, base); - } - --/* Timings configuration */ --static void stm32_fmc2_timings_init(struct nand_chip *chip) -+static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip) - { -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); - struct stm32_fmc2_timings *timings = &nand->timings; -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); - u32 pmem, patt; - - /* Set tclr/tar timings */ -- pcr &= ~FMC2_PCR_TCLR_MASK; -- pcr |= FMC2_PCR_TCLR(timings->tclr); -- pcr &= ~FMC2_PCR_TAR_MASK; -- pcr |= FMC2_PCR_TAR(timings->tar); -+ clrsetbits_le32(nfc->io_base + FMC2_PCR, -+ FMC2_PCR_TCLR | FMC2_PCR_TAR, -+ FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | -+ FIELD_PREP(FMC2_PCR_TAR, timings->tar)); - - /* Set tset/twait/thold/thiz timings in common bank */ -- pmem = FMC2_PMEM_MEMSET(timings->tset_mem); -- pmem |= FMC2_PMEM_MEMWAIT(timings->twait); -- pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem); -- pmem |= FMC2_PMEM_MEMHIZ(timings->thiz); -+ pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); -+ pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait); -+ pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem); -+ pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz); -+ writel(pmem, nfc->io_base + FMC2_PMEM); - - /* Set tset/twait/thold/thiz timings in attribut bank */ -- patt = FMC2_PATT_ATTSET(timings->tset_att); -- patt |= FMC2_PATT_ATTWAIT(timings->twait); -- patt |= FMC2_PATT_ATTHOLD(timings->thold_att); -- patt |= FMC2_PATT_ATTHIZ(timings->thiz); -- -- writel(pcr, fmc2->io_base + FMC2_PCR); -- writel(pmem, fmc2->io_base + FMC2_PMEM); -- writel(patt, fmc2->io_base + FMC2_PATT); -+ patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att); -+ patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait); -+ patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att); -+ patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz); -+ writel(patt, nfc->io_base + FMC2_PATT); - } - --/* Controller configuration */ --static void stm32_fmc2_setup(struct nand_chip *chip) -+static void stm32_fmc2_nfc_setup(struct nand_chip *chip) - { -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); -+ u32 pcr = 0, pcr_mask; - - /* Configure ECC algorithm (default configuration is Hamming) */ -- pcr &= ~FMC2_PCR_ECCALG; -- pcr &= ~FMC2_PCR_BCHECC; -+ pcr_mask = FMC2_PCR_ECCALG; -+ pcr_mask |= FMC2_PCR_BCHECC; - if (chip->ecc.strength == FMC2_ECC_BCH8) { - pcr |= FMC2_PCR_ECCALG; - pcr |= FMC2_PCR_BCHECC; -@@ -224,111 +213,95 @@ static void stm32_fmc2_setup(struct nand_chip *chip) - } - - /* Set buswidth */ -- pcr &= ~FMC2_PCR_PWID_MASK; -+ pcr_mask |= FMC2_PCR_PWID; - if (chip->options & NAND_BUSWIDTH_16) -- pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16); -+ pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); - - /* Set ECC sector size */ -- pcr &= ~FMC2_PCR_ECCSS_MASK; -- pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); -+ pcr_mask |= FMC2_PCR_ECCSS; -+ pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512); - -- writel(pcr, fmc2->io_base + FMC2_PCR); -+ clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr); - } - --/* Select target */ --static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr) -+static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); - - if (chipnr < 0 || chipnr >= nand->ncs) - return; - -- if (nand->cs_used[chipnr] == fmc2->cs_sel) -+ if (nand->cs_used[chipnr] == nfc->cs_sel) - return; - -- fmc2->cs_sel = nand->cs_used[chipnr]; -- chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel]; -- chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel]; -- -- /* FMC2 setup routine */ -- stm32_fmc2_setup(chip); -+ nfc->cs_sel = nand->cs_used[chipnr]; -+ chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel]; -+ chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel]; - -- /* Apply timings */ -- stm32_fmc2_timings_init(chip); -+ stm32_fmc2_nfc_setup(chip); -+ stm32_fmc2_nfc_timings_init(chip); - } - --/* Set bus width to 16-bit or 8-bit */ --static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set) -+static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, -+ bool set) - { -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); -+ u32 pcr; - -- pcr &= ~FMC2_PCR_PWID_MASK; -- if (set) -- pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16); -- writel(pcr, fmc2->io_base + FMC2_PCR); -+ pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) : -+ FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8); -+ -+ clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr); - } - --/* Enable/disable ECC */ --static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable) -+static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable) - { -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); -- -- pcr &= ~FMC2_PCR_ECCEN; -- if (enable) -- pcr |= FMC2_PCR_ECCEN; -- writel(pcr, fmc2->io_base + FMC2_PCR); -+ clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN, -+ enable ? FMC2_PCR_ECCEN : 0); - } - --/* Clear irq sources in case of bch is used */ --static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2) -+static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc) - { -- writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR); -+ writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR); - } - --/* Send command and address cycles */ --static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd, -- unsigned int ctrl) -+static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) { -- writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]); -+ writeb(cmd, nfc->cmd_base[nfc->cs_sel]); - return; - } - -- writeb(cmd, fmc2->addr_base[fmc2->cs_sel]); -+ writeb(cmd, nfc->addr_base[nfc->cs_sel]); - } - - /* - * Enable ECC logic and reset syndrome/parity bits previously calculated - * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 - */ --static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode) -+static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - -- stm32_fmc2_set_ecc(fmc2, false); -+ stm32_fmc2_nfc_set_ecc(nfc, false); - - if (chip->ecc.strength != FMC2_ECC_HAM) { -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); -+ clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN, -+ mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0); - -- if (mode == NAND_ECC_WRITE) -- pcr |= FMC2_PCR_WEN; -- else -- pcr &= ~FMC2_PCR_WEN; -- writel(pcr, fmc2->io_base + FMC2_PCR); -- -- stm32_fmc2_clear_bch_irq(fmc2); -+ stm32_fmc2_nfc_clear_bch_irq(nfc); - } - -- stm32_fmc2_set_ecc(fmc2, true); -+ stm32_fmc2_nfc_set_ecc(nfc, true); - } - - /* -@@ -336,35 +309,34 @@ static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode) - * ECC is 3 bytes for 512 bytes of data (supports error correction up to - * max of 1-bit) - */ --static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data, -- u8 *ecc) -+static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data, -+ u8 *ecc) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - u32 heccr, sr; - int ret; - -- ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr, -- sr & FMC2_SR_NWRF, 10000); -+ ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr, -+ sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S); - if (ret < 0) { - pr_err("Ham timeout\n"); - return ret; - } - -- heccr = readl(fmc2->io_base + FMC2_HECCR); -+ heccr = readl(nfc->io_base + FMC2_HECCR); - - ecc[0] = heccr; - ecc[1] = heccr >> 8; - ecc[2] = heccr >> 16; - -- /* Disable ecc */ -- stm32_fmc2_set_ecc(fmc2, false); -+ stm32_fmc2_nfc_set_ecc(nfc, false); - - return 0; - } - --static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat, -- u8 *read_ecc, u8 *calc_ecc) -+static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat, -+ u8 *read_ecc, u8 *calc_ecc) - { - u8 bit_position = 0, b0, b1, b2; - u32 byte_addr = 0, b; -@@ -421,30 +393,30 @@ static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat, - * max of 4-bit/8-bit) - */ - --static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data, -- u8 *ecc) -+static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data, -+ u8 *ecc) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - u32 bchpbr, bchisr; - int ret; - - /* Wait until the BCH code is ready */ -- ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr, -- bchisr & FMC2_BCHISR_EPBRF, 10000); -+ ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, -+ bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S); - if (ret < 0) { - pr_err("Bch timeout\n"); - return ret; - } - - /* Read parity bits */ -- bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1); -+ bchpbr = readl(nfc->io_base + FMC2_BCHPBR1); - ecc[0] = bchpbr; - ecc[1] = bchpbr >> 8; - ecc[2] = bchpbr >> 16; - ecc[3] = bchpbr >> 24; - -- bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2); -+ bchpbr = readl(nfc->io_base + FMC2_BCHPBR2); - ecc[4] = bchpbr; - ecc[5] = bchpbr >> 8; - ecc[6] = bchpbr >> 16; -@@ -452,49 +424,46 @@ static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data, - if (chip->ecc.strength == FMC2_ECC_BCH8) { - ecc[7] = bchpbr >> 24; - -- bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3); -+ bchpbr = readl(nfc->io_base + FMC2_BCHPBR3); - ecc[8] = bchpbr; - ecc[9] = bchpbr >> 8; - ecc[10] = bchpbr >> 16; - ecc[11] = bchpbr >> 24; - -- bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4); -+ bchpbr = readl(nfc->io_base + FMC2_BCHPBR4); - ecc[12] = bchpbr; - } - -- /* Disable ecc */ -- stm32_fmc2_set_ecc(fmc2, false); -+ stm32_fmc2_nfc_set_ecc(nfc, false); - - return 0; - } - --/* BCH algorithm correction */ --static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat, -- u8 *read_ecc, u8 *calc_ecc) -+static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat, -+ u8 *read_ecc, u8 *calc_ecc) - { - struct nand_chip *chip = mtd_to_nand(mtd); -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr; - u16 pos[8]; - int i, ret, den, eccsize = chip->ecc.size; - unsigned int nb_errs = 0; - - /* Wait until the decoding error is ready */ -- ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr, -- bchisr & FMC2_BCHISR_DERF, 10000); -+ ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, -+ bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S); - if (ret < 0) { - pr_err("Bch timeout\n"); - return ret; - } - -- bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0); -- bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1); -- bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2); -- bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3); -- bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4); -+ bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0); -+ bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1); -+ bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2); -+ bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3); -+ bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4); - -- /* Disable ECC */ -- stm32_fmc2_set_ecc(fmc2, false); -+ stm32_fmc2_nfc_set_ecc(nfc, false); - - /* No errors found */ - if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) -@@ -504,16 +473,16 @@ static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat, - if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) - return -EBADMSG; - -- pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; -- pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; -- pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; -- pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; -- pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; -- pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; -- pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; -- pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; -+ pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1); -+ pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1); -+ pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2); -+ pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2); -+ pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3); -+ pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3); -+ pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4); -+ pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4); - -- den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; -+ den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0); - for (i = 0; i < den; i++) { - if (pos[i] < eccsize * 8) { - __change_bit(pos[i], (unsigned long *)dat); -@@ -524,9 +493,9 @@ static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat, - return nb_errs; - } - --static int stm32_fmc2_read_page(struct mtd_info *mtd, -- struct nand_chip *chip, u8 *buf, -- int oob_required, int page) -+static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd, -+ struct nand_chip *chip, u8 *buf, -+ int oob_required, int page) - { - int i, s, stat, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; -@@ -575,21 +544,19 @@ static int stm32_fmc2_read_page(struct mtd_info *mtd, - return max_bitflips; - } - --/* Controller initialization */ --static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2) -+static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent) - { -- u32 pcr = readl(fmc2->io_base + FMC2_PCR); -- u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1); -+ u32 pcr = readl(nfc->io_base + FMC2_PCR); - - /* Set CS used to undefined */ -- fmc2->cs_sel = -1; -+ nfc->cs_sel = -1; - - /* Enable wait feature and nand flash memory bank */ - pcr |= FMC2_PCR_PWAITEN; - pcr |= FMC2_PCR_PBKEN; - - /* Set buswidth to 8 bits mode for identification */ -- pcr &= ~FMC2_PCR_PWID_MASK; -+ pcr &= ~FMC2_PCR_PWID; - - /* ECC logic is disabled */ - pcr &= ~FMC2_PCR_ECCEN; -@@ -600,32 +567,31 @@ static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2) - pcr &= ~FMC2_PCR_WEN; - - /* Set default ECC sector size */ -- pcr &= ~FMC2_PCR_ECCSS_MASK; -- pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); -+ pcr &= ~FMC2_PCR_ECCSS; -+ pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048); - - /* Set default tclr/tar timings */ -- pcr &= ~FMC2_PCR_TCLR_MASK; -- pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); -- pcr &= ~FMC2_PCR_TAR_MASK; -- pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); -+ pcr &= ~FMC2_PCR_TCLR; -+ pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT); -+ pcr &= ~FMC2_PCR_TAR; -+ pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); - - /* Enable FMC2 controller */ -- bcr1 |= FMC2_BCR1_FMC2EN; -+ if (!has_parent) -+ setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN); - -- writel(bcr1, fmc2->io_base + FMC2_BCR1); -- writel(pcr, fmc2->io_base + FMC2_PCR); -- writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM); -- writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT); -+ writel(pcr, nfc->io_base + FMC2_PCR); -+ writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM); -+ writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT); - } - --/* Controller timings */ --static void stm32_fmc2_calc_timings(struct nand_chip *chip, -- const struct nand_sdr_timings *sdrt) -+static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, -+ const struct nand_sdr_timings *sdrt) - { -- struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); -+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); - struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); - struct stm32_fmc2_timings *tims = &nand->timings; -- unsigned long hclk = clk_get_rate(&fmc2->clk); -+ unsigned long hclk = clk_get_rate(&nfc->clk); - unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); - unsigned long timing, tar, tclr, thiz, twait; - unsigned long tset_mem, tset_att, thold_mem, thold_att; -@@ -749,31 +715,28 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, - tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); - } - --static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr, -- const struct nand_data_interface *conf) -+static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr, -+ const struct nand_data_interface *cf) - { - struct nand_chip *chip = mtd_to_nand(mtd); - const struct nand_sdr_timings *sdrt; - -- sdrt = nand_get_sdr_timings(conf); -+ sdrt = nand_get_sdr_timings(cf); - if (IS_ERR(sdrt)) - return PTR_ERR(sdrt); - - if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) - return 0; - -- stm32_fmc2_calc_timings(chip, sdrt); -- -- /* Apply timings */ -- stm32_fmc2_timings_init(chip); -+ stm32_fmc2_nfc_calc_timings(chip, sdrt); -+ stm32_fmc2_nfc_timings_init(chip); - - return 0; - } - --/* NAND callbacks setup */ --static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip) -+static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip) - { -- chip->ecc.hwctl = stm32_fmc2_hwctl; -+ chip->ecc.hwctl = stm32_fmc2_nfc_hwctl; - - /* - * Specific callbacks to read/write a page depending on -@@ -781,17 +744,17 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip) - */ - if (chip->ecc.strength == FMC2_ECC_HAM) { - /* Hamming is used */ -- chip->ecc.calculate = stm32_fmc2_ham_calculate; -- chip->ecc.correct = stm32_fmc2_ham_correct; -+ chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate; -+ chip->ecc.correct = stm32_fmc2_nfc_ham_correct; - chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; - chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; - return; - } - - /* BCH is used */ -- chip->ecc.read_page = stm32_fmc2_read_page; -- chip->ecc.calculate = stm32_fmc2_bch_calculate; -- chip->ecc.correct = stm32_fmc2_bch_correct; -+ chip->ecc.read_page = stm32_fmc2_nfc_read_page; -+ chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate; -+ chip->ecc.correct = stm32_fmc2_nfc_bch_correct; - - if (chip->ecc.strength == FMC2_ECC_BCH8) - chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; -@@ -799,8 +762,7 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip) - chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; - } - --/* FMC2 caps */ --static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength) -+static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength) - { - /* Hamming */ - if (strength == FMC2_ECC_HAM) -@@ -814,15 +776,13 @@ static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength) - return 8; - } - --NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes, -+NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes, - FMC2_ECC_STEP_SIZE, - FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); - --/* FMC2 probe */ --static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2, -- ofnode node) -+static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) - { -- struct stm32_fmc2_nand *nand = &fmc2->nand; -+ struct stm32_fmc2_nand *nand = &nfc->nand; - u32 cs[FMC2_MAX_CE]; - int ret, i; - -@@ -842,19 +802,19 @@ static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2, - } - - for (i = 0; i < nand->ncs; i++) { -- if (cs[i] > FMC2_MAX_CE) { -+ if (cs[i] >= FMC2_MAX_CE) { - pr_err("Invalid reg value: %d\n", - nand->cs_used[i]); - return -EINVAL; - } - -- if (fmc2->cs_assigned & BIT(cs[i])) { -+ if (nfc->cs_assigned & BIT(cs[i])) { - pr_err("Cs already assigned: %d\n", - nand->cs_used[i]); - return -EINVAL; - } - -- fmc2->cs_assigned |= BIT(cs[i]); -+ nfc->cs_assigned |= BIT(cs[i]); - nand->cs_used[i] = cs[i]; - } - -@@ -863,8 +823,8 @@ static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2, - return 0; - } - --static int stm32_fmc2_parse_dt(struct udevice *dev, -- struct stm32_fmc2_nfc *fmc2) -+static int stm32_fmc2_nfc_parse_dt(struct udevice *dev, -+ struct stm32_fmc2_nfc *nfc) - { - ofnode child; - int ret, nchips = 0; -@@ -883,7 +843,7 @@ static int stm32_fmc2_parse_dt(struct udevice *dev, - } - - dev_for_each_subnode(child, dev) { -- ret = stm32_fmc2_parse_child(fmc2, child); -+ ret = stm32_fmc2_nfc_parse_child(nfc, child); - if (ret) - return ret; - } -@@ -891,69 +851,98 @@ static int stm32_fmc2_parse_dt(struct udevice *dev, - return 0; - } - --static int stm32_fmc2_probe(struct udevice *dev) -+static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev) - { -- struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev); -- struct stm32_fmc2_nand *nand = &fmc2->nand; -+ struct udevice *pdev = dev_get_parent(dev); -+ struct udevice *cdev = NULL; -+ bool ebi_found = false; -+ -+ if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev), -+ "st,stm32mp1-fmc2-ebi")) -+ ebi_found = true; -+ -+ if (ofnode_device_is_compatible(dev_ofnode(dev), -+ "st,stm32mp1-fmc2-nfc")) { -+ if (ebi_found) -+ cdev = pdev; -+ -+ return cdev; -+ } -+ -+ if (!ebi_found) -+ cdev = dev; -+ -+ return cdev; -+} -+ -+static int stm32_fmc2_nfc_probe(struct udevice *dev) -+{ -+ struct stm32_fmc2_nfc *nfc = dev_get_priv(dev); -+ struct stm32_fmc2_nand *nand = &nfc->nand; - struct nand_chip *chip = &nand->chip; - struct mtd_info *mtd = &chip->mtd; - struct nand_ecclayout *ecclayout; -- struct resource resource; -+ struct udevice *cdev; - struct reset_ctl reset; - int oob_index, chip_cs, mem_region, ret; - unsigned int i; -+ int start_region = 0; -+ fdt_addr_t addr; -+ -+ spin_lock_init(&nfc->controller.lock); -+ init_waitqueue_head(&nfc->controller.wq); - -- spin_lock_init(&fmc2->controller.lock); -- init_waitqueue_head(&fmc2->controller.wq); -+ cdev = stm32_fmc2_nfc_get_cdev(dev); -+ if (!cdev) -+ return -EINVAL; - -- ret = stm32_fmc2_parse_dt(dev, fmc2); -+ ret = stm32_fmc2_nfc_parse_dt(dev, nfc); - if (ret) - return ret; - -- /* Get resources */ -- ret = dev_read_resource(dev, 0, &resource); -- if (ret) { -- pr_err("Resource io_base not found"); -- return ret; -- } -- fmc2->io_base = (void __iomem *)resource.start; -+ nfc->io_base = dev_read_addr(cdev); -+ if (nfc->io_base == FDT_ADDR_T_NONE) -+ return -EINVAL; -+ -+ if (dev == cdev) -+ start_region = 1; - -- for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE; -+ for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE; - chip_cs++, mem_region += 3) { -- if (!(fmc2->cs_assigned & BIT(chip_cs))) -+ if (!(nfc->cs_assigned & BIT(chip_cs))) - continue; - -- ret = dev_read_resource(dev, mem_region, &resource); -- if (ret) { -+ addr = dev_read_addr_index(dev, mem_region); -+ if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource data_base not found for cs%d", - chip_cs); - return ret; - } -- fmc2->data_base[chip_cs] = (void __iomem *)resource.start; -+ nfc->data_base[chip_cs] = addr; - -- ret = dev_read_resource(dev, mem_region + 1, &resource); -- if (ret) { -+ addr = dev_read_addr_index(dev, mem_region + 1); -+ if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource cmd_base not found for cs%d", - chip_cs); - return ret; - } -- fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start; -+ nfc->cmd_base[chip_cs] = addr; - -- ret = dev_read_resource(dev, mem_region + 2, &resource); -- if (ret) { -+ addr = dev_read_addr_index(dev, mem_region + 2); -+ if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource addr_base not found for cs%d", - chip_cs); - return ret; - } -- fmc2->addr_base[chip_cs] = (void __iomem *)resource.start; -+ nfc->addr_base[chip_cs] = addr; - } - - /* Enable the clock */ -- ret = clk_get_by_index(dev, 0, &fmc2->clk); -+ ret = clk_get_by_index(cdev, 0, &nfc->clk); - if (ret) - return ret; - -- ret = clk_enable(&fmc2->clk); -+ ret = clk_enable(&nfc->clk); - if (ret) - return ret; - -@@ -965,13 +954,12 @@ static int stm32_fmc2_probe(struct udevice *dev) - reset_deassert(&reset); - } - -- /* FMC2 init routine */ -- stm32_fmc2_init(fmc2); -+ stm32_fmc2_nfc_init(nfc, dev != cdev); - -- chip->controller = &fmc2->base; -- chip->select_chip = stm32_fmc2_select_chip; -- chip->setup_data_interface = stm32_fmc2_setup_interface; -- chip->cmd_ctrl = stm32_fmc2_cmd_ctrl; -+ chip->controller = &nfc->base; -+ chip->select_chip = stm32_fmc2_nfc_select_chip; -+ chip->setup_data_interface = stm32_fmc2_nfc_setup_interface; -+ chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl; - chip->chip_delay = FMC2_RB_DELAY_US; - chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | - NAND_USE_BOUNCE_BUFFER; -@@ -981,7 +969,6 @@ static int stm32_fmc2_probe(struct udevice *dev) - chip->ecc.size = FMC2_ECC_STEP_SIZE; - chip->ecc.strength = FMC2_ECC_BCH8; - -- /* Scan to find existence of the device */ - ret = nand_scan_ident(mtd, nand->ncs, NULL); - if (ret) - return ret; -@@ -998,7 +985,7 @@ static int stm32_fmc2_probe(struct udevice *dev) - return -EINVAL; - } - -- ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps, -+ ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps, - mtd->oobsize - FMC2_BBM_LEN); - if (ret) { - pr_err("No valid ECC settings set\n"); -@@ -1008,11 +995,10 @@ static int stm32_fmc2_probe(struct udevice *dev) - if (chip->bbt_options & NAND_BBT_USE_FLASH) - chip->bbt_options |= NAND_BBT_NO_OOB; - -- /* NAND callbacks setup */ -- stm32_fmc2_nand_callbacks_setup(chip); -+ stm32_fmc2_nfc_nand_callbacks_setup(chip); - - /* Define ECC layout */ -- ecclayout = &fmc2->ecclayout; -+ ecclayout = &nfc->ecclayout; - ecclayout->eccbytes = chip->ecc.bytes * - (mtd->writesize / chip->ecc.size); - oob_index = FMC2_BBM_LEN; -@@ -1022,11 +1008,9 @@ static int stm32_fmc2_probe(struct udevice *dev) - ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; - chip->ecc.layout = ecclayout; - -- /* Configure bus width to 16-bit */ - if (chip->options & NAND_BUSWIDTH_16) -- stm32_fmc2_set_buswidth_16(fmc2, true); -+ stm32_fmc2_nfc_set_buswidth_16(nfc, true); - -- /* Scan the device to fill MTD data-structures */ - ret = nand_scan_tail(mtd); - if (ret) - return ret; -@@ -1034,16 +1018,17 @@ static int stm32_fmc2_probe(struct udevice *dev) - return nand_register(0, mtd); - } - --static const struct udevice_id stm32_fmc2_match[] = { -+static const struct udevice_id stm32_fmc2_nfc_match[] = { - { .compatible = "st,stm32mp15-fmc2" }, -+ { .compatible = "st,stm32mp1-fmc2-nfc" }, - { /* Sentinel */ } - }; - --U_BOOT_DRIVER(stm32_fmc2_nand) = { -- .name = "stm32_fmc2_nand", -+U_BOOT_DRIVER(stm32_fmc2_nfc) = { -+ .name = "stm32_fmc2_nfc", - .id = UCLASS_MTD, -- .of_match = stm32_fmc2_match, -- .probe = stm32_fmc2_probe, -+ .of_match = stm32_fmc2_nfc_match, -+ .probe = stm32_fmc2_nfc_probe, - .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc), - }; - -@@ -1053,9 +1038,9 @@ void board_nand_init(void) - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, -- DM_GET_DRIVER(stm32_fmc2_nand), -+ DM_GET_DRIVER(stm32_fmc2_nfc), - &dev); - if (ret && ret != -ENODEV) -- pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n", -+ pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n", - ret); - } -diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c -index fad78100b7..bf416dd524 100644 ---- a/drivers/net/dwc_eth_qos.c -+++ b/drivers/net/dwc_eth_qos.c -@@ -1287,9 +1287,9 @@ static int eqos_start(struct udevice *dev) - struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); - rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + - (i * EQOS_MAX_PACKET_SIZE)); -- rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; -+ rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; -+ eqos->config->ops->eqos_flush_desc(rx_desc); - } -- eqos->config->ops->eqos_flush_desc(eqos->descs); - - writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); - writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); -@@ -1418,7 +1418,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length) - tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; - eqos->config->ops->eqos_flush_desc(tx_desc); - -- writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer); -+ writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), -+ &eqos->dma_regs->ch0_txdesc_tail_pointer); - - for (i = 0; i < 1000000; i++) { - eqos->config->ops->eqos_inval_desc(tx_desc); -@@ -1441,6 +1442,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) - debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); - - rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); -+ eqos->config->ops->eqos_inval_desc(rx_desc); - if (rx_desc->des3 & EQOS_DESC3_OWN) { - debug("%s: RX packet not available\n", __func__); - return -EAGAIN; -@@ -1473,6 +1475,11 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) - } - - rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); -+ -+ rx_desc->des0 = 0; -+ mb(); -+ eqos->config->ops->eqos_flush_desc(rx_desc); -+ eqos->config->ops->eqos_inval_buffer(packet, length); - rx_desc->des0 = (u32)(ulong)packet; - rx_desc->des1 = 0; - rx_desc->des2 = 0; -@@ -1481,7 +1488,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) - * writes to the rest of the descriptor too. - */ - mb(); -- rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; -+ rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; - eqos->config->ops->eqos_flush_desc(rx_desc); - - writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); -@@ -1535,6 +1542,9 @@ static int eqos_probe_resources_core(struct udevice *dev) - } - debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); - -+ eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, -+ EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX); -+ - debug("%s: OK\n", __func__); - return 0; - -diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c -index c12260842e..0fe39507a9 100644 ---- a/drivers/phy/phy-stm32-usbphyc.c -+++ b/drivers/phy/phy-stm32-usbphyc.c -@@ -56,6 +56,7 @@ struct stm32_usbphyc { - struct udevice *vdda1v8; - struct stm32_usbphyc_phy { - struct udevice *vdd; -+ struct udevice *vbus; - bool init; - bool powered; - } phys[MAX_PHYS]; -@@ -241,6 +242,11 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) - if (ret) - return ret; - } -+ if (usbphyc_phy->vbus) { -+ ret = regulator_set_enable(usbphyc_phy->vbus, true); -+ if (ret) -+ return ret; -+ } - - usbphyc_phy->powered = true; - -@@ -259,6 +265,11 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) - if (stm32_usbphyc_is_powered(usbphyc)) - return 0; - -+ if (usbphyc_phy->vbus) { -+ ret = regulator_set_enable(usbphyc_phy->vbus, false); -+ if (ret) -+ return ret; -+ } - if (usbphyc_phy->vdd) { - ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false); - if (ret) -@@ -268,7 +279,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) - return 0; - } - --static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, -+static int stm32_usbphyc_get_regulator(ofnode node, - char *supply_name, - struct udevice **regulator) - { -@@ -278,19 +289,14 @@ static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node, - ret = ofnode_parse_phandle_with_args(node, supply_name, - NULL, 0, 0, - ®ulator_phandle); -- if (ret) { -- dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret); -+ if (ret) - return ret; -- } - - ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, - regulator_phandle.node, - regulator); -- -- if (ret) { -- dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret); -+ if (ret) - return ret; -- } - - return 0; - } -@@ -377,10 +383,17 @@ static int stm32_usbphyc_probe(struct udevice *dev) - - usbphyc_phy->init = false; - usbphyc_phy->powered = false; -- ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply", -+ ret = stm32_usbphyc_get_regulator(node, "phy-supply", - &usbphyc_phy->vdd); -- if (ret) -+ if (ret) { -+ dev_err(dev, "Can't get phy-supply regulator\n"); - return ret; -+ } -+ -+ ret = stm32_usbphyc_get_regulator(node, "vbus-supply", -+ &usbphyc_phy->vbus); -+ if (ret) -+ usbphyc_phy->vbus = NULL; - - node = dev_read_next_subnode(node); - } -diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c -index cc7b429baa..b15c47b633 100644 ---- a/drivers/ram/stm32mp1/stm32mp1_tests.c -+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c -@@ -11,6 +11,8 @@ - - #define ADDR_INVALID 0xFFFFFFFF - -+#define PATTERN_DEFAULT "-" -+ - DECLARE_GLOBAL_DATA_PTR; - - static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, -@@ -29,9 +31,9 @@ static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, - argv[arg_nb], min_size); - return -1; - } -- if (value & 0x3) { -- sprintf(string, "unaligned size %s", -- argv[arg_nb]); -+ if (value & (min_size - 1)) { -+ sprintf(string, "unaligned size %s (min=%d)", -+ argv[arg_nb], min_size); - return -1; - } - *bufsize = value; -@@ -100,6 +102,10 @@ static int get_pattern(char *string, int argc, char *argv[], int arg_nb, - unsigned long value; - - if (argc > arg_nb) { -+ if (!strcmp(argv[arg_nb], PATTERN_DEFAULT)) { -+ *pattern = default_pattern; -+ return 0; -+ } - if (strict_strtoul(argv[arg_nb], 16, &value) < 0) { - sprintf(string, "invalid %d parameter %s", - arg_nb, argv[arg_nb]); -@@ -439,7 +445,7 @@ static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl, - u32 bufsize; - u32 error; - -- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) -+ if (get_bufsize(string, argc, argv, 0, &bufsize, STM32_DDR_SIZE, 4)) - return TEST_ERROR; - if (!is_power_of_2(bufsize)) { - sprintf(string, "size 0x%x is not a power of 2", -@@ -449,6 +455,7 @@ static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl, - if (get_addr(string, argc, argv, 1, &addr)) - return TEST_ERROR; - -+ printf("running at 0x%08x length 0x%x\n", addr, bufsize); - error = (u32)addressbus((u32 *)addr, bufsize); - if (error) { - sprintf(string, "0x%x: error for address 0x%x", -@@ -916,10 +923,12 @@ static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl, - enum test_result res = TEST_PASSED, pattern_res; - int i, bus_width; - const u32 **patterns; -- u32 bufsize; -+ u32 bufsize, addr; - - if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128)) - return TEST_ERROR; -+ if (get_addr(string, argc, argv, 1, &addr)) -+ return TEST_ERROR; - - switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { - case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: -@@ -932,15 +941,14 @@ static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl, - } - - printf("running test pattern at 0x%08x length 0x%x width = %d\n", -- STM32_DDR_BASE, bufsize, bus_width); -+ addr, bufsize, bus_width); - - patterns = - (const u32 **)(bus_width == 16 ? patterns_x16 : patterns_x32); - - for (i = 0; i < NB_PATTERN; i++) { - printf("test data pattern %s:", patterns_comments[i]); -- pattern_res = test_loop(patterns[i], (u32 *)STM32_DDR_BASE, -- bufsize); -+ pattern_res = test_loop(patterns[i], (u32 *)addr, bufsize); - if (pattern_res != TEST_PASSED) { - printf("Failed\n"); - return pattern_res; -@@ -1338,17 +1346,52 @@ static enum test_result test_all(struct stm32mp1_ddrctl *ctl, - char *string, int argc, char *argv[]) - { - enum test_result res = TEST_PASSED, result; -- int i, nb_error = 0; -+ int i, j, nb_error = 0, len; - u32 loop = 0, nb_loop; -+ int argc_test; -+ char *argv_test[4]; -+ char loop_string[] = "1"; -+ char pattern_string[] = PATTERN_DEFAULT; -+ u32 *addr; - - if (get_nb_loop(string, argc, argv, 0, &nb_loop, 1)) - return TEST_ERROR; - -+ if (get_addr(string, argc, argv, 2, (u32 *)&addr)) -+ return TEST_ERROR; -+ - while (!nb_error) { - /* execute all the test except the lasts which are infinite */ - for (i = 1; i < test_nb - NB_TEST_INFINITE; i++) { -+ argc_test = 0; -+ j = 0; -+ len = strlen(test[i].usage); -+ if (argc > 1 && j < len && -+ !strncmp("[size]", &test[i].usage[j], 6)) { -+ argv_test[argc_test++] = argv[1]; -+ j += 7; -+ } -+ if (argc > 2) { -+ if (j < len && -+ !strncmp("[loop]", &test[i].usage[j], 6)) { -+ argv_test[argc_test++] = loop_string; -+ j += 7; -+ } -+ if (j < len && -+ !strncmp("[pattern]", &test[i].usage[j], -+ 9)) { -+ argv_test[argc_test++] = pattern_string; -+ j += 10; -+ } -+ if (j < len && -+ !strncmp("[addr]", &test[i].usage[j], 6)) { -+ argv_test[argc_test++] = argv[2]; -+ j += 7; -+ } -+ } - printf("execute %d:%s\n", (int)i, test[i].name); -- result = test[i].fct(ctl, phy, string, 0, NULL); -+ result = test[i].fct(ctl, phy, string, -+ argc_test, argv_test); - printf("result %d:%s = ", (int)i, test[i].name); - if (result != TEST_PASSED) { - nb_error++; -@@ -1379,7 +1422,7 @@ static enum test_result test_all(struct stm32mp1_ddrctl *ctl, - ****************************************************************/ - - const struct test_desc test[] = { -- {test_all, "All", "[loop]", "Execute all tests", 1 }, -+ {test_all, "All", "[loop] [size] [addr]", "Execute all tests", 3 }, - {test_databus, "Simple DataBus", "[addr]", - "Verifies each data line by walking 1 on fixed address", - 1 -@@ -1416,9 +1459,9 @@ const struct test_desc test[] = { - "Verifies r/w and memcopy(burst for pseudo random value.", - 3 - }, -- {test_freq_pattern, "FrequencySelectivePattern", "[size]", -+ {test_freq_pattern, "FrequencySelectivePattern", "[size] [addr]", - "write & test patterns: Mostly Zero, Mostly One and F/n", -- 1 -+ 2 - }, - {test_blockseq, "BlockSequential", "[size] [loop] [addr]", - "test incremental pattern", -diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig -index 7c2e4804b5..3e1c9ed54f 100644 ---- a/drivers/remoteproc/Kconfig -+++ b/drivers/remoteproc/Kconfig -@@ -12,6 +12,14 @@ config REMOTEPROC - bool - depends on DM - -+config REMOTEPROC_OPTEE -+ bool "Support for the remoteproc in OPTEE" -+ depends on REMOTEPROC -+ depends on OPTEE -+ help -+ Say y here to support remote processor firmware management by the -+ trusted execution environment. -+ - # Please keep the configuration alphabetically sorted. - config K3_SYSTEM_CONTROLLER - bool "Support for TI' K3 System Controller" -diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile -index 69ae7bd1e8..d6c5f54fb7 100644 ---- a/drivers/remoteproc/Makefile -+++ b/drivers/remoteproc/Makefile -@@ -5,6 +5,7 @@ - # - - obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o -+obj-$(CONFIG_REMOTEPROC_OPTEE) += rproc-optee.o - - # Remote proc drivers - Please keep this list alphabetically sorted. - obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o -diff --git a/drivers/remoteproc/rproc-optee.c b/drivers/remoteproc/rproc-optee.c -new file mode 100644 -index 0000000000..8e9f51ada0 ---- /dev/null -+++ b/drivers/remoteproc/rproc-optee.c -@@ -0,0 +1,218 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved -+ * Authors: Arnaud Pouliquen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define TA_REMOTEPROC_UUID { 0x80a4c275, 0x0a47, 0x4905, \ -+ { 0x82, 0x85, 0x14, 0x86, 0xa9, 0x77, 0x1a, 0x08} } -+ -+/* The function IDs implemented in the associated TA */ -+ -+/* -+ * Authentication of the firmware and load in the remote processor memory. -+ * -+ * [in] params[0].value.a: unique 32bit identifier of the firmware -+ * [in] params[1].memref: buffer containing the image of the firmware -+ */ -+#define TA_RPROC_FW_CMD_LOAD_FW 1 -+ -+/* -+ * Start the remote processor. -+ * -+ * [in] params[0].value.a: unique 32bit identifier of the firmware -+ */ -+#define TA_RPROC_FW_CMD_START_FW 2 -+ -+/* -+ * Stop the remote processor. -+ * -+ * [in] params[0].value.a: unique 32bit identifier of the firmware -+ */ -+#define TA_RPROC_FW_CMD_STOP_FW 3 -+ -+/* -+ * Return the physical address of the resource table, or 0 if not found -+ * No check is done to verify that the address returned is accessible by the -+ * non secure world. If the resource table is loaded in a protected memory, -+ * then accesses from non-secure world will likely fail. -+ * -+ * [in] params[0].value.a: unique 32bit identifier of the firmware -+ * [out] params[1].value.a: 32bit LSB resource table memory address -+ * [out] params[1].value.b: 32bit MSB resource table memory address -+ * [out] params[2].value.a: 32bit LSB resource table memory size -+ * [out] params[2].value.b: 32bit MSB resource table memory size -+ */ -+#define TA_RPROC_FW_CMD_GET_RSC_TABLE 4 -+ -+/* -+ * Get remote processor firmware core dump. If found, return either -+ * TEE_SUCCESS on successful completion or TEE_ERROR_SHORT_BUFFER if output -+ * buffer is too short to store the core dump. -+ * -+ * [in] params[0].value.a: unique 32bit identifier of the firmware -+ * [out] params[1].memref: Core dump, if found -+ */ -+#define TA_RPROC_FW_CMD_GET_COREDUMP 5 -+ -+static void prepare_args(struct rproc_optee *trproc, int cmd, -+ struct tee_invoke_arg *arg, uint num_param, -+ struct tee_param *param) -+{ -+ memset(arg, 0, sizeof(*arg)); -+ memset(param, 0, num_param * sizeof(*param)); -+ -+ arg->func = cmd; -+ arg->session = trproc->session; -+ -+ param[0] = (struct tee_param) { -+ .attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT, -+ .u.value.a = trproc->fw_id, -+ }; -+} -+ -+int rproc_optee_load(struct rproc_optee *trproc, ulong addr, ulong size) -+{ -+ struct tee_invoke_arg arg; -+ struct tee_param param[2]; -+ struct tee_shm *fw_shm; -+ int rc; -+ -+ rc = tee_shm_register(trproc->tee, (void *)addr, size, 0, &fw_shm); -+ if (rc) -+ return rc; -+ -+ prepare_args(trproc, TA_RPROC_FW_CMD_LOAD_FW, &arg, 2, param); -+ -+ /* Provide the address and size of the firmware image */ -+ param[1] = (struct tee_param){ -+ .attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT, -+ .u.memref = { -+ .shm = fw_shm, -+ .size = size, -+ .shm_offs = 0, -+ }, -+ }; -+ -+ rc = tee_invoke_func(trproc->tee, &arg, 2, param); -+ if (rc < 0 || arg.ret != 0) { -+ dev_err(trproc->tee, -+ "TA_RPROC_FW_CMD_LOAD_FW invoke failed TEE err: %x, err:%x\n", -+ arg.ret, rc); -+ if (!rc) -+ rc = -EIO; -+ } -+ -+ tee_shm_free(fw_shm); -+ -+ return rc; -+} -+ -+int rproc_optee_get_rsc_table(struct rproc_optee *trproc, phys_addr_t *rsc_addr, -+ phys_size_t *rsc_size) -+{ -+ struct tee_invoke_arg arg; -+ struct tee_param param[3]; -+ int rc; -+ -+ prepare_args(trproc, TA_RPROC_FW_CMD_GET_RSC_TABLE, &arg, 3, param); -+ -+ param[1].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT; -+ param[2].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT; -+ -+ rc = tee_invoke_func(trproc->tee, &arg, 3, param); -+ if (rc < 0 || arg.ret != 0) { -+ dev_err(trproc->tee, -+ "TA_RPROC_FW_CMD_GET_RSC_TABLE invoke failed TEE err: %x, err:%x\n", -+ arg.ret, rc); -+ if (!rc) -+ rc = -EIO; -+ -+ return rc; -+ } -+ -+ *rsc_size = (phys_size_t) -+ (param[2].u.value.b << 32 | param[2].u.value.a); -+ *rsc_addr = (phys_addr_t) -+ (param[1].u.value.b << 32 | param[1].u.value.a); -+ -+ return 0; -+} -+ -+int rproc_optee_start(struct rproc_optee *trproc) -+{ -+ struct tee_invoke_arg arg; -+ struct tee_param param; -+ int rc; -+ -+ prepare_args(trproc, TA_RPROC_FW_CMD_START_FW, &arg, 1, ¶m); -+ -+ rc = tee_invoke_func(trproc->tee, &arg, 1, ¶m); -+ if (rc < 0 || arg.ret != 0) { -+ dev_err(trproc->tee, -+ "TA_RPROC_FW_CMD_START_FW invoke failed TEE err: %x, err:%x\n", -+ arg.ret, rc); -+ if (!rc) -+ rc = -EIO; -+ } -+ -+ return rc; -+} -+ -+int rproc_optee_stop(struct rproc_optee *trproc) -+{ -+ struct tee_invoke_arg arg; -+ struct tee_param param; -+ int rc; -+ -+ prepare_args(trproc, TA_RPROC_FW_CMD_STOP_FW, &arg, 1, ¶m); -+ -+ rc = tee_invoke_func(trproc->tee, &arg, 1, ¶m); -+ if (rc < 0 || arg.ret != 0) { -+ dev_err(trproc->tee, -+ "TA_RPROC_FW_CMD_STOP_FW invoke failed TEE err: %x, err:%x\n", -+ arg.ret, rc); -+ if (!rc) -+ rc = -EIO; -+ } -+ -+ return rc; -+} -+ -+int rproc_optee_open(struct rproc_optee *trproc) -+{ -+ struct udevice *tee = NULL; -+ const struct tee_optee_ta_uuid uuid = TA_REMOTEPROC_UUID; -+ struct tee_open_session_arg arg = { }; -+ int rc; -+ -+ if (!trproc) -+ return -EINVAL; -+ -+ tee = tee_find_device(tee, NULL, NULL, NULL); -+ if (!tee) -+ return -ENODEV; -+ -+ tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); -+ rc = tee_open_session(tee, &arg, 0, NULL); -+ if (!rc) { -+ trproc->tee = tee; -+ trproc->session = arg.session; -+ } -+ -+ return 0; -+} -+ -+int rproc_optee_close(struct rproc_optee *trproc) -+{ -+ if (!trproc->tee) -+ return -ENODEV; -+ -+ return tee_close_session(trproc->tee, trproc->session); -+} -diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c -index b8e62e52eb..35ac4a7eab 100644 ---- a/drivers/remoteproc/stm32_copro.c -+++ b/drivers/remoteproc/stm32_copro.c -@@ -7,31 +7,22 @@ - #include - #include - #include --#include - #include -+#include - #include --#include - #include --#include - --#define RCC_GCR_HOLD_BOOT 0 --#define RCC_GCR_RELEASE_BOOT 1 -+#define STM32MP15_M4_FW_ID 0 - - /** - * struct stm32_copro_privdata - power processor private data - * @reset_ctl: reset controller handle -- * @hold_boot_regmap: regmap for remote processor reset hold boot -- * @hold_boot_offset: offset of the register controlling the hold boot setting -- * @hold_boot_mask: bitmask of the register for the hold boot field -- * @secured_soc: TZEN flag (register protection) -+ * @hold_boot: hold boot controller handle - * @rsc_table_addr: resource table address - */ - struct stm32_copro_privdata { - struct reset_ctl reset_ctl; -- struct regmap *hold_boot_regmap; -- uint hold_boot_offset; -- uint hold_boot_mask; -- bool secured_soc; -+ struct reset_ctl hold_boot; - ulong rsc_table_addr; - }; - -@@ -43,98 +34,51 @@ struct stm32_copro_privdata { - static int stm32_copro_probe(struct udevice *dev) - { - struct stm32_copro_privdata *priv; -- struct regmap *regmap; -- const fdt32_t *cell; -- uint tz_offset, tz_mask, tzen; -- int len, ret; -+ int ret; - - priv = dev_get_priv(dev); - -- regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-holdboot"); -- if (IS_ERR(regmap)) { -- dev_err(dev, "unable to find holdboot regmap (%ld)\n", -- PTR_ERR(regmap)); -- return PTR_ERR(regmap); -- } -- -- cell = dev_read_prop(dev, "st,syscfg-holdboot", &len); -- if (len < 3 * sizeof(fdt32_t)) { -- dev_err(dev, "holdboot offset and mask not available\n"); -- return -EINVAL; -- } -- -- priv->hold_boot_regmap = regmap; -- priv->hold_boot_offset = fdtdec_get_number(cell + 1, 1); -- priv->hold_boot_mask = fdtdec_get_number(cell + 2, 1); -- -- ret = reset_get_by_index(dev, 0, &priv->reset_ctl); -+ ret = reset_get_by_name(dev, "mcu_rst", &priv->reset_ctl); - if (ret) { - dev_err(dev, "failed to get reset (%d)\n", ret); - return ret; - } - -- regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-tz"); -- if (IS_ERR(regmap)) { -- dev_dbg(dev, "unable to find tz regmap (%ld)\n", -- PTR_ERR(regmap)); -- return -EINVAL; -- } -- -- cell = dev_read_prop(dev, "st,syscfg-tz", &len); -- if (3 * sizeof(fdt32_t) - len > 0) { -- dev_dbg(dev, "tz offset and mask not available\n"); -- return -EINVAL; -- } -- -- tz_offset = fdtdec_get_number(cell + 1, 1); -- -- tz_mask = fdtdec_get_number(cell + 2, 1); -- -- ret = regmap_read(regmap, tz_offset, &tzen); -+ ret = reset_get_by_name(dev, "hold_boot", &priv->hold_boot); - if (ret) { -- dev_dbg(dev, "failed to read soc secure state\n"); -+ dev_err(dev, "failed to get hold boot (%d)\n", ret); - return ret; - } - -- priv->secured_soc = !!(tzen & tz_mask); -- - dev_dbg(dev, "probed\n"); - - return 0; - } - - /** -- * stm32_copro_set_hold_boot() - Hold boot bit management -+ * stm32_copro_optee_probe() - Open a session toward rproc trusted application - * @dev: corresponding STM32 remote processor device -- * @hold: hold boot value - * @return 0 if all went ok, else corresponding -ve error - */ --static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold) -+static int stm32_copro_optee_probe(struct udevice *dev) - { -- struct stm32_copro_privdata *priv; -- uint val; -- int ret; -+ struct rproc_optee *trproc = dev_get_priv(dev); - -- priv = dev_get_priv(dev); -- -- val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT; -+ trproc->fw_id = (u32)dev_get_driver_data(dev); - -- if (priv->secured_soc) { -- return stm32_smc_exec(STM32_SMC_RCC, STM32_SMC_REG_WRITE, -- priv->hold_boot_offset, val); -- } -+ return rproc_optee_open(trproc); -+} - -- /* -- * Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured. -- * To be updated when the code for this SMC service is available which -- * is not the case for the time being. -- */ -- ret = regmap_update_bits(priv->hold_boot_regmap, priv->hold_boot_offset, -- priv->hold_boot_mask, val); -- if (ret) -- dev_err(dev, "failed to set hold boot\n"); -+/** -+ * stm32_copro_optee_remove() - Close the rproc trusted application session -+ * @dev: corresponding STM32 remote processor device -+ * @return 0 if all went ok, else corresponding -ve error -+ */ -+static int stm32_copro_optee_remove(struct udevice *dev) -+{ -+ struct rproc_optee *trproc = dev_get_priv(dev); - -- return ret; -+ return rproc_optee_close(trproc); - } - - /** -@@ -180,9 +124,11 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) - - priv = dev_get_priv(dev); - -- ret = stm32_copro_set_hold_boot(dev, true); -- if (ret) -+ ret = reset_assert(&priv->hold_boot); -+ if (ret) { -+ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); - return ret; -+ } - - ret = reset_assert(&priv->reset_ctl); - if (ret) { -@@ -199,6 +145,18 @@ static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size) - return rproc_elf32_load_image(dev, addr, size); - } - -+/** -+ * stm32_copro_optee_load() - Request OP−TEE to load the remote processor firmware -+ * @dev: corresponding OP-TEE remote processor device -+ * @return 0 if all went ok, else corresponding -ve error -+ */ -+static int stm32_copro_optee_load(struct udevice *dev, ulong addr, ulong size) -+{ -+ struct rproc_optee *trproc = dev_get_priv(dev); -+ -+ return rproc_optee_load(trproc, addr, size); -+} -+ - /** - * stm32_copro_start() - Start the STM32 remote processor - * @dev: corresponding STM32 remote processor device -@@ -211,23 +169,54 @@ static int stm32_copro_start(struct udevice *dev) - - priv = dev_get_priv(dev); - -- /* move hold boot from true to false start the copro */ -- ret = stm32_copro_set_hold_boot(dev, false); -- if (ret) -+ ret = reset_deassert(&priv->hold_boot); -+ if (ret) { -+ dev_err(dev, "Unable to deassert hold boot (ret=%d)\n", ret); - return ret; -+ } - - /* - * Once copro running, reset hold boot flag to avoid copro -- * rebooting autonomously -+ * rebooting autonomously (error should never occur) - */ -- ret = stm32_copro_set_hold_boot(dev, true); -- writel(ret ? TAMP_COPRO_STATE_OFF : TAMP_COPRO_STATE_CRUN, -- TAMP_COPRO_STATE); -- if (!ret) -- /* Store rsc_address in bkp register */ -- writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); -- -- return ret; -+ ret = reset_assert(&priv->hold_boot); -+ if (ret) -+ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); -+ -+ /* indicates that copro is running */ -+ writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE); -+ /* Store rsc_address in bkp register */ -+ writel(priv->rsc_table_addr, TAMP_COPRO_RSC_TBL_ADDRESS); -+ -+ return 0; -+} -+ -+/** -+ * stm32_copro_optee_start() - Request OP−TEE to start the STM32 remote processor -+ * @dev: corresponding OP-TEE remote processor device -+ * @return 0 if all went ok, else corresponding -ve error -+ */ -+static int stm32_copro_optee_start(struct udevice *dev) -+{ -+ struct rproc_optee *trproc = dev_get_priv(dev); -+ phys_addr_t rsc_addr; -+ phys_size_t rsc_size; -+ int ret; -+ -+ ret = rproc_optee_get_rsc_table(trproc, &rsc_addr, &rsc_size); -+ if (ret) -+ return ret; -+ -+ ret = rproc_optee_start(trproc); -+ if (ret) -+ return ret; -+ -+ /* indicates that copro is running */ -+ writel(TAMP_COPRO_STATE_CRUN, TAMP_COPRO_STATE); -+ /* Store rsc_address in bkp register */ -+ writel(rsc_addr, TAMP_COPRO_RSC_TBL_ADDRESS); -+ -+ return 0; - } - - /** -@@ -242,9 +231,11 @@ static int stm32_copro_reset(struct udevice *dev) - - priv = dev_get_priv(dev); - -- ret = stm32_copro_set_hold_boot(dev, true); -- if (ret) -+ ret = reset_assert(&priv->hold_boot); -+ if (ret) { -+ dev_err(dev, "Unable to assert hold boot (ret=%d)\n", ret); - return ret; -+ } - - ret = reset_assert(&priv->reset_ctl); - if (ret) { -@@ -267,6 +258,35 @@ static int stm32_copro_stop(struct udevice *dev) - return stm32_copro_reset(dev); - } - -+/** -+ * stm32_copro_optee_reset() - Request OP−TEE to reset the STM32 remote processor -+ * @dev: corresponding STM32 remote processor device -+ * @return 0 if all went ok, else corresponding -ve error -+ */ -+static int stm32_copro_optee_reset(struct udevice *dev) -+{ -+ struct rproc_optee *trproc = dev_get_priv(dev); -+ int ret; -+ -+ ret = rproc_optee_stop(trproc); -+ if (ret) -+ return ret; -+ -+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); -+ -+ return 0; -+} -+ -+/** -+ * stm32_copro_optee_stop() - Request OP−TEE to stop the STM32 remote processor -+ * @dev: corresponding STM32 remote processor device -+ * @return 0 if all went ok, else corresponding -ve error -+ */ -+static int stm32_copro_optee_stop(struct udevice *dev) -+{ -+ return stm32_copro_optee_reset(dev); -+} -+ - /** - * stm32_copro_is_running() - Is the STM32 remote processor running - * @dev: corresponding STM32 remote processor device -@@ -299,3 +319,28 @@ U_BOOT_DRIVER(stm32_copro) = { - .probe = stm32_copro_probe, - .priv_auto_alloc_size = sizeof(struct stm32_copro_privdata), - }; -+ -+static const struct dm_rproc_ops stm32_copro_optee_ops = { -+ .load = stm32_copro_optee_load, -+ .start = stm32_copro_optee_start, -+ .stop = stm32_copro_optee_stop, -+ .reset = stm32_copro_optee_reset, -+ .is_running = stm32_copro_is_running, -+ .device_to_virt = stm32_copro_device_to_virt, -+}; -+ -+static const struct udevice_id stm32_copro_optee_ids[] = { -+ { .compatible = "st,stm32mp1-m4_optee", .data = STM32MP15_M4_FW_ID }, -+ {} -+}; -+ -+U_BOOT_DRIVER(stm32_copro_optee) = { -+ .name = "stm32_m4_proc_optee", -+ .of_match = stm32_copro_optee_ids, -+ .id = UCLASS_REMOTEPROC, -+ .ops = &stm32_copro_optee_ops, -+ .probe = stm32_copro_optee_probe, -+ .remove = stm32_copro_optee_remove, -+ .priv_auto_alloc_size = sizeof(struct rproc_optee), -+ .flags = DM_FLAG_OS_PREPARE, -+}; -diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c -index 16d3dba749..bb481d3ee3 100644 ---- a/drivers/reset/stm32-reset.c -+++ b/drivers/reset/stm32-reset.c -@@ -11,6 +11,9 @@ - #include - #include - -+/* offset of register without set/clear management */ -+#define RCC_MP_GCR_OFFSET 0x10C -+ - /* reset clear offset for STM32MP RCC */ - #define RCC_CL 0x4 - -@@ -37,8 +40,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) - reset_ctl->id, bank, offset); - - if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) -- /* reset assert is done in rcc set register */ -- writel(BIT(offset), priv->base + bank); -+ if (bank != RCC_MP_GCR_OFFSET) -+ /* reset assert is done in rcc set register */ -+ writel(BIT(offset), priv->base + bank); -+ else -+ clrbits_le32(priv->base + bank, BIT(offset)); - else - setbits_le32(priv->base + bank, BIT(offset)); - -@@ -54,8 +60,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) - reset_ctl->id, bank, offset); - - if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) -- /* reset deassert is done in rcc clr register */ -- writel(BIT(offset), priv->base + bank + RCC_CL); -+ if (bank != RCC_MP_GCR_OFFSET) -+ /* reset deassert is done in rcc clr register */ -+ writel(BIT(offset), priv->base + bank + RCC_CL); -+ else -+ setbits_le32(priv->base + bank, BIT(offset)); - else - clrbits_le32(priv->base + bank, BIT(offset)); - -diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c -index 35495e41fc..554bf2bd8d 100644 ---- a/drivers/usb/gadget/dwc2_udc_otg.c -+++ b/drivers/usb/gadget/dwc2_udc_otg.c -@@ -1068,6 +1068,9 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) - platdata->force_b_session_valid = - dev_read_bool(dev, "u-boot,force-b-session-valid"); - -+ platdata->force_vbus_detection = -+ dev_read_bool(dev, "u-boot,force-vbus-detection"); -+ - /* force platdata according compatible */ - drvdata = dev_get_driver_data(dev); - if (drvdata) { -@@ -1160,31 +1163,45 @@ static int dwc2_udc_otg_probe(struct udevice *dev) - if (ret) - return ret; - -- if (CONFIG_IS_ENABLED(DM_REGULATOR) && -- platdata->activate_stm_id_vb_detection && -- !platdata->force_b_session_valid) { -- ret = device_get_supply_regulator(dev, "usb33d-supply", -- &priv->usb33d_supply); -- if (ret) { -- dev_err(dev, "can't get voltage level detector supply\n"); -- return ret; -+ if (platdata->activate_stm_id_vb_detection) { -+ if (CONFIG_IS_ENABLED(DM_REGULATOR) && -+ (!platdata->force_b_session_valid || -+ platdata->force_vbus_detection)) { -+ ret = device_get_supply_regulator(dev, "usb33d-supply", -+ &priv->usb33d_supply); -+ if (ret) { -+ dev_err(dev, "can't get voltage level detector supply\n"); -+ return ret; -+ } -+ ret = regulator_set_enable(priv->usb33d_supply, true); -+ if (ret) { -+ dev_err(dev, "can't enable voltage level detector supply\n"); -+ return ret; -+ } - } -- ret = regulator_set_enable(priv->usb33d_supply, true); -- if (ret) { -- dev_err(dev, "can't enable voltage level detector supply\n"); -- return ret; -+ -+ if (platdata->force_b_session_valid && -+ !platdata->force_vbus_detection) { -+ /* Override VBUS detection: enable then value*/ -+ setbits_le32(&usbotg_reg->gotgctl, VB_VALOEN); -+ setbits_le32(&usbotg_reg->gotgctl, VB_VALOVAL); -+ } else { -+ /* Enable VBUS sensing */ -+ setbits_le32(&usbotg_reg->ggpio, -+ GGPIO_STM32_OTG_GCCFG_VBDEN); -+ } -+ if (platdata->force_b_session_valid) { -+ /* Override B session bits: enable then value */ -+ setbits_le32(&usbotg_reg->gotgctl, A_VALOEN | B_VALOEN); -+ setbits_le32(&usbotg_reg->gotgctl, -+ A_VALOVAL | B_VALOVAL); -+ } else { -+ /* Enable ID detection */ -+ setbits_le32(&usbotg_reg->ggpio, -+ GGPIO_STM32_OTG_GCCFG_IDEN); - } -- /* Enable vbus sensing */ -- setbits_le32(&usbotg_reg->ggpio, -- GGPIO_STM32_OTG_GCCFG_VBDEN | -- GGPIO_STM32_OTG_GCCFG_IDEN); - } - -- if (platdata->force_b_session_valid) -- /* Override B session bits : value and enable */ -- setbits_le32(&usbotg_reg->gotgctl, -- A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL); -- - ret = dwc2_udc_probe(platdata); - if (ret) - return ret; -diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h -index 434db5ba39..a4f7d54368 100644 ---- a/drivers/usb/gadget/dwc2_udc_otg_regs.h -+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h -@@ -93,6 +93,8 @@ struct dwc2_usbotg_reg { - #define B_VALOEN BIT(6) - #define A_VALOVAL BIT(5) - #define A_VALOEN BIT(4) -+#define VB_VALOVAL BIT(3) -+#define VB_VALOEN BIT(2) - - /* DWC2_UDC_OTG_GOTINT */ - #define GOTGINT_SES_END_DET (1<<2) -diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h -index b875f9b132..af5b92443e 100644 ---- a/include/configs/grpeach.h -+++ b/include/configs/grpeach.h -@@ -16,7 +16,6 @@ - - /* Miscellaneous */ - #define CONFIG_SYS_PBSIZE 256 --#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - #define CONFIG_CMDLINE_TAG - - /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h -index e25800a095..2632d48cc9 100644 ---- a/include/configs/pxa-common.h -+++ b/include/configs/pxa-common.h -@@ -8,8 +8,6 @@ - #ifndef __CONFIG_PXA_COMMON_H__ - #define __CONFIG_PXA_COMMON_H__ - --#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH -- - /* - * KGDB - */ -diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h -index 7b4fe484d3..becca68a78 100644 ---- a/include/configs/stm32mp1.h -+++ b/include/configs/stm32mp1.h -@@ -168,7 +168,7 @@ - - #define STM32MP_ANDROID \ - "suffix=a\0" \ -- "dtimg_addr=0xc4500000\0" \ -+ "dtimg_addr=0xc44FFF80\0" \ - "android_mmc_splash="\ - "if part start mmc ${devnum} splash splash_start && " \ - "part size mmc ${devnum} splash splash_size;"\ -@@ -186,22 +186,20 @@ - "dtimg start ${dtimg_addr} ${dt_index} fdt_addr_r;"\ - "fi\0" \ - "android_mmc_kernel="\ -- "if part start mmc ${devnum} boot_${suffix} boot_start &&" \ -+ "if part start mmc ${devnum} boot_${suffix} boot_start && " \ - "part size mmc ${devnum} boot_${suffix} boot_size;"\ - "then " \ - "mmc read ${kernel_addr_r} ${boot_start} ${boot_size};" \ -- "part nb mmc ${devnum} system_${suffix} rootpart_nb;" \ -- "env set bootargs" \ -- "root=/dev/mmcblk${devnum}p${rootpart_nb} " \ -+ "env set bootargs ${android_bootargs} " \ - "androidboot.serialno=${serial#} " \ -- "androidboot.slot_suffix=_${suffix};"\ -+ "androidboot.slot_suffix=_${suffix};" \ - "fi\0" \ - "android_mmc_boot="\ - "mmc dev ${devnum};"\ - "run android_mmc_splash;" \ - "run android_mmc_fdt;" \ - "run android_mmc_kernel;" \ -- "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \ -+ "bootm ${kernel_addr_r} ${kernel_addr_r} ${fdt_addr_r};\0" \ - "bootcmd_android=" \ - "env set mmc_boot run android_mmc_boot;" \ - "run bootcmd_stm32mp\0" -diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h -index bc71924faa..f3a0ed3178 100644 ---- a/include/dt-bindings/reset/stm32mp1-resets.h -+++ b/include/dt-bindings/reset/stm32mp1-resets.h -@@ -7,6 +7,7 @@ - #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ - #define _DT_BINDINGS_STM32MP1_RESET_H_ - -+#define MCU_HOLD_BOOT_R 2144 - #define LTDC_R 3072 - #define DSI_R 3076 - #define DDRPERFM_R 3080 -@@ -117,5 +118,6 @@ - #define RST_SCMI0_RNG1 8 - #define RST_SCMI0_MDMA 9 - #define RST_SCMI0_MCU 10 -+#define RST_SCMI0_MCU_HOLD_BOOT 11 - - #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ -diff --git a/include/fdtdec.h b/include/fdtdec.h -index 696e0fd024..a6446aa624 100644 ---- a/include/fdtdec.h -+++ b/include/fdtdec.h -@@ -1035,7 +1035,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) - * }; - * uint32_t phandle; - * -- * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); -+ * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); - * - * This results in the following subnode being added to the top-level - * /reserved-memory node: -@@ -1062,11 +1062,12 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) - * @param carveout information about the carveout region - * @param phandlep return location for the phandle of the carveout region - * can be NULL if no phandle should be added -+ * @param no_map add "no-map" property if true - * @return 0 on success or a negative error code on failure - */ - int fdtdec_add_reserved_memory(void *blob, const char *basename, - const struct fdt_memory *carveout, -- uint32_t *phandlep); -+ uint32_t *phandlep, bool no_map); - - /** - * fdtdec_get_carveout() - reads a carveout from an FDT -diff --git a/include/lmb.h b/include/lmb.h -index 3b338dfee0..dab635030d 100644 ---- a/include/lmb.h -+++ b/include/lmb.h -@@ -14,9 +14,20 @@ - - #define MAX_LMB_REGIONS 8 - -+/** -+ * enum lmb_flags - definition of memory region attributes -+ * @LMB_NONE: no special request -+ * @LMB_NOMAP: don't add to mmu configuration -+ */ -+enum lmb_flags { -+ LMB_NONE = 0x0, /* No special request */ -+ LMB_NOMAP = 0x4, /* don't add to mmu config */ -+}; -+ - struct lmb_property { - phys_addr_t base; - phys_size_t size; -+ enum lmb_flags flags; - }; - - struct lmb_region { -@@ -36,6 +47,8 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, - phys_size_t size, void *fdt_blob); - extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); - extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); -+extern long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, -+ phys_size_t size, enum lmb_flags flags); - extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); - extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, - phys_addr_t max_addr); -@@ -45,6 +58,7 @@ extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, - phys_size_t size); - extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); - extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); -+extern int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); - extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); - - extern void lmb_dump_all(struct lmb *lmb); -@@ -58,6 +72,13 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) - void board_lmb_reserve(struct lmb *lmb); - void arch_lmb_reserve(struct lmb *lmb); - -+/* Low level functions */ -+ -+static inline bool lmb_is_nomap(struct lmb_property *m) -+{ -+ return !!(m->flags & LMB_NOMAP); -+} -+ - #endif /* __KERNEL__ */ - - #endif /* _LINUX_LMB_H */ -diff --git a/include/rproc_optee.h b/include/rproc_optee.h -new file mode 100644 -index 0000000000..13193bbe77 ---- /dev/null -+++ b/include/rproc_optee.h -@@ -0,0 +1,127 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved -+ */ -+ -+#ifndef _RPROC_OPTEE_H_ -+#define _RPROC_OPTEE_H_ -+ -+/** -+ * struct rproc_optee - TEE remoteproc structure -+ * @tee: TEE device -+ * @fw_id: Identifier of the target firmware -+ * @session: TEE session identifier -+ */ -+struct rproc_optee { -+ struct udevice *tee; -+ u32 fw_id; -+ u32 session; -+}; -+ -+#if IS_ENABLED(CONFIG_REMOTEPROC_OPTEE) -+ -+/** -+ * rproc_optee_open() - open a rproc tee session -+ * -+ * Open a session towards the trusted application in charge of the remote -+ * processor. -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * -+ * @return 0 if the session is opened, or an appropriate error value. -+ */ -+int rproc_optee_open(struct rproc_optee *trproc); -+ -+/** -+ * rproc_optee_close() - close a rproc tee session -+ * -+ * Close the trusted application session in charge of the remote processor. -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * -+ * @return 0 on success, or an appropriate error value. -+ */ -+int rproc_optee_close(struct rproc_optee *trproc); -+ -+/** -+ * rproc_optee_start() - Request OP-TEE to start a remote processor -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * -+ * @return 0 on success, or an appropriate error value. -+ */ -+int rproc_optee_start(struct rproc_optee *trproc); -+ -+/** -+ * rproc_optee_stop() - Request OP-TEE to stop a remote processor -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * -+ * @return 0 on success, or an appropriate error value. -+ */ -+int rproc_optee_stop(struct rproc_optee *trproc); -+ -+/** -+ * rproc_optee_get_rsc_table() - Request OP-TEE the resource table -+ * -+ * Get the address and the size of the resource table. If no resource table is -+ * found, the size and address are null. -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * @rsc_addr: out the physical address of the resource table returned -+ * @rsc_size: out the size of the resource table -+ * -+ * @return 0 on success, or an appropriate error value. -+ */ -+int rproc_optee_get_rsc_table(struct rproc_optee *trproc, phys_addr_t *rsc_addr, -+ phys_size_t *rsc_size); -+ -+/** -+ * rproc_optee_load() - load an signed ELF image -+ * -+ * @trproc: OPTEE remoteproc context structure -+ * @addr: valid ELF image address -+ * @size: size of the image -+ * -+ * @return 0 if the image is successfully loaded, else appropriate error value. -+ */ -+int rproc_optee_load(struct rproc_optee *trproc, ulong addr, ulong size); -+ -+#else -+ -+static inline int rproc_optee_open(struct rproc_optee *trproc) -+{ -+ return -ENOSYS; -+} -+ -+static inline int rproc_optee_close(struct rproc_optee *trproc) -+{ -+ return -ENOSYS; -+} -+ -+static inline int rproc_optee_start(struct rproc_optee *trproc) -+{ -+ return -ENOSYS; -+} -+ -+static inline int rproc_optee_stop(struct rproc_optee *trproc) -+{ -+ return -ENOSYS; -+} -+ -+static inline int rproc_optee_get_rsc_table(struct rproc_optee *trproc, -+ phys_addr_t *rsc_addr, -+ phys_size_t *rsc_size) -+{ -+ return -ENOSYS; -+} -+ -+static inline int rproc_optee_load(struct rproc_optee *trproc, ulong addr, -+ ulong size) -+{ -+ return -ENOSYS; -+} -+ -+#endif -+ -+#endif /* _RPROC_OPTEE_H_ */ -diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h -index a2af381a66..aa37e957b4 100644 ---- a/include/usb/dwc2_udc.h -+++ b/include/usb/dwc2_udc.h -@@ -28,6 +28,7 @@ struct dwc2_plat_otg_data { - unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS]; - unsigned char tx_fifo_sz_nb; - bool force_b_session_valid; -+ bool force_vbus_detection; - bool activate_stm_id_vb_detection; - }; - -diff --git a/lib/fdtdec.c b/lib/fdtdec.c -index 61af3472e6..63df8e1ba1 100644 ---- a/lib/fdtdec.c -+++ b/lib/fdtdec.c -@@ -1272,7 +1272,7 @@ static int fdtdec_init_reserved_memory(void *blob) - - int fdtdec_add_reserved_memory(void *blob, const char *basename, - const struct fdt_memory *carveout, -- uint32_t *phandlep) -+ uint32_t *phandlep, bool no_map) - { - fdt32_t cells[4] = {}, *ptr = cells; - uint32_t upper, lower, phandle; -@@ -1369,6 +1369,12 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, - if (err < 0) - return err; - -+ if (no_map) { -+ err = fdt_setprop(blob, node, "no-map", NULL, 0); -+ if (err < 0) -+ return err; -+ } -+ - /* return the phandle for the new node for the caller to use */ - if (phandlep) - *phandlep = phandle; -@@ -1439,7 +1445,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, - return -FDT_ERR_BADOFFSET; - } - -- err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle); -+ err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false); - if (err < 0) { - debug("failed to add reserved memory: %d\n", err); - return err; -diff --git a/lib/lmb.c b/lib/lmb.c -index b3b84e4d37..2f15610419 100644 ---- a/lib/lmb.c -+++ b/lib/lmb.c -@@ -25,6 +25,8 @@ void lmb_dump_all(struct lmb *lmb) - (unsigned long long)lmb->memory.region[i].base); - debug(" .size = 0x%llx\n", - (unsigned long long)lmb->memory.region[i].size); -+ debug(" .flags = 0x%x\n", -+ lmb->memory.region[i].flags); - } - - debug("\n reserved.cnt = 0x%lx\n", -@@ -36,6 +38,8 @@ void lmb_dump_all(struct lmb *lmb) - (unsigned long long)lmb->reserved.region[i].base); - debug(" .size = 0x%llx\n", - (unsigned long long)lmb->reserved.region[i].size); -+ debug(" .flags = 0x%x\n", -+ lmb->reserved.region[i].flags); - } - #endif /* DEBUG */ - } -@@ -78,6 +82,7 @@ static void lmb_remove_region(struct lmb_region *rgn, unsigned long r) - for (i = r; i < rgn->cnt - 1; i++) { - rgn->region[i].base = rgn->region[i + 1].base; - rgn->region[i].size = rgn->region[i + 1].size; -+ rgn->region[i].flags = rgn->region[i + 1].flags; - } - rgn->cnt--; - } -@@ -139,7 +144,8 @@ void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, - } - - /* This routine called with relocation disabled. */ --static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) -+static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, -+ phys_size_t size, enum lmb_flags flags) - { - unsigned long coalesced = 0; - long adjacent, i; -@@ -147,6 +153,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - if (rgn->cnt == 0) { - rgn->region[0].base = base; - rgn->region[0].size = size; -+ rgn->region[0].flags = flags; - rgn->cnt = 1; - return 0; - } -@@ -155,18 +162,27 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - for (i = 0; i < rgn->cnt; i++) { - phys_addr_t rgnbase = rgn->region[i].base; - phys_size_t rgnsize = rgn->region[i].size; -+ phys_size_t rgnflags = rgn->region[i].flags; - -- if ((rgnbase == base) && (rgnsize == size)) -- /* Already have this region, so we're done */ -- return 0; -+ if (rgnbase == base && rgnsize == size) { -+ if (flags == rgnflags) -+ /* Already have this region, so we're done */ -+ return 0; -+ else -+ return -1; /* regions with new flags */ -+ } - - adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); - if (adjacent > 0) { -+ if (flags != rgnflags) -+ break; - rgn->region[i].base -= size; - rgn->region[i].size += size; - coalesced++; - break; - } else if (adjacent < 0) { -+ if (flags != rgnflags) -+ break; - rgn->region[i].size += size; - coalesced++; - break; -@@ -177,8 +193,10 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - } - - if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) { -- lmb_coalesce_regions(rgn, i, i + 1); -- coalesced++; -+ if (rgn->region[i].flags == rgn->region[i + 1].flags) { -+ lmb_coalesce_regions(rgn, i, i + 1); -+ coalesced++; -+ } - } - - if (coalesced) -@@ -191,9 +209,11 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - if (base < rgn->region[i].base) { - rgn->region[i + 1].base = rgn->region[i].base; - rgn->region[i + 1].size = rgn->region[i].size; -+ rgn->region[i + 1].flags = rgn->region[i].flags; - } else { - rgn->region[i + 1].base = base; - rgn->region[i + 1].size = size; -+ rgn->region[i + 1].flags = flags; - break; - } - } -@@ -201,6 +221,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - if (base < rgn->region[0].base) { - rgn->region[0].base = base; - rgn->region[0].size = size; -+ rgn->region[0].flags = flags; - } - - rgn->cnt++; -@@ -208,6 +229,12 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t - return 0; - } - -+static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, -+ phys_size_t size) -+{ -+ return lmb_add_region_flags(rgn, base, size, LMB_NONE); -+} -+ - /* This routine may be called with relocation disabled. */ - long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) - { -@@ -262,14 +289,21 @@ long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) - * beginging of the hole and add the region after hole. - */ - rgn->region[i].size = base - rgn->region[i].base; -- return lmb_add_region(rgn, end + 1, rgnend - end); -+ return lmb_add_region_flags(rgn, end + 1, rgnend - end, -+ rgn->region[i].flags); - } - --long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) -+long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size, -+ enum lmb_flags flags) - { - struct lmb_region *_rgn = &(lmb->reserved); - -- return lmb_add_region(_rgn, base, size); -+ return lmb_add_region_flags(_rgn, base, size, flags); -+} -+ -+long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) -+{ -+ return lmb_reserve_flags(lmb, base, size, LMB_NONE); - } - - static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, -@@ -404,7 +438,7 @@ phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr) - return 0; - } - --int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) -+int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags) - { - int i; - -@@ -412,11 +446,17 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) - phys_addr_t upper = lmb->reserved.region[i].base + - lmb->reserved.region[i].size - 1; - if ((addr >= lmb->reserved.region[i].base) && (addr <= upper)) -- return 1; -+ return !!((lmb->reserved.region[i].flags & flags) -+ == flags); - } - return 0; - } - -+int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) -+{ -+ return lmb_is_reserved_flags(lmb, addr, LMB_NONE); -+} -+ - __weak void board_lmb_reserve(struct lmb *lmb) - { - /* please define platform specific board_lmb_reserve() */ -diff --git a/lib/optee/optee.c b/lib/optee/optee.c -index 79b058a17a..5aa99964aa 100644 ---- a/lib/optee/optee.c -+++ b/lib/optee/optee.c -@@ -154,8 +154,9 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) - /* optee inserts its memory regions as reserved-memory nodes */ - nodeoffset = fdt_subnode_offset(old_blob, 0, "reserved-memory"); - if (nodeoffset >= 0) { -- subnode = fdt_first_subnode(old_blob, nodeoffset); -- while (subnode >= 0) { -+ for (subnode = fdt_first_subnode(old_blob, nodeoffset); -+ subnode >= 0; -+ subnode = fdt_next_subnode(old_blob, subnode)) { - const char *name = fdt_get_name(old_blob, - subnode, NULL); - if (!name) -@@ -189,14 +190,12 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) - ret = fdtdec_add_reserved_memory(new_blob, - nodename, - &carveout, -- NULL); -+ NULL, true); - free(oldname); - - if (ret < 0) - return ret; - } -- -- subnode = fdt_next_subnode(old_blob, subnode); - } - } - -diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt -index db089bed1a..a8767d4554 100644 ---- a/scripts/config_whitelist.txt -+++ b/scripts/config_whitelist.txt -@@ -1791,7 +1791,6 @@ CONFIG_SYS_AMASK4 - CONFIG_SYS_AMASK5 - CONFIG_SYS_AMASK6 - CONFIG_SYS_AMASK7 --CONFIG_SYS_ARM_CACHE_WRITETHROUGH - CONFIG_SYS_AT91_CPU_NAME - CONFIG_SYS_AT91_MAIN_CLOCK - CONFIG_SYS_AT91_PLLA --- -2.17.1 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch b/recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch deleted file mode 100644 index 692570f..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 881509572b6d9fac6dc570b710e89d47cabbf05b Mon Sep 17 00:00:00 2001 -From: Christophe Priouzeau -Date: Tue, 27 Oct 2020 11:49:05 +0100 -Subject: [PATCH 10/10] ARM-v2020.01-stm32mp-r2-CONFIG - ---- - configs/stm32mp15_basic_defconfig | 3 +-- - configs/stm32mp15_trusted_defconfig | 4 ++-- - 2 files changed, 3 insertions(+), 4 deletions(-) - -diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig -index cf282177f7..79e77e122c 100644 ---- a/configs/stm32mp15_basic_defconfig -+++ b/configs/stm32mp15_basic_defconfig -@@ -27,8 +27,6 @@ CONFIG_CMD_DTIMG=y - # CONFIG_CMD_ELF is not set - # CONFIG_CMD_IMI is not set - # CONFIG_CMD_XIMG is not set --# CONFIG_CMD_EXPORTENV is not set --# CONFIG_CMD_IMPORTENV is not set - CONFIG_CMD_ERASEENV=y - CONFIG_CMD_MEMINFO=y - CONFIG_CMD_MEMTEST=y -@@ -89,6 +87,7 @@ CONFIG_LED=y - CONFIG_LED_GPIO=y - CONFIG_DM_MAILBOX=y - CONFIG_STM32_IPCC=y -+CONFIG_STM32_FMC2_EBI=y - CONFIG_DM_MMC=y - CONFIG_SUPPORT_EMMC_BOOT=y - CONFIG_STM32_SDMMC2=y -diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig -index e248b7d1d3..b5069bc6d5 100644 ---- a/configs/stm32mp15_trusted_defconfig -+++ b/configs/stm32mp15_trusted_defconfig -@@ -15,8 +15,6 @@ CONFIG_CMD_DTIMG=y - # CONFIG_CMD_ELF is not set - # CONFIG_CMD_IMI is not set - # CONFIG_CMD_XIMG is not set --# CONFIG_CMD_EXPORTENV is not set --# CONFIG_CMD_IMPORTENV is not set - CONFIG_CMD_ERASEENV=y - CONFIG_CMD_MEMINFO=y - CONFIG_CMD_MEMTEST=y -@@ -77,6 +75,7 @@ CONFIG_LED_GPIO=y - CONFIG_DM_MAILBOX=y - CONFIG_STM32_IPCC=y - CONFIG_ARM_SMC_MAILBOX=y -+CONFIG_STM32_FMC2_EBI=y - CONFIG_DM_MMC=y - CONFIG_SUPPORT_EMMC_BOOT=y - CONFIG_STM32_SDMMC2=y -@@ -106,6 +105,7 @@ CONFIG_DM_REGULATOR_FIXED=y - CONFIG_DM_REGULATOR_GPIO=y - CONFIG_DM_REGULATOR_STM32_VREFBUF=y - CONFIG_DM_REGULATOR_STPMIC1=y -+CONFIG_REMOTEPROC_OPTEE=y - CONFIG_REMOTEPROC_STM32_COPRO=y - CONFIG_RESET_SCMI=y - CONFIG_DM_RTC=y --- -2.17.1 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt b/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt index c1fcafc..fcd71ea 100644 --- a/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt +++ b/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt @@ -98,7 +98,7 @@ To compile U-Boot source code, first move to U-Boot source: or $ cd u-boot -5.1 Compilation for one target (one defconfig, one device tree) +5.1 Compilation for one target (one defconfig, one device tree) - and no FIP see /board/st/stm32mp1/README for details @@ -115,11 +115,14 @@ To compile U-Boot source code, first move to U-Boot source: $ make stm32mp15_basic_defconfig $ make DEVICE_TREE=stm32mp157c-dk2 all -5.2 Compilation for several targets: use Makefile.sdk - +5.2 Compilation for several targets: use Makefile.sdk (with FIP) Calls the specific 'Makefile.sdk' provided to compile U-Boot: - Display 'Makefile.sdk' file default configuration and targets: - $> make -f $PWD/../Makefile.sdk help + $ make -f $PWD/../Makefile.sdk help +As mentionned in help, OpenSTLinux has activated FIP by default, so the FIP_artifacts should be specified + - In case of using SOURCES-xxxx.tar.gz of Developer package the FIP_DEPLOYDIR_ROOT should be set as below: + $> export FIP_DEPLOYDIR_ROOT=$PWD/../../FIP_artifacts + - Compile default U-Boot configuration: $> make -f $PWD/../Makefile.sdk all @@ -133,15 +136,7 @@ variables 'DEVICE_TREE' and 'UBOOT_CONFIGS': is the u-boot binary to export (ex: 'u-boot.bin', 'u-boot.stm32', etc) ex: UBOOT_CONFIGS=",basic,u-boot.bin ,trusted,u-boot.stm32" -The generated binary files are available in ../build-${config}. - -by default we define 3 configs: basic, trusted, optee for the several boards -The generated files are : - for trusted and optee configs: - #> ../build-{trusted,optee}/*.stm32 - for basic config - #> ../build-basic/u-boot-spl.elf-*-basic - #> ../build-basic/u-boot-*-basic.img +The generated FIP images are available in $FIP_DEPLOYDIR_ROOT/fip You can override the default U-Boot configuration if you specify these variables: - Compile default U-Boot configuration but applying specific devicetree(s): @@ -153,101 +148,5 @@ You can override the default U-Boot configuration if you specify these variables 6. Update software on board: ---------------------------- +Please use STM32CubeProgrammer and only tick the ssbl-boot and fip partition (more informations on the wiki website http://wiki.st.com/stm32mpu) -see also /board/st/stm32mp1/README - -6.1. partitioning of binaries: ------------------------------- - -There are two possible boot chains available: -- Basic boot chain (for basic configuration) -- Trusted boot chain (for trusted and optee configuration) - -U-Boot build provides binaries for each configuration: -- Basic boot chain: U-Boot SPL and U-Boot imgage (for FSBL and SSBL) -- Trusted boot chain: U-Boot binary with ".stm32" extension (for SSBL, FSBL is provided by TF-A) - -6.1.1. Basic boot chain: -On this configuration, we use U-Boot SPL as First Stage Boot Loader (FSBL) and -U-Boot as Second Stage Boot Loader (SSBL). -U-Boot SPL (u-boot-spl.stm32-*) MUST be copied on a dedicated partition named "fsbl1" -U-Boot image (u-boot*.img) MUST be copied on a dedicated partition named "ssbl" - -6.1.2. Trusted boot chain: -On this configuration, U-Boot is associated to Trusted Firmware (TF-A) and only -U-Boot image is used as Second Stage Boot Loader (SSBL). -TF-A binary (tf-a-*.stm32) MUST be copied on a dedicated partition named "fsbl1" -U-boot binary (u-boot*.stm32) MUST be copied on a dedicated partition named "ssbl" - -6.2. Update via SDCARD: ------------------------ - -6.2.1. Basic boot chain -* u-boot-spl.stm32-* - Copy the binary on the dedicated partition, on SDCARD/USB disk the partition - "fsbl1" is the partition 1: - - SDCARD: /dev/mmcblkXp1 (where X is the instance number) - - SDCARD via USB reader: /dev/sdX1 (where X is the instance number) - $ dd if= of=/dev/ bs=1M conv=fdatasync - -* u-boot*.img - Copy the binary on the dedicated partition, on SDCARD/USB disk the partition - "ssbl" is the partition 4: - - SDCARD: /dev/mmcblkXp3 (where X is the instance number) - - SDCARD via USB reader: /dev/sdX3 (where X is the instance number) - $ dd if= of=/dev/ bs=1M conv=fdatasync - -6.2.2. Trusted boot chain -* tf-a-*.stm32 - Copy the binary on the dedicated partition, on SDCARD/USB disk the partition - "fsbl1" is the partition 1: - - SDCARD: /dev/mmcblkXp1 (where X is the instance number) - - SDCARD via USB reader: /dev/sdX1 (where X is the instance number) - $ dd if= of=/dev/ bs=1M conv=fdatasync - -* u-boot*.stm32 - Copy the binary on the dedicated partition, on SDCARD/USB disk the partition - "ssbl" is the partition 4: - - SDCARD: /dev/mmcblkXp3 (where X is the instance number) - - SDCARD via USB reader: /dev/sdX3 (where X is the instance number) - $ dd if= of=/dev/ bs=1M conv=fdatasync - -6.2.3. FAQ -to found the partition associated to a specific label, just plug the -SDCARD/USB disk on your PC and call the following command: - $ ls -l /dev/disk/by-partlabel/ -total 0 -lrwxrwxrwx 1 root root 10 Jan 17 17:38 bootfs -> ../../mmcblk0p4 -lrwxrwxrwx 1 root root 10 Jan 17 17:38 fsbl1 -> ../../mmcblk0p1 ➔ FSBL (TF-A) -lrwxrwxrwx 1 root root 10 Jan 17 17:38 fsbl2 -> ../../mmcblk0p2 ➔ FSBL backup (TF-A backup – same content as FSBL) -lrwxrwxrwx 1 root root 10 Jan 17 17:38 rootfs -> ../../mmcblk0p5 -lrwxrwxrwx 1 root root 10 Jan 17 17:38 ssbl -> ../../mmcblk0p3 ➔ SSBL (U-Boot) -lrwxrwxrwx 1 root root 10 Jan 17 17:38 userfs -> ../../mmcblk0p6 - -6.3. Update via USB mass storage on U-Boot: -------------------------------------------- - -We are using the U-Boot command ums - -STM32MP> help ums - ums - Use the UMS [USB Mass Storage] - - Usage: - ums [] e.g. ums 0 mmc 0 - devtype defaults to mmc - ums - -By default on STMicroelectronics board, "mmc 0" is SD card on SDMMC1. - -* Plug the SDCARD on Board. -* Start the board and stop on U-Boot shell: - Hit any key to stop autoboot: 0 - STM32MP> -* plug an USB cable between the PC and the board via USB OTG port. -* On U-Boot shell, call the usb mass storage functionality: - STM32MP> ums 0 mmc 0 -* After a delay (of up to 15 seconds), the host sees the exported block device. -* Follow section 6.2 to put U-Boot SPL binary and U-Boot binary - (*.img or *.stm32) on SDCARD/USB disk. - -PS: A Ctrl-C is needed to stop the command. \ No newline at end of file diff --git a/recipes-bsp/u-boot/u-boot-stm32mp/remove-redundant-yyloc-global.patch b/recipes-bsp/u-boot/u-boot-stm32mp/remove-redundant-yyloc-global.patch deleted file mode 100644 index 2a184e5..0000000 --- a/recipes-bsp/u-boot/u-boot-stm32mp/remove-redundant-yyloc-global.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 018921ee79d3f30893614b3b2b63b588d8544f73 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Thu, 30 Jan 2020 09:37:15 +0000 -Subject: [PATCH] Remove redundant YYLOC global declaration - -Same as the upstream fix for building dtc with gcc 10. - -Signed-off-by: Peter Robinson ---- - scripts/dtc/dtc-lexer.l | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l -index fd825ebba6..24af549977 100644 ---- a/scripts/dtc/dtc-lexer.l -+++ b/scripts/dtc/dtc-lexer.l -@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n - #include "srcpos.h" - #include "dtc-parser.tab.h" - --YYLTYPE yylloc; - extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ --- -2.26.2 - diff --git a/recipes-bsp/u-boot/u-boot-stm32mp_2020.01.bb b/recipes-bsp/u-boot/u-boot-stm32mp_2020.10.bb similarity index 100% rename from recipes-bsp/u-boot/u-boot-stm32mp_2020.01.bb rename to recipes-bsp/u-boot/u-boot-stm32mp_2020.10.bb