TF-A-STM32MP: update to v2.4-stm32mp-r2
Change-Id: I8ff248b82c8f4da0f5905d381176402e16e096ff Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
This commit is contained in:
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0e297b657a
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@ -35,8 +35,11 @@ DEPENDS_append = " ${@bb.utils.contains('TF_A_ENABLE_DEBUG_WRAPPER', '1', 'stm32
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# Default log level
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ST_TF_A_DEBUG_LOG_LEVEL ??= "40"
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# Extra make settings
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EXTRA_OEMAKE = 'CROSS_COMPILE=${TARGET_PREFIX}'
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# Configure make settings
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EXTRA_OEMAKE += 'PLAT=${TFA_PLATFORM}'
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EXTRA_OEMAKE += 'ARCH=${TFA_ARM_ARCH}'
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EXTRA_OEMAKE += 'ARM_ARCH_MAJOR=${TFA_ARM_MAJOR}'
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EXTRA_OEMAKE += 'CROSS_COMPILE=${TARGET_PREFIX}'
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# Debug support
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EXTRA_OEMAKE += '${@bb.utils.contains('ST_TF_A_DEBUG_TRACE', '1', 'DEBUG=1', '', d)}'
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EXTRA_OEMAKE += '${@bb.utils.contains('ST_TF_A_DEBUG_TRACE', '1', 'LOG_LEVEL=${ST_TF_A_DEBUG_LOG_LEVEL}', '', d)}'
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@ -0,0 +1,157 @@
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From 903a55e874e91ccd1fb435bea3a675e2eb4257fa Mon Sep 17 00:00:00 2001
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From: Romuald JEANNE <romuald.jeanne@st.com>
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Date: Wed, 2 Jun 2021 16:45:18 +0200
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Subject: [PATCH 2/3] v2.4-stm32mp-r1.1-rc1
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---
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docs/plat/stm32mp1.rst | 9 ++++++---
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drivers/st/clk/stm32mp1_clk.c | 4 ++--
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include/drivers/st/stm32mp1_rcc.h | 16 ++++++++++++++++
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plat/st/common/stm32mp_crypto_lib.c | 5 ++++-
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plat/st/stm32mp1/stm32mp1_def.h | 2 ++
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plat/st/stm32mp1/stm32mp1_helper.S | 13 +++++++++++++
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6 files changed, 43 insertions(+), 6 deletions(-)
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diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
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index fb7afdbbb0..95f4a186f5 100644
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--- a/docs/plat/stm32mp1.rst
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+++ b/docs/plat/stm32mp1.rst
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@@ -153,7 +153,10 @@ To build TF-A BL2 with its STM32 header for SD-card boot:
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.. code:: bash
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make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
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- DTB_FILE_NAME=stm32mp157c-ev1.dtb
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+ DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
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+
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+For other boot devices, you have to replace STM32MP_SDMMC in the previous command
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+with the desired devive flag.
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This BL2 is independent of the BL32 used (SP_min or OP-TEE)
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@@ -204,14 +207,14 @@ __________________
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--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
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--nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
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--nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
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- --hw-config <u-boot_directory>/u-boot.dtb
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+ --hw-config <u-boot_directory>/u-boot.dtb \
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--fw-config build/stm32mp1/debug/fdts/fw-config.dtb
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tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
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--tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
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--tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
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--nt-fw <u-boot_directory>/u-boot-nodtb.bin \
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- --hw-config <u-boot_directory>/uboot-nodtb.dtb \
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+ --hw-config <u-boot_directory>/u-boot.dtb \
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--tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
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--tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
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--nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
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diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
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index 00954cb2e8..d074a1568c 100644
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--- a/drivers/st/clk/stm32mp1_clk.c
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+++ b/drivers/st/clk/stm32mp1_clk.c
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
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+ * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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@@ -1853,7 +1853,7 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
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(clksrc != (uint32_t)CLK_RTC_DISABLED)) {
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mmio_clrsetbits_32(address,
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RCC_BDCR_RTCSRC_MASK,
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- clksrc << RCC_BDCR_RTCSRC_SHIFT);
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+ (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
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mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
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}
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diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
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index feaac43a13..616051e772 100644
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--- a/include/drivers/st/stm32mp1_rcc.h
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+++ b/include/drivers/st/stm32mp1_rcc.h
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@@ -576,6 +576,22 @@
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#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)
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#define RCC_FMCCKSELR_FMCSRC_SHIFT 0
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+/* RCC_APB1RSTSETR register fields */
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+#define RCC_APB1RSTSETR_USART2RST BIT(14)
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+#define RCC_APB1RSTSETR_USART3RST BIT(15)
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+#define RCC_APB1RSTSETR_UART4RST BIT(16)
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+#define RCC_APB1RSTSETR_UART5RST BIT(17)
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+#define RCC_APB1RSTSETR_UART7RST BIT(18)
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+#define RCC_APB1RSTSETR_UART8RST BIT(19)
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+
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+/* RCC_APB1RSTCLRR register fields */
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+#define RCC_APB1RSTCLRR_USART2RST BIT(14)
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+#define RCC_APB1RSTCLRR_USART3RST BIT(15)
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+#define RCC_APB1RSTCLRR_UART4RST BIT(16)
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+#define RCC_APB1RSTCLRR_UART5RST BIT(17)
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+#define RCC_APB1RSTCLRR_UART7RST BIT(18)
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+#define RCC_APB1RSTCLRR_UART8RST BIT(19)
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+
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/* RCC_USBCKSELR register fields */
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#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)
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#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0
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diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c
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index de9601d2b8..9582162813 100644
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--- a/plat/st/common/stm32mp_crypto_lib.c
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+++ b/plat/st/common/stm32mp_crypto_lib.c
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@@ -40,6 +40,7 @@ static void crypto_lib_init(void)
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{
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp_get_boot_ctx_address();
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+ int ret;
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if (!stm32mp_is_auth_supported()) {
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return;
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@@ -48,7 +49,9 @@ static void crypto_lib_init(void)
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auth_ops.verify_signature =
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boot_context->bootrom_ecdsa_verify_signature;
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- if (stm32_hash_register() != 0) {
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+ ret = stm32_hash_register();
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+ if (ret != 0) {
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+ ERROR("HASH init (%d)\n", ret);
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panic();
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}
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}
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diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
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index 027dba1bde..326b227842 100644
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--- a/plat/st/stm32mp1/stm32mp1_def.h
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+++ b/plat/st/stm32mp1/stm32mp1_def.h
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@@ -433,6 +433,8 @@ enum ddr_type {
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#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
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#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
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#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
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+#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
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+#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
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/*******************************************************************************
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* STM32MP1 ETZPC
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diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S
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index bc2d73cebb..315a67f2cf 100644
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--- a/plat/st/stm32mp1/stm32mp1_helper.S
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+++ b/plat/st/stm32mp1/stm32mp1_helper.S
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@@ -245,6 +245,19 @@ endfunc plat_my_core_pos
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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+ /* Reset UART peripheral */
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+ ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG)
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+ ldr r2, =DEBUG_UART_RST_BIT
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+ str r2, [r1]
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+1:
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+ ldr r0, [r1]
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+ ands r0, r2
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+ beq 1b
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+ str r2, [r1, #4] /* RSTCLR register */
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+2:
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+ ldr r0, [r1]
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+ ands r0, r2
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+ bne 2b
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/* Enable GPIOs for UART TX */
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ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
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ldr r2, [r1]
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--
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2.17.1
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File diff suppressed because it is too large
Load Diff
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@ -14,11 +14,13 @@ SRCREV = "e2c509a39c6cc4dda8734e6509cdbe6e3603cdfc"
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SRC_URI += " \
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file://0001-st-update-v2.4-r1.0.0.patch \
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file://0002-v2.4-stm32mp-r1.1-rc1.patch \
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file://0003-v2.4-stm32mp-r2.patch \
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"
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TF_A_VERSION = "v2.4"
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TF_A_SUBVERSION = "stm32mp"
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TF_A_RELEASE = "r1"
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TF_A_RELEASE = "r2"
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PV = "${TF_A_VERSION}-${TF_A_SUBVERSION}-${TF_A_RELEASE}"
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ARCHIVER_ST_BRANCH = "${TF_A_VERSION}-${TF_A_SUBVERSION}"
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@ -28,10 +30,10 @@ ARCHIVER_COMMUNITY_REVISION = "${TF_A_VERSION}"
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S = "${WORKDIR}/git"
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# Configure stm32mp1 make settings
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EXTRA_OEMAKE += "PLAT=stm32mp1"
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EXTRA_OEMAKE += "ARCH=aarch32"
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EXTRA_OEMAKE += "ARM_ARCH_MAJOR=7"
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# Configure settings
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TFA_PLATFORM = "stm32mp1"
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TFA_ARM_MAJOR = "7"
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TFA_ARM_ARCH = "aarch32"
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# Enable the wrapper for debug
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TF_A_ENABLE_DEBUG_WRAPPER ?= "1"
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@ -47,7 +49,7 @@ include ${@oe.utils.ifelse(d.getVar('ST_ARCHIVER_ENABLE') == '1', 'tf-a-stm32mp-
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BBCLASSEXTEND = "devupstream:target"
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SRC_URI_class-devupstream = "git://github.com/STMicroelectronics/arm-trusted-firmware.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
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SRCREV_class-devupstream = "40572e4067f205691a4dca3b5fdabe3a40c69594"
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SRCREV_class-devupstream = "3e1e3f0a6149d04946ff5debcd871173e782111c"
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# ---------------------------------
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# Configure default preference to manage dynamic selection between tarball and github
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