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e48b3d7d0d ... e0eb17949a

41 changed files with 2842 additions and 6927 deletions
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1
conf/machine/include/gpu_vivante.inc
View File

@ -42,7 +42,6 @@ GPU_USERLAND_LIBRARIES_INSTALL = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/egl = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/libgles1 = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/libgles2 = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/libgles3 = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/libgbm = "${@get_gpu_vivante_handler(d)}"
PREFERRED_PROVIDER_virtual/mesa = "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/egl','mesa','mesa','mesa-gl',d)}"
PREFERRED_PROVIDER_virtual/libgl = "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/egl','mesa','mesa','mesa-gl',d)}"

5
recipes-bsp/trusted-firmware-a/tf-a-stm32mp-common.inc
View File

@ -11,12 +11,11 @@ SRCREV = "a1f02f4f3daae7e21ee58b4c93ec3e46b8f28d15"
SRC_URI += " \
file://0001-v2.6-stm32mp-r1.patch \
file://0002-v2.6-stm32mp-r2.patch \
file://0003-v2.6-stm32mp-r2.1.patch\
"
TF_A_VERSION = "v2.6"
TF_A_SUBVERSION = "stm32mp"
TF_A_RELEASE = "r2.1"
TF_A_RELEASE = "r2"
PV = "${TF_A_VERSION}-${TF_A_SUBVERSION}-${TF_A_RELEASE}"
ARCHIVER_ST_BRANCH = "${TF_A_VERSION}-${TF_A_SUBVERSION}"
@ -32,7 +31,7 @@ S = "${WORKDIR}/git"
BBCLASSEXTEND = "devupstream:target"
SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/arm-trusted-firmware.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
SRCREV:class-devupstream = "aa1e9e2db80e49ed0259757a0f09ff119725409d"
SRCREV:class-devupstream = "4b6e8e9bf8fa676ff8d1358ea2cf2e44904c2473"
# ---------------------------------
# Configure default preference to manage dynamic selection between tarball and github

2
recipes-bsp/trusted-firmware-a/tf-a-stm32mp.inc
View File

@ -92,7 +92,7 @@ TF_A_SIGN_ENABLE ??= "0"
TF_A_ENCRYPTED_ENABLE ??= "0"
# Set metadata generation
TF_A_ENABLE_METADATA ??= "${@bb.utils.contains('MACHINE_FEATURES', 'fw-update', '1', '0', d)}"
TF_A_ENABLE_METADATA ??= "${@bb.utils.contains('MACHINE_FEATURES', 'fw-update', '1', '0', 'd')}"
TF_A_METADATA_NAME ?= "metadata"
TF_A_METADATA_SUFFIX ?= "bin"
TF_A_METADATA_BINARY ??= "${TF_A_METADATA_NAME}.${TF_A_METADATA_SUFFIX}"

582
recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-v2.6-stm32mp-r2.1.patch
View File

@ -1,582 +0,0 @@
From 26924c80204083a5184a425f534e39fbc5d97484 Mon Sep 17 00:00:00 2001
From: Lionel VITTE <lionel.vitte@st.com>
Date: Mon, 3 Jul 2023 10:24:57 +0200
Subject: [PATCH] v2.6-stm32mp-r2.1-rc1
---
drivers/mtd/nand/spi_nand.c | 3 +-
drivers/st/bsec/bsec2.c | 17 ----------
drivers/st/uart/aarch32/stm32_console.S | 9 ++++--
fdts/stm32mp15-bl2.dtsi | 1 -
fdts/stm32mp15-bl32.dtsi | 1 -
include/drivers/spi_nand.h | 4 +++
include/drivers/st/bsec.h | 1 -
include/drivers/st/bsec2_reg.h | 1 -
plat/st/common/stm32cubeprogrammer_uart.c | 9 +++++-
plat/st/stm32mp1/include/stm32mp1_private.h | 4 ++-
plat/st/stm32mp1/plat_def_uuid_config.c | 11 +++++--
plat/st/stm32mp1/platform.mk | 2 +-
plat/st/stm32mp1/stm32mp1_context.c | 28 +++++++++++++++-
.../stm32mp1/stm32mp1_critic_power_wrapper.S | 9 +-----
plat/st/stm32mp1/stm32mp1_def.h | 11 +++++--
plat/st/stm32mp1/stm32mp1_low_power.c | 22 ++++++-------
plat/st/stm32mp1/stm32mp1_pm.c | 6 ++--
plat/st/stm32mp1/stm32mp1_private.c | 32 ++++++++++++++++++-
plat/st/stm32mp1/stm32mp1_ssp.c | 5 ++-
19 files changed, 119 insertions(+), 57 deletions(-)
diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c
index abb524d7f..a18b06f58 100644
--- a/drivers/mtd/nand/spi_nand.c
+++ b/drivers/mtd/nand/spi_nand.c
@@ -17,7 +17,6 @@
#define SPI_NAND_MAX_ID_LEN 4U
#define DELAY_US_400MS 400000U
-#define MACRONIX_ID 0xC2U
static struct spinand_device spinand_dev;
@@ -91,7 +90,7 @@ static int spi_nand_quad_enable(uint8_t manufacturer_id)
{
bool enable = false;
- if (manufacturer_id != MACRONIX_ID) {
+ if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) {
return 0;
}
diff --git a/drivers/st/bsec/bsec2.c b/drivers/st/bsec/bsec2.c
index 6a8af5c13..8a07b118e 100644
--- a/drivers/st/bsec/bsec2.c
+++ b/drivers/st/bsec/bsec2.c
@@ -582,23 +582,6 @@ uint32_t bsec_permanent_lock_otp(uint32_t otp)
return result;
}
-/*
- * bsec_write_debug_conf: write value in debug feature.
- * to enable/disable debug service.
- * val: value to write.
- * return value: none.
- */
-void bsec_write_debug_conf(uint32_t val)
-{
- if (is_otp_invalid_mode()) {
- return;
- }
-
- bsec_lock();
- mmio_write_32(bsec_base + BSEC_DEN_OFF, val & BSEC_DEN_ALL_MSK);
- bsec_unlock();
-}
-
/*
* bsec_read_debug_conf: return debug configuration register value.
*/
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
index abe47b53f..43039fdc7 100644
--- a/drivers/st/uart/aarch32/stm32_console.S
+++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -238,14 +238,19 @@ func console_stm32_core_flush
cmp r0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
+ /* Skip flush if UART is not enabled */
+ ldr r1, [r0, #USART_CR1]
+ tst r1, #USART_CR1_UE
+ beq 1f
/* Check Transmit Data Register Empty */
mov r2, #USART_TIMEOUT
txe_loop_3:
subs r2, r2, #1
- beq plat_panic_handler
+ beq 1f
ldr r1, [r0, #USART_ISR]
tst r1, #USART_ISR_TXE
beq txe_loop_3
+1:
bx lr
endfunc console_stm32_core_flush
diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
index 6938d9e3f..52c8e1670 100644
--- a/fdts/stm32mp15-bl2.dtsi
+++ b/fdts/stm32mp15-bl2.dtsi
@@ -42,7 +42,6 @@
/delete-node/ rtc@5c004000;
/delete-node/ etzpc@5c007000;
/delete-node/ stgen@5c008000;
- /delete-node/ i2c@5c009000;
/delete-node/ tamp@5c00a000;
pinctrl@50002000 {
diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
index 264aaf098..6de0207dd 100644
--- a/fdts/stm32mp15-bl32.dtsi
+++ b/fdts/stm32mp15-bl32.dtsi
@@ -24,7 +24,6 @@
/delete-node/ mmc@58007000;
/delete-node/ spi@5c001000;
/delete-node/ stgen@5c008000;
- /delete-node/ i2c@5c009000;
pinctrl@50002000 {
/delete-node/ fmc-0;
diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h
index 40e206375..1eddbb6c0 100644
--- a/include/drivers/spi_nand.h
+++ b/include/drivers/spi_nand.h
@@ -29,9 +29,13 @@
#define SPI_NAND_STATUS_BUSY BIT(0)
#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
+/* Flags for specific configuration */
+#define SPI_NAND_HAS_QE_BIT BIT(0)
+
struct spinand_device {
struct nand_device *nand_dev;
struct spi_mem_op spi_read_cache_op;
+ uint32_t flags;
uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
};
diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h
index 145f9d783..909884289 100644
--- a/include/drivers/st/bsec.h
+++ b/include/drivers/st/bsec.h
@@ -102,7 +102,6 @@ uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
uint32_t bsec_permanent_lock_otp(uint32_t otp);
-void bsec_write_debug_conf(uint32_t val);
uint32_t bsec_read_debug_conf(void);
void bsec_write_scratch(uint32_t val);
diff --git a/include/drivers/st/bsec2_reg.h b/include/drivers/st/bsec2_reg.h
index 0d8fedc48..fbe2e3767 100644
--- a/include/drivers/st/bsec2_reg.h
+++ b/include/drivers/st/bsec2_reg.h
@@ -94,7 +94,6 @@
#define BSEC_SPIDEN BIT(5)
#define BSEC_SPINDEN BIT(6)
#define BSEC_DBGSWGEN BIT(10)
-#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
/* BSEC_FENABLE Register */
#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c
index a993afdbf..48da167bf 100644
--- a/plat/st/common/stm32cubeprogrammer_uart.c
+++ b/plat/st/common/stm32cubeprogrammer_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -138,11 +138,13 @@ static int uart_send_result(uint8_t byte)
return uart_write_8(byte);
}
+#if !STM32MP_SSP
static int is_valid_header(fip_toc_header_t *header)
{
return (header->name == TOC_HEADER_NAME) &&
(header->serial_number != 0U);
}
+#endif
static int uart_receive_command(uint8_t *command)
{
@@ -395,12 +397,15 @@ static int uart_start_cmd(uintptr_t buffer)
return 0;
}
+#if !STM32MP_SSP
if (!is_valid_header((fip_toc_header_t *)buffer)) {
STM32PROG_ERROR("FIP Header check failed %lx, for phase %u\n",
buffer, handle.phase);
return -EIO;
}
+
VERBOSE("FIP header looks OK.\n");
+#endif
return 0;
}
@@ -589,6 +594,8 @@ static int uart_read(uint8_t id, uintptr_t buffer, size_t length)
}
}
+ stm32_uart_flush(&handle.uart);
+
return 0;
}
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 73222815c..ccddc5bad 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,6 +47,8 @@ void stm32mp1_init_scmi_server(void);
void stm32mp1_pm_save_scmi_state(uint8_t *state, size_t size);
void stm32mp1_pm_restore_scmi_state(uint8_t *state, size_t size);
+bool stm32mp_bkpram_get_access(void);
+
#if defined(IMAGE_BL32) && DEBUG
void stm32mp_dump_core_registers(bool fcore);
#endif
diff --git a/plat/st/stm32mp1/plat_def_uuid_config.c b/plat/st/stm32mp1/plat_def_uuid_config.c
index efaf56701..4df414468 100644
--- a/plat/st/stm32mp1/plat_def_uuid_config.c
+++ b/plat/st/stm32mp1/plat_def_uuid_config.c
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <stddef.h>
+
#include <firmware_image_package.h>
#include "tbbr_config.h"
@@ -13,6 +15,11 @@ toc_entry_t plat_def_toc_entries[] = {
.name = "STM32MP CONFIG CERT",
.uuid = UUID_STM32MP_CONFIG_CERT,
.cmdline_name = "stm32mp-cfg-cert"
+ },
+
+ {
+ .name = NULL,
+ .uuid = { {0} },
+ .cmdline_name = NULL,
}
};
-
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 9a4122184..97cedb514 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -14,7 +14,7 @@ STM32MP_RECONFIGURE_CONSOLE ?= 0
STM32MP_UART_BAUDRATE ?= 115200
# Add specific ST version
-ST_VERSION := r2.0
+ST_VERSION := r2.1
ST_GIT_SHA1 := $(shell git rev-parse --short=8 HEAD 2>/dev/null)
VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}-${PLAT}-${ST_VERSION}(${BUILD_TYPE}):${BUILD_STRING}(${ST_GIT_SHA1})
diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
index 4ed88e6c4..4c881e1cf 100644
--- a/plat/st/stm32mp1/stm32mp1_context.c
+++ b/plat/st/stm32mp1/stm32mp1_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -158,6 +158,10 @@ uint32_t stm32_pm_get_optee_ep(void)
void stm32_clean_context(void)
{
+ if (!stm32mp_bkpram_get_access()) {
+ return;
+ }
+
clk_enable(BKPSRAM);
#if defined(IMAGE_BL2)
@@ -410,6 +414,10 @@ void stm32_context_save_bl2_param(void)
{
struct backup_data_s *backup_data;
+ if (!stm32mp_bkpram_get_access()) {
+ return;
+ }
+
clk_enable(BKPSRAM);
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
@@ -578,6 +586,10 @@ void stm32mp1_pm_save_mce_mkey_in_context(uint8_t *data)
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ if (!stm32mp_bkpram_get_access()) {
+ return;
+ }
+
clk_enable(BKPSRAM);
memcpy(backup_data->mce_mkey, data, MCE_KEY_SIZE_IN_BYTES);
@@ -591,6 +603,11 @@ void stm32mp1_pm_get_mce_mkey_from_context(uint8_t *data)
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ if (!stm32mp_bkpram_get_access()) {
+ ERROR("DDR encryption key not available\n");
+ panic();
+ }
+
clk_enable(BKPSRAM);
memcpy(data, backup_data->mce_mkey, MCE_KEY_SIZE_IN_BYTES);
@@ -606,6 +623,10 @@ void stm32mp1_pm_save_mce_region(uint32_t index, struct stm32_mce_region_s *conf
panic();
}
+ if (!stm32mp_bkpram_get_access()) {
+ return;
+ }
+
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
clk_enable(BKPSRAM);
@@ -625,6 +646,11 @@ void stm32mp1_pm_get_mce_region(uint32_t index, struct stm32_mce_region_s *confi
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ if (!stm32mp_bkpram_get_access()) {
+ ERROR("MCE region not available\n");
+ panic();
+ }
+
clk_enable(BKPSRAM);
memcpy(config, &backup_data->mce_regions[index], sizeof(struct stm32_mce_region_s));
diff --git a/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S b/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
index d7981d61c..c3fb5cdbf 100644
--- a/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
+++ b/plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,13 +61,6 @@ func stm32_pwr_down_wfi_wrapper
# Set sp to BL2 STACK (as BL2 is not using it anymore)
ldr sp, =__STACKS_END__
- # Disable MMU as TLB are still stored in DDR,
- # and in few instructions DDR won't be readable
- bl disable_mmu_secure
-
- # dsb is done in disable mmu
- # isb is done in disable mmu
-
mov r0, r2
mov r1, r3
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index ba92bd321..d80d64695 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -380,9 +380,11 @@ enum ddr_type {
#if STM32MP13
#define NAND_OTP "cfg9_otp"
#define NAND2_OTP "cfg10_otp"
+#define SSP_OTP "cfg9_otp"
#endif
#if STM32MP15
#define NAND_OTP "nand_otp"
+#define SSP_OTP "ssp_otp"
#endif
#define MONOTONIC_OTP "monotonic_otp"
#define UID_OTP "uid_otp"
@@ -390,7 +392,6 @@ enum ddr_type {
#define ENCKEY_OTP "enckey_otp"
#define BOARD_ID_OTP "board_id"
#define CFG2_OTP "cfg2_otp"
-#define SSP_OTP "ssp_otp"
#define CHIP_CERTIFICATE_OTP "chip_otp"
#define RMA_OTP "rma_otp"
@@ -521,7 +522,13 @@ enum ddr_type {
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
#define TAMP_BKP_SEC_NUMBER U(10)
#define TAMP_BKP_S_W_NS_R_NUMBER U(5)
+#define TAMP_CR2 U(0x4)
+#define TAMP_CR2_MASK_NOER GENMASK_32(7, 0)
+#define TAMP_CR3 U(0x8)
+#define TAMP_CR3_MASK_NOER GENMASK_32(12, 0)
+#define TAMP_SR U(0x30)
#define TAMP_COUNTR U(0x40)
+#define TAMP_ERCFGR U(0x54)
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
static inline uintptr_t tamp_bkpr(uint32_t idx)
diff --git a/plat/st/stm32mp1/stm32mp1_low_power.c b/plat/st/stm32mp1/stm32mp1_low_power.c
index a4b473515..0be84c935 100644
--- a/plat/st/stm32mp1/stm32mp1_low_power.c
+++ b/plat/st/stm32mp1/stm32mp1_low_power.c
@@ -232,13 +232,6 @@ static void enter_cstop(uint32_t mode, uint32_t nsec_addr)
;
}
}
-
- /* Keep backup RAM content in standby */
- mmio_setbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN);
- while ((mmio_read_32(pwr_base + PWR_CR2) &
- PWR_CR2_BRRDY) == 0U) {
- ;
- }
}
clk_disable(RTCAPB);
@@ -281,8 +274,8 @@ void stm32_exit_cstop(void)
dsb();
isb();
- /* Disable retention and backup RAM content after stop */
- mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN);
+ /* Disable retention RAM content after stop */
+ mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_RREN);
/* Update STGEN counter with low power mode duration */
stm32_rtc_get_calendar(&current_calendar);
@@ -431,11 +424,18 @@ void stm32_init_low_power(void)
mmio_setbits_32(rcc_base + RCC_MP_SREQCLRR,
RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1);
- /* Disable retention and backup RAM content after standby */
- mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN);
+ /* Disable retention RAM content after standby */
+ mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_RREN);
/* Wait 5 HSI periods before re-enabling PLLs after STOP modes */
mmio_clrsetbits_32(rcc_base + RCC_PWRLPDLYCR,
RCC_PWRLPDLYCR_PWRLP_DLY_MASK,
PWRLP_TEMPO_5_HSI);
+
+ /* Keep backup RAM content in standby and VBAT mode */
+ mmio_setbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN);
+ while ((mmio_read_32(pwr_base + PWR_CR2) &
+ PWR_CR2_BRRDY) == 0U) {
+ ;
+ }
}
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 1346c11b5..c482af502 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -169,13 +169,13 @@ static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
void (*warm_entrypoint)(void) =
(void (*)(void))stm32_sec_entrypoint;
+ disable_mmu_icache_secure();
+
stm32_pwr_down_wfi(stm32_is_cstop_done(),
stm32mp1_get_lp_soc_mode(PSCI_MODE_SYSTEM_SUSPEND));
stm32_exit_cstop();
- disable_mmu_icache_secure();
-
warm_entrypoint();
}
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 7e2c0ed4e..97f64e772 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -988,3 +988,33 @@ void stm32_set_max_fwu_trial_boot_cnt(void)
clk_disable(RTCAPB);
}
#endif /* PSA_FWU_SUPPORT */
+
+#if STM32MP13
+bool stm32mp_bkpram_get_access(void)
+{
+ static bool state = true;
+
+ if (!state) {
+ return state;
+ }
+
+ clk_enable(RTCAPB);
+
+ if ((mmio_read_32(TAMP_BASE + TAMP_ERCFGR) != 0U) &&
+ (mmio_read_32(TAMP_BASE + TAMP_SR) != 0U) &&
+ (((mmio_read_32(TAMP_BASE + TAMP_CR2) & TAMP_CR2_MASK_NOER) == 0U) ||
+ ((mmio_read_32(TAMP_BASE + TAMP_CR3) & TAMP_CR3_MASK_NOER) == 0U))) {
+ NOTICE("TAMPER detected : Degraded mode\n");
+ state = false;
+ }
+
+ clk_disable(RTCAPB);
+
+ return state;
+}
+#else /* STM32MP15 */
+bool stm32mp_bkpram_get_access(void)
+{
+ return true;
+}
+#endif
diff --git a/plat/st/stm32mp1/stm32mp1_ssp.c b/plat/st/stm32mp1/stm32mp1_ssp.c
index ed1fd8ec0..f9ff52f58 100644
--- a/plat/st/stm32mp1/stm32mp1_ssp.c
+++ b/plat/st/stm32mp1/stm32mp1_ssp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1000,6 +1000,9 @@ void bl2_el3_plat_arch_setup(void)
initialize_pmic();
}
+ stm32_save_boot_interface(boot_context->boot_interface_selected,
+ boot_context->boot_interface_instance);
+
#if DEBUG
if (stm32mp_uart_console_setup() != 0) {
goto skip_console_init;
--
2.25.1

5
recipes-bsp/u-boot/u-boot-stm32mp-common_2021.10.inc
View File

@ -25,7 +25,6 @@ SRC_URI += "\
file://0007-ARM-v2021.10-stm32mp-r2-BOARD.patch \
file://0008-ARM-v2021.10-stm32mp-r2-MISC-DRIVERS.patch \
file://0009-ARM-v2021.10-stm32mp-r2-DEVICETREE.patch \
file://0010-ARM-v2021.10-stm32mp-r2.1.patch \
\
file://0099-Add-external-var-to-allow-build-of-new-devicetree-fi.patch \
"
@ -35,7 +34,7 @@ SRC_URI += "${@bb.utils.contains('ST_UBOOT_DEBUG_TRACE', '1', '', 'file://0098-s
U_BOOT_VERSION = "v2021.10"
U_BOOT_SUBVERSION = "stm32mp"
U_BOOT_RELEASE = "r2.1"
U_BOOT_RELEASE = "r2"
PV = "${U_BOOT_VERSION}-${U_BOOT_SUBVERSION}-${U_BOOT_RELEASE}"
@ -52,7 +51,7 @@ S = "${WORKDIR}/git"
BBCLASSEXTEND = "devupstream:target"
SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/u-boot.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
SRCREV:class-devupstream = "d1bbf3f7edb786fe854034810355e750b08a9851"
SRCREV:class-devupstream = "3984366f6997c680b8c6ccc82d50e77a6e1cccf2"
# ---------------------------------
# Configure default preference to manage dynamic selection between tarball and github

1377
recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2021.10-stm32mp-r2.1.patch
View File

File diff suppressed because it is too large Load Diff

15
recipes-bsp/u-boot/u-boot-stm32mp/0098-silent_mode.patch
View File

@ -1,21 +1,22 @@
From 8ba56fabc89de0df9613c30c8e9d72513a09b017 Mon Sep 17 00:00:00 2001
From: Lionel VITTE <lionel.vitte@st.com>
Date: Thu, 6 Jul 2023 17:38:46 +0200
From 9538ad0348aef5f00cd0a6858873d5ffac2e287f Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@foss.st.com>
Date: Wed, 28 Sep 2022 10:52:51 +0200
Subject: [PATCH] silent_mode
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@foss.st.com>
---
include/configs/stm32mp13_st_common.h | 3 ++-
include/configs/stm32mp15_st_common.h | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index 82a428fe63..1ee1beaae6 100644
index 41681537a2..49d3398663 100644
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h
@@ -10,7 +10,8 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=2000\0" \
"usb_pgood_delay=1000\0" \
- "console=ttySTM0\0"
+ "console=ttySTM0\0" \
+ "silent=1\0"
@ -23,13 +24,13 @@ index 82a428fe63..1ee1beaae6 100644
#include <configs/stm32mp13_common.h>
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index 9865ef5843..2542012148 100644
index c395f7f986..81865b24ea 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -10,7 +10,8 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=2000\0" \
"usb_pgood_delay=1000\0" \
- "console=ttySTM0\0"
+ "console=ttySTM0\0" \
+ "silent=1\0"

4
recipes-core/systemd/systemd-conf_%.bbappend
View File

@ -4,8 +4,6 @@ do_install:append:stm32mpcommon() {
install -d ${D}${systemd_unitdir}/system.conf.d/
echo "[Manager]" > ${D}${systemd_unitdir}/system.conf.d/01-watchdog.conf
echo "RuntimeWatchdogSec=32" >> ${D}${systemd_unitdir}/system.conf.d/01-watchdog.conf
echo "ShutdownWatchdogSec=32" >> ${D}${systemd_unitdir}/system.conf.d/01-watchdog.conf
echo "RebootWatchdogSec=32" >> ${D}${systemd_unitdir}/system.conf.d/01-watchdog.conf
echo "ShutdownWatchdogSec=2min" >> ${D}${systemd_unitdir}/system.conf.d/01-watchdog.conf
fi
}

2
recipes-devtools/cmsis-svd/cmsis-svd_git.bb
View File

@ -17,7 +17,7 @@ NO_GENERIC_LICENSE[svd-STMicro] = "data/STMicro/License.html"
inherit pkgconfig autotools-brokensep gettext
SRC_URI = "git://github.com/posborne/cmsis-svd.git;protocol=https;branch=main"
SRC_URI = "git://github.com/posborne/cmsis-svd.git;protocol=https;branch=master"
SRCREV = "f487b5ca7c132b8f09d11514c509372f83a6cb75"
PV = "0.4+git${SRCPV}"

4
recipes-devtools/gcc/gcc-source_11.4.bbappend
View File

@ -1,4 +0,0 @@
FILESEXTRAPATHS:prepend:stm32mpcommon := "${THISDIR}/gcc:"
SRC_URI += " \
file://0031-make-gcc-plugins-work-for-the-sdk.patch \
"

80
recipes-devtools/gcc/gcc/0031-make-gcc-plugins-work-for-the-sdk.patch
View File

@ -1,80 +0,0 @@
From a426b2c12053304035854184976637a665d3396a Mon Sep 17 00:00:00 2001
From: Lionel VITTE <lionel.vitte@st.com>
Date: Wed, 1 Feb 2023 15:29:23 +0100
Subject: [PATCH] make gcc-plugins work for the sdk
Upstream-Status: Pending
---
config/gcc-plugin.m4 | 11 ++++++++++-
gcc/configure | 12 +++++++++++-
gcc/plugin.c | 5 +++++
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/config/gcc-plugin.m4 b/config/gcc-plugin.m4
index 8f2787191..966d4c14e 100644
--- a/config/gcc-plugin.m4
+++ b/config/gcc-plugin.m4
@@ -77,7 +77,16 @@ AC_DEFUN([GCC_ENABLE_PLUGINS],
AC_MSG_RESULT([$plugin_rdynamic])
fi
else
- AC_MSG_RESULT([unable to check])
+ case "${host}" in
+ *-*-linux*)
+ AC_MSG_RESULT([unable to check, guessing -rdynamic is needed])
+ plugin_rdynamic=yes
+ pluginlibs="-rdynamic"
+ ;;
+ *)
+ AC_MSG_RESULT([unable to check])
+ ;;
+ esac
fi
# Check -ldl
diff --git a/gcc/configure b/gcc/configure
index 27ca7dfa4..a731fbbdc 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -32137,8 +32137,18 @@ $as_echo_n "checking for -rdynamic... " >&6; }
$as_echo "$plugin_rdynamic" >&6; }
fi
else
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: unable to check" >&5
+ case "${host}" in
+ *-*-linux*)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: unable to check, guessing -rdynamic is needed" >&5
+$as_echo "unable to check, guessing -rdynamic is needed" >&6; }
+ plugin_rdynamic=yes
+ pluginlibs="-rdynamic"
+ ;;
+ *)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: unable to check" >&5
$as_echo "unable to check" >&6; }
+ ;;
+ esac
fi
# Check -ldl
diff --git a/gcc/plugin.c b/gcc/plugin.c
index d47fa512a..21a98c223 100644
--- a/gcc/plugin.c
+++ b/gcc/plugin.c
@@ -980,9 +980,14 @@ plugin_default_version_check (struct plugin_gcc_version *gcc_version,
return false;
if (strcmp (gcc_version->revision, plugin_version->revision))
return false;
+#if 0
+ /* In case of a cross compiler, this compares the cross config with the native
+ config, which will always fail, at least for OE. Disable it. */
if (strcmp (gcc_version->configuration_arguments,
plugin_version->configuration_arguments))
return false;
+#endif
+
return true;
}
--
2.17.1

2
recipes-devtools/openocd/openocd-stm32mp_0.11.0.bb
View File

@ -19,5 +19,5 @@ SRC_URI += ""
# To be removed after a new jimtcl release get used by openocd.
do_configure:prepend() {
git add jimtcl
git commit --allow-empty -m "Update jimtcl"
git commit -m "Update jimtcl"
}

4
recipes-graphics/gcnano-userland/gcnano-userland-binary.inc
View File

@ -6,12 +6,12 @@ LIC_FILES_CHKSUM = "file://${GCNANO_TAR_FILENAME}/LICENSE;md5=dd36864f287701862a
DEPENDS += " libdrm wayland "
SRC_URI = "git://github.com/STMicroelectronics/gcnano-binaries;protocol=https;branch=gcnano-${GCNANO_VERSION}-binaries"
SRCREV = "0ac1a89d7a59d040a69745a85f0da7e98644cc4b"
SRCREV = "787d3311e1bae40805fe2091be653eaadf059611"
PV = "${GCNANO_VERSION}+${GCNANO_DATE}"
GCNANO_VERSION = "6.4.9"
GCNANO_DATE = "20221206"
GCNANO_DATE = "20221020"
S = "${WORKDIR}/git"
B = "${S}/${GCNANO_TAR_FILENAME}"

1
recipes-graphics/gcnano-userland/gcnano-userland.inc
View File

@ -8,7 +8,6 @@ PROVIDES = "\
${@bb.utils.contains('GCNANO_PACKAGECONFIG', 'gbm', 'virtual/libgbm', '', d)} \
${@bb.utils.contains('GCNANO_PACKAGECONFIG', 'glesv1', 'virtual/libgles1', '', d)} \
${@bb.utils.contains('GCNANO_PACKAGECONFIG', 'glesv2', 'virtual/libgles2', '', d)} \
${@bb.utils.contains('GCNANO_PACKAGECONFIG', 'glesv2', 'virtual/libgles3', '', d)} \
${@bb.utils.contains('GCNANO_PACKAGECONFIG', 'vg', 'virtual/libopenvg', '', d)} \
"

553
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0013-v5.15-stm32mp-r2.1-MMC.patch
View File

@ -1,553 +0,0 @@
From d366624fc551bb25c4a1a9b94de2408eb75b56fd Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:51:31 +0200
Subject: [PATCH 13/22] v5.15-stm32mp-r2.1 MMC
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
drivers/mmc/host/mmci.c | 70 ++++++++++++-
drivers/mmc/host/mmci.h | 4 +
drivers/mmc/host/mmci_stm32_sdmmc.c | 137 ++++++++++++++++++++-----
drivers/mtd/nand/raw/Kconfig | 2 +-
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 40 +++++++-
5 files changed, 222 insertions(+), 31 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 2c4eda83ca18..05cfc28a5e98 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -270,6 +270,7 @@ static struct variant_data variant_stm32_sdmmc = {
.datactrl_any_blocksz = true,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
.stm32_idmabsize_mask = GENMASK(12, 5),
+ .use_sdio_irq = true,
.busy_timeout = true,
.busy_detect = true,
.busy_detect_flag = MCI_STM32_BUSYD0,
@@ -280,7 +281,7 @@ static struct variant_data variant_stm32_sdmmc = {
static struct variant_data variant_stm32_sdmmcv2 = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
- .f_max = 208000000,
+ .f_max = 267000000,
.stm32_clkdiv = true,
.cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
.cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
@@ -296,6 +297,7 @@ static struct variant_data variant_stm32_sdmmcv2 = {
.datactrl_any_blocksz = true,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
.stm32_idmabsize_mask = GENMASK(16, 5),
+ .use_sdio_irq = true,
.dma_lli = true,
.busy_timeout = true,
.busy_detect = true,
@@ -392,6 +394,10 @@ static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
/* Keep busy mode in DPSM if enabled */
datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
+ /* Keep SD I/O interrupt mode enabled */
+ if (host->variant->use_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ)
+ datactrl |= host->variant->datactrl_mask_sdio;
+
if (host->datactrl_reg != datactrl) {
host->datactrl_reg = datactrl;
writel(datactrl, host->base + MMCIDATACTRL);
@@ -1644,6 +1650,11 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
mmci_data_irq(host, host->data, status);
}
+ if (host->variant->use_sdio_irq &&
+ host->mmc->caps & MMC_CAP_SDIO_IRQ &&
+ host->ops && host->ops->sdio_irq)
+ host->ops->sdio_irq(host, status);
+
/*
* Busy detection has been handled by mmci_cmd_irq() above.
* Clear the status bit to prevent polling in IRQ context.
@@ -1729,7 +1740,8 @@ static void mmci_set_max_busy_timeout(struct mmc_host *mmc)
return;
if (host->variant->busy_timeout && mmc->actual_clock)
- max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC);
+ max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock,
+ MSEC_PER_SEC);
mmc->max_busy_timeout = max_busy_timeout;
}
@@ -1883,6 +1895,45 @@ static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
return ret;
}
+static void mmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct mmci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ if (!host->variant->use_sdio_irq)
+ return;
+
+ if (host->ops && host->ops->enable_sdio_irq) {
+ if (enable)
+ /* Keep device active while SDIO IRQ is enabled */
+ pm_runtime_get_sync(mmc_dev(mmc));
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->ops->enable_sdio_irq(host, enable);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ if (!enable) {
+ pm_runtime_mark_last_busy(mmc_dev(mmc));
+ pm_runtime_put_autosuspend(mmc_dev(mmc));
+ }
+ }
+}
+
+static void mmci_ack_sdio_irq(struct mmc_host *mmc)
+{
+ struct mmci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ if (!host->variant->use_sdio_irq)
+ return;
+
+ if (host->ops && host->ops->enable_sdio_irq) {
+ spin_lock_irqsave(&host->lock, flags);
+ host->ops->enable_sdio_irq(host, 1);
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+}
+
static struct mmc_host_ops mmci_ops = {
.request = mmci_request,
.pre_req = mmci_pre_request,
@@ -1891,6 +1942,8 @@ static struct mmc_host_ops mmci_ops = {
.get_ro = mmc_gpio_get_ro,
.get_cd = mmci_get_cd,
.start_signal_voltage_switch = mmci_sig_volt_switch,
+ .enable_sdio_irq = mmci_enable_sdio_irq,
+ .ack_sdio_irq = mmci_ack_sdio_irq,
};
static void mmci_probe_level_translator(struct mmc_host *mmc)
@@ -2158,6 +2211,14 @@ static int mmci_probe(struct amba_device *dev,
mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
}
+ if (variant->use_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) {
+ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+
+ if (variant->datactrl_mask_sdio)
+ mmci_write_datactrlreg(host,
+ host->variant->datactrl_mask_sdio);
+ }
+
/* Variants with mandatory busy timeout in HW needs R1B responses. */
if (variant->busy_timeout)
mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
@@ -2433,6 +2494,11 @@ static const struct amba_id mmci_ids[] = {
.mask = 0xf0ffffff,
.data = &variant_stm32_sdmmcv2,
},
+ {
+ .id = 0x20253180,
+ .mask = 0xf0ffffff,
+ .data = &variant_stm32_sdmmcv2,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index e1a9b96a3396..a710cd686cb2 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -316,6 +316,7 @@ struct mmci_host;
* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
* @dma_lli: true if variant has dma link list feature.
* @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
+ * @use_sdio_irq: allow SD I/O card to interrupt the host
*/
struct variant_data {
unsigned int clkreg;
@@ -360,6 +361,7 @@ struct variant_data {
u32 start_err;
u32 opendrain;
u8 dma_lli:1;
+ u8 use_sdio_irq:1;
u32 stm32_idmabsize_mask;
void (*init)(struct mmci_host *host);
};
@@ -383,6 +385,8 @@ struct mmci_host_ops {
bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
void (*pre_sig_volt_switch)(struct mmci_host *host);
int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios);
+ void (*enable_sdio_irq)(struct mmci_host *host, int enable);
+ void (*sdio_irq)(struct mmci_host *host, u32 status);
};
struct mmci_host {
diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index 4cceb9bab036..0cc33b172080 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -43,6 +43,9 @@ struct sdmmc_lli_desc {
struct sdmmc_idma {
dma_addr_t sg_dma;
void *sg_cpu;
+ dma_addr_t bounce_dma_addr;
+ void *bounce_buf;
+ bool use_bounce_buffer;
};
struct sdmmc_dlyb {
@@ -54,6 +57,8 @@ struct sdmmc_dlyb {
static int sdmmc_idma_validate_data(struct mmci_host *host,
struct mmc_data *data)
{
+ struct sdmmc_idma *idma = host->dma_priv;
+ struct device *dev = mmc_dev(host->mmc);
struct scatterlist *sg;
int i;
@@ -61,41 +66,69 @@ static int sdmmc_idma_validate_data(struct mmci_host *host,
* idma has constraints on idmabase & idmasize for each element
* excepted the last element which has no constraint on idmasize
*/
+ idma->use_bounce_buffer = false;
for_each_sg(data->sg, sg, data->sg_len - 1, i) {
if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
!IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) {
- dev_err(mmc_dev(host->mmc),
+ dev_dbg(mmc_dev(host->mmc),
"unaligned scatterlist: ofst:%x length:%d\n",
data->sg->offset, data->sg->length);
- return -EINVAL;
+ goto use_bounce_buffer;
}
}
if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
- dev_err(mmc_dev(host->mmc),
+ dev_dbg(mmc_dev(host->mmc),
"unaligned last scatterlist: ofst:%x length:%d\n",
data->sg->offset, data->sg->length);
- return -EINVAL;
+ goto use_bounce_buffer;
}
+ return 0;
+
+use_bounce_buffer:
+ if (!idma->bounce_buf) {
+ idma->bounce_buf = dmam_alloc_coherent(dev,
+ host->mmc->max_req_size,
+ &idma->bounce_dma_addr,
+ GFP_KERNEL);
+ if (!idma->bounce_buf) {
+ dev_err(dev, "Unable to map allocate DMA bounce buffer.\n");
+ return -ENOMEM;
+ }
+ }
+
+ idma->use_bounce_buffer = true;
+
return 0;
}
static int _sdmmc_idma_prep_data(struct mmci_host *host,
struct mmc_data *data)
{
- int n_elem;
+ struct sdmmc_idma *idma = host->dma_priv;
- n_elem = dma_map_sg(mmc_dev(host->mmc),
- data->sg,
- data->sg_len,
- mmc_get_dma_dir(data));
+ if (idma->use_bounce_buffer) {
+ if (data->flags & MMC_DATA_WRITE) {
+ unsigned int xfer_bytes = data->blksz * data->blocks;
- if (!n_elem) {
- dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
- return -EINVAL;
- }
+ sg_copy_to_buffer(data->sg, data->sg_len,
+ idma->bounce_buf, xfer_bytes);
+ dma_wmb();
+ }
+ } else {
+ int n_elem;
+
+ n_elem = dma_map_sg(mmc_dev(host->mmc),
+ data->sg,
+ data->sg_len,
+ mmc_get_dma_dir(data));
+ if (!n_elem) {
+ dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
+ return -EINVAL;
+ }
+ }
return 0;
}
@@ -112,8 +145,19 @@ static int sdmmc_idma_prep_data(struct mmci_host *host,
static void sdmmc_idma_unprep_data(struct mmci_host *host,
struct mmc_data *data, int err)
{
- dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
- mmc_get_dma_dir(data));
+ struct sdmmc_idma *idma = host->dma_priv;
+
+ if (idma->use_bounce_buffer) {
+ if (data->flags & MMC_DATA_READ) {
+ unsigned int xfer_bytes = data->blksz * data->blocks;
+
+ sg_copy_from_buffer(data->sg, data->sg_len,
+ idma->bounce_buf, xfer_bytes);
+ }
+ } else {
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+ mmc_get_dma_dir(data));
+ }
}
static int sdmmc_idma_setup(struct mmci_host *host)
@@ -137,6 +181,8 @@ static int sdmmc_idma_setup(struct mmci_host *host)
host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
sizeof(struct sdmmc_lli_desc);
host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
+
+ host->mmc->max_req_size = SZ_1M;
} else {
host->mmc->max_segs = 1;
host->mmc->max_seg_size = host->mmc->max_req_size;
@@ -154,8 +200,16 @@ static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
struct scatterlist *sg;
int i;
- if (!host->variant->dma_lli || data->sg_len == 1) {
- writel_relaxed(sg_dma_address(data->sg),
+ if (!host->variant->dma_lli || data->sg_len == 1 ||
+ idma->use_bounce_buffer) {
+ u32 dma_addr;
+
+ if (idma->use_bounce_buffer)
+ dma_addr = idma->bounce_dma_addr;
+ else
+ dma_addr = sg_dma_address(data->sg);
+
+ writel_relaxed(dma_addr,
host->base + MMCI_STM32_IDMABASE0R);
writel_relaxed(MMCI_STM32_IDMAEN,
host->base + MMCI_STM32_IDMACTRLR);
@@ -239,17 +293,8 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
clk |= host->clk_reg_add;
clk |= ddr;
- /*
- * SDMMC_FBCK is selected when an external Delay Block is needed
- * with SDR104.
- */
- if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
+ if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50)
clk |= MCI_STM32_CLK_BUSSPEED;
- if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
- clk &= ~MCI_STM32_CLK_SEL_MSK;
- clk |= MCI_STM32_CLK_SELFBCK;
- }
- }
mmci_write_clkreg(host, clk);
}
@@ -456,10 +501,27 @@ static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct mmci_host *host = mmc_priv(mmc);
struct sdmmc_dlyb *dlyb = host->variant_priv;
+ u32 clk;
+
+ if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 &&
+ host->mmc->ios.timing != MMC_TIMING_MMC_HS200) ||
+ host->mmc->actual_clock <= 50000000)
+ return 0;
if (!dlyb || !dlyb->base)
return -EINVAL;
+ writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
+
+ /*
+ * SDMMC_FBCK is selected when an external Delay Block is needed
+ * with SDR104 or HS200.
+ */
+ clk = host->clk_reg;
+ clk &= ~MCI_STM32_CLK_SEL_MSK;
+ clk |= MCI_STM32_CLK_SELFBCK;
+ mmci_write_clkreg(host, clk);
+
if (sdmmc_dlyb_lng_tuning(host))
return -EINVAL;
@@ -504,6 +566,25 @@ static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
return ret;
}
+static void sdmmc_enable_sdio_irq(struct mmci_host *host, int enable)
+{
+ void __iomem *base = host->base;
+ u32 mask = readl_relaxed(base + MMCIMASK0);
+
+ if (enable)
+ writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);
+ else
+ writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0);
+}
+
+static void sdmmc_sdio_irq(struct mmci_host *host, u32 status)
+{
+ if (status & MCI_ST_SDIOIT) {
+ sdmmc_enable_sdio_irq(host, 0);
+ sdio_signal_irq(host->mmc);
+ }
+}
+
static struct mmci_host_ops sdmmc_variant_ops = {
.validate_data = sdmmc_idma_validate_data,
.prep_data = sdmmc_idma_prep_data,
@@ -517,6 +598,8 @@ static struct mmci_host_ops sdmmc_variant_ops = {
.busy_complete = sdmmc_busy_complete,
.pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
.post_sig_volt_switch = sdmmc_post_sig_volt_switch,
+ .enable_sdio_irq = sdmmc_enable_sdio_irq,
+ .sdio_irq = sdmmc_sdio_irq,
};
void sdmmc_variant_init(struct mmci_host *host)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 67b7cb67c030..dccb86e577a3 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -385,7 +385,7 @@ config MTD_NAND_TEGRA
config MTD_NAND_STM32_FMC2
tristate "Support for NAND controller on STM32MP SoCs"
- depends on MACH_STM32MP157 || COMPILE_TEST
+ depends on ARCH_STM32 || COMPILE_TEST
select MFD_SYSCON
help
Enables support for NAND Flash chips on SoCs containing the FMC2
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 1ac8c4887ce0..7c491e5a661d 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -9,6 +9,7 @@
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
@@ -231,6 +232,7 @@ struct stm32_fmc2_timings {
struct stm32_fmc2_nand {
struct nand_chip chip;
+ struct gpio_desc *wp_gpio;
struct stm32_fmc2_timings timings;
int ncs;
int cs_used[FMC2_MAX_CE];
@@ -1750,6 +1752,18 @@ static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
.setup_interface = stm32_fmc2_nfc_setup_interface,
};
+static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 1);
+}
+
+static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 0);
+}
+
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
struct device_node *dn)
{
@@ -1788,6 +1802,18 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
nand->cs_used[i] = cs;
}
+ nand->wp_gpio = devm_gpiod_get_from_of_node(nfc->dev, dn,
+ "wp-gpios", 0,
+ GPIOD_OUT_HIGH, "wp");
+ if (IS_ERR(nand->wp_gpio)) {
+ ret = PTR_ERR(nand->wp_gpio);
+ if (ret != -ENOENT)
+ return dev_err_probe(nfc->dev, ret,
+ "failed to request WP GPIO\n");
+
+ nand->wp_gpio = NULL;
+ }
+
nand_set_flash_node(&nand->chip, dn);
return 0;
@@ -1963,10 +1989,12 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
NAND_USES_DMA;
+ stm32_fmc2_nfc_wp_disable(nand);
+
/* Scan to find existence of the device */
ret = nand_scan(chip, nand->ncs);
if (ret)
- goto err_release_dma;
+ goto err_wp_enable;
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
@@ -1979,6 +2007,9 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
err_nand_cleanup:
nand_cleanup(chip);
+err_wp_enable:
+ stm32_fmc2_nfc_wp_enable(nand);
+
err_release_dma:
if (nfc->dma_ecc_ch)
dma_release_channel(nfc->dma_ecc_ch);
@@ -2019,15 +2050,20 @@ static int stm32_fmc2_nfc_remove(struct platform_device *pdev)
clk_disable_unprepare(nfc->clk);
+ stm32_fmc2_nfc_wp_enable(nand);
+
return 0;
}
static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
{
struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
+ struct stm32_fmc2_nand *nand = &nfc->nand;
clk_disable_unprepare(nfc->clk);
+ stm32_fmc2_nfc_wp_enable(nand);
+
pinctrl_pm_select_sleep_state(dev);
return 0;
@@ -2049,6 +2085,8 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
stm32_fmc2_nfc_init(nfc);
+ stm32_fmc2_nfc_wp_disable(nand);
+
for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
if (!(nfc->cs_assigned & BIT(chip_cs)))
continue;
--
2.17.1

10
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0001-v5.15-stm32mp-r2.1-MACHINE.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0001-v5.15-stm32mp-r2-MACHINE.patch
View File

@ -1,9 +1,9 @@
From 79ae410c50b3664a3006547c2235128e5f4736d1 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:34:11 +0200
Subject: [PATCH 01/22] v5.15-stm32mp-r2.1 MACHINE
From 84827f5873b8cd852cc79177e9a42b12760b3723 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 13 Oct 2022 12:22:34 +0200
Subject: [PATCH 01/22] v5.15-stm32mp-r2 MACHINE
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
Documentation/arm/index.rst | 1 +
.../arm/stm32/stm32mp13-overview.rst | 37 +++++++++++++++++++

12
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0002-v5.15-stm32mp-r2.1-CLOCK.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0002-v5.15-stm32mp-r2-CLOCK.patch
View File

@ -1,9 +1,9 @@
From b931df769e83687f9676f7fbe0154b9a88c3812e Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:35:04 +0200
Subject: [PATCH 02/22] v5.15-stm32mp-r2.1 CLOCK
From 7fce50075a5475b4af7b4918076e0577457530c9 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:22:35 +0100
Subject: [PATCH 02/22] v5.15-stm32mp-r2 CLOCK
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/clk/Kconfig | 5 +
drivers/clk/Makefile | 1 +
@ -32,7 +32,7 @@ Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 100e474ff3dc..0a93f074cede 100644
index c5b3dc97396a..c23287f7d108 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -334,6 +334,11 @@ config COMMON_CLK_VC5

87
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0003-v5.15-stm32mp-r2.1-CPUFREQ.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0003-v5.15-stm32mp-r2-CPUFREQ.patch
View File

@ -1,17 +1,86 @@
From 3297b2b5cfda8baab37e49aadea8b6fc6a755326 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:35:55 +0200
Subject: [PATCH 03/22] v5.15-stm32mp-r2.1 CPUFREQ
From 7b129c9db71e9dcb515a4585861898b6a3644f1b Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:23:32 +0100
Subject: [PATCH 03/22] v5.15-stm32mp-r2 CPUFREQ
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../bindings/cpufreq/stm32-cpufreq.txt | 61 +++++++++++
drivers/cpufreq/Kconfig.arm | 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/stm32-cpufreq.c | 103 +++++++++++++++++++++++++++
4 files changed, 112 insertions(+)
drivers/cpufreq/stm32-cpufreq.c | 103 ++++++++++++++++++
5 files changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
create mode 100644 drivers/cpufreq/stm32-cpufreq.c
diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
new file mode 100644
index 000000000000..1292eb2612a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
@@ -0,0 +1,61 @@
+STM32 CPUFreq and OPP bindings
+==============================
+
+STM32 CPUFreq driver needs to read chip information from the SoC to list
+available OPPs. Then it depends on cpufreq-dt bindings.
+
+Required properties:
+--------------------
+- clocks: Phandle to the cpu clock "cpu".
+- clocks-name: Should contain "cpu".
+- nvmem-cells: Phandle to nvmem cell that contains "part_number".
+- nvmem-cell-names: Must be "part_number".
+- operating-points-v2: Phandle to operating points table. See ../power/opp.txt
+ for more details.
+
+Optional properties:
+--------------------
+See cpufreq-dt.txt for optional properties.
+
+Examples:
+---------
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ };
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 954749afb5fe..eac08e90768c 100644
--- a/drivers/cpufreq/Kconfig.arm
@ -43,10 +112,10 @@ index 48ee5859030c..d34de1b927bf 100644
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e1b5975c7daa..9e3cd2746eeb 100644
index ca1d103ec449..f205e6e9703e 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -152,6 +152,7 @@ static const struct of_device_id blocklist[] __initconst = {
@@ -150,6 +150,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "st,stih407", },
{ .compatible = "st,stih410", },
{ .compatible = "st,stih418", },

10
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0004-v5.15-stm32mp-r2.1-CPUIDLE-POWER.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0004-v5.15-stm32mp-r2-CPUIDLE-POWER.patch
View File

@ -1,9 +1,9 @@
From 06dab8c8240a3a813f147ce5daa94b64eaf9ff9f Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:37:00 +0200
Subject: [PATCH 04/22] v5.15-stm32mp-r2.1 CPUIDLE-POWER
From dc62943bb269dbe5f3294beda26e299bb00f0e97 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:49:53 +0100
Subject: [PATCH 04/22] v5.15-stm32mp-r2 CPUIDLE-POWER
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/cpuidle/Kconfig.arm | 8 +
drivers/cpuidle/Makefile | 1 +

50
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0005-v5.15-stm32mp-r2.1-CRYPTO.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0005-v5.15-stm32mp-r2-CRYPTO.patch
View File

@ -1,14 +1,48 @@
From 313fd2a08ceee58571f3af89fbb740710cb9db42 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:37:32 +0200
Subject: [PATCH 05/22] v5.15-stm32mp-r2.1 CRYPTO
From 0d2fcaf7ef322a9caec811097a3877d9a89eaae4 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:26:07 +0100
Subject: [PATCH 05/22] v5.15-stm32mp-r2 CRYPTO
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/crypto/stm32/stm32-cryp.c | 741 ++++++++++++++++++++--
drivers/crypto/stm32/stm32-hash.c | 999 +++++++++++++++++++++---------
2 files changed, 1399 insertions(+), 341 deletions(-)
.../bindings/crypto/st,stm32-cryp.yaml | 9 +
.../bindings/crypto/st,stm32-hash.yaml | 1 +
drivers/crypto/stm32/stm32-cryp.c | 741 ++++++++++++-
drivers/crypto/stm32/stm32-hash.c | 999 ++++++++++++------
4 files changed, 1409 insertions(+), 341 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
index a4574552502a..6c3f8f7bfd67 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
@@ -27,6 +27,15 @@ properties:
resets:
maxItems: 1
+ dmas:
+ maxItems: 2
+ minItems: 2
+
+ dma-names:
+ items:
+ - const: in
+ - const: out
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 6dd658f0912c..1a944608d8ff 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- st,stm32f456-hash
- st,stm32f756-hash
+ - st,stm32mp13-hash
reg:
maxItems: 1
diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c
index 81eb136b6c11..d76641596db4 100644
--- a/drivers/crypto/stm32/stm32-cryp.c

134
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0006-v5.15-stm32mp-r2.1-DMA.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0006-v5.15-stm32mp-r2-DMA.patch
View File

@ -1,15 +1,133 @@
From a5162908ea9e9ed9fdcb92fc16a979e9ddd6997d Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:39:12 +0200
Subject: [PATCH 06/22] v5.15-stm32mp-r2.1 DMA
From 62911b17f33f57875c1b18ed211d5fa0f731ad42 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:26:34 +0100
Subject: [PATCH 06/22] v5.15-stm32mp-r2 DMA
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/dma/stm32-dma.c | 1169 ++++++++++++++++++++++++++++++++----
.../devicetree/bindings/dma/st,stm32-dma.yaml | 47 +
.../bindings/dma/st,stm32-mdma.yaml | 12 +-
drivers/dma/stm32-dma.c | 1169 +++++++++++++++--
drivers/dma/stm32-dmamux.c | 2 +-
drivers/dma/stm32-mdma.c | 147 ++++-
3 files changed, 1185 insertions(+), 133 deletions(-)
drivers/dma/stm32-mdma.c | 147 ++-
5 files changed, 1240 insertions(+), 137 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 4bf676fd25dc..99351fe0fa17 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -47,6 +47,14 @@ description: |
not wait for the de-assertion of the REQuest, ACK is only managed
by transfer completion. This must only be used on channels
managing transfers for STM32 USART/UART.
+ -bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
+ Order is given by those 2 bits starting at 0.
+ Valid only whether Intermediate M2M transfer is set.
+ For cyclic, whether Intermediate M2M transfer is chosen, any value can be set:
+ SRAM buffer size will rely on period size and not on this DT value.
+ -bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
+ 0: MDMA not used to generate an intermediate M2M transfer
+ 1: MDMA used to generate an intermediate M2M transfer.
maintainers:
@@ -82,6 +90,35 @@ properties:
description: if defined, it indicates that the controller
supports memory-to-memory transfer
+ dmas:
+ description: A list of eight dma specifiers, one for each entry in dma-names.
+ Refer to stm32-mdma.yaml for more details.
+ items:
+ - description: DMA channel 0 connected to the MDMA channel specified
+ - description: DMA channel 1 connected to the MDMA channel specified
+ - description: DMA channel 2 connected to the MDMA channel specified
+ - description: DMA channel 3 connected to the MDMA channel specified
+ - description: DMA channel 4 connected to the MDMA channel specified
+ - description: DMA channel 5 connected to the MDMA channel specified
+ - description: DMA channel 6 connected to the MDMA channel specified
+ - description: DMA channel 7 connected to the MDMA channel specified
+
+ dma-names:
+ description: Represents each STM32 DMA channel connected to a STM32 MDMA one.
+ items:
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+
+ memory-region:
+ description: Phandle to a node describing memory to be used for M2M intermediate transfer
+ between DMA and MDMA.
+
required:
- compatible
- reg
@@ -111,6 +148,16 @@ examples:
st,mem2mem;
resets = <&rcc 150>;
dma-requests = <8>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x40026408 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x40026408 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x40026408 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x40026408 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4002640C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4002640C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4002640C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4002640C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ memory-region = <&sram_dmapool>;
};
...
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
index c30be840be1c..c4bb58014374 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
@@ -10,8 +10,8 @@ description: |
The STM32 MDMA is a general-purpose direct memory access controller capable of
supporting 64 independent DMA channels with 256 HW requests.
DMA clients connected to the STM32 MDMA controller must use the format
- described in the dma.txt file, using a five-cell specifier for each channel:
- a phandle to the MDMA controller plus the following five integer cells:
+ described in the dma.txt file, using a six-cell specifier for each channel:
+ a phandle to the MDMA controller plus the following six integer cells:
1. The request line number
2. The priority level
0x0: Low
@@ -48,6 +48,10 @@ description: |
if no HW ack signal is used by the MDMA client
5. A 32bit mask specifying the value to be written to acknowledge the request
if no HW ack signal is used by the MDMA client
+ 6. A bitfield value specifying if the MDMA client wants to generate M2M transfer
+ with HW trigger (1) or not (0). This bitfield should be only enabled for
+ M2M transfer triggered by STM32 DMA client. The memory devices involved in this
+ kind of transfer are SRAM and DDR.
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
@@ -57,7 +61,7 @@ allOf:
properties:
"#dma-cells":
- const: 5
+ const: 6
compatible:
const: st,stm32h7-mdma
@@ -97,7 +101,7 @@ examples:
interrupts = <122>;
clocks = <&timer_clk>;
resets = <&rcc 992>;
- #dma-cells = <5>;
+ #dma-cells = <6>;
dma-channels = <16>;
dma-requests = <32>;
st,ahb-addr-masks = <0x20000000>, <0x00000000>;
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 7dfc743ac433..7c6078c6c3bf 100644
--- a/drivers/dma/stm32-dma.c

520
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0007-v5.15-stm32mp-r2.1-DRM.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0007-v5.15-stm32mp-r2-DRM.patch
View File

@ -1,9 +1,9 @@
From 6c74d8a9e9dd425dc13d45fcd0c95e0b7dda589b Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:40:32 +0200
Subject: [PATCH 07/22] v5.15-stm32mp-r2.1 DRM
From 1f085af24db6752b0028d1aea4a451f772922b12 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:27:37 +0100
Subject: [PATCH 07/22] v5.15-stm32mp-r2 DRM
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/gpu/drm/bridge/sii902x.c | 100 +-
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 5 +-
@ -12,19 +12,19 @@ Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
drivers/gpu/drm/drm_connector.c | 62 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/panel/panel-orisetech-otm8009a.c | 163 ++-
drivers/gpu/drm/panel/panel-raydium-rm68200.c | 76 +-
drivers/gpu/drm/panel/panel-rocktech-hx8394.c | 432 +++++++
.../gpu/drm/panel/panel-orisetech-otm8009a.c | 101 +-
drivers/gpu/drm/panel/panel-raydium-rm68200.c | 7 +-
drivers/gpu/drm/panel/panel-rocktech-hx8394.c | 397 ++++++
drivers/gpu/drm/panel/panel-simple.c | 16 +
drivers/gpu/drm/stm/drv.c | 6 +
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 118 +-
drivers/gpu/drm/stm/ltdc.c | 1143 ++++++++++++++---
drivers/gpu/drm/stm/ltdc.c | 1118 ++++++++++++++---
drivers/gpu/drm/stm/ltdc.h | 25 +-
drivers/video/backlight/gpio_backlight.c | 7 +-
drivers/video/fbdev/simplefb.c | 21 +-
include/drm/bridge/dw_mipi_dsi.h | 4 +-
include/drm/drm_connector.h | 14 +
19 files changed, 1918 insertions(+), 298 deletions(-)
19 files changed, 1763 insertions(+), 262 deletions(-)
create mode 100644 drivers/gpu/drm/panel/panel-rocktech-hx8394.c
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c
@ -252,7 +252,7 @@ index f195c7013137..9301aa72e6cb 100644
*val = state->hdr_output_metadata ?
state->hdr_output_metadata->base.id : 0;
diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
index 78bc315b0b73..f240af91d401 100644
index 7ee29f073857..798d2cff102f 100644
--- a/drivers/gpu/drm/drm_bridge.c
+++ b/drivers/gpu/drm/drm_bridge.c
@@ -227,11 +227,13 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge,
@ -274,10 +274,10 @@ index 78bc315b0b73..f240af91d401 100644
return ret;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index cfe163103cfd..185df70e94b9 100644
index e9b7926d9b66..c035729fa995 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -827,6 +827,12 @@ static const struct drm_prop_enum_list drm_scaling_mode_enum_list[] = {
@@ -824,6 +824,12 @@ static const struct drm_prop_enum_list drm_scaling_mode_enum_list[] = {
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
@ -290,7 +290,7 @@ index cfe163103cfd..185df70e94b9 100644
static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
{ DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
{ DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
@@ -1779,6 +1785,62 @@ int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
@@ -1776,6 +1782,62 @@ int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_attach_scaling_mode_property);
@ -386,18 +386,10 @@ index c8132050bcec..57d7948975c2 100644
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index f8dbccd55033..e75d2fdc678f 100644
index f80b44a8a700..70b2bb72dbbc 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -10,6 +10,7 @@
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
@@ -60,6 +61,9 @@
@@ -60,6 +60,9 @@
#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
@ -407,7 +399,7 @@ index f8dbccd55033..e75d2fdc678f 100644
struct otm8009a {
struct device *dev;
struct drm_panel panel;
@@ -70,19 +74,35 @@ struct otm8009a {
@@ -70,19 +73,35 @@ struct otm8009a {
bool enabled;
};
@ -456,7 +448,7 @@ index f8dbccd55033..e75d2fdc678f 100644
};
static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
@@ -208,12 +228,11 @@ static int otm8009a_init_sequence(struct otm8009a *ctx)
@@ -208,12 +227,11 @@ static int otm8009a_init_sequence(struct otm8009a *ctx)
/* Default portrait 480x800 rgb24 */
dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
@ -471,52 +463,7 @@ index f8dbccd55033..e75d2fdc678f 100644
if (ret)
return ret;
@@ -272,16 +291,15 @@ static int otm8009a_disable(struct drm_panel *panel)
static int otm8009a_unprepare(struct drm_panel *panel)
{
struct otm8009a *ctx = panel_to_otm8009a(panel);
+ int ret;
if (!ctx->prepared)
return 0;
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- }
-
- regulator_disable(ctx->supply);
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
ctx->prepared = false;
@@ -296,20 +314,12 @@ static int otm8009a_prepare(struct drm_panel *panel)
if (ctx->prepared)
return 0;
- ret = regulator_enable(ctx->supply);
+ ret = pm_runtime_get_sync(panel->dev);
if (ret < 0) {
- dev_err(panel->dev, "failed to enable supply: %d\n", ret);
+ pm_runtime_put_autosuspend(panel->dev);
return ret;
}
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- msleep(100);
- }
-
ret = otm8009a_init_sequence(ctx);
if (ret)
return ret;
@@ -337,24 +347,35 @@ static int otm8009a_get_modes(struct drm_panel *panel,
@@ -337,24 +355,35 @@ static int otm8009a_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct drm_display_mode *mode;
@ -565,7 +512,7 @@ index f8dbccd55033..e75d2fdc678f 100644
}
static const struct drm_panel_funcs otm8009a_drm_funcs = {
@@ -419,8 +440,10 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
@@ -419,8 +448,18 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset_gpio)) {
@ -575,92 +522,22 @@ index f8dbccd55033..e75d2fdc678f 100644
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "cannot get reset GPIO: %d\n", ret);
+ return ret;
+ }
+
+ /* Reset the panel to avoid visual artifacts */
+ if (ctx->reset_gpio) {
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
}
ctx->supply = devm_regulator_get(dev, "power");
@@ -467,6 +490,10 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
return 0;
}
@@ -477,9 +504,50 @@ static int otm8009a_remove(struct mipi_dsi_device *dsi)
mipi_dsi_detach(dsi);
drm_panel_remove(&ctx->panel);
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
return 0;
}
+static __maybe_unused int orisetech_otm8009a_suspend(struct device *dev)
+{
+ struct otm8009a *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int orisetech_otm8009a_resume(struct device *dev)
+{
+ struct otm8009a *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(100);
+
+ return 0;
+}
+
+static const struct dev_pm_ops orisetech_otm8009a_pm_ops = {
+ SET_RUNTIME_PM_OPS(orisetech_otm8009a_suspend, orisetech_otm8009a_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
static const struct of_device_id orisetech_otm8009a_of_match[] = {
{ .compatible = "orisetech,otm8009a" },
{ }
@@ -492,6 +560,7 @@ static struct mipi_dsi_driver orisetech_otm8009a_driver = {
.driver = {
.name = "panel-orisetech-otm8009a",
.of_match_table = orisetech_otm8009a_of_match,
+ .pm = &orisetech_otm8009a_pm_ops,
},
};
module_mipi_dsi_driver(orisetech_otm8009a_driver);
diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index 412c0dbcb2b6..6bd2c6406e4a 100644
index 412c0dbcb2b6..d5542266e754 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -10,6 +10,7 @@
#include <linux/gpio/consumer.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
@@ -91,7 +92,7 @@ static const struct drm_display_mode default_mode = {
@@ -91,7 +91,7 @@ static const struct drm_display_mode default_mode = {
.vsync_start = 1280 + 12,
.vsync_end = 1280 + 12 + 5,
.vtotal = 1280 + 12 + 5 + 12,
@ -669,48 +546,7 @@ index 412c0dbcb2b6..6bd2c6406e4a 100644
.width_mm = 68,
.height_mm = 122,
};
@@ -260,14 +261,10 @@ static int rm68200_unprepare(struct drm_panel *panel)
if (ret)
dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
- msleep(120);
-
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- }
-
- regulator_disable(ctx->supply);
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
ctx->prepared = false;
@@ -283,19 +280,12 @@ static int rm68200_prepare(struct drm_panel *panel)
if (ctx->prepared)
return 0;
- ret = regulator_enable(ctx->supply);
+ ret = pm_runtime_get_sync(panel->dev);
if (ret < 0) {
- dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ pm_runtime_put_autosuspend(panel->dev);
return ret;
}
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- msleep(100);
- }
-
rm68200_init_sequence(ctx);
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
@@ -347,6 +337,8 @@ static int rm68200_get_modes(struct drm_panel *panel,
@@ -347,6 +347,8 @@ static int rm68200_get_modes(struct drm_panel *panel,
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
@ -719,7 +555,7 @@ index 412c0dbcb2b6..6bd2c6406e4a 100644
return 1;
}
@@ -372,7 +364,8 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
@@ -372,7 +374,8 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset_gpio)) {
ret = PTR_ERR(ctx->reset_gpio);
@ -729,81 +565,12 @@ index 412c0dbcb2b6..6bd2c6406e4a 100644
return ret;
}
@@ -409,6 +402,10 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
return 0;
}
@@ -419,9 +416,49 @@ static int rm68200_remove(struct mipi_dsi_device *dsi)
mipi_dsi_detach(dsi);
drm_panel_remove(&ctx->panel);
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
return 0;
}
+static __maybe_unused int raydium_rm68200_suspend(struct device *dev)
+{
+ struct rm68200 *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int raydium_rm68200_resume(struct device *dev)
+{
+ struct rm68200 *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(100);
+
+ return 0;
+}
+
+static const struct dev_pm_ops raydium_rm68200_pm_ops = {
+ SET_RUNTIME_PM_OPS(raydium_rm68200_suspend, raydium_rm68200_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
static const struct of_device_id raydium_rm68200_of_match[] = {
{ .compatible = "raydium,rm68200" },
{ }
@@ -434,6 +471,7 @@ static struct mipi_dsi_driver raydium_rm68200_driver = {
.driver = {
.name = "panel-raydium-rm68200",
.of_match_table = raydium_rm68200_of_match,
+ .pm = &raydium_rm68200_pm_ops,
},
};
module_mipi_dsi_driver(raydium_rm68200_driver);
diff --git a/drivers/gpu/drm/panel/panel-rocktech-hx8394.c b/drivers/gpu/drm/panel/panel-rocktech-hx8394.c
new file mode 100644
index 000000000000..29a64a546364
index 000000000000..6a5926cc79ba
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-rocktech-hx8394.c
@@ -0,0 +1,432 @@
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics SA 2022
@ -815,7 +582,6 @@ index 000000000000..29a64a546364
+#include <linux/gpio/consumer.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
@ -1014,12 +780,19 @@ index 000000000000..29a64a546364
+ if (ctx->prepared)
+ return 0;
+
+ ret = pm_runtime_get_sync(panel->dev);
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ pm_runtime_put_autosuspend(panel->dev);
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ if (ctx->reset_gpio) {
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(1);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(50);
+ }
+
+ ret = hx8394_read_id(ctx);
+ if (ret < 0)
+ return ret;
@ -1064,10 +837,14 @@ index 000000000000..29a64a546364
+ if (ret)
+ dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
+
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
+ msleep(120);
+
+ if (ctx->reset_gpio) {
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ }
+
+ regulator_disable(ctx->supply);
+
+ ctx->prepared = false;
+
@ -1159,10 +936,6 @@ index 000000000000..29a64a546364
+ return ret;
+ }
+
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
+ return 0;
+}
+
@ -1173,49 +946,9 @@ index 000000000000..29a64a546364
+ mipi_dsi_detach(dsi);
+ drm_panel_remove(&ctx->panel);
+
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
+ return 0;
+}
+
+static __maybe_unused int rocktech_hx8394_suspend(struct device *dev)
+{
+ struct hx8394 *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int rocktech_hx8394_resume(struct device *dev)
+{
+ struct hx8394 *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ mdelay(1);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(50);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rocktech_hx8394_pm_ops = {
+ SET_RUNTIME_PM_OPS(rocktech_hx8394_suspend, rocktech_hx8394_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
+static const struct of_device_id rocktech_hx8394_of_match[] = {
+ { .compatible = "rocktech,hx8394" },
+ { }
@ -1228,7 +961,6 @@ index 000000000000..29a64a546364
+ .driver = {
+ .name = "panel-rocktech-hx8394",
+ .of_match_table = rocktech_hx8394_of_match,
+ .pm = &rocktech_hx8394_pm_ops,
+ },
+};
+module_mipi_dsi_driver(rocktech_hx8394_driver);
@ -1237,7 +969,7 @@ index 000000000000..29a64a546364
+MODULE_DESCRIPTION("DRM Driver for rocktech HX8394 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index fb785f5a106a..3af0982bed64 100644
index 8dd7013c75f2..6934f3680a14 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -575,6 +575,7 @@ static int panel_dpi_probe(struct device *dev,
@ -1465,7 +1197,7 @@ index 32cb41b2202f..1750b6a25e87 100644
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 9d235b60b428..30f4995f8836 100644
index 9d235b60b428..3dcd63f20ee0 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -18,6 +18,7 @@
@ -1978,7 +1710,7 @@ index 9d235b60b428..30f4995f8836 100644
- return 0;
+ ret = NB_PF; /* error case, trace msg is handled by the caller */
+ break;
}
+ }
+
+ if (ret == PF_FLEXIBLE) {
+ regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
@ -1986,17 +1718,22 @@ index 9d235b60b428..30f4995f8836 100644
+
+ regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
+ (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos);
+ }
}
+
+ return ret;
}
-static inline u32 get_pixelformat_without_alpha(u32 drm)
+}
+
+/*
+ * All non-alpha color formats derived from native alpha color formats are
+ * either characterized by a FourCC format code
+ */
+static inline u32 is_xrgb(u32 drm)
+{
+ return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
}
-static inline u32 get_pixelformat_without_alpha(u32 drm)
+static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
{
- switch (drm) {
- case DRM_FORMAT_ARGB4444:
@ -2011,11 +1748,6 @@ index 9d235b60b428..30f4995f8836 100644
- return DRM_FORMAT_XRGB8888;
- case DRM_FORMAT_RGBA8888:
- return DRM_FORMAT_RGBX8888;
+ return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
+}
+
+static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ u32 lofs = plane->index * LAY_OFS;
@ -2079,7 +1811,7 @@ index 9d235b60b428..30f4995f8836 100644
+ DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
+ /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
+ ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
}
+ }
+
+ DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
+ regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
@ -2097,7 +1829,7 @@ index 9d235b60b428..30f4995f8836 100644
+ if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
+ ldev->crc_skip_count++;
+ return;
+ }
}
+
+ /* Get the CRC of the frame */
+ ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
@ -2188,7 +1920,7 @@ index 9d235b60b428..30f4995f8836 100644
drm_crtc_vblank_on(crtc);
}
@@ -447,18 +799,38 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
@@ -447,18 +799,32 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
struct drm_device *ddev = crtc->dev;
@ -2199,15 +1931,9 @@ index 9d235b60b428..30f4995f8836 100644
drm_crtc_vblank_off(crtc);
+ /* Disable all layers */
+ for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) {
+ for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++)
+ regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS,
+ LXCR_CLUTEN | LXCR_LEN, 0);
+
+ /* immediately commit disable of layer */
+ if (ldev->caps.plane_reg_shadow)
+ regmap_write_bits(ldev->regmap, LTDC_L1RCR + layer_index * LAY_OFS,
+ LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_IMR);
+ }
+
/* disable IRQ */
- reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
@ -2217,10 +1943,10 @@ index 9d235b60b428..30f4995f8836 100644
- reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+ if (!ldev->caps.plane_reg_shadow)
+ regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
+
+ pm_runtime_put_sync_suspend(ddev->dev);
- pm_runtime_put_sync(ddev->dev);
+ pm_runtime_put_sync_suspend(ddev->dev);
+
+ /* clear interrupt error counters */
+ mutex_lock(&ldev->err_lock);
+ ldev->transfer_err = 0;
@ -2230,7 +1956,7 @@ index 9d235b60b428..30f4995f8836 100644
}
#define CLK_TOLERANCE_HZ 50
@@ -533,6 +905,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
@@ -533,6 +899,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
u32 total_width, total_height;
@ -2238,7 +1964,7 @@ index 9d235b60b428..30f4995f8836 100644
u32 bus_flags = 0;
u32 val;
int ret;
@@ -560,10 +933,13 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
@@ -560,10 +927,13 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_connector_list_iter_end(&iter);
}
@ -2254,7 +1980,7 @@ index 9d235b60b428..30f4995f8836 100644
if (!pm_runtime_active(ddev->dev)) {
ret = pm_runtime_get_sync(ddev->dev);
@@ -608,26 +984,59 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
@@ -608,26 +978,59 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
val |= GCR_PCPOL;
@ -2285,10 +2011,10 @@ index 9d235b60b428..30f4995f8836 100644
val = (total_width << 16) | total_height;
- reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+ regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+
+ regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
- reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
+ regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
+
+ /* Configure the output format (hw version dependent) */
+ if (ldev->caps.ycbcr_output) {
+ /* Input video dynamic_range & colorimetry */
@ -2321,7 +2047,7 @@ index 9d235b60b428..30f4995f8836 100644
}
static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
@@ -642,7 +1051,8 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
@@ -642,7 +1045,8 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
ltdc_crtc_update_clut(crtc);
/* Commit shadow registers = update planes at next vblank */
@ -2331,28 +2057,7 @@ index 9d235b60b428..30f4995f8836 100644
if (event) {
crtc->state->event = NULL;
@@ -656,6 +1066,20 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
}
}
+static int ltdc_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ /* force a full mode set if active state changed */
+ if (crtc_state->active_changed)
+ crtc_state->mode_changed = true;
+
+ return 0;
+}
+
static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
bool in_vblank_irq,
int *vpos, int *hpos,
@@ -684,10 +1108,14 @@ static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
@@ -684,10 +1088,14 @@ static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
* simplify the code and only test if line > vactive_end
*/
if (pm_runtime_active(ddev->dev)) {
@ -2371,15 +2076,7 @@ index 9d235b60b428..30f4995f8836 100644
if (line > vactive_end)
*vpos = line - vtotal - vactive_start;
@@ -712,6 +1140,7 @@ static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
.atomic_flush = ltdc_crtc_atomic_flush,
.atomic_enable = ltdc_crtc_atomic_enable,
.atomic_disable = ltdc_crtc_atomic_disable,
+ .atomic_check = ltdc_crtc_atomic_check,
.get_scanout_position = ltdc_crtc_get_scanout_position,
};
@@ -723,7 +1152,7 @@ static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
@@ -723,7 +1131,7 @@ static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
DRM_DEBUG_DRIVER("\n");
if (state->enable)
@ -2388,7 +2085,7 @@ index 9d235b60b428..30f4995f8836 100644
else
return -EPERM;
@@ -735,7 +1164,61 @@ static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
@@ -735,7 +1143,61 @@ static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
DRM_DEBUG_DRIVER("\n");
@ -2451,7 +2148,7 @@ index 9d235b60b428..30f4995f8836 100644
}
static const struct drm_crtc_funcs ltdc_crtc_funcs = {
@@ -748,6 +1231,22 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = {
@@ -748,6 +1210,22 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = {
.enable_vblank = ltdc_crtc_enable_vblank,
.disable_vblank = ltdc_crtc_disable_vblank,
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
@ -2474,7 +2171,7 @@ index 9d235b60b428..30f4995f8836 100644
};
/*
@@ -773,7 +1272,8 @@ static int ltdc_plane_atomic_check(struct drm_plane *plane,
@@ -773,7 +1251,8 @@ static int ltdc_plane_atomic_check(struct drm_plane *plane,
/* Reject scaling */
if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
@ -2484,7 +2181,7 @@ index 9d235b60b428..30f4995f8836 100644
return -EINVAL;
}
@@ -784,6 +1284,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
@@ -784,6 +1263,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct ltdc_device *ldev = plane_to_ltdc(plane);
@ -2492,7 +2189,7 @@ index 9d235b60b428..30f4995f8836 100644
struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
plane);
struct drm_framebuffer *fb = newstate->fb;
@@ -793,7 +1294,8 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
@@ -793,7 +1273,8 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
u32 y0 = newstate->crtc_y;
u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
u32 src_x, src_y, src_w, src_h;
@ -2502,7 +2199,7 @@ index 9d235b60b428..30f4995f8836 100644
enum ltdc_pix_fmt pf;
if (!newstate->crtc || !fb) {
@@ -813,19 +1315,23 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
@@ -813,19 +1294,23 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
newstate->crtc_w, newstate->crtc_h,
newstate->crtc_x, newstate->crtc_y);
@ -2531,7 +2228,7 @@ index 9d235b60b428..30f4995f8836 100644
/* Specifies the pixel format */
pf = to_ltdc_pixelformat(fb->format->format);
@@ -833,24 +1339,20 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
@@ -833,24 +1318,20 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
if (ldev->caps.pix_fmt_hw[val] == pf)
break;
@ -2563,7 +2260,7 @@ index 9d235b60b428..30f4995f8836 100644
/* Specifies the blending factors */
val = BF1_PAXCA | BF2_1PAXCA;
@@ -862,35 +1364,168 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
@@ -862,35 +1343,168 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
plane->type != DRM_PLANE_TYPE_PRIMARY)
val = BF1_PAXCA | BF2_1PAXCA;
@ -2747,7 +2444,7 @@ index 9d235b60b428..30f4995f8836 100644
}
mutex_unlock(&ldev->err_lock);
}
@@ -901,10 +1536,19 @@ static void ltdc_plane_atomic_disable(struct drm_plane *plane,
@@ -901,10 +1515,19 @@ static void ltdc_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
plane);
struct ltdc_device *ldev = plane_to_ltdc(plane);
@ -2769,7 +2466,7 @@ index 9d235b60b428..30f4995f8836 100644
DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
oldstate->crtc->base.id, plane->base.id);
@@ -957,36 +1601,57 @@ static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
@@ -957,36 +1580,57 @@ static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
};
static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
@ -2818,11 +2515,11 @@ index 9d235b60b428..30f4995f8836 100644
+ if (ldev->caps.non_alpha_only_l1)
+ if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
+ continue; /* XR24 & RX24 like formats supported only on primary layer */
- formats[nb_fmt++] = drm_fmt_no_alpha;
+
+ formats[nb_fmt++] = drm_fmt;
+ }
+
- formats[nb_fmt++] = drm_fmt_no_alpha;
+ /* Add YCbCr supported pixel formats */
+ if (ldev->caps.ycbcr_input) {
+ regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
@ -2844,7 +2541,7 @@ index 9d235b60b428..30f4995f8836 100644
}
plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
@@ -999,8 +1664,21 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
@@ -999,8 +1643,21 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
if (ret < 0)
return NULL;
@ -2866,7 +2563,7 @@ index 9d235b60b428..30f4995f8836 100644
DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
return plane;
@@ -1019,17 +1697,42 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
@@ -1019,17 +1676,42 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
{
struct ltdc_device *ldev = ddev->dev_private;
struct drm_plane *primary, *overlay;
@ -2912,7 +2609,7 @@ index 9d235b60b428..30f4995f8836 100644
if (ret) {
DRM_ERROR("Can not initialize CRTC\n");
goto cleanup;
@@ -1044,12 +1747,20 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
@@ -1044,12 +1726,20 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
/* Add planes. Note : the first layer is used by primary plane */
for (i = 1; i < ldev->caps.nb_layers; i++) {
@ -2934,7 +2631,7 @@ index 9d235b60b428..30f4995f8836 100644
}
return 0;
@@ -1067,7 +1778,7 @@ static void ltdc_encoder_disable(struct drm_encoder *encoder)
@@ -1067,7 +1757,7 @@ static void ltdc_encoder_disable(struct drm_encoder *encoder)
DRM_DEBUG_DRIVER("\n");
/* Disable LTDC */
@ -2943,7 +2640,7 @@ index 9d235b60b428..30f4995f8836 100644
/* Set to sleep state the pinctrl whatever type of encoder */
pinctrl_pm_select_sleep_state(ddev->dev);
@@ -1080,8 +1791,12 @@ static void ltdc_encoder_enable(struct drm_encoder *encoder)
@@ -1080,8 +1770,12 @@ static void ltdc_encoder_enable(struct drm_encoder *encoder)
DRM_DEBUG_DRIVER("\n");
@ -2957,7 +2654,7 @@ index 9d235b60b428..30f4995f8836 100644
}
static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
@@ -1144,21 +1859,25 @@ static int ltdc_get_caps(struct drm_device *ddev)
@@ -1144,21 +1838,25 @@ static int ltdc_get_caps(struct drm_device *ddev)
* at least 1 layer must be managed & the number of layers
* must not exceed LTDC_MAX_LAYER
*/
@ -2987,7 +2684,7 @@ index 9d235b60b428..30f4995f8836 100644
/*
* Hw older versions support non-alpha color formats derived
* from native alpha color formats only on the primary layer.
@@ -1171,13 +1890,49 @@ static int ltdc_get_caps(struct drm_device *ddev)
@@ -1171,13 +1869,49 @@ static int ltdc_get_caps(struct drm_device *ddev)
if (ldev->caps.hw_version == HWVER_10200)
ldev->caps.pad_max_freq_hz = 65000000;
ldev->caps.nb_irq = 2;
@ -3038,24 +2735,7 @@ index 9d235b60b428..30f4995f8836 100644
break;
default:
return -ENODEV;
@@ -1220,7 +1975,6 @@ int ltdc_load(struct drm_device *ddev)
struct drm_panel *panel;
struct drm_crtc *crtc;
struct reset_control *rstc;
- struct resource *res;
int irq, i, nb_endpoints;
int ret = -ENODEV;
@@ -1287,17 +2041,19 @@ int ltdc_load(struct drm_device *ddev)
reset_control_deassert(rstc);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ldev->regs = devm_ioremap_resource(dev, res);
+ ldev->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ldev->regs)) {
DRM_ERROR("Unable to get ltdc registers\n");
ret = PTR_ERR(ldev->regs);
@@ -1295,9 +2029,12 @@ int ltdc_load(struct drm_device *ddev)
goto err;
}
@ -3071,7 +2751,7 @@ index 9d235b60b428..30f4995f8836 100644
ret = ltdc_get_caps(ddev);
if (ret) {
@@ -1306,8 +2062,22 @@ int ltdc_load(struct drm_device *ddev)
@@ -1306,8 +2043,22 @@ int ltdc_load(struct drm_device *ddev)
goto err;
}
@ -3094,7 +2774,7 @@ index 9d235b60b428..30f4995f8836 100644
for (i = 0; i < ldev->caps.nb_irq; i++) {
irq = platform_get_irq(pdev, i);
if (irq < 0) {
@@ -1322,7 +2092,6 @@ int ltdc_load(struct drm_device *ddev)
@@ -1322,7 +2073,6 @@ int ltdc_load(struct drm_device *ddev)
DRM_ERROR("Failed to register LTDC interrupt\n");
goto err;
}

95
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0008-v5.15-stm32mp-r2.1-HWSPINLOCK.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0008-v5.15-stm32mp-r2-HWSPINLOCK.patch
View File

@ -1,16 +1,95 @@
From af1a71eda7ad9bacd5a5c577b6b89a70c4b1a53a Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:41:17 +0200
Subject: [PATCH 08/22] v5.15-stm32mp-r2.1 HWSPINLOCK
From 8fade81923d0fc70c09d3f2beae3466cc5e71c2d Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:28:58 +0100
Subject: [PATCH 08/22] v5.15-stm32mp-r2 HWSPINLOCK
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../devicetree/bindings/hwlock/hwlock.txt | 27 +++++--
.../bindings/hwlock/st,stm32-hwspinlock.yaml | 4 +-
Documentation/locking/hwspinlock.rst | 10 ++-
drivers/hwspinlock/hwspinlock_core.c | 80 +++++++++++++++++++-----
drivers/hwspinlock/hwspinlock_core.c | 80 +++++++++++++++----
drivers/hwspinlock/hwspinlock_internal.h | 2 +
drivers/hwspinlock/stm32_hwspinlock.c | 58 ++++++++++-------
4 files changed, 109 insertions(+), 41 deletions(-)
drivers/hwspinlock/stm32_hwspinlock.c | 58 +++++++++-----
6 files changed, 131 insertions(+), 50 deletions(-)
diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt
index 085d1f5c916a..e98088a409ba 100644
--- a/Documentation/devicetree/bindings/hwlock/hwlock.txt
+++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt
@@ -13,7 +13,7 @@ hwlock providers:
Required properties:
- #hwlock-cells: Specifies the number of cells needed to represent a
- specific lock.
+ specific lock. Shall be 1 or 2 (see hwlocks below).
hwlock users:
=============
@@ -27,6 +27,11 @@ Required properties:
#hwlock-cells. The list can have just a single hwlock
or multiple hwlocks, with each hwlock represented by
a phandle and a corresponding args specifier.
+ If #hwlock-cells is 1, all of the locks are exclusive
+ (cannot be used by several users).
+ If #hwlock-cells is 2, the value of the second cell
+ defines whether the lock is for exclusive usage (0) or
+ shared (1) i.e. can be used by several users.
Optional properties:
- hwlock-names: List of hwlock name strings defined in the same order
@@ -46,14 +51,22 @@ of length 1.
...
};
-2. Example of a node using multiple specific hwlocks:
+2. Example of nodes using multiple and shared specific hwlocks:
-The following example has a node requesting two hwlocks, a hwlock within
-the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
-hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.
+The following example has a nodeA requesting two hwlocks:
+- an exclusive one (#hwlock-cells = 1) within the hwlock device node 'hwlock1'
+- a shared one (#hwlock-cells = 2, second cell = 1) within the hwlock device
+ node 'hwlock2'.
+The shared lock is also be used by nodeB.
- node {
+ nodeA {
...
- hwlocks = <&hwlock1 2>, <&hwlock2 0 3>;
+ hwlocks = <&hwlock1 2>, <&hwlock2 0 1>;
...
};
+
+ nodeB {
+ ...
+ hwlocks = <&hwlock2 0 1>;
+ ...
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
index 47cf9c8d97e9..539a1dc052b7 100644
--- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
+++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
@@ -12,7 +12,7 @@ maintainers:
properties:
"#hwlock-cells":
- const: 1
+ const: 2
compatible:
const: st,stm32-hwspinlock
@@ -41,7 +41,7 @@ examples:
#include <dt-bindings/clock/stm32mp1-clks.h>
hwspinlock@4c000000 {
compatible = "st,stm32-hwspinlock";
- #hwlock-cells = <1>;
+ #hwlock-cells = <2>;
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
clock-names = "hsem";
diff --git a/Documentation/locking/hwspinlock.rst b/Documentation/locking/hwspinlock.rst
index 6f03713b7003..605bd2dc8a03 100644
--- a/Documentation/locking/hwspinlock.rst

350
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0009-v5.15-stm32mp-r2.1-I2C-IIO-IRQCHIP.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0009-v5.15-stm32mp-r2-I2C-IIO-IRQCHIP.patch
View File

@ -1,23 +1,327 @@
From 56ee138f53ea518a8d1bf9178496e6a4ed65a582 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:43:45 +0200
Subject: [PATCH 09/22] v5.15-stm32mp-r2.1 I2C-IIO-IRQCHIP
From e02af9ac4cbbe463217ac8c34eee18170d57e5af Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:36:23 +0100
Subject: [PATCH 09/22] v5.15-stm32mp-r2 I2C-IIO-IRQCHIP
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/i2c/busses/i2c-stm32f7.c | 265 ++++-----
drivers/iio/adc/sd_adc_modulator.c | 89 ++-
drivers/iio/adc/stm32-adc-core.c | 208 ++++++-
drivers/iio/adc/stm32-adc-core.h | 90 +++
drivers/iio/adc/stm32-adc.c | 861 +++++++++++++++++++++++++----
drivers/iio/adc/stm32-dfsdm-adc.c | 107 +++-
drivers/iio/adc/stm32-dfsdm-core.c | 91 ++-
drivers/iio/adc/stm32-dfsdm.h | 69 ++-
drivers/irqchip/irq-stm32-exti.c | 427 ++++++++++----
.../devicetree/bindings/i2c/st,stm32-i2c.yaml | 2 +
.../iio/adc/sigma-delta-modulator.yaml | 3 +
.../bindings/iio/adc/st,stm32-adc.yaml | 175 +++-
drivers/i2c/busses/i2c-stm32f7.c | 265 +++---
drivers/iio/adc/sd_adc_modulator.c | 89 +-
drivers/iio/adc/stm32-adc-core.c | 208 ++++-
drivers/iio/adc/stm32-adc-core.h | 90 ++
drivers/iio/adc/stm32-adc.c | 861 ++++++++++++++++--
drivers/iio/adc/stm32-dfsdm-adc.c | 108 ++-
drivers/iio/adc/stm32-dfsdm-core.c | 91 +-
drivers/iio/adc/stm32-dfsdm.h | 69 +-
drivers/irqchip/irq-stm32-exti.c | 427 ++++++---
include/linux/irqdomain.h | 4 +
kernel/irq/irqdomain.c | 6 +-
11 files changed, 1793 insertions(+), 424 deletions(-)
14 files changed, 1965 insertions(+), 433 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index d747f4990ad8..5df3dbd6091f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -17,6 +17,7 @@ allOf:
contains:
enum:
- st,stm32f7-i2c
+ - st,stm32mp13-i2c
- st,stm32mp15-i2c
then:
properties:
@@ -52,6 +53,7 @@ properties:
enum:
- st,stm32f4-i2c
- st,stm32f7-i2c
+ - st,stm32mp13-i2c
- st,stm32mp15-i2c
reg:
diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
index a390343d0c2a..bf5d71fb60da 100644
--- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
@@ -21,6 +21,9 @@ properties:
'#io-channel-cells':
const: 0
+ vref-supply:
+ description: Phandle to the vref input analog reference voltage.
+
required:
- compatible
- '#io-channel-cells'
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index a58334c3bb76..47883701e331 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -27,6 +27,7 @@ properties:
- st,stm32f4-adc-core
- st,stm32h7-adc-core
- st,stm32mp1-adc-core
+ - st,stm32mp13-adc-core
reg:
maxItems: 1
@@ -37,6 +38,7 @@ properties:
- stm32f4 and stm32h7 share a common ADC interrupt line.
- stm32mp1 has two separate interrupt lines, one for each ADC within
ADC block.
+ - stm32mp13 has an interrupt line per ADC block.
minItems: 1
maxItems: 2
@@ -182,6 +184,34 @@ allOf:
maximum: 36000000
default: 36000000
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc-core
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: bus
+ - const: adc
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ items:
+ - description: ADC interrupt line
+
+ st,max-clk-rate-hz:
+ minimum: 120000
+ maximum: 36000000
+ default: 36000000
+
additionalProperties: false
required:
@@ -210,6 +240,7 @@ patternProperties:
- st,stm32f4-adc
- st,stm32h7-adc
- st,stm32mp1-adc
+ - st,stm32mp13-adc
reg:
description: |
@@ -222,10 +253,16 @@ patternProperties:
'#io-channel-cells':
const: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
interrupts:
description: |
IRQ Line for the ADC instance. Valid values are:
- - 0 for adc@0
+ - 0 for adc@0 (single adc for stm32mp13)
- 1 for adc@100
- 2 for adc@200 (stm32f4 only)
maxItems: 1
@@ -246,16 +283,18 @@ patternProperties:
assigned-resolution-bits:
description: |
Resolution (bits) to use for conversions:
- - can be 6, 8, 10 or 12 on stm32f4
+ - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
- can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
st,adc-channels:
description: |
List of single-ended channels muxed for this ADC. It can have up to:
- 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
+ - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
- 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
stm32mp1.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
st,adc-diff-channels:
description: |
@@ -265,7 +304,9 @@ patternProperties:
<vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
- required. Both properties can be used together. Some channels can be
+ required if no adc generic channel is defined. These legacy channel
+ properties are exclusive with adc generic channel bindings.
+ Both properties can be used together. Some channels can be
used as single-ended and some other ones as differential (mixed). But
channels can't be configured both as single-ended and differential.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
@@ -279,6 +320,7 @@ patternProperties:
"vinn" indicates negative input number
minimum: 0
maximum: 19
+ deprecated: true
st,min-sample-time-nsecs:
description:
@@ -289,6 +331,50 @@ patternProperties:
list, to set sample time resp. for all channels, or independently for
each channel.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
+
+ nvmem-cells:
+ items:
+ - description: Phandle to the calibration vrefint data provided by otp
+
+ nvmem-cell-names:
+ items:
+ - const: vrefint
+
+ patternProperties:
+ "^channel@([0-9]|1[0-9])$":
+ type: object
+ $ref: "adc.yaml"
+ description: Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 19
+
+ label:
+ description: |
+ Unique name to identify which channel this is.
+ Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
+ are used to identify internal channels with matching names.
+
+ diff-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minimum: 0
+ maximum: 19
+
+ st,min-sample-time-ns:
+ description: |
+ Minimum sampling time in nanoseconds. Depending on hardware (board)
+ e.g. high/low analog input source impedance, fine tune of ADC
+ sampling time may be recommended.
+
+ required:
+ - reg
+
+ additionalProperties: false
allOf:
- if:
@@ -367,13 +453,38 @@ patternProperties:
items:
minimum: 40
- additionalProperties: false
- anyOf:
- - required:
- - st,adc-channels
- - required:
- - st,adc-diff-channels
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc
+
+ then:
+ properties:
+ reg:
+ const: 0x0
+
+ interrupts:
+ const: 0
+
+ assigned-resolution-bits:
+ enum: [6, 8, 10, 12]
+ default: 12
+
+ st,adc-channels:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 0
+ maximum: 18
+
+ st,min-sample-time-nsecs:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 40
+ additionalProperties: false
required:
- compatible
@@ -451,4 +562,50 @@ examples:
// other adc child node follow...
};
+ - |
+ // Example 3: with stm32mp157c to setup ADC2 with:
+ // - internal channels 13, 14, 15.
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ adc122: adc@48003000 {
+ compatible = "st,stm32mp1-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ booster-supply = <&booster>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vref>;
+ st,syscfg = <&syscfg>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@100 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@15 {
+ reg = <15>;
+ label = "vbat";
+ st,min-sample-time-ns = <9000>;
+ };
+ };
+ };
+
...
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 50d5ae81d227..791baea3623b 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
@ -2466,7 +2770,7 @@ index ef5b54ed9661..d05e081e1009 100644
};
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c
index 6592221cbe21..997f1f387a04 100644
index 1cfefb3b5e56..997f1f387a04 100644
--- a/drivers/iio/adc/stm32-dfsdm-adc.c
+++ b/drivers/iio/adc/stm32-dfsdm-adc.c
@@ -10,6 +10,7 @@
@ -2647,6 +2951,14 @@ index 6592221cbe21..997f1f387a04 100644
}
indio_dev->num_channels = num_ch;
@@ -1521,6 +1620,7 @@ static const struct of_device_id stm32_dfsdm_adc_match[] = {
},
{}
};
+MODULE_DEVICE_TABLE(of, stm32_dfsdm_adc_match);
static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
{
diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c
index a627af9a825e..65c01d522ce3 100644
--- a/drivers/iio/adc/stm32-dfsdm-core.c
@ -3594,10 +3906,10 @@ index 9ee238ad29ce..553da4899f55 100644
* Should several domains have the same device node, but serve
* different purposes (for example one domain is for PCI/MSI, and the
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index e0b67784ac1e..0c768e06a798 100644
index 035e3038c4de..5c74ebb13a77 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -794,9 +794,8 @@ static int irq_domain_translate(struct irq_domain *d,
@@ -744,9 +744,8 @@ static int irq_domain_translate(struct irq_domain *d,
return 0;
}
@ -3609,7 +3921,7 @@ index e0b67784ac1e..0c768e06a798 100644
{
int i;
@@ -806,6 +805,7 @@ static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args,
@@ -756,6 +755,7 @@ static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args,
for (i = 0; i < count; i++)
fwspec->param[i] = args[i];
}

237
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0010-v5.15-stm32mp-r2.1-REMOTEPROC-RPMSG.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0010-v5.15-stm32mp-r2-REMOTEPROC-RPMSG.patch
View File

@ -1,50 +1,53 @@
From 1114fa4cbc859f4a0cc5e19f267c66634888c798 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:45:56 +0200
Subject: [PATCH 10/22] v5.15-stm32mp-r2.1 REMOTEPROC-RPMSG
From 2af007b9996146b7357a9b3952bc16940da1ee58 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:40:22 +0100
Subject: [PATCH 10/22] v5.15-stm32mp-r2 REMOTEPROC-RPMSG
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../bindings/remoteproc/rproc-srm.txt | 58 ++
.../bindings/remoteproc/st,stm32-rproc.yaml | 25 +-
Documentation/staging/remoteproc.rst | 22 +
Documentation/staging/tee.rst | 30 +
drivers/remoteproc/Kconfig | 29 +
drivers/remoteproc/Makefile | 3 +
drivers/remoteproc/remoteproc_core.c | 8 +
drivers/remoteproc/rproc_srm_core.c | 303 ++++++++++
drivers/remoteproc/rproc_srm_core.h | 98 ++++
drivers/remoteproc/rproc_srm_dev.c | 744 ++++++++++++++++++++++++
drivers/remoteproc/stm32_rproc.c | 324 +++++++----
drivers/remoteproc/tee_remoteproc.c | 378 +++++++++++++
drivers/remoteproc/rproc_srm_core.c | 303 +++++++
drivers/remoteproc/rproc_srm_core.h | 98 +++
drivers/remoteproc/rproc_srm_dev.c | 744 ++++++++++++++++
drivers/remoteproc/stm32_rproc.c | 324 ++++---
drivers/remoteproc/tee_remoteproc.c | 378 ++++++++
drivers/rpmsg/Kconfig | 8 +
drivers/rpmsg/Makefile | 1 +
drivers/rpmsg/qcom_glink_native.c | 2 +-
drivers/rpmsg/qcom_smd.c | 2 +-
drivers/rpmsg/rpmsg_char.c | 229 +++-----
drivers/rpmsg/rpmsg_char.h | 46 ++
drivers/rpmsg/rpmsg_char.c | 229 ++---
drivers/rpmsg/rpmsg_char.h | 46 +
drivers/rpmsg/rpmsg_core.c | 36 +-
drivers/rpmsg/rpmsg_ctrl.c | 243 ++++++++
drivers/rpmsg/rpmsg_ctrl.c | 243 ++++++
drivers/rpmsg/rpmsg_internal.h | 12 +-
drivers/rpmsg/virtio_rpmsg_bus.c | 12 +-
drivers/tee/amdtee/amdtee_private.h | 8 +-
drivers/tee/amdtee/core.c | 22 +-
drivers/tee/optee/Makefile | 2 +
drivers/tee/optee/call.c | 814 +++++++++++++++++++++------
drivers/tee/optee/call_queue.c | 86 +++
drivers/tee/optee/core.c | 463 +++++++++++++--
drivers/tee/optee/notif.c | 125 ++++
drivers/tee/optee/optee_msg.h | 160 +++++-
drivers/tee/optee/optee_private.h | 180 +++++-
drivers/tee/optee/call.c | 814 ++++++++++++++----
drivers/tee/optee/call_queue.c | 86 ++
drivers/tee/optee/core.c | 463 +++++++++-
drivers/tee/optee/notif.c | 125 +++
drivers/tee/optee/optee_msg.h | 160 +++-
drivers/tee/optee/optee_private.h | 180 +++-
drivers/tee/optee/optee_rpc_cmd.h | 31 +-
drivers/tee/optee/optee_smc.h | 94 +++-
drivers/tee/optee/rpc.c | 99 ++--
drivers/tee/tee_core.c | 73 ++-
drivers/tee/optee/optee_smc.h | 94 +-
drivers/tee/optee/rpc.c | 99 +--
drivers/tee/tee_core.c | 73 +-
drivers/tee/tee_shm.c | 13 +-
include/linux/rpmsg.h | 10 +
include/linux/tee_drv.h | 17 +-
include/linux/tee_remoteproc.h | 101 ++++
include/linux/tee_remoteproc.h | 101 +++
include/uapi/linux/rpmsg.h | 10 +
include/uapi/linux/tee.h | 36 +-
39 files changed, 4292 insertions(+), 582 deletions(-)
41 files changed, 4358 insertions(+), 599 deletions(-)
create mode 100644 Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
create mode 100644 drivers/remoteproc/rproc_srm_core.c
create mode 100644 drivers/remoteproc/rproc_srm_core.h
create mode 100644 drivers/remoteproc/rproc_srm_dev.c
@ -55,6 +58,122 @@ Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
create mode 100644 drivers/tee/optee/notif.c
create mode 100644 include/linux/tee_remoteproc.h
diff --git a/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
new file mode 100644
index 000000000000..baa6e8e135e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
@@ -0,0 +1,58 @@
+Remoteproc System Resource Manager
+----------------------------------
+
+The remoteproc SRM (System Resource Manager) handles resources allocated
+to remote processors.
+This makes it possible for remote proc to reserve and initialize system
+resources for a peripheral assigned to a coprocessor.
+
+The devices are grouped in a core node
+
+Core
+====
+Required properties:
+- compatible: should be "rproc-srm-core"
+
+Dev
+===
+Required properties:
+- compatible: should be "rproc-srm-dev"
+
+Optional properties:
+- reg: register base address and length
+- clocks: clocks required by the coprocessor
+- clock-names: see clock-bindings.txt
+- pinctrl-0: pins configurations required by the coprocessor
+ The SRM reserves the pins for the coprocessor, which prevents the local
+ processor to use them.
+- pinctrl-names: must be "default".
+- x-supply: power supplies required by the coprocessor
+- interrupts: external interrupts configurations required by the coprocessor.
+ This is optional since the configuration is done by the coprocessor.
+ When defined, the SRM (over)writes the configuration which allows the
+ interrupt controller to check for configuration conflicts.
+- interrupt-parent: see interrupts.txt
+- interrupt-names: see interrupts.txt
+
+Example:
+ system_resources {
+ compatible = "rproc-srm-core";
+
+ mmc0: sdhci@09060000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x09060000 0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pinctrl_mmc0>;
+ clock-names = "mmc", "icn";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
+ vdda-supply = <&vdda>;
+ };
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <5 1>;
+ interrupt-names = "gpio_key";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
index 1e6225677e00..93c27e3ecd85 100644
--- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
@@ -25,21 +25,12 @@ properties:
maxItems: 3
resets:
- maxItems: 1
-
- st,syscfg-holdboot:
- description: remote processor reset hold boot
- - Phandle of syscon block.
- - The offset of the hold boot setting register.
- - The field mask of the hold boot.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ maxItems: 2
- st,syscfg-tz:
- description:
- Reference to the system configuration which holds the RCC trust zone mode
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ reset-names:
+ items:
+ - const: mcu_rst
+ - const: hold_boot
interrupts:
description: Should contain the WWDG1 watchdog reset interrupt
@@ -119,7 +110,6 @@ required:
- reg
- resets
- st,syscfg-holdboot
- - st,syscfg-tz
additionalProperties: false
@@ -131,9 +121,10 @@ examples:
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
};
diff --git a/Documentation/staging/remoteproc.rst b/Documentation/staging/remoteproc.rst
index 9cccd3dd6a4b..c2367e3c0b19 100644
--- a/Documentation/staging/remoteproc.rst
@ -195,7 +314,7 @@ index bb26c9e4ef9c..521dd3384fba 100644
obj-$(CONFIG_INGENIC_VPU_RPROC) += ingenic_rproc.o
obj-$(CONFIG_MTK_SCP) += mtk_scp.o mtk_scp_ipi.o
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 97e59f746126..4312fe52a826 100644
index 775df165eb45..df31b9222b38 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -38,6 +38,7 @@
@ -206,7 +325,7 @@ index 97e59f746126..4312fe52a826 100644
#include <asm/byteorder.h>
#include <linux/platform_device.h>
@@ -2363,6 +2364,11 @@ int rproc_add(struct rproc *rproc)
@@ -2356,6 +2357,11 @@ int rproc_add(struct rproc *rproc)
/* create debugfs entries */
rproc_create_debug_dir(rproc);
@ -218,7 +337,7 @@ index 97e59f746126..4312fe52a826 100644
/* if rproc is marked always-on, request it to boot */
if (rproc->auto_boot) {
ret = rproc_trigger_auto_boot(rproc);
@@ -2644,6 +2650,8 @@ int rproc_del(struct rproc *rproc)
@@ -2637,6 +2643,8 @@ int rproc_del(struct rproc *rproc)
list_del_rcu(&rproc->node);
mutex_unlock(&rproc_list_mutex);
@ -1391,7 +1510,7 @@ index 000000000000..e47654af3e3a
+MODULE_DESCRIPTION("Remoteproc System Resource Manager driver - dev");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c
index aba3df1d1bf5..5c7cdeae917e 100644
index b643efcf995a..4b713b74ad44 100644
--- a/drivers/remoteproc/stm32_rproc.c
+++ b/drivers/remoteproc/stm32_rproc.c
@@ -20,13 +20,11 @@
@ -1582,7 +1701,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
static int stm32_rproc_prepare(struct rproc *rproc)
{
struct device *dev = rproc->dev.parent;
@@ -270,7 +409,14 @@ static int stm32_rproc_prepare(struct rproc *rproc)
@@ -266,7 +405,14 @@ static int stm32_rproc_prepare(struct rproc *rproc)
static int stm32_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
{
@ -1598,7 +1717,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
dev_warn(&rproc->dev, "no resource table found for this firmware\n");
return 0;
@@ -406,30 +552,6 @@ static int stm32_rproc_request_mbox(struct rproc *rproc)
@@ -394,30 +540,6 @@ static int stm32_rproc_request_mbox(struct rproc *rproc)
return -EPROBE_DEFER;
}
@ -1629,7 +1748,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
static void stm32_rproc_add_coredump_trace(struct rproc *rproc)
{
struct rproc_debug_trace *trace;
@@ -469,18 +591,20 @@ static int stm32_rproc_start(struct rproc *rproc)
@@ -457,18 +579,20 @@ static int stm32_rproc_start(struct rproc *rproc)
}
}
@ -1653,7 +1772,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
}
static int stm32_rproc_detach(struct rproc *rproc)
@@ -497,27 +621,21 @@ static int stm32_rproc_detach(struct rproc *rproc)
@@ -485,27 +609,21 @@ static int stm32_rproc_detach(struct rproc *rproc)
}
/* Allow remote processor to auto-reboot */
@ -1688,7 +1807,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
err = reset_control_assert(ddata->rst);
if (err) {
@@ -525,29 +643,8 @@ static int stm32_rproc_stop(struct rproc *rproc)
@@ -513,29 +631,8 @@ static int stm32_rproc_stop(struct rproc *rproc)
return err;
}
@ -1719,7 +1838,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
}
static void stm32_rproc_kick(struct rproc *rproc, int vqid)
@@ -659,8 +756,21 @@ static const struct rproc_ops st_rproc_ops = {
@@ -647,8 +744,21 @@ static const struct rproc_ops st_rproc_ops = {
.get_boot_addr = rproc_elf_get_boot_addr,
};
@ -1742,7 +1861,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
{},
};
MODULE_DEVICE_TABLE(of, stm32_rproc_match);
@@ -692,8 +802,6 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
@@ -680,8 +790,6 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
@ -1751,7 +1870,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
int err, irq;
irq = platform_get_irq(pdev, 0);
@@ -717,35 +825,15 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
@@ -705,35 +813,15 @@ static int stm32_rproc_parse_dt(struct platform_device *pdev,
dev_info(dev, "wdg irq registered\n");
}
@ -1792,7 +1911,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
err = stm32_rproc_get_syscon(np, "st,syscfg-pdds", &ddata->pdds);
if (err)
@@ -801,6 +889,7 @@ static int stm32_rproc_probe(struct platform_device *pdev)
@@ -789,6 +877,7 @@ static int stm32_rproc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct stm32_rproc *ddata;
struct device_node *np = dev->of_node;
@ -1800,7 +1919,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
struct rproc *rproc;
unsigned int state;
int ret;
@@ -809,11 +898,32 @@ static int stm32_rproc_probe(struct platform_device *pdev)
@@ -797,11 +886,32 @@ static int stm32_rproc_probe(struct platform_device *pdev)
if (ret)
return ret;
@ -1836,7 +1955,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
@@ -864,6 +974,10 @@ static int stm32_rproc_probe(struct platform_device *pdev)
@@ -852,6 +962,10 @@ static int stm32_rproc_probe(struct platform_device *pdev)
device_init_wakeup(dev, false);
}
rproc_free(rproc);
@ -1847,7 +1966,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
return ret;
}
@@ -885,10 +999,21 @@ static int stm32_rproc_remove(struct platform_device *pdev)
@@ -873,10 +987,21 @@ static int stm32_rproc_remove(struct platform_device *pdev)
device_init_wakeup(dev, false);
}
rproc_free(rproc);
@ -1869,7 +1988,7 @@ index aba3df1d1bf5..5c7cdeae917e 100644
static int __maybe_unused stm32_rproc_suspend(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
@@ -917,6 +1042,7 @@ static SIMPLE_DEV_PM_OPS(stm32_rproc_pm_ops,
@@ -905,6 +1030,7 @@ static SIMPLE_DEV_PM_OPS(stm32_rproc_pm_ops,
static struct platform_driver stm32_rproc_driver = {
.probe = stm32_rproc_probe,
.remove = stm32_rproc_remove,
@ -2293,10 +2412,10 @@ index 8d452656f0ee..58e3b382e316 100644
obj-$(CONFIG_RPMSG_MTK_SCP) += mtk_rpmsg.o
qcom_glink-objs := qcom_glink_native.o qcom_glink_ssr.o
diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c
index fd4c2f0fa4b1..0a7dabf3f329 100644
index 05533c71b10e..7d7e809800ec 100644
--- a/drivers/rpmsg/qcom_glink_native.c
+++ b/drivers/rpmsg/qcom_glink_native.c
@@ -1643,7 +1643,7 @@ static int qcom_glink_create_chrdev(struct qcom_glink *glink)
@@ -1642,7 +1642,7 @@ static int qcom_glink_create_chrdev(struct qcom_glink *glink)
rpdev->dev.parent = glink->dev;
rpdev->dev.release = qcom_glink_device_release;
@ -2306,7 +2425,7 @@ index fd4c2f0fa4b1..0a7dabf3f329 100644
struct qcom_glink *qcom_glink_native_probe(struct device *dev,
diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c
index 56bc622de25e..754161b02407 100644
index c1c07ff39a79..b2cd71c350ee 100644
--- a/drivers/rpmsg/qcom_smd.c
+++ b/drivers/rpmsg/qcom_smd.c
@@ -1113,7 +1113,7 @@ static int qcom_smd_create_chrdev(struct qcom_smd_edge *edge)
@ -3197,7 +3316,7 @@ index 6d0f7062bb87..73c183510c26 100644
int amdtee_cancel_req(struct tee_context *ctx, u32 cancel_id, u32 session);
diff --git a/drivers/tee/amdtee/core.c b/drivers/tee/amdtee/core.c
index 372d64756ed6..78511ae99b91 100644
index 297dc62bca29..e6f1e331d3c3 100644
--- a/drivers/tee/amdtee/core.c
+++ b/drivers/tee/amdtee/core.c
@@ -230,7 +230,9 @@ static void destroy_session(struct kref *ref)
@ -3223,7 +3342,7 @@ index 372d64756ed6..78511ae99b91 100644
if (arg->clnt_login != TEE_IOCTL_LOGIN_PUBLIC) {
pr_err("unsupported client login method\n");
return -EINVAL;
@@ -268,7 +275,7 @@ int amdtee_open_session(struct tee_context *ctx,
@@ -283,7 +290,7 @@ int amdtee_open_session(struct tee_context *ctx,
}
/* Open session with loaded TA */
@ -3231,8 +3350,8 @@ index 372d64756ed6..78511ae99b91 100644
+ handle_open_session(arg, &session_info, normal_param);
if (arg->ret != TEEC_SUCCESS) {
pr_err("open_session failed %d\n", arg->ret);
handle_unload_ta(ta_handle);
@@ -404,12 +411,19 @@ void amdtee_unmap_shmem(struct tee_shm *shm)
spin_lock(&sess->lock);
@@ -405,12 +412,19 @@ void amdtee_unmap_shmem(struct tee_shm *shm)
int amdtee_invoke_func(struct tee_context *ctx,
struct tee_ioctl_invoke_arg *arg,
@ -3253,7 +3372,7 @@ index 372d64756ed6..78511ae99b91 100644
/* Check that the session is valid */
mutex_lock(&session_list_mutex);
sess = find_session(ctxdata, arg->session);
@@ -422,7 +436,7 @@ int amdtee_invoke_func(struct tee_context *ctx,
@@ -423,7 +437,7 @@ int amdtee_invoke_func(struct tee_context *ctx,
if (!sess)
return -EINVAL;
@ -5895,10 +6014,10 @@ index 456833d82007..ae41f4e640ab 100644
+ return false;
+}
diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c
index a44e5b53e7a9..4c2103fb4cf8 100644
index 3fc426dad2df..705bb4e53301 100644
--- a/drivers/tee/tee_core.c
+++ b/drivers/tee/tee_core.c
@@ -359,6 +359,14 @@ tee_ioctl_shm_register(struct tee_context *ctx,
@@ -356,6 +356,14 @@ tee_ioctl_shm_register(struct tee_context *ctx,
return ret;
}
@ -5913,7 +6032,7 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
static int params_from_user(struct tee_context *ctx, struct tee_param *params,
size_t num_params,
struct tee_ioctl_param __user *uparams)
@@ -467,6 +475,33 @@ static int params_to_user(struct tee_ioctl_param __user *uparams,
@@ -464,6 +472,33 @@ static int params_to_user(struct tee_ioctl_param __user *uparams,
return 0;
}
@ -5947,7 +6066,7 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
static int tee_ioctl_open_session(struct tee_context *ctx,
struct tee_ioctl_buf_data __user *ubuf)
{
@@ -514,7 +549,9 @@ static int tee_ioctl_open_session(struct tee_context *ctx,
@@ -511,7 +546,9 @@ static int tee_ioctl_open_session(struct tee_context *ctx,
goto out;
}
@ -5958,7 +6077,7 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
if (rc)
goto out;
have_session = true;
@@ -585,7 +622,9 @@ static int tee_ioctl_invoke(struct tee_context *ctx,
@@ -582,7 +619,9 @@ static int tee_ioctl_invoke(struct tee_context *ctx,
goto out;
}
@ -5969,7 +6088,7 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
if (rc)
goto out;
@@ -1162,9 +1201,22 @@ int tee_client_open_session(struct tee_context *ctx,
@@ -1159,9 +1198,22 @@ int tee_client_open_session(struct tee_context *ctx,
struct tee_ioctl_open_session_arg *arg,
struct tee_param *param)
{
@ -5993,7 +6112,7 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
}
EXPORT_SYMBOL_GPL(tee_client_open_session);
@@ -1180,9 +1232,22 @@ int tee_client_invoke_func(struct tee_context *ctx,
@@ -1177,9 +1229,22 @@ int tee_client_invoke_func(struct tee_context *ctx,
struct tee_ioctl_invoke_arg *arg,
struct tee_param *param)
{
@ -6018,10 +6137,10 @@ index a44e5b53e7a9..4c2103fb4cf8 100644
EXPORT_SYMBOL_GPL(tee_client_invoke_func);
diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c
index 6fb4400333fb..36304fe6accd 100644
index 6e662fb131d5..94282f2bb154 100644
--- a/drivers/tee/tee_shm.c
+++ b/drivers/tee/tee_shm.c
@@ -158,7 +158,8 @@ struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr,
@@ -157,7 +157,8 @@ struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr,
int num_pages;
unsigned long start;
@ -6031,7 +6150,7 @@ index 6fb4400333fb..36304fe6accd 100644
return ERR_PTR(-ENOTSUPP);
if (!tee_device_get(teedev))
@@ -432,6 +433,16 @@ struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id)
@@ -434,6 +435,16 @@ struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id)
}
EXPORT_SYMBOL_GPL(tee_shm_get_from_id);

569
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0011-v5.15-stm32mp-r2.1-MISC-MEDIA-SOC-THERMAL.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0011-v5.15-stm32mp-r2-MISC-MEDIA-SOC-THERMAL.patch
View File

@ -1,23 +1,25 @@
From 7ec3e513a3c37c2e20b1f2545f6cb84e4422b045 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:50:21 +0200
Subject: [PATCH 11/22] v5.15-stm32mp-r2.1 MISC-MEDIA-SOC-THERMAL
From ba945334e6168553846f1fcc73a59a463a276255 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:54:37 +0100
Subject: [PATCH 11/22] v5.15-stm32mp-r2 MISC-MEDIA-SOC-THERMAL
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
CONTRIBUTING.md | 30 +
.../bindings/media/i2c/galaxycore,gc2145.yaml | 115 +
.../bindings/media/st,stm32-dcmipp.yaml | 96 +
.../bindings/soc/stm32/st,stm32mp1-hslv.yaml | 44 +
.../bindings/soc/stm32/stm32_hdp.txt | 39 +
MAINTAINERS | 17 +
SECURITY.md | 8 +
drivers/char/hw_random/stm32-rng.c | 229 +-
drivers/firmware/Kconfig | 2 +-
drivers/gpio/gpiolib-acpi.c | 3 +
drivers/gpio/gpiolib-of.c | 7 +
drivers/gpio/gpiolib.c | 28 +-
drivers/input/touchscreen/edt-ft5x06.c | 31 +
drivers/input/touchscreen/goodix.c | 51 +-
drivers/gpio/gpiolib.c | 20 +-
drivers/input/touchscreen/edt-ft5x06.c | 20 +
drivers/input/touchscreen/goodix.c | 39 +-
drivers/media/i2c/Kconfig | 12 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/gc2145.c | 1948 +++++++++++++++++
drivers/media/i2c/gc2145.c | 1949 +++++++++++++++++
drivers/media/i2c/ov5640.c | 459 +++-
drivers/media/i2c/st-mipid02.c | 10 +-
drivers/media/platform/Kconfig | 13 +
@ -42,16 +44,18 @@ Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
drivers/soc/st/stm32-hslv.c | 157 ++
drivers/soc/st/stm32_hdp.c | 242 ++
drivers/soc/st/stm32_pm_domain.c | 212 ++
drivers/thermal/st/Kconfig | 4 +-
drivers/thermal/st/stm_thermal.c | 30 +-
include/dt-bindings/soc/stm32-hdp.h | 108 +
include/dt-bindings/soc/stm32mp13-hdp.h | 133 ++
include/linux/gpio/machine.h | 1 +
include/linux/smscphy.h | 20 +
include/media/mipi-csi2.h | 45 +
include/media/v4l2-fwnode.h | 2 +
45 files changed, 7805 insertions(+), 257 deletions(-)
45 files changed, 8058 insertions(+), 253 deletions(-)
create mode 100644 CONTRIBUTING.md
create mode 100644 Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
create mode 100644 Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
create mode 100644 Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
create mode 100644 SECURITY.md
create mode 100644 drivers/media/i2c/gc2145.c
create mode 100644 drivers/media/platform/stm32/stm32-dcmipp/Makefile
@ -106,11 +110,329 @@ index 000000000000..3d1bacd78a54
+__Note__
+
+Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered.
diff --git a/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml b/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
new file mode 100644
index 000000000000..af07250ceadb
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc2145.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Galaxy Core 1/5'' UXGA CMOS Image Sensor
+
+maintainers:
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+description: |
+ The Galaxy Core GC2145 is a high quality 2 Mega CMOS image sensor, for mobile phone camera
+ applications and digital camera products. GC2145 incorporates a 1616V x 1232H active pixel
+ array, on-chip 10-bit ADC, and image signal processor. It is programmable through an I2C
+ interface. Image data is sent either through a parallel interface or through MIPI CSI-2.
+
+allOf:
+ - $ref: ../video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: galaxycore,gc2145
+
+ reg:
+ enum:
+ - 0x3c
+
+ clocks:
+ description: Reference to the xclk clock.
+ maxItems: 1
+
+ powerdown-gpios:
+ description: GPIO descriptor for the powerdown pin.
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO descriptor for the reset pin.
+ maxItems: 1
+
+ IOVDD-supply:
+ description: Power Supply for I/O circuits (1.7 - 3V).
+
+ AVDD-supply:
+ description: Power for analog circuit/sensor array (2.7 - 3V).
+
+ DVDD-supply:
+ description: Power for digital core (1.7 - 1.9V).
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description: |
+ Video output port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ anyOf:
+ - items:
+ - const: 1
+ - const: 2
+ - items:
+ - const: 1
+ - const: 2
+
+ required:
+ - data-lanes
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - powerdown-gpios
+ - reset-gpios
+ - IOVDD-supply
+ - AVDD-supply
+ - DVDD-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gc2145@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ IOVDD-supply = <&scmi_v3v3_sw>;
+ AVDD-supply = <&scmi_v3v3_sw>;
+ DVDD-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
new file mode 100644
index 000000000000..70631046017d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32-dcmipp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor binding
+
+maintainers:
+ - Hugues Fruchet <hugues.fruchet@foss.st.com>
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+properties:
+ compatible:
+ const: st,stm32mp13-dcmipp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: kclk
+
+ resets:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ DCMIPP supports a single port node with parallel bus.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+ default: 5
+
+ bus-width:
+ enum: [8, 10, 12, 14]
+ default: 8
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+ required:
+ - pclk-sample
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp13-clks.h>
+ #include <dt-bindings/reset/stm32mp13-resets.h>
+ dcmipp: dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+ clock-names = "kclk";
+
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ pclk-max-frequency = <120000000>;
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml b/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
new file mode 100644
index 000000000000..a228a5b262d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/st,stm32mp1-hslv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32MP1 HSLV IO Speed config assistant
+
+maintainers:
+ - Pascal Paillet <p.paillet@st.com>
+
+description: |
+ Some of the STMicroelectronics's STM32 MP13 IOs can be set to high speed mode
+ if their supply is lower than a 2.7V. The goal of this driver is to
+ automatically set the IOs to high speed mode depending on their supply's
+ regulator voltage value.
+
+properties:
+ compatible:
+ const: st,stm32mp13,hslv
+
+ hslv-supply:
+ description: Input supply phandle(s) for hslv input
+
+ st,syscon:
+ description: hslv sysconf register offset and mask
+
+required:
+ - compatible
+ - hslv-supply
+ - st,syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ hslv@1 {
+ compatible = "st,stm32mp13,hslv";
+
+ /* sdmmc1 hslv = 0x50 + 4 * 4 = 0x60 */
+ st,syscon = <&syscfg 0x60 0x1018>;
+ hslv-supply = <&sdmmc1_regu>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
new file mode 100644
index 000000000000..e2bd82f4980e
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
@@ -0,0 +1,39 @@
+STM32 - STM32MP1- HDP Pin configuration for STM32MP1
+=======================================================
+
+The Hardware Debug Port (HDP) allows the observation of internal signals. By using multiplexers,
+up to 16 signals for each of 8-bit output can be observed.
+
+Required Properties:
+
+ - compatible: Must be "st,stm32mp1-hdp"
+ - muxing-hdp: Indicates for each HDP pins selected which HDP output among the 16 available signals you want
+
+For each HDP pins you can select one of 16 signals which will be described in file : include/dt-bindings/soc/stm32-hdp.h
+
+Example
+-------
+
+In common dtsi file:
+
+hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+};
+
+In board-specific file:
+
+In this example I've selected HDP0, HDP6 and HDP7, and for HDP0 the output signal is HDP0_GPOVAL_0,
+for HDP6 is HDP6_GPOVAL_6, and for HDP7 is HDP7_GPOVAL_7.
+
+&hdp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
+
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
+ STM32_HDP(6, HDP6_GPOVAL_6) |
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 2bf1ad0fb2a6..f27b6574d93e 100644
index edc32575828b..29e2729008d9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7743,6 +7743,14 @@ F: kernel/futex/*
@@ -7753,6 +7753,14 @@ F: kernel/futex.c
F: tools/perf/bench/futex*
F: tools/testing/selftests/futex/
@ -125,7 +447,7 @@ index 2bf1ad0fb2a6..f27b6574d93e 100644
GATEWORKS SYSTEM CONTROLLER (GSC) DRIVER
M: Tim Harvey <tharvey@gateworks.com>
M: Robert Jones <rjones@gateworks.com>
@@ -11720,6 +11728,15 @@ T: git git://linuxtv.org/media_tree.git
@@ -11732,6 +11740,15 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
F: drivers/media/platform/stm32/stm32-dcmi.c
@ -465,57 +787,11 @@ index 97ce31e667fc..b54bfd332613 100644
help
System Control and Power Interface (SCPI) Message Protocol is
defined for the purpose of communication between the Application
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index 53be0bdf2bc3..dba8dfebf26a 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -702,6 +702,9 @@ int acpi_gpio_update_gpiod_lookup_flags(unsigned long *lookupflags,
case ACPI_PIN_CONFIG_PULLDOWN:
*lookupflags |= GPIO_PULL_DOWN;
break;
+ case ACPI_PIN_CONFIG_NOPULL:
+ *lookupflags |= GPIO_PULL_DISABLE;
+ break;
default:
break;
}
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 7a96eb626a08..e37a619aed56 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -354,6 +354,9 @@ struct gpio_desc *gpiod_get_from_of_node(const struct device_node *node,
if (flags & OF_GPIO_PULL_DOWN)
lflags |= GPIO_PULL_DOWN;
+ if (flags & OF_GPIO_PULL_DISABLE)
+ lflags |= GPIO_PULL_DISABLE;
+
ret = gpiod_configure_flags(desc, propname, lflags, dflags);
if (ret < 0) {
gpiod_put(desc);
@@ -556,6 +559,8 @@ struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
*flags |= GPIO_PULL_UP;
if (of_flags & OF_GPIO_PULL_DOWN)
*flags |= GPIO_PULL_DOWN;
+ if (of_flags & OF_GPIO_PULL_DISABLE)
+ *flags |= GPIO_PULL_DISABLE;
return desc;
}
@@ -621,6 +626,8 @@ static struct gpio_desc *of_parse_own_gpio(struct device_node *np,
*lflags |= GPIO_PULL_UP;
if (xlate_flags & OF_GPIO_PULL_DOWN)
*lflags |= GPIO_PULL_DOWN;
+ if (xlate_flags & OF_GPIO_PULL_DISABLE)
+ *lflags |= GPIO_PULL_DISABLE;
if (of_property_read_bool(np, "input"))
*dflags |= GPIOD_IN;
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 8c041a8dd9d8..73737407cc82 100644
index 320baed949ee..db4ad34fcac4 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -421,8 +421,16 @@ static int devprop_gpiochip_set_names(struct gpio_chip *chip)
@@ -422,8 +422,16 @@ static int devprop_gpiochip_set_names(struct gpio_chip *chip)
if (count > chip->ngpio)
count = chip->ngpio;
@ -534,7 +810,7 @@ index 8c041a8dd9d8..73737407cc82 100644
kfree(names);
@@ -733,10 +741,12 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
@@ -708,10 +716,12 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
INIT_LIST_HEAD(&gdev->pin_ranges);
#endif
@ -550,31 +826,8 @@ index 8c041a8dd9d8..73737407cc82 100644
if (ret)
goto err_remove_from_list;
@@ -3869,9 +3879,11 @@ int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
if (lflags & GPIO_OPEN_SOURCE)
set_bit(FLAG_OPEN_SOURCE, &desc->flags);
- if ((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) {
+ if (((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) ||
+ ((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DISABLE)) ||
+ ((lflags & GPIO_PULL_DOWN) && (lflags & GPIO_PULL_DISABLE))) {
gpiod_err(desc,
- "both pull-up and pull-down enabled, invalid configuration\n");
+ "multiple pull-up, pull-down or pull-disable enabled, invalid configuration\n");
return -EINVAL;
}
@@ -3879,6 +3891,8 @@ int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
set_bit(FLAG_PULL_UP, &desc->flags);
else if (lflags & GPIO_PULL_DOWN)
set_bit(FLAG_PULL_DOWN, &desc->flags);
+ else if (lflags & GPIO_PULL_DISABLE)
+ set_bit(FLAG_BIAS_DISABLE, &desc->flags);
ret = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY));
if (ret < 0)
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index bb2e1cbffba7..8acf3d4d8d75 100644
index bb2e1cbffba7..918d81e6ebac 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -30,6 +30,8 @@
@ -597,7 +850,7 @@ index bb2e1cbffba7..8acf3d4d8d75 100644
case 0x5a: /* Solomon Goldentek Display */
snprintf(model_name, EDT_NAME_LEN, "GKTW50SCED1R0");
break;
@@ -1078,13 +1084,38 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
@@ -1078,6 +1084,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
const struct edt_i2c_chip_data *chip_data;
struct edt_ft5x06_ts_data *tsdata;
u8 buf[2] = { 0xfc, 0x00 };
@ -605,11 +858,10 @@ index bb2e1cbffba7..8acf3d4d8d75 100644
+ struct device_node *np;
struct input_dev *input;
unsigned long irq_flags;
+ struct device_link *dlink;
int error;
char fw_version[EDT_NAME_LEN];
dev_dbg(&client->dev, "probing for EDT FT5x06 I2C\n");
@@ -1255,6 +1263,18 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
if (error)
return error;
+ np = of_parse_phandle(client->dev.of_node, "panel", 0);
+ if (np) {
@ -618,26 +870,16 @@ index bb2e1cbffba7..8acf3d4d8d75 100644
+ if (!panel)
+ return -EPROBE_DEFER;
+
+ dlink = device_link_add(&client->dev, &panel->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
+
+ if (IS_ERR(dlink)) {
+ error = PTR_ERR(dlink);
+ dev_err(&client->dev,
+ "Failed to add link to device %d\n", error);
+ return error;
+ }
+
+ if (dlink && dlink->status != DL_STATE_CONSUMER_PROBE)
+ return -EPROBE_DEFER;
+
+ device_link_add(&client->dev, &panel->dev, DL_FLAG_STATELESS |
+ DL_FLAG_AUTOREMOVE_SUPPLIER);
+ put_device(&panel->dev);
+ }
+
tsdata = devm_kzalloc(&client->dev, sizeof(*tsdata), GFP_KERNEL);
if (!tsdata) {
dev_err(&client->dev, "failed to allocate driver data.\n");
edt_ft5x06_ts_prepare_debugfs(tsdata, dev_driver_string(&client->dev));
dev_dbg(&client->dev,
diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c
index 166d36b2626e..819880e7d00c 100644
index 3667f7e51fde..890cc8270c6a 100644
--- a/drivers/input/touchscreen/goodix.c
+++ b/drivers/input/touchscreen/goodix.c
@@ -16,6 +16,7 @@
@ -648,7 +890,7 @@ index 166d36b2626e..819880e7d00c 100644
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
@@ -257,7 +258,7 @@ static int goodix_ts_read_input_report(struct goodix_ts_data *ts, u8 *data)
@@ -248,7 +249,7 @@ static int goodix_ts_read_input_report(struct goodix_ts_data *ts, u8 *data)
error = goodix_i2c_read(ts->client, addr, data,
header_contact_keycode_size);
if (error) {
@ -657,7 +899,7 @@ index 166d36b2626e..819880e7d00c 100644
error);
return error;
}
@@ -385,7 +386,7 @@ static irqreturn_t goodix_ts_irq_handler(int irq, void *dev_id)
@@ -376,7 +377,7 @@ static irqreturn_t goodix_ts_irq_handler(int irq, void *dev_id)
goodix_process_events(ts);
if (goodix_i2c_write_u8(ts->client, GOODIX_READ_COOR_ADDR, 0) < 0)
@ -666,43 +908,16 @@ index 166d36b2626e..819880e7d00c 100644
return IRQ_HANDLED;
}
@@ -1155,10 +1156,35 @@ static int goodix_ts_probe(struct i2c_client *client,
@@ -1135,6 +1136,8 @@ static int goodix_ts_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct goodix_ts_data *ts;
+ struct mipi_dsi_device *panel;
+ struct device_node *np;
+ struct device_link *dlink;
int error;
dev_dbg(&client->dev, "I2C Address: 0x%02x\n", client->addr);
+ np = of_parse_phandle(client->dev.of_node, "panel", 0);
+ if (np) {
+ panel = of_find_mipi_dsi_device_by_node(np);
+ of_node_put(np);
+ if (!panel)
+ return -EPROBE_DEFER;
+
+ dlink = device_link_add(&client->dev, &panel->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
+
+ if (IS_ERR(dlink)) {
+ error = PTR_ERR(dlink);
+ dev_err(&client->dev,
+ "Failed to add link to device %d\n", error);
+ return error;
+ }
+
+ if (dlink && dlink->status != DL_STATE_CONSUMER_PROBE)
+ return -EPROBE_DEFER;
+
+ put_device(&panel->dev);
+ }
+
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
dev_err(&client->dev, "I2C check functionality failed.\n");
return -ENXIO;
@@ -1206,6 +1232,26 @@ static int goodix_ts_probe(struct i2c_client *client,
@@ -1186,6 +1189,26 @@ static int goodix_ts_probe(struct i2c_client *client,
error = goodix_reset(ts);
if (error)
return error;
@ -729,7 +944,25 @@ index 166d36b2626e..819880e7d00c 100644
}
error = goodix_i2c_test(client);
@@ -1307,6 +1353,7 @@ static int __maybe_unused goodix_suspend(struct device *dev)
@@ -1232,6 +1255,17 @@ static int goodix_ts_probe(struct i2c_client *client,
return error;
}
+ np = of_parse_phandle(client->dev.of_node, "panel", 0);
+ if (np) {
+ panel = of_find_mipi_dsi_device_by_node(np);
+ of_node_put(np);
+ if (!panel)
+ return -EPROBE_DEFER;
+ device_link_add(&client->dev, &panel->dev, DL_FLAG_STATELESS |
+ DL_FLAG_AUTOREMOVE_SUPPLIER);
+ put_device(&panel->dev);
+ }
+
return 0;
}
@@ -1287,6 +1321,7 @@ static int __maybe_unused goodix_suspend(struct device *dev)
* sooner, delay 58ms here.
*/
msleep(58);
@ -772,10 +1005,10 @@ index 83268f20aa3a..3916c2818522 100644
obj-$(CONFIG_SDR_MAX2175) += max2175.o
diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
new file mode 100644
index 000000000000..222e47d76321
index 000000000000..f892f18dc19b
--- /dev/null
+++ b/drivers/media/i2c/gc2145.c
@@ -0,0 +1,1948 @@
@@ -0,0 +1,1949 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * A V4L2 driver for Galaxycore GC2145 camera.
@ -2118,13 +2351,14 @@ index 000000000000..222e47d76321
+
+ /*
+ * Adjust the MIPI Fifo Full Level
+ * TODO - would need to understand better the constraints
+ * 640x480 RGB: 0x0190
+ * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0001
+ * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0010
+ * 1600x1200 RAW: 0x0190
+ */
+ if (gc2145_format->colorspace != V4L2_COLORSPACE_RAW) {
+ if (gc2145->mode->width == 1280 || gc2145->mode->width == 1600)
+ fifo_full_lvl = 0x0001;
+ if ((gc2145->mode->width == 720) || (gc2145->mode->width == 1200))
+ fifo_full_lvl = 0x0010;
+ else
+ fifo_full_lvl = 0x0190;
+ } else
@ -2725,7 +2959,7 @@ index 000000000000..222e47d76321
+MODULE_DESCRIPTION("GalaxyCore GC2145 sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
index a141552531f7..5ec6addf777b 100644
index db5a19babe67..df2b1fc1a4eb 100644
--- a/drivers/media/i2c/ov5640.c
+++ b/drivers/media/i2c/ov5640.c
@@ -65,6 +65,7 @@
@ -8166,7 +8400,7 @@ index 74afbb7a4f5e..654ca9e9808c 100644
of_platform_default_populate(NULL, NULL, NULL);
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 61a1c87cd501..1c03db71661d 100644
index 3115abb3f52a..917428242775 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -58,7 +58,7 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
@ -8228,7 +8462,7 @@ index a05e9fbcd3e0..e4909f6467f9 100644
obj-y += ti/
diff --git a/drivers/soc/st/Kconfig b/drivers/soc/st/Kconfig
new file mode 100644
index 000000000000..e0ee54bcd04e
index 000000000000..8fde9d232291
--- /dev/null
+++ b/drivers/soc/st/Kconfig
@@ -0,0 +1,25 @@
@ -8252,9 +8486,9 @@ index 000000000000..e0ee54bcd04e
+
+config STM32_PM_DOMAINS
+ bool "STM32 PM domains"
+ depends on MACH_STM32MP157 || MACH_STM32MP13
+ depends on MACH_STM32MP157
+ select PM_GENERIC_DOMAINS
+ default y if MACH_STM32MP157 || MACH_STM32MP13
+ default y if MACH_STM32MP157
+
+endif # ARCH_STM32
diff --git a/drivers/soc/st/Makefile b/drivers/soc/st/Makefile
@ -8895,23 +9129,6 @@ index 000000000000..0386624c20f2
+ return platform_driver_register(&stm32_pm_domains_driver);
+}
+core_initcall(stm32_pm_domains_init);
diff --git a/drivers/thermal/st/Kconfig b/drivers/thermal/st/Kconfig
index 58ece381956b..91db3e2885d6 100644
--- a/drivers/thermal/st/Kconfig
+++ b/drivers/thermal/st/Kconfig
@@ -18,10 +18,10 @@ config ST_THERMAL_MEMMAP
config STM32_THERMAL
tristate "Thermal framework support on STMicroelectronics STM32 series of SoCs"
- depends on MACH_STM32MP157
+ depends on MACH_STM32MP157 || MACH_STM32MP13
default y
help
Support for thermal framework on STMicroelectronics STM32 series of
SoCs. This thermal driver allows to access to general thermal framework
functionalities and to access to SoC sensor functionalities. This
- configuration is fully dependent of MACH_STM32MP157.
+ configuration is fully dependent of MACH_STM32MP157 or MACH_STM32MP13.
diff --git a/drivers/thermal/st/stm_thermal.c b/drivers/thermal/st/stm_thermal.c
index 5fd3fb8912a6..1e065a3323f9 100644
--- a/drivers/thermal/st/stm_thermal.c
@ -9248,18 +9465,6 @@ index 000000000000..091c1c83587a
+#define HDP7_GPOVAL_7 15
+
+#endif /* _DT_BINDINGS_STM32_HDP_H */
diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h
index d755e529c1e3..1ed588fec969 100644
--- a/include/linux/gpio/machine.h
+++ b/include/linux/gpio/machine.h
@@ -14,6 +14,7 @@ enum gpio_lookup_flags {
GPIO_TRANSITORY = (1 << 3),
GPIO_PULL_UP = (1 << 4),
GPIO_PULL_DOWN = (1 << 5),
+ GPIO_PULL_DISABLE = (1 << 6),
GPIO_LOOKUP_FLAGS_DEFAULT = GPIO_ACTIVE_HIGH | GPIO_PERSISTENT,
};
diff --git a/include/linux/smscphy.h b/include/linux/smscphy.h
index 1a136271ba6a..00884908e509 100644
--- a/include/linux/smscphy.h

112
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0012-v5.15-stm32mp-r2.1-MFD.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0012-v5.15-stm32mp-r2-MFD.patch
View File

@ -1,39 +1,105 @@
From e2857bb430c4d142e2d73a55fdb488eabb0e4805 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:51:02 +0200
Subject: [PATCH 12/22] v5.15-stm32mp-r2.1 MFD
From 69ed3aa4864f05afff66ffd7596de3b45d739360 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:55:56 +0100
Subject: [PATCH 12/22] v5.15-stm32mp-r2 MFD
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/memory/Kconfig | 2 +-
.../bindings/mfd/st,stm32-lptimer.yaml | 3 +
.../bindings/mfd/st,stm32mp1-pwr.txt | 57 +++
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/stm32-pwr.c | 423 +++++++++++++++++++++++++++++++
drivers/mfd/stm32-pwr.c | 423 ++++++++++++++++++
drivers/mfd/stmfx.c | 2 -
drivers/mfd/stpmic1.c | 6 +
drivers/mfd/wm8994-core.c | 6 +
include/linux/mfd/stm32-timers.h | 1 +
8 files changed, 448 insertions(+), 3 deletions(-)
9 files changed, 507 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
create mode 100644 drivers/mfd/stm32-pwr.c
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 72c0df129d5c..dbbc96ad730e 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -217,7 +217,7 @@ config RENESAS_RPCIF
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 8bcea8dd7d90..6e518ae12e7f 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,9 @@ properties:
config STM32_FMC2_EBI
tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
- depends on MACH_STM32MP157 || COMPILE_TEST
+ depends on ARCH_STM32 || COMPILE_TEST
select MFD_SYSCON
help
Select this option to enable the STM32 FMC2 External Bus Interface
wakeup-source: true
+ power-domains:
+ maxItems: 1
+
pwm:
type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
new file mode 100644
index 000000000000..b5f414a19120
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
@@ -0,0 +1,57 @@
+STMicroelectronics STM32MP1 Power Management Controller
+=======================================================
+
+The PWR IP is responsible for handling the power related resources such as
+clocks, power supplies and resets. It provides 6 wake-up pins that are handled
+by an interrupt-controller. Wake-up pin can be used to wake-up from STANDBY SoC state.
+
+Required properties:
+- compatible should be: "st,stm32mp1-pwr"
+- reg: should be register base and length as documented in the
+ datasheet
+- interrupts: contains the reference to the gic wake-up pin interrupt
+- interrupt-controller; Enable interrupt controller for wake-up pins.
+- #interrupt-cells = <3>
+- st,wakeup-pins: contains a list of GPIO spec describing each wake-up pin.
+
+Optional Properties:
+- pwr-supply: main soc power supply
+
+Interrupt consumers have to specify 3 cells:
+ - cell 1: wake-up pin id from 0 to 5
+ - cell 2: IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_RISING
+ - cell 3: Pull config: 0 = No Pull, 1=Pull Up, 2=Pull Down
+
+
+Example:
+
+ pwr: pwr@50001000 {
+ compatible = "st,stm32mp1-pwr", "simple-mfd";
+ reg = <0x50001000 0x400>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ st,wakeup-pins = <&gpioa 0 0>, <&gpioa 2 0>,
+ <&gpioc 13 0>, <&gpioi 8 0>,
+ <&gpioi 11 0>, <&gpioc 1 0>;
+
+ pwr-supply = <&vdd>;
+ };
+
+
+Example of interrupt user:
+gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@4 {
+ label = "WakeUp4";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&pwr>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING 1>;
+ wakeup-source;
+ };
+};
+
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index ef550d33af92..8b035ef7d7e9 100644
index d2f345245538..181730a693a1 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2044,6 +2044,16 @@ config MFD_STPMIC1
@@ -2042,6 +2042,16 @@ config MFD_STPMIC1
To compile this driver as a module, choose M here: the
module will be called stpmic1.
@ -551,7 +617,7 @@ index 7b1d270722ba..e2c98c66bf9f 100644
wm8994->supplies);
if (ret != 0) {
diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
index 5f5c43fd69dd..1b94325febb3 100644
index f8db83aedb2b..f48f04dc4187 100644
--- a/include/linux/mfd/stm32-timers.h
+++ b/include/linux/mfd/stm32-timers.h
@@ -31,6 +31,7 @@

341
recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0013-v5.15-stm32mp-r2-MMC.patch Normal file
View File

@ -0,0 +1,341 @@
From 99e2eb7f37c25b7e9a5e0b18af405d8bae95df12 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:56:26 +0100
Subject: [PATCH 13/22] v5.15-stm32mp-r2 MMC
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../devicetree/bindings/mmc/arm,pl18x.yaml | 6 ++
drivers/mmc/host/mmci.c | 7 +-
drivers/mmc/host/mmci_stm32_sdmmc.c | 93 +++++++++++++++----
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 40 +++++++-
4 files changed, 125 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 47595cb483be..eed54bee7665 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -53,6 +53,12 @@ properties:
items:
- const: arm,pl18x
- const: arm,primecell
+ - description: Entry for STMicroelectronics variant of PL18x.
+ This dedicated compatible is used by bootloaders.
+ items:
+ - const: st,stm32-sdmmc2
+ - const: arm,pl18x
+ - const: arm,primecell
clocks:
description: One or two clocks, the "apb_pclk" and the "MCLK"
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3765e2f4ad98..3d416c4edc7c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -280,7 +280,7 @@ static struct variant_data variant_stm32_sdmmc = {
static struct variant_data variant_stm32_sdmmcv2 = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
- .f_max = 208000000,
+ .f_max = 267000000,
.stm32_clkdiv = true,
.cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
.cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
@@ -2431,6 +2431,11 @@ static const struct amba_id mmci_ids[] = {
.mask = 0xf0ffffff,
.data = &variant_stm32_sdmmcv2,
},
+ {
+ .id = 0x20253180,
+ .mask = 0xf0ffffff,
+ .data = &variant_stm32_sdmmcv2,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index 4cceb9bab036..60bca78a72b1 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -43,6 +43,9 @@ struct sdmmc_lli_desc {
struct sdmmc_idma {
dma_addr_t sg_dma;
void *sg_cpu;
+ dma_addr_t bounce_dma_addr;
+ void *bounce_buf;
+ bool use_bounce_buffer;
};
struct sdmmc_dlyb {
@@ -54,6 +57,8 @@ struct sdmmc_dlyb {
static int sdmmc_idma_validate_data(struct mmci_host *host,
struct mmc_data *data)
{
+ struct sdmmc_idma *idma = host->dma_priv;
+ struct device *dev = mmc_dev(host->mmc);
struct scatterlist *sg;
int i;
@@ -61,41 +66,69 @@ static int sdmmc_idma_validate_data(struct mmci_host *host,
* idma has constraints on idmabase & idmasize for each element
* excepted the last element which has no constraint on idmasize
*/
+ idma->use_bounce_buffer = false;
for_each_sg(data->sg, sg, data->sg_len - 1, i) {
if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
!IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) {
- dev_err(mmc_dev(host->mmc),
+ dev_dbg(mmc_dev(host->mmc),
"unaligned scatterlist: ofst:%x length:%d\n",
data->sg->offset, data->sg->length);
- return -EINVAL;
+ goto use_bounce_buffer;
}
}
if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
- dev_err(mmc_dev(host->mmc),
+ dev_dbg(mmc_dev(host->mmc),
"unaligned last scatterlist: ofst:%x length:%d\n",
data->sg->offset, data->sg->length);
- return -EINVAL;
+ goto use_bounce_buffer;
}
+ return 0;
+
+use_bounce_buffer:
+ if (!idma->bounce_buf) {
+ idma->bounce_buf = dmam_alloc_coherent(dev,
+ host->mmc->max_req_size,
+ &idma->bounce_dma_addr,
+ GFP_KERNEL);
+ if (!idma->bounce_buf) {
+ dev_err(dev, "Unable to map allocate DMA bounce buffer.\n");
+ return -ENOMEM;
+ }
+ }
+
+ idma->use_bounce_buffer = true;
+
return 0;
}
static int _sdmmc_idma_prep_data(struct mmci_host *host,
struct mmc_data *data)
{
- int n_elem;
+ struct sdmmc_idma *idma = host->dma_priv;
- n_elem = dma_map_sg(mmc_dev(host->mmc),
- data->sg,
- data->sg_len,
- mmc_get_dma_dir(data));
+ if (idma->use_bounce_buffer) {
+ if (data->flags & MMC_DATA_WRITE) {
+ unsigned int xfer_bytes = data->blksz * data->blocks;
- if (!n_elem) {
- dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
- return -EINVAL;
- }
+ sg_copy_to_buffer(data->sg, data->sg_len,
+ idma->bounce_buf, xfer_bytes);
+ dma_wmb();
+ }
+ } else {
+ int n_elem;
+
+ n_elem = dma_map_sg(mmc_dev(host->mmc),
+ data->sg,
+ data->sg_len,
+ mmc_get_dma_dir(data));
+ if (!n_elem) {
+ dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
+ return -EINVAL;
+ }
+ }
return 0;
}
@@ -112,8 +145,19 @@ static int sdmmc_idma_prep_data(struct mmci_host *host,
static void sdmmc_idma_unprep_data(struct mmci_host *host,
struct mmc_data *data, int err)
{
- dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
- mmc_get_dma_dir(data));
+ struct sdmmc_idma *idma = host->dma_priv;
+
+ if (idma->use_bounce_buffer) {
+ if (data->flags & MMC_DATA_READ) {
+ unsigned int xfer_bytes = data->blksz * data->blocks;
+
+ sg_copy_from_buffer(data->sg, data->sg_len,
+ idma->bounce_buf, xfer_bytes);
+ }
+ } else {
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+ mmc_get_dma_dir(data));
+ }
}
static int sdmmc_idma_setup(struct mmci_host *host)
@@ -137,6 +181,8 @@ static int sdmmc_idma_setup(struct mmci_host *host)
host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
sizeof(struct sdmmc_lli_desc);
host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
+
+ host->mmc->max_req_size = SZ_1M;
} else {
host->mmc->max_segs = 1;
host->mmc->max_seg_size = host->mmc->max_req_size;
@@ -154,8 +200,16 @@ static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
struct scatterlist *sg;
int i;
- if (!host->variant->dma_lli || data->sg_len == 1) {
- writel_relaxed(sg_dma_address(data->sg),
+ if (!host->variant->dma_lli || data->sg_len == 1 ||
+ idma->use_bounce_buffer) {
+ u32 dma_addr;
+
+ if (idma->use_bounce_buffer)
+ dma_addr = idma->bounce_dma_addr;
+ else
+ dma_addr = sg_dma_address(data->sg);
+
+ writel_relaxed(dma_addr,
host->base + MMCI_STM32_IDMABASE0R);
writel_relaxed(MMCI_STM32_IDMAEN,
host->base + MMCI_STM32_IDMACTRLR);
@@ -241,11 +295,12 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
/*
* SDMMC_FBCK is selected when an external Delay Block is needed
- * with SDR104.
+ * with SDR104 or HS200.
*/
if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
clk |= MCI_STM32_CLK_BUSSPEED;
- if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
+ if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
clk &= ~MCI_STM32_CLK_SEL_MSK;
clk |= MCI_STM32_CLK_SELFBCK;
}
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 1c277fbb91f2..733f9857e801 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -9,6 +9,7 @@
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
@@ -231,6 +232,7 @@ struct stm32_fmc2_timings {
struct stm32_fmc2_nand {
struct nand_chip chip;
+ struct gpio_desc *wp_gpio;
struct stm32_fmc2_timings timings;
int ncs;
int cs_used[FMC2_MAX_CE];
@@ -1747,6 +1749,18 @@ static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
.setup_interface = stm32_fmc2_nfc_setup_interface,
};
+static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 1);
+}
+
+static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 0);
+}
+
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
struct device_node *dn)
{
@@ -1785,6 +1799,18 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
nand->cs_used[i] = cs;
}
+ nand->wp_gpio = devm_gpiod_get_from_of_node(nfc->dev, dn,
+ "wp-gpios", 0,
+ GPIOD_OUT_HIGH, "wp");
+ if (IS_ERR(nand->wp_gpio)) {
+ ret = PTR_ERR(nand->wp_gpio);
+ if (ret != -ENOENT)
+ return dev_err_probe(nfc->dev, ret,
+ "failed to request WP GPIO\n");
+
+ nand->wp_gpio = NULL;
+ }
+
nand_set_flash_node(&nand->chip, dn);
return 0;
@@ -1960,10 +1986,12 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
NAND_USES_DMA;
+ stm32_fmc2_nfc_wp_disable(nand);
+
/* Scan to find existence of the device */
ret = nand_scan(chip, nand->ncs);
if (ret)
- goto err_release_dma;
+ goto err_wp_enable;
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
@@ -1976,6 +2004,9 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
err_nand_cleanup:
nand_cleanup(chip);
+err_wp_enable:
+ stm32_fmc2_nfc_wp_enable(nand);
+
err_release_dma:
if (nfc->dma_ecc_ch)
dma_release_channel(nfc->dma_ecc_ch);
@@ -2016,15 +2047,20 @@ static int stm32_fmc2_nfc_remove(struct platform_device *pdev)
clk_disable_unprepare(nfc->clk);
+ stm32_fmc2_nfc_wp_enable(nand);
+
return 0;
}
static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
{
struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
+ struct stm32_fmc2_nand *nand = &nfc->nand;
clk_disable_unprepare(nfc->clk);
+ stm32_fmc2_nfc_wp_enable(nand);
+
pinctrl_pm_select_sleep_state(dev);
return 0;
@@ -2046,6 +2082,8 @@ static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
stm32_fmc2_nfc_init(nfc);
+ stm32_fmc2_nfc_wp_disable(nand);
+
for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
if (!(nfc->cs_assigned & BIT(chip_cs)))
continue;
--
2.17.1

603
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0014-v5.15-stm32mp-r2.1-NET-TTY.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0014-v5.15-stm32mp-r2-NET-TTY.patch
View File

File diff suppressed because it is too large Load Diff

64
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0015-v5.15-stm32mp-r2.1-PERF.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0015-v5.15-stm32mp-r2-PERF.patch
View File

@ -1,17 +1,19 @@
From 780373655145ec7ceb3689781dd9dc6c422a0c81 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:53:28 +0200
Subject: [PATCH 15/22] v5.15-stm32mp-r2.1 PERF
From df5b54b2fc266fd51fff7130ee8707027e2aa3ea Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:58:41 +0100
Subject: [PATCH 15/22] v5.15-stm32mp-r2 PERF
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
Documentation/admin-guide/perf/index.rst | 1 +
.../admin-guide/perf/stm32-ddr-pmu.rst | 44 ++
.../bindings/perf/stm32-ddr-pmu.yaml | 44 ++
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/stm32_ddr_pmu.c | 439 ++++++++++++++++++
5 files changed, 492 insertions(+)
6 files changed, 536 insertions(+)
create mode 100644 Documentation/admin-guide/perf/stm32-ddr-pmu.rst
create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
create mode 100644 drivers/perf/stm32_ddr_pmu.c
diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst
@ -76,6 +78,56 @@ index 000000000000..db647fc1acad
+
+ 20.021068551 seconds time elapsed
+
diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
new file mode 100644
index 000000000000..085f2886e580
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/stm32-ddr-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+ - Gerald Baeza <gerald.baeza@st.com>
+
+title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) bindings
+
+properties:
+ compatible:
+ const: st,stm32-ddr-pmu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ };
+...
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 77522e5efe11..fb55e0bbfb90 100644
--- a/drivers/perf/Kconfig

501
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0016-v5.15-stm32mp-r2.1-PHY-USB.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0016-v5.15-stm32mp-r2-PHY-USB.patch
View File

@ -1,34 +1,385 @@
From 55c55e32e74d48375a64917346cf768ef4da86e6 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:54:38 +0200
Subject: [PATCH 16/22] v5.15-stm32mp-r2.1 PHY-USB
From f593955537b76035054bfc42586146cd974c9ae3 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:59:56 +0100
Subject: [PATCH 16/22] v5.15-stm32mp-r2 PHY-USB
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/phy/st/phy-stm32-usbphyc.c | 233 +++++++-
.../bindings/phy/phy-stm32-usbphyc.yaml | 133 +++
.../devicetree/bindings/usb/dwc2.yaml | 33 +-
.../devicetree/bindings/usb/generic-ehci.yaml | 5 +
.../devicetree/bindings/usb/generic-ohci.yaml | 5 +
.../bindings/usb/st,typec-stm32g0.yaml | 83 ++
drivers/phy/st/phy-stm32-usbphyc.c | 233 +++++-
drivers/usb/core/hcd.c | 9 +-
drivers/usb/core/phy.c | 22 +-
drivers/usb/core/phy.h | 6 +-
drivers/usb/dwc2/core.h | 24 +-
drivers/usb/dwc2/core.h | 22 +-
drivers/usb/dwc2/core_intr.c | 3 +-
drivers/usb/dwc2/debugfs.c | 4 +-
drivers/usb/dwc2/drd.c | 79 ++-
drivers/usb/dwc2/drd.c | 79 +-
drivers/usb/dwc2/gadget.c | 2 +-
drivers/usb/dwc2/hcd.c | 61 +-
drivers/usb/dwc2/params.c | 75 +--
drivers/usb/dwc2/platform.c | 119 ++--
drivers/usb/dwc2/params.c | 75 +-
drivers/usb/dwc2/platform.c | 82 +-
drivers/usb/host/ehci-platform.c | 16 +-
drivers/usb/host/ohci-platform.c | 14 +-
drivers/usb/typec/ucsi/Kconfig | 10 +
drivers/usb/typec/ucsi/Makefile | 1 +
drivers/usb/typec/ucsi/ucsi.c | 49 +-
drivers/usb/typec/ucsi/ucsi.h | 2 +
drivers/usb/typec/ucsi/ucsi_stm32g0.c | 770 ++++++++++++++++++++++++++
19 files changed, 1334 insertions(+), 165 deletions(-)
drivers/usb/typec/ucsi/ucsi_stm32g0.c | 770 ++++++++++++++++++
24 files changed, 1551 insertions(+), 168 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
create mode 100644 drivers/usb/typec/ucsi/ucsi_stm32g0.c
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 3329f1d33a4f..750ce7074648 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -74,6 +74,10 @@ patternProperties:
"#phy-cells":
enum: [ 0x0, 0x1 ]
+ interrupts:
+ maxItems: 1
+ description: interrupt used for wakeup when port is used by USBH controller
+
connector:
type: object
allOf:
@@ -81,6 +85,119 @@ patternProperties:
properties:
vbus-supply: true
+ # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due
+ # to USB connector/receptacle, routing, ESD protection component,... Here is the list of
+ # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full-
+ # Speed, LS for Low-Speed)
+
+ st,current-boost-microamp:
+ description: Current boosting in uA
+ enum: [ 1000, 2000 ]
+
+ st,no-lsfs-fb-cap:
+ description: Disables the LS/FS feedback capacitor
+ type: boolean
+
+ st,decrease-hs-slew-rate:
+ description: Decreases the HS driver slew rate by 10%
+ type: boolean
+
+ st,tune-hs-dc-level:
+ description: |
+ Tunes the HS driver DC level
+ - <0> normal level
+ - <1> increases the level by 5 to 7 mV
+ - <2> increases the level by 10 to 14 mV
+ - <3> decreases the level by 5 to 7 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,enable-fs-rftime-tuning:
+ description: Enables the FS rise/fall tuning option
+ type: boolean
+
+ st,enable-hs-rftime-reduction:
+ description: Enables the HS rise/fall reduction feature
+ type: boolean
+
+ st,trim-hs-current:
+ description: |
+ Controls HS driver current trimming for choke compensation
+ - <0> = 18.87 mA target current / nominal + 0%
+ - <1> = 19.165 mA target current / nominal + 1.56%
+ - <2> = 19.46 mA target current / nominal + 3.12%
+ - <3> = 19.755 mA target current / nominal + 4.68%
+ - <4> = 20.05 mA target current / nominal + 6.24%
+ - <5> = 20.345 mA target current / nominal + 7.8%
+ - <6> = 20.64 mA target current / nominal + 9.36%
+ - <7> = 20.935 mA target current / nominal + 10.92%
+ - <8> = 21.23 mA target current / nominal + 12.48%
+ - <9> = 21.525 mA target current / nominal + 14.04%
+ - <10> = 21.82 mA target current / nominal + 15.6%
+ - <11> = 22.115 mA target current / nominal + 17.16%
+ - <12> = 22.458 mA target current / nominal + 19.01%
+ - <13> = 22.755 mA target current / nominal + 20.58%
+ - <14> = 23.052 mA target current / nominal + 22.16%
+ - <15> = 23.348 mA target current / nominal + 23.73%
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ default: 0
+
+ st,trim-hs-impedance:
+ description: |
+ Controls HS driver impedance tuning for choke compensation
+ - <0> = no impedance offset
+ - <1> = reduce the impedance by 2 ohms
+ - <2> = reduce the impedance by 4 ohms
+ - <3> = reduce the impedance by 6 ohms
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,tune-squelch-level:
+ description: |
+ Tunes the squelch DC threshold value
+ - <0> = no shift in threshold
+ - <1> = threshold shift by +7 mV
+ - <2> = threshold shift by -5 mV
+ - <3> = threshold shift by +14 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,enable-hs-rx-gain-eq:
+ description: Enables the HS Rx gain equalizer
+ type: boolean
+
+ st,tune-hs-rx-offset:
+ description: |
+ Adjusts the HS Rx offset
+ - <0> = no offset
+ - <1> = offset of +5 mV
+ - <2> = offset of +10 mV
+ - <3> = offset of -5 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,no-hs-ftime-ctrl:
+ description: Disables the HS fall time control of single ended signals during pre-emphasis
+ type: boolean
+
+ st,no-lsfs-sc:
+ description: Disables the short circuit protection in LS/FS driver
+ type: boolean
+
+ st,enable-hs-tx-staggering:
+ description: Enables the basic staggering in HS Tx mode
+ type: boolean
+
allOf:
- if:
properties:
@@ -137,6 +254,14 @@ examples:
reg = <0>;
phy-supply = <&vdd_usb>;
#phy-cells = <0>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>;
@@ -147,6 +272,14 @@ examples:
reg = <1>;
phy-supply = <&vdd_usb>;
#phy-cells = <1>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
};
...
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 10c7d9b6cc53..882a2f1e0738 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -9,6 +9,9 @@ title: DesignWare HS OTG USB 2.0 controller Bindings
maintainers:
- Rob Herring <robh@kernel.org>
+allOf:
+ - $ref: usb-drd.yaml#
+
properties:
compatible:
oneOf:
@@ -101,12 +104,17 @@ properties:
description: reference to the VBUS and ID sensing comparators supply, in
order to perform OTG operation, used on STM32MP15 SoCs.
- dr_mode:
- enum: [host, peripheral, otg]
+ dr_mode: true
- usb-role-switch:
- $ref: /schemas/types.yaml#/definitions/flag
- description: Support role switch.
+ otg-rev: true
+
+ hnp-disable: true
+
+ srp-disable: true
+
+ usb-role-switch: true
+
+ role-switch-default-mode: true
g-rx-fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -130,6 +138,21 @@ properties:
description: If present indicates that we need to reset the PHY when we
detect a wakeup. This is due to a hardware errata.
+ port:
+ description:
+ Any connector to the data bus of this controller should be modelled
+ using the OF graph bindings specified, if the "usb-role-switch"
+ property is used.
+ $ref: /schemas/graph.yaml#/properties/port
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If present indicates this device has wakeup capabilities
+
+dependencies:
+ port: [ usb-role-switch ]
+ role-switch-default-mode: [ usb-role-switch ]
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index cb5da1df8d40..0b12acf804ec 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -149,6 +149,11 @@ properties:
- host
- otg
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate this device has wakeup capabilities.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index d5fd3aa53ed2..ef237675a83a 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -116,6 +116,11 @@ properties:
- host
- otg
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate this device has wakeup capabilities.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml b/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
new file mode 100644
index 000000000000..b2729bd015a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/st,typec-stm32g0.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: STMicroelectronics STM32G0 Type-C controller bindings
+
+description: |
+ The STM32G0 MCU can be programmed to control Type-C connector(s) through I2C
+ typically using the UCSI protocol over I2C, with a dedicated alert
+ (interrupt) pin.
+
+maintainers:
+ - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+properties:
+ compatible:
+ const: st,stm32g0-typec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ connector:
+ type: object
+ allOf:
+ - $ref: ../connector/usb-connector.yaml#
+
+ firmware-name:
+ description: |
+ Should contain the name of the default firmware image
+ file located on the firmware search path
+
+ wakeup-source: true
+ power-domains: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ stm32g0@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on GPIO PE12 */
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioe>;
+
+ /* Example with one type-C connector */
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+ };
+
+ usbotg_hs {
+ usb-role-switch;
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_ep>;
+ };
+ };
+ };
+...
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index 27f7e2292cf0..6115f9b21ee1 100644
index cd0747ab6267..af198f7c3f09 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -12,6 +12,7 @@
@ -298,7 +649,7 @@ index 27f7e2292cf0..6115f9b21ee1 100644
goto clk_disable;
}
@@ -554,6 +746,15 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
@@ -552,6 +744,15 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
usbphyc->phys[port]->vbus = NULL;
}
@ -314,7 +665,7 @@ index 27f7e2292cf0..6115f9b21ee1 100644
port++;
}
@@ -602,6 +803,25 @@ static int stm32_usbphyc_remove(struct platform_device *pdev)
@@ -600,6 +801,25 @@ static int stm32_usbphyc_remove(struct platform_device *pdev)
return 0;
}
@ -340,7 +691,7 @@ index 27f7e2292cf0..6115f9b21ee1 100644
static const struct of_device_id stm32_usbphyc_of_match[] = {
{ .compatible = "st,stm32mp1-usbphyc", },
{ },
@@ -614,6 +834,7 @@ static struct platform_driver stm32_usbphyc_driver = {
@@ -612,6 +832,7 @@ static struct platform_driver stm32_usbphyc_driver = {
.driver = {
.of_match_table = stm32_usbphyc_of_match,
.name = "stm32-usbphyc",
@ -451,7 +802,7 @@ index 20a267cd986b..3df4ddbb6046 100644
#endif /* __USB_CORE_PHY_H_ */
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 71e62b3081db..3edf73858ec3 100644
index 71e62b3081db..255fca4e8346 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -238,11 +238,14 @@ enum dwc2_ep0_state {
@ -496,15 +847,7 @@ index 71e62b3081db..3edf73858ec3 100644
* @hcd_enabled: Host mode sub-driver initialization indicator.
* @gadget_enabled: Peripheral mode sub-driver initialization indicator.
* @ll_hw_enabled: Status of low-level hardware resources.
@@ -1027,6 +1028,7 @@ struct dwc2_hregs_backup {
* @ctrl_out_desc: EP0 OUT data phase desc chain pointer
* @irq: Interrupt request line number
* @clk: Pointer to otg clock
+ * @utmi_clk: Pointer to utmi_clk clock
* @reset: Pointer to dwc2 reset controller
* @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
* @regset: A pointer to a struct debugfs_regset32, which contains
@@ -1066,6 +1068,7 @@ struct dwc2_hsotg {
@@ -1066,6 +1067,7 @@ struct dwc2_hsotg {
enum usb_otg_state op_state;
enum usb_dr_mode dr_mode;
struct usb_role_switch *role_sw;
@ -512,14 +855,6 @@ index 71e62b3081db..3edf73858ec3 100644
unsigned int hcd_enabled:1;
unsigned int gadget_enabled:1;
unsigned int ll_hw_enabled:1;
@@ -1088,6 +1091,7 @@ struct dwc2_hsotg {
void *priv;
int irq;
struct clk *clk;
+ struct clk *utmi_clk;
struct reset_control *reset;
struct reset_control *reset_ecc;
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index a5c52b237e72..c786560fb54e 100644
--- a/drivers/usb/dwc2/core_intr.c
@ -1055,69 +1390,10 @@ index 59e119345994..d300ae3d9274 100644
if (!valid)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 7a09476e9f19..7defbe5d8b04 100644
index 265d437ca0f1..d16a69355e89 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -131,10 +131,16 @@ static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
if (ret)
return ret;
+ if (hsotg->utmi_clk) {
+ ret = clk_prepare_enable(hsotg->utmi_clk);
+ if (ret)
+ goto err_dis_reg;
+ }
+
if (hsotg->clk) {
ret = clk_prepare_enable(hsotg->clk);
if (ret)
- return ret;
+ goto err_dis_utmi_clk;
}
if (hsotg->uphy) {
@@ -143,10 +149,29 @@ static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
} else {
ret = phy_init(hsotg->phy);
- if (ret == 0)
+ if (ret == 0) {
ret = phy_power_on(hsotg->phy);
+ if (ret)
+ phy_exit(hsotg->phy);
+ }
}
+ if (ret)
+ goto err_dis_clk;
+
+ return 0;
+
+err_dis_clk:
+ if (hsotg->clk)
+ clk_disable_unprepare(hsotg->clk);
+
+err_dis_utmi_clk:
+ if (hsotg->utmi_clk)
+ clk_disable_unprepare(hsotg->utmi_clk);
+
+err_dis_reg:
+ regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
+
return ret;
}
@@ -186,6 +211,9 @@ static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
if (hsotg->clk)
clk_disable_unprepare(hsotg->clk);
+ if (hsotg->utmi_clk)
+ clk_disable_unprepare(hsotg->utmi_clk);
+
return regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
}
@@ -210,20 +238,16 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
@@ -222,20 +222,16 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
int i, ret;
hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
@ -1144,7 +1420,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
reset_control_deassert(hsotg->reset_ecc);
@@ -239,11 +263,8 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
@@ -251,11 +247,8 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
case -ENOSYS:
hsotg->phy = NULL;
break;
@ -1157,7 +1433,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
}
}
@@ -256,12 +277,8 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
@@ -268,12 +261,8 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
case -ENXIO:
hsotg->uphy = NULL;
break;
@ -1171,7 +1447,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
}
}
}
@@ -270,10 +287,13 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
@@ -282,10 +271,8 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
/* Clock */
hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
@ -1181,15 +1457,10 @@ index 7a09476e9f19..7defbe5d8b04 100644
- }
+ if (IS_ERR(hsotg->clk))
+ return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n");
+
+ hsotg->utmi_clk = devm_clk_get_optional(hsotg->dev, "utmi");
+ if (IS_ERR(hsotg->utmi_clk))
+ return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->utmi_clk),
+ "cannot get utmi clock\n");
/* Regulators */
for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
@@ -281,12 +301,9 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
@@ -293,12 +280,9 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
hsotg->supplies);
@ -1205,7 +1476,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
return 0;
}
@@ -546,16 +563,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
@@ -558,16 +542,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
if (IS_ERR(hsotg->usb33d)) {
retval = PTR_ERR(hsotg->usb33d);
@ -1224,7 +1495,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
goto error;
}
@@ -570,8 +583,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
@@ -582,8 +562,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
retval = dwc2_drd_init(hsotg);
if (retval) {
@ -1234,7 +1505,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
goto error_init;
}
@@ -657,8 +669,19 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
@@ -669,8 +648,19 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
bool is_device_mode = dwc2_is_device_mode(dwc2);
int ret = 0;
@ -1255,7 +1526,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
dwc2_drd_suspend(dwc2);
@@ -699,6 +722,9 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
@@ -711,6 +701,9 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
dwc2->phy_off_for_suspend = true;
}
@ -1265,7 +1536,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
return ret;
}
@@ -707,6 +733,9 @@ static int __maybe_unused dwc2_resume(struct device *dev)
@@ -719,6 +712,9 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
@ -1275,7 +1546,7 @@ index 7a09476e9f19..7defbe5d8b04 100644
if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
ret = __dwc2_lowlevel_hw_enable(dwc2);
if (ret)
@@ -739,10 +768,12 @@ static int __maybe_unused dwc2_resume(struct device *dev)
@@ -751,10 +747,12 @@ static int __maybe_unused dwc2_resume(struct device *dev)
spin_unlock_irqrestore(&dwc2->lock, flags);
}
@ -1436,7 +1707,7 @@ index 8a8eb5cb8e0f..480d533d762f 100644
obj-$(CONFIG_UCSI_CCG) += ucsi_ccg.o
+obj-$(CONFIG_UCSI_STM32G0) += ucsi_stm32g0.o
diff --git a/drivers/usb/typec/ucsi/ucsi.c b/drivers/usb/typec/ucsi/ucsi.c
index dca6803a75bd..cde70a9c838e 100644
index 1f23eb543d8f..9659819ca2c9 100644
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -205,8 +205,11 @@ void ucsi_altmode_update_active(struct ucsi_connector *con)
@ -1453,7 +1724,7 @@ index dca6803a75bd..cde70a9c838e 100644
return;
}
cur = 0xff;
@@ -1154,12 +1157,8 @@ static int ucsi_register_port(struct ucsi *ucsi, int index)
@@ -1156,12 +1159,8 @@ static int ucsi_register_port(struct ucsi *ucsi, int index)
ucsi_port_psy_changed(con);
}
@ -1468,7 +1739,7 @@ index dca6803a75bd..cde70a9c838e 100644
/* Only notify USB controller if partner supports USB data */
if (!(UCSI_CONSTAT_PARTNER_FLAGS(con->status.flags) & UCSI_CONSTAT_PARTNER_FLAG_USB))
@@ -1344,7 +1343,9 @@ EXPORT_SYMBOL_GPL(ucsi_destroy);
@@ -1345,7 +1344,9 @@ EXPORT_SYMBOL_GPL(ucsi_destroy);
*/
int ucsi_register(struct ucsi *ucsi)
{
@ -1479,7 +1750,7 @@ index dca6803a75bd..cde70a9c838e 100644
ret = ucsi->ops->read(ucsi, UCSI_VERSION, &ucsi->version,
sizeof(ucsi->version));
@@ -1354,6 +1355,33 @@ int ucsi_register(struct ucsi *ucsi)
@@ -1355,6 +1356,33 @@ int ucsi_register(struct ucsi *ucsi)
if (!ucsi->version)
return -ENODEV;
@ -1513,7 +1784,7 @@ index dca6803a75bd..cde70a9c838e 100644
queue_work(system_long_wq, &ucsi->work);
return 0;
@@ -1387,6 +1415,9 @@ void ucsi_unregister(struct ucsi *ucsi)
@@ -1388,6 +1416,9 @@ void ucsi_unregister(struct ucsi *ucsi)
}
kfree(ucsi->connector);

340
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0017-v5.15-stm32mp-r2.1-PINCTRL-REGULATOR-SPI.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0017-v5.15-stm32mp-r2-PINCTRL-REGULATOR-SPI.patch
View File

@ -1,11 +1,16 @@
From 91f1de6f27098c2093dcea33a16450d5934454b9 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:56:09 +0200
Subject: [PATCH 17/22] v5.15-stm32mp-r2.1 PINCTRL-REGULATOR-SPI
From f7a7db118a4e7aa18f8038644ea143c5f1432c4d Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:03:16 +0100
Subject: [PATCH 17/22] v5.15-stm32mp-r2 PINCTRL-REGULATOR-SPI
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 237 ++++++++----
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 8 +
.../regulator/protection-consumer.txt | 23 ++
.../bindings/regulator/st,stm32-vrefbuf.yaml | 4 +-
.../bindings/spi/st,stm32-qspi.yaml | 8 +
.../devicetree/bindings/spi/st,stm32-spi.yaml | 23 ++
drivers/pinctrl/stm32/pinctrl-stm32.c | 237 ++++++++---
drivers/pinctrl/stm32/pinctrl-stm32.h | 16 +-
drivers/pinctrl/stm32/pinctrl-stm32mp135.c | 3 +-
drivers/pinctrl/stm32/pinctrl-stm32mp157.c | 2 +-
@ -13,22 +18,157 @@ Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
drivers/regulator/Makefile | 1 +
drivers/regulator/protection-consumer.c | 137 +++++++
drivers/regulator/scmi-regulator.c | 99 +++--
drivers/regulator/stm32-pwr.c | 85 ++++-
drivers/regulator/stm32-pwr.c | 85 +++-
drivers/regulator/stm32-vrefbuf.c | 69 +++-
drivers/regulator/stpmic1_regulator.c | 182 ++++++++-
drivers/regulator/stpmic1_regulator.c | 182 +++++++-
drivers/spi/Kconfig | 1 +
drivers/spi/spi-mem.c | 2 +-
drivers/spi/spi-stm32-qspi.c | 151 ++++++--
drivers/spi/spi-stm32.c | 396 ++++++++++++++------
drivers/spi/spi-stm32-qspi.c | 151 +++++--
drivers/spi/spi-stm32.c | 388 ++++++++++++------
include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
include/dt-bindings/spi/spi-stm32.h | 15 +
include/linux/of_gpio.h | 1 +
18 files changed, 1132 insertions(+), 277 deletions(-)
22 files changed, 1188 insertions(+), 278 deletions(-)
create mode 100644 Documentation/devicetree/bindings/regulator/protection-consumer.txt
create mode 100644 drivers/regulator/protection-consumer.c
create mode 100644 include/dt-bindings/spi/spi-stm32.h
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index dfee6d38a701..7348f40d49b5 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -140,9 +140,13 @@ patternProperties:
* ...
* 16 : Alternate Function 15
* 17 : Analog
+ * 18 : Reserved
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
+ Setting the pinmux's function to the Reserved (RSVD) value is used to inform
+ the driver that it shall not apply the mux setting. This can be used to
+ reserve some pins, for example to a co-processor not running Linux.
Some examples of using macro:
/* GPIO A9 set as alernate function 2 */
... {
@@ -156,6 +160,10 @@ patternProperties:
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
+ /* GPIO A9 reserved for co-processor */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, RSVD)>;
+ };
bias-disable:
type: boolean
diff --git a/Documentation/devicetree/bindings/regulator/protection-consumer.txt b/Documentation/devicetree/bindings/regulator/protection-consumer.txt
new file mode 100644
index 000000000000..bf8169e008c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/protection-consumer.txt
@@ -0,0 +1,23 @@
+regulator protection bindings
+
+
+Required properties:
+ compatible: "protection-consumer"
+ protection-supply: the phandle of the regulator to control
+
+Optional properties:
+--------------------
+ interrupt
+
+
+Example:
+
+ regulator_protection {
+ compatible = "protection-consumer";
+ protection-supply = <&vdd>;
+ status = "okay";
+
+ interrupts = <15 2>;
+ interrupt-parent = <&gpiof>;
+ };
+
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index 3cd4a254e4cb..fe9c5e83c459 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -19,7 +19,9 @@ allOf:
properties:
compatible:
- const: st,stm32-vrefbuf
+ enum:
+ - st,stm32-vrefbuf
+ - st,stm32mp13-vrefbuf
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 983c4e54c0be..a21246712f3f 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,14 @@ properties:
- const: tx
- const: rx
+ st,dual-flash:
+ type: boolean
+ description:
+ Allows to use 8 data lines in case cs-gpios property is defined.
+
+dependencies:
+ st,dual-flash: [ cs-gpios ]
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 2d9af4c506bb..8962b2b4de9d 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -27,8 +27,13 @@ allOf:
then:
properties:
st,spi-midi-ns: false
+ spi-slave: false
+ st,spi-slave-underrun: false
properties:
+ "#address-cells": true
+ "#size-cells": true
+
compatible:
enum:
- st,stm32f4-spi
@@ -59,6 +64,24 @@ properties:
- const: rx
- const: tx
+ spi-slave:
+ description:
+ The SPI controller acts as a slave, instead of a master.
+
+ cs-gpios:
+ description:
+ In case of spi-slave not defined, cs-gpios behave as defined in
+ spi-controller.yaml.
+ In case of spi-slave defined, if <0>, indicate that SS should be
+ detected via the dedicated HW pin
+
+ st,spi-slave-underrun:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ First parameter enables and selects slave underrun reaction.
+ Refer to "dt-bindings/spi/spi-stm32.h" for the supported values.
+ Second parameter is the pattern in case of SPI_SEND_PATTERN mode.
+
patternProperties:
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
type: object
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index abb12a5c3c32..b852894d7da9 100644
index d3fa8cf0d72c..98acad49b960 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -43,6 +43,7 @@
@ -544,7 +684,7 @@ index abb12a5c3c32..b852894d7da9 100644
}
static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
@@ -1427,7 +1516,8 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
@@ -1426,7 +1515,8 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
if (pctl->pkg && !(pctl->pkg & p->pkg))
continue;
pins->pin = p->pin;
@ -554,7 +694,7 @@ index abb12a5c3c32..b852894d7da9 100644
pins++;
nb_pins_available++;
}
@@ -1437,17 +1527,6 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
@@ -1436,17 +1526,6 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
return 0;
}
@ -572,7 +712,7 @@ index abb12a5c3c32..b852894d7da9 100644
int stm32_pctl_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -1497,8 +1576,9 @@ int stm32_pctl_probe(struct platform_device *pdev)
@@ -1496,8 +1575,9 @@ int stm32_pctl_probe(struct platform_device *pdev)
pctl->dev = dev;
pctl->match_data = match->data;
@ -584,7 +724,7 @@ index abb12a5c3c32..b852894d7da9 100644
pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
sizeof(*pctl->pins), GFP_KERNEL);
@@ -1590,6 +1670,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
@@ -1589,6 +1669,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
ret = stm32_gpiolib_register_bank(pctl, child);
if (ret) {
of_node_put(child);
@ -595,7 +735,7 @@ index abb12a5c3c32..b852894d7da9 100644
return ret;
}
@@ -1616,6 +1700,9 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
@@ -1615,6 +1699,9 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
if (!range)
return 0;
@ -605,7 +745,7 @@ index abb12a5c3c32..b852894d7da9 100644
pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
if (!desc || (!pin_is_irq && !desc->gpio_owner))
@@ -1662,12 +1749,26 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
@@ -1661,12 +1748,26 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
return 0;
}
@ -1077,7 +1217,7 @@ index 41ae7ac27ff6..fd884082c578 100644
sreg->rdev = devm_regulator_register(&sdev->dev, &sreg->desc,
diff --git a/drivers/regulator/stm32-pwr.c b/drivers/regulator/stm32-pwr.c
index e5dd4db6403b..87f160d2b461 100644
index 2a42acb7c24e..2b328b970b46 100644
--- a/drivers/regulator/stm32-pwr.c
+++ b/drivers/regulator/stm32-pwr.c
@@ -3,12 +3,15 @@
@ -1215,8 +1355,8 @@ index e5dd4db6403b..87f160d2b461 100644
+
static int stm32_pwr_regulator_probe(struct platform_device *pdev)
{
struct stm32_pwr_reg *priv;
@@ -134,6 +199,11 @@ static int stm32_pwr_regulator_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
@@ -135,6 +200,11 @@ static int stm32_pwr_regulator_probe(struct platform_device *pdev)
struct regulator_dev *rdev;
struct regulator_config config = { };
int i, ret = 0;
@ -1226,9 +1366,9 @@ index e5dd4db6403b..87f160d2b461 100644
+ if (ret)
+ return ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
@@ -148,6 +218,7 @@ static int stm32_pwr_regulator_probe(struct platform_device *pdev)
base = of_iomap(np, 0);
if (!base) {
@@ -149,6 +219,7 @@ static int stm32_pwr_regulator_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!priv)
return -ENOMEM;
@ -1363,7 +1503,7 @@ index 161622ea7259..d7eb7607b1b2 100644
};
MODULE_DEVICE_TABLE(of, stm32_vrefbuf_of_match);
diff --git a/drivers/regulator/stpmic1_regulator.c b/drivers/regulator/stpmic1_regulator.c
index 2d7597c76e4a..6ff66e874951 100644
index 2d7597c76e4a..c2cddba6dcda 100644
--- a/drivers/regulator/stpmic1_regulator.c
+++ b/drivers/regulator/stpmic1_regulator.c
@@ -2,7 +2,9 @@
@ -1527,7 +1667,7 @@ index 2d7597c76e4a..6ff66e874951 100644
}
}
@@ -598,15 +690,62 @@ static int stpmic1_regulator_register(struct platform_device *pdev, int id,
@@ -598,15 +690,60 @@ static int stpmic1_regulator_register(struct platform_device *pdev, int id,
pdev->name, rdev);
if (ret) {
dev_err(&pdev->dev, "Request IRQ failed\n");
@ -1565,8 +1705,6 @@ index 2d7597c76e4a..6ff66e874951 100644
+ return rdev;
+ }
+
+ usb_data->boost_rdev = rdev;
+
+ /* setup an irq handler for over-current detection */
+ irq = of_irq_get(config.of_node, 0);
+ if (irq > 0) {
@ -1592,7 +1730,7 @@ index 2d7597c76e4a..6ff66e874951 100644
ret = of_regulator_match(&pdev->dev, pdev->dev.of_node, stpmic1_matches,
ARRAY_SIZE(stpmic1_matches));
@@ -616,11 +755,28 @@ static int stpmic1_regulator_probe(struct platform_device *pdev)
@@ -616,11 +753,30 @@ static int stpmic1_regulator_probe(struct platform_device *pdev)
return ret;
}
@ -1610,6 +1748,8 @@ index 2d7597c76e4a..6ff66e874951 100644
+ stpmic1_boost_register(pdev, i, &stpmic1_matches[i],
+ &stpmic1_regulator_cfgs[i],
+ usb_data);
+
+ usb_data->boost_rdev = rdev;
+ } else {
+ rdev =
+ stpmic1_regulator_register(pdev, i, &stpmic1_matches[i],
@ -1626,10 +1766,10 @@ index 2d7597c76e4a..6ff66e874951 100644
dev_dbg(&pdev->dev, "stpmic1_regulator driver probed\n");
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4fc23236d3bd..29d363e14b5f 100644
index 83e352b0c8f9..a9342e57843f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -806,6 +806,7 @@ config SPI_SPRD_ADI
@@ -807,6 +807,7 @@ config SPI_SPRD_ADI
config SPI_STM32
tristate "STMicroelectronics STM32 SPI controller"
depends on ARCH_STM32 || COMPILE_TEST
@ -1947,7 +2087,7 @@ index dd38cb8ffbc2..00e84f3cb239 100644
ctrl->dev.of_node = dev->of_node;
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 3c6f201b5dd8..f9ebc01194ce 100644
index 9bd3fd1652f7..573f51e630d3 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1,6 +1,6 @@
@ -2075,15 +2215,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
* @cfg: compatible configuration data
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
@@ -268,6 +290,7 @@ struct stm32_spi_cfg {
* @fifo_size: size of the embedded fifo in bytes
* @cur_midi: master inter-data idleness in ns
* @cur_speed: speed configured in Hz
+ * @cur_half_period: time of a half bit in us
* @cur_bpw: number of bits in a single SPI data frame
* @cur_fthlv: fifo threshold level (data frames in a single data packet)
* @cur_comm: SPI communication mode
@@ -280,10 +303,13 @@ struct stm32_spi_cfg {
@@ -280,10 +302,13 @@ struct stm32_spi_cfg {
* @dma_tx: dma channel for TX transfer
* @dma_rx: dma channel for RX transfer
* @phys_addr: SPI registers physical base address
@ -2098,15 +2230,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
const struct stm32_spi_cfg *cfg;
void __iomem *base;
struct clk *clk;
@@ -294,6 +320,7 @@ struct stm32_spi {
unsigned int cur_midi;
unsigned int cur_speed;
+ unsigned int cur_half_period;
unsigned int cur_bpw;
unsigned int cur_fthlv;
unsigned int cur_comm;
@@ -307,6 +334,10 @@ struct stm32_spi {
@@ -307,6 +332,10 @@ struct stm32_spi {
struct dma_chan *dma_tx;
struct dma_chan *dma_rx;
dma_addr_t phys_addr;
@ -2117,7 +2241,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
};
static const struct stm32_spi_regspec stm32f4_spi_regspec = {
@@ -318,6 +349,7 @@ static const struct stm32_spi_regspec stm32f4_spi_regspec = {
@@ -318,6 +347,7 @@ static const struct stm32_spi_regspec stm32f4_spi_regspec = {
.cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
.cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
.lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
@ -2125,7 +2249,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
.br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
.rx = { STM32F4_SPI_DR },
@@ -336,6 +368,7 @@ static const struct stm32_spi_regspec stm32h7_spi_regspec = {
@@ -336,6 +366,7 @@ static const struct stm32_spi_regspec stm32h7_spi_regspec = {
.cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
.cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
.lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
@ -2133,8 +2257,8 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
.br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
STM32H7_SPI_CFG1_MBR_SHIFT },
@@ -437,9 +470,9 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
@@ -437,9 +468,9 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
/*
- * SPI framework set xfer->speed_hz to master->max_speed_hz if
@ -2146,16 +2270,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
* no need to check it there.
* However, we need to ensure the following calculations.
*/
@@ -454,6 +487,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
+ spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
+
return mbrdiv - 1;
}
@@ -657,9 +692,9 @@ static void stm32f4_spi_disable(struct stm32_spi *spi)
@@ -657,9 +688,9 @@ static void stm32f4_spi_disable(struct stm32_spi *spi)
}
if (spi->cur_usedma && spi->dma_tx)
@ -2167,14 +2282,9 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
@@ -695,10 +730,14 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
return;
@@ -696,9 +727,9 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
}
+ /* Add a delay to make sure that transmission is ended. */
+ if (spi->cur_half_period)
+ udelay(spi->cur_half_period);
+
if (spi->cur_usedma && spi->dma_tx)
- dmaengine_terminate_all(spi->dma_tx);
+ dmaengine_terminate_async(spi->dma_tx);
@ -2184,7 +2294,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
@@ -714,19 +753,19 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
@@ -714,19 +745,19 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
/**
* stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
@ -2207,7 +2317,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
if (spi->cfg->has_fifo)
dma_size = spi->fifo_size;
@@ -742,12 +781,12 @@ static bool stm32_spi_can_dma(struct spi_master *master,
@@ -742,12 +773,12 @@ static bool stm32_spi_can_dma(struct spi_master *master,
/**
* stm32f4_spi_irq_event - Interrupt handler for SPI controller events
* @irq: interrupt line
@ -2223,7 +2333,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
u32 sr, mask = 0;
bool end = false;
@@ -830,14 +869,14 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
@@ -830,14 +861,14 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
/**
* stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
* @irq: interrupt line
@ -2242,7 +2352,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
stm32f4_spi_disable(spi);
return IRQ_HANDLED;
@@ -846,12 +885,12 @@ static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
@@ -846,12 +877,12 @@ static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
/**
* stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
* @irq: interrupt line
@ -2258,7 +2368,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
u32 sr, ier, mask;
unsigned long flags;
bool end = false;
@@ -909,6 +948,14 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
@@ -908,6 +939,14 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
end = true;
}
@ -2273,7 +2383,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
if (sr & STM32H7_SPI_SR_EOT) {
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
stm32h7_spi_read_rxfifo(spi);
@@ -931,7 +978,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
@@ -930,7 +969,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
if (end) {
stm32h7_spi_disable(spi);
@ -2282,7 +2392,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
}
return IRQ_HANDLED;
@@ -939,13 +986,13 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
@@ -938,13 +977,13 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
/**
* stm32_spi_prepare_msg - set up the controller to transfer a single message
@ -2299,7 +2409,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
struct spi_device *spi_dev = msg->spi;
struct device_node *np = spi_dev->dev.of_node;
unsigned long flags;
@@ -971,6 +1018,11 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
@@ -970,6 +1009,11 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
else
clrb |= spi->cfg->regs->lsb_first.mask;
@ -2311,7 +2421,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
!!(spi_dev->mode & SPI_CPOL),
!!(spi_dev->mode & SPI_CPHA),
@@ -984,7 +1036,7 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
@@ -983,7 +1027,7 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
if (spi->cfg->set_number_of_data) {
int ret;
@ -2320,7 +2430,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
STM32H7_SPI_TSIZE_MAX,
GFP_KERNEL | GFP_DMA);
if (ret)
@@ -1016,7 +1068,7 @@ static void stm32f4_spi_dma_tx_cb(void *data)
@@ -1015,7 +1059,7 @@ static void stm32f4_spi_dma_tx_cb(void *data)
struct stm32_spi *spi = data;
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
@ -2329,7 +2439,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
stm32f4_spi_disable(spi);
}
}
@@ -1031,7 +1083,7 @@ static void stm32_spi_dma_rx_cb(void *data)
@@ -1030,7 +1074,7 @@ static void stm32_spi_dma_rx_cb(void *data)
{
struct stm32_spi *spi = data;
@ -2338,7 +2448,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->cfg->disable(spi);
}
@@ -1161,7 +1213,11 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
@@ -1160,7 +1204,11 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
if (spi->tx_buf)
stm32h7_spi_write_txfifo(spi);
@ -2351,7 +2461,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
@@ -1204,11 +1260,15 @@ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
@@ -1203,11 +1251,15 @@ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
@ -2368,7 +2478,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
}
/**
@@ -1302,7 +1362,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
@@ -1301,7 +1353,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
dma_submit_error:
if (spi->dma_rx)
@ -2377,7 +2487,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
dma_desc_error:
stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
@@ -1511,6 +1571,53 @@ static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
@@ -1510,6 +1562,53 @@ static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
return 0;
}
@ -2431,7 +2541,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
/**
* stm32_spi_transfer_one_setup - common setup to transfer a single
* spi_transfer either using DMA or
@@ -1536,16 +1643,18 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
@@ -1535,16 +1634,18 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
spi->cfg->set_bpw(spi);
/* Update spi->cur_speed with real clock speed */
@ -2459,7 +2569,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
comm_type = stm32_spi_communication_type(spi_dev, transfer);
ret = spi->cfg->set_mode(spi, comm_type);
@@ -1554,7 +1663,7 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
@@ -1553,7 +1654,7 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
spi->cur_comm = comm_type;
@ -2468,7 +2578,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->cfg->set_data_idleness(spi, transfer->len);
if (spi->cur_bpw <= 8)
@@ -1570,12 +1679,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
@@ -1569,12 +1670,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
goto out;
}
@ -2486,7 +2596,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
spi->cur_xferlen, nb_words);
dev_dbg(spi->dev, "dma %s\n",
@@ -1589,18 +1702,18 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
@@ -1588,18 +1693,18 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
/**
* stm32_spi_transfer_one - transfer a single spi_transfer
@ -2508,7 +2618,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
int ret;
spi->tx_buf = transfer->tx_buf;
@@ -1608,8 +1721,8 @@ static int stm32_spi_transfer_one(struct spi_master *master,
@@ -1607,8 +1712,8 @@ static int stm32_spi_transfer_one(struct spi_master *master,
spi->tx_len = spi->tx_buf ? transfer->len : 0;
spi->rx_len = spi->rx_buf ? transfer->len : 0;
@ -2519,7 +2629,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
if (ret) {
@@ -1625,13 +1738,13 @@ static int stm32_spi_transfer_one(struct spi_master *master,
@@ -1624,13 +1729,13 @@ static int stm32_spi_transfer_one(struct spi_master *master,
/**
* stm32_spi_unprepare_msg - relax the hardware
@ -2536,7 +2646,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->cfg->disable(spi);
@@ -1670,12 +1783,13 @@ static int stm32f4_spi_config(struct stm32_spi *spi)
@@ -1669,12 +1774,13 @@ static int stm32f4_spi_config(struct stm32_spi *spi)
}
/**
@ -2551,7 +2661,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spin_lock_irqsave(&spi->lock, flags);
@@ -1683,24 +1797,28 @@ static int stm32h7_spi_config(struct stm32_spi *spi)
@@ -1682,24 +1788,28 @@ static int stm32h7_spi_config(struct stm32_spi *spi)
stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
STM32H7_SPI_I2SCFGR_I2SMOD);
@ -2597,7 +2707,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spin_unlock_irqrestore(&spi->lock, flags);
@@ -1723,6 +1841,7 @@ static const struct stm32_spi_cfg stm32f4_spi_cfg = {
@@ -1722,6 +1832,7 @@ static const struct stm32_spi_cfg stm32f4_spi_cfg = {
.baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
.baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
.has_fifo = false,
@ -2605,7 +2715,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
};
static const struct stm32_spi_cfg stm32h7_spi_cfg = {
@@ -1746,6 +1865,7 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = {
@@ -1745,6 +1856,7 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = {
.baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
.baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
.has_fifo = true,
@ -2613,7 +2723,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
};
static const struct of_device_id stm32_spi_of_match[] = {
@@ -1755,24 +1875,64 @@ static const struct of_device_id stm32_spi_of_match[] = {
@@ -1754,24 +1866,64 @@ static const struct of_device_id stm32_spi_of_match[] = {
};
MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
@ -2685,7 +2795,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spin_lock_init(&spi->lock);
spi->cfg = (const struct stm32_spi_cfg *)
@@ -1794,13 +1954,16 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1793,13 +1945,16 @@ static int stm32_spi_probe(struct platform_device *pdev)
ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
spi->cfg->irq_handler_event,
spi->cfg->irq_handler_thread,
@ -2703,7 +2813,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(spi->clk)) {
ret = PTR_ERR(spi->clk);
@@ -1843,19 +2006,21 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1842,19 +1997,21 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
@ -2738,7 +2848,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->dma_tx = dma_request_chan(spi->dev, "tx");
if (IS_ERR(spi->dma_tx)) {
@@ -1866,7 +2031,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1865,7 +2022,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, "failed to request tx dma channel\n");
} else {
@ -2747,7 +2857,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
}
spi->dma_rx = dma_request_chan(spi->dev, "rx");
@@ -1878,11 +2043,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1877,11 +2034,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, "failed to request rx dma channel\n");
} else {
@ -2761,7 +2871,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
pm_runtime_set_autosuspend_delay(&pdev->dev,
STM32_SPI_AUTOSUSPEND_DELAY);
@@ -1891,9 +2056,9 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1890,9 +2047,9 @@ static int stm32_spi_probe(struct platform_device *pdev)
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_enable(&pdev->dev);
@ -2773,7 +2883,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
ret);
goto err_pm_disable;
}
@@ -1901,7 +2066,8 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1900,7 +2057,8 @@ static int stm32_spi_probe(struct platform_device *pdev)
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
@ -2783,7 +2893,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
return 0;
@@ -1923,12 +2089,12 @@ static int stm32_spi_probe(struct platform_device *pdev)
@@ -1922,12 +2080,12 @@ static int stm32_spi_probe(struct platform_device *pdev)
static int stm32_spi_remove(struct platform_device *pdev)
{
@ -2799,7 +2909,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
spi->cfg->disable(spi);
pm_runtime_disable(&pdev->dev);
@@ -1936,10 +2102,10 @@ static int stm32_spi_remove(struct platform_device *pdev)
@@ -1935,10 +2093,10 @@ static int stm32_spi_remove(struct platform_device *pdev)
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
@ -2814,7 +2924,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
clk_disable_unprepare(spi->clk);
@@ -1951,8 +2117,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
@@ -1950,8 +2108,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
{
@ -2825,7 +2935,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
clk_disable_unprepare(spi->clk);
@@ -1961,8 +2127,8 @@ static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
@@ -1960,8 +2118,8 @@ static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
{
@ -2836,7 +2946,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
int ret;
ret = pinctrl_pm_select_default_state(dev);
@@ -1974,10 +2140,10 @@ static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
@@ -1973,10 +2131,10 @@ static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
static int __maybe_unused stm32_spi_suspend(struct device *dev)
{
@ -2849,7 +2959,7 @@ index 3c6f201b5dd8..f9ebc01194ce 100644
if (ret)
return ret;
@@ -1986,15 +2152,15 @@ static int __maybe_unused stm32_spi_suspend(struct device *dev)
@@ -1985,15 +2143,15 @@ static int __maybe_unused stm32_spi_suspend(struct device *dev)
static int __maybe_unused stm32_spi_resume(struct device *dev)
{
@ -2901,18 +3011,6 @@ index 000000000000..7c818a399a0c
+#define SPI_REPEAT_LAST_TRANSMITTED_DATA 3
+
+#endif
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index 8bf2ea859653..a5166eb93437 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -29,6 +29,7 @@ enum of_gpio_flags {
OF_GPIO_TRANSITORY = 0x8,
OF_GPIO_PULL_UP = 0x10,
OF_GPIO_PULL_DOWN = 0x20,
+ OF_GPIO_PULL_DISABLE = 0x40,
};
#ifdef CONFIG_OF_GPIO
--
2.17.1

97
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0018-v5.15-stm32mp-r2.1-RESET-RTC.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0018-v5.15-stm32mp-r2-RESET-RTC.patch
View File

@ -1,19 +1,102 @@
From d046f916a037e6dcb46bdb7083a5b46132702090 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:56:49 +0200
Subject: [PATCH 18/22] v5.15-stm32mp-r2.1 RESET-RTC
From b0e70738cf7a9a1c9b4e10c3aec7cea6004ed9a4 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:04:20 +0100
Subject: [PATCH 18/22] v5.15-stm32mp-r2 RESET-RTC
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../devicetree/bindings/rtc/st,stm32-rtc.yaml | 37 ++
drivers/rtc/Kconfig | 1 +
drivers/rtc/rtc-stm32.c | 365 +++++++++++++++----
drivers/rtc/rtc-stm32.c | 365 ++++++++++++++----
include/dt-bindings/reset/stm32mp1-resets.h | 24 +-
include/dt-bindings/reset/stm32mp13-resets.h | 100 +++++
include/dt-bindings/rtc/rtc-stm32.h | 14 +
5 files changed, 422 insertions(+), 82 deletions(-)
6 files changed, 459 insertions(+), 82 deletions(-)
create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h
create mode 100644 include/dt-bindings/rtc/rtc-stm32.h
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
index 5456604b1c14..d94e1d13d908 100644
--- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
@@ -52,6 +52,20 @@ properties:
override default rtc_ck parent clock phandle of the new parent clock of rtc_ck
maxItems: 1
+ st,lsco:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ To select and enable RTC Low Speed Clock Output.
+ Refer to <include/dt-bindings/rtc/rtc-stm32.h> for the supported values.
+ Pinctrl state named "default" may be defined to reserve pin for RTC output.
+
+ st,alarm:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ To select and enable RTC Alarm A output.
+ Refer to <include/dt-bindings/rtc/rtc-stm32.h> for the supported values.
+ Pinctrl state named "default" may be defined to reserve pin for RTC output.
+
allOf:
- if:
properties:
@@ -65,6 +79,12 @@ allOf:
minItems: 1
maxItems: 1
+ st,lsco:
+ maxItems: 0
+
+ st,alarm:
+ maxItems: 0
+
clock-names: false
required:
@@ -82,6 +102,12 @@ allOf:
minItems: 2
maxItems: 2
+ st,lsco:
+ maxItems: 0
+
+ st,alarm:
+ maxItems: 0
+
required:
- clock-names
- st,syscfg
@@ -101,6 +127,12 @@ allOf:
assigned-clocks: false
assigned-clock-parents: false
+ st,lsco:
+ maxItems: 1
+
+ st,alarm:
+ maxItems: 1
+
required:
- clock-names
@@ -129,12 +161,17 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/rtc/rtc-stm32.h>
rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
clocks = <&rcc RTCAPB>, <&rcc RTC>;
clock-names = "pclk", "rtc_ck";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ st,alarm = <RTC_OUT1>;
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out1_pins_a &rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
};
...
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index e1bc5214494e..57ef1efdfc3c 100644
--- a/drivers/rtc/Kconfig

24
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0019-v5.15-stm32mp-r2.1-SCMI.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0019-v5.15-stm32mp-r2-SCMI.patch
View File

@ -1,9 +1,9 @@
From efeb9aad0de2f5453e9c27a8a4e0e18e6faa1938 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:57:24 +0200
Subject: [PATCH 19/22] v5.15-stm32mp-r2.1 SCMI
From ae4d172fd1f74a9adc7eed21b80dc3049a56a462 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:05:11 +0100
Subject: [PATCH 19/22] v5.15-stm32mp-r2 SCMI
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
drivers/firmware/arm_scmi/Makefile | 1 +
drivers/firmware/arm_scmi/clock.c | 78 +++
@ -27,7 +27,7 @@ index 1dcf123d64ab..d1460cf7e9de 100644
scmi-module-objs := $(scmi-bus-y) $(scmi-driver-y) $(scmi-protocols-y) \
$(scmi-transport-y)
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index e76194a60edf..86e84f8ff6f6 100644
index 492f3a9197ec..47814d175ce7 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -16,6 +16,8 @@ enum scmi_clock_protocol_cmd {
@ -134,7 +134,7 @@ index e76194a60edf..86e84f8ff6f6 100644
static int
scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id,
u32 config)
@@ -335,6 +411,8 @@ static const struct scmi_clk_proto_ops clk_proto_ops = {
@@ -331,6 +407,8 @@ static const struct scmi_clk_proto_ops clk_proto_ops = {
.rate_set = scmi_clock_rate_set,
.enable = scmi_clock_enable,
.disable = scmi_clock_disable,
@ -144,10 +144,10 @@ index e76194a60edf..86e84f8ff6f6 100644
static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h
index b9f5829c0c4d..14f70b4f7874 100644
index dea1bfbe1052..82ff3c3a6d2d 100644
--- a/drivers/firmware/arm_scmi/common.h
+++ b/drivers/firmware/arm_scmi/common.h
@@ -422,6 +422,9 @@ extern const struct scmi_desc scmi_smc_desc;
@@ -421,6 +421,9 @@ extern const struct scmi_desc scmi_smc_desc;
#ifdef CONFIG_ARM_SCMI_TRANSPORT_VIRTIO
extern const struct scmi_desc scmi_virtio_desc;
#endif
@ -158,10 +158,10 @@ index b9f5829c0c4d..14f70b4f7874 100644
void scmi_rx_callback(struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv);
void scmi_free_channel(struct scmi_chan_info *cinfo, struct idr *idr, int id);
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index 7ccda7d720a1..02db19079701 100644
index e815b8f98739..4a5b9c2c0c53 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -2011,6 +2011,9 @@ static const struct of_device_id scmi_of_match[] = {
@@ -1998,6 +1998,9 @@ static const struct of_device_id scmi_of_match[] = {
#ifdef CONFIG_ARM_SCMI_TRANSPORT_SMC
{ .compatible = "arm,scmi-smc", .data = &scmi_smc_desc},
#endif
@ -1026,7 +1026,7 @@ index 000000000000..4ec54b3c6628
+MODULE_AUTHOR("Etienne Carriere <etienne.carriere@linaro.org>");
+MODULE_DESCRIPTION("OP-TEE SCMI transport driver");
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index d22f62203ee3..74cee314fa91 100644
index 80e781c51ddc..f0b8bc4cf83a 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -82,6 +82,10 @@ struct scmi_clk_proto_ops {

49
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0020-v5.15-stm32mp-r2.1-SOUND.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0020-v5.15-stm32mp-r2-SOUND.patch
View File

@ -1,20 +1,20 @@
From 73957b4c529874c1c4ddcad2db33caff026973e1 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:57:46 +0200
Subject: [PATCH 20/22] v5.15-stm32mp-r2.1 SOUND
From bf84be1a6e25855048a341b6e8d86a660d6fac1a Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:05:34 +0100
Subject: [PATCH 20/22] v5.15-stm32mp-r2 SOUND
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
sound/soc/codecs/Kconfig | 2 +-
sound/soc/codecs/wm8994.c | 81 ++++++++++++++++++++++++++++++++---
sound/soc/stm/stm32_adfsdm.c | 11 +++--
sound/soc/stm/stm32_adfsdm.c | 22 ++++++++--
sound/soc/stm/stm32_i2s.c | 6 ++-
sound/soc/stm/stm32_sai_sub.c | 4 +-
sound/soc/stm/stm32_spdifrx.c | 4 ++
6 files changed, 95 insertions(+), 13 deletions(-)
6 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c3deb82c5da3..76981d82b005 100644
index d59a7e99ce42..31ed450b4069 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -1774,7 +1774,7 @@ config SND_SOC_WM8993
@ -27,7 +27,7 @@ index c3deb82c5da3..76981d82b005 100644
config SND_SOC_WM8995
tristate
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 6759db92f6c4..c037368acdd4 100644
index f117ec0c489f..98e803516fe5 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -7,6 +7,7 @@
@ -163,7 +163,7 @@ index 6759db92f6c4..c037368acdd4 100644
ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
if (ret < 0)
return ret;
@@ -4443,6 +4504,14 @@ static int wm8994_component_probe(struct snd_soc_component *component)
@@ -4438,6 +4499,14 @@ static int wm8994_component_probe(struct snd_soc_component *component)
ARRAY_SIZE(wm8994_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
ARRAY_SIZE(wm8994_specific_dapm_widgets));
@ -179,7 +179,7 @@ index 6759db92f6c4..c037368acdd4 100644
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
ARRAY_SIZE(wm8994_lateclk_revd_widgets));
diff --git a/sound/soc/stm/stm32_adfsdm.c b/sound/soc/stm/stm32_adfsdm.c
index 1e9b4b1df69e..75e75cc7fa02 100644
index e6078f50e508..75e75cc7fa02 100644
--- a/sound/soc/stm/stm32_adfsdm.c
+++ b/sound/soc/stm/stm32_adfsdm.c
@@ -12,7 +12,7 @@
@ -191,7 +191,32 @@ index 1e9b4b1df69e..75e75cc7fa02 100644
#include <linux/iio/iio.h>
#include <linux/iio/consumer.h>
#include <linux/iio/adc/stm32-dfsdm-adc.h>
@@ -374,15 +374,20 @@ static int stm32_adfsdm_probe(struct platform_device *pdev)
@@ -303,6 +303,11 @@ static int stm32_adfsdm_dummy_cb(const void *data, void *private)
return 0;
}
+static void stm32_adfsdm_cleanup(void *data)
+{
+ iio_channel_release_all_cb(data);
+}
+
static struct snd_soc_component_driver stm32_adfsdm_soc_platform = {
.open = stm32_adfsdm_pcm_open,
.close = stm32_adfsdm_pcm_close,
@@ -349,6 +354,12 @@ static int stm32_adfsdm_probe(struct platform_device *pdev)
if (IS_ERR(priv->iio_cb))
return PTR_ERR(priv->iio_cb);
+ ret = devm_add_action_or_reset(&pdev->dev, stm32_adfsdm_cleanup, priv->iio_cb);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Unable to add action\n");
+ return ret;
+ }
+
component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL);
if (!component)
return -ENOMEM;
@@ -363,15 +374,20 @@ static int stm32_adfsdm_probe(struct platform_device *pdev)
#endif
ret = snd_soc_add_component(component, NULL, 0);

1858
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0021-v5.15-stm32mp-r2.1-DEVICETREE.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0021-v5.15-stm32mp-r2-DEVICETREE.patch
View File

File diff suppressed because it is too large Load Diff

24
recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0022-v5.15-stm32mp-r2.1-CONFIG.patch → recipes-kernel/linux/linux-stm32mp/5.15/5.15.67/0022-v5.15-stm32mp-r2-CONFIG.patch
View File

@ -1,23 +1,23 @@
From 5b3e499d2722661e1d1290a86939f3f4cd93541e Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:58:05 +0200
Subject: [PATCH 22/22] v5.15-stm32mp-r2.1 CONFIG
From ff0775651b034096b3f72ed6ec90efc39eb8627c Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:51:45 +0100
Subject: [PATCH 22/22] v5.15-stm32mp-r2 CONFIG
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
---
.../fragment-01-multiv7_cleanup.config | 412 +++++++++++++++++
.../fragment-01-multiv7_cleanup.config | 408 +++++++++++++++++
.../configs/fragment-02-multiv7_addons.config | 426 ++++++++++++++++++
arch/arm/configs/multi_v7_defconfig | 1 +
3 files changed, 839 insertions(+)
3 files changed, 835 insertions(+)
create mode 100644 arch/arm/configs/fragment-01-multiv7_cleanup.config
create mode 100644 arch/arm/configs/fragment-02-multiv7_addons.config
diff --git a/arch/arm/configs/fragment-01-multiv7_cleanup.config b/arch/arm/configs/fragment-01-multiv7_cleanup.config
new file mode 100644
index 000000000000..23eb90e36f33
index 000000000000..52f28a765b25
--- /dev/null
+++ b/arch/arm/configs/fragment-01-multiv7_cleanup.config
@@ -0,0 +1,412 @@
@@ -0,0 +1,408 @@
+#
+# CPU Core family selection
+#
@ -426,10 +426,6 @@ index 000000000000..23eb90e36f33
+
+# Remove Console display driver support
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+
+# Remove RNDIS support
+# CONFIG_USB_CONFIGFS_RNDIS is not set
+# CONFIG_USB_ETH_RNDIS is not set
diff --git a/arch/arm/configs/fragment-02-multiv7_addons.config b/arch/arm/configs/fragment-02-multiv7_addons.config
new file mode 100644
index 000000000000..7b5ffd562d8a
@ -863,7 +859,7 @@ index 000000000000..7b5ffd562d8a
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_OFB=m
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2eafcf1c5d89..ea6a2dc838fe 100644
index 33572998dbbe..afb97c5051c9 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -646,6 +646,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y

8
recipes-kernel/linux/linux-stm32mp/README.HOW_TO.txt
View File

@ -149,10 +149,10 @@ We highly preconized the build is a build directory method as:
$ scripts/kconfig/merge_config.sh -m -r -O $PWD/../build $PWD/../build/.config ../fragment-01-xxx.config
$ scripts/kconfig/merge_config.sh -m -r -O $PWD/../build $PWD/../build/.config ../fragment-02-xxx.config
...
$ (yes '' || true) | make ARCH=arm oldconfig O="$PWD/../build"
$ yes '' | make ARCH=arm oldconfig O="$PWD/../build"
* or, by loop:
$> for f in `ls -1 ../fragment*.config`; do scripts/kconfig/merge_config.sh -m -r -O $PWD/../build $PWD/../build/.config $f; done
$> (yes '' || true) | make ARCH=arm oldconfig O="$PWD/../build"
$> yes '' | make ARCH=arm oldconfig O="$PWD/../build"
* Configure on the current source code directory
$ cd <directory to kernel source code>
@ -163,10 +163,10 @@ We highly preconized the build is a build directory method as:
$ scripts/kconfig/merge_config.sh -m -r .config ../fragment-01-xxxx.config
$ scripts/kconfig/merge_config.sh -m -r .config ../fragment-02-xxxx.config
...
$ (yes '' || true) | make oldconfig
$ yes '' | make oldconfig
* or, by loop:
$ for f in `ls -1 ../fragment*.config`; do scripts/kconfig/merge_config.sh -m -r .config $f; done
$ (yes '' || true) | make ARCH=arm oldconfig
$ yes '' | make ARCH=arm oldconfig
NB: Two types of fragments are provided:
* official fragments (fragment-xxx.config)

52
recipes-kernel/linux/linux-stm32mp_5.15.bb
View File

@ -7,41 +7,41 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
include linux-stm32mp.inc
LINUX_VERSION = "5.15"
LINUX_SUBVERSION = "118"
LINUX_SUBVERSION = "67"
LINUX_TARNAME = "linux-${LINUX_VERSION}.${LINUX_SUBVERSION}"
SRC_URI = "https://cdn.kernel.org/pub/linux/kernel/v5.x/${LINUX_TARNAME}.tar.xz;name=kernel"
#SRC_URI = "https://git.kernel.org/torvalds/t/linux-${LINUX_VERSION}-${LINUX_SUBVERSION}.tar.gz;name=kernel"
SRC_URI[kernel.sha256sum] = "4e6bf4dadb04d5d11d1d4cc37c0eabcf33bc333b7dd3dc2143c3099a823eb5b3"
SRC_URI[kernel.sha256sum] = "da47d9a80b694548835ccb553b6eb1a1f3f5d5cddd9e2bd6f4886b99ca14f940"
SRC_URI += " \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0001-v5.15-stm32mp-r2.1-MACHINE.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0002-v5.15-stm32mp-r2.1-CLOCK.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0003-v5.15-stm32mp-r2.1-CPUFREQ.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0004-v5.15-stm32mp-r2.1-CPUIDLE-POWER.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0005-v5.15-stm32mp-r2.1-CRYPTO.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0006-v5.15-stm32mp-r2.1-DMA.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0007-v5.15-stm32mp-r2.1-DRM.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0008-v5.15-stm32mp-r2.1-HWSPINLOCK.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0009-v5.15-stm32mp-r2.1-I2C-IIO-IRQCHIP.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0010-v5.15-stm32mp-r2.1-REMOTEPROC-RPMSG.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0011-v5.15-stm32mp-r2.1-MISC-MEDIA-SOC-THERMAL.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0012-v5.15-stm32mp-r2.1-MFD.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0013-v5.15-stm32mp-r2.1-MMC.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0014-v5.15-stm32mp-r2.1-NET-TTY.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0015-v5.15-stm32mp-r2.1-PERF.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0016-v5.15-stm32mp-r2.1-PHY-USB.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0017-v5.15-stm32mp-r2.1-PINCTRL-REGULATOR-SPI.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0018-v5.15-stm32mp-r2.1-RESET-RTC.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0019-v5.15-stm32mp-r2.1-SCMI.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0020-v5.15-stm32mp-r2.1-SOUND.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0021-v5.15-stm32mp-r2.1-DEVICETREE.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0022-v5.15-stm32mp-r2.1-CONFIG.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0001-v5.15-stm32mp-r2-MACHINE.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0002-v5.15-stm32mp-r2-CLOCK.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0003-v5.15-stm32mp-r2-CPUFREQ.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0004-v5.15-stm32mp-r2-CPUIDLE-POWER.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0005-v5.15-stm32mp-r2-CRYPTO.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0006-v5.15-stm32mp-r2-DMA.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0007-v5.15-stm32mp-r2-DRM.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0008-v5.15-stm32mp-r2-HWSPINLOCK.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0009-v5.15-stm32mp-r2-I2C-IIO-IRQCHIP.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0010-v5.15-stm32mp-r2-REMOTEPROC-RPMSG.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0011-v5.15-stm32mp-r2-MISC-MEDIA-SOC-THERMAL.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0012-v5.15-stm32mp-r2-MFD.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0013-v5.15-stm32mp-r2-MMC.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0014-v5.15-stm32mp-r2-NET-TTY.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0015-v5.15-stm32mp-r2-PERF.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0016-v5.15-stm32mp-r2-PHY-USB.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0017-v5.15-stm32mp-r2-PINCTRL-REGULATOR-SPI.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0018-v5.15-stm32mp-r2-RESET-RTC.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0019-v5.15-stm32mp-r2-SCMI.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0020-v5.15-stm32mp-r2-SOUND.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0021-v5.15-stm32mp-r2-DEVICETREE.patch \
file://${LINUX_VERSION}/${LINUX_VERSION}.${LINUX_SUBVERSION}/0022-v5.15-stm32mp-r2-CONFIG.patch \
"
LINUX_TARGET = "stm32mp"
LINUX_RELEASE = "r2.1"
LINUX_RELEASE = "r2"
PV = "${LINUX_VERSION}.${LINUX_SUBVERSION}-${LINUX_TARGET}-${LINUX_RELEASE}"
@ -59,7 +59,7 @@ S = "${WORKDIR}/linux-${LINUX_VERSION}.${LINUX_SUBVERSION}"
BBCLASSEXTEND = "devupstream:target"
SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/linux.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
SRCREV:class-devupstream = "61ca40c154195a5b3b288db386086f0bf9c5273f"
SRCREV:class-devupstream = "661e4b11da679e4e1f4de088279282f6fbbe528b"
# ---------------------------------
# Configure default preference to manage dynamic selection between tarball and github

5
recipes-security/optee/optee-os-stm32mp_3.16.0.bb
View File

@ -9,14 +9,13 @@ SRC_URI += " \
file://fonts.tar.gz;subdir=git;name=fonts \
file://0001-3.16.0-stm32mp-r1.patch \
file://0002-3.16.0-stm32mp-r2.patch \
file://0003-3.16.0-stm32mp-r2.1.patch \
"
SRC_URI[fonts.sha256sum] = "4941e8bb6d8ac377838e27b214bf43008c496a24a8f897e0b06433988cbd53b2"
OPTEE_VERSION = "3.16.0"
OPTEE_SUBVERSION = "stm32mp"
OPTEE_RELEASE = "r2.1"
OPTEE_RELEASE = "r2"
PV = "${OPTEE_VERSION}-${OPTEE_SUBVERSION}-${OPTEE_RELEASE}"
@ -51,7 +50,7 @@ include ${@oe.utils.ifelse(d.getVar('ST_ARCHIVER_ENABLE') == '1', 'optee-os-stm3
BBCLASSEXTEND = "devupstream:target"
SRC_URI:class-devupstream = "git://github.com/STMicroelectronics/optee_os.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
SRCREV:class-devupstream = "b8750c4600166f0019a8c1cf35362b1889840ec3"
SRCREV:class-devupstream = "0f631da995da50fe7e19e0b7291032d77f7048bc"
# ---------------------------------
# Configure default preference to manage dynamic selection between tarball and github

848
recipes-security/optee/optee-os/0003-3.16.0-stm32mp-r2.1.patch
View File

@ -1,848 +0,0 @@
From 40bea7e6dd305b8fec278fa56bc38eed127ce946 Mon Sep 17 00:00:00 2001
From: Lionel VITTE <lionel.vitte@st.com>
Date: Mon, 3 Jul 2023 10:30:06 +0200
Subject: [PATCH] 3.16.0-stm32mp-r2.1-rc1
---
core/arch/arm/dts/stm32mp135f-dk.dts | 4 +-
core/arch/arm/plat-stm32mp1/conf.mk | 4 +-
.../arm/plat-stm32mp1/drivers/stm32mp1_pmic.c | 151 +++++++++++++-----
.../plat-stm32mp1/drivers/stm32mp1_pwr_irq.c | 78 ++++++---
core/arch/arm/plat-stm32mp1/main.c | 4 +-
core/arch/arm/plat-stm32mp1/pm/context.c | 12 +-
core/arch/arm/plat-stm32mp1/pm/low_power.c | 15 +-
core/drivers/crypto/stm32/stm32_saes.c | 7 +
core/drivers/regulator/core.c | 5 +
core/drivers/stm32_iwdg.c | 18 ++-
core/drivers/stm32_rng.c | 12 +-
core/drivers/stm32_uart.c | 4 +-
core/include/drivers/stpmic1.h | 35 ----
core/include/kernel/huk_subkey.h | 5 +
core/kernel/huk_subkey.c | 16 +-
.../devicetree/bindings/mfd/st,stpmic1.yaml | 51 ++++++
16 files changed, 293 insertions(+), 128 deletions(-)
diff --git a/core/arch/arm/dts/stm32mp135f-dk.dts b/core/arch/arm/dts/stm32mp135f-dk.dts
index 4400b2b13..710446101 100644
--- a/core/arch/arm/dts/stm32mp135f-dk.dts
+++ b/core/arch/arm/dts/stm32mp135f-dk.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/stm32mp13-clksrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/stm32mp_gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
#include <dt-bindings/power/stm32mp1-power.h>
#include <dt-bindings/rtc/rtc-stm32.h>
#include <dt-bindings/soc/stm32mp-tzc400-macro.h>
@@ -192,7 +193,8 @@
reg = <0x33>;
status = "okay";
st,wakeup-pin-number = <1>;
- st,notif-it-id = <0>;
+ st,pmic-it-id = <IT_PONKEY_F IT_PONKEY_R>;
+ st,notif-it-id = <0 2>;
regulators {
compatible = "st,stpmic1-regulators";
diff --git a/core/arch/arm/plat-stm32mp1/conf.mk b/core/arch/arm/plat-stm32mp1/conf.mk
index 6c959d4bc..05229e61e 100644
--- a/core/arch/arm/plat-stm32mp1/conf.mk
+++ b/core/arch/arm/plat-stm32mp1/conf.mk
@@ -310,10 +310,8 @@ CFG_ENABLE_EMBEDDED_TESTS ?= y
CFG_WITH_STATS ?= y
CFG_WERROR ?= y
-# Enable to allow debug
-ifeq ($(CFG_TEE_CORE_DEBUG),y)
+# Enable OTP update with BSEC driver
CFG_STM32_BSEC_WRITE ?= y
-endif
# Default disable some support for pager memory size constraint
ifeq ($(CFG_WITH_PAGER),y)
diff --git a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
index 4eda619cf..653ac4f7d 100644
--- a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
+++ b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
@@ -12,6 +12,7 @@
#include <drivers/stm32mp1_pmic.h>
#include <drivers/stm32mp1_pwr.h>
#include <drivers/stpmic1.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
#include <io.h>
#include <keep.h>
#include <kernel/boot.h>
@@ -26,6 +27,7 @@
#include <platform_config.h>
#include <stdbool.h>
#include <stm32_util.h>
+#include <sys/queue.h>
#include <trace.h>
#include <util.h>
@@ -42,6 +44,17 @@
static struct i2c_handle_s *i2c_pmic_handle;
static uint32_t pmic_i2c_addr;
+struct pmic_it_handle_s {
+ uint8_t pmic_reg;
+ uint8_t pmic_bit;
+ uint8_t notif_id;
+
+ SLIST_ENTRY(pmic_it_handle_s) link;
+};
+
+static SLIST_HEAD(pmic_it_handle_head, pmic_it_handle_s) pmic_it_handle_list =
+ SLIST_HEAD_INITIALIZER(pmic_it_handle_list);
+
/* CPU voltage supplier if found */
static char cpu_supply_name[PMIC_REGU_SUPPLY_NAME_LEN];
@@ -508,11 +521,10 @@ static void register_non_secure_pmic(void)
}
}
-static enum itr_return stpmic1_irq_handler(struct itr_handler *handler)
+static enum itr_return stpmic1_irq_handler(struct itr_handler *handler __unused)
{
uint8_t read_val = 0U;
unsigned int i = 0U;
- uint32_t *it_id = handler->data;
FMSG("Stpmic1 irq handler");
@@ -523,16 +535,22 @@ static enum itr_return stpmic1_irq_handler(struct itr_handler *handler)
panic();
if (read_val) {
+ struct pmic_it_handle_s *prv = NULL;
+
FMSG("Stpmic1 irq pending %u: %#"PRIx8, i, read_val);
if (stpmic1_register_write(ITCLEARLATCH1_REG + i,
read_val))
panic();
- /* forward falling interrupt to non-secure */
- if (i == 0 && (read_val & BIT(IT_PONKEY_F)))
- if (it_id)
- notif_send_it(*it_id);
+ SLIST_FOREACH(prv, &pmic_it_handle_list, link)
+ if ((prv->pmic_reg == ITCLEARMASK1_REG + i) &&
+ (read_val & BIT(prv->pmic_bit))) {
+ FMSG("STPMIC1 send notif %u",
+ prv->notif_id);
+
+ notif_send_it(prv->notif_id);
+ }
}
}
@@ -587,57 +605,104 @@ static void initialize_pmic(const void *fdt, int pmic_node)
stm32mp_put_pmic();
}
-static TEE_Result stm32_pmic_probe(const void *fdt, int node,
- const void *compat_data __unused)
+static TEE_Result stm32_pmic_init_it(const void *fdt, int node)
{
- TEE_Result res = TEE_SUCCESS;
- const fdt32_t *cuint = NULL;
+ TEE_Result res = TEE_ERROR_GENERIC;
+ const uint32_t *notif_ids = NULL;
+ int nb_notif = 0;
+ size_t pwr_it = 0;
struct itr_handler *hdl = NULL;
- size_t it = 0;
- uint32_t *it_id = NULL;
+ const fdt32_t *cuint = NULL;
- res = i2c_dt_get_by_subnode(fdt, node, &i2c_pmic_handle);
- if (res)
- return res;
+ cuint = fdt_getprop(fdt, node, "st,wakeup-pin-number", NULL);
+ if (!cuint) {
+ IMSG("Missing wake-up pin description");
+ return TEE_SUCCESS;
+ }
- initialize_pmic(fdt, node);
+ pwr_it = fdt32_to_cpu(*cuint) - 1U;
- if (IS_ENABLED(CFG_STM32MP13)) {
- cuint = fdt_getprop(fdt, node, "st,wakeup-pin-number", NULL);
- if (!cuint) {
- IMSG("Missing wake-up pin description");
- return TEE_SUCCESS;
- }
+ notif_ids = fdt_getprop(fdt, node, "st,notif-it-id", &nb_notif);
+ if (!notif_ids)
+ return TEE_ERROR_ITEM_NOT_FOUND;
- it = fdt32_to_cpu(*cuint) - 1U;
+ if (nb_notif > 0) {
+ struct pmic_it_handle_s *prv = NULL;
+ unsigned int i = 0;
+ const uint32_t *pmic_its = NULL;
+ int nb_it = 0;
- cuint = fdt_getprop(fdt, node, "st,notif-it-id", NULL);
- if (cuint) {
- it_id = calloc(1, sizeof(it_id));
- if (!it_id)
- return TEE_ERROR_OUT_OF_MEMORY;
+ pmic_its = fdt_getprop(fdt, node, "st,pmic-it-id", &nb_it);
+ if (!pmic_its)
+ return TEE_ERROR_ITEM_NOT_FOUND;
- *it_id = fdt32_to_cpu(*cuint);
- }
+ if (nb_it != nb_notif)
+ panic("st,notif-it-id incorrect description");
- res = stm32mp1_pwr_itr_alloc_add(it, stpmic1_irq_handler,
- PWR_WKUP_FLAG_FALLING |
- PWR_WKUP_FLAG_THREADED,
- it_id, &hdl);
- if (res)
- panic("pmic: Couldn't allocate itr");
+ for (i = 0; i < (nb_notif / sizeof(uint32_t)); i++) {
+ uint8_t val = 0;
+ uint8_t pmic_it = 0;
- stm32mp1_pwr_itr_enable(hdl->it);
+ prv = calloc(1, sizeof(*prv));
+ if (!prv)
+ panic("pmic: Couldn't allocate pmic it");
- /* Enable ponkey irq */
- stm32mp_get_pmic();
- if (stpmic1_register_write(ITCLEARMASK1_REG,
- BIT(IT_PONKEY_F) | BIT(IT_PONKEY_R)))
- panic();
+ pmic_it = fdt32_to_cpu(pmic_its[i]);
+
+ assert(pmic_it <= IT_SWIN_R);
+
+ prv->pmic_reg = ITCLEARMASK1_REG + pmic_it / U(8);
+ prv->pmic_bit = pmic_it % U(8);
+ prv->notif_id = fdt32_to_cpu(notif_ids[i]);
+
+ SLIST_INSERT_HEAD(&pmic_it_handle_list, prv, link);
+
+ stm32mp_get_pmic();
- stm32mp_put_pmic();
+ /* Enable requested interrupt */
+ if (stpmic1_register_read(prv->pmic_reg, &val))
+ panic();
+
+ val |= BIT(prv->pmic_bit);
+
+ if (stpmic1_register_write(prv->pmic_reg, val))
+ panic();
+
+ stm32mp_put_pmic();
+ }
+
+ SLIST_FOREACH(prv, &pmic_it_handle_list, link) {
+ FMSG("STPMIC1 forwards irq reg:%u bit:%u as notif:%u",
+ prv->pmic_reg, prv->pmic_bit, prv->notif_id);
+ }
}
+ res = stm32mp1_pwr_itr_alloc_add(pwr_it, stpmic1_irq_handler,
+ PWR_WKUP_FLAG_FALLING |
+ PWR_WKUP_FLAG_THREADED,
+ NULL, &hdl);
+ if (res)
+ panic("pmic: Couldn't allocate itr");
+
+ stm32mp1_pwr_itr_enable(hdl->it);
+
+ return res;
+}
+
+static TEE_Result stm32_pmic_probe(const void *fdt, int node,
+ const void *compat_data __unused)
+{
+ TEE_Result res = TEE_SUCCESS;
+
+ res = i2c_dt_get_by_subnode(fdt, node, &i2c_pmic_handle);
+ if (res)
+ return res;
+
+ initialize_pmic(fdt, node);
+
+ if (IS_ENABLED(CFG_STM32MP13))
+ res = stm32_pmic_init_it(fdt, node);
+
return res;
}
diff --git a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pwr_irq.c b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pwr_irq.c
index 0913e9151..ca2761a81 100644
--- a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pwr_irq.c
+++ b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pwr_irq.c
@@ -13,6 +13,7 @@
#include <kernel/dt.h>
#include <kernel/notif.h>
#include <kernel/panic.h>
+#include <kernel/spinlock.h>
#include <libfdt.h>
#include <platform_config.h>
#include <stm32_util.h>
@@ -47,6 +48,7 @@ struct stm32_pwr_data {
struct itr_handler *gic_hdl;
bool threaded[PWR_NB_WAKEUPPINS];
bool pending[PWR_NB_WAKEUPPINS];
+ unsigned int spinlock;
};
static struct stm32_pwr_data *pwr_data;
@@ -148,6 +150,7 @@ static TEE_Result
stm32_pwr_irq_set_pull_config(size_t it, enum wkup_pull_setting config)
{
struct stm32_pwr_data *priv = pwr_data;
+ uint32_t exceptions = 0;
VERBOSE_PWR("irq:%zu pull config:0%#"PRIx32, it, config);
@@ -156,29 +159,59 @@ stm32_pwr_irq_set_pull_config(size_t it, enum wkup_pull_setting config)
return TEE_ERROR_GENERIC;
}
+ exceptions = cpu_spin_lock_xsave(&priv->spinlock);
+
io_mask32(priv->base + WKUPCR,
(config & WKUP_PULL_MASK) << (WKUP_PULL_SHIFT + it * 2),
(WKUP_PULL_MASK) << (WKUP_PULL_SHIFT + it * 2));
+ cpu_spin_unlock_xrestore(&priv->spinlock, exceptions);
+
return TEE_SUCCESS;
}
-static TEE_Result
-stm32_pwr_irq_set_trig(size_t it, enum pwr_wkup_flags trig)
+static void stm32mp1_pwr_itr_enable_nolock(size_t it)
+{
+ struct stm32_pwr_data *priv = pwr_data;
+
+ VERBOSE_PWR("Pwr irq enable");
+
+ if (IS_ENABLED(CFG_STM32_EXTI))
+ stm32_exti_enable_wake(PWR_EXTI_WKUP1 + it);
+
+ io_setbits32(priv->base + MPUWKUPENR, BIT(it));
+}
+
+static void stm32mp1_pwr_itr_disable_nolock(size_t it)
+{
+ struct stm32_pwr_data *priv = pwr_data;
+
+ VERBOSE_PWR("Pwr irq disable");
+
+ io_clrbits32(priv->base + MPUWKUPENR, BIT(it));
+
+ if (IS_ENABLED(CFG_STM32_EXTI))
+ stm32_exti_disable_wake(PWR_EXTI_WKUP1 + it);
+}
+
+static TEE_Result stm32_pwr_irq_set_trig(size_t it, enum pwr_wkup_flags trig)
{
struct stm32_pwr_data *priv = pwr_data;
+ uint32_t exceptions = 0;
uint32_t wkupcr = 0;
int en = 0;
VERBOSE_PWR("irq:%zu trig:%#"PRIx32, it, trig);
+ exceptions = cpu_spin_lock_xsave(&priv->spinlock);
+
en = io_read32(priv->base + MPUWKUPENR) & BIT(it);
/*
* Reference manual request to disable the wakeup pin while
- * changing the edge detection setting
+ * changing the edge detection setting.
*/
if (en)
- stm32mp1_pwr_itr_disable(it);
+ stm32mp1_pwr_itr_disable_nolock(it);
wkupcr = io_read32(priv->base + WKUPCR);
switch (trig) {
@@ -195,7 +228,9 @@ stm32_pwr_irq_set_trig(size_t it, enum pwr_wkup_flags trig)
io_write32(priv->base + WKUPCR, wkupcr);
if (en)
- stm32mp1_pwr_itr_enable(it);
+ stm32mp1_pwr_itr_enable_nolock(it);
+
+ cpu_spin_unlock_xrestore(&priv->spinlock, exceptions);
return TEE_SUCCESS;
}
@@ -203,25 +238,21 @@ stm32_pwr_irq_set_trig(size_t it, enum pwr_wkup_flags trig)
void stm32mp1_pwr_itr_enable(size_t it)
{
struct stm32_pwr_data *priv = pwr_data;
+ uint32_t exceptions = 0;
- VERBOSE_PWR("Pwr irq enable");
-
- if (IS_ENABLED(CFG_STM32_EXTI))
- stm32_exti_enable_wake(PWR_EXTI_WKUP1 + it);
-
- io_setbits32(priv->base + MPUWKUPENR, BIT(it));
+ exceptions = cpu_spin_lock_xsave(&priv->spinlock);
+ stm32mp1_pwr_itr_enable_nolock(it);
+ cpu_spin_unlock_xrestore(&priv->spinlock, exceptions);
}
void stm32mp1_pwr_itr_disable(size_t it)
{
struct stm32_pwr_data *priv = pwr_data;
+ uint32_t exceptions = 0;
- VERBOSE_PWR("Pwr irq disable");
-
- io_clrbits32(priv->base + MPUWKUPENR, BIT(it));
-
- if (IS_ENABLED(CFG_STM32_EXTI))
- stm32_exti_disable_wake(PWR_EXTI_WKUP1 + it);
+ exceptions = cpu_spin_lock_xsave(&priv->spinlock);
+ stm32mp1_pwr_itr_disable_nolock(it);
+ cpu_spin_unlock_xrestore(&priv->spinlock, exceptions);
}
static TEE_Result stm32mp1_pwr_irt_add(struct itr_handler *hdl)
@@ -231,7 +262,9 @@ static TEE_Result stm32mp1_pwr_irt_add(struct itr_handler *hdl)
struct stm32_pinctrl_list pinctrl_list = { };
struct stm32_pinctrl pin = { };
struct stm32_pinctrl *pinctrl = NULL;
+ uint32_t exceptions = 0;
unsigned int i = 0;
+ bool itr_free = false;
VERBOSE_PWR("Pwr IRQ add");
@@ -241,10 +274,15 @@ static TEE_Result stm32mp1_pwr_irt_add(struct itr_handler *hdl)
}
assert(it >= PWR_WKUP_PIN1 && it < PWR_NB_WAKEUPPINS);
- /* check IRQ not already in use */
- assert(!priv->hdl[it]);
- priv->hdl[it] = hdl;
+ /* Use PWR lock to ensure consistent interrupt registering */
+ exceptions = cpu_spin_lock_xsave(&priv->spinlock);
+ itr_free = !priv->hdl[it];
+ if (itr_free)
+ priv->hdl[it] = hdl;
+ cpu_spin_unlock_xrestore(&priv->spinlock, exceptions);
+ if (!itr_free)
+ return TEE_ERROR_GENERIC;
if (hdl->flags & PWR_WKUP_FLAG_THREADED)
priv->threaded[it] = true;
diff --git a/core/arch/arm/plat-stm32mp1/main.c b/core/arch/arm/plat-stm32mp1/main.c
index 2e9f7a699..3ae327ee5 100644
--- a/core/arch/arm/plat-stm32mp1/main.c
+++ b/core/arch/arm/plat-stm32mp1/main.c
@@ -165,9 +165,9 @@ static TEE_Result init_console_from_dt(void)
/* Replace early console with the new one */
console_flush();
console_data = *pd;
- free(pd);
register_serial_console(&console_data.chip);
IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-");
+ free(pd);
return TEE_SUCCESS;
}
@@ -727,7 +727,7 @@ static TEE_Result stm32_configure_tamp(void)
return TEE_SUCCESS;
}
-driver_init_late(stm32_configure_tamp);
+service_init(stm32_configure_tamp);
#endif
#ifdef CFG_STM32_HSE_MONITORING
diff --git a/core/arch/arm/plat-stm32mp1/pm/context.c b/core/arch/arm/plat-stm32mp1/pm/context.c
index c9d26ee37..7e08bc0a2 100644
--- a/core/arch/arm/plat-stm32mp1/pm/context.c
+++ b/core/arch/arm/plat-stm32mp1/pm/context.c
@@ -213,7 +213,7 @@ static void __maybe_unused print_ccm_decryption_duration(void)
((unsigned long long)ctx->stgen_cnt * 1000) /
io_read32(stgen + CNTFID_OFFSET));
- clk_enable(pm_clocks.bkpsram);
+ clk_disable(pm_clocks.bkpsram);
}
#else
static void __maybe_unused print_ccm_decryption_duration(void)
@@ -582,15 +582,17 @@ TEE_Result stm32mp_pm_call_bl2_lp_entry(unsigned int soc_mode)
dcache_op_all(DCACHE_OP_CLEAN_INV);
+ /* Disable Cache & MMU before calling low_power section */
+ write_sctlr(read_sctlr() & ~(SCTLR_C | SCTLR_M));
+
dsb();
+ isb();
- /* Disable MMU before calling low_power section */
- write_sctlr(read_sctlr() & ~SCTLR_M);
(*stm32_pwr_down_wfi)(true, soc_mode);
- /* Enable MMU */
- write_sctlr(read_sctlr() | SCTLR_M);
+ /* Enable Cache & MMU */
+ write_sctlr(read_sctlr() | SCTLR_C | SCTLR_M);
clk_disable(pm_clocks.bkpsram);
diff --git a/core/arch/arm/plat-stm32mp1/pm/low_power.c b/core/arch/arm/plat-stm32mp1/pm/low_power.c
index cbc5fa151..653c3dfb7 100644
--- a/core/arch/arm/plat-stm32mp1/pm/low_power.c
+++ b/core/arch/arm/plat-stm32mp1/pm/low_power.c
@@ -292,13 +292,6 @@ void stm32_enter_cstop(uint32_t mode)
io_clrsetbits32(pwr_base + PWR_CR3_OFF, PWR_CR3_POPL_MASK,
20U << PWR_CR3_POPL_SHIFT);
- /* Keep backup RAM content in standby */
- io_setbits32(pwr_base + PWR_CR2_OFF, PWR_CR2_BREN);
-
- // TODO add a timeout?
- while (!(io_read32(pwr_base + PWR_CR2_OFF) & PWR_CR2_BRRDY))
- ;
-
#ifndef CFG_STM32MP13
if (stm32mp1_is_retram_during_standby()) {
/* Keep retention in standby */
@@ -344,9 +337,6 @@ void stm32_exit_cstop(void)
dsb();
isb();
- /* Disable retention and backup RAM content after stop */
- io_clrbits32(stm32_pwr_base() + PWR_CR2_OFF, PWR_CR2_BREN);
-
#ifndef CFG_STM32MP13
/* Disable retention and backup RAM content after stop */
io_clrbits32(stm32_pwr_base() + PWR_CR2_OFF, PWR_CR2_RREN);
@@ -525,6 +515,11 @@ static TEE_Result init_low_power(void)
RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1);
#endif
+ /* Keep backup RAM content in standby */
+ io_setbits32(pwr_base + PWR_CR2_OFF, PWR_CR2_BREN);
+ while (!(io_read32(pwr_base + PWR_CR2_OFF) & PWR_CR2_BRRDY))
+ ;
+
return TEE_SUCCESS;
}
driver_init_late(init_low_power);
diff --git a/core/drivers/crypto/stm32/stm32_saes.c b/core/drivers/crypto/stm32/stm32_saes.c
index 9453d0d52..d8495a16e 100644
--- a/core/drivers/crypto/stm32/stm32_saes.c
+++ b/core/drivers/crypto/stm32/stm32_saes.c
@@ -1337,6 +1337,13 @@ TEE_Result huk_subkey_derive(enum huk_subkey_usage usage,
struct stm32_saes_context ctx = { };
uint8_t separator = 0;
+ // Check if driver is probed
+ if (saes_pdata.base.pa == 0) {
+ DMSG("Use __huk_subkey_derive instead of SAES IP features");
+ return __huk_subkey_derive(usage, const_data, const_data_len,
+ subkey, subkey_len);
+ }
+
input = malloc(const_data_len + sizeof(separator) + sizeof(usage) +
sizeof(subkey_bitlen) + AES_BLOCK_SIZE);
if (!input)
diff --git a/core/drivers/regulator/core.c b/core/drivers/regulator/core.c
index d4dc3751d..7ef58b268 100644
--- a/core/drivers/regulator/core.c
+++ b/core/drivers/regulator/core.c
@@ -575,6 +575,11 @@ static TEE_Result parse_properties(const void *fdt, struct rdev *rdev, int node)
}
rdev->reg_name = fdt_getprop(fdt, node, "regulator-name", NULL);
+ if (rdev->reg_name) {
+ rdev->reg_name = strdup(rdev->reg_name);
+ if (!rdev->reg_name)
+ panic();
+ }
return TEE_SUCCESS;
}
diff --git a/core/drivers/stm32_iwdg.c b/core/drivers/stm32_iwdg.c
index 49e4fad50..fba4abe7e 100644
--- a/core/drivers/stm32_iwdg.c
+++ b/core/drivers/stm32_iwdg.c
@@ -35,6 +35,7 @@
#define IWDG_EWCR_OFFSET U(0x14)
/* Registers values */
+#define IWDG_KR_WPROT_KEY U(0x0000)
#define IWDG_KR_ACCESS_KEY U(0x5555)
#define IWDG_KR_RELOAD_KEY U(0xAAAA)
#define IWDG_KR_START_KEY U(0xCCCC)
@@ -45,6 +46,7 @@
#define IWDG_RLR_RL_MASK GENMASK_32(11, 0)
#define IWDG_SR_EWU BIT(3)
+#define IWDG_SR_EWIF BIT(14)
#define IWDG_EWCR_EWIE BIT(15)
#define IWDG_EWCR_EWIC BIT(14)
@@ -88,10 +90,22 @@ static enum itr_return stm32_iwdg_it_handler(struct itr_handler *handler)
stm32mp_dump_core_registers(true);
- iwdg_refresh(iwdg);
-
clk_enable(iwdg->pdata.clock);
+ /* Check for spurious interrupt */
+ if (!(io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_EWIF)) {
+ clk_disable(iwdg->pdata.clock);
+ return ITRR_NONE;
+ }
+
+ /*
+ * Writing IWDG_EWCR_EWIT triggers a watchdog refresh.
+ * To prevent the watchdog refresh, write-protect all the registers;
+ * this makes read-only all IWDG_EWCR fields except IWDG_EWCR_EWIC.
+ */
+ io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_WPROT_KEY);
+
+ /* Disable early interrupt */
io_setbits32(iwdg_base + IWDG_EWCR_OFFSET, IWDG_EWCR_EWIC);
clk_disable(iwdg->pdata.clock);
diff --git a/core/drivers/stm32_rng.c b/core/drivers/stm32_rng.c
index ef5862308..363aeee00 100644
--- a/core/drivers/stm32_rng.c
+++ b/core/drivers/stm32_rng.c
@@ -140,9 +140,19 @@ static TEE_Result stm32_rng_read_available(struct stm32_rng_device *dev,
/* RNG is ready: read up to 4 32bit words */
while (size) {
- uint32_t data32 = io_read32(base + RNG_DR);
+ uint32_t data32 = 0;
size_t sz = MIN(size, sizeof(uint32_t));
+ if (!(io_read32(base + RNG_SR) & RNG_SR_DRDY))
+ return TEE_ERROR_NO_DATA;
+
+ data32 = io_read32(base + RNG_DR);
+ /* Late seed error case: DR being 0 is an error status */
+ if (!data32) {
+ conceal_seed_error(dev);
+ return TEE_ERROR_NO_DATA;
+ }
+
memcpy(buf, &data32, sz);
buf += sz;
size -= sz;
diff --git a/core/drivers/stm32_uart.c b/core/drivers/stm32_uart.c
index 5105b14bc..1ffc99117 100644
--- a/core/drivers/stm32_uart.c
+++ b/core/drivers/stm32_uart.c
@@ -38,12 +38,12 @@
* Bit 5 RXNE: Read data register not empty/RXFIFO not empty
* Bit 6 TC: Transmission complete
* Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full
- * Bit 27 TXFE: TXFIFO threshold reached
+ * Bit 23 TXFE: TXFIFO empty
*/
#define USART_ISR_RXNE_RXFNE BIT(5)
#define USART_ISR_TC BIT(6)
#define USART_ISR_TXE_TXFNF BIT(7)
-#define USART_ISR_TXFE BIT(27)
+#define USART_ISR_TXFE BIT(23)
static vaddr_t loc_chip_to_base(struct serial_chip *chip)
{
diff --git a/core/include/drivers/stpmic1.h b/core/include/drivers/stpmic1.h
index 5fe48232f..b293c846f 100644
--- a/core/include/drivers/stpmic1.h
+++ b/core/include/drivers/stpmic1.h
@@ -171,41 +171,6 @@
#define USBSW_OTG_SWITCH_ENABLED_POS 1
#define BOOST_ENABLED_POS 0
-/* IRQ definitions */
-#define IT_PONKEY_F 0
-#define IT_PONKEY_R 1
-#define IT_WAKEUP_F 2
-#define IT_WAKEUP_R 3
-#define IT_VBUS_OTG_F 4
-#define IT_VBUS_OTG_R 5
-#define IT_SWOUT_F 6
-#define IT_SWOUT_R 7
-
-#define IT_CURLIM_BUCK1 0
-#define IT_CURLIM_BUCK2 1
-#define IT_CURLIM_BUCK3 2
-#define IT_CURLIM_BUCK4 3
-#define IT_OCP_OTG 4
-#define IT_OCP_SWOUT 5
-#define IT_OCP_BOOST 6
-#define IT_OVP_BOOST 7
-
-#define IT_CURLIM_LDO1 0
-#define IT_CURLIM_LDO2 1
-#define IT_CURLIM_LDO3 2
-#define IT_CURLIM_LDO4 3
-#define IT_CURLIM_LDO5 4
-#define IT_CURLIM_LDO6 5
-#define IT_SHORT_SWOTG 6
-#define IT_SHORT_SWOUT 7
-
-#define IT_TWARN_F 0
-#define IT_TWARN_R 1
-#define IT_VINLOW_F 2
-#define IT_VINLOW_R 3
-#define IT_SWIN_F 4
-#define IT_SWIN_R 5
-
/*
* Bind SPMIC1 device driver with a specific I2C bus instance
* @i2c_handle: target I2C instance to use
diff --git a/core/include/kernel/huk_subkey.h b/core/include/kernel/huk_subkey.h
index 59bcf2773..a6a18e953 100644
--- a/core/include/kernel/huk_subkey.h
+++ b/core/include/kernel/huk_subkey.h
@@ -49,12 +49,17 @@ enum huk_subkey_usage {
*
* Returns a subkey derived from the hardware unique key. Given the same
* input the same subkey is returned each time.
+ * Function huk_subkey_derive is __weak to allow platform custom implementation.
+ * __huk_subkey_derive implements the default behavior of huk_subkey_derive.
*
* Return TEE_SUCCES on success or an error code on failure.
*/
TEE_Result huk_subkey_derive(enum huk_subkey_usage usage,
const void *const_data, size_t const_data_len,
uint8_t *subkey, size_t subkey_len);
+TEE_Result __huk_subkey_derive(enum huk_subkey_usage usage,
+ const void *const_data, size_t const_data_len,
+ uint8_t *subkey, size_t subkey_len);
#endif /*__KERNEL_HUK_SUBKEY_H*/
diff --git a/core/kernel/huk_subkey.c b/core/kernel/huk_subkey.c
index 5481120b6..3db2cfe5f 100644
--- a/core/kernel/huk_subkey.c
+++ b/core/kernel/huk_subkey.c
@@ -58,10 +58,9 @@ static TEE_Result huk_compat(void *ctx, enum huk_subkey_usage usage)
}
#endif /*CFG_CORE_HUK_SUBKEY_COMPAT*/
-__weak
-TEE_Result huk_subkey_derive(enum huk_subkey_usage usage,
- const void *const_data, size_t const_data_len,
- uint8_t *subkey, size_t subkey_len)
+TEE_Result __huk_subkey_derive(enum huk_subkey_usage usage,
+ const void *const_data, size_t const_data_len,
+ uint8_t *subkey, size_t subkey_len)
{
void *ctx = NULL;
struct tee_hw_unique_key huk = { };
@@ -106,3 +105,12 @@ out:
crypto_mac_free_ctx(ctx);
return res;
}
+
+__weak
+TEE_Result huk_subkey_derive(enum huk_subkey_usage usage,
+ const void *const_data, size_t const_data_len,
+ uint8_t *subkey, size_t subkey_len)
+{
+ return __huk_subkey_derive(usage, const_data, const_data_len, subkey,
+ subkey_len);
+}
diff --git a/documentation/devicetree/bindings/mfd/st,stpmic1.yaml b/documentation/devicetree/bindings/mfd/st,stpmic1.yaml
index 344623f1f..7d97a7082 100644
--- a/documentation/devicetree/bindings/mfd/st,stpmic1.yaml
+++ b/documentation/devicetree/bindings/mfd/st,stpmic1.yaml
@@ -262,6 +262,51 @@ properties:
minItems: 1
maxItems: 1
+ st,pmic-it-id:
+ description: PMIC interruptions id to forward to the non-secure world
+ in the form of OPTEE notifications described by st,notif-it-id.
+ IT_PONKEY_F = 0
+ IT_PONKEY_R = 1
+ IT_WAKEUP_F = 2
+ IT_WAKEUP_R = 3
+ IT_VBUS_OTG_F = 4
+ IT_VBUS_OTG_R = 5
+ IT_SWOUT_F = 6
+ IT_SWOUT_R = 7
+ IT_CURLIM_BUCK1 = 8
+ IT_CURLIM_BUCK2 = 9
+ IT_CURLIM_BUCK3 = 10
+ IT_CURLIM_BUCK4 = 11
+ IT_OCP_OTG = 12
+ IT_OCP_SWOUT = 13
+ IT_OCP_BOOST = 14
+ IT_OVP_BOOST = 15
+ IT_CURLIM_LDO1 = 16
+ IT_CURLIM_LDO2 = 17
+ IT_CURLIM_LDO3 = 18
+ IT_CURLIM_LDO4 = 19
+ IT_CURLIM_LDO5 = 20
+ IT_CURLIM_LDO6 = 21
+ IT_SHORT_SWOTG = 22
+ IT_SHORT_SWOUT = 23
+ IT_TWARN_F = 24
+ IT_TWARN_R = 25
+ IT_VINLOW_F = 26
+ IT_VINLOW_R = 27
+ IT_SWIN_F = 30
+ IT_SWIN_R = 31
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minItems: 1
+ maxItems: 32
+
+ st,notif-it-id:
+ description: OPTEE notification numbers to send to the non-secure world.
+ One notification is needed for each interruption listed by st,pmic-it-id,
+ so the number of notifications must be eaqual to the number of interrupts.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minItems: 1
+ maxItems: 32
+
additionalProperties: false
required:
@@ -271,6 +316,10 @@ required:
- "#interrupt-cells"
- interrupt-controller
+dependencies:
+ st,notif-it-id: [ 'st,pmic-it-id' ]
+ st,pmic-it-id: [ 'st,notif-it-id' ]
+
examples:
- |
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -289,6 +338,8 @@ examples:
#interrupt-cells = <2>;
st,wakeup-pin-number = <1>;
+ st,pmic-it-id = <IT_PONKEY_F IT_PONKEY_R>;
+ st,notif-it-id = <0 2>;
onkey {
compatible = "st,stpmic1-onkey";
--
2.25.1