From c8d598d448c6a49bcfd5383053a226db1f883ef7 Mon Sep 17 00:00:00 2001 From: christophe montaud Date: Mon, 28 Jan 2019 11:06:23 +0100 Subject: [PATCH 7/8] ARM v2018.11 stm32mp r2 DEVICETREE --- arch/arm/dts/stm32mp157a-dk1.dts | 3 +- arch/arm/dts/stm32mp157c-ed1.dts | 3 +- arch/arm/dts/stm32mp157c-m4-srm.dtsi | 436 +++++++++++++++++++++++++ doc/device-tree-bindings/clock/st,stm32mp1.txt | 427 ++++++++++++++++-------- 4 files changed, 727 insertions(+), 142 deletions(-) create mode 100644 arch/arm/dts/stm32mp157c-m4-srm.dtsi diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e3d305a..8e09447 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" +#include "stm32mp157c-m4-srm.dtsi" #include "stm32mp157cac-pinctrl.dtsi" #include #include @@ -309,7 +310,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 37edf87..0f70bb7 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" +#include "stm32mp157c-m4-srm.dtsi" #include "stm32mp157caa-pinctrl.dtsi" #include #include @@ -202,7 +203,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; diff --git a/arch/arm/dts/stm32mp157c-m4-srm.dtsi b/arch/arm/dts/stm32mp157c-m4-srm.dtsi new file mode 100644 index 0000000..5ebe24b --- /dev/null +++ b/arch/arm/dts/stm32mp157c-m4-srm.dtsi @@ -0,0 +1,436 @@ +&m4_rproc { + m4_system_resources { + #address-cells = <1>; + #size-cells = <0>; + + m4_timers2: timer@40000000 { + compatible = "rproc-srm-dev"; + reg = <0x40000000>; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers3: timer@40001000 { + compatible = "rproc-srm-dev"; + reg = <0x40001000>; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers4: timer@40002000 { + compatible = "rproc-srm-dev"; + reg = <0x40002000>; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers5: timer@40003000 { + compatible = "rproc-srm-dev"; + reg = <0x40003000>; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers6: timer@40004000 { + compatible = "rproc-srm-dev"; + reg = <0x40004000>; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers7: timer@40005000 { + compatible = "rproc-srm-dev"; + reg = <0x40005000>; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers12: timer@40006000 { + compatible = "rproc-srm-dev"; + reg = <0x40006000>; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers13: timer@40007000 { + compatible = "rproc-srm-dev"; + reg = <0x40007000>; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers14: timer@40008000 { + compatible = "rproc-srm-dev"; + reg = <0x40008000>; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_lptimer1: timer@40009000 { + compatible = "rproc-srm-dev"; + reg = <0x40009000>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_spi2: spi@4000b000 { + compatible = "rproc-srm-dev"; + reg = <0x4000b000>; + clocks = <&rcc SPI2_K>; + status = "disabled"; + }; + m4_i2s2: audio-controller@4000b000 { + compatible = "rproc-srm-dev"; + reg = <0x4000b000>; + status = "disabled"; + }; + m4_spi3: spi@4000c000 { + compatible = "rproc-srm-dev"; + reg = <0x4000c000>; + clocks = <&rcc SPI3_K>; + status = "disabled"; + }; + m4_i2s3: audio-controller@4000c000 { + compatible = "rproc-srm-dev"; + reg = <0x4000c000>; + status = "disabled"; + }; + m4_spdifrx: audio-controller@4000d000 { + compatible = "rproc-srm-dev"; + reg = <0x4000d000>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + status = "disabled"; + }; + m4_usart2: serial@4000e000 { + compatible = "rproc-srm-dev"; + reg = <0x4000e000>; + interrupt-parent = <&exti>; + interrupts = <27 1>; + clocks = <&rcc USART2_K>; + status = "disabled"; + }; + m4_usart3: serial@4000f000 { + compatible = "rproc-srm-dev"; + reg = <0x4000f000>; + interrupt-parent = <&exti>; + interrupts = <28 1>; + clocks = <&rcc USART3_K>; + status = "disabled"; + }; + m4_uart4: serial@40010000 { + compatible = "rproc-srm-dev"; + reg = <0x40010000>; + interrupt-parent = <&exti>; + interrupts = <30 1>; + clocks = <&rcc UART4_K>; + status = "disabled"; + }; + m4_uart5: serial@40011000 { + compatible = "rproc-srm-dev"; + reg = <0x40011000>; + interrupt-parent = <&exti>; + interrupts = <31 1>; + clocks = <&rcc UART5_K>; + status = "disabled"; + }; + m4_i2c1: i2c@40012000 { + compatible = "rproc-srm-dev"; + reg = <0x40012000>; + interrupt-parent = <&exti>; + interrupts = <21 1>; + clocks = <&rcc I2C1_K>; + status = "disabled"; + }; + m4_i2c2: i2c@40013000 { + compatible = "rproc-srm-dev"; + reg = <0x40013000>; + interrupt-parent = <&exti>; + interrupts = <22 1>; + clocks = <&rcc I2C2_K>; + status = "disabled"; + }; + m4_i2c3: i2c@40014000 { + compatible = "rproc-srm-dev"; + reg = <0x40014000>; + interrupt-parent = <&exti>; + interrupts = <23 1>; + clocks = <&rcc I2C3_K>; + status = "disabled"; + }; + m4_i2c5: i2c@40015000 { + compatible = "rproc-srm-dev"; + reg = <0x40015000>; + interrupt-parent = <&exti>; + interrupts = <25 1>; + clocks = <&rcc I2C5_K>; + status = "disabled"; + }; + m4_cec: cec@40016000 { + compatible = "rproc-srm-dev"; + reg = <0x40016000>; + interrupt-parent = <&exti>; + interrupts = <69 1>; + clocks = <&rcc CEC_K>, <&rcc CK_LSE>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + m4_dac: dac@40017000 { + compatible = "rproc-srm-dev"; + reg = <0x40017000>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + status = "disabled"; + }; + m4_uart7: serial@40018000 { + compatible = "rproc-srm-dev"; + reg = <0x40018000>; + interrupt-parent = <&exti>; + interrupts = <32 1>; + clocks = <&rcc UART7_K>; + status = "disabled"; + }; + m4_uart8: serial@40019000 { + compatible = "rproc-srm-dev"; + reg = <0x40019000>; + interrupt-parent = <&exti>; + interrupts = <33 1>; + clocks = <&rcc UART8_K>; + status = "disabled"; + }; + m4_timers1: timer@44000000 { + compatible = "rproc-srm-dev"; + reg = <0x44000000>; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers8: timer@44001000 { + compatible = "rproc-srm-dev"; + reg = <0x44001000>; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_usart6: serial@44003000 { + compatible = "rproc-srm-dev"; + reg = <0x44003000>; + interrupt-parent = <&exti>; + interrupts = <29 1>; + clocks = <&rcc USART6_K>; + status = "disabled"; + }; + m4_spi1: spi@44004000 { + compatible = "rproc-srm-dev"; + reg = <0x44004000>; + clocks = <&rcc SPI1_K>; + status = "disabled"; + }; + m4_i2s1: audio-controller@44004000 { + compatible = "rproc-srm-dev"; + reg = <0x44004000>; + status = "disabled"; + }; + m4_spi4: spi@44005000 { + compatible = "rproc-srm-dev"; + reg = <0x44005000>; + clocks = <&rcc SPI4_K>; + status = "disabled"; + }; + m4_timers15: timer@44006000 { + compatible = "rproc-srm-dev"; + reg = <0x44006000>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers16: timer@44007000 { + compatible = "rproc-srm-dev"; + reg = <0x44007000>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers17: timer@44008000 { + compatible = "rproc-srm-dev"; + reg = <0x44008000>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_spi5: spi@44009000 { + compatible = "rproc-srm-dev"; + reg = <0x44009000>; + clocks = <&rcc SPI5_K>; + status = "disabled"; + }; + m4_sai1: sai@4400a000 { + compatible = "rproc-srm-dev"; + reg = <0x4400a000>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_sai2: sai@4400b000 { + compatible = "rproc-srm-dev"; + reg = <0x4400b000>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_sai3: sai@4400c000 { + compatible = "rproc-srm-dev"; + reg = <0x4400c000>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_dfsdm: dfsdm@4400d000 { + compatible = "rproc-srm-dev"; + reg = <0x4400d000>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + status = "disabled"; + }; + m4_m_can1: can@4400e000 { + compatible = "rproc-srm-dev"; + reg = <0x4400e000>, <0x44011000>; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + status = "disabled"; + }; + m4_m_can2: can@4400f000 { + compatible = "rproc-srm-dev"; + reg = <0x4400f000>, <0x44011000>; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + status = "disabled"; + }; + m4_dma1: dma@48000000 { + compatible = "rproc-srm-dev"; + reg = <0x48000000>; + clocks = <&rcc DMA1>; + status = "disabled"; + }; + m4_dma2: dma@48001000 { + compatible = "rproc-srm-dev"; + reg = <0x48001000>; + clocks = <&rcc DMA2>; + status = "disabled"; + }; + m4_dmamux1: dma-router@48002000 { + compatible = "rproc-srm-dev"; + reg = <0x48002000>; + clocks = <&rcc DMAMUX>; + status = "disabled"; + }; + m4_adc: adc@48003000 { + compatible = "rproc-srm-dev"; + reg = <0x48003000>; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + status = "disabled"; + }; + m4_sdmmc3: sdmmc@48004000 { + compatible = "rproc-srm-dev"; + reg = <0x48004000>, <0x48005000>; + clocks = <&rcc SDMMC3_K>; + status = "disabled"; + }; + m4_usbotg_hs: usb-otg@49000000 { + compatible = "rproc-srm-dev"; + reg = <0x49000000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + status = "disabled"; + }; + m4_hash2: hash@4c002000 { + compatible = "rproc-srm-dev"; + reg = <0x4c002000>; + clocks = <&rcc HASH2>; + status = "disabled"; + }; + m4_rng2: rng@4c003000 { + compatible = "rproc-srm-dev"; + reg = <0x4c003000>; + clocks = <&rcc RNG2_K>; + status = "disabled"; + }; + m4_crc2: crc@4c004000 { + compatible = "rproc-srm-dev"; + reg = <0x4c004000>; + clocks = <&rcc CRC2>; + status = "disabled"; + }; + m4_cryp2: cryp@4c005000 { + compatible = "rproc-srm-dev"; + reg = <0x4c005000>; + clocks = <&rcc CRYP2>; + status = "disabled"; + }; + m4_dcmi: dcmi@4c006000 { + compatible = "rproc-srm-dev"; + reg = <0x4c006000>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + status = "disabled"; + }; + m4_lptimer2: timer@50021000 { + compatible = "rproc-srm-dev"; + reg = <0x50021000>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer3: timer@50022000 { + compatible = "rproc-srm-dev"; + reg = <0x50022000>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer4: timer@50023000 { + compatible = "rproc-srm-dev"; + reg = <0x50023000>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer5: timer@50024000 { + compatible = "rproc-srm-dev"; + reg = <0x50024000>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_sai4: sai@50027000 { + compatible = "rproc-srm-dev"; + reg = <0x50027000>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_qspi: qspi@58003000 { + compatible = "rproc-srm-dev"; + reg = <0x58003000>, <0x70000000>; + clocks = <&rcc QSPI_K>; + status = "disabled"; + }; + m4_ethernet0: ethernet@5800a000 { + compatible = "rproc-srm-dev"; + reg = <0x5800a000>; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "syscfg-clk"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHSTP>, + <&rcc SYSCFG>; + status = "disabled"; + }; + }; +}; + diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e..02e1460 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -1,185 +1,186 @@ STMicroelectronics STM32MP1 clock tree initialization ===================================================== -The STM32MP clock tree initialization is based on device tree information -for RCC IP and on fixed clocks. +The STM32MP1 clock tree initialization is based on device tree information +for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes. -------------------------------- -RCC CLOCK = st,stm32mp1-rcc-clk -------------------------------- +RCC IP = st,stm32mp1-rcc +======================== The RCC IP is both a reset and a clock controller but this documentation only describes the fields added for clock tree initialization which are not present -in Linux binding. +in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt +file. -Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common -with Linux. +The added properties for clock tree initialization are: Required properties: +- st,clksrc : The clock sources configuration array in a platform specific + order. -- compatible: Should be "st,stm32mp1-rcc-clk" + For the STM32MP15x family there are 9 clock sources selector which are + configured in the following order: + MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 -- st,clksrc : The clock source in this order + Clock source configuration values are defined by macros CLK__ + from dt-bindings/clock/stm32mp1-clksrc.h. - for STM32MP15x: 9 clock sources are requested - MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 - - with value equals to RCC clock specifier as defined in - dt-bindings/clock/stm32mp1-clksrc.h: CLK__ - -- st,clkdiv : The div parameters in this order - for STM32MP15x: 11 dividers value are requested + Example: + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + +- st,clkdiv : The clock main dividers value specified in an array + in a platform specific order. + + When used, it shall describe the whole clock dividers tree. + + For the STM32MP15x family there are 11 dividers values expected. + They shall be configured in the following order: MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2 - with DIV coding defined in RCC associated register RCC_xxxDIVR - - most the case, it is: + The each divider value uses the DIV coding defined in RCC associated + register RCC_xxxDIVR. In most the case, it is: 0x0: not divided 0x1: division by 2 0x2: division by 4 0x3: division by 8 ... - but for RTC MCO1 MCO2, the coding is different: + Note that for RTC MCO1 MCO2, the coding is different: 0x0: not divided 0x1: division by 2 0x2: division by 3 0x3: division by 4 ... -Optional Properties: -- st,pll - PLL children node for PLL1 to PLL4 : (see ref manual for details) - with associated index 0 to 3 (st,pll@0 to st,pll@4) - PLLx is off when the associated node is absent + Example: + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; - - Sub-nodes: +Optional Properties: +- st,pll : A specific PLL configuration, including frequency. - - cfg: The parameters for PLL configuration in this order: - DIVM DIVN DIVP DIVQ DIVR Output + PLL children nodes for PLL1 to PLL4 (see ref manual for details) + are listed with associated index 0 to 3 (st,pll@0 to st,pll@3). + PLLx is off when the associated node is absent. - with DIV value as defined in RCC spec: - 0x0: bypass (division by 1) - 0x1: division by 2 - 0x2: division by 3 - 0x3: division by 4 - ... + Here are the available properties for each PLL node: - and Output = bitfield for each output value = 1:ON/0:OFF - BIT(0) => output P : DIVPEN - BIT(1) => output Q : DIVQEN - BIT(2) => output R : DIVREN - NB : macro PQR(p,q,r) can be used to build this value - with p,p,r = 0 or 1 + - cfg: The parameters for PLL configuration in the following order: + DIVM DIVN DIVP DIVQ DIVR Output. - - frac : Fractional part of the multiplication factor - (optional, PLL is in integer mode when absent) + DIVx values are defined as in RCC spec: + 0x0: bypass (division by 1) + 0x1: division by 2 + 0x2: division by 3 + 0x3: division by 4 + ... - - csg : Clock Spreading Generator (optional) - with parameters in this order: - MOD_PER INC_STEP SSCG_MODE + Output contains a bitfield for each output value (1:ON/0:OFF) + BIT(0) => output P : DIVPEN + BIT(1) => output Q : DIVQEN + BIT(2) => output R : DIVREN + NB: macro PQR(p,q,r) can be used to build this value + with p,q,r = 0 or 1. + + - frac : Fractional part of the multiplication factor + (optional, PLL is in integer mode when absent). + + - csg : Clock Spreading Generator (optional) with parameters in the + following order: MOD_PER INC_STEP SSCG_MODE. + + MOD_PER: Modulation Period Adjustment + INC_STEP: Modulation Depth Adjustment + SSCG_MODE: Spread spectrum clock generator mode, with associated + defined from stm32mp1-clksrc.h: + - SSCG_MODE_CENTER_SPREAD = 0 + - SSCG_MODE_DOWN_SPREAD = 1 + + Example: + st,pll@0 { + cfg = < 1 53 0 0 0 1 >; + frac = < 0x810 >; + }; + st,pll@1 { + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; + }; + st,pll@2 { + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; + }; + st,pll@3 { + cfg = < 2 78 4 7 9 3 >; + }; - * MOD_PER: Modulation Period Adjustment - * INC_STEP: Modulation Depth Adjustment - * SSCG_MODE: Spread spectrum clock generator mode - you can use associated defines from stm32mp1-clksrc.h - * SSCG_MODE_CENTER_SPREAD = 0 - * SSCG_MODE_DOWN_SPREAD = 1 +- st,pkcs : used to configure the peripherals kernel clock selection. + The property is a list of peripheral kernel clock source identifiers defined + by macros CLK__ as defined by header file + dt-bindings/clock/stm32mp1-clksrc.h. -- st,pkcs : used to configure the peripherals kernel clock selection - containing a list of peripheral kernel clock source identifier as defined - in the file dt-bindings/clock/stm32mp1-clksrc.h + st,pkcs may not list all the kernel clocks and has no ordering requirements. Example: + st,pkcs = < + CLK_STGEN_HSE + CLK_CKPER_HSI + CLK_USBPHY_PLL2P + CLK_DSI_PLL2Q + CLK_I2C46_HSI + CLK_UART1_HSI + CLK_UART24_HSI + >; - rcc: rcc@50000000 { - compatible = "syscon", "simple-mfd"; - - reg = <0x50000000 0x1000>; - - rcc_clk: rcc-clk@50000000 { - #clock-cells = <1>; - compatible = "st,stm32mp1-rcc-clk"; - - st,clksrc = < CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_HSI - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_HSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 5 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pll@0 { - cfg = < 1 53 0 0 0 1 >; - frac = < 0x810 >; - }; - st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; - }; - st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; - }; - st,pll@3 { - cfg = < 2 78 4 7 9 3>; - }; - st,pkcs = < - CLK_STGEN_HSE - CLK_CKPER_HSI - CLK_USBPHY_PLL2P - CLK_DSI_PLL2Q - >; - }; - }; - --------------------------- other clocks = fixed-clock --------------------------- +========================== + The clock tree is also based on 5 fixed-clock in clocks node used to define the state of associated ST32MP1 oscillators: -- clk-lsi -- clk-lse -- clk-hsi -- clk-hse -- clk-csi + - clk-lsi + - clk-lse + - clk-hsi + - clk-hse + - clk-csi At boot the clock tree initialization will -- enable the oscillator present in device tree -- disable HSI oscillator if the node is absent (always activated by bootrom) + - enable oscillators present in device tree + - disable HSI oscillator if the node is absent (always activated by bootrom) Optional properties : a) for external oscillator: "clk-lse", "clk-hse" - 4 optional fields are managed - - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP) - - "st,digbypass" Configure the bypass mode as full-swing digital signal - (DIGBYP) - - "st,css" Activate the clock security system (HSECSSON, LSECSSON) - - "st,drive" (only for LSE) value of the drive for the oscillator - (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h) - - Example board file: + 4 optional fields are managed + - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP) + - "st,digbypass" configures the bypass mode as full-swing digital + signal (DIGBYP) + - "st,css" activates the clock security system (HSECSSON, LSECSSON) + - "st,drive" (only for LSE) contains the value of the drive for the + oscillator (see LSEDRV_ defined in the file + dt-bindings/clock/stm32mp1-clksrc.h) + Example board file: / { clocks { clk_hse: clk-hse { @@ -200,13 +201,12 @@ a) for external oscillator: "clk-lse", "clk-hse" b) for internal oscillator: "clk-hsi" - internally HSI clock is fixed to 64MHz for STM32MP157 soc - in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc) - So this clock frequency is used to compute the expected HSI_DIV - for the clock tree initialisation - - ex: for HSIDIV = /1 + Internally HSI clock is fixed to 64MHz for STM32MP157 SoC. + In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC + doc). So this clock frequency is used to compute the expected HSI_DIV + for the clock tree initialization. + Example with HSIDIV = /1: / { clocks { clk_hsi: clk-hsi { @@ -216,8 +216,7 @@ b) for internal oscillator: "clk-hsi" }; }; - ex: for HSIDIV = /2 - + Example with HSIDIV = /2 / { clocks { clk_hsi: clk-hsi { @@ -226,3 +225,151 @@ b) for internal oscillator: "clk-hsi" clock-frequency = <32000000>; }; }; + +Example of clock tree initialization +==================================== + +/ { + clocks { + u-boot,dm-pre-reloc; + clk_hse: clk-hse { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + st,digbypass; + }; + + clk_hsi: clk-hsi { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + soc { + + rcc: rcc@50000000 { + u-boot,dm-pre-reloc; + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = ; + + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4Q + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + cfg = < 2 80 0 0 0 PQR(1,0,0) >; + frac = < 0x800 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), + R = 533 (DDR) */ + pll2: st,pll@1 { + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + pll4: st,pll@3 { + cfg = < 3 98 5 7 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; + }; + }; +}; -- 2.7.4