From 903a55e874e91ccd1fb435bea3a675e2eb4257fa Mon Sep 17 00:00:00 2001 From: Romuald JEANNE Date: Wed, 2 Jun 2021 16:45:18 +0200 Subject: [PATCH 2/3] v2.4-stm32mp-r1.1-rc1 --- docs/plat/stm32mp1.rst | 9 ++++++--- drivers/st/clk/stm32mp1_clk.c | 4 ++-- include/drivers/st/stm32mp1_rcc.h | 16 ++++++++++++++++ plat/st/common/stm32mp_crypto_lib.c | 5 ++++- plat/st/stm32mp1/stm32mp1_def.h | 2 ++ plat/st/stm32mp1/stm32mp1_helper.S | 13 +++++++++++++ 6 files changed, 43 insertions(+), 6 deletions(-) diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index fb7afdbbb0..95f4a186f5 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -153,7 +153,10 @@ To build TF-A BL2 with its STM32 header for SD-card boot: .. code:: bash make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - DTB_FILE_NAME=stm32mp157c-ev1.dtb + DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1 + +For other boot devices, you have to replace STM32MP_SDMMC in the previous command +with the desired devive flag. This BL2 is independent of the BL32 used (SP_min or OP-TEE) @@ -204,14 +207,14 @@ __________________ --nt-fw /u-boot-nodtb.bin \ --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ - --hw-config /u-boot.dtb + --hw-config /u-boot.dtb \ --fw-config build/stm32mp1/debug/fdts/fw-config.dtb tools/fiptool/fiptool create --tos-fw /tee-header_v2.bin \ --tos-fw-extra1 /tee-pager_v2.bin \ --tos-fw-extra2 /tee-pageable_v2.bin \ --nt-fw /u-boot-nodtb.bin \ - --hw-config /uboot-nodtb.dtb \ + --hw-config /u-boot.dtb \ --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 00954cb2e8..d074a1568c 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -1853,7 +1853,7 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) (clksrc != (uint32_t)CLK_RTC_DISABLED)) { mmio_clrsetbits_32(address, RCC_BDCR_RTCSRC_MASK, - clksrc << RCC_BDCR_RTCSRC_SHIFT); + (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); mmio_setbits_32(address, RCC_BDCR_RTCCKEN); } diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index feaac43a13..616051e772 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -576,6 +576,22 @@ #define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) #define RCC_FMCCKSELR_FMCSRC_SHIFT 0 +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_USART2RST BIT(14) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_USART2RST BIT(14) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) + /* RCC_USBCKSELR register fields */ #define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) #define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c index de9601d2b8..9582162813 100644 --- a/plat/st/common/stm32mp_crypto_lib.c +++ b/plat/st/common/stm32mp_crypto_lib.c @@ -40,6 +40,7 @@ static void crypto_lib_init(void) { boot_api_context_t *boot_context = (boot_api_context_t *)stm32mp_get_boot_ctx_address(); + int ret; if (!stm32mp_is_auth_supported()) { return; @@ -48,7 +49,9 @@ static void crypto_lib_init(void) auth_ops.verify_signature = boot_context->bootrom_ecdsa_verify_signature; - if (stm32_hash_register() != 0) { + ret = stm32_hash_register(); + if (ret != 0) { + ERROR("HASH init (%d)\n", ret); panic(); } } diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 027dba1bde..326b227842 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -433,6 +433,8 @@ enum ddr_type { #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN +#define DEBUG_UART_RST_REG RCC_APB1RSTSETR +#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST /******************************************************************************* * STM32MP1 ETZPC diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S index bc2d73cebb..315a67f2cf 100644 --- a/plat/st/stm32mp1/stm32mp1_helper.S +++ b/plat/st/stm32mp1/stm32mp1_helper.S @@ -245,6 +245,19 @@ endfunc plat_my_core_pos * --------------------------------------------- */ func plat_crash_console_init + /* Reset UART peripheral */ + ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG) + ldr r2, =DEBUG_UART_RST_BIT + str r2, [r1] +1: + ldr r0, [r1] + ands r0, r2 + beq 1b + str r2, [r1, #4] /* RSTCLR register */ +2: + ldr r0, [r1] + ands r0, r2 + bne 2b /* Enable GPIOs for UART TX */ ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG) ldr r2, [r1] -- 2.17.1