From f539f59331650f195c24a84b2a99f5f8109c0e38 Mon Sep 17 00:00:00 2001 From: Romuald JEANNE Date: Tue, 16 Mar 2021 09:03:16 +0100 Subject: [PATCH 21/22] ARM 5.10.10-stm32mp1-r1 DEVICETREE --- .../bindings/connector/usb-connector.yaml | 24 + .../bindings/cpufreq/stm32-cpufreq.txt | 61 ++ .../devicetree/bindings/dma/st,stm32-dma.yaml | 54 ++ .../bindings/dma/st,stm32-mdma.yaml | 12 +- .../devicetree/bindings/hwlock/hwlock.txt | 27 +- .../bindings/hwlock/st,stm32-hwspinlock.yaml | 4 +- .../devicetree/bindings/i2c/st,stm32-i2c.yaml | 12 + .../iio/adc/sigma-delta-modulator.yaml | 3 + .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 7 +- .../interrupt-controller/st,stm32-exti.yaml | 19 + .../bindings/media/st,stm32-dcmi.yaml | 38 + .../bindings/media/video-interfaces.txt | 2 + .../bindings/mfd/st,stm32-timers.yaml | 6 +- .../bindings/mfd/st,stm32mp1-pwr.txt | 57 ++ .../bindings/perf/stm32-ddr-pmu.yaml | 44 ++ .../bindings/phy/phy-stm32-usbphyc.txt | 73 -- .../bindings/phy/phy-stm32-usbphyc.yaml | 179 +++++ .../bindings/pinctrl/st,stm32-pinctrl.yaml | 8 + .../bindings/remoteproc/rproc-srm.txt | 58 ++ .../bindings/remoteproc/st,stm32-rproc.yaml | 51 +- .../devicetree/bindings/serial/rs485.yaml | 16 + .../bindings/serial/st,stm32-uart.yaml | 75 +- .../bindings/soc/stm32/stm32_hdp.txt | 39 + .../bindings/sound/st,stm32-adfsdm.txt | 63 -- .../bindings/sound/st,stm32-i2s.yaml | 4 + .../bindings/sound/st,stm32-sai.txt | 107 --- .../bindings/sound/st,stm32-sai.yaml | 200 +++++ .../devicetree/bindings/usb/dwc2.yaml | 4 + .../devicetree/bindings/usb/generic-ehci.yaml | 5 + .../devicetree/bindings/usb/st,stusb160x.yaml | 87 +++ arch/arm/boot/dts/Makefile | 48 ++ arch/arm/boot/dts/stm32429i-eval.dts | 1 + arch/arm/boot/dts/stm32f746.dtsi | 4 + arch/arm/boot/dts/stm32h743.dtsi | 4 + .../boot/dts/stm32mp15-m4-srm-pinctrl.dtsi | 524 +++++++++++++ arch/arm/boot/dts/stm32mp15-m4-srm.dtsi | 442 +++++++++++ arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 157 ++++ arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 228 +++++- arch/arm/boot/dts/stm32mp151.dtsi | 627 +++++++++++----- arch/arm/boot/dts/stm32mp153.dtsi | 8 +- arch/arm/boot/dts/stm32mp157.dtsi | 3 +- arch/arm/boot/dts/stm32mp157a-dk1.dts | 2 +- arch/arm/boot/dts/stm32mp157a-ed1.dts | 32 + arch/arm/boot/dts/stm32mp157a-ev1.dts | 88 +++ .../boot/dts/stm32mp157c-dk2-a7-examples.dts | 60 ++ .../boot/dts/stm32mp157c-dk2-m4-examples.dts | 129 ++++ arch/arm/boot/dts/stm32mp157c-dk2.dts | 68 +- arch/arm/boot/dts/stm32mp157c-ed1.dts | 368 +--------- .../boot/dts/stm32mp157c-ev1-a7-examples.dts | 57 ++ .../boot/dts/stm32mp157c-ev1-m4-examples.dts | 146 ++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 330 +-------- arch/arm/boot/dts/stm32mp157d-dk1.dts | 28 + arch/arm/boot/dts/stm32mp157d-ed1.dts | 33 + arch/arm/boot/dts/stm32mp157d-ev1.dts | 88 +++ .../boot/dts/stm32mp157f-dk2-a7-examples.dts | 60 ++ .../boot/dts/stm32mp157f-dk2-m4-examples.dts | 129 ++++ arch/arm/boot/dts/stm32mp157f-dk2.dts | 157 ++++ arch/arm/boot/dts/stm32mp157f-ed1.dts | 37 + .../boot/dts/stm32mp157f-ev1-a7-examples.dts | 57 ++ .../boot/dts/stm32mp157f-ev1-m4-examples.dts | 146 ++++ arch/arm/boot/dts/stm32mp157f-ev1.dts | 89 +++ arch/arm/boot/dts/stm32mp15xa.dtsi | 13 + arch/arm/boot/dts/stm32mp15xc.dtsi | 6 +- arch/arm/boot/dts/stm32mp15xd.dtsi | 42 ++ arch/arm/boot/dts/stm32mp15xf.dtsi | 20 + arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 122 +++- arch/arm/boot/dts/stm32mp15xx-edx.dtsi | 413 +++++++++++ arch/arm/boot/dts/stm32mp15xx-evx.dtsi | 686 ++++++++++++++++++ 68 files changed, 5596 insertions(+), 1195 deletions(-) create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml create mode 100644 Documentation/devicetree/bindings/remoteproc/rproc-srm.txt create mode 100644 Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt delete mode 100644 Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt delete mode 100644 Documentation/devicetree/bindings/sound/st,stm32-sai.txt create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-sai.yaml create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml create mode 100644 arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15-m4-srm.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi create mode 100644 arch/arm/boot/dts/stm32mp157a-ed1.dts create mode 100644 arch/arm/boot/dts/stm32mp157a-ev1.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157d-dk1.dts create mode 100644 arch/arm/boot/dts/stm32mp157d-ed1.dts create mode 100644 arch/arm/boot/dts/stm32mp157d-ev1.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-ed1.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1.dts create mode 100644 arch/arm/boot/dts/stm32mp15xa.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xd.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xf.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-edx.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-evx.dtsi diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml index 728f82db073d..ccf6eb22ba05 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -93,6 +93,24 @@ properties: - device - dual + typec-power-opmode: + description: Determines the power operation mode that the Type C connector + will support and will advertise through CC pins when it has no power + delivery support. + - "default" corresponds to default USB voltage and current defined by the + USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and + 5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane + operation respectively. + - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB + Type-C Cable and Connector specification, when Power Delivery is not + supported. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - default + - 1.5A + - 3.0A + # The following are optional properties for "usb-c-connector" with power # delivery support. source-pdos: @@ -173,6 +191,12 @@ allOf: type: const: micro +anyOf: + - not: + required: + - typec-power-opmode + - new-source-frs-typec-current + additionalProperties: true examples: diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt new file mode 100644 index 000000000000..1292eb2612a0 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt @@ -0,0 +1,61 @@ +STM32 CPUFreq and OPP bindings +============================== + +STM32 CPUFreq driver needs to read chip information from the SoC to list +available OPPs. Then it depends on cpufreq-dt bindings. + +Required properties: +-------------------- +- clocks: Phandle to the cpu clock "cpu". +- clocks-name: Should contain "cpu". +- nvmem-cells: Phandle to nvmem cell that contains "part_number". +- nvmem-cell-names: Must be "part_number". +- operating-points-v2: Phandle to operating points table. See ../power/opp.txt + for more details. + +Optional properties: +-------------------- +See cpufreq-dt.txt for optional properties. + +Examples: +--------- + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&rcc CK_MPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&rcc CK_MPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 2a5325f480f6..99351fe0fa17 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -40,6 +40,21 @@ description: | 0x0: FIFO mode with threshold selectable with bit 0-1 0x1: Direct mode: each DMA request immediately initiates a transfer from/to the memory, FIFO is bypassed. + -bit 4: alternative DMA request/acknowledge protocol + 0x0: Use standard DMA ACK management, where ACK signal is maintained + up to the removal of request and transfer completion + 0x1: Use alternative DMA ACK management, where ACK de-assertion does + not wait for the de-assertion of the REQuest, ACK is only managed + by transfer completion. This must only be used on channels + managing transfers for STM32 USART/UART. + -bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE. + Order is given by those 2 bits starting at 0. + Valid only whether Intermediate M2M transfer is set. + For cyclic, whether Intermediate M2M transfer is chosen, any value can be set: + SRAM buffer size will rely on period size and not on this DT value. + -bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA + 0: MDMA not used to generate an intermediate M2M transfer + 1: MDMA used to generate an intermediate M2M transfer. maintainers: @@ -75,6 +90,35 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer + dmas: + description: A list of eight dma specifiers, one for each entry in dma-names. + Refer to stm32-mdma.yaml for more details. + items: + - description: DMA channel 0 connected to the MDMA channel specified + - description: DMA channel 1 connected to the MDMA channel specified + - description: DMA channel 2 connected to the MDMA channel specified + - description: DMA channel 3 connected to the MDMA channel specified + - description: DMA channel 4 connected to the MDMA channel specified + - description: DMA channel 5 connected to the MDMA channel specified + - description: DMA channel 6 connected to the MDMA channel specified + - description: DMA channel 7 connected to the MDMA channel specified + + dma-names: + description: Represents each STM32 DMA channel connected to a STM32 MDMA one. + items: + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + + memory-region: + description: Phandle to a node describing memory to be used for M2M intermediate transfer + between DMA and MDMA. + required: - compatible - reg @@ -104,6 +148,16 @@ examples: st,mem2mem; resets = <&rcc 150>; dma-requests = <8>; + dmas = <&mdma1 8 0x3 0x1200000a 0x40026408 0x00000020 1>, + <&mdma1 9 0x3 0x1200000a 0x40026408 0x00000800 1>, + <&mdma1 10 0x3 0x1200000a 0x40026408 0x00200000 1>, + <&mdma1 11 0x3 0x1200000a 0x40026408 0x08000000 1>, + <&mdma1 12 0x3 0x1200000a 0x4002640C 0x00000020 1>, + <&mdma1 13 0x3 0x1200000a 0x4002640C 0x00000800 1>, + <&mdma1 14 0x3 0x1200000a 0x4002640C 0x00200000 1>, + <&mdma1 15 0x3 0x1200000a 0x4002640C 0x08000000 1>; + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; + memory-region = <&sram_dmapool>; }; ... diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml index c30be840be1c..c4bb58014374 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml @@ -10,8 +10,8 @@ description: | The STM32 MDMA is a general-purpose direct memory access controller capable of supporting 64 independent DMA channels with 256 HW requests. DMA clients connected to the STM32 MDMA controller must use the format - described in the dma.txt file, using a five-cell specifier for each channel: - a phandle to the MDMA controller plus the following five integer cells: + described in the dma.txt file, using a six-cell specifier for each channel: + a phandle to the MDMA controller plus the following six integer cells: 1. The request line number 2. The priority level 0x0: Low @@ -48,6 +48,10 @@ description: | if no HW ack signal is used by the MDMA client 5. A 32bit mask specifying the value to be written to acknowledge the request if no HW ack signal is used by the MDMA client + 6. A bitfield value specifying if the MDMA client wants to generate M2M transfer + with HW trigger (1) or not (0). This bitfield should be only enabled for + M2M transfer triggered by STM32 DMA client. The memory devices involved in this + kind of transfer are SRAM and DDR. maintainers: - Amelie Delaunay @@ -57,7 +61,7 @@ allOf: properties: "#dma-cells": - const: 5 + const: 6 compatible: const: st,stm32h7-mdma @@ -97,7 +101,7 @@ examples: interrupts = <122>; clocks = <&timer_clk>; resets = <&rcc 992>; - #dma-cells = <5>; + #dma-cells = <6>; dma-channels = <16>; dma-requests = <32>; st,ahb-addr-masks = <0x20000000>, <0x00000000>; diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt index 085d1f5c916a..e98088a409ba 100644 --- a/Documentation/devicetree/bindings/hwlock/hwlock.txt +++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt @@ -13,7 +13,7 @@ hwlock providers: Required properties: - #hwlock-cells: Specifies the number of cells needed to represent a - specific lock. + specific lock. Shall be 1 or 2 (see hwlocks below). hwlock users: ============= @@ -27,6 +27,11 @@ Required properties: #hwlock-cells. The list can have just a single hwlock or multiple hwlocks, with each hwlock represented by a phandle and a corresponding args specifier. + If #hwlock-cells is 1, all of the locks are exclusive + (cannot be used by several users). + If #hwlock-cells is 2, the value of the second cell + defines whether the lock is for exclusive usage (0) or + shared (1) i.e. can be used by several users. Optional properties: - hwlock-names: List of hwlock name strings defined in the same order @@ -46,14 +51,22 @@ of length 1. ... }; -2. Example of a node using multiple specific hwlocks: +2. Example of nodes using multiple and shared specific hwlocks: -The following example has a node requesting two hwlocks, a hwlock within -the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another -hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2. +The following example has a nodeA requesting two hwlocks: +- an exclusive one (#hwlock-cells = 1) within the hwlock device node 'hwlock1' +- a shared one (#hwlock-cells = 2, second cell = 1) within the hwlock device + node 'hwlock2'. +The shared lock is also be used by nodeB. - node { + nodeA { ... - hwlocks = <&hwlock1 2>, <&hwlock2 0 3>; + hwlocks = <&hwlock1 2>, <&hwlock2 0 1>; ... }; + + nodeB { + ... + hwlocks = <&hwlock2 0 1>; + ... + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml index 47cf9c8d97e9..539a1dc052b7 100644 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml @@ -12,7 +12,7 @@ maintainers: properties: "#hwlock-cells": - const: 1 + const: 2 compatible: const: st,stm32-hwspinlock @@ -41,7 +41,7 @@ examples: #include hwspinlock@4c000000 { compatible = "st,stm32-hwspinlock"; - #hwlock-cells = <1>; + #hwlock-cells = <2>; reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hsem"; diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..9f0b098e899a 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -20,6 +20,13 @@ allOf: - st,stm32mp15-i2c then: properties: + i2c-analog-filter: true + + i2c-digital-filter: true + + i2c-digital-filter-width-ns: + default: 0 + i2c-scl-rising-time-ns: default: 25 @@ -36,6 +43,11 @@ allOf: minItems: 3 maxItems: 3 + st,smbus-alert: + description: Enable the SMBus-Alert via SMBA pin, note SMBA pin + must also be configured via pinctrl. + type: boolean + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml index a390343d0c2a..bf5d71fb60da 100644 --- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml +++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml @@ -21,6 +21,9 @@ properties: '#io-channel-cells': const: 0 + vref-supply: + description: Phandle to the vref input analog reference voltage. + required: - compatible - '#io-channel-cells' diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index d61bc011e820..6f2398cdc82d 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -199,8 +199,6 @@ patternProperties: description: From common IIO binding. Used to pipe external sigma delta modulator or internal ADC output to DFSDM channel. - This is not required for "st,stm32-dfsdm-pdm" compatibility as - PDM microphone is binded in Audio DT node. required: - io-channels @@ -235,6 +233,10 @@ patternProperties: description: child node properties: + compatible: + enum: + - st,stm32h7-dfsdm-dai + "#sound-dai-cells": const: 0 @@ -244,6 +246,7 @@ patternProperties: modulator or internal ADC output to DFSDM channel. required: + - compatible - "#sound-dai-cells" - io-channels diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index 2a5b29567926..8e4093cbc9b5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -39,6 +39,25 @@ properties: description: Interrupts references to primary interrupt controller +patternProperties: + '^exti[0-9a-f]*$': + type: object + properties: + interrupt-controller: true + "#interrupt-cells": + const: 2 + + st,irq-number: + description: + Interrupt number mapped on the parent. + $ref: "/schemas/types.yaml#/definitions/uint32" + + required: + - "#interrupt-cells" + - interrupt-controller + - st,irq-number + - interrupt-parent + required: - "#interrupt-cells" - compatible diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 3fe778cb5cc3..c18574bb3e81 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -44,6 +44,43 @@ properties: bindings defined in Documentation/devicetree/bindings/media/video-interfaces.txt. + properties: + endpoint: + type: object + + properties: + bus-type: + enum: [5, 6] + default: 5 + + bus-width: + enum: [8, 10, 12, 14] + default: 8 + + remote-endpoint: true + + allOf: + - if: + properties: + bus-type: + const: 6 + + then: + properties: + hsync-active: false + vsync-active: false + bus-width: + enum: [8] + + required: + - remote-endpoint + - bus-type + - pclk-sample + + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg @@ -75,6 +112,7 @@ examples: port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index 3920f25a9123..5d63c4de8783 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -513,6 +513,8 @@ Optional endpoint properties as 0 (normal). This property is valid for serial busses only. - strobe: Whether the clock signal is used as clock (0) or strobe (1). Used with CCP2, for instance. +- pclk-max-frequency: maximum pixel clock frequency admissible by video + host interface. Example ------- diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f212fc6e1661..0f16c8864a87 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -131,7 +131,7 @@ additionalProperties: false examples: - | #include - timers2: timers@40000000 { + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; @@ -149,9 +149,9 @@ examples: #pwm-cells = <3>; st,breakinput = <0 1 5>; }; - timer@0 { + timer@1 { compatible = "st,stm32-timer-trigger"; - reg = <0>; + reg = <1>; }; counter { compatible = "st,stm32-timer-counter"; diff --git a/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt new file mode 100644 index 000000000000..eb622387bb65 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt @@ -0,0 +1,57 @@ +STMicroelectronics STM32MP1 Power Management Controller +======================================================= + +The PWR IP is responsible for handling the power related resources such as +clocks, power supplies and resets. It provides 6 wake-up pins that are handled +by an interrupt-controller. Wake-up pin can be used to wake-up from STANDBY SoC state. + +Required properties: +- compatible should be: "st,stm32mp1-pwr" +- reg: should be register base and length as documented in the + datasheet +- interrupts: contains the reference to the gic wake-up pin interrupt +- interrupt-controller; Enable interrupt controller for wake-up pins. +- #interrupt-cells = <3> +- wakeup-gpios: contains a list of GPIO spec describing each wake-up pin. + +Optional Properties: +- pwr-supply: main soc power supply + +Interrupt consumers have to specify 3 cells: + - cell 1: wake-up pin id from 0 to 5 + - cell 2: IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_RISING + - cell 3: Pull config: 0 = No Pull, 1=Pull Up, 2=Pull Down + + +Example: + + pwr: pwr@50001000 { + compatible = "st,stm32mp1-pwr", "simple-mfd"; + reg = <0x50001000 0x400>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + wakeup-gpios = <&gpioa 0 0>, <&gpioa 2 0>, + <&gpioc 13 0>, <&gpioi 8 0>, + <&gpioi 11 0>, <&gpioc 1 0>; + + pwr-supply = <&vdd>; + }; + + +Example of interrupt user: +gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@4 { + label = "WakeUp4"; + linux,code = ; + interrupt-parent = <&pwr>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING 1>; + wakeup-source; + }; +}; + diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml new file mode 100644 index 000000000000..085f2886e580 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/stm32-ddr-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Gerald Baeza + +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) bindings + +properties: + compatible: + const: st,stm32-ddr-pmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + ddrperfm: perf@5a007000 { + compatible = "st,stm32-ddr-pmu"; + reg = <0x5a007000 0x400>; + clocks = <&rcc DDRPERFM>; + resets = <&rcc DDRPERFM_R>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt deleted file mode 100644 index 725ae71ae653..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt +++ /dev/null @@ -1,73 +0,0 @@ -STMicroelectronics STM32 USB HS PHY controller - -The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI -switch. It controls PHY configuration and status, and the UTMI+ switch that -selects either OTG or HOST controller for the second PHY port. It also sets -PLL configuration. - -USBPHYC - |_ PLL - | - |_ PHY port#1 _________________ HOST controller - | _ | - | / 1|________________| - |_ PHY port#2 ----| |________________ - | \_0| | - |_ UTMI switch_______| OTG controller - - -Phy provider node -================= - -Required properties: -- compatible: must be "st,stm32mp1-usbphyc" -- reg: address and length of the usb phy control register set -- clocks: phandle + clock specifier for the PLL phy clock -- #address-cells: number of address cells for phys sub-nodes, must be <1> -- #size-cells: number of size cells for phys sub-nodes, must be <0> - -Optional properties: -- assigned-clocks: phandle + clock specifier for the PLL phy clock -- assigned-clock-parents: the PLL phy clock parent -- resets: phandle + reset specifier - -Required nodes: one sub-node per port the controller provides. - -Phy sub-nodes -============== - -Required properties: -- reg: phy port index -- phy-supply: phandle to the regulator providing 3V3 power to the PHY, - see phy-bindings.txt in the same directory. -- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY -- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY -- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY - port#1 and must be <1> for PHY port#2, to select USB controller - - -Example: - usbphyc: usb-phy@5a006000 { - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc_clk USBPHY_K>; - resets = <&rcc_rst USBPHY_R>; - #address-cells = <1>; - #size-cells = <0>; - - usbphyc_port0: usb-phy@0 { - reg = <0>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <0>; - }; - - usbphyc_port1: usb-phy@1 { - reg = <1>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml new file mode 100644 index 000000000000..35460bb9f513 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 USB HS PHY controller binding + +description: + + The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI + switch. It controls PHY configuration and status, and the UTMI+ switch that + selects either OTG or HOST controller for the second PHY port. It also sets + PLL configuration. + + USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | __ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + +maintainers: + - Amelie Delaunay + +properties: + compatible: + enum: + - st,stm32mp1-usbphyc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + vdda1v1-supply: + description: regulator providing 1V1 power supply to the PLL block + + vdda1v8-supply: + description: regulator providing 1V8 power supply to the PLL block + + '#clock-cells': + description: number of clock cells for ck_usbo_48m consumer + const: 0 + +#Required child nodes: + +patternProperties: + "^usb-phy@[0|1]$": + type: object + description: + Each port the controller provides must be represented as a sub-node. + + properties: + reg: + description: phy port index. + maxItems: 1 + + phy-supply: + description: regulator providing 3V3 power supply to the PHY. + + vbus-supply: + description: regulator providing 5V Vbus to the USB connector. + + st,phy-tuning: + $ref: /schemas/types.yaml#definitions/phandle + description: + It can be necessary to adjust the PHY settings to compensate parasitics, which can be due + to USB connector/receptacle, routing, ESD protection component,... Here is the list of + all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- + Speed, LS for Low-Speed) + * st,current-boost, <1> current boosting of 1mA + <2> current boosting of 2mA + * st,no-lsfs-fb-cap, disables the LS/FS feedback capacitor + * st,hs-slew-ctrl, slows the HS driver slew rate by 10% + * st,hs-dc-level, <0> decreases the HS driver DC level by 5 to 7mV + <1> increases the HS driver DC level by 5 to 7mV + <2> increases the HS driver DC level by 10 to 14mV + * st,fs-rftime-tuning, enables the FS rise/fall tuning option + * st,hs-rftime-reduction, enables the HS rise/fall reduction feature + * st,hs-current-trim, controls HS driver current trimming for choke + * st,hs-impedance-trim, controls HS driver impedance tuning for choke + * st,squelch-level, adjusts the squelch DC threshold value + * st,hs-rx-gain-eq, enables the HS Rx gain equalizer + * st,hs-rx-offset, adjusts the HS Rx offset + * st,no-hs-ftime-ctrl, disables the HS fall time control of single ended signals + during pre-emphasis + * st,no-lsfs-sc, disables the short circuit protection in LS/FS driver + * st,hs-tx-staggering, enables the basic staggering in HS Tx mode + + '#phy-cells': + enum: [ 0x0, 0x1 ] + + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + '#phy-cells': + const: 0 + else: + properties: + '#phy-cells': + const: 1 + description: + The value is used to select UTMI switch output. + 0 for OTG controller and 1 for Host controller. + + required: + - reg + - phy-supply + - '#phy-cells' + +required: + - compatible + - reg + - clocks + - '#address-cells' + - '#size-cells' + - vdda1v1-supply + - vdda1v8-supply + - '#clock-cells' + - usb-phy@0 + - usb-phy@1 + +examples: + - | + #include + #include + + usb_phy_tuning: usb-phy-tuning { + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; + + usbphyc: usbphyc@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc_clk USBPHY_K>; + resets = <&rcc_rst USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + #phy-cells = <0>; + st,phy-tuning = <&usb_phy_tuning>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + #phy-cells = <1>; + st,phy-tuning = <&usb_phy_tuning>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 72877544ca78..f67e2e7079f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -139,9 +139,13 @@ patternProperties: * ... * 16 : Alternate Function 15 * 17 : Analog + * 18 : Reserved To simplify the usage, macro is available to generate "pinmux" field. This macro is available here: - include/dt-bindings/pinctrl/stm32-pinfunc.h + Setting the pinmux's function to the Reserved (RSVD) value is used to inform + the driver that it shall not apply the mux setting. This can be used to + reserve some pins, for example to a co-processor not running Linux. Some examples of using macro: /* GPIO A9 set as alernate function 2 */ ... { @@ -155,6 +159,10 @@ patternProperties: ... { pinmux = ; }; + /* GPIO A9 reserved for co-processor */ + ... { + pinmux = ; + }; bias-disable: type: boolean diff --git a/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt new file mode 100644 index 000000000000..baa6e8e135e1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt @@ -0,0 +1,58 @@ +Remoteproc System Resource Manager +---------------------------------- + +The remoteproc SRM (System Resource Manager) handles resources allocated +to remote processors. +This makes it possible for remote proc to reserve and initialize system +resources for a peripheral assigned to a coprocessor. + +The devices are grouped in a core node + +Core +==== +Required properties: +- compatible: should be "rproc-srm-core" + +Dev +=== +Required properties: +- compatible: should be "rproc-srm-dev" + +Optional properties: +- reg: register base address and length +- clocks: clocks required by the coprocessor +- clock-names: see clock-bindings.txt +- pinctrl-0: pins configurations required by the coprocessor + The SRM reserves the pins for the coprocessor, which prevents the local + processor to use them. +- pinctrl-names: must be "default". +- x-supply: power supplies required by the coprocessor +- interrupts: external interrupts configurations required by the coprocessor. + This is optional since the configuration is done by the coprocessor. + When defined, the SRM (over)writes the configuration which allows the + interrupt controller to check for configuration conflicts. +- interrupt-parent: see interrupts.txt +- interrupt-names: see interrupts.txt + +Example: + system_resources { + compatible = "rproc-srm-core"; + + mmc0: sdhci@09060000 { + compatible = "rproc-srm-dev"; + reg = <0x09060000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&m4_pinctrl_mmc0>; + clock-names = "mmc", "icn"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; + vdda-supply = <&vdda>; + }; + + button { + compatible = "rproc-srm-dev"; + interrupt-parent = <&gpioa>; + interrupts = <5 1>; + interrupt-names = "gpio_key"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 4ffa25268fcc..7180d545ab80 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -16,7 +16,9 @@ maintainers: properties: compatible: - const: st,stm32mp1-m4 + enum: + - st,stm32mp1-m4 + - st,stm32mp1-m4_optee reg: description: @@ -25,24 +27,13 @@ properties: maxItems: 3 resets: - maxItems: 1 - - st,syscfg-holdboot: - description: remote processor reset hold boot - - Phandle of syscon block. - - The offset of the hold boot setting register. - - The field mask of the hold boot. - $ref: "/schemas/types.yaml#/definitions/phandle-array" - maxItems: 1 + maxItems: 2 - st,syscfg-tz: - description: - Reference to the system configuration which holds the RCC trust zone mode - - Phandle of syscon block. - - The offset of the RCC trust zone mode register. - - The field mask of the RCC trust zone mode. - $ref: "/schemas/types.yaml#/definitions/phandle-array" - maxItems: 1 + reset-names: + items: + - const: mcu_rst + - const: hold_boot + maxItems: 2 interrupts: description: Should contain the WWDG1 watchdog reset interrupt @@ -91,9 +82,19 @@ properties: $ref: "/schemas/types.yaml#/definitions/phandle-array" description: | Reference to the system configuration which holds the remote - 1st cell: phandle to syscon block - 2nd cell: register offset containing the deep sleep setting - 3rd cell: register bitmask for the deep sleep bit + maxItems: 1 + + st,syscfg-m4-state: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: | + Reference to the tamp register which exposes the Cortex-M4 state. + maxItems: 1 + + st,syscfg-rsc-tbl: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: | + Reference to the tamp register which references the Cortex-M4 + resource table address. maxItems: 1 st,auto-boot: @@ -107,7 +108,6 @@ required: - reg - resets - st,syscfg-holdboot - - st,syscfg-tz additionalProperties: false @@ -119,9 +119,12 @@ examples: reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; - resets = <&rcc MCU_R>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; }; ... diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 0c9fa694f85c..a2ac9de2d85e 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -29,6 +29,22 @@ properties: default: 0 maximum: 1000 + rs485-rts-delay-ns: + description: This property is used to define delays lower than 1ms. + prop-encoded-array + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + items: + - description: Delay between rts signal and beginning of data sent in + nanoseconds. It corresponds to the delay before sending data. + default: 0 + maximum: 1000 + - description: Delay between end of data sent and rts signal in nanoseconds. + It corresponds to the delay after sending data and actual release + of the line. + default: 0 + maximum: 1000 + rs485-rts-active-low: description: drive RTS low when sending (default is high). $ref: /schemas/types.yaml#/definitions/flag diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 06d5f251ec88..d2df06f4d8f9 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -9,9 +9,6 @@ maintainers: title: STMicroelectronics STM32 USART bindings -allOf: - - $ref: rs485.yaml - properties: compatible: enum: @@ -50,26 +47,54 @@ properties: minItems: 1 maxItems: 2 - cts-gpios: - maxItems: 1 - - rts-gpios: - maxItems: 1 +# cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts' +# or 'st,hw-flow-ctrl' (deprecated) for making use of any gpio pins for flow +# control instead of dedicated pins. +# +# It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or +# 'st,hw-flow-ctrl' (deprecated) properties cannot co-exist in a design. + cts-gpios: true + rts-gpios: true wakeup-source: true rs485-rts-delay: true + rs485-rts-delay-ns: true rs485-rts-active-low: true linux,rs485-enabled-at-boot-time: true rs485-rx-during-tx: true -if: - required: - - st,hw-flow-ctrl -then: - properties: - cts-gpios: false - rts-gpios: false + st,rx-fifo-threshold-bytes: + description: RX FIFO threshold configuration in bytes. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8, 12, 14, 16] + default: 8 + + st,tx-fifo-threshold-bytes: + description: TX FIFO threshold configuration in bytes. + If value is set to 1, TX FIFO threshold is disabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8, 12, 14, 16] + default: 8 + +allOf: + - $ref: rs485.yaml + + - if: + required: + - st,hw-flow-ctrl + then: + properties: + cts-gpios: false + rts-gpios: false + + - if: + required: + - st,stm32h7-uart + then: + properties: + st,rx-fifo-threshold-bytes: false + st,tx-fifo-threshold-bytes: false required: - compatible @@ -82,6 +107,26 @@ additionalProperties: false examples: - | #include + + usart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&clk_pclk1>; + st,hw-flow-ctrl; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>; + }; + usart1: serial@40011000 { compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; diff --git a/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt new file mode 100644 index 000000000000..e2bd82f4980e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt @@ -0,0 +1,39 @@ +STM32 - STM32MP1- HDP Pin configuration for STM32MP1 +======================================================= + +The Hardware Debug Port (HDP) allows the observation of internal signals. By using multiplexers, +up to 16 signals for each of 8-bit output can be observed. + +Required Properties: + + - compatible: Must be "st,stm32mp1-hdp" + - muxing-hdp: Indicates for each HDP pins selected which HDP output among the 16 available signals you want + +For each HDP pins you can select one of 16 signals which will be described in file : include/dt-bindings/soc/stm32-hdp.h + +Example +------- + +In common dtsi file: + +hdp: hdp@5002a000 { + compatible = "st,stm32mp1-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + clock-names = "hdp"; +}; + +In board-specific file: + +In this example I've selected HDP0, HDP6 and HDP7, and for HDP0 the output signal is HDP0_GPOVAL_0, +for HDP6 is HDP6_GPOVAL_6, and for HDP7 is HDP7_GPOVAL_7. + +&hdp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>; + pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>; + + muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) | + STM32_HDP(6, HDP6_GPOVAL_6) | + STM32_HDP(7, HDP7_GPOVAL_7))>; +}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt deleted file mode 100644 index 864f5b00b031..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt +++ /dev/null @@ -1,63 +0,0 @@ -STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM) - -The DFSDM allows PDM microphones capture through SPI interface. The Audio -interface is seems as a sub block of the DFSDM device. -For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt - -Required properties: - - compatible: "st,stm32h7-dfsdm-dai". - - - #sound-dai-cells : Must be equal to 0 - - - io-channels : phandle to iio dfsdm instance node. - -Example of a sound card using audio DFSDM node. - - sound_card { - compatible = "audio-graph-card"; - - dais = <&cpu_port>; - }; - - dfsdm: dfsdm@40017000 { - compatible = "st,stm32h7-dfsdm"; - reg = <0x40017000 0x400>; - clocks = <&rcc DFSDM1_CK>; - clock-names = "dfsdm"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dfsdm_adc0: filter@0 { - compatible = "st,stm32-dfsdm-dmic"; - reg = <0>; - interrupts = <110>; - dmas = <&dmamux1 101 0x400 0x00>; - dma-names = "rx"; - st,adc-channels = <1>; - st,adc-channel-names = "dmic0"; - st,adc-channel-types = "SPI_R"; - st,adc-channel-clk-src = "CLKOUT"; - st,filter-order = <5>; - - dfsdm_dai0: dfsdm-dai { - compatible = "st,stm32h7-dfsdm-dai"; - #sound-dai-cells = <0>; - io-channels = <&dfsdm_adc0 0>; - cpu_port: port { - dfsdm_endpoint: endpoint { - remote-endpoint = <&dmic0_endpoint>; - }; - }; - }; - }; - - dmic0: dmic@0 { - compatible = "dmic-codec"; - #sound-dai-cells = <0>; - port { - dmic0_endpoint: endpoint { - remote-endpoint = <&dfsdm_endpoint>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index f32410890589..6feb5a09c184 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -54,6 +54,10 @@ properties: resets: maxItems: 1 + "#clock-cells": + description: Configure the I2S device as MCLK clock provider. + const: 0 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt deleted file mode 100644 index c42b91e525fa..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt +++ /dev/null @@ -1,107 +0,0 @@ -STMicroelectronics STM32 Serial Audio Interface (SAI). - -The SAI interface (Serial Audio Interface) offers a wide set of audio protocols -as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97. -The SAI contains two independent audio sub-blocks. Each sub-block has -its own clock generator and I/O lines controller. - -Required properties: - - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai" - - reg: Base address and size of SAI common register set. - - clocks: Must contain phandle and clock specifier pairs for each entry - in clock-names. - - clock-names: Must contain "pclk" "x8k" and "x11k" - "pclk": Clock which feeds the peripheral bus interface. - Mandatory for "st,stm32h7-sai" compatible. - Not used for "st,stm32f4-sai" compatible. - "x8k": SAI parent clock for sampling rates multiple of 8kHz. - "x11k": SAI parent clock for sampling rates multiple of 11.025kHz. - - interrupts: cpu DAI interrupt line shared by SAI sub-blocks - -Optional properties: - - resets: Reference to a reset controller asserting the SAI - -SAI subnodes: -Two subnodes corresponding to SAI sub-block instances A et B can be defined. -Subnode can be omitted for unsused sub-block. - -SAI subnodes required properties: - - compatible: Should be "st,stm32-sai-sub-a" or "st,stm32-sai-sub-b" - for SAI sub-block A or B respectively. - - reg: Base address and size of SAI sub-block register set. - - clocks: Must contain one phandle and clock specifier pair - for sai_ck which feeds the internal clock generator. - If the SAI shares a master clock, with another SAI set as MCLK - clock provider, SAI provider phandle must be specified here. - - clock-names: Must contain "sai_ck". - Must also contain "MCLK", if SAI shares a master clock, - with a SAI set as MCLK clock provider. - - dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml - - dma-names: identifier string for each DMA request line - "tx": if sai sub-block is configured as playback DAI - "rx": if sai sub-block is configured as capture DAI - - pinctrl-names: should contain only value "default" - - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml - -SAI subnodes Optional properties: - - st,sync: specify synchronization mode. - By default SAI sub-block is in asynchronous mode. - This property sets SAI sub-block as slave of another SAI sub-block. - Must contain the phandle and index of the sai sub-block providing - the synchronization. - - st,iec60958: support S/PDIF IEC6958 protocol for playback - IEC60958 protocol is not available for capture. - By default, custom protocol is assumed, meaning that protocol is - configured according to protocol defined in related DAI link node, - such as i2s, left justified, right justified, dsp and pdm protocols. - Note: ac97 protocol is not supported by SAI driver - - #clock-cells: should be 0. This property must be present if the SAI device - is a master clock provider, according to clocks bindings, described in - Documentation/devicetree/bindings/clock/clock-bindings.txt. - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -sound_card { - compatible = "audio-graph-card"; - dais = <&sai1b_port>; -}; - -sai1: sai1@40015800 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40015800 0x400>; - reg = <0x40015800 0x4>; - clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; - clock-names = "pclk", "x8k", "x11k"; - interrupts = <87>; - - sai1a: audio-controller@40015804 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1C>; - clocks = <&rcc SAI1_CK>; - clock-names = "sai_ck"; - dmas = <&dmamux1 1 87 0x400 0x0>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1a>; - - sai1b_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - format = "i2s"; - }; - }; - }; -}; - -audio-codec { - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml new file mode 100644 index 000000000000..6ad48c7681c1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -0,0 +1,200 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Serial Audio Interface (SAI) + +maintainers: + - Olivier Moysan + +description: + The SAI interface (Serial Audio Interface) offers a wide set of audio + protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97. + The SAI contains two independent audio sub-blocks. Each sub-block has + its own clock generator and I/O lines controller. + +properties: + compatible: + enum: + - st,stm32f4-sai + - st,stm32h7-sai + + reg: + items: + - description: Base address and size of SAI common register set. + - description: Base address and size of SAI identification register set. + minItems: 1 + maxItems: 2 + + ranges: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + +patternProperties: + "^audio-controller@[0-9a-f]+$": + type: object + description: + Two subnodes corresponding to SAI sub-block instances A et B + can be defined. Subnode can be omitted for unsused sub-block. + + properties: + compatible: + description: Compatible for SAI sub-block A or B. + pattern: "st,stm32-sai-sub-[ab]" + + "#sound-dai-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + items: + - description: sai_ck clock feeding the internal clock generator. + - description: MCLK clock from a SAI set as master clock provider. + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: sai_ck + - const: MCLK + minItems: 1 + maxItems: 2 + + dmas: + maxItems: 1 + + dma-names: + description: | + rx: SAI sub-block is configured as a capture DAI. + tx: SAI sub-block is configured as a playback DAI. + enum: [ rx, tx ] + + st,sync: + description: + Configure the SAI sub-block as slave of another SAI sub-block. + By default SAI sub-block is in asynchronous mode. + Must contain the phandle and index of the SAI sub-block providing + the synchronization. + allOf: + - $ref: /schemas/types.yaml#definitions/phandle-array + - maxItems: 1 + + st,iec60958: + description: + If set, support S/PDIF IEC6958 protocol for playback. + IEC60958 protocol is not available for capture. + By default, custom protocol is assumed, meaning that protocol is + configured according to protocol defined in related DAI link node, + such as i2s, left justified, right justified, dsp and pdm protocols. + allOf: + - $ref: /schemas/types.yaml#definitions/flag + + "#clock-cells": + description: Configure the SAI device as master clock provider. + const: 0 + + required: + - compatible + - "#sound-dai-cells" + - reg + - clocks + - clock-names + - dmas + - dma-names + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32f4-sai + + - then: + properties: + clocks: + items: + - description: x8k, SAI parent clock for sampling rates multiple of 8kHz. + - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz. + + clock-names: + items: + - const: x8k + - const: x11k + + - else: + properties: + clocks: + items: + - description: pclk feeds the peripheral bus interface. + - description: x8k, SAI parent clock for sampling rates multiple of 8kHz. + - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz. + + clock-names: + items: + - const: pclk + - const: x8k + - const: x11k + +additionalProperties: false + +examples: + - | + #include + #include + #include + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x1c>; + dmas = <&dmamux1 89 0x400 0x01>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index e5ee51b7b470..5dbe0b723667 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -129,6 +129,10 @@ properties: description: If present indicates that we need to reset the PHY when we detect a wakeup. This is due to a hardware errata. + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: If present indicates this device has wakeup capabilities + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 247ef00381ea..e7647bd1195c 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -91,6 +91,11 @@ properties: iommus: maxItems: 1 + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicate this device has wakeup capabilities. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml new file mode 100644 index 000000000000..9a51efa9d101 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STUSB160x Type-C controller bindings + +maintainers: + - Amelie Delaunay + +properties: + compatible: + enum: + - st,stusb1600 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: main power supply (4.1V-22V) + + vsys-supply: + description: low power supply (3.0V-5.5V) + + vconn-supply: + description: power supply (2.7V-5.5V) used to supply VConn on CC pin in + source or dual power role + + connector: + type: object + + allOf: + - $ref: ../connector/usb-connector.yaml + + properties: + compatible: + const: usb-c-connector + + power-role: true + + typec-power-opmode: true + + required: + - compatible + +required: + - compatible + - reg + - connector + +additionalProperties: false + +examples: + - | + #include + i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + typec: stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + vdd-supply = <&vbus_drd>; + vsys-supply = <&vdd_usb>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + typec-power-opmode = "default"; + + port { + typec_con_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + }; +... diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..4c3ba0468276 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,4 +1,36 @@ # SPDX-License-Identifier: GPL-2.0 + +# board-specific dtc flags +DTC_FLAGS_stm32mp157c-dk2 += -@ +DTC_FLAGS_stm32f429-disco += -@ +DTC_FLAGS_stm32f469-disco += -@ +DTC_FLAGS_stm32f746-disco += -@ +DTC_FLAGS_stm32f769-disco += -@ +DTC_FLAGS_stm32429i-eval += -@ +DTC_FLAGS_stm32746g-eval += -@ +DTC_FLAGS_stm32h743i-eval += -@ +DTC_FLAGS_stm32h743i-disco += -@ +DTC_FLAGS_stm32mp157a-dk1 += -@ +DTC_FLAGS_stm32mp157d-dk1 += -@ +DTC_FLAGS_stm32mp157c-dk2 += -@ +DTC_FLAGS_stm32mp157f-dk2 += -@ +DTC_FLAGS_stm32mp157c-dk2-a7-examples += -@ +DTC_FLAGS_stm32mp157c-dk2-m4-examples += -@ +DTC_FLAGS_stm32mp157f-dk2-a7-examples += -@ +DTC_FLAGS_stm32mp157f-dk2-m4-examples += -@ +DTC_FLAGS_stm32mp157a-ed1 += -@ +DTC_FLAGS_stm32mp157c-ed1 += -@ +DTC_FLAGS_stm32mp157d-ed1 += -@ +DTC_FLAGS_stm32mp157f-ed1 += -@ +DTC_FLAGS_stm32mp157a-ev1 += -@ +DTC_FLAGS_stm32mp157c-ev1 += -@ +DTC_FLAGS_stm32mp157d-ev1 += -@ +DTC_FLAGS_stm32mp157f-ev1 += -@ +DTC_FLAGS_stm32mp157c-ev1-a7-examples += -@ +DTC_FLAGS_stm32mp157c-ev1-m4-examples += -@ +DTC_FLAGS_stm32mp157f-ev1-a7-examples += -@ +DTC_FLAGS_stm32mp157f-ev1-m4-examples += -@ + dtb-$(CONFIG_ARCH_ALPINE) += \ alpine-db.dtb dtb-$(CONFIG_MACH_ARTPEC6) += \ @@ -1063,12 +1095,28 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157d-dk1.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-a7-examples.dtb \ + stm32mp157c-dk2-m4-examples.dtb \ + stm32mp157f-dk2.dtb \ + stm32mp157f-dk2-a7-examples.dtb \ + stm32mp157f-dk2-m4-examples.dtb \ + stm32mp157a-ed1.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157d-ed1.dtb \ + stm32mp157f-ed1.dtb \ + stm32mp157a-ev1.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-a7-examples.dtb \ + stm32mp157c-ev1-m4-examples.dtb \ + stm32mp157d-ev1.dtb \ + stm32mp157f-ev1.dtb \ + stm32mp157f-ev1-a7-examples.dtb \ + stm32mp157f-ev1-m4-examples.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 67e7648de41e..7e10ae744c9d 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -188,6 +188,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov2640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 640ff54ed00c..2e69f1bb84ef 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -349,6 +349,7 @@ clocks = <&rcc 1 CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -361,6 +362,7 @@ clocks = <&rcc 1 CLK_I2C2>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -373,6 +375,7 @@ clocks = <&rcc 1 CLK_I2C3>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -385,6 +388,7 @@ clocks = <&rcc 1 CLK_I2C4>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 7febe19e780d..078b078297ae 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -144,6 +144,7 @@ <32>; resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; clocks = <&rcc I2C1_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -156,6 +157,7 @@ <34>; resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; clocks = <&rcc I2C2_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -168,6 +170,7 @@ <73>; resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; clocks = <&rcc I2C3_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -401,6 +404,7 @@ <96>; resets = <&rcc STM32H7_APB4_RESET(I2C4)>; clocks = <&rcc I2C4_CK>; + i2c-analog-filter; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi new file mode 100644 index 000000000000..b4030e5c9422 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Fabien Dessenne for STMicroelectronics. + */ + +&pinctrl { + m4_adc1_in6_pins_a: m4-adc1-in6 { + pins { + pinmux = ; + }; + }; + + m4_adc12_ain_pins_a: m4-adc12-ain-0 { + pins { + pinmux = , /* ADC1 in13 */ + , /* ADC1 in6 */ + , /* ADC2 in2 */ + ; /* ADC2 in6 */ + }; + }; + + m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 { + pins { + pinmux = , /* ADC12 in18 */ + ; /* ADC12 in19 */ + }; + }; + + m4_cec_pins_a: m4-cec-0 { + pins { + pinmux = ; + }; + }; + + m4_cec_pins_b: m4-cec-1 { + pins { + pinmux = ; + }; + }; + + m4_dac_ch1_pins_a: m4-dac-ch1 { + pins { + pinmux = ; + }; + }; + + m4_dac_ch2_pins_a: m4-dac-ch2 { + pins { + pinmux = ; + }; + }; + + m4_dcmi_pins_a: m4-dcmi-0 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ,/* DCMI_D9 */ + ,/* DCMI_D10 */ + ;/* DCMI_D11 */ + }; + }; + + m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 { + pins { + pinmux = ; /* DFSDM_CKOUT */ + }; + }; + + m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA1 */ + }; + }; + + m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA3 */ + }; + }; + + m4_ethernet0_rgmii_pins_a: m4-rgmii-0 { + pins { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + m4_fmc_pins_a: m4-fmc-0 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_A16_FMC_CLE */ + , /* FMC_A17_FMC_ALE */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NWAIT */ + }; + }; + + m4_hdp0_pins_a: m4-hdp0-0 { + pins { + pinmux = ; /* HDP0 */ + }; + }; + + m4_hdp6_pins_a: m4-hdp6-0 { + pins { + pinmux = ; /* HDP6 */ + }; + }; + + m4_hdp7_pins_a: m4-hdp7-0 { + pins { + pinmux = ; /* HDP7 */ + }; + }; + + m4_i2c1_pins_a: m4-i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + m4_i2c2_pins_a: m4-i2c2-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + m4_i2c5_pins_a: m4-i2c5-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + m4_i2s2_pins_a: m4-i2s2-0 { + pins { + pinmux = , /* I2S2_SDO */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + + m4_ltdc_pins_a: m4-ltdc-a-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + m4_ltdc_pins_b: m4-ltdc-b-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + + m4_m_can1_pins_a: m4-m-can1-0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m4_pwm1_pins_a: m4-pwm1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH4 */ + }; + }; + + m4_pwm2_pins_a: m4-pwm2-0 { + pins { + pinmux = ; /* TIM2_CH4 */ + }; + }; + + m4_pwm3_pins_a: m4-pwm3-0 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + + m4_pwm4_pins_a: m4-pwm4-0 { + pins { + pinmux = , /* TIM4_CH3 */ + ; /* TIM4_CH4 */ + }; + }; + + m4_pwm4_pins_b: m4-pwm4-1 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + m4_pwm5_pins_a: m4-pwm5-0 { + pins { + pinmux = ; /* TIM5_CH2 */ + }; + }; + + m4_pwm8_pins_a: m4-pwm8-0 { + pins { + pinmux = ; /* TIM8_CH4 */ + }; + }; + + m4_pwm12_pins_a: m4-pwm12-0 { + pins { + pinmux = ; /* TIM12_CH1 */ + }; + }; + + m4_qspi_bk1_pins_a: m4-qspi-bk1-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + , /* QSPI_BK1_IO3 */ + ; /* QSPI_BK1_NCS */ + }; + }; + + m4_qspi_bk2_pins_a: m4-qspi-bk2-0 { + pins { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ + , /* QSPI_BK2_IO3 */ + ; /* QSPI_BK2_NCS */ + }; + }; + + m4_qspi_clk_pins_a: m4-qspi-clk-0 { + pins { + pinmux = ; /* QSPI_CLK */ + }; + }; + + m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 { + pins { + pinmux = ; /* RTC_OUT2_RMP */ + }; + }; + + m4_sai2a_pins_a: m4-sai2a-0 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + , /* SAI2_FS_A */ + ; /* SAI2_MCLK_A */ + }; + }; + + m4_sai2b_pins_a: m4-sai2b-0 { + pins { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + , /* SAI2_MCLK_B */ + ; /* SAI2_SD_B */ + }; + }; + + m4_sai2b_pins_b: m4-sai2b-2 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + m4_sai4a_pins_a: m4-sai4a-0 { + pins { + pinmux = ; /* SAI4_SD_A */ + }; + }; + + m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CMD */ + ; /* SDMMC1_CK */ + }; + }; + + m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CMD */ + ; /* SDMMC2_CK */ + }; + }; + + m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CMD */ + ; /* SDMMC2_CK */ + }; + }; + + m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CMD */ + ; /* SDMMC3_CK */ + }; + }; + + m4_spdifrx_pins_a: m4-spdifrx-0 { + pins { + pinmux = ; /* SPDIF_IN1 */ + }; + }; + + m4_spi4_pins_a: m4-spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + , /* SPI4_MOSI */ + ; /* SPI4_MISO */ + }; + }; + + m4_spi5_pins_a: m4-spi5-0 { + pins { + pinmux = , /* SPI5_SCK */ + , /* SPI5_MOSI */ + ; /* SPI5_MISO */ + }; + }; + + m4_stusb1600_pins_a: m4-stusb1600-0 { + pins { + pinmux = ; + }; + }; + + m4_uart4_pins_a: m4-uart4-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + m4_uart7_pins_a: m4-uart7-0 { + pins { + pinmux = , /* USART7_TX */ + ; /* USART7_RX */ + }; + }; + + m4_usart2_pins_a: m4-usart2-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + m4_usart3_pins_a: m4-usart3-0 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + }; + }; + + m4_usart3_pins_b: m4-usart3-1 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + }; + }; + + m4_usbotg_hs_pins_a: m4-usbotg_hs-0 { + pins { + pinmux = ; /* OTG_ID */ + }; + }; + + m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 { + pins { + pinmux = , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + }; + }; +}; + +&pinctrl_z { + m4_i2c4_pins_a: m4-i2c4-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + }; + }; + + m4_spi1_pins_a: m4-spi1-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi b/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi new file mode 100644 index 000000000000..60454aee4123 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Fabien Dessenne for STMicroelectronics. + */ + +&m4_rproc { + m4_system_resources { + #address-cells = <1>; + #size-cells = <0>; + + m4_timers2: timer@40000000 { + compatible = "rproc-srm-dev"; + reg = <0x40000000 0x400>; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers3: timer@40001000 { + compatible = "rproc-srm-dev"; + reg = <0x40001000 0x400>; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers4: timer@40002000 { + compatible = "rproc-srm-dev"; + reg = <0x40002000 0x400>; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers5: timer@40003000 { + compatible = "rproc-srm-dev"; + reg = <0x40003000 0x400>; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers6: timer@40004000 { + compatible = "rproc-srm-dev"; + reg = <0x40004000 0x400>; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers7: timer@40005000 { + compatible = "rproc-srm-dev"; + reg = <0x40005000 0x400>; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers12: timer@40006000 { + compatible = "rproc-srm-dev"; + reg = <0x40006000 0x400>; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers13: timer@40007000 { + compatible = "rproc-srm-dev"; + reg = <0x40007000 0x400>; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers14: timer@40008000 { + compatible = "rproc-srm-dev"; + reg = <0x40008000 0x400>; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_lptimer1: timer@40009000 { + compatible = "rproc-srm-dev"; + reg = <0x40009000 0x400>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_spi2: spi@4000b000 { + compatible = "rproc-srm-dev"; + reg = <0x4000b000 0x400>; + clocks = <&rcc SPI2_K>; + status = "disabled"; + }; + m4_i2s2: audio-controller@4000b000 { + compatible = "rproc-srm-dev"; + reg = <0x4000b000 0x400>; + status = "disabled"; + }; + m4_spi3: spi@4000c000 { + compatible = "rproc-srm-dev"; + reg = <0x4000c000 0x400>; + clocks = <&rcc SPI3_K>; + status = "disabled"; + }; + m4_i2s3: audio-controller@4000c000 { + compatible = "rproc-srm-dev"; + reg = <0x4000c000 0x400>; + status = "disabled"; + }; + m4_spdifrx: audio-controller@4000d000 { + compatible = "rproc-srm-dev"; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + status = "disabled"; + }; + m4_usart2: serial@4000e000 { + compatible = "rproc-srm-dev"; + reg = <0x4000e000 0x400>; + interrupt-parent = <&exti>; + interrupts = <27 1>; + clocks = <&rcc USART2_K>; + status = "disabled"; + }; + m4_usart3: serial@4000f000 { + compatible = "rproc-srm-dev"; + reg = <0x4000f000 0x400>; + interrupt-parent = <&exti>; + interrupts = <28 1>; + clocks = <&rcc USART3_K>; + status = "disabled"; + }; + m4_uart4: serial@40010000 { + compatible = "rproc-srm-dev"; + reg = <0x40010000 0x400>; + interrupt-parent = <&exti>; + interrupts = <30 1>; + clocks = <&rcc UART4_K>; + status = "disabled"; + }; + m4_uart5: serial@40011000 { + compatible = "rproc-srm-dev"; + reg = <0x40011000 0x400>; + interrupt-parent = <&exti>; + interrupts = <31 1>; + clocks = <&rcc UART5_K>; + status = "disabled"; + }; + m4_i2c1: i2c@40012000 { + compatible = "rproc-srm-dev"; + reg = <0x40012000 0x400>; + interrupt-parent = <&exti>; + interrupts = <21 1>; + clocks = <&rcc I2C1_K>; + status = "disabled"; + }; + m4_i2c2: i2c@40013000 { + compatible = "rproc-srm-dev"; + reg = <0x40013000 0x400>; + interrupt-parent = <&exti>; + interrupts = <22 1>; + clocks = <&rcc I2C2_K>; + status = "disabled"; + }; + m4_i2c3: i2c@40014000 { + compatible = "rproc-srm-dev"; + reg = <0x40014000 0x400>; + interrupt-parent = <&exti>; + interrupts = <23 1>; + clocks = <&rcc I2C3_K>; + status = "disabled"; + }; + m4_i2c5: i2c@40015000 { + compatible = "rproc-srm-dev"; + reg = <0x40015000 0x400>; + interrupt-parent = <&exti>; + interrupts = <25 1>; + clocks = <&rcc I2C5_K>; + status = "disabled"; + }; + m4_cec: cec@40016000 { + compatible = "rproc-srm-dev"; + reg = <0x40016000 0x400>; + interrupt-parent = <&exti>; + interrupts = <69 1>; + clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + m4_dac: dac@40017000 { + compatible = "rproc-srm-dev"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + status = "disabled"; + }; + m4_uart7: serial@40018000 { + compatible = "rproc-srm-dev"; + reg = <0x40018000 0x400>; + interrupt-parent = <&exti>; + interrupts = <32 1>; + clocks = <&rcc UART7_K>; + status = "disabled"; + }; + m4_uart8: serial@40019000 { + compatible = "rproc-srm-dev"; + reg = <0x40019000 0x400>; + interrupt-parent = <&exti>; + interrupts = <33 1>; + clocks = <&rcc UART8_K>; + status = "disabled"; + }; + m4_timers1: timer@44000000 { + compatible = "rproc-srm-dev"; + reg = <0x44000000 0x400>; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers8: timer@44001000 { + compatible = "rproc-srm-dev"; + reg = <0x44001000 0x400>; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_usart6: serial@44003000 { + compatible = "rproc-srm-dev"; + reg = <0x44003000 0x400>; + interrupt-parent = <&exti>; + interrupts = <29 1>; + clocks = <&rcc USART6_K>; + status = "disabled"; + }; + m4_spi1: spi@44004000 { + compatible = "rproc-srm-dev"; + reg = <0x44004000 0x400>; + clocks = <&rcc SPI1_K>; + status = "disabled"; + }; + m4_i2s1: audio-controller@44004000 { + compatible = "rproc-srm-dev"; + reg = <0x44004000 0x400>; + status = "disabled"; + }; + m4_spi4: spi@44005000 { + compatible = "rproc-srm-dev"; + reg = <0x44005000 0x400>; + clocks = <&rcc SPI4_K>; + status = "disabled"; + }; + m4_timers15: timer@44006000 { + compatible = "rproc-srm-dev"; + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers16: timer@44007000 { + compatible = "rproc-srm-dev"; + reg = <0x44007000 0x400>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_timers17: timer@44008000 { + compatible = "rproc-srm-dev"; + reg = <0x44008000 0x400>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + status = "disabled"; + }; + m4_spi5: spi@44009000 { + compatible = "rproc-srm-dev"; + reg = <0x44009000 0x400>; + clocks = <&rcc SPI5_K>; + status = "disabled"; + }; + m4_sai1: sai@4400a000 { + compatible = "rproc-srm-dev"; + reg = <0x4400a000 0x4>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_sai2: sai@4400b000 { + compatible = "rproc-srm-dev"; + reg = <0x4400b000 0x4>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_sai3: sai@4400c000 { + compatible = "rproc-srm-dev"; + reg = <0x4400c000 0x4>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_dfsdm: dfsdm@4400d000 { + compatible = "rproc-srm-dev"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; + clock-names = "dfsdm", "audio"; + status = "disabled"; + }; + m4_m_can1: can@4400e000 { + compatible = "rproc-srm-dev"; + reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + status = "disabled"; + }; + m4_m_can2: can@4400f000 { + compatible = "rproc-srm-dev"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + status = "disabled"; + }; + m4_dma1: dma@48000000 { + compatible = "rproc-srm-dev"; + reg = <0x48000000 0x400>; + clocks = <&rcc DMA1>; + status = "disabled"; + }; + m4_dma2: dma@48001000 { + compatible = "rproc-srm-dev"; + reg = <0x48001000 0x400>; + clocks = <&rcc DMA2>; + status = "disabled"; + }; + m4_dmamux1: dma-router@48002000 { + compatible = "rproc-srm-dev"; + reg = <0x48002000 0x1c>; + clocks = <&rcc DMAMUX>; + status = "disabled"; + }; + m4_adc: adc@48003000 { + compatible = "rproc-srm-dev"; + reg = <0x48003000 0x400>; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + status = "disabled"; + }; + m4_sdmmc3: sdmmc@48004000 { + compatible = "rproc-srm-dev"; + reg = <0x48004000 0x400>, <0x48005000 0x400>; + clocks = <&rcc SDMMC3_K>; + status = "disabled"; + }; + m4_usbotg_hs: usb-otg@49000000 { + compatible = "rproc-srm-dev"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + status = "disabled"; + }; + m4_hash2: hash@4c002000 { + compatible = "rproc-srm-dev"; + reg = <0x4c002000 0x400>; + clocks = <&rcc HASH2>; + status = "disabled"; + }; + m4_rng2: rng@4c003000 { + compatible = "rproc-srm-dev"; + reg = <0x4c003000 0x400>; + clocks = <&rcc RNG2_K>; + status = "disabled"; + }; + m4_crc2: crc@4c004000 { + compatible = "rproc-srm-dev"; + reg = <0x4c004000 0x400>; + clocks = <&rcc CRC2>; + status = "disabled"; + }; + m4_cryp2: cryp@4c005000 { + compatible = "rproc-srm-dev"; + reg = <0x4c005000 0x400>; + clocks = <&rcc CRYP2>; + status = "disabled"; + }; + m4_dcmi: dcmi@4c006000 { + compatible = "rproc-srm-dev"; + reg = <0x4c006000 0x400>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + status = "disabled"; + }; + m4_lptimer2: timer@50021000 { + compatible = "rproc-srm-dev"; + reg = <0x50021000 0x400>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer3: timer@50022000 { + compatible = "rproc-srm-dev"; + reg = <0x50022000 0x400>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer4: timer@50023000 { + compatible = "rproc-srm-dev"; + reg = <0x50023000 0x400>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_lptimer5: timer@50024000 { + compatible = "rproc-srm-dev"; + reg = <0x50024000 0x400>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + status = "disabled"; + }; + m4_sai4: sai@50027000 { + compatible = "rproc-srm-dev"; + reg = <0x50027000 0x4>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + status = "disabled"; + }; + m4_qspi: qspi@58003000 { + compatible = "rproc-srm-dev"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + clocks = <&rcc QSPI_K>; + status = "disabled"; + }; + m4_ethernet0: ethernet@5800a000 { + compatible = "rproc-srm-dev"; + reg = <0x5800a000 0x2000>; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "syscfg-clk"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHSTP>, + <&rcc SYSCFG>; + status = "disabled"; + }; + }; +}; + diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi new file mode 100644 index 000000000000..94a10b86a179 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +/ { + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpus { + cpu0: cpu@0 { + clocks = <&rcc CK_MPU>; + }; + + cpu1: cpu@1 { + clocks = <&rcc CK_MPU>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; + }; + + soc { + m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + cryp1: cryp@54001000 { + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + }; + + dsi: dsi@5a000000 { + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + }; + }; + + ahb { + m4_rproc: m4@10000000 { + resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; + + m4_system_resources { + m4_cec: cec@40016000 { + clocks = <&rcc CEC_K>, <&rcc CK_LSE>; + }; + + m4_m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m4_m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + }; + }; + }; + + firmware { + /delete-node/ scmi0; + /delete-node/ scmi1; + }; + /delete-node/ sram@2ffff000; +}; + +&cec { + clocks = <&rcc CEC_K>, <&clk_lse>; +}; + +&gpioz { + clocks = <&rcc GPIOZ>; +}; + +&hash1 { + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; +}; + +&i2c4 { + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; +}; + +&i2c6 { + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +}; + +&mdma1 { + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc", "syscon"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; +}; + +&rng1 { + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; +}; + +&rtc { + clocks = <&rcc RTCAPB>, <&rcc RTC>; +}; + +&spi6 { + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; +}; + +&usart1 { + clocks = <&rcc USART1_K>; +}; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index d84686e00370..a0b76e238c18 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,45 @@ }; }; + dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 { + pins { + pinmux = ; /* DFSDM_CKOUT */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 { + pins { + pinmux = ; /* DFSDM_CKOUT */ + }; + }; + + dfsdm_data1_pins_a: dfsdm-data1-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA1 */ + }; + }; + + dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA1 */ + }; + }; + + dfsdm_data3_pins_a: dfsdm-data3-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA3 */ + }; + }; + + dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 { + pins { + pinmux = ; /* DFSDM_DATA3 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ @@ -349,6 +388,51 @@ }; }; + hdp0_pins_a: hdp0-0 { + pins { + pinmux = ; /* HDP0 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + hdp0_pins_sleep_a: hdp0-sleep-0 { + pins { + pinmux = ; /* HDP0 */ + }; + }; + + hdp6_pins_a: hdp6-0 { + pins { + pinmux = ; /* HDP6 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + hdp6_pins_sleep_a: hdp6-sleep-0 { + pins { + pinmux = ; /* HDP6 */ + }; + }; + + hdp7_pins_a: hdp7-0 { + pins { + pinmux = ; /* HDP7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + hdp7_pins_sleep_a: hdp7-sleep-0 { + pins { + pinmux = ; /* HDP7 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -1051,6 +1135,12 @@ }; }; + rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { + pins { + pinmux = ; /* RTC_OUT2_RMP */ + }; + }; + sai2a_pins_a: sai2a-0 { pins { pinmux = , /* SAI2_SCK_A */ @@ -1147,7 +1237,7 @@ }; }; - sai2b_pins_c: sai2a-4 { + sai2b_pins_c: sai2b-4 { pins1 { pinmux = ; /* SAI2_SD_B */ bias-disable; @@ -1591,6 +1681,73 @@ }; }; + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + + spi4_pins_b: spi4-1 { + pins1 { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + + spi4_sleep_pins_b: spi4-sleep-1 { + pins { + pinmux = , /* SPI4_SCK */ + , /* SPI4_MISO */ + ; /* SPI4_MOSI */ + }; + }; + + spi5_pins_a: spi5-0 { + pins1 { + pinmux = , /* SPI5_SCK */ + ; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = , /* SPI5_SCK */ + , /* SPI5_MISO */ + ; /* SPI5_MOSI */ + }; + }; + + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1605,20 +1762,20 @@ }; uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; }; uart4_sleep_pins_a: uart4-sleep-0 { - pins { + pins { pinmux = , /* UART4_TX */ ; /* UART4_RX */ - }; + }; }; uart4_pins_b: uart4-1 { @@ -1684,7 +1841,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1694,7 +1851,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1726,20 +1883,6 @@ }; }; - spi4_pins_a: spi4-0 { - pins { - pinmux = , /* SPI4_SCK */ - ; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* SPI4_MISO */ - bias-disable; - }; - }; - usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -1806,10 +1949,15 @@ usart2_idle_pins_c: usart2-idle-2 { pins1 { pinmux = , /* USART2_TX */ - , /* USART2_RTS */ ; /* USART2_CTS_NSS */ }; pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { pinmux = ; /* USART2_RX */ bias-disable; }; @@ -1855,10 +2003,15 @@ usart3_idle_pins_b: usart3-idle-1 { pins1 { pinmux = , /* USART3_TX */ - , /* USART3_RTS */ ; /* USART3_CTS_NSS */ }; pins2 { + pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { pinmux = ; /* USART3_RX */ bias-disable; }; @@ -1884,19 +2037,24 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; usart3_idle_pins_c: usart3-idle-2 { pins1 { pinmux = , /* USART3_TX */ - , /* USART3_RTS */ ; /* USART3_CTS_NSS */ }; pins2 { - pinmux = ; /* USART3_RX */ + pinmux = ; /* USART3_RTS */ bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART3_RX */ + bias-pull-up; }; }; @@ -1970,4 +2128,12 @@ bias-disable; }; }; + + spi1_sleep_pins_a: spi1-sleep-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + }; + }; }; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 84757901cd8d..ca71139f3ad4 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -5,7 +5,10 @@ */ #include #include +#include #include +#include + / { #address-cells = <1>; @@ -17,9 +20,14 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; device_type = "cpu"; reg = <0>; + clocks = <&scmi0_clk CK_SCMI0_MPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + #cooling-cells = <2>; }; }; @@ -30,6 +38,61 @@ interrupt-parent = <&intc>; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + }; + + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi0_shm: scmi_shm@0 { + reg = <0 0x80>; + }; + + scmi1_shm: scmi_shm@200 { + reg = <0x200 0x80>; + }; + }; + + firmware { + scmi0: scmi0 { + compatible = "arm,scmi-smc"; + #address-cells = <1>; + #size-cells = <0>; + arm,smc-id = <0x82002000>; + shmem = <&scmi0_shm>; + + scmi0_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi0_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi1 { + compatible = "arm,scmi-smc"; + #address-cells = <1>; + #size-cells = <0>; + arm,smc-id = <0x82002001>; + shmem = <&scmi1_shm>; + status = "disabled"; + + scmi1_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -50,38 +113,7 @@ , ; interrupt-parent = <&intc>; - }; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; + always-on; }; thermal-zones { @@ -91,12 +123,6 @@ thermal-sensors = <&dts>; trips { - cpu_alert1: cpu-alert1 { - temperature = <85000>; - hysteresis = <0>; - type = "passive"; - }; - cpu-crit { temperature = <120000>; hysteresis = <0>; @@ -115,6 +141,26 @@ status = "disabled"; }; + pm_domain { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp157c-pd"; + + pd_core_ret: core-ret-power-domain@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #power-domain-cells = <0>; + label = "CORE-RETENTION"; + + pd_core: core-power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + label = "CORE"; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -122,6 +168,14 @@ interrupt-parent = <&intc>; ranges; + sram: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x60000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10000000 0x60000>; + }; + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -129,11 +183,11 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; + dmas = <&dmamux1 18 0x400 0x80000001>, + <&dmamux1 19 0x400 0x80000001>, + <&dmamux1 20 0x400 0x80000001>, + <&dmamux1 21 0x400 0x80000001>, + <&dmamux1 22 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled"; @@ -162,12 +216,12 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; + dmas = <&dmamux1 23 0x400 0x80000001>, + <&dmamux1 24 0x400 0x80000001>, + <&dmamux1 25 0x400 0x80000001>, + <&dmamux1 26 0x400 0x80000001>, + <&dmamux1 27 0x400 0x80000001>, + <&dmamux1 28 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; @@ -196,10 +250,10 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; + dmas = <&dmamux1 29 0x400 0x80000001>, + <&dmamux1 30 0x400 0x80000001>, + <&dmamux1 31 0x400 0x80000001>, + <&dmamux1 32 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled"; @@ -228,12 +282,12 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; + dmas = <&dmamux1 55 0x400 0x80000001>, + <&dmamux1 56 0x400 0x80000001>, + <&dmamux1 57 0x400 0x80000001>, + <&dmamux1 58 0x400 0x80000001>, + <&dmamux1 59 0x400 0x80000001>, + <&dmamux1 60 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; @@ -262,7 +316,7 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; + dmas = <&dmamux1 69 0x400 0x80000001>; dma-names = "up"; status = "disabled"; @@ -280,7 +334,7 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; + dmas = <&dmamux1 70 0x400 0x80000001>; dma-names = "up"; status = "disabled"; @@ -362,8 +416,11 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; pwm { @@ -382,6 +439,11 @@ compatible = "st,stm32-lptimer-counter"; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; spi2: spi@4000b000 { @@ -392,9 +454,10 @@ interrupts = ; clocks = <&rcc SPI2_K>; resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -417,9 +480,10 @@ interrupts = ; clocks = <&rcc SPI3_K>; resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -450,32 +514,52 @@ usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; - interrupts = ; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; usart3: serial@4000f000 { compatible = "st,stm32h7-uart"; reg = <0x4000f000 0x400>; - interrupts = ; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; uart5: serial@40011000 { compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; - interrupts = ; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -483,14 +567,19 @@ compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C1_K>; resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x80000001>, + <&dmamux1 34 0x400 0x80000001>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -498,14 +587,19 @@ compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C2_K>; resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x80000001>, + <&dmamux1 36 0x400 0x80000001>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -513,14 +607,19 @@ compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C3_K>; resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x80000001>, + <&dmamux1 74 0x400 0x80000001>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -528,14 +627,19 @@ compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C5_K>; resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x80000001>, + <&dmamux1 116 0x400 0x80000001>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -543,7 +647,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = ; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -575,16 +679,26 @@ uart7: serial@40018000 { compatible = "st,stm32h7-uart"; reg = <0x40018000 0x400>; - interrupts = ; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; uart8: serial@40019000 { compatible = "st,stm32h7-uart"; reg = <0x40019000 0x400>; - interrupts = ; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -595,13 +709,13 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; + dmas = <&dmamux1 11 0x400 0x80000001>, + <&dmamux1 12 0x400 0x80000001>, + <&dmamux1 13 0x400 0x80000001>, + <&dmamux1 14 0x400 0x80000001>, + <&dmamux1 15 0x400 0x80000001>, + <&dmamux1 16 0x400 0x80000001>, + <&dmamux1 17 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; status = "disabled"; @@ -631,13 +745,13 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; + dmas = <&dmamux1 47 0x400 0x80000001>, + <&dmamux1 48 0x400 0x80000001>, + <&dmamux1 49 0x400 0x80000001>, + <&dmamux1 50 0x400 0x80000001>, + <&dmamux1 51 0x400 0x80000001>, + <&dmamux1 52 0x400 0x80000001>, + <&dmamux1 53 0x400 0x80000001>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; status = "disabled"; @@ -663,8 +777,13 @@ usart6: serial@44003000 { compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; - interrupts = ; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; + wakeup-source; + power-domains = <&pd_core>; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -676,9 +795,10 @@ interrupts = ; clocks = <&rcc SPI1_K>; resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -701,9 +821,10 @@ interrupts = ; clocks = <&rcc SPI4_K>; resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -714,10 +835,10 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; + dmas = <&dmamux1 105 0x400 0x80000001>, + <&dmamux1 106 0x400 0x80000001>, + <&dmamux1 107 0x400 0x80000001>, + <&dmamux1 108 0x400 0x80000001>; dma-names = "ch1", "up", "trig", "com"; status = "disabled"; @@ -741,8 +862,8 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; + dmas = <&dmamux1 109 0x400 0x80000001>, + <&dmamux1 110 0x400 0x80000001>; dma-names = "ch1", "up"; status = "disabled"; @@ -765,8 +886,8 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; + dmas = <&dmamux1 111 0x400 0x80000001>, + <&dmamux1 112 0x400 0x80000001>; dma-names = "ch1", "up"; status = "disabled"; @@ -791,9 +912,10 @@ interrupts = ; clocks = <&rcc SPI5_K>; resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -811,7 +933,7 @@ #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; + reg = <0x4 0x20>; clocks = <&rcc SAI1_K>; clock-names = "sai_ck"; dmas = <&dmamux1 87 0x400 0x01>; @@ -821,7 +943,7 @@ sai1b: audio-controller@4400a024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI1_K>; clock-names = "sai_ck"; dmas = <&dmamux1 88 0x400 0x01>; @@ -842,7 +964,7 @@ sai2a: audio-controller@4400b004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; + reg = <0x4 0x20>; clocks = <&rcc SAI2_K>; clock-names = "sai_ck"; dmas = <&dmamux1 89 0x400 0x01>; @@ -852,7 +974,7 @@ sai2b: audio-controller@4400b024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI2_K>; clock-names = "sai_ck"; dmas = <&dmamux1 90 0x400 0x01>; @@ -873,7 +995,7 @@ sai3a: audio-controller@4400c004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; + reg = <0x04 0x20>; clocks = <&rcc SAI3_K>; clock-names = "sai_ck"; dmas = <&dmamux1 113 0x400 0x01>; @@ -883,7 +1005,7 @@ sai3b: audio-controller@4400c024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI3_K>; clock-names = "sai_ck"; dmas = <&dmamux1 114 0x400 0x01>; @@ -977,6 +1099,15 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>, + <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>, + <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>, + <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>, + <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>, + <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>, + <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>, + <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>; + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; }; dma2: dma-controller@48001000 { @@ -995,11 +1126,20 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>, + <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>, + <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>, + <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>, + <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>, + <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>, + <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>, + <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>; + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; }; dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; + reg = <0x48002000 0x40>; #dma-cells = <3>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; @@ -1028,7 +1168,7 @@ reg = <0x0>; interrupt-parent = <&adc>; interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; + dmas = <&dmamux1 9 0x400 0x80000001>; dma-names = "rx"; status = "disabled"; }; @@ -1039,7 +1179,7 @@ reg = <0x100>; interrupt-parent = <&adc>; interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; + dmas = <&dmamux1 10 0x400 0x80000001>; dma-names = "rx"; status = "disabled"; }; @@ -1047,7 +1187,7 @@ sdmmc3: sdmmc@48004000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1067,27 +1207,37 @@ clock-names = "otg"; resets = <&rcc USBO_R>; reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <256>; + interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; usb33d-supply = <&usb33>; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; }; + hsem: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <2>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; + ipcc: mailbox@4c001000 { compatible = "st,stm32mp1-ipcc"; #mbox-cells = <1>; reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; + power-domains = <&pd_core>; status = "disabled"; }; @@ -1098,21 +1248,30 @@ resets = <&rcc CAMITF_R>; clocks = <&rcc DCMI>; clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; + dmas = <&dmamux1 75 0x400 0xe0000001>; dma-names = "tx"; status = "disabled"; }; rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; + compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + interrupts = ; + + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi0_clk CK_SCMI0_HSE>, + <&scmi0_clk CK_SCMI0_HSI>, + <&scmi0_clk CK_SCMI0_CSI>, + <&scmi0_clk CK_SCMI0_LSE>, + <&scmi0_clk CK_SCMI0_LSI>; }; pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; + st,tzcr = <&rcc 0x0 0x1>; reg11: reg11 { regulator-name = "reg11"; @@ -1138,11 +1297,38 @@ reg = <0x50001014 0x4>; }; + pwr_irq: pwr@50001020 { + compatible = "st,stm32mp1-pwr"; + reg = <0x50001020 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>, + <&gpioa 2 GPIO_ACTIVE_HIGH>, + <&gpioc 13 GPIO_ACTIVE_HIGH>, + <&gpioi 8 GPIO_ACTIVE_HIGH>, + <&gpioi 11 GPIO_ACTIVE_HIGH>, + <&gpioc 1 GPIO_ACTIVE_HIGH>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000d000 0x400>; + hwlocks = <&hsem 1 1>; + + /* exti_pwr is an extra interrupt controller used for + * EXTI 55 to 60. It's mapped on pwr interrupt + * controller. + */ + exti_pwr: exti-pwr { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&pwr_irq>; + st,irq-number = <6>; + }; }; syscfg: syscon@50020000 { @@ -1156,8 +1342,11 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; pwm { @@ -1176,6 +1365,11 @@ compatible = "st,stm32-lptimer-counter"; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer3: timer@50022000 { @@ -1183,8 +1377,11 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; pwm { @@ -1198,13 +1395,21 @@ reg = <2>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; pwm { @@ -1212,13 +1417,21 @@ #pwm-cells = <3>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer5: timer@50024000 { compatible = "st,stm32-lptimer"; reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; pwm { @@ -1226,6 +1439,11 @@ #pwm-cells = <3>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; vrefbuf: vrefbuf@50025000 { @@ -1250,7 +1468,7 @@ sai4a: audio-controller@50027004 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; + reg = <0x04 0x20>; clocks = <&rcc SAI4_K>; clock-names = "sai_ck"; dmas = <&dmamux1 99 0x400 0x01>; @@ -1260,7 +1478,7 @@ sai4b: audio-controller@50027024 { #sound-dai-cells = <0>; compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; + reg = <0x24 0x20>; clocks = <&rcc SAI4_K>; clock-names = "sai_ck"; dmas = <&dmamux1 100 0x400 0x01>; @@ -1278,13 +1496,21 @@ status = "disabled"; }; + hdp: hdp@5002a000 { + compatible = "st,stm32mp1-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + clock-names = "hdp"; + status = "disabled"; + }; + hash1: hash@54002000 { compatible = "st,stm32f756-hash"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; + clocks = <&scmi0_clk CK_SCMI0_HASH1>; + resets = <&scmi0_reset RST_SCMI0_HASH1>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; status = "disabled"; @@ -1293,8 +1519,8 @@ rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; + clocks = <&scmi0_clk CK_SCMI0_RNG1>; + resets = <&scmi0_reset RST_SCMI0_RNG1>; status = "disabled"; }; @@ -1303,8 +1529,8 @@ reg = <0x58000000 0x1000>; interrupts = ; clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; - #dma-cells = <5>; + resets = <&scmi0_reset RST_SCMI0_MDMA>; + #dma-cells = <6>; dma-channels = <32>; dma-requests = <48>; }; @@ -1335,9 +1561,9 @@ <4 0x09010000 0x1000>, <4 0x09020000 0x1000>; interrupts = ; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>; dma-names = "tx", "rx", "ecc"; status = "disabled"; }; @@ -1348,8 +1574,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>, + <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; @@ -1360,7 +1586,7 @@ sdmmc1: sdmmc@58005000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1375,7 +1601,7 @@ sdmmc2: sdmmc@58007000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1405,8 +1631,10 @@ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <&exti 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", @@ -1423,6 +1651,7 @@ snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; + power-domains = <&pd_core>; status = "disabled"; }; @@ -1440,8 +1669,10 @@ reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; resets = <&rcc USBH_R>; - interrupts = ; + interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>; companion = <&usbh_ohci>; + power-domains = <&pd_core>; + wakeup-source; status = "disabled"; }; @@ -1464,7 +1695,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -1472,10 +1703,13 @@ usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; + #clock-cells = <0>; compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; status = "disabled"; usbphyc_port0: usb-phy@0 { @@ -1489,11 +1723,21 @@ }; }; + ddrperfm: perf@5a007000 { + compatible = "st,stm32-ddr-pmu"; + reg = <0x5a007000 0x400>; + clocks = <&rcc DDRPERFM>; + resets = <&rcc DDRPERFM_R>; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; - interrupts = ; - clocks = <&rcc USART1_K>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi0_clk CK_SCMI0_USART1>; + resets = <&scmi0_reset RST_SCMI0_USART1>; + wakeup-source; + power-domains = <&pd_core>; status = "disabled"; }; @@ -1503,11 +1747,12 @@ compatible = "st,stm32h7-spi"; reg = <0x5c001000 0x400>; interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; + clocks = <&scmi0_clk CK_SCMI0_SPI6>; + resets = <&scmi0_reset RST_SCMI0_SPI6>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; status = "disabled"; }; @@ -1515,23 +1760,29 @@ compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi0_clk CK_SCMI0_I2C4>; + resets = <&scmi0_reset RST_SCMI0_I2C4>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>, + <&mdma1 37 0x0 0x40002 0x0 0x0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; + clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, + <&scmi0_clk CK_SCMI0_RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = ; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -1540,26 +1791,37 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + part_number_otp: part_number_otp@4 { + reg = <0x4 0x1>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac_address: mac@e4 { + reg = <0xe4 0x6>; + }; }; i2c6: i2c@5c009000 { compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; + interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi0_clk CK_SCMI0_I2C6>; + resets = <&scmi0_reset RST_SCMI0_I2C6>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>, + <&mdma1 39 0x0 0x40002 0x0 0x0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_core>; st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -1574,6 +1836,7 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hsem 0 1>; pins-are-numbered; gpioa: gpio@50002000 { @@ -1706,6 +1969,7 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hsem 0 1>; gpioz: gpio@54004000 { gpio-controller; @@ -1713,12 +1977,30 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&rcc GPIOZ>; + clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; }; }; + + tamp: tamp@5c00a000 { + compatible = "simple-bus", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x150>; /* reg20 */ + mask = <0xff>; + mode-normal = <0>; + mode-fastboot = <0x1>; + mode-recovery = <0x2>; + mode-stm32cubeprogrammer = <0x3>; + mode-ums_mmc0 = <0x10>; + mode-ums_mmc1 = <0x11>; + mode-ums_mmc2 = <0x12>; + }; + }; }; mlahb: ahb { @@ -1735,11 +2017,18 @@ reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; + + m4_system_resources { + compatible = "rproc-srm-core"; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 1c1889b194cf..cf16b843c6b5 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -10,9 +10,11 @@ cpus { cpu1: cpu@1 { compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; device_type = "cpu"; reg = <1>; + clocks = <&scmi0_clk CK_SCMI0_MPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; }; @@ -30,7 +32,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -43,7 +45,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 54e73ccea446..8a34964b9d79 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -20,7 +20,8 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + phy-dsi-supply = <®18>; + clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 4c8be9c8eb20..f415e581a63c 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "stm32mp157.dtsi" +#include "stm32mp15xa.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #include "stm32mp15xx-dkx.dtsi" @@ -16,7 +17,6 @@ compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; aliases { - ethernet0 = ðernet0; serial0 = &uart4; serial1 = &usart3; serial2 = &uart7; diff --git a/arch/arm/boot/dts/stm32mp157a-ed1.dts b/arch/arm/boot/dts/stm32mp157a-ed1.dts new file mode 100644 index 000000000000..0213ca5c17fa --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-ed1.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xa.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include "stm32mp15xx-edx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A eval daughter"; + compatible = "st,stm32mp157a-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + gpu_reserved: gpu@f6000000 { + reg = <0xf6000000 0x8000000>; + no-map; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-ev1.dts b/arch/arm/boot/dts/stm32mp157a-ev1.dts new file mode 100644 index 000000000000..11bd88a82f05 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-ev1.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157a-ed1.dts" +#include "stm32mp15xx-evx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A eval daughter on eval mother"; + compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel_dsi: panel-dsi@0 { + compatible = "raydium,rm68200"; + reg = <0>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + backlight = <&panel_backlight>; + power-supply = <&v3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&i2c2 { + gt9147: goodix_ts@5d { + compatible = "goodix,gt9147"; + reg = <0x5d>; + panel = <&panel_dsi>; + pinctrl-0 = <&goodix_pins>; + pinctrl-names = "default"; + status = "okay"; + + interrupts = <14 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&stmfx_pinctrl>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts new file mode 100644 index 000000000000..372ceb2c7128 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 configured to run Linux A7 examples"; + compatible = "st,stm32mp157c-dk2-a7-examples", "st,stm32mp157c-dk2", "st,stm32mp157"; +}; + +&adc { + status = "okay"; + + adc2: adc@100 { + /* Set IRQ mode as example. DMA is the preferred mode, yet. */ + /delete-property/dmas; + /delete-property/dma-names; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&timers1 { + status = "okay"; +}; + +&timers3 { + status = "okay"; +}; + +&timers4 { + status = "okay"; +}; + +&timers5 { + status = "okay"; +}; + +&timers6 { + status = "okay"; +}; + +&timers12 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts new file mode 100644 index 000000000000..14eac740d4e3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 configured to run M4 examples"; + compatible = "st,stm32mp157c-dk2-m4-examples", "st,stm32mp157c-dk2", "st,stm32mp157"; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&dma2 { + status = "disabled"; +}; + +&dmamux1 { + dma-masters = <&dma1>; + dma-channels = <8>; +}; + +&m4_adc { + vref-supply = <&vrefbuf>; + status = "okay"; +}; + +&m4_dac { + vref-supply = <&vrefbuf>; + status = "okay"; +}; + +&m4_dma2 { + status = "okay"; +}; + +&m4_crc2 { + status = "okay"; +}; + +&m4_cryp2 { + status = "okay"; +}; + +&m4_hash2 { + status = "okay"; +}; + +&m4_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_i2c5_pins_a>; + status = "okay"; +}; + +&m4_rng2 { + status = "okay"; +}; + +&m4_rproc { + m4_system_resources { + status = "okay"; + + button { + compatible = "rproc-srm-dev"; + interrupt-parent = <&gpioa>; + interrupts = <14 2>; + interrupt-names = "irq"; + status = "okay"; + }; + + m4_led: m4_led { + compatible = "rproc-srm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins>; + status = "okay"; + }; + }; +}; + +&m4_spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_spi4_pins_a>; + status = "okay"; +}; + + +&m4_timers2 { + status = "okay"; +}; + +&m4_timers1 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_pwm1_pins_a_ch1>; + status = "okay"; +}; + +&m4_uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_uart7_pins_a>; + status = "okay"; +}; + +&pinctrl { + m4_leds_orange_pins: m4-leds-orange-0 { + pins { + pinmux = ; + }; + }; + + m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 { + pins { + pinmux = ; + }; + }; +}; + +&timers1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 045636555ddd..1c894f288c66 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -11,13 +11,13 @@ #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #include "stm32mp15xx-dkx.dtsi" +#include / { model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; aliases { - ethernet0 = ðernet0; serial0 = &uart4; serial1 = &usart3; serial2 = &uart7; @@ -27,11 +27,19 @@ chosen { stdout-path = "serial0:115200n8"; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; + }; +}; + +&cryp1 { + status = "okay"; }; &dsi { status = "okay"; - phy-dsi-supply = <®18>; ports { port@0 { @@ -49,7 +57,7 @@ }; }; - panel@0 { + panel_otm8009a: panel-otm8009a@0 { compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; @@ -65,6 +73,18 @@ }; &i2c1 { + touchscreen@2a { + compatible = "focaltech,ft6236"; + reg = <0x2a>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + vcc-supply = <&v3v3>; + status = "okay"; + }; touchscreen@38 { compatible = "focaltech,ft6236"; reg = <0x38>; @@ -73,6 +93,8 @@ interrupt-controller; touchscreen-size-x = <480>; touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + vcc-supply = <&v3v3>; status = "okay"; }; }; @@ -88,10 +110,48 @@ }; }; +&rtc { + st,lsco = ; + pinctrl-0 = <&rtc_out2_rmp_pins_a>; + pinctrl-names = "default"; +}; + +/* Wifi */ +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ &usart2 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&usart2_pins_c>; pinctrl-1 = <&usart2_sleep_pins_c>; pinctrl-2 = <&usart2_idle_pins_c>; - status = "disabled"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2e77ccec3fc1..d2c24803b99e 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. */ /dts-v1/; @@ -9,8 +9,7 @@ #include "stm32mp15xc.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" -#include -#include +#include "stm32mp15xx-edx.dtsi" / { model = "STMicroelectronics STM32MP157C eval daughter"; @@ -20,373 +19,18 @@ stdout-path = "serial0:115200n8"; }; - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; + gpu_reserved: gpu@f6000000 { + reg = <0xf6000000 0x8000000>; no-map; }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; - }; - - aliases { - serial0 = &uart4; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ - pinctrl-0 = <&adc1_in6_pins_a>; - pinctrl-names = "default"; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "disabled"; - adc1: adc@0 { - st,adc-channels = <0 1 6>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-nsecs = <400>; - status = "okay"; - }; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "disabled"; - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; }; }; -&dts { +&cryp1 { status = "okay"; }; &gpu { contiguous-area = <&gpu_reserved>; }; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&timers6 { - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - timer@5 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - status = "okay"; -}; - -&usbotg_hs { - vbus-supply = <&vbus_otg>; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts new file mode 100644 index 000000000000..8a4eda70d452 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" +#include + +/ { + model = "STMicroelectronics STM32MP157C-EV1 configured to run Linux A7 examples"; + compatible = "st,stm32mp157c-ev1-a7-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; + + test_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + status = "okay"; + /* gpio needs vdd core in retention for wakeup */ + power-domains = <&pd_core_ret>; + + button@1 { + label = "PA13"; + linux,code = ; + interrupts-extended = <&gpioa 13 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + wakeup-source; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&dac { + status = "okay"; +}; + +&timers2 { + status = "okay"; +}; + +&timers8 { + status = "okay"; +}; + +&timers12 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts new file mode 100644 index 000000000000..b1bb38efbfa8 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 configured to run M4 examples"; + compatible = "st,stm32mp157c-ev1-m4-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&dcmi { + status = "disabled"; +}; + +&dma2 { + status = "disabled"; +}; + +&dmamux1 { + dma-masters = <&dma1>; + dma-channels = <8>; +}; + +&fmc { + status = "disabled"; +}; + +&i2c5 { + status = "disabled"; +}; + +&m4_adc { + vref-supply = <&vdda>; + status = "okay"; +}; + +&m4_crc2 { + status = "okay"; +}; + +&m4_cryp2 { + status = "okay"; +}; + +&m4_dac { + vref-supply = <&vdda>; + status = "okay"; +}; + +&m4_dma2 { + status = "okay"; +}; + +&m4_hash2 { + status = "okay"; +}; + +&m4_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_i2c5_pins_a>; + status = "okay"; +}; + +&m4_qspi { + pinctrl-names = "default"; + pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a + &m4_qspi_bk2_pins_a>; + status = "okay"; +}; + +&m4_rproc { + m4_system_resources { + status = "okay"; + + /* button { + compatible = "rproc-srm-dev"; + interrupt-parent = <&gpioa>; + interrupts = <14 2>; + interrupt-names = "irq"; + status = "okay"; + };*/ + + m4_led: m4_led { + compatible = "rproc-srm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins>; + status = "okay"; + }; + }; +}; + +&m4_rng2 { + status = "okay"; +}; + +&m4_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_spi1_pins_a>; + status = "okay"; +}; + + +&m4_timers2 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_pwm2_pins_a>; + status = "okay"; +}; + +&m4_usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_usart3_pins_a>; + status = "okay"; +}; + +&pinctrl { + m4_leds_orange_pins: m4-leds-orange-0 { + pins { + pinmux = ; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sai2b { + status = "disabled"; +}; + +&timers2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index a55e80ce2602..e84897ef4443 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -1,13 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. */ /dts-v1/; #include "stm32mp157c-ed1.dts" -#include -#include +#include "stm32mp15xx-evx.dtsi" / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -20,89 +19,29 @@ aliases { serial0 = &uart4; serial1 = &usart3; - ethernet0 = ðernet0; }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - button-1 { - label = "JoyDown"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - }; - button-3 { - label = "JoyRight"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; - button-4 { - label = "JoyUp"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - }; - }; - - panel_backlight: panel-backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - default-on; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; }; -&dcmi { +<dc { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_a>; - pinctrl-1 = <&dcmi_sleep_pins_a>; port { - dcmi_0: endpoint { - remote-endpoint = <&ov5640_0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; }; }; }; &dsi { - phy-dsi-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -118,7 +57,7 @@ }; }; - panel-dsi@0 { + panel_dsi: panel-dsi@0 { compatible = "raydium,rm68200"; reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; @@ -134,243 +73,16 @@ }; }; -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - - nand-controller@4,0 { - status = "okay"; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - &i2c2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - DOVDD-supply = <&v2v8>; - powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; - reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; - rotation = <180>; - status = "okay"; - - port { - ov5640_0: endpoint { - remote-endpoint = <&dcmi_0>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - vdd-supply = <&v3v3>; - - stmfx_pinctrl: pinctrl { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - bias-pull-down; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -<dc { - status = "okay"; - - port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: mx66l51235l@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - flash1: mx66l51235l@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "disabled"; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-1 = <&pwm2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@1 { + gt9147: goodix_ts@5d { + compatible = "goodix,gt9147"; + reg = <0x5d>; + panel = <&panel_dsi>; + pinctrl-0 = <&goodix_pins>; + pinctrl-names = "default"; status = "okay"; - }; -}; -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; + interrupts = <14 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&stmfx_pinctrl>; }; }; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_b>; - pinctrl-1 = <&usart3_sleep_pins_b>; - pinctrl-2 = <&usart3_idle_pins_b>; - /* - * HW flow control USART3_RTS is optional, and isn't default wired to - * the connector. SB23 needs to be soldered in order to use it, and R77 - * (ETH_CLK) should be removed. - */ - uart-has-rtscts; - status = "disabled"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp157d-dk1.dts b/arch/arm/boot/dts/stm32mp157d-dk1.dts new file mode 100644 index 000000000000..bcc012cfff7c --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157d-dk1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xd.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157D-DK1 Discovery Board"; + compatible = "st,stm32mp157d-dk1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157d-ed1.dts b/arch/arm/boot/dts/stm32mp157d-ed1.dts new file mode 100644 index 000000000000..5aa383d3b585 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157d-ed1.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xd.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include "stm32mp15xx-edx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157D eval daughter"; + compatible = "st,stm32mp157d-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + gpu_reserved: gpu@f6000000 { + reg = <0xf6000000 0x8000000>; + no-map; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157d-ev1.dts b/arch/arm/boot/dts/stm32mp157d-ev1.dts new file mode 100644 index 000000000000..5cb08c707990 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157d-ev1.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157d-ed1.dts" +#include "stm32mp15xx-evx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157D eval daughter on eval mother"; + compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel_dsi: panel-dsi@0 { + compatible = "raydium,rm68200"; + reg = <0>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + backlight = <&panel_backlight>; + power-supply = <&v3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&i2c2 { + gt9147: goodix_ts@5d { + compatible = "goodix,gt9147"; + reg = <0x5d>; + panel = <&panel_dsi>; + pinctrl-0 = <&goodix_pins>; + pinctrl-names = "default"; + status = "okay"; + + interrupts = <14 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&stmfx_pinctrl>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts new file mode 100644 index 000000000000..8dcb52fedb22 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157f-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157F-DK2 configured to run Linux A7 examples"; + compatible = "st,stm32mp157f-dk2-a7-examples", "st,stm32mp157f-dk2", "st,stm32mp157"; +}; + +&adc { + status = "okay"; + + adc2: adc@100 { + /* Set IRQ mode as example. DMA is the preferred mode, yet. */ + /delete-property/dmas; + /delete-property/dma-names; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&timers1 { + status = "okay"; +}; + +&timers3 { + status = "okay"; +}; + +&timers4 { + status = "okay"; +}; + +&timers5 { + status = "okay"; +}; + +&timers6 { + status = "okay"; +}; + +&timers12 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts new file mode 100644 index 000000000000..72652299743b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157f-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157F-DK2 configured to run M4 examples"; + compatible = "st,stm32mp157f-dk2-m4-examples", "st,stm32mp157f-dk2", "st,stm32mp157"; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&dma2 { + status = "disabled"; +}; + +&dmamux1 { + dma-masters = <&dma1>; + dma-channels = <8>; +}; + +&m4_adc { + vref-supply = <&vrefbuf>; + status = "okay"; +}; + +&m4_dac { + vref-supply = <&vrefbuf>; + status = "okay"; +}; + +&m4_dma2 { + status = "okay"; +}; + +&m4_crc2 { + status = "okay"; +}; + +&m4_cryp2 { + status = "okay"; +}; + +&m4_hash2 { + status = "okay"; +}; + +&m4_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_i2c5_pins_a>; + status = "okay"; +}; + +&m4_rng2 { + status = "okay"; +}; + +&m4_rproc { + m4_system_resources { + status = "okay"; + + button { + compatible = "rproc-srm-dev"; + interrupt-parent = <&gpioa>; + interrupts = <14 2>; + interrupt-names = "irq"; + status = "okay"; + }; + + m4_led: m4_led { + compatible = "rproc-srm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins>; + status = "okay"; + }; + }; +}; + +&m4_spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_spi4_pins_a>; + status = "okay"; +}; + + +&m4_timers2 { + status = "okay"; +}; + +&m4_timers1 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_pwm1_pins_a_ch1>; + status = "okay"; +}; + +&m4_uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_uart7_pins_a>; + status = "okay"; +}; + +&pinctrl { + m4_leds_orange_pins: m4-leds-orange-0 { + pins { + pinmux = ; + }; + }; + + m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 { + pins { + pinmux = ; + }; + }; +}; + +&timers1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-dk2.dts b/arch/arm/boot/dts/stm32mp157f-dk2.dts new file mode 100644 index 000000000000..15a397c4cf5d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-dk2.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xf.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" +#include + +/ { + model = "STMicroelectronics STM32MP157F-DK2 Discovery Board"; + compatible = "st,stm32mp157f-dk2", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel_otm8009a: panel-otm8009a@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&i2c1 { + touchscreen@2a { + compatible = "focaltech,ft6236"; + reg = <0x2a>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + vcc-supply = <&v3v3>; + status = "okay"; + }; + touchscreen@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; + interrupts = <2 2>; + interrupt-parent = <&gpiof>; + interrupt-controller; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + panel = <&panel_otm8009a>; + vcc-supply = <&v3v3>; + status = "okay"; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&rtc { + st,lsco = ; + pinctrl-0 = <&rtc_out2_rmp_pins_a>; + pinctrl-names = "default"; +}; + +/* Wifi */ +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-ed1.dts b/arch/arm/boot/dts/stm32mp157f-ed1.dts new file mode 100644 index 000000000000..29c6833e2896 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-ed1.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xf.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include "stm32mp15xx-edx.dtsi" + +/ { + model = "STMicroelectronics STM32MP157F eval daughter"; + compatible = "st,stm32mp157f-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + gpu_reserved: gpu@f6000000 { + reg = <0xf6000000 0x8000000>; + no-map; + }; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts new file mode 100644 index 000000000000..3d51e48d14fe --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157f-ev1.dts" +#include + +/ { + model = "STMicroelectronics STM32MP157F-EV1 configured to run Linux A7 examples"; + compatible = "st,stm32mp157f-ev1-a7-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157"; + + test_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + status = "okay"; + /* gpio needs vdd core in retention for wakeup */ + power-domains = <&pd_core_ret>; + + button@1 { + label = "PA13"; + linux,code = ; + interrupts-extended = <&gpioa 13 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + wakeup-source; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&dac { + status = "okay"; +}; + +&timers2 { + status = "okay"; +}; + +&timers8 { + status = "okay"; +}; + +&timers12 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts new file mode 100644 index 000000000000..d508be27666a --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157f-ev1.dts" + +/ { + model = "STMicroelectronics STM32MP157F-EV1 configured to run M4 examples"; + compatible = "st,stm32mp157f-ev1-m4-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157"; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&dcmi { + status = "disabled"; +}; + +&dma2 { + status = "disabled"; +}; + +&dmamux1 { + dma-masters = <&dma1>; + dma-channels = <8>; +}; + +&fmc { + status = "disabled"; +}; + +&i2c5 { + status = "disabled"; +}; + +&m4_adc { + vref-supply = <&vdda>; + status = "okay"; +}; + +&m4_crc2 { + status = "okay"; +}; + +&m4_cryp2 { + status = "okay"; +}; + +&m4_dac { + vref-supply = <&vdda>; + status = "okay"; +}; + +&m4_dma2 { + status = "okay"; +}; + +&m4_hash2 { + status = "okay"; +}; + +&m4_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_i2c5_pins_a>; + status = "okay"; +}; + +&m4_qspi { + pinctrl-names = "default"; + pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a + &m4_qspi_bk2_pins_a>; + status = "okay"; +}; + +&m4_rproc { + m4_system_resources { + status = "okay"; + + /* button { + compatible = "rproc-srm-dev"; + interrupt-parent = <&gpioa>; + interrupts = <14 2>; + interrupt-names = "irq"; + status = "okay"; + };*/ + + m4_led: m4_led { + compatible = "rproc-srm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins>; + status = "okay"; + }; + }; +}; + +&m4_rng2 { + status = "okay"; +}; + +&m4_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_spi1_pins_a>; + status = "okay"; +}; + + +&m4_timers2 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_pwm2_pins_a>; + status = "okay"; +}; + +&m4_usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&m4_usart3_pins_a>; + status = "okay"; +}; + +&pinctrl { + m4_leds_orange_pins: m4-leds-orange-0 { + pins { + pinmux = ; + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sai2b { + status = "disabled"; +}; + +&timers2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157f-ev1.dts b/arch/arm/boot/dts/stm32mp157f-ev1.dts new file mode 100644 index 000000000000..6fe600f81388 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157f-ev1.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157f-ed1.dts" +#include "stm32mp15xx-evx.dtsi" +#include + +/ { + model = "STMicroelectronics STM32MP157F eval daughter on eval mother"; + compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel_dsi: panel-dsi@0 { + compatible = "raydium,rm68200"; + reg = <0>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + backlight = <&panel_backlight>; + power-supply = <&v3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&i2c2 { + gt9147: goodix_ts@5d { + compatible = "goodix,gt9147"; + reg = <0x5d>; + panel = <&panel_dsi>; + pinctrl-0 = <&goodix_pins>; + pinctrl-names = "default"; + status = "okay"; + + interrupts = <14 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&stmfx_pinctrl>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp15xa.dtsi b/arch/arm/boot/dts/stm32mp15xa.dtsi new file mode 100644 index 000000000000..5ed7e594f4cd --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xa.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&cpu0_opp_table { + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi index b06a55a2fa18..adc1568a7285 100644 --- a/arch/arm/boot/dts/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/stm32mp15xc.dtsi @@ -4,14 +4,16 @@ * Author: Alexandre Torgue for STMicroelectronics. */ +#include "stm32mp15xa.dtsi" + / { soc { cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; + clocks = <&scmi0_clk CK_SCMI0_CRYP1>; + resets = <&scmi0_reset RST_SCMI0_CRYP1>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xd.dtsi b/arch/arm/boot/dts/stm32mp15xd.dtsi new file mode 100644 index 000000000000..e2f8b1297c33 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xd.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&cpu0_opp_table { + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x2>; + opp-suspend; + }; +}; + +&cpu_thermal { + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_alert: cpu-alert { + temperature = <95000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 1 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp15xf.dtsi b/arch/arm/boot/dts/stm32mp15xf.dtsi new file mode 100644 index 000000000000..77f50b9bda64 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xf.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp15xd.dtsi" + +/ { + soc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&scmi0_clk CK_SCMI0_CRYP1>; + resets = <&scmi0_reset RST_SCMI0_CRYP1>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 93398cfae97e..acff8755d308 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -4,10 +4,16 @@ * Author: Alexandre Torgue for STMicroelectronics. */ +#include "stm32mp15-m4-srm.dtsi" +#include "stm32mp15-m4-srm-pinctrl.dtsi" #include #include / { + aliases { + ethernet0 = ðernet0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -72,7 +78,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-DK"; + label = "STM32MP15-DK"; routing = "Playback" , "MCLK", "Capture" , "MCLK", @@ -81,6 +87,17 @@ status = "okay"; }; + usb_phy_tuning: usb-phy-tuning { + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; + vin: vin { compatible = "regulator-fixed"; regulator-name = "vin"; @@ -124,6 +141,26 @@ status = "okay"; }; +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&crc1 { + status = "okay"; +}; + +&dma1 { + sram = <&dma_pool>; +}; + +&dma2 { + sram = <&dma_pool>; +}; + &dts { status = "okay"; }; @@ -136,6 +173,8 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; + nvmem-cells = <ðernet_mac_address>; + nvmem-cell-names = "mac-address"; mdio0 { #address-cells = <1>; @@ -151,6 +190,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -238,10 +281,34 @@ /delete-property/dmas; /delete-property/dma-names; + stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; @@ -348,23 +415,24 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; + regulator-over-current-protection; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = ; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; regulator-active-discharge = <1>; - }; + }; }; onkey { @@ -442,6 +510,7 @@ mbox-names = "vq0", "vq1", "shutdown"; interrupt-parent = <&exti>; interrupts = <68 1>; + wakeup-source; status = "okay"; }; @@ -469,8 +538,6 @@ sai2a: audio-controller@4400b004 { #clock-cells = <0>; dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; status = "okay"; sai2a_port: port { @@ -528,6 +595,27 @@ status = "disabled"; }; +&spi4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_pins_b>; + pinctrl-1 = <&spi4_sleep_pins_b>; + status = "disabled"; +}; + +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + +&sram { + dma_pool: dma_pool@0 { + reg = <0x50000 0x10000>; + pool; + }; +}; + &timers1 { /* spare dmas for other usage */ /delete-property/dmas; @@ -618,6 +706,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -626,6 +716,8 @@ pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; @@ -648,6 +740,12 @@ phy-names = "usb2-phy"; usb-role-switch; status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; }; &usbphyc { @@ -656,14 +754,12 @@ &usbphyc_port0 { phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; + st,phy-tuning = <&usb_phy_tuning>; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; + st,phy-tuning = <&usb_phy_tuning>; }; &vrefbuf { diff --git a/arch/arm/boot/dts/stm32mp15xx-edx.dtsi b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi new file mode 100644 index 000000000000..3662f449de23 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ + +#include "stm32mp15-m4-srm.dtsi" +#include "stm32mp15-m4-srm-pinctrl.dtsi" +#include +#include + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + aliases { + serial0 = &uart4; + }; + + led { + compatible = "gpio-leds"; + led-blue { + label = "heartbeat"; + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&adc { + /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ + pinctrl-0 = <&adc1_in6_pins_a>; + pinctrl-names = "default"; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "disabled"; + adc1: adc@0 { + st,adc-channels = <0 1 6>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-nsecs = <400>; + status = "okay"; + }; +}; + +&cpu0{ + cpu-supply = <&vddcore>; +}; + +&cpu1{ + cpu-supply = <&vddcore>; +}; + +&crc1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dma1 { + sram = <&dma_pool>; +}; + +&dma2 { + sram = <&dma_pool>; +}; + +&dts { + status = "okay"; +}; + +&hash1 { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + wakeup-source; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&sram { + dma_pool: dma_pool@0 { + reg = <0x50000 0x10000>; + pool; + }; +}; + +&timers6 { + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + timer@5 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-evx.dtsi b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi new file mode 100644 index 000000000000..47a2c8e5ead7 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ + +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + joystick { + compatible = "gpio-keys"; + #size-cells = <0>; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + button-1 { + label = "JoyDown"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + button-3 { + label = "JoyRight"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + button-4 { + label = "JoyUp"; + linux,code = ; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + }; + }; + + panel_backlight: panel-backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + default-on; + status = "okay"; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + + spdif_out_port: port { + spdif_out_endpoint: endpoint { + remote-endpoint = <&sai4a_endpoint>; + }; + }; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + status = "okay"; + + spdif_in_port: port { + spdif_in_endpoint: endpoint { + remote-endpoint = <&spdifrx_endpoint>; + }; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15-EV"; + routing = + "AIF1CLK" , "MCLK1", + "AIF2CLK" , "MCLK1", + "IN1LN" , "MICBIAS2", + "DMIC2DAT" , "MICBIAS1", + "DMIC1DAT" , "MICBIAS1"; + dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port + &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>; + status = "okay"; + }; + + dmic0: dmic-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic0"; + status = "okay"; + + port { + dmic0_endpoint: endpoint { + remote-endpoint = <&dfsdm_endpoint0>; + }; + }; + }; + + dmic1: dmic-1 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic1"; + status = "okay"; + + port { + dmic1_endpoint: endpoint { + remote-endpoint = <&dfsdm_endpoint1>; + }; + }; + }; + + dmic2: dmic-2 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic2"; + status = "okay"; + + port { + dmic2_endpoint: endpoint { + remote-endpoint = <&dfsdm_endpoint2>; + }; + }; + }; + + dmic3: dmic-3 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic3"; + status = "okay"; + + port { + dmic3_endpoint: endpoint { + remote-endpoint = <&dfsdm_endpoint3>; + }; + }; + }; + + usb_phy_tuning: usb-phy-tuning { + st,hs-dc-level = <2>; + st,fs-rftime-tuning; + st,hs-rftime-reduction; + st,hs-current-trim = <15>; + st,hs-impedance-trim = <1>; + st,squelch-level = <3>; + st,hs-rx-offset = <2>; + st,no-lsfs-sc; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +&dcmi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_a>; + pinctrl-1 = <&dcmi_sleep_pins_a>; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov5640_0>; + bus-type = <5>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + pclk-max-frequency = <77000000>; + }; + }; +}; + +&dfsdm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dfsdm_clkout_pins_a + &dfsdm_data1_pins_a &dfsdm_data3_pins_a>; + pinctrl-1 = <&dfsdm_clkout_sleep_pins_a + &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>; + spi-max-frequency = <2048000>; + + clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; + clock-names = "dfsdm", "audio"; + status = "okay"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-dmic"; + st,adc-channels = <3>; + st,adc-channel-names = "dmic_u1"; + st,adc-channel-types = "SPI_R"; + st,adc-channel-clk-src = "CLKOUT"; + st,filter-order = <3>; + status = "okay"; + + asoc_pdm0: dfsdm-dai { + compatible = "st,stm32h7-dfsdm-dai"; + #sound-dai-cells = <0>; + io-channels = <&dfsdm0 0>; + status = "okay"; + + dfsdm0_port: port { + dfsdm_endpoint0: endpoint { + remote-endpoint = <&dmic0_endpoint>; + }; + }; + }; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-dmic"; + st,adc-channels = <0>; + st,adc-channel-names = "dmic_u2"; + st,adc-channel-types = "SPI_F"; + st,adc-channel-clk-src = "CLKOUT"; + st,filter-order = <3>; + st,adc-alt-channel = <1>; + status = "okay"; + + asoc_pdm1: dfsdm-dai { + compatible = "st,stm32h7-dfsdm-dai"; + #sound-dai-cells = <0>; + io-channels = <&dfsdm1 0>; + status = "okay"; + + dfsdm1_port: port { + dfsdm_endpoint1: endpoint { + remote-endpoint = <&dmic1_endpoint>; + }; + }; + }; + }; + + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-dmic"; + st,adc-channels = <2>; + st,adc-channel-names = "dmic_u3"; + st,adc-channel-types = "SPI_F"; + st,adc-channel-clk-src = "CLKOUT"; + st,adc-alt-channel = <1>; + st,filter-order = <3>; + status = "okay"; + + asoc_pdm2: dfsdm-dai { + compatible = "st,stm32h7-dfsdm-dai"; + #sound-dai-cells = <0>; + io-channels = <&dfsdm2 0>; + status = "okay"; + + dfsdm2_port: port { + dfsdm_endpoint2: endpoint { + remote-endpoint = <&dmic2_endpoint>; + }; + }; + }; + }; + + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-dmic"; + st,adc-channels = <1>; + st,adc-channel-names = "dmic_u4"; + st,adc-channel-types = "SPI_R"; + st,adc-channel-clk-src = "CLKOUT"; + st,filter-order = <3>; + status = "okay"; + + asoc_pdm3: dfsdm-dai { + compatible = "st,stm32h7-dfsdm-dai"; + #sound-dai-cells = <0>; + io-channels = <&dfsdm3 0>; + status = "okay"; + + dfsdm3_port: port { + dfsdm_endpoint3: endpoint { + remote-endpoint = <&dmic3_endpoint>; + }; + }; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + nvmem-cells = <ðernet_mac_address>; + nvmem-cell-names = "mac-address"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "okay"; + + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&hdp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>; + pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>; + status = "disabled"; + + muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) | + STM32_HDP(6, HDP6_GPOVAL_6) | + STM32_HDP(7, HDP7_GPOVAL_7))>; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + wm8994: wm8994@1b { + compatible = "wlf,wm8994"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + + DBVDD-supply = <&vdd>; + SPKVDD1-supply = <&vdd>; + SPKVDD2-supply = <&vdd>; + AVDD2-supply = <&v1v8>; + CPVDD-supply = <&v1v8>; + + wlf,ldoena-always-driven; + + clocks = <&sai2a>; + clock-names = "MCLK1"; + + wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + wm8994_tx_port: port@0 { + reg = <0>; + wm8994_tx_endpoint: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + + wm8994_rx_port: port@1 { + reg = <1>; + wm8994_rx_endpoint: endpoint { + remote-endpoint = <&sai2b_endpoint>; + }; + }; + }; + }; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + DOVDD-supply = <&v2v8>; + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&dcmi_0>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + pclk-max-frequency = <77000000>; + }; + }; + }; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + vdd-supply = <&v3v3>; + + stmfx_pinctrl: pinctrl { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + goodix_pins: goodix { + pins = "gpio14"; + bias-pull-down; + }; + + joystick_pins: joystick-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + bias-pull-down; + }; + }; + }; +}; + +&i2c4 { + pmic: stpmic@33 { + regulators { + v1v8: ldo6 { + regulator-enable-ramp-delay = <300000>; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + flash1: mx66l51235l@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>; + pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&wm8994_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&wm8994_rx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sai4 { + clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai4a: audio-controller@50027004 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai4a_pins_a>; + pinctrl-1 = <&sai4a_sleep_pins_a>; + dma-names = "tx"; + st,iec60958; + status = "okay"; + + sai4a_port: port { + sai4a_endpoint: endpoint { + remote-endpoint = <&spdif_out_endpoint>; + }; + }; + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + +&spdifrx { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spdifrx_pins_a>; + pinctrl-1 = <&spdifrx_sleep_pins_a>; + status = "okay"; + + spdifrx_port: port { + spdifrx_endpoint: endpoint { + remote-endpoint = <&spdif_in_endpoint>; + }; + }; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + status = "disabled"; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-1 = <&pwm2_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers12 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-1 = <&pwm12_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_b>; + pinctrl-1 = <&usart3_sleep_pins_b>; + pinctrl-2 = <&usart3_idle_pins_b>; + /* + * HW flow control USART3_RTS is optional, and isn't default wired to + * the connector. SB23 needs to be soldered in order to use it, and R77 + * (ETH_CLK) should be removed. + */ + uart-has-rtscts; + status = "disabled"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + st,phy-tuning = <&usb_phy_tuning>; + vbus-supply = <&vbus_sw>; +}; + +&usbphyc_port1 { + st,phy-tuning = <&usb_phy_tuning>; +}; -- 2.17.1