From df2861a1384f3bf2ab8236ee51f8a5ff40e8f45b Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Fri, 12 Oct 2018 11:49:18 +0200 Subject: [PATCH] Add support for silicon revB --- src/jtag/drivers/cmsis_dap_usb.c | 4 +- src/jtag/drivers/libusb0_common.c | 7 ++ src/jtag/drivers/libusb1_common.c | 7 ++ tcl/board/stm32mp15x_dk2.cfg | 2 +- tcl/board/stm32mp15x_ev1_jlink_jtag.cfg | 2 +- tcl/board/stm32mp15x_ev1_jlink_swd.cfg | 2 +- tcl/board/stm32mp15x_ev1_stlink_jtag.cfg | 2 +- tcl/board/stm32mp15x_ev1_stlink_swd.cfg | 2 +- tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg | 2 +- tcl/board/stm32mp15x_ev1_ulink2_swd.cfg | 2 +- tcl/target/stm32mp15x.cfg | 11 ++- tcl/target/stm32mp15x_stpmic1.cfg | 113 +++++++++++++++++++++++++++++++ tcl/target/stm32mp15x_stpmu1.cfg | 113 ------------------------------- 13 files changed, 145 insertions(+), 124 deletions(-) diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c index 4ee4836..9e723b5 100644 --- a/src/jtag/drivers/cmsis_dap_usb.c +++ b/src/jtag/drivers/cmsis_dap_usb.c @@ -895,9 +895,7 @@ static int cmsis_dap_init(void) retval = cmsis_dap_swd_open(); if (retval != ERROR_OK) return retval; - } - - if (cmsis_dap_handle == NULL) { + } else { /* Connect in JTAG mode */ if (!(cmsis_dap_handle->caps & INFO_CAPS_JTAG)) { LOG_ERROR("CMSIS-DAP: JTAG not supported"); diff --git a/src/jtag/drivers/libusb0_common.c b/src/jtag/drivers/libusb0_common.c index 1825543..04f88b6 100644 --- a/src/jtag/drivers/libusb0_common.c +++ b/src/jtag/drivers/libusb0_common.c @@ -68,6 +68,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], struct jtag_libusb_device_handle **out) { int retval = -ENODEV; + bool serial_mismatch = false; struct jtag_libusb_device_handle *libusb_handle; usb_init(); @@ -90,14 +91,20 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], /* Device must be open to use libusb_get_string_descriptor_ascii. */ if (serial != NULL && !string_descriptor_equal(libusb_handle, dev->descriptor.iSerialNumber, serial)) { + serial_mismatch = true; usb_close(libusb_handle); continue; } *out = libusb_handle; retval = 0; + serial_mismatch = false; break; } } + + if (serial_mismatch) + LOG_DEBUG("No device matches the serial string"); + return retval; } diff --git a/src/jtag/drivers/libusb1_common.c b/src/jtag/drivers/libusb1_common.c index a1db86f..0ec5fb9 100644 --- a/src/jtag/drivers/libusb1_common.c +++ b/src/jtag/drivers/libusb1_common.c @@ -72,6 +72,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], { int cnt, idx, errCode; int retval = ERROR_FAIL; + bool serial_mismatch = false; struct jtag_libusb_device_handle *libusb_handle = NULL; if (libusb_init(&jtag_libusb_context) < 0) @@ -99,6 +100,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], /* Device must be open to use libusb_get_string_descriptor_ascii. */ if (serial != NULL && !string_descriptor_equal(libusb_handle, dev_desc.iSerialNumber, serial)) { + serial_mismatch = true; libusb_close(libusb_handle); continue; } @@ -106,10 +108,15 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[], /* Success. */ *out = libusb_handle; retval = ERROR_OK; + serial_mismatch = false; break; } if (cnt >= 0) libusb_free_device_list(devs, 1); + + if (serial_mismatch) + LOG_DEBUG("No device matches the serial string"); + return retval; } diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg index 82617c5..8d673fa 100644 --- a/tcl/board/stm32mp15x_dk2.cfg +++ b/tcl/board/stm32mp15x_dk2.cfg @@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg] transport select stlink_swd -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config srst_only diff --git a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg index 7d74fa6..665dc82 100644 --- a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg +++ b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg @@ -4,6 +4,6 @@ source [find interface/jlink.cfg] transport select jtag -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config trst_and_srst separate diff --git a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg index 33e6ef5..7ca27af 100644 --- a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg +++ b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg @@ -4,6 +4,6 @@ source [find interface/jlink.cfg] transport select swd -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config srst_only diff --git a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg index 6fb1e31..9364c92 100644 --- a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg +++ b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg @@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg] transport select stlink_jtag -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config trst_and_srst separate diff --git a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg index 3c561c9..d8527ee 100644 --- a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg +++ b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg @@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg] transport select stlink_swd -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config srst_only diff --git a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg index 6b10351..c7954ea 100644 --- a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg +++ b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg @@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg] transport select jtag -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config trst_and_srst separate diff --git a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg index 5495bc3..b00cc61 100644 --- a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg +++ b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg @@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg] transport select swd -source [find target/stm32mp15x_stpmu1.cfg] +source [find target/stm32mp15x_stpmic1.cfg] reset_config srst_only diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg index 0def780..5d7e230 100644 --- a/tcl/target/stm32mp15x.cfg +++ b/tcl/target/stm32mp15x.cfg @@ -77,7 +77,7 @@ proc delayed_reset_halt_cpu0 { } { global _CHIPNAME global arp_reset_mode - set rom_halt_pc 0x0000688c + set rom_halt_pc 0x000079ac # only "reset halt" or "reset init" if { 0 != [ string compare "$arp_reset_mode" "run" ] } { @@ -85,6 +85,15 @@ proc delayed_reset_halt_cpu0 { } { targets $_CHIPNAME.cpu0 arp_reset_default_handler post $_CHIPNAME.cpu0 + # quick test for cut1.0, check bootrom + set v "" + ap0_non_secure_access + mem2array v 32 0x0000a000 1 phys + ap0_secure_access + if { $v(0) == 0x1e494610 } { + set rom_halt_pc 0x0000688c + } + poll on catch { $_CHIPNAME.cpu0 arp_waitstate halted 1000 } bp $rom_halt_pc 2 hw diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg new file mode 100644 index 0000000..c080441 --- /dev/null +++ b/tcl/target/stm32mp15x_stpmic1.cfg @@ -0,0 +1,113 @@ +# script for stm32mp15x family with companion PMIC STPMIC1 + +source [find target/stm32mp15x.cfg] + +$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }} + +# Wait for expression to be true with a timeout of 200ms +proc wait_state {condition} { + for {set t 0} {$t < 200} {incr t} { + if {[uplevel 1 $condition] == 0} { + return + } + sleep 1 + } + return -code 1 "Timed out" +} + +proc mrw_phys {reg} { + set value "" + mem2array value 32 $reg 1 phys + return $value(0) +} + +proc mmw_phys {reg setbits clearbits} { + set old [mrw_phys $reg] + set new [expr ($old & ~$clearbits) | $setbits] + mww phys $reg $new +} + +# Set mask_reset bits in PMIC to keep all powers on at next reset event +# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD +# This procedure requires Secure memory access +proc pmic_init {} { + global _CHIPNAME + + targets $_CHIPNAME.cpu0 + $_CHIPNAME.dap apsel 0 + + set RCC_BASE 0x50000000 + set GPIO_BASE 0x54004000 + set I2C_BASE 0x5c002000 + + # i2c @ 100kHz, rise 100ns, fall 100ns + # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz + set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b} + + mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI) + mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck) + + mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1 + mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST + mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST + + mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ) + mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF + mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain + mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed + mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down + mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6 + + set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3] + mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv] + mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1 + mww phys [expr $I2C_BASE + 0x004] 0x02043066 + wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS + mww phys [expr $I2C_BASE + 0x028] 0x18 + wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS + mww phys [expr $I2C_BASE + 0x028] 0x0f + wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS + mww phys [expr $I2C_BASE + 0x028] 0x00 + wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS + mww phys [expr $I2C_BASE + 0x028] 0x6f + wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF + mww phys [expr $I2C_BASE + 0x01c] 0x00000020 + mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe + +# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4) +# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ) +} + +# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we +# are in a debug session. This will force them (at next reboot) to program +# the PMIC for keeping powered-on the debug unit during reset. +proc set_pmic_in_backup_reg {} { + global _CHIPNAME + + targets $_CHIPNAME.cpu0 + $_CHIPNAME.dap apsel 0 + + mmw_phys 0x5c00a150 0x00010000 0x00000000 +} + +proc clear_pmic_in_backup_reg {} { + global _CHIPNAME + + targets $_CHIPNAME.cpu0 + $_CHIPNAME.dap apsel 0 + + mmw_phys 0x5c00a150 0x00000000 0x00010000 +} + +# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown +rename init _init +proc init {} { + _init + set_pmic_in_backup_reg +} + +rename shutdown _shutdown +proc shutdown {} { + clear_pmic_in_backup_reg + _shutdown +} diff --git a/tcl/target/stm32mp15x_stpmu1.cfg b/tcl/target/stm32mp15x_stpmu1.cfg deleted file mode 100644 index 413abf2..0000000 --- a/tcl/target/stm32mp15x_stpmu1.cfg +++ /dev/null @@ -1,113 +0,0 @@ -# script for stm32mp15x family with companion PMIC STPMU1 - -source [find target/stm32mp15x.cfg] - -$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }} - -# Wait for expression to be true with a timeout of 200ms -proc wait_state {condition} { - for {set t 0} {$t < 200} {incr t} { - if {[uplevel 1 $condition] == 0} { - return - } - sleep 1 - } - return -code 1 "Timed out" -} - -proc mrw_phys {reg} { - set value "" - mem2array value 32 $reg 1 phys - return $value(0) -} - -proc mmw_phys {reg setbits clearbits} { - set old [mrw_phys $reg] - set new [expr ($old & ~$clearbits) | $setbits] - mww phys $reg $new -} - -# Set mask_reset bits in PMIC to keep all powers on at next reset event -# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD -# This procedure requires Secure memory access -proc pmic_init {} { - global _CHIPNAME - - targets $_CHIPNAME.cpu0 - $_CHIPNAME.dap apsel 0 - - set RCC_BASE 0x50000000 - set GPIO_BASE 0x54004000 - set I2C_BASE 0x5c002000 - - # i2c @ 100kHz, rise 100ns, fall 100ns - # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz - set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b} - - mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI) - mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck) - - mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1 - mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST - mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST - - mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ) - mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF - mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain - mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed - mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down - mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6 - - set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3] - mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv] - mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1 - mww phys [expr $I2C_BASE + 0x004] 0x02043066 - wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS - mww phys [expr $I2C_BASE + 0x028] 0x18 - wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS - mww phys [expr $I2C_BASE + 0x028] 0x0f - wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS - mww phys [expr $I2C_BASE + 0x028] 0x00 - wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS - mww phys [expr $I2C_BASE + 0x028] 0x6f - wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF - mww phys [expr $I2C_BASE + 0x01c] 0x00000020 - mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe - -# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4) -# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ) -} - -# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we -# are in a debug session. This will force them (at next reboot) to program -# the PMIC for keeping powered-on the debug unit during reset. -proc set_pmic_in_backup_reg {} { - global _CHIPNAME - - targets $_CHIPNAME.cpu0 - $_CHIPNAME.dap apsel 0 - - mmw_phys 0x5c00a150 0x00010000 0x00000000 -} - -proc clear_pmic_in_backup_reg {} { - global _CHIPNAME - - targets $_CHIPNAME.cpu0 - $_CHIPNAME.dap apsel 0 - - mmw_phys 0x5c00a150 0x00000000 0x00010000 -} - -# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown -rename init _init -proc init {} { - _init - set_pmic_in_backup_reg -} - -rename shutdown _shutdown -proc shutdown {} { - clear_pmic_in_backup_reg - _shutdown -} -- 2.7.4