12461 lines
323 KiB
Diff
12461 lines
323 KiB
Diff
From 52b77d7689df6579e251a92b3911b13b3124d363 Mon Sep 17 00:00:00 2001
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From: Christophe Priouzeau <christophe.priouzeau@st.com>
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Date: Fri, 10 Apr 2020 14:49:54 +0200
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Subject: [PATCH 20/23] ARM-stm32mp1-r1-DEVICETREE
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---
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.../devicetree/bindings/arm/stm32/stm32.yaml | 5 +-
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.../bindings/clock/st,stm32mp1-rcc.txt | 5 +-
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.../bindings/connector/usb-connector.txt | 2 +
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.../bindings/cpufreq/stm32-cpufreq.txt | 61 +
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.../display/panel/orisetech,otm8009a.txt | 23 -
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.../display/panel/orisetech,otm8009a.yaml | 53 +
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.../display/panel/raydium,rm68200.txt | 25 -
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.../display/panel/raydium,rm68200.yaml | 52 +
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.../devicetree/bindings/dma/stm32-dma.txt | 36 +-
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.../devicetree/bindings/dma/stm32-dmamux.txt | 5 +-
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.../devicetree/bindings/dma/stm32-mdma.txt | 66 +-
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.../devicetree/bindings/hwlock/hwlock.txt | 27 +-
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.../bindings/hwlock/st,stm32-hwspinlock.txt | 6 +-
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.../devicetree/bindings/i2c/i2c-stm32.txt | 12 +-
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.../iio/adc/sigma-delta-modulator.txt | 3 +
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.../bindings/iio/adc/st,stm32-adc.txt | 2 +
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.../iio/timer/stm32-timer-trigger.txt | 9 +
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.../interrupt-controller/st,stm32-exti.txt | 30 +-
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.../devicetree/bindings/mailbox/arm-smc.yaml | 96 ++
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.../bindings/mailbox/stm32-ipcc.txt | 4 +-
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.../bindings/media/video-interfaces.txt | 2 +
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.../bindings/mfd/st,stm32mp1-pwr.txt | 57 +
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.../devicetree/bindings/mmc/mmci.txt | 2 +
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.../bindings/perf/stm32-ddr-pmu.txt | 18 +
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.../bindings/phy/phy-stm32-usbphyc.txt | 59 +-
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.../bindings/pinctrl/st,stm32-pinctrl.yaml | 8 +
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.../devicetree/bindings/pwm/pwm-stm32.txt | 8 +-
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.../bindings/remoteproc/rproc-srm.txt | 58 +
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.../bindings/remoteproc/stm32-rproc.txt | 13 +
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.../devicetree/bindings/rtc/st,stm32-rtc.txt | 10 +-
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.../bindings/serial/st,stm32-usart.txt | 46 +-
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.../bindings/soc/stm32/stm32_hdp.txt | 39 +
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.../devicetree/bindings/usb/dwc2.txt | 8 +
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.../devicetree/bindings/usb/generic-ehci.yaml | 5 +
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.../bindings/usb/st,typec-stusb.txt | 48 +
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arch/arm/boot/dts/Makefile | 19 +-
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arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 157 ++
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arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 1411 +++++++++++++++++
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.../dts/{stm32mp157c.dtsi => stm32mp151.dtsi} | 941 ++++++++---
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arch/arm/boot/dts/stm32mp153.dtsi | 54 +
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.../boot/dts/stm32mp157-m4-srm-pinctrl.dtsi | 524 ++++++
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arch/arm/boot/dts/stm32mp157-m4-srm.dtsi | 442 ++++++
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arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 925 -----------
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arch/arm/boot/dts/stm32mp157.dtsi | 32 +
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arch/arm/boot/dts/stm32mp157a-avenger96.dts | 17 +-
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arch/arm/boot/dts/stm32mp157a-dk1.dts | 431 +----
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arch/arm/boot/dts/stm32mp157a-ed1.dts | 52 +
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arch/arm/boot/dts/stm32mp157a-ev1.dts | 86 +
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.../boot/dts/stm32mp157c-dk2-a7-examples.dts | 46 +
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.../boot/dts/stm32mp157c-dk2-m4-examples.dts | 129 ++
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arch/arm/boot/dts/stm32mp157c-dk2.dts | 126 +-
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arch/arm/boot/dts/stm32mp157c-ed1.dts | 317 +---
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.../boot/dts/stm32mp157c-ev1-a7-examples.dts | 53 +
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.../boot/dts/stm32mp157c-ev1-m4-examples.dts | 146 ++
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arch/arm/boot/dts/stm32mp157c-ev1.dts | 293 +---
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arch/arm/boot/dts/stm32mp157d-dk1.dts | 44 +
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arch/arm/boot/dts/stm32mp157d-ed1.dts | 52 +
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arch/arm/boot/dts/stm32mp157d-ev1.dts | 86 +
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.../boot/dts/stm32mp157f-dk2-a7-examples.dts | 46 +
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.../boot/dts/stm32mp157f-dk2-m4-examples.dts | 129 ++
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arch/arm/boot/dts/stm32mp157f-dk2.dts | 185 +++
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arch/arm/boot/dts/stm32mp157f-ed1.dts | 56 +
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.../boot/dts/stm32mp157f-ev1-a7-examples.dts | 53 +
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.../boot/dts/stm32mp157f-ev1-m4-examples.dts | 146 ++
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arch/arm/boot/dts/stm32mp157f-ev1.dts | 86 +
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arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi | 90 --
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arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi | 62 -
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arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi | 78 -
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arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi | 62 -
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arch/arm/boot/dts/stm32mp15xa.dtsi | 13 +
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arch/arm/boot/dts/stm32mp15xc.dtsi | 20 +
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arch/arm/boot/dts/stm32mp15xd.dtsi | 42 +
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arch/arm/boot/dts/stm32mp15xf.dtsi | 20 +
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arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 768 +++++++++
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arch/arm/boot/dts/stm32mp15xx-edx.dtsi | 408 +++++
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arch/arm/boot/dts/stm32mp15xx-evx.dtsi | 680 ++++++++
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arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi | 85 +
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arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi | 57 +
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arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi | 73 +
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arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi | 57 +
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include/dt-bindings/clock/stm32mp1-clks.h | 33 +
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include/dt-bindings/mfd/stm32f4-rcc.h | 1 -
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include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
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include/dt-bindings/reset/stm32mp1-resets.h | 13 +
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include/dt-bindings/rtc/rtc-stm32.h | 13 +
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include/dt-bindings/soc/stm32-hdp.h | 108 ++
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86 files changed, 8088 insertions(+), 2583 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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delete mode 100644 Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
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create mode 100644 Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml
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delete mode 100644 Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
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create mode 100644 Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml
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create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml
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create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
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create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt
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create mode 100644 Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
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create mode 100644 Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
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create mode 100644 Documentation/devicetree/bindings/usb/st,typec-stusb.txt
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create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
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rename arch/arm/boot/dts/{stm32mp157c.dtsi => stm32mp151.dtsi} (59%)
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create mode 100644 arch/arm/boot/dts/stm32mp153.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp157-m4-srm-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp157-m4-srm.dtsi
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delete mode 100644 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp157.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp157a-ed1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157a-ev1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157d-dk1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157d-ed1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157d-ev1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-ed1.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
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create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1.dts
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delete mode 100644 arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
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delete mode 100644 arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
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delete mode 100644 arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
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delete mode 100644 arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xa.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xc.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xd.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xf.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xx-edx.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xx-evx.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
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create mode 100644 arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
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create mode 100644 include/dt-bindings/rtc/rtc-stm32.h
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create mode 100644 include/dt-bindings/soc/stm32-hdp.h
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diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
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index 4d194f1eb..c9d74357b 100644
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--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
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+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
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@@ -27,5 +27,8 @@ properties:
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- items:
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- enum:
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- arrow,stm32mp157a-avenger96 # Avenger96
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- - const: st,stm32mp157
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+ - enum:
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+ - st,stm32mp157
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+ - st,stm32mp153
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+ - st,stm32mp151
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...
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diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
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index fb9495ea5..1f1ec3446 100644
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--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
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+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
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@@ -12,7 +12,7 @@ binding usage.
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Required properties:
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-- compatible: "st,stm32mp1-rcc", "syscon"
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+- compatible: "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"
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- reg: should be register base and length as documented in the datasheet
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- #clock-cells: 1, device nodes should specify the clock in their
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"clocks" property, containing a phandle to the clock device node,
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@@ -23,7 +23,8 @@ Required properties:
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Example:
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rcc: rcc@50000000 {
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- compatible = "st,stm32mp1-rcc", "syscon";
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+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc",
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+ "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt
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index d35798718..5c0bb0395 100644
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--- a/Documentation/devicetree/bindings/connector/usb-connector.txt
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+++ b/Documentation/devicetree/bindings/connector/usb-connector.txt
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@@ -34,6 +34,8 @@ Optional properties for usb-b-connector:
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Optional properties for usb-c-connector:
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- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
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connector has power support.
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+- power-opmode: should be one of "default", "1.5A", "3.0A" or
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+ "usb_power_delivery" if typec connector has power support.
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- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
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or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
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- data-role: should be one of "host", "device", "dual"(DRD) if typec
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diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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new file mode 100644
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index 000000000..1292eb261
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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@@ -0,0 +1,61 @@
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+STM32 CPUFreq and OPP bindings
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+==============================
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+
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+STM32 CPUFreq driver needs to read chip information from the SoC to list
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+available OPPs. Then it depends on cpufreq-dt bindings.
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+
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+Required properties:
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+--------------------
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+- clocks: Phandle to the cpu clock "cpu".
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+- clocks-name: Should contain "cpu".
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+- nvmem-cells: Phandle to nvmem cell that contains "part_number".
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+- nvmem-cell-names: Must be "part_number".
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+- operating-points-v2: Phandle to operating points table. See ../power/opp.txt
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+ for more details.
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+
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+Optional properties:
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+--------------------
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+See cpufreq-dt.txt for optional properties.
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+
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+Examples:
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+---------
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <0>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ nvmem-cells = <&part_number_otp>;
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+ nvmem-cell-names = "part_number";
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+ };
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+
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+ cpu1: cpu@1 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <1>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ };
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+ };
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+
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+ cpu0_opp_table: cpu0-opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
|
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+
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+ opp-650000000 {
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+ opp-hz = /bits/ 64 <650000000>;
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+ opp-microvolt = <1200000>;
|
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+ opp-supported-hw = <0x1>;
|
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+ };
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
|
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+ opp-microvolt = <1350000>;
|
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+ opp-supported-hw = <0x2>;
|
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+ };
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+ };
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diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
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deleted file mode 100644
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index 203b03eef..000000000
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--- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
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+++ /dev/null
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@@ -1,23 +0,0 @@
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-Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
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-
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-The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
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-a MIPI-DSI video interface. Its backlight is managed through the DSI link.
|
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-
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-Required properties:
|
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- - compatible: "orisetech,otm8009a"
|
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- - reg: the virtual channel number of a DSI peripheral
|
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-
|
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-Optional properties:
|
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- - reset-gpios: a GPIO spec for the reset pin (active low).
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- - power-supply: phandle of the regulator that provides the supply voltage.
|
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-
|
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-Example:
|
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-&dsi {
|
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- ...
|
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- panel@0 {
|
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- compatible = "orisetech,otm8009a";
|
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- reg = <0>;
|
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- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
|
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- power-supply = <&v1v8>;
|
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- };
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-};
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diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml
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new file mode 100644
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index 000000000..6eda24035
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml
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@@ -0,0 +1,53 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/panel/orisetech,otm8009a.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
|
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+title: Orise Tech OTM8009A 3.97" 480x800 panel
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+
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+maintainers:
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+ - Yannick Fertre <yannick.fertre@st.com>
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+
|
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+description:
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+ The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
|
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+ a MIPI-DSI video interface. Its backlight is managed through the DSI link.
|
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+
|
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+properties:
|
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+ compatible:
|
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+ const: orisetech,otm8009a
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+
|
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+ power-supply: true
|
|
+ reset-gpios: true
|
|
+ backlight: true
|
|
+ port: true
|
|
+ reg: true
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - port
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ #include <dt-bindings/gpio/gpio.h>
|
|
+ display1: display {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ panel {
|
|
+ compatible = "orisetech,otm8009a";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
|
|
+ power-supply = <&v1v8>;
|
|
+
|
|
+ port {
|
|
+ panel_in_dsi: endpoint {
|
|
+ remote-endpoint = <&controller_out_dsi>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+...
|
|
diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
|
|
deleted file mode 100644
|
|
index cbb79ef3b..000000000
|
|
--- a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
|
|
+++ /dev/null
|
|
@@ -1,25 +0,0 @@
|
|
-Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
|
|
-
|
|
-The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
|
|
-panel connected using a MIPI-DSI video interface.
|
|
-
|
|
-Required properties:
|
|
- - compatible: "raydium,rm68200"
|
|
- - reg: the virtual channel number of a DSI peripheral
|
|
-
|
|
-Optional properties:
|
|
- - reset-gpios: a GPIO spec for the reset pin (active low).
|
|
- - power-supply: phandle of the regulator that provides the supply voltage.
|
|
- - backlight: phandle of the backlight device attached to the panel.
|
|
-
|
|
-Example:
|
|
-&dsi {
|
|
- ...
|
|
- panel@0 {
|
|
- compatible = "raydium,rm68200";
|
|
- reg = <0>;
|
|
- reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
- power-supply = <&v1v8>;
|
|
- backlight = <&pwm_backlight>;
|
|
- };
|
|
-};
|
|
diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml
|
|
new file mode 100644
|
|
index 000000000..2bbd4a0cb
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml
|
|
@@ -0,0 +1,52 @@
|
|
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/display/panel/raydium,rm68200.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: Raydium RM68200 5.5" 720x1280 panel
|
|
+
|
|
+maintainers:
|
|
+ - Yannick Fertre <yannick.fertre@st.com>
|
|
+
|
|
+description:
|
|
+ The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
|
|
+ panel connected using a MIPI-DSI video interface.
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ const: raydium,rm68200
|
|
+
|
|
+ power-supply: true
|
|
+ reset-gpios: true
|
|
+ backlight: true
|
|
+ port: true
|
|
+ reg: true
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - port
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ #include <dt-bindings/gpio/gpio.h>
|
|
+ display0: display {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ panel {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ power-supply = <&v1v8>;
|
|
+ port {
|
|
+ panel_in_dsi: endpoint {
|
|
+ remote-endpoint = <&controller_out_dsi>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+...
|
|
diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
|
|
index c5f519097..11ee1e9f8 100644
|
|
--- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
|
|
+++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
|
|
@@ -17,6 +17,12 @@ Optional properties:
|
|
- resets: Reference to a reset controller asserting the DMA controller
|
|
- st,mem2mem: boolean; if defined, it indicates that the controller supports
|
|
memory-to-memory transfer
|
|
+- dmas: A list of eight dma specifiers, one for each entry in dma-names.
|
|
+ Refer to stm32-mdma.txt for more details.
|
|
+- dma-names: should contain "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6" and
|
|
+ "ch7" and represents each STM32 DMA channel connected to a STM32 MDMA one.
|
|
+- memory-region : phandle to a node describing memory to be used for
|
|
+ M2M intermediate transfer between DMA and MDMA.
|
|
|
|
Example:
|
|
|
|
@@ -36,6 +42,16 @@ Example:
|
|
st,mem2mem;
|
|
resets = <&rcc 150>;
|
|
dma-requests = <8>;
|
|
+ dmas = <&mdma1 8 0x10 0x1200000a 0x40026408 0x00000020 1>,
|
|
+ <&mdma1 9 0x10 0x1200000a 0x40026408 0x00000800 1>,
|
|
+ <&mdma1 10 0x10 0x1200000a 0x40026408 0x00200000 1>,
|
|
+ <&mdma1 11 0x10 0x1200000a 0x40026408 0x08000000 1>,
|
|
+ <&mdma1 12 0x10 0x1200000a 0x4002640C 0x00000020 1>,
|
|
+ <&mdma1 13 0x10 0x1200000a 0x4002640C 0x00000800 1>,
|
|
+ <&mdma1 14 0x10 0x1200000a 0x4002640C 0x00200000 1>,
|
|
+ <&mdma1 15 0x10 0x1200000a 0x4002640C 0x08000000 1>;
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
+ memory-region = <&sram_dmapool>;
|
|
};
|
|
|
|
* DMA client
|
|
@@ -62,13 +78,25 @@ channel: a phandle to the DMA controller plus the following four integer cells:
|
|
0x1: medium
|
|
0x2: high
|
|
0x3: very high
|
|
-4. A 32bit bitfield value specifying DMA features which are device dependent:
|
|
+4. A bitfield value specifying DMA features which are device dependent:
|
|
-bit 0-1: DMA FIFO threshold selection
|
|
0x0: 1/4 full FIFO
|
|
0x1: 1/2 full FIFO
|
|
0x2: 3/4 full FIFO
|
|
0x3: full FIFO
|
|
-
|
|
+ -bit 2: DMA direct mode
|
|
+ 0: FIFO mode: with threshold level selectable with bit 0-1
|
|
+ 1: Direct mode: each DMA request immediately initiates a transfer
|
|
+ from/to the memory.
|
|
+ -bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
|
|
+ Order is given by those 2 bits starting at 0.
|
|
+ Valid only whether Intermediate M2M transfer is set.
|
|
+ For cyclic, whether Intermediate M2M transfer is chosen, any value can
|
|
+ be set: SRAM buffer size will rely on period size and not on this DT
|
|
+ value.
|
|
+ -bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
|
|
+ 0: MDMA not used to generate an intermediate M2M transfer
|
|
+ 1: MDMA used to generate an intermediate M2M transfer.
|
|
|
|
Example:
|
|
|
|
@@ -77,7 +105,7 @@ Example:
|
|
reg = <0x40011000 0x400>;
|
|
interrupts = <37>;
|
|
clocks = <&clk_pclk2>;
|
|
- dmas = <&dma2 2 4 0x10400 0x3>,
|
|
- <&dma2 7 5 0x10200 0x3>;
|
|
+ dmas = <&dma2 2 4 0x10400 0x1>,
|
|
+ <&dma2 7 5 0x10200 0x1>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
|
|
index 1b893b235..8e092d29b 100644
|
|
--- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
|
|
+++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
|
|
@@ -4,9 +4,6 @@ Required properties:
|
|
- compatible: "st,stm32h7-dmamux"
|
|
- reg: Memory map for accessing module
|
|
- #dma-cells: Should be set to <3>.
|
|
- First parameter is request line number.
|
|
- Second is DMA channel configuration
|
|
- Third is Fifo threshold
|
|
For more details about the three cells, please see
|
|
stm32-dma.txt documentation binding file
|
|
- dma-masters: Phandle pointing to the DMA controllers.
|
|
@@ -53,7 +50,7 @@ dma2: dma@40020400 {
|
|
<68>,
|
|
<69>,
|
|
<70>;
|
|
- clocks = <&timer_clk>;
|
|
+ clocks = <&clk_hclk>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
resets = <&rcc 150>;
|
|
diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
|
|
index d18772d6b..077c819a5 100644
|
|
--- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
|
|
+++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
|
|
@@ -10,7 +10,7 @@ Required properties:
|
|
- interrupts: Should contain the MDMA interrupt.
|
|
- clocks: Should contain the input clock of the DMA instance.
|
|
- resets: Reference to a reset controller asserting the DMA controller.
|
|
-- #dma-cells : Must be <5>. See DMA client paragraph for more details.
|
|
+- #dma-cells : Must be <6>. See DMA client paragraph for more details.
|
|
|
|
Optional properties:
|
|
- dma-channels: Number of DMA channels supported by the controller.
|
|
@@ -26,7 +26,7 @@ Example:
|
|
interrupts = <122>;
|
|
clocks = <&timer_clk>;
|
|
resets = <&rcc 992>;
|
|
- #dma-cells = <5>;
|
|
+ #dma-cells = <6>;
|
|
dma-channels = <16>;
|
|
dma-requests = <32>;
|
|
st,ahb-addr-masks = <0x20000000>, <0x00000000>;
|
|
@@ -35,60 +35,64 @@ Example:
|
|
* DMA client
|
|
|
|
DMA clients connected to the STM32 MDMA controller must use the format
|
|
-described in the dma.txt file, using a five-cell specifier for each channel:
|
|
-a phandle to the MDMA controller plus the following five integer cells:
|
|
+described in the dma.txt file, using a six-cell specifier for each channel:
|
|
+a phandle to the MDMA controller plus the following six integer cells:
|
|
|
|
1. The request line number
|
|
2. The priority level
|
|
- 0x00: Low
|
|
- 0x01: Medium
|
|
- 0x10: High
|
|
- 0x11: Very high
|
|
+ 0x0: Low
|
|
+ 0x1: Medium
|
|
+ 0x2: High
|
|
+ 0x3: Very high
|
|
3. A 32bit mask specifying the DMA channel configuration
|
|
-bit 0-1: Source increment mode
|
|
- 0x00: Source address pointer is fixed
|
|
- 0x10: Source address pointer is incremented after each data transfer
|
|
- 0x11: Source address pointer is decremented after each data transfer
|
|
+ 0x0: Source address pointer is fixed
|
|
+ 0x2: Source address pointer is incremented after each data transfer
|
|
+ 0x3: Source address pointer is decremented after each data transfer
|
|
-bit 2-3: Destination increment mode
|
|
- 0x00: Destination address pointer is fixed
|
|
- 0x10: Destination address pointer is incremented after each data
|
|
+ 0x0: Destination address pointer is fixed
|
|
+ 0x2: Destination address pointer is incremented after each data
|
|
transfer
|
|
- 0x11: Destination address pointer is decremented after each data
|
|
+ 0x3: Destination address pointer is decremented after each data
|
|
transfer
|
|
-bit 8-9: Source increment offset size
|
|
- 0x00: byte (8bit)
|
|
- 0x01: half-word (16bit)
|
|
- 0x10: word (32bit)
|
|
- 0x11: double-word (64bit)
|
|
+ 0x0: byte (8bit)
|
|
+ 0x1: half-word (16bit)
|
|
+ 0x2: word (32bit)
|
|
+ 0x3: double-word (64bit)
|
|
-bit 10-11: Destination increment offset size
|
|
- 0x00: byte (8bit)
|
|
- 0x01: half-word (16bit)
|
|
- 0x10: word (32bit)
|
|
- 0x11: double-word (64bit)
|
|
+ 0x0: byte (8bit)
|
|
+ 0x1: half-word (16bit)
|
|
+ 0x2: word (32bit)
|
|
+ 0x3: double-word (64bit)
|
|
-bit 25-18: The number of bytes to be transferred in a single transfer
|
|
(min = 1 byte, max = 128 bytes)
|
|
-bit 29:28: Trigger Mode
|
|
- 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
|
|
- 0x01: Each MDMA request triggers a block transfer (max 64K bytes)
|
|
- 0x10: Each MDMA request triggers a repeated block transfer
|
|
- 0x11: Each MDMA request triggers a linked list transfer
|
|
+ 0x0: Each MDMA request triggers a buffer transfer (max 128 bytes)
|
|
+ 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
|
|
+ 0x2: Each MDMA request triggers a repeated block transfer
|
|
+ 0x3: Each MDMA request triggers a linked list transfer
|
|
4. A 32bit value specifying the register to be used to acknowledge the request
|
|
if no HW ack signal is used by the MDMA client
|
|
5. A 32bit mask specifying the value to be written to acknowledge the request
|
|
if no HW ack signal is used by the MDMA client
|
|
+6. A bitfield value specifying if the MDMA client wants to generate M2M
|
|
+ transfer with HW trigger (1) or not (0). This bitfield should be only
|
|
+ enabled for M2M transfer triggered by STM32 DMA client. The memory devices
|
|
+ involved in this kind of transfer are SRAM and DDR.
|
|
|
|
Example:
|
|
|
|
i2c4: i2c@5c002000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x5c002000 0x400>;
|
|
- interrupts = <95>,
|
|
- <96>;
|
|
- clocks = <&timer_clk>;
|
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>,
|
|
+ <GIC_SPI 96 IRQ_TYPE_NONE>;
|
|
+ clocks = <&clk_hsi>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
- dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>,
|
|
- <&mdma1 37 0x0 0x40002 0x0 0x0>;
|
|
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
|
|
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt
|
|
index 085d1f5c9..e98088a40 100644
|
|
--- a/Documentation/devicetree/bindings/hwlock/hwlock.txt
|
|
+++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt
|
|
@@ -13,7 +13,7 @@ hwlock providers:
|
|
|
|
Required properties:
|
|
- #hwlock-cells: Specifies the number of cells needed to represent a
|
|
- specific lock.
|
|
+ specific lock. Shall be 1 or 2 (see hwlocks below).
|
|
|
|
hwlock users:
|
|
=============
|
|
@@ -27,6 +27,11 @@ Required properties:
|
|
#hwlock-cells. The list can have just a single hwlock
|
|
or multiple hwlocks, with each hwlock represented by
|
|
a phandle and a corresponding args specifier.
|
|
+ If #hwlock-cells is 1, all of the locks are exclusive
|
|
+ (cannot be used by several users).
|
|
+ If #hwlock-cells is 2, the value of the second cell
|
|
+ defines whether the lock is for exclusive usage (0) or
|
|
+ shared (1) i.e. can be used by several users.
|
|
|
|
Optional properties:
|
|
- hwlock-names: List of hwlock name strings defined in the same order
|
|
@@ -46,14 +51,22 @@ of length 1.
|
|
...
|
|
};
|
|
|
|
-2. Example of a node using multiple specific hwlocks:
|
|
+2. Example of nodes using multiple and shared specific hwlocks:
|
|
|
|
-The following example has a node requesting two hwlocks, a hwlock within
|
|
-the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
|
|
-hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.
|
|
+The following example has a nodeA requesting two hwlocks:
|
|
+- an exclusive one (#hwlock-cells = 1) within the hwlock device node 'hwlock1'
|
|
+- a shared one (#hwlock-cells = 2, second cell = 1) within the hwlock device
|
|
+ node 'hwlock2'.
|
|
+The shared lock is also be used by nodeB.
|
|
|
|
- node {
|
|
+ nodeA {
|
|
...
|
|
- hwlocks = <&hwlock1 2>, <&hwlock2 0 3>;
|
|
+ hwlocks = <&hwlock1 2>, <&hwlock2 0 1>;
|
|
...
|
|
};
|
|
+
|
|
+ nodeB {
|
|
+ ...
|
|
+ hwlocks = <&hwlock2 0 1>;
|
|
+ ...
|
|
+ };
|
|
\ No newline at end of file
|
|
diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt
|
|
index adf4f000e..60a37163b 100644
|
|
--- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt
|
|
+++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt
|
|
@@ -4,8 +4,8 @@ STM32 Hardware Spinlock Device Binding
|
|
Required properties :
|
|
- compatible : should be "st,stm32-hwspinlock".
|
|
- reg : the register address of hwspinlock.
|
|
-- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
|
|
- hwlock, so the number of cells should be <1> here.
|
|
+- #hwlock-cells : should be <2> so the hwlock users use the hwlock id to
|
|
+ represent a specific hwlock and define its shared / exclusive attribute.
|
|
- clock-names : Must contain "hsem".
|
|
- clocks : Must contain a phandle entry for the clock in clock-names, see the
|
|
common clock bindings.
|
|
@@ -16,7 +16,7 @@ Please look at the generic hwlock binding for usage information for consumers,
|
|
Example of hwlock provider:
|
|
hwspinlock@4c000000 {
|
|
compatible = "st,stm32-hwspinlock";
|
|
- #hwlock-cells = <1>;
|
|
+ #hwlock-cells = <2>;
|
|
reg = <0x4c000000 0x400>;
|
|
clocks = <&rcc HSEM>;
|
|
clock-names = "hsem";
|
|
diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
|
|
index ce3df2fff..62ccd03fa 100644
|
|
--- a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
|
|
+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
|
|
@@ -4,13 +4,15 @@ Required properties:
|
|
- compatible: Must be one of the following
|
|
- "st,stm32f4-i2c"
|
|
- "st,stm32f7-i2c"
|
|
+ - "st,stm32mp15-i2c"
|
|
- reg: Offset and length of the register set for the device
|
|
- interrupts: Must contain the interrupt id for I2C event and then the
|
|
interrupt id for I2C error.
|
|
- resets: Must contain the phandle to the reset controller.
|
|
- clocks: Must contain the input clock of the I2C instance.
|
|
- A pinctrl state named "default" must be defined to set pins in mode of
|
|
- operation for I2C transfer
|
|
+ operation for I2C transfer. An optional pinctrl state named "sleep" has to
|
|
+ be defined as well as to put I2C in low power mode in suspend mode.
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
|
|
@@ -34,6 +36,10 @@ Optional properties:
|
|
2nd cell: register offset within SYSCFG
|
|
3rd cell: register bitmask for FMP bit
|
|
For STM32F7, STM32H7 and STM32MP1 only.
|
|
+- st,smbus-alert: enable the SMBus Alert feature
|
|
+- st,smbus-host-notify: enable the SMBus Host-Notify feature
|
|
+- wakeup-source: Enable the possibility to use the I2C as a wakeup-source
|
|
+ For STM32H7 and STM32MP1 only.
|
|
|
|
Example:
|
|
|
|
@@ -60,6 +66,8 @@ Example:
|
|
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
|
|
clocks = <&rcc 1 CLK_I2C1>;
|
|
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
|
|
- pinctrl-names = "default";
|
|
+ pinctrl-1 = <&i2c1_sda_pin_sleep>, <&i2c1_scl_pin_sleep>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x1>;
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
|
|
index 59b92cd32..fa70fda13 100644
|
|
--- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
|
|
+++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt
|
|
@@ -5,6 +5,9 @@ Required properties:
|
|
as a generic SD modulator if modulator not specified in compatible list.
|
|
- #io-channel-cells = <0>: See the IIO bindings section "IIO consumers".
|
|
|
|
+Optional properties:
|
|
+- vref-supply: Phandle to the vref input analog reference voltage.
|
|
+
|
|
Example node:
|
|
|
|
ads1202: adc {
|
|
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
|
|
index 4c0da8c74..8de933146 100644
|
|
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
|
|
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
|
|
@@ -53,6 +53,8 @@ Optional properties:
|
|
analog input switches on stm32mp1.
|
|
- st,syscfg: Phandle to system configuration controller. It can be used to
|
|
control the analog circuitry on stm32mp1.
|
|
+- st,max-clk-rate-hz: Allow to specify desired max clock rate used by analog
|
|
+ circuitry.
|
|
|
|
Contents of a stm32 adc child node:
|
|
-----------------------------------
|
|
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
|
|
index b8e8c769d..4713ff1f5 100644
|
|
--- a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
|
|
+++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
|
|
@@ -9,6 +9,12 @@ Required parameters:
|
|
"st,stm32h7-timer-trigger"
|
|
- reg: Identify trigger hardware block.
|
|
|
|
+Optional properties:
|
|
+- pinctrl-names: Set to "default". An additional "sleep" state can be
|
|
+ defined to set pins in sleep state when in low power.
|
|
+- pinctrl-n: Phandle(s) pointing to pin configuration node for PWM,
|
|
+ respectively for "default" and "sleep" states.
|
|
+
|
|
Example:
|
|
timers@40010000 {
|
|
#address-cells = <1>;
|
|
@@ -21,5 +27,8 @@ Example:
|
|
timer@0 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <0>;
|
|
+ pinctrl-0 = <&tim1_pins>;
|
|
+ pinctrl-1 = <&tim1_sleep_pins>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
};
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
|
|
index cd01b2292..abcf816d6 100644
|
|
--- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
|
|
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
|
|
@@ -18,7 +18,19 @@ Optional properties:
|
|
|
|
- hwlocks: reference to a phandle of a hardware spinlock provider node.
|
|
|
|
-Example:
|
|
+Exti could have several parent interrupt controllers. In this case child nodes
|
|
+are used to describe those "extra" parent controllers. Properties to use are:
|
|
+
|
|
+- interrupt-controller: Indentifies the node as an interrupt controller
|
|
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
|
|
+ specifier, shall be 2
|
|
+- interrupt-parent: Phandle to the interrupt parent node.
|
|
+- st,irq-number: Interrupt number mapped on the parent.
|
|
+
|
|
+See example 2.
|
|
+
|
|
+
|
|
+Example 1:
|
|
|
|
exti: interrupt-controller@40013c00 {
|
|
compatible = "st,stm32-exti";
|
|
@@ -27,3 +39,19 @@ exti: interrupt-controller@40013c00 {
|
|
reg = <0x40013C00 0x400>;
|
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
|
};
|
|
+
|
|
+Example 2:
|
|
+
|
|
+exti: interrupt-controller@5000d000 {
|
|
+ compatible = "st,stm32mp1-exti", "syscon";
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x5000d000 0x400>;
|
|
+
|
|
+ exti_pwr: exti-pwr {
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ interrupt-parent = <&pwr>;
|
|
+ st,irq-number = <6>;
|
|
+ };
|
|
+};
|
|
diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml
|
|
new file mode 100644
|
|
index 000000000..c165946a6
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml
|
|
@@ -0,0 +1,96 @@
|
|
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: ARM SMC Mailbox Interface
|
|
+
|
|
+maintainers:
|
|
+ - Peng Fan <peng.fan@nxp.com>
|
|
+
|
|
+description: |
|
|
+ This mailbox uses the ARM smc (secure monitor call) or hvc (hypervisor
|
|
+ call) instruction to trigger a mailbox-connected activity in firmware,
|
|
+ executing on the very same core as the caller. The value of r0/w0/x0
|
|
+ the firmware returns after the smc call is delivered as a received
|
|
+ message to the mailbox framework, so synchronous communication can be
|
|
+ established. The exact meaning of the action the mailbox triggers as
|
|
+ well as the return value is defined by their users and is not subject
|
|
+ to this binding.
|
|
+
|
|
+ One example use case of this mailbox is the SCMI interface, which uses
|
|
+ shared memory to transfer commands and parameters, and a mailbox to
|
|
+ trigger a function call. This allows SoCs without a separate management
|
|
+ processor (or when such a processor is not available or used) to use
|
|
+ this standardized interface anyway.
|
|
+
|
|
+ This binding describes no hardware, but establishes a firmware interface.
|
|
+ Upon receiving an SMC using the described SMC function identifier, the
|
|
+ firmware is expected to trigger some mailbox connected functionality.
|
|
+ The communication follows the ARM SMC calling convention.
|
|
+ Firmware expects an SMC function identifier in r0 or w0. The supported
|
|
+ identifier is listed in the the arm,func-id property as described below.
|
|
+ The firmware can return one value in the first SMC result register,
|
|
+ it is expected to be an error value, which shall be propagated to the
|
|
+ mailbox client.
|
|
+
|
|
+ Any core which supports the SMC or HVC instruction can be used, as long
|
|
+ as a firmware component running in EL3 or EL2 is handling these calls.
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ oneOf:
|
|
+ - description:
|
|
+ For implementations using ARM SMC instruction.
|
|
+ const: arm,smc-mbox
|
|
+
|
|
+ - description:
|
|
+ For implementations using ARM HVC instruction.
|
|
+ const: arm,hvc-mbox
|
|
+
|
|
+ "#mbox-cells":
|
|
+ const: 0
|
|
+
|
|
+ arm,func-id:
|
|
+ description: |
|
|
+ An single 32-bit value specifying the function ID used by the mailbox.
|
|
+ The function ID follows the ARM SMC calling convention standard.
|
|
+ $ref: /schemas/types.yaml#/definitions/uint32
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - "#mbox-cells"
|
|
+ - arm,func-id
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ sram@93f000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x0 0x93f000 0x0 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0x0 0x93f000 0x1000>;
|
|
+
|
|
+ cpu_scp_lpri: scp-shmem@0 {
|
|
+ compatible = "arm,scmi-shmem";
|
|
+ reg = <0x0 0x200>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ smc_tx_mbox: tx_mbox {
|
|
+ #mbox-cells = <0>;
|
|
+ compatible = "arm,smc-mbox";
|
|
+ arm,func-id = <0xc20000fe>;
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ scmi {
|
|
+ compatible = "arm,scmi";
|
|
+ mboxes = <&smc_tx_mbox>;
|
|
+ mbox-names = "tx";
|
|
+ shmem = <&cpu_scp_lpri>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+...
|
|
diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
|
|
index 1d2b7fee7..139c06a94 100644
|
|
--- a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
|
|
+++ b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
|
|
@@ -14,9 +14,9 @@ Required properties:
|
|
property. Must contain the following entries:
|
|
- "rx"
|
|
- "tx"
|
|
- - "wakeup"
|
|
- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
|
|
- free" and "system wakeup".
|
|
+ free". If "wakeup-source" is set the rx interrupt is the
|
|
+ one used to wake up the system.
|
|
- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
|
|
The data contained in the mbox specifier of the "mboxes"
|
|
property in the client node is the mailbox channel index.
|
|
diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt
|
|
index f884ada0b..aff685a25 100644
|
|
--- a/Documentation/devicetree/bindings/media/video-interfaces.txt
|
|
+++ b/Documentation/devicetree/bindings/media/video-interfaces.txt
|
|
@@ -149,6 +149,8 @@ Optional endpoint properties
|
|
as 0 (normal). This property is valid for serial busses only.
|
|
- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used
|
|
with CCP2, for instance.
|
|
+- pclk-max-frequency: maximum pixel clock frequency admissible by video
|
|
+ host interface.
|
|
|
|
Example
|
|
-------
|
|
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
|
|
new file mode 100644
|
|
index 000000000..eb622387b
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
|
|
@@ -0,0 +1,57 @@
|
|
+STMicroelectronics STM32MP1 Power Management Controller
|
|
+=======================================================
|
|
+
|
|
+The PWR IP is responsible for handling the power related resources such as
|
|
+clocks, power supplies and resets. It provides 6 wake-up pins that are handled
|
|
+by an interrupt-controller. Wake-up pin can be used to wake-up from STANDBY SoC state.
|
|
+
|
|
+Required properties:
|
|
+- compatible should be: "st,stm32mp1-pwr"
|
|
+- reg: should be register base and length as documented in the
|
|
+ datasheet
|
|
+- interrupts: contains the reference to the gic wake-up pin interrupt
|
|
+- interrupt-controller; Enable interrupt controller for wake-up pins.
|
|
+- #interrupt-cells = <3>
|
|
+- wakeup-gpios: contains a list of GPIO spec describing each wake-up pin.
|
|
+
|
|
+Optional Properties:
|
|
+- pwr-supply: main soc power supply
|
|
+
|
|
+Interrupt consumers have to specify 3 cells:
|
|
+ - cell 1: wake-up pin id from 0 to 5
|
|
+ - cell 2: IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_RISING
|
|
+ - cell 3: Pull config: 0 = No Pull, 1=Pull Up, 2=Pull Down
|
|
+
|
|
+
|
|
+Example:
|
|
+
|
|
+ pwr: pwr@50001000 {
|
|
+ compatible = "st,stm32mp1-pwr", "simple-mfd";
|
|
+ reg = <0x50001000 0x400>;
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+
|
|
+ wakeup-gpios = <&gpioa 0 0>, <&gpioa 2 0>,
|
|
+ <&gpioc 13 0>, <&gpioi 8 0>,
|
|
+ <&gpioi 11 0>, <&gpioc 1 0>;
|
|
+
|
|
+ pwr-supply = <&vdd>;
|
|
+ };
|
|
+
|
|
+
|
|
+Example of interrupt user:
|
|
+gpio_keys {
|
|
+ compatible = "gpio-keys";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ button@4 {
|
|
+ label = "WakeUp4";
|
|
+ linux,code = <BTN_4>;
|
|
+ interrupt-parent = <&pwr>;
|
|
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING 1>;
|
|
+ wakeup-source;
|
|
+ };
|
|
+};
|
|
+
|
|
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt
|
|
index 6d3c626e0..4ec921e4b 100644
|
|
--- a/Documentation/devicetree/bindings/mmc/mmci.txt
|
|
+++ b/Documentation/devicetree/bindings/mmc/mmci.txt
|
|
@@ -28,6 +28,8 @@ specific for ux500 variant:
|
|
- st,sig-pin-fbclk : feedback clock signal pin used.
|
|
|
|
specific for sdmmc variant:
|
|
+- reg : a second base register may be defined if a delay
|
|
+ block is present and used for tuning.
|
|
- st,sig-dir : signal direction polarity used for cmd, dat0 dat123.
|
|
- st,neg-edge : data & command phase relation, generated on
|
|
sd clock falling edge.
|
|
diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt
|
|
new file mode 100644
|
|
index 000000000..7533b8964
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt
|
|
@@ -0,0 +1,18 @@
|
|
+* STM32 DDR Performance Monitor (DDRPERFM)
|
|
+
|
|
+Required properties:
|
|
+- compatible: must be "st,stm32-ddr-pmu".
|
|
+- reg: physical address and length of the registers set.
|
|
+- clocks: list of phandles and specifiers to all input clocks listed in
|
|
+ clock-names property.
|
|
+- clock-names: "bus" corresponds to the DDRPERFM bus clock and "ddr" to
|
|
+ the DDR frequency.
|
|
+
|
|
+Example:
|
|
+ ddrperfm: perf@5a007000 {
|
|
+ compatible = "st,stm32-ddr-pmu";
|
|
+ reg = <0x5a007000 0x400>;
|
|
+ clocks = <&rcc DDRPERFM>, <&scmi0_clk CK_SCMI0_PLL2_R>;
|
|
+ clock-names = "bus", "ddr";
|
|
+ };
|
|
+
|
|
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
|
|
index 725ae71ae..156229b2e 100644
|
|
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
|
|
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
|
|
@@ -23,8 +23,11 @@ Required properties:
|
|
- compatible: must be "st,stm32mp1-usbphyc"
|
|
- reg: address and length of the usb phy control register set
|
|
- clocks: phandle + clock specifier for the PLL phy clock
|
|
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
|
|
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
|
|
- #address-cells: number of address cells for phys sub-nodes, must be <1>
|
|
- #size-cells: number of size cells for phys sub-nodes, must be <0>
|
|
+- #clock-cells: number of clock cells for ck_usbo_48m consumer, must be <0>
|
|
|
|
Optional properties:
|
|
- assigned-clocks: phandle + clock specifier for the PLL phy clock
|
|
@@ -34,40 +37,82 @@ Optional properties:
|
|
Required nodes: one sub-node per port the controller provides.
|
|
|
|
Phy sub-nodes
|
|
-==============
|
|
+=============
|
|
|
|
Required properties:
|
|
- reg: phy port index
|
|
- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
|
|
see phy-bindings.txt in the same directory.
|
|
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
|
|
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
|
|
- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
|
|
port#1 and must be <1> for PHY port#2, to select USB controller
|
|
|
|
+Optional properties:
|
|
+- st,phy-tuning : phandle to the usb phy tuning node, see Phy tuning node below
|
|
+
|
|
+Phy tuning node
|
|
+===============
|
|
+
|
|
+It may be necessary to adjust the phy settings to compensate parasitics, which
|
|
+can be due to USB connector/receptacle, routing, ESD protection component, ...
|
|
+
|
|
+Here is the list of all optional parameters to tune the interface of the phy
|
|
+(HS for High-Speed, FS for Full-Speed, LS for Low-Speed)
|
|
+
|
|
+Optional properties:
|
|
+- st,current-boost: <1> current boosting of 1mA
|
|
+ <2> current boosting of 2mA
|
|
+- st,no-lsfs-fb-cap: disables the LS/FS feedback capacitor
|
|
+- st,hs-slew-ctrl: slows the HS driver slew rate by 10%
|
|
+- st,hs-dc-level: <0> decreases the HS driver DC level by 5 to 7mV
|
|
+ <1> increases the HS driver DC level by 5 to 7mV
|
|
+ <2> increases the HS driver DC level by 10 to 14mV
|
|
+- st,fs-rftime-tuning: enables the FS rise/fall tuning option
|
|
+- st,hs-rftime-reduction: enables the HS rise/fall reduction feature
|
|
+- st,hs-current-trim: controls HS driver current trimming for choke
|
|
+- st,hs-impedance-trim: controls HS driver impedance tuning for choke
|
|
+- st,squelch-level: adjusts the squelch DC threshold value
|
|
+- st,hs-rx-gain-eq: enables the HS Rx gain equalizer
|
|
+- st,hs-rx-offset: adjusts the HS Rx offset
|
|
+- st,no-hs-ftime-ctrl: disables the HS fall time control of single
|
|
+ ended signals during pre-emphasis
|
|
+- st,no-lsfs-sc: disables the short circuit protection in LS/FS driver
|
|
+- st,hs-tx-staggering: enables the basic staggering in HS Tx mode
|
|
+
|
|
|
|
Example:
|
|
+ usb_phy_tuning: usb-phy-tuning {
|
|
+ st,current-boost = <2>;
|
|
+ st,no-lfs-fb-cap;
|
|
+ st,hs-dc-level = <2>;
|
|
+ st,hs-rftime-reduction;
|
|
+ st,hs-current-trim = <5>;
|
|
+ st,hs-impedance-trim = <0>;
|
|
+ st,squelch-level = <1>;
|
|
+ st,no-hs-ftime-ctrl;
|
|
+ st,hs-tx-staggering;
|
|
+ };
|
|
+
|
|
usbphyc: usb-phy@5a006000 {
|
|
compatible = "st,stm32mp1-usbphyc";
|
|
reg = <0x5a006000 0x1000>;
|
|
clocks = <&rcc_clk USBPHY_K>;
|
|
resets = <&rcc_rst USBPHY_R>;
|
|
+ vdda1v1-supply = <®11>;
|
|
+ vdda1v8-supply = <®18>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ #clock-cells = <0>;
|
|
|
|
usbphyc_port0: usb-phy@0 {
|
|
reg = <0>;
|
|
phy-supply = <&vdd_usb>;
|
|
- vdda1v1-supply = <®11>;
|
|
- vdda1v8-supply = <®18>
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usbphyc_port1: usb-phy@1 {
|
|
reg = <1>;
|
|
phy-supply = <&vdd_usb>;
|
|
- vdda1v1-supply = <®11>;
|
|
- vdda1v8-supply = <®18>
|
|
#phy-cells = <1>;
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
};
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
|
|
index 400df2da0..4e24a8e86 100644
|
|
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
|
|
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
|
|
@@ -144,9 +144,13 @@ patternProperties:
|
|
* ...
|
|
* 16 : Alternate Function 15
|
|
* 17 : Analog
|
|
+ * 18 : Reserved
|
|
To simplify the usage, macro is available to generate "pinmux" field.
|
|
This macro is available here:
|
|
- include/dt-bindings/pinctrl/stm32-pinfunc.h
|
|
+ Setting the pinmux's function to the Reserved (RSVD) value is used to inform
|
|
+ the driver that it shall not apply the mux setting. This can be used to
|
|
+ reserve some pins, for example to a co-processor not running Linux.
|
|
Some examples of using macro:
|
|
/* GPIO A9 set as alernate function 2 */
|
|
... {
|
|
@@ -160,6 +164,10 @@ patternProperties:
|
|
... {
|
|
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
|
|
};
|
|
+ /* GPIO A9 reserved for co-processor */
|
|
+ ... {
|
|
+ pinmux = <STM32_PINMUX('A', 9, RSVD)>;
|
|
+ };
|
|
|
|
bias-disable:
|
|
type: boolean
|
|
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
|
|
index a8690bfa5..f1620c1fe 100644
|
|
--- a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
|
|
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
|
|
@@ -5,8 +5,9 @@ See ../mfd/stm32-timers.txt for details about the parent node.
|
|
|
|
Required parameters:
|
|
- compatible: Must be "st,stm32-pwm".
|
|
-- pinctrl-names: Set to "default".
|
|
-- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
|
|
+- pinctrl-names: Set to "default". An additional "sleep" state can be
|
|
+ defined to set pins in sleep state when in low power.
|
|
+- pinctrl-n: List of phandles pointing to pin configuration nodes for PWM module.
|
|
For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
|
|
- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
|
|
bindings defined in pwm.txt.
|
|
@@ -32,7 +33,8 @@ Example:
|
|
compatible = "st,stm32-pwm";
|
|
#pwm-cells = <3>;
|
|
pinctrl-0 = <&pwm1_pins>;
|
|
- pinctrl-names = "default";
|
|
+ pinctrl-1 = <&pwm1_sleep_pins>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
st,breakinput = <0 1 5>;
|
|
};
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
|
|
new file mode 100644
|
|
index 000000000..baa6e8e13
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
|
|
@@ -0,0 +1,58 @@
|
|
+Remoteproc System Resource Manager
|
|
+----------------------------------
|
|
+
|
|
+The remoteproc SRM (System Resource Manager) handles resources allocated
|
|
+to remote processors.
|
|
+This makes it possible for remote proc to reserve and initialize system
|
|
+resources for a peripheral assigned to a coprocessor.
|
|
+
|
|
+The devices are grouped in a core node
|
|
+
|
|
+Core
|
|
+====
|
|
+Required properties:
|
|
+- compatible: should be "rproc-srm-core"
|
|
+
|
|
+Dev
|
|
+===
|
|
+Required properties:
|
|
+- compatible: should be "rproc-srm-dev"
|
|
+
|
|
+Optional properties:
|
|
+- reg: register base address and length
|
|
+- clocks: clocks required by the coprocessor
|
|
+- clock-names: see clock-bindings.txt
|
|
+- pinctrl-0: pins configurations required by the coprocessor
|
|
+ The SRM reserves the pins for the coprocessor, which prevents the local
|
|
+ processor to use them.
|
|
+- pinctrl-names: must be "default".
|
|
+- x-supply: power supplies required by the coprocessor
|
|
+- interrupts: external interrupts configurations required by the coprocessor.
|
|
+ This is optional since the configuration is done by the coprocessor.
|
|
+ When defined, the SRM (over)writes the configuration which allows the
|
|
+ interrupt controller to check for configuration conflicts.
|
|
+- interrupt-parent: see interrupts.txt
|
|
+- interrupt-names: see interrupts.txt
|
|
+
|
|
+Example:
|
|
+ system_resources {
|
|
+ compatible = "rproc-srm-core";
|
|
+
|
|
+ mmc0: sdhci@09060000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x09060000 0x100>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_pinctrl_mmc0>;
|
|
+ clock-names = "mmc", "icn";
|
|
+ clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
|
|
+ <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
|
|
+ vdda-supply = <&vdda>;
|
|
+ };
|
|
+
|
|
+ button {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ interrupt-parent = <&gpioa>;
|
|
+ interrupts = <5 1>;
|
|
+ interrupt-names = "gpio_key";
|
|
+ };
|
|
+ };
|
|
diff --git a/Documentation/devicetree/bindings/remoteproc/stm32-rproc.txt b/Documentation/devicetree/bindings/remoteproc/stm32-rproc.txt
|
|
index 5fa915a4b..1188d22bd 100644
|
|
--- a/Documentation/devicetree/bindings/remoteproc/stm32-rproc.txt
|
|
+++ b/Documentation/devicetree/bindings/remoteproc/stm32-rproc.txt
|
|
@@ -21,6 +21,9 @@ Required properties:
|
|
|
|
Optional properties:
|
|
- interrupts: Should contain the watchdog interrupt
|
|
+- wakeup-source: Flag indicating whether remoteproc can wake up the system by
|
|
+ the watchdog interrupt. Only meaningful if the "interrupts"
|
|
+ property is defined.
|
|
- mboxes: This property is required only if the rpmsg/virtio functionality
|
|
is used. List of phandle and mailbox channel specifiers:
|
|
- a channel (a) used to communicate through virtqueues with the
|
|
@@ -48,6 +51,16 @@ Optional properties:
|
|
1st cell: phandle to syscon block
|
|
2nd cell: register offset containing the deep sleep setting
|
|
3rd cell: register bitmask for the deep sleep bit
|
|
+- st,syscfg-rsc-tbl: Reference to the system configuration controlling the
|
|
+ resource table address loaded by the bootloader
|
|
+ 1st cell: phandle to syscon block
|
|
+ 2nd cell: register offset containing the resource table address
|
|
+ 3rd cell: register bitmask for the resource table address
|
|
+- st,syscfg-copro-state: Reference to the system configuration which returns the
|
|
+ coprocessor state.
|
|
+ 1st cell: phandle to syscon block
|
|
+ 2nd cell: register offset containing the coprocessor state
|
|
+ 3rd cell: register bitmask for the coprocessor state
|
|
- st,auto-boot: If defined, when remoteproc is probed, it loads the default
|
|
firmware and starts the remote processor.
|
|
|
|
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
|
|
index 130ca5b98..bab0df81a 100644
|
|
--- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
|
|
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
|
|
@@ -21,9 +21,14 @@ Required properties:
|
|
domain (RTC registers) write protection.
|
|
It is required on stm32(f4/f7/h7).
|
|
|
|
-Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7):
|
|
+Optional properties:
|
|
+* to override default rtc_ck parent clock on stm32(f4/f7/h7):
|
|
- assigned-clocks: reference to the rtc_ck clock entry.
|
|
- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
|
|
+* to select and enable RTC Low Speed Clock Output on stm32mp1:
|
|
+- st,lsco: defines the RTC output on which RTC Low-Speed Clock is Output. The
|
|
+ valid output values are defined in <dt-bindings/rtc/rtc-stm32.h>.
|
|
+- pinctrl state named "default" may be defined to reserve pin for RTC output.
|
|
|
|
Example:
|
|
|
|
@@ -58,4 +63,7 @@ Example:
|
|
clock-names = "pclk", "rtc_ck";
|
|
interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>,
|
|
<&exti 19 1>;
|
|
+ st,lsco = <RTC_OUT2_RMP>;
|
|
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
};
|
|
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
|
|
index 8620f7fcb..8b032ac3b 100644
|
|
--- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
|
|
+++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
|
|
@@ -1,7 +1,7 @@
|
|
* STMicroelectronics STM32 USART
|
|
|
|
Required properties:
|
|
-- compatible: can be either:
|
|
+- compatible: Can be either:
|
|
- "st,stm32-uart",
|
|
- "st,stm32f7-uart",
|
|
- "st,stm32h7-uart".
|
|
@@ -9,22 +9,43 @@ Required properties:
|
|
- reg: The address and length of the peripheral registers space
|
|
- interrupts:
|
|
- The interrupt line for the USART instance,
|
|
- - An optional wake-up interrupt.
|
|
- clocks: The input clock of the USART instance
|
|
|
|
Optional properties:
|
|
- resets: Must contain the phandle to the reset controller.
|
|
-- pinctrl: The reference on the pins configuration
|
|
-- st,hw-flow-ctrl: bool flag to enable hardware flow control.
|
|
+- pinctrl-names: Set to "default". An additional "sleep" state can be defined
|
|
+ to set pins in sleep state when in low power. In case the device is used as
|
|
+ a wakeup source, "idle" state is defined in order to keep RX pin active.
|
|
+- pinctrl-n: Phandle(s) pointing to pin configuration nodes.
|
|
+ For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
|
|
+- uart-has-rtscts: See description in serial.txt binding.
|
|
- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low,
|
|
- linux,rs485-enabled-at-boot-time: see rs485.txt.
|
|
-- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt
|
|
+ linux,rs485-enabled-at-boot-time: See rs485.txt.
|
|
+- dmas: Phandle(s) to DMA controller node(s). Refer to stm32-dma.txt
|
|
- dma-names: "rx" and/or "tx"
|
|
-- wakeup-source: bool flag to indicate this device has wakeup capabilities
|
|
-- interrupt-names, if optional wake-up interrupt is used, should be:
|
|
- - "event": the name for the interrupt line of the USART instance
|
|
- - "wakeup" the name for the optional wake-up interrupt
|
|
+- wakeup-source: Bool flag to indicate this device has wakeup capabilities
|
|
|
|
+Note for dma using:
|
|
+- "tx" dma can be used without any constraint since it uses single
|
|
+dma transfers.
|
|
+- "rx" dma using requires some attention:
|
|
+ 1) if you cannot anticipate the length of your received packets
|
|
+ and if your usart device embeds an internal fifo, then DON'T use
|
|
+ dma mode.
|
|
+ 2) if you enable dma mode WITHOUT mdma intermediate copy (cf.
|
|
+ stm32-dma.txt), then the availability of the received data will
|
|
+ depend on the dma driver policy and it may be delayed until dma
|
|
+ internal fifo is full. The usart driver will see this checking
|
|
+ the dma residue when rx interrupt (RXNE or RTO) occurs.
|
|
+ 3) if you enable dma mode WITH mdma intermediate copy (cf.
|
|
+ stm32-dma.txt) then the usart driver will never see the dma
|
|
+ residue becoming smaller than RX_BUF_P but it will get its
|
|
+ rx dma complete callback called when the cyclic transfer period
|
|
+ (RX_BUF_P) is reached.
|
|
+The three possibilities above are ordered from the most cpu time
|
|
+consuming one to the least one. The counterpart of this optimisation
|
|
+is the reception granularity achievable by the usart driver, from
|
|
+one byte up to RX_BUF_P.
|
|
|
|
Examples:
|
|
usart4: serial@40004c00 {
|
|
@@ -32,8 +53,11 @@ usart4: serial@40004c00 {
|
|
reg = <0x40004c00 0x400>;
|
|
interrupts = <52>;
|
|
clocks = <&clk_pclk1>;
|
|
- pinctrl-names = "default";
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
pinctrl-0 = <&pinctrl_usart4>;
|
|
+ pinctrl-1 = <&pinctrl_usart4_sleep>;
|
|
+ pinctrl-2 = <&pinctrl_usart4_idle>;
|
|
+ pinctrl-3 = <&pinctrl_usart4>;
|
|
};
|
|
|
|
usart2: serial@40004400 {
|
|
diff --git a/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
|
|
new file mode 100644
|
|
index 000000000..e2bd82f49
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
|
|
@@ -0,0 +1,39 @@
|
|
+STM32 - STM32MP1- HDP Pin configuration for STM32MP1
|
|
+=======================================================
|
|
+
|
|
+The Hardware Debug Port (HDP) allows the observation of internal signals. By using multiplexers,
|
|
+up to 16 signals for each of 8-bit output can be observed.
|
|
+
|
|
+Required Properties:
|
|
+
|
|
+ - compatible: Must be "st,stm32mp1-hdp"
|
|
+ - muxing-hdp: Indicates for each HDP pins selected which HDP output among the 16 available signals you want
|
|
+
|
|
+For each HDP pins you can select one of 16 signals which will be described in file : include/dt-bindings/soc/stm32-hdp.h
|
|
+
|
|
+Example
|
|
+-------
|
|
+
|
|
+In common dtsi file:
|
|
+
|
|
+hdp: hdp@5002a000 {
|
|
+ compatible = "st,stm32mp1-hdp";
|
|
+ reg = <0x5002a000 0x400>;
|
|
+ clocks = <&rcc HDP>;
|
|
+ clock-names = "hdp";
|
|
+};
|
|
+
|
|
+In board-specific file:
|
|
+
|
|
+In this example I've selected HDP0, HDP6 and HDP7, and for HDP0 the output signal is HDP0_GPOVAL_0,
|
|
+for HDP6 is HDP6_GPOVAL_6, and for HDP7 is HDP7_GPOVAL_7.
|
|
+
|
|
+&hdp {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
|
|
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
|
|
+
|
|
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
|
|
+ STM32_HDP(6, HDP6_GPOVAL_6) |
|
|
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
|
|
+};
|
|
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
|
|
index aafff3a69..1a65303d0 100644
|
|
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
|
|
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
|
|
@@ -23,6 +23,9 @@ Required properties:
|
|
configured in HS mode;
|
|
- "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs
|
|
configured in HS mode;
|
|
+ - "st,stm32mp1-fsotg": The DWC2 USB controller instance in STM32MP1 SoCs,
|
|
+ configured in FS mode (using dedicated FS transceiver).
|
|
+ - "st,stm32mp1-hsotg": The DWC2 USB controller instance in STM32MP1 SoCs;
|
|
- reg : Should contain 1 register range (address and length)
|
|
- interrupts : Should contain 1 interrupt
|
|
- clocks: clock provider specifier
|
|
@@ -46,6 +49,11 @@ Refer to phy/phy-bindings.txt for generic phy consumer properties
|
|
on for remote wakeup during suspend.
|
|
- snps,reset-phy-on-wake: If present indicates that we need to reset the PHY when
|
|
we detect a wakeup. This is due to a hardware errata.
|
|
+- usb33d-supply: external VBUS and ID sensing comparators supply, in order to
|
|
+ perform OTG operation, used on STM32MP1 SoCs.
|
|
+- usb-role-switch: use USB Role Switch to support dynamic dual role switch.
|
|
+ Refer to usb/generic.txt
|
|
+- wakeup-source: bool flag to indicate this device has wakeup capabilities
|
|
|
|
Deprecated properties:
|
|
- g-use-dma: gadget DMA mode is automatically detected
|
|
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
|
|
index 1ca64c851..b71c15dc8 100644
|
|
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
|
|
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
|
|
@@ -69,6 +69,11 @@ properties:
|
|
phy-names:
|
|
const: usb
|
|
|
|
+ wakeup-source:
|
|
+ $ref: /schemas/types.yaml#/definitions/flag
|
|
+ description:
|
|
+ Indicate this device has wakeup capabilities.
|
|
+
|
|
required:
|
|
- compatible
|
|
- reg
|
|
diff --git a/Documentation/devicetree/bindings/usb/st,typec-stusb.txt b/Documentation/devicetree/bindings/usb/st,typec-stusb.txt
|
|
new file mode 100644
|
|
index 000000000..415e14e14
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/usb/st,typec-stusb.txt
|
|
@@ -0,0 +1,48 @@
|
|
+STMicroelectronics STUSB Type-C Controller family
|
|
+
|
|
+Required properties:
|
|
+ - compatible: should be "st,stusb1600".
|
|
+ - reg: I2C slave address of the device.
|
|
+
|
|
+Optional properties:
|
|
+ - vdd-supply: main power supply [4.1V;22V].
|
|
+ - vsys-supply: low power supply [3.0V;5.5V].
|
|
+ - vconn-supply: power supply [2.7;5.5V] used to supply VConn on CC pin in
|
|
+ source or dual power role.
|
|
+ - interrupts: interrupt specifier triggered by ALERT# signal.
|
|
+ Please refer to ../interrupt-controller/interrupt.txt
|
|
+ - pinctrl state named "default" may be defined to configure pin for #ALERT
|
|
+ signal
|
|
+
|
|
+USB-C connector attached to STUSB Type-C port controller can be described in
|
|
+an optional connector sub-node. Refer to ../connector/usb-connector.txt.
|
|
+In case role switch can be used, an optional port sub-node can be added. Refer
|
|
+to ../graph.txt.
|
|
+
|
|
+Example :
|
|
+
|
|
+ typec: stusb1600@28 {
|
|
+ compatible = "st,stusb1600";
|
|
+ reg = <0x28>;
|
|
+ vdd-supply = <&vbus_drd>;
|
|
+ vsys-supply = <&vdd_usb>;
|
|
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-parent = <&gpioi>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&stusb1600_pins_a>;
|
|
+
|
|
+ usb_con: connector {
|
|
+ compatible = "usb-c-connector";
|
|
+ label = "USB-C";
|
|
+ power-role = "dual";
|
|
+ power-opmode = "1.5A";
|
|
+ data-role = "dual";
|
|
+
|
|
+ port {
|
|
+ con_usbotg_hs_ep: endpoint {
|
|
+ remote-endpoint = <&usbotg_hs_ep>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
|
index b21b3a646..3f1859094 100644
|
|
--- a/arch/arm/boot/dts/Makefile
|
|
+++ b/arch/arm/boot/dts/Makefile
|
|
@@ -989,9 +989,26 @@ dtb-$(CONFIG_ARCH_STM32) += \
|
|
stm32h743i-disco.dtb \
|
|
stm32mp157a-avenger96.dtb \
|
|
stm32mp157a-dk1.dtb \
|
|
+ stm32mp157d-dk1.dtb \
|
|
stm32mp157c-dk2.dtb \
|
|
+ stm32mp157f-dk2.dtb \
|
|
+ stm32mp157c-dk2-a7-examples.dtb \
|
|
+ stm32mp157c-dk2-m4-examples.dtb \
|
|
+ stm32mp157f-dk2-a7-examples.dtb \
|
|
+ stm32mp157f-dk2-m4-examples.dtb \
|
|
+ stm32mp157a-ed1.dtb \
|
|
stm32mp157c-ed1.dtb \
|
|
- stm32mp157c-ev1.dtb
|
|
+ stm32mp157d-ed1.dtb \
|
|
+ stm32mp157f-ed1.dtb \
|
|
+ stm32mp157a-ev1.dtb \
|
|
+ stm32mp157c-ev1.dtb \
|
|
+ stm32mp157d-ev1.dtb \
|
|
+ stm32mp157f-ev1.dtb \
|
|
+ stm32mp157c-ev1-a7-examples.dtb \
|
|
+ stm32mp157c-ev1-m4-examples.dtb \
|
|
+ stm32mp157f-ev1-a7-examples.dtb \
|
|
+ stm32mp157f-ev1-m4-examples.dtb
|
|
+
|
|
dtb-$(CONFIG_MACH_SUN4I) += \
|
|
sun4i-a10-a1000.dtb \
|
|
sun4i-a10-ba10-tvbox.dtb \
|
|
diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
|
|
new file mode 100644
|
|
index 000000000..3bb96ab8a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi
|
|
@@ -0,0 +1,157 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
|
|
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/ {
|
|
+
|
|
+ clocks {
|
|
+ clk_hse: clk-hse {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ };
|
|
+
|
|
+ clk_hsi: clk-hsi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <64000000>;
|
|
+ };
|
|
+
|
|
+ clk_lse: clk-lse {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ };
|
|
+
|
|
+ clk_lsi: clk-lsi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32000>;
|
|
+ };
|
|
+
|
|
+ clk_csi: clk-csi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <4000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ cpu0: cpu@0 {
|
|
+ clocks = <&rcc CK_MPU>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@1 {
|
|
+ clocks = <&rcc CK_MPU>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ m_can1: can@4400e000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ m_can2: can@4400f000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ cryp1: cryp@54001000 {
|
|
+ clocks = <&rcc CRYP1>;
|
|
+ resets = <&rcc CRYP1_R>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mlahb {
|
|
+ m4_rproc: m4@10000000 {
|
|
+ resets = <&rcc MCU_R>;
|
|
+
|
|
+ m4_system_resources {
|
|
+ m4_cec: cec@40016000 {
|
|
+ clocks = <&rcc CEC_K>, <&rcc CK_LSE>;
|
|
+ };
|
|
+
|
|
+ m4_m_can1: can@4400e000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ m4_m_can2: can@4400f000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ /delete-node/ scmi-0;
|
|
+ /delete-node/ scmi-1;
|
|
+ };
|
|
+ /delete-node/ sram@2ffff000;
|
|
+ /delete-node/ mailbox-0;
|
|
+ /delete-node/ mailbox-1;
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ clocks = <&rcc CEC_K>, <&clk_lse>;
|
|
+};
|
|
+
|
|
+&ddrperfm {
|
|
+ clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
+};
|
|
+
|
|
+&gpioz {
|
|
+ clocks = <&rcc GPIOZ>;
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ clocks = <&rcc HASH1>;
|
|
+ resets = <&rcc HASH1_R>;
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ clocks = <&rcc I2C4_K>;
|
|
+ resets = <&rcc I2C4_R>;
|
|
+};
|
|
+
|
|
+&i2c6 {
|
|
+ clocks = <&rcc I2C6_K>;
|
|
+ resets = <&rcc I2C6_R>;
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
+};
|
|
+
|
|
+&mdma1 {
|
|
+ clocks = <&rcc MDMA>;
|
|
+ resets = <&rcc MDMA_R>;
|
|
+};
|
|
+
|
|
+&rcc {
|
|
+ compatible = "st,stm32mp1-rcc", "syscon";
|
|
+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ clocks = <&rcc RNG1_K>;
|
|
+ resets = <&rcc RNG1_R>;
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
+};
|
|
+
|
|
+&spi6 {
|
|
+ clocks = <&rcc SPI6_K>;
|
|
+ resets = <&rcc SPI6_R>;
|
|
+};
|
|
+
|
|
+&usart1 {
|
|
+ clocks = <&rcc USART1_K>;
|
|
+ resets = <&rcc USART1_R>;
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..38c792694
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
|
|
@@ -0,0 +1,1411 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
+
|
|
+&pinctrl {
|
|
+ adc1_in6_pins_a: adc1-in6 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ adc12_ain_pins_a: adc12-ain-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
|
|
+ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
|
|
+ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
|
|
+ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
|
|
+ <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_a: cec-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_sleep_a: cec-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_b: cec-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, AF5)>;
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_sleep_b: cec-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dac_ch1_pins_a: dac-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dac_ch2_pins_a: dac-ch2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcmi_pins_a: dcmi-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet0_rgmii_pins_a: rgmii-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
|
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
|
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fmc_pins_a: fmc-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fmc_sleep_pins_a: fmc-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
|
|
+ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp0_pins_a: hdp0-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp0_pins_sleep_a: hdp0-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp6_pins_a: hdp6-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp6_pins_sleep_a: hdp6-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp7_pins_a: hdp7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp7_pins_sleep_a: hdp7-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_a: i2c1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_sleep_a: i2c1-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_b: i2c1-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_sleep_b: i2c1-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_a: i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_a: i2c2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_b1: i2c2-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_b1: i2c2-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c5_pins_a: i2c5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c5_pins_sleep_a: i2c5-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s2_pins_a: i2s2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s2_pins_sleep_a: i2s2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_a: ltdc-a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_sleep_a: ltdc-a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_b: ltdc-b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_sleep_b: ltdc-b-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m_can1_pins_a: m-can1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
|
|
+ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm1_pins_a: pwm1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm1_sleep_pins_a: pwm1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm2_pins_a: pwm2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm3_pins_a: pwm3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_pins_a: pwm4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_pins_b: pwm4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_sleep_pins_b: pwm4-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm5_pins_a: pwm5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm8_pins_a: pwm8-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm12_pins_a: pwm12-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm12_sleep_pins_a: pwm12-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_clk_pins_a: qspi-clk-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <3>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk1_pins_a: qspi-bk1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
+ bias-pull-up;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
|
|
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk2_pins_a: qspi-bk2-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
+ bias-pull-up;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
|
|
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2a_pins_a: sai2a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2a_sleep_pins_a: sai2a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_pins_a: sai2b-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_sleep_pins_a: sai2b-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
|
|
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_pins_b: sai2b-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_sleep_pins_b: sai2b-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai4a_pins_a: sai4a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai4a_sleep_pins_a: sai4a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
|
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2{
|
|
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
|
|
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
|
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
|
|
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdifrx_pins_a: spdifrx-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdifrx_sleep_pins_a: spdifrx-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi4_pins_a: spi4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi4_sleep_pins_a: spi4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi5_pins_a: spi5-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi5_sleep_pins_a: spi5-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
|
|
+ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ stusb1600_pins_a: stusb1600-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_pins_a: uart4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_idle_pins_a: uart4-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_sleep_pins_a: uart4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
|
|
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_pins_b: uart4-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_pins_a: uart7-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
|
|
+ <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
|
|
+ <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_pins_b: uart7-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_idle_pins_b: uart7-idle-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* USART7_TX */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_sleep_pins_b: uart7-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
|
|
+ <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_pins_a: usart2-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <3>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_idle_pins_a: usart2-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_sleep_pins_a: usart2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_pins_a: usart3-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_idle_pins_a: usart3-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_sleep_pins_a: usart3-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_pins_b: usart3-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_idle_pins_b: usart3-idle-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_sleep_pins_b: usart3-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbotg_hs_pins_a: usbotg_hs-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
|
|
+ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ i2c2_pins_b2: i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_b2: i2c2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c4_pins_a: i2c4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c4_pins_sleep_a: i2c4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi1_pins_a: spi1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi1_sleep_pins_a: spi1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
|
|
+ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
|
|
similarity index 59%
|
|
rename from arch/arm/boot/dts/stm32mp157c.dtsi
|
|
rename to arch/arm/boot/dts/stm32mp151.dtsi
|
|
index f98e0370c..c516e2ed0 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
|
|
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
|
|
@@ -5,7 +5,10 @@
|
|
*/
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/stm32mp1-clks.h>
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/reset/stm32mp1-resets.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
@@ -19,20 +22,101 @@
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_MPU>;
|
|
+ clock-names = "cpu";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ nvmem-cells = <&part_number_otp>;
|
|
+ nvmem-cell-names = "part_number";
|
|
+ #cooling-cells = <2>;
|
|
};
|
|
+ };
|
|
|
|
- cpu1: cpu@1 {
|
|
- compatible = "arm,cortex-a7";
|
|
- device_type = "cpu";
|
|
- reg = <1>;
|
|
+ cpu0_opp_table: cpu0-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ compatible = "arm,cortex-a7-pmu";
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>;
|
|
+ interrupt-parent = <&intc>;
|
|
+ };
|
|
+
|
|
+ scmi_sram: sram@2ffff000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x2ffff000 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x2ffff000 0x1000>;
|
|
+
|
|
+ scmi0_shm: scmi_shm@0 {
|
|
+ reg = <0 0x80>;
|
|
+ };
|
|
+
|
|
+ scmi1_shm: scmi_shm@200 {
|
|
+ reg = <0x200 0x80>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ scmi0_mbox: mailbox-0 {
|
|
+ #mbox-cells = <0>;
|
|
+ compatible = "arm,smc-mbox";
|
|
+ arm,func-id = <0x82002000>;
|
|
+ };
|
|
+
|
|
+ scmi1_mbox: mailbox-1 {
|
|
+ #mbox-cells = <0>;
|
|
+ compatible = "arm,smc-mbox";
|
|
+ arm,func-id = <0x82002001>;
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ scmi0: scmi-0 {
|
|
+ compatible = "arm,scmi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mboxes = <&scmi0_mbox 0>;
|
|
+ mbox-names = "txrx";
|
|
+ shmem = <&scmi0_shm>;
|
|
+
|
|
+ scmi0_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+ scmi0_reset: protocol@16 {
|
|
+ reg = <0x16>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ scmi1: scmi-1 {
|
|
+ compatible = "arm,scmi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ mboxes = <&scmi1_mbox 0>;
|
|
+ mbox-names = "txrx";
|
|
+ shmem = <&scmi1_shm>;
|
|
+
|
|
+ scmi1_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ optee: optee {
|
|
+ compatible = "linaro,optee-tz";
|
|
+ method = "smc";
|
|
+ status = "disabled";
|
|
};
|
|
};
|
|
|
|
psci {
|
|
- compatible = "arm,psci";
|
|
+ compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
- cpu_off = <0x84000002>;
|
|
- cpu_on = <0x84000003>;
|
|
};
|
|
|
|
intc: interrupt-controller@a0021000 {
|
|
@@ -50,38 +134,7 @@
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&intc>;
|
|
- };
|
|
-
|
|
- clocks {
|
|
- clk_hse: clk-hse {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <24000000>;
|
|
- };
|
|
-
|
|
- clk_hsi: clk-hsi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <64000000>;
|
|
- };
|
|
-
|
|
- clk_lse: clk-lse {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <32768>;
|
|
- };
|
|
-
|
|
- clk_lsi: clk-lsi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <32000>;
|
|
- };
|
|
-
|
|
- clk_csi: clk-csi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <4000000>;
|
|
- };
|
|
+ always-on;
|
|
};
|
|
|
|
thermal-zones {
|
|
@@ -91,12 +144,6 @@
|
|
thermal-sensors = <&dts>;
|
|
|
|
trips {
|
|
- cpu_alert1: cpu-alert1 {
|
|
- temperature = <85000>;
|
|
- hysteresis = <0>;
|
|
- type = "passive";
|
|
- };
|
|
-
|
|
cpu-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <0>;
|
|
@@ -115,6 +162,33 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ pm_domain {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32mp157c-pd";
|
|
+
|
|
+ pd_core_ret: core-ret-power-domain@1 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <1>;
|
|
+ #power-domain-cells = <0>;
|
|
+ label = "CORE-RETENTION";
|
|
+
|
|
+ pd_core: core-power-domain@2 {
|
|
+ reg = <2>;
|
|
+ #power-domain-cells = <0>;
|
|
+ label = "CORE";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reboot {
|
|
+ compatible = "syscon-reboot";
|
|
+ regmap = <&rcc>;
|
|
+ offset = <0x404>;
|
|
+ mask = <0x1>;
|
|
+ };
|
|
+
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
@@ -122,6 +196,14 @@
|
|
interrupt-parent = <&intc>;
|
|
ranges;
|
|
|
|
+ sram: sram@10000000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x10000000 0x60000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x10000000 0x60000>;
|
|
+ };
|
|
+
|
|
timers2: timer@40000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -129,11 +211,11 @@
|
|
reg = <0x40000000 0x400>;
|
|
clocks = <&rcc TIM2_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 18 0x400 0x1>,
|
|
- <&dmamux1 19 0x400 0x1>,
|
|
- <&dmamux1 20 0x400 0x1>,
|
|
- <&dmamux1 21 0x400 0x1>,
|
|
- <&dmamux1 22 0x400 0x1>;
|
|
+ dmas = <&dmamux1 18 0x400 0x80000001>,
|
|
+ <&dmamux1 19 0x400 0x80000001>,
|
|
+ <&dmamux1 20 0x400 0x80000001>,
|
|
+ <&dmamux1 21 0x400 0x80000001>,
|
|
+ <&dmamux1 22 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4", "up";
|
|
status = "disabled";
|
|
|
|
@@ -148,6 +230,11 @@
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
timers3: timer@40001000 {
|
|
@@ -157,12 +244,12 @@
|
|
reg = <0x40001000 0x400>;
|
|
clocks = <&rcc TIM3_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 23 0x400 0x1>,
|
|
- <&dmamux1 24 0x400 0x1>,
|
|
- <&dmamux1 25 0x400 0x1>,
|
|
- <&dmamux1 26 0x400 0x1>,
|
|
- <&dmamux1 27 0x400 0x1>,
|
|
- <&dmamux1 28 0x400 0x1>;
|
|
+ dmas = <&dmamux1 23 0x400 0x80000001>,
|
|
+ <&dmamux1 24 0x400 0x80000001>,
|
|
+ <&dmamux1 25 0x400 0x80000001>,
|
|
+ <&dmamux1 26 0x400 0x80000001>,
|
|
+ <&dmamux1 27 0x400 0x80000001>,
|
|
+ <&dmamux1 28 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
status = "disabled";
|
|
|
|
@@ -177,6 +264,11 @@
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
timers4: timer@40002000 {
|
|
@@ -186,10 +278,10 @@
|
|
reg = <0x40002000 0x400>;
|
|
clocks = <&rcc TIM4_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 29 0x400 0x1>,
|
|
- <&dmamux1 30 0x400 0x1>,
|
|
- <&dmamux1 31 0x400 0x1>,
|
|
- <&dmamux1 32 0x400 0x1>;
|
|
+ dmas = <&dmamux1 29 0x400 0x80000001>,
|
|
+ <&dmamux1 30 0x400 0x80000001>,
|
|
+ <&dmamux1 31 0x400 0x80000001>,
|
|
+ <&dmamux1 32 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4";
|
|
status = "disabled";
|
|
|
|
@@ -204,6 +296,11 @@
|
|
reg = <3>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
timers5: timer@40003000 {
|
|
@@ -213,12 +310,12 @@
|
|
reg = <0x40003000 0x400>;
|
|
clocks = <&rcc TIM5_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 55 0x400 0x1>,
|
|
- <&dmamux1 56 0x400 0x1>,
|
|
- <&dmamux1 57 0x400 0x1>,
|
|
- <&dmamux1 58 0x400 0x1>,
|
|
- <&dmamux1 59 0x400 0x1>,
|
|
- <&dmamux1 60 0x400 0x1>;
|
|
+ dmas = <&dmamux1 55 0x400 0x80000001>,
|
|
+ <&dmamux1 56 0x400 0x80000001>,
|
|
+ <&dmamux1 57 0x400 0x80000001>,
|
|
+ <&dmamux1 58 0x400 0x80000001>,
|
|
+ <&dmamux1 59 0x400 0x80000001>,
|
|
+ <&dmamux1 60 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
status = "disabled";
|
|
|
|
@@ -233,6 +330,11 @@
|
|
reg = <4>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
timers6: timer@40004000 {
|
|
@@ -242,7 +344,7 @@
|
|
reg = <0x40004000 0x400>;
|
|
clocks = <&rcc TIM6_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 69 0x400 0x1>;
|
|
+ dmas = <&dmamux1 69 0x400 0x80000001>;
|
|
dma-names = "up";
|
|
status = "disabled";
|
|
|
|
@@ -260,7 +362,7 @@
|
|
reg = <0x40005000 0x400>;
|
|
clocks = <&rcc TIM7_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 70 0x400 0x1>;
|
|
+ dmas = <&dmamux1 70 0x400 0x80000001>;
|
|
dma-names = "up";
|
|
status = "disabled";
|
|
|
|
@@ -372,9 +474,10 @@
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc SPI2_K>;
|
|
resets = <&rcc SPI2_R>;
|
|
- dmas = <&dmamux1 39 0x400 0x05>,
|
|
- <&dmamux1 40 0x400 0x05>;
|
|
+ dmas = <&dmamux1 39 0x400 0x01>,
|
|
+ <&dmamux1 40 0x400 0x01>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -397,9 +500,10 @@
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc SPI3_K>;
|
|
resets = <&rcc SPI3_R>;
|
|
- dmas = <&dmamux1 61 0x400 0x05>,
|
|
- <&dmamux1 62 0x400 0x05>;
|
|
+ dmas = <&dmamux1 61 0x400 0x01>,
|
|
+ <&dmamux1 62 0x400 0x01>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -430,84 +534,132 @@
|
|
usart2: serial@4000e000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x4000e000 0x400>;
|
|
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART2_K>;
|
|
+ resets = <&rcc USART2_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 43 0x400 0x5>,
|
|
+ <&dmamux1 44 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@4000f000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x4000f000 0x400>;
|
|
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART3_K>;
|
|
+ resets = <&rcc USART3_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 45 0x400 0x5>,
|
|
+ <&dmamux1 46 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@40010000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40010000 0x400>;
|
|
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART4_K>;
|
|
+ resets = <&rcc UART4_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 63 0x400 0x5>,
|
|
+ <&dmamux1 64 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@40011000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40011000 0x400>;
|
|
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART5_K>;
|
|
+ resets = <&rcc UART5_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 65 0x400 0x5>,
|
|
+ <&dmamux1 66 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@40012000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x40012000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C1_K>;
|
|
resets = <&rcc I2C1_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&dmamux1 33 0x400 0x80000001>,
|
|
+ <&dmamux1 34 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@40013000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x40013000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C2_K>;
|
|
resets = <&rcc I2C2_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&dmamux1 35 0x400 0x80000001>,
|
|
+ <&dmamux1 36 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@40014000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x40014000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C3_K>;
|
|
resets = <&rcc I2C3_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&dmamux1 73 0x400 0x80000001>,
|
|
+ <&dmamux1 74 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@40015000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x40015000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C5_K>;
|
|
resets = <&rcc I2C5_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&dmamux1 115 0x400 0x80000001>,
|
|
+ <&dmamux1 116 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -515,7 +667,7 @@
|
|
compatible = "st,stm32-cec";
|
|
reg = <0x40016000 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc CEC_K>, <&clk_lse>;
|
|
+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
|
|
clock-names = "cec", "hdmi-cec";
|
|
status = "disabled";
|
|
};
|
|
@@ -531,14 +683,14 @@
|
|
|
|
dac1: dac@1 {
|
|
compatible = "st,stm32-dac";
|
|
- #io-channels-cells = <1>;
|
|
+ #io-channel-cells = <1>;
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dac2: dac@2 {
|
|
compatible = "st,stm32-dac";
|
|
- #io-channels-cells = <1>;
|
|
+ #io-channel-cells = <1>;
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
@@ -547,16 +699,28 @@
|
|
uart7: serial@40018000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40018000 0x400>;
|
|
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART7_K>;
|
|
+ resets = <&rcc UART7_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 79 0x400 0x5>,
|
|
+ <&dmamux1 80 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart8: serial@40019000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40019000 0x400>;
|
|
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART8_K>;
|
|
+ resets = <&rcc UART8_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 81 0x400 0x5>,
|
|
+ <&dmamux1 82 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -567,13 +731,13 @@
|
|
reg = <0x44000000 0x400>;
|
|
clocks = <&rcc TIM1_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 11 0x400 0x1>,
|
|
- <&dmamux1 12 0x400 0x1>,
|
|
- <&dmamux1 13 0x400 0x1>,
|
|
- <&dmamux1 14 0x400 0x1>,
|
|
- <&dmamux1 15 0x400 0x1>,
|
|
- <&dmamux1 16 0x400 0x1>,
|
|
- <&dmamux1 17 0x400 0x1>;
|
|
+ dmas = <&dmamux1 11 0x400 0x80000001>,
|
|
+ <&dmamux1 12 0x400 0x80000001>,
|
|
+ <&dmamux1 13 0x400 0x80000001>,
|
|
+ <&dmamux1 14 0x400 0x80000001>,
|
|
+ <&dmamux1 15 0x400 0x80000001>,
|
|
+ <&dmamux1 16 0x400 0x80000001>,
|
|
+ <&dmamux1 17 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
"up", "trig", "com";
|
|
status = "disabled";
|
|
@@ -589,6 +753,11 @@
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
timers8: timer@44001000 {
|
|
@@ -598,13 +767,13 @@
|
|
reg = <0x44001000 0x400>;
|
|
clocks = <&rcc TIM8_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 47 0x400 0x1>,
|
|
- <&dmamux1 48 0x400 0x1>,
|
|
- <&dmamux1 49 0x400 0x1>,
|
|
- <&dmamux1 50 0x400 0x1>,
|
|
- <&dmamux1 51 0x400 0x1>,
|
|
- <&dmamux1 52 0x400 0x1>,
|
|
- <&dmamux1 53 0x400 0x1>;
|
|
+ dmas = <&dmamux1 47 0x400 0x80000001>,
|
|
+ <&dmamux1 48 0x400 0x80000001>,
|
|
+ <&dmamux1 49 0x400 0x80000001>,
|
|
+ <&dmamux1 50 0x400 0x80000001>,
|
|
+ <&dmamux1 51 0x400 0x80000001>,
|
|
+ <&dmamux1 52 0x400 0x80000001>,
|
|
+ <&dmamux1 53 0x400 0x80000001>;
|
|
dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
"up", "trig", "com";
|
|
status = "disabled";
|
|
@@ -620,13 +789,24 @@
|
|
reg = <7>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
usart6: serial@44003000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x44003000 0x400>;
|
|
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART6_K>;
|
|
+ resets = <&rcc USART6_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 71 0x400 0x5>,
|
|
+ <&dmamux1 72 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -638,9 +818,10 @@
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc SPI1_K>;
|
|
resets = <&rcc SPI1_R>;
|
|
- dmas = <&dmamux1 37 0x400 0x05>,
|
|
- <&dmamux1 38 0x400 0x05>;
|
|
+ dmas = <&dmamux1 37 0x400 0x01>,
|
|
+ <&dmamux1 38 0x400 0x01>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -663,9 +844,10 @@
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc SPI4_K>;
|
|
resets = <&rcc SPI4_R>;
|
|
- dmas = <&dmamux1 83 0x400 0x05>,
|
|
- <&dmamux1 84 0x400 0x05>;
|
|
+ dmas = <&dmamux1 83 0x400 0x01>,
|
|
+ <&dmamux1 84 0x400 0x01>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -676,10 +858,10 @@
|
|
reg = <0x44006000 0x400>;
|
|
clocks = <&rcc TIM15_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 105 0x400 0x1>,
|
|
- <&dmamux1 106 0x400 0x1>,
|
|
- <&dmamux1 107 0x400 0x1>,
|
|
- <&dmamux1 108 0x400 0x1>;
|
|
+ dmas = <&dmamux1 105 0x400 0x80000001>,
|
|
+ <&dmamux1 106 0x400 0x80000001>,
|
|
+ <&dmamux1 107 0x400 0x80000001>,
|
|
+ <&dmamux1 108 0x400 0x80000001>;
|
|
dma-names = "ch1", "up", "trig", "com";
|
|
status = "disabled";
|
|
|
|
@@ -703,8 +885,8 @@
|
|
reg = <0x44007000 0x400>;
|
|
clocks = <&rcc TIM16_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 109 0x400 0x1>,
|
|
- <&dmamux1 110 0x400 0x1>;
|
|
+ dmas = <&dmamux1 109 0x400 0x80000001>,
|
|
+ <&dmamux1 110 0x400 0x80000001>;
|
|
dma-names = "ch1", "up";
|
|
status = "disabled";
|
|
|
|
@@ -727,8 +909,8 @@
|
|
reg = <0x44008000 0x400>;
|
|
clocks = <&rcc TIM17_K>;
|
|
clock-names = "int";
|
|
- dmas = <&dmamux1 111 0x400 0x1>,
|
|
- <&dmamux1 112 0x400 0x1>;
|
|
+ dmas = <&dmamux1 111 0x400 0x80000001>,
|
|
+ <&dmamux1 112 0x400 0x80000001>;
|
|
dma-names = "ch1", "up";
|
|
status = "disabled";
|
|
|
|
@@ -753,9 +935,10 @@
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc SPI5_K>;
|
|
resets = <&rcc SPI5_R>;
|
|
- dmas = <&dmamux1 85 0x400 0x05>,
|
|
- <&dmamux1 86 0x400 0x05>;
|
|
+ dmas = <&dmamux1 85 0x400 0x01>,
|
|
+ <&dmamux1 86 0x400 0x01>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -923,32 +1106,6 @@
|
|
};
|
|
};
|
|
|
|
- m_can1: can@4400e000 {
|
|
- compatible = "bosch,m_can";
|
|
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
- reg-names = "m_can", "message_ram";
|
|
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "int0", "int1";
|
|
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
- clock-names = "hclk", "cclk";
|
|
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- m_can2: can@4400f000 {
|
|
- compatible = "bosch,m_can";
|
|
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
- reg-names = "m_can", "message_ram";
|
|
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "int0", "int1";
|
|
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
- clock-names = "hclk", "cclk";
|
|
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
dma1: dma@48000000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x48000000 0x400>;
|
|
@@ -961,9 +1118,19 @@
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc DMA1>;
|
|
+ resets = <&rcc DMA1_R>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
dma-requests = <8>;
|
|
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
|
|
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
|
|
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
|
|
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
|
|
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
|
|
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
|
|
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
|
|
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
};
|
|
|
|
dma2: dma@48001000 {
|
|
@@ -978,19 +1145,30 @@
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc DMA2>;
|
|
+ resets = <&rcc DMA2_R>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
dma-requests = <8>;
|
|
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
|
|
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
|
|
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
|
|
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
|
|
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
|
|
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
|
|
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
|
|
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
};
|
|
|
|
dmamux1: dma-router@48002000 {
|
|
compatible = "st,stm32h7-dmamux";
|
|
- reg = <0x48002000 0x1c>;
|
|
+ reg = <0x48002000 0x40>;
|
|
#dma-cells = <3>;
|
|
dma-requests = <128>;
|
|
dma-masters = <&dma1 &dma2>;
|
|
dma-channels = <16>;
|
|
clocks = <&rcc DMAMUX>;
|
|
+ resets = <&rcc DMAMUX_R>;
|
|
};
|
|
|
|
adc: adc@48003000 {
|
|
@@ -1013,7 +1191,7 @@
|
|
reg = <0x0>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <0>;
|
|
- dmas = <&dmamux1 9 0x400 0x01>;
|
|
+ dmas = <&dmamux1 9 0x400 0x80000001>;
|
|
dma-names = "rx";
|
|
status = "disabled";
|
|
};
|
|
@@ -1024,39 +1202,65 @@
|
|
reg = <0x100>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <1>;
|
|
- dmas = <&dmamux1 10 0x400 0x01>;
|
|
+ dmas = <&dmamux1 10 0x400 0x80000001>;
|
|
dma-names = "rx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
+ sdmmc3: sdmmc@48004000 {
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cmd_irq";
|
|
+ clocks = <&rcc SDMMC3_K>;
|
|
+ clock-names = "apb_pclk";
|
|
+ resets = <&rcc SDMMC3_R>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
usbotg_hs: usb-otg@49000000 {
|
|
- compatible = "snps,dwc2";
|
|
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
reg = <0x49000000 0x10000>;
|
|
clocks = <&rcc USBO_K>;
|
|
clock-names = "otg";
|
|
resets = <&rcc USBO_R>;
|
|
reset-names = "dwc2";
|
|
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
- g-rx-fifo-size = <256>;
|
|
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ g-rx-fifo-size = <512>;
|
|
g-np-tx-fifo-size = <32>;
|
|
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
|
|
dr_mode = "otg";
|
|
+ usb33d-supply = <&usb33>;
|
|
+ power-domains = <&pd_core>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
+ hsem: hwspinlock@4c000000 {
|
|
+ compatible = "st,stm32-hwspinlock";
|
|
+ #hwlock-cells = <2>;
|
|
+ reg = <0x4c000000 0x400>;
|
|
+ clocks = <&rcc HSEM>;
|
|
+ clock-names = "hsem";
|
|
+ };
|
|
+
|
|
ipcc: mailbox@4c001000 {
|
|
compatible = "st,stm32mp1-ipcc";
|
|
#mbox-cells = <1>;
|
|
reg = <0x4c001000 0x400>;
|
|
st,proc-id = <0>;
|
|
interrupts-extended =
|
|
- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <&exti 61 1>;
|
|
- interrupt-names = "rx", "tx", "wakeup";
|
|
+ <&exti 61 1>,
|
|
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rx", "tx";
|
|
clocks = <&rcc IPCC>;
|
|
wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1067,16 +1271,68 @@
|
|
resets = <&rcc CAMITF_R>;
|
|
clocks = <&rcc DCMI>;
|
|
clock-names = "mclk";
|
|
- dmas = <&dmamux1 75 0x400 0x0d>;
|
|
+ dmas = <&dmamux1 75 0x400 0xe0000001>;
|
|
dma-names = "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rcc: rcc@50000000 {
|
|
- compatible = "st,stm32mp1-rcc", "syscon";
|
|
+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
|
|
reg = <0x50000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
+
|
|
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>,
|
|
+ <&scmi0_clk CK_SCMI0_HSI>,
|
|
+ <&scmi0_clk CK_SCMI0_CSI>,
|
|
+ <&scmi0_clk CK_SCMI0_LSE>,
|
|
+ <&scmi0_clk CK_SCMI0_LSI>;
|
|
+ };
|
|
+
|
|
+ pwr_regulators: pwr@50001000 {
|
|
+ compatible = "st,stm32mp1,pwr-reg";
|
|
+ reg = <0x50001000 0x10>;
|
|
+ st,tzcr = <&rcc 0x0 0x1>;
|
|
+
|
|
+ reg11: reg11 {
|
|
+ regulator-name = "reg11";
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ };
|
|
+
|
|
+ reg18: reg18 {
|
|
+ regulator-name = "reg18";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ };
|
|
+
|
|
+ usb33: usb33 {
|
|
+ regulator-name = "usb33";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwr_mcu: pwr_mcu@50001014 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x50001014 0x4>;
|
|
+ };
|
|
+
|
|
+ pwr_irq: pwr@50001020 {
|
|
+ compatible = "st,stm32mp1-pwr";
|
|
+ reg = <0x50001020 0x100>;
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+
|
|
+ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
exti: interrupt-controller@5000d000 {
|
|
@@ -1084,6 +1340,18 @@
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x5000d000 0x400>;
|
|
+ hwlocks = <&hsem 1 1>;
|
|
+
|
|
+ /* exti_pwr is an extra interrupt controller used for
|
|
+ * EXTI 55 to 60. It's mapped on pwr interrupt
|
|
+ * controller.
|
|
+ */
|
|
+ exti_pwr: exti-pwr {
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ interrupt-parent = <&pwr_irq>;
|
|
+ st,irq-number = <6>;
|
|
+ };
|
|
};
|
|
|
|
syscfg: syscon@50020000 {
|
|
@@ -1219,12 +1487,11 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
- cryp1: cryp@54001000 {
|
|
- compatible = "st,stm32mp1-cryp";
|
|
- reg = <0x54001000 0x400>;
|
|
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc CRYP1>;
|
|
- resets = <&rcc CRYP1_R>;
|
|
+ hdp: hdp@5002a000 {
|
|
+ compatible = "st,stm32mp1-hdp";
|
|
+ reg = <0x5002a000 0x400>;
|
|
+ clocks = <&rcc HDP>;
|
|
+ clock-names = "hdp";
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1232,9 +1499,9 @@
|
|
compatible = "st,stm32f756-hash";
|
|
reg = <0x54002000 0x400>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc HASH1>;
|
|
- resets = <&rcc HASH1_R>;
|
|
- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HASH1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_HASH1>;
|
|
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
|
|
dma-names = "in";
|
|
dma-maxburst = <2>;
|
|
status = "disabled";
|
|
@@ -1243,8 +1510,8 @@
|
|
rng1: rng@54003000 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x54003000 0x400>;
|
|
- clocks = <&rcc RNG1_K>;
|
|
- resets = <&rcc RNG1_R>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_RNG1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_RNG1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1253,7 +1520,8 @@
|
|
reg = <0x58000000 0x1000>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc MDMA>;
|
|
- #dma-cells = <5>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_MDMA>;
|
|
+ #dma-cells = <6>;
|
|
dma-channels = <32>;
|
|
dma-requests = <48>;
|
|
};
|
|
@@ -1268,9 +1536,9 @@
|
|
<0x89010000 0x1000>,
|
|
<0x89020000 0x1000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
|
|
- <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
|
|
- <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
|
|
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
|
|
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
|
|
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
|
|
dma-names = "tx", "rx", "ecc";
|
|
clocks = <&rcc FMC_K>;
|
|
resets = <&rcc FMC_R>;
|
|
@@ -1282,8 +1550,8 @@
|
|
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
reg-names = "qspi", "qspi_mm";
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
|
|
- <&mdma1 22 0x10 0x100008 0x0 0x0>;
|
|
+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
|
|
+ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&rcc QSPI_K>;
|
|
resets = <&rcc QSPI_R>;
|
|
@@ -1292,16 +1560,32 @@
|
|
|
|
sdmmc1: sdmmc@58005000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
- arm,primecell-periphid = <0x10153180>;
|
|
- reg = <0x58005000 0x1000>;
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "cmd_irq";
|
|
+ interrupt-names = "cmd_irq";
|
|
clocks = <&rcc SDMMC1_K>;
|
|
clock-names = "apb_pclk";
|
|
resets = <&rcc SDMMC1_R>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc2: sdmmc@58007000 {
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
|
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cmd_irq";
|
|
+ clocks = <&rcc SDMMC2_K>;
|
|
+ clock-names = "apb_pclk";
|
|
+ resets = <&rcc SDMMC2_R>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
};
|
|
|
|
crc1: crc@58009000 {
|
|
@@ -1321,23 +1605,25 @@
|
|
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
|
reg = <0x5800a000 0x2000>;
|
|
reg-names = "stmmaceth";
|
|
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "macirq";
|
|
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq",
|
|
+ "eth_wake_irq";
|
|
clock-names = "stmmaceth",
|
|
"mac-clk-tx",
|
|
"mac-clk-rx",
|
|
- "ethstp",
|
|
- "syscfg-clk";
|
|
+ "ethstp";
|
|
clocks = <&rcc ETHMAC>,
|
|
<&rcc ETHTX>,
|
|
<&rcc ETHRX>,
|
|
- <&rcc ETHSTP>,
|
|
- <&rcc SYSCFG>;
|
|
+ <&rcc ETHSTP>;
|
|
st,syscon = <&syscfg 0x4>;
|
|
snps,mixed-burst;
|
|
snps,pbl = <2>;
|
|
+ snps,en-tx-lpi-clockgating;
|
|
snps,axi-config = <&stmmac_axi_config_0>;
|
|
snps,tso;
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1355,28 +1641,10 @@
|
|
reg = <0x5800d000 0x1000>;
|
|
clocks = <&rcc USBH>;
|
|
resets = <&rcc USBH_R>;
|
|
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
companion = <&usbh_ohci>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpu: gpu@59000000 {
|
|
- compatible = "vivante,gc";
|
|
- reg = <0x59000000 0x800>;
|
|
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc GPU>, <&rcc GPU_K>;
|
|
- clock-names = "bus" ,"core";
|
|
- resets = <&rcc GPU_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dsi: dsi@5a000000 {
|
|
- compatible = "st,stm32-dsi";
|
|
- reg = <0x5a000000 0x800>;
|
|
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
- clock-names = "pclk", "ref", "px_clk";
|
|
- resets = <&rcc DSI_R>;
|
|
- reset-names = "apb";
|
|
+ power-domains = <&pd_core>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1394,7 +1662,7 @@
|
|
iwdg2: watchdog@5a002000 {
|
|
compatible = "st,stm32mp1-iwdg";
|
|
reg = <0x5a002000 0x400>;
|
|
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
+ clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>;
|
|
clock-names = "pclk", "lsi";
|
|
status = "disabled";
|
|
};
|
|
@@ -1402,10 +1670,13 @@
|
|
usbphyc: usbphyc@5a006000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ #clock-cells = <0>;
|
|
compatible = "st,stm32mp1-usbphyc";
|
|
reg = <0x5a006000 0x1000>;
|
|
clocks = <&rcc USBPHY_K>;
|
|
resets = <&rcc USBPHY_R>;
|
|
+ vdda1v1-supply = <®11>;
|
|
+ vdda1v8-supply = <®18>;
|
|
status = "disabled";
|
|
|
|
usbphyc_port0: usb-phy@0 {
|
|
@@ -1419,11 +1690,22 @@
|
|
};
|
|
};
|
|
|
|
+ ddrperfm: perf@5a007000 {
|
|
+ compatible = "st,stm32-ddr-pmu";
|
|
+ reg = <0x5a007000 0x400>;
|
|
+ clocks = <&rcc DDRPERFM>, <&scmi0_clk CK_SCMI0_PLL2_R>;
|
|
+ clock-names = "bus", "ddr";
|
|
+ resets = <&rcc DDRPERFM_R>;
|
|
+ };
|
|
+
|
|
usart1: serial@5c000000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x5c000000 0x400>;
|
|
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc USART1_K>;
|
|
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_USART1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_USART1>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1433,33 +1715,41 @@
|
|
compatible = "st,stm32h7-spi";
|
|
reg = <0x5c001000 0x400>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI6_K>;
|
|
- resets = <&rcc SPI6_R>;
|
|
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
|
|
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_SPI6>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_SPI6>;
|
|
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
|
|
+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
|
|
dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@5c002000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x5c002000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C4_K>;
|
|
- resets = <&rcc I2C4_R>;
|
|
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_I2C4>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_I2C4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
|
|
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@5c004000 {
|
|
compatible = "st,stm32mp1-rtc";
|
|
reg = <0x5c004000 0x400>;
|
|
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_RTCAPB>,
|
|
+ <&scmi0_clk CK_SCMI0_RTC>;
|
|
clock-names = "pclk", "rtc_ck";
|
|
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1468,6 +1758,10 @@
|
|
reg = <0x5c005000 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
+
|
|
+ part_number_otp: part_number_otp@4 {
|
|
+ reg = <0x4 0x1>;
|
|
+ };
|
|
ts_cal1: calib@5c {
|
|
reg = <0x5c 0x2>;
|
|
};
|
|
@@ -1477,17 +1771,200 @@
|
|
};
|
|
|
|
i2c6: i2c@5c009000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
reg = <0x5c009000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C6_K>;
|
|
- resets = <&rcc I2C6_R>;
|
|
+ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_I2C6>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_I2C6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
|
|
+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
|
+ wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ tamp: tamp@5c00a000 {
|
|
+ compatible = "simple-bus", "syscon", "simple-mfd";
|
|
+ reg = <0x5c00a000 0x400>;
|
|
+
|
|
+ reboot-mode {
|
|
+ compatible = "syscon-reboot-mode";
|
|
+ offset = <0x150>; /* reg20 */
|
|
+ mask = <0xff>;
|
|
+ mode-normal = <0>;
|
|
+ mode-fastboot = <0x1>;
|
|
+ mode-recovery = <0x2>;
|
|
+ mode-stm32cubeprogrammer = <0x3>;
|
|
+ mode-ums_mmc0 = <0x10>;
|
|
+ mode-ums_mmc1 = <0x11>;
|
|
+ mode-ums_mmc2 = <0x12>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ /*
|
|
+ * Break node order to solve dependency probe issue between
|
|
+ * pinctrl and exti.
|
|
+ */
|
|
+ pinctrl: pin-controller@50002000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "st,stm32mp157-pinctrl";
|
|
+ ranges = <0 0x50002000 0xa400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ st,syscfg = <&exti 0x60 0xff>;
|
|
+ hwlocks = <&hsem 0 1>;
|
|
+ pins-are-numbered;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x0 0x400>;
|
|
+ clocks = <&rcc GPIOA>;
|
|
+ st,bank-name = "GPIOA";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x1000 0x400>;
|
|
+ clocks = <&rcc GPIOB>;
|
|
+ st,bank-name = "GPIOB";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x2000 0x400>;
|
|
+ clocks = <&rcc GPIOC>;
|
|
+ st,bank-name = "GPIOC";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x3000 0x400>;
|
|
+ clocks = <&rcc GPIOD>;
|
|
+ st,bank-name = "GPIOD";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x4000 0x400>;
|
|
+ clocks = <&rcc GPIOE>;
|
|
+ st,bank-name = "GPIOE";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x5000 0x400>;
|
|
+ clocks = <&rcc GPIOF>;
|
|
+ st,bank-name = "GPIOF";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x6000 0x400>;
|
|
+ clocks = <&rcc GPIOG>;
|
|
+ st,bank-name = "GPIOG";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x7000 0x400>;
|
|
+ clocks = <&rcc GPIOH>;
|
|
+ st,bank-name = "GPIOH";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x8000 0x400>;
|
|
+ clocks = <&rcc GPIOI>;
|
|
+ st,bank-name = "GPIOI";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioj: gpio@5000b000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x9000 0x400>;
|
|
+ clocks = <&rcc GPIOJ>;
|
|
+ st,bank-name = "GPIOJ";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiok: gpio@5000c000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0xa000 0x400>;
|
|
+ clocks = <&rcc GPIOK>;
|
|
+ st,bank-name = "GPIOK";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pinctrl_z: pin-controller-z@54004000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "st,stm32mp157-z-pinctrl";
|
|
+ ranges = <0 0x54004000 0x400>;
|
|
+ pins-are-numbered;
|
|
+ interrupt-parent = <&exti>;
|
|
+ st,syscfg = <&exti 0x60 0xff>;
|
|
+ hwlocks = <&hsem 0 1>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0 0x400>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_GPIOZ>;
|
|
+ st,bank-name = "GPIOZ";
|
|
+ st,bank-ioport = <11>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
};
|
|
|
|
mlahb {
|
|
@@ -1503,10 +1980,18 @@
|
|
reg = <0x10000000 0x40000>,
|
|
<0x30000000 0x40000>,
|
|
<0x38000000 0x10000>;
|
|
- resets = <&rcc MCU_R>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_MCU>;
|
|
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
|
|
st,syscfg-tz = <&rcc 0x000 0x1>;
|
|
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
|
|
+ st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>;
|
|
+ st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
|
|
status = "disabled";
|
|
+
|
|
+ m4_system_resources {
|
|
+ compatible = "rproc-srm-core";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
};
|
|
};
|
|
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
|
|
new file mode 100644
|
|
index 000000000..cf16b843c
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
|
|
@@ -0,0 +1,54 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp151.dtsi"
|
|
+
|
|
+/ {
|
|
+ cpus {
|
|
+ cpu1: cpu@1 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <1>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_MPU>;
|
|
+ clock-names = "cpu";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>, <&cpu1>;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ m_can1: can@4400e000 {
|
|
+ compatible = "bosch,m_can";
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
+ reg-names = "m_can", "message_ram";
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "int0", "int1";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ m_can2: can@4400f000 {
|
|
+ compatible = "bosch,m_can";
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
+ reg-names = "m_can", "message_ram";
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "int0", "int1";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157-m4-srm-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-m4-srm-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..b4030e5c9
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157-m4-srm-pinctrl.dtsi
|
|
@@ -0,0 +1,524 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ m4_adc1_in6_pins_a: m4-adc1-in6 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 12, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_adc12_ain_pins_a: m4-adc12-ain-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
|
|
+ <STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
|
|
+ <STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
|
|
+ <STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
|
|
+ <STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_cec_pins_a: m4-cec-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_cec_pins_b: m4-cec-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dac_ch1_pins_a: m4-dac-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dac_ch2_pins_a: m4-dac-ch2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 5, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dcmi_pins_a: m4-dcmi-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
|
|
+ <STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
|
|
+ <STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_fmc_pins_a: m4-fmc-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
|
|
+ <STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp0_pins_a: m4-hdp0-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp6_pins_a: m4-hdp6-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp7_pins_a: m4-hdp7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c1_pins_a: m4-i2c1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c2_pins_a: m4-i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c5_pins_a: m4-i2c5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2s2_pins_a: m4-i2s2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ltdc_pins_a: m4-ltdc-a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ltdc_pins_b: m4-ltdc-b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_m_can1_pins_a: m4-m-can1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
|
|
+ <STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm1_pins_a: m4-pwm1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm2_pins_a: m4-pwm2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm3_pins_a: m4-pwm3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm4_pins_a: m4-pwm4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm4_pins_b: m4-pwm4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm5_pins_a: m4-pwm5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm8_pins_a: m4-pwm8-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm12_pins_a: m4-pwm12-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
|
|
+ <STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
|
|
+ <STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_clk_pins_a: m4-qspi-clk-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2a_pins_a: m4-sai2a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2b_pins_a: m4-sai2b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
|
|
+ <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2b_pins_b: m4-sai2b-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai4a_pins_a: m4-sai4a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
|
|
+ <STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
|
|
+ <STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
|
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
|
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
|
|
+ <STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spdifrx_pins_a: m4-spdifrx-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi4_pins_a: m4-spi4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
|
|
+ <STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi5_pins_a: m4-spi5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
|
|
+ <STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_stusb1600_pins_a: m4-stusb1600-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 11, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_uart4_pins_a: m4-uart4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
|
|
+ <STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_uart7_pins_a: m4-uart7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
|
|
+ <STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart2_pins_a: m4-usart2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart3_pins_a: m4-usart3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart3_pins_b: m4-usart3-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
|
|
+ <STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ m4_i2c4_pins_a: m4-i2c4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi1_pins_a: m4-spi1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
|
|
+ <STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157-m4-srm.dtsi b/arch/arm/boot/dts/stm32mp157-m4-srm.dtsi
|
|
new file mode 100644
|
|
index 000000000..60454aee4
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157-m4-srm.dtsi
|
|
@@ -0,0 +1,442 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ m4_timers2: timer@40000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40000000 0x400>;
|
|
+ clocks = <&rcc TIM2_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers3: timer@40001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40001000 0x400>;
|
|
+ clocks = <&rcc TIM3_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers4: timer@40002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40002000 0x400>;
|
|
+ clocks = <&rcc TIM4_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers5: timer@40003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40003000 0x400>;
|
|
+ clocks = <&rcc TIM5_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers6: timer@40004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40004000 0x400>;
|
|
+ clocks = <&rcc TIM6_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers7: timer@40005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40005000 0x400>;
|
|
+ clocks = <&rcc TIM7_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers12: timer@40006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40006000 0x400>;
|
|
+ clocks = <&rcc TIM12_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers13: timer@40007000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40007000 0x400>;
|
|
+ clocks = <&rcc TIM13_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers14: timer@40008000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40008000 0x400>;
|
|
+ clocks = <&rcc TIM14_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer1: timer@40009000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40009000 0x400>;
|
|
+ clocks = <&rcc LPTIM1_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi2: spi@4000b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ clocks = <&rcc SPI2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s2: audio-controller@4000b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi3: spi@4000c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ clocks = <&rcc SPI3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s3: audio-controller@4000c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spdifrx: audio-controller@4000d000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000d000 0x400>;
|
|
+ clocks = <&rcc SPDIF_K>;
|
|
+ clock-names = "kclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart2: serial@4000e000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000e000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <27 1>;
|
|
+ clocks = <&rcc USART2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart3: serial@4000f000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000f000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <28 1>;
|
|
+ clocks = <&rcc USART3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart4: serial@40010000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40010000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <30 1>;
|
|
+ clocks = <&rcc UART4_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart5: serial@40011000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40011000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <31 1>;
|
|
+ clocks = <&rcc UART5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c1: i2c@40012000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40012000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <21 1>;
|
|
+ clocks = <&rcc I2C1_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c2: i2c@40013000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40013000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <22 1>;
|
|
+ clocks = <&rcc I2C2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c3: i2c@40014000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40014000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <23 1>;
|
|
+ clocks = <&rcc I2C3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c5: i2c@40015000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40015000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <25 1>;
|
|
+ clocks = <&rcc I2C5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_cec: cec@40016000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40016000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <69 1>;
|
|
+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
|
|
+ clock-names = "cec", "hdmi-cec";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dac: dac@40017000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40017000 0x400>;
|
|
+ clocks = <&rcc DAC12>;
|
|
+ clock-names = "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart7: serial@40018000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40018000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <32 1>;
|
|
+ clocks = <&rcc UART7_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart8: serial@40019000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40019000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <33 1>;
|
|
+ clocks = <&rcc UART8_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers1: timer@44000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44000000 0x400>;
|
|
+ clocks = <&rcc TIM1_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers8: timer@44001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44001000 0x400>;
|
|
+ clocks = <&rcc TIM8_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart6: serial@44003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44003000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <29 1>;
|
|
+ clocks = <&rcc USART6_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi1: spi@44004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44004000 0x400>;
|
|
+ clocks = <&rcc SPI1_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s1: audio-controller@44004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44004000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi4: spi@44005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44005000 0x400>;
|
|
+ clocks = <&rcc SPI4_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers15: timer@44006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44006000 0x400>;
|
|
+ clocks = <&rcc TIM15_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers16: timer@44007000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44007000 0x400>;
|
|
+ clocks = <&rcc TIM16_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers17: timer@44008000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44008000 0x400>;
|
|
+ clocks = <&rcc TIM17_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi5: spi@44009000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44009000 0x400>;
|
|
+ clocks = <&rcc SPI5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai1: sai@4400a000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400a000 0x4>;
|
|
+ clocks = <&rcc SAI1_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai2: sai@4400b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400b000 0x4>;
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai3: sai@4400c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400c000 0x4>;
|
|
+ clocks = <&rcc SAI3_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dfsdm: dfsdm@4400d000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400d000 0x800>;
|
|
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
|
|
+ clock-names = "dfsdm", "audio";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_m_can1: can@4400e000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_m_can2: can@4400f000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dma1: dma@48000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48000000 0x400>;
|
|
+ clocks = <&rcc DMA1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dma2: dma@48001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48001000 0x400>;
|
|
+ clocks = <&rcc DMA2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dmamux1: dma-router@48002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48002000 0x1c>;
|
|
+ clocks = <&rcc DMAMUX>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_adc: adc@48003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48003000 0x400>;
|
|
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
+ clock-names = "bus", "adc";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sdmmc3: sdmmc@48004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
+ clocks = <&rcc SDMMC3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usbotg_hs: usb-otg@49000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x49000000 0x10000>;
|
|
+ clocks = <&rcc USBO_K>;
|
|
+ clock-names = "otg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_hash2: hash@4c002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c002000 0x400>;
|
|
+ clocks = <&rcc HASH2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_rng2: rng@4c003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c003000 0x400>;
|
|
+ clocks = <&rcc RNG2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_crc2: crc@4c004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c004000 0x400>;
|
|
+ clocks = <&rcc CRC2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_cryp2: cryp@4c005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c005000 0x400>;
|
|
+ clocks = <&rcc CRYP2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dcmi: dcmi@4c006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c006000 0x400>;
|
|
+ clocks = <&rcc DCMI>;
|
|
+ clock-names = "mclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer2: timer@50021000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50021000 0x400>;
|
|
+ clocks = <&rcc LPTIM2_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer3: timer@50022000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50022000 0x400>;
|
|
+ clocks = <&rcc LPTIM3_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer4: timer@50023000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50023000 0x400>;
|
|
+ clocks = <&rcc LPTIM4_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer5: timer@50024000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50024000 0x400>;
|
|
+ clocks = <&rcc LPTIM5_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai4: sai@50027000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50027000 0x4>;
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_qspi: qspi@58003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
+ clocks = <&rcc QSPI_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_ethernet0: ethernet@5800a000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x5800a000 0x2000>;
|
|
+ clock-names = "stmmaceth",
|
|
+ "mac-clk-tx",
|
|
+ "mac-clk-rx",
|
|
+ "ethstp",
|
|
+ "syscfg-clk";
|
|
+ clocks = <&rcc ETHMAC>,
|
|
+ <&rcc ETHTX>,
|
|
+ <&rcc ETHRX>,
|
|
+ <&rcc ETHSTP>,
|
|
+ <&rcc SYSCFG>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 0a3a7d667..000000000
|
|
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,925 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
- */
|
|
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
-
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- compatible = "st,stm32mp157-pinctrl";
|
|
- ranges = <0 0x50002000 0xa400>;
|
|
- interrupt-parent = <&exti>;
|
|
- st,syscfg = <&exti 0x60 0xff>;
|
|
- pins-are-numbered;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x0 0x400>;
|
|
- clocks = <&rcc GPIOA>;
|
|
- st,bank-name = "GPIOA";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x1000 0x400>;
|
|
- clocks = <&rcc GPIOB>;
|
|
- st,bank-name = "GPIOB";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x2000 0x400>;
|
|
- clocks = <&rcc GPIOC>;
|
|
- st,bank-name = "GPIOC";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x3000 0x400>;
|
|
- clocks = <&rcc GPIOD>;
|
|
- st,bank-name = "GPIOD";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x4000 0x400>;
|
|
- clocks = <&rcc GPIOE>;
|
|
- st,bank-name = "GPIOE";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x5000 0x400>;
|
|
- clocks = <&rcc GPIOF>;
|
|
- st,bank-name = "GPIOF";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x6000 0x400>;
|
|
- clocks = <&rcc GPIOG>;
|
|
- st,bank-name = "GPIOG";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x7000 0x400>;
|
|
- clocks = <&rcc GPIOH>;
|
|
- st,bank-name = "GPIOH";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x8000 0x400>;
|
|
- clocks = <&rcc GPIOI>;
|
|
- st,bank-name = "GPIOI";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioj: gpio@5000b000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x9000 0x400>;
|
|
- clocks = <&rcc GPIOJ>;
|
|
- st,bank-name = "GPIOJ";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiok: gpio@5000c000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0xa000 0x400>;
|
|
- clocks = <&rcc GPIOK>;
|
|
- st,bank-name = "GPIOK";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- cec_pins_a: cec-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_sleep_a: cec-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_b: cec-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_sleep_b: cec-sleep-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
|
|
- };
|
|
- };
|
|
-
|
|
- dcmi_pins_a: dcmi-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
|
|
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
|
|
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
|
|
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
|
|
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
|
|
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
|
|
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
|
|
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
|
|
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
|
|
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
|
|
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
|
|
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
|
|
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
|
|
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
|
|
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- dcmi_sleep_pins_a: dcmi-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
|
|
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
|
|
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
|
|
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
|
|
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
|
|
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
|
|
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
|
|
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
|
|
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
|
|
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
|
|
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
|
|
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
|
|
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
|
|
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
|
|
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
|
|
- };
|
|
- };
|
|
-
|
|
- ethernet0_rgmii_pins_a: rgmii-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
|
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
|
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
|
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
|
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
|
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
|
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
|
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
|
|
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
|
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
|
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
|
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
|
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
|
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
|
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
|
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
|
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
|
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
|
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
|
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
|
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
|
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
|
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
|
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
|
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
|
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
|
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
|
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
|
- };
|
|
- };
|
|
-
|
|
- fmc_pins_a: fmc-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
|
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
|
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- fmc_sleep_pins_a: fmc-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
|
|
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
|
|
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
|
|
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
|
|
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
|
|
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
|
|
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
|
|
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
|
|
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
|
|
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
|
|
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
|
|
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
|
|
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
|
|
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_a: i2c1-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_sleep_a: i2c1-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_b: i2c1-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_sleep_b: i2c1-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_a: i2c2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
|
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_a: i2c2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
|
|
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_b1: i2c2-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_b1: i2c2-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c5_pins_a: i2c5-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
|
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c5_pins_sleep_a: i2c5-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
|
|
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
|
|
-
|
|
- };
|
|
- };
|
|
-
|
|
- i2s2_pins_a: i2s2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
|
|
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
|
|
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- i2s2_pins_sleep_a: i2s2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
|
|
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
|
|
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_a: ltdc-a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
|
|
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_sleep_a: ltdc-a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
|
|
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_b: ltdc-b-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
|
|
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_sleep_b: ltdc-b-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
|
|
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
|
|
- };
|
|
- };
|
|
-
|
|
- m_can1_pins_a: m-can1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- m_can1_sleep_pins_a: m_can1-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
|
|
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
|
|
- };
|
|
- };
|
|
-
|
|
- pwm2_pins_a: pwm2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- pwm8_pins_a: pwm8-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- pwm12_pins_a: pwm12-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_clk_pins_a: qspi-clk-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk1_pins_a: qspi-bk1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
- bias-pull-up;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
|
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
|
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
|
|
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
|
|
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk2_pins_a: qspi-bk2-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
- bias-pull-up;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
|
|
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
|
|
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
|
|
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
|
|
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2a_pins_a: sai2a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
|
|
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
|
|
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
|
|
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2a_sleep_pins_a: sai2a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
|
|
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
|
|
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
|
|
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_pins_a: sai2b-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
|
|
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
|
|
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_sleep_pins_a: sai2b-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
|
|
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
|
|
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
|
|
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_pins_b: sai2b-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_sleep_pins_b: sai2b-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
|
|
- };
|
|
- };
|
|
-
|
|
- sai4a_pins_a: sai4a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai4a_sleep_pins_a: sai4a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
|
|
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2{
|
|
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
- slew-rate = <3>;
|
|
- drive-open-drain;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
|
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
|
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
|
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- pins2{
|
|
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
|
|
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
|
|
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
|
|
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
|
|
- };
|
|
- };
|
|
-
|
|
- spdifrx_pins_a: spdifrx-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- spdifrx_sleep_pins_a: spdifrx-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
|
|
- };
|
|
- };
|
|
-
|
|
- uart4_pins_a: uart4-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- uart4_pins_b: uart4-1 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- uart7_pins_a: uart7-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
|
|
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
|
|
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- compatible = "st,stm32mp157-z-pinctrl";
|
|
- ranges = <0 0x54004000 0x400>;
|
|
- pins-are-numbered;
|
|
- interrupt-parent = <&exti>;
|
|
- st,syscfg = <&exti 0x60 0xff>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0 0x400>;
|
|
- clocks = <&rcc GPIOZ>;
|
|
- st,bank-name = "GPIOZ";
|
|
- st,bank-ioport = <11>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c2_pins_b2: i2c2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_b2: i2c2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c4_pins_a: i2c4-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c4_pins_sleep_a: i2c4-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
|
|
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- spi1_pins_a: spi1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
|
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
-
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi
|
|
new file mode 100644
|
|
index 000000000..ce1d83aa7
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157.dtsi
|
|
@@ -0,0 +1,32 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp153.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ gpu: gpu@59000000 {
|
|
+ compatible = "vivante,gc";
|
|
+ reg = <0x59000000 0x800>;
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
|
|
+ clock-names = "bus" ,"core";
|
|
+ resets = <&rcc GPU_R>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dsi: dsi@5a000000 {
|
|
+ compatible = "st,stm32-dsi";
|
|
+ reg = <0x5a000000 0x800>;
|
|
+ phy-dsi-supply = <®18>;
|
|
+ clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>;
|
|
+ clock-names = "pclk", "ref", "px_clk";
|
|
+ resets = <&rcc DSI_R>;
|
|
+ reset-names = "apb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
|
|
index 2e4742c53..887b76662 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts
|
|
+++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
|
|
@@ -6,9 +6,10 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xac-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
#include <dt-bindings/mfd/st,stpmic1.h>
|
|
|
|
/ {
|
|
@@ -252,14 +253,13 @@
|
|
regulator-name = "vbus_otg";
|
|
interrupts = <IT_OCP_OTG 0>;
|
|
interrupt-parent = <&pmic>;
|
|
- regulator-active-discharge;
|
|
};
|
|
|
|
vbus_sw: pwr_sw2 {
|
|
regulator-name = "vbus_sw";
|
|
interrupts = <IT_OCP_SWOUT 0>;
|
|
interrupt-parent = <&pmic>;
|
|
- regulator-active-discharge;
|
|
+ regulator-active-discharge = <1>;
|
|
};
|
|
};
|
|
|
|
@@ -282,6 +282,11 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
&rng1 {
|
|
status = "okay";
|
|
};
|
|
@@ -295,7 +300,7 @@
|
|
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
- broken-cd;
|
|
+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
st,sig-dir;
|
|
st,neg-edge;
|
|
st,use-ckin;
|
|
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
|
|
index 0615d1c8a..baff3f694 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
|
|
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
|
|
@@ -6,11 +6,11 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xac-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include <dt-bindings/mfd/st,stpmic1.h>
|
|
-
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
|
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
|
|
@@ -18,434 +18,27 @@
|
|
aliases {
|
|
ethernet0 = ðernet0;
|
|
serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
- memory@c0000000 {
|
|
- reg = <0xc0000000 0x20000000>;
|
|
- };
|
|
-
|
|
reserved-memory {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges;
|
|
-
|
|
- mcuram2: mcuram2@10000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring0: vdev0vring0@10040000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10040000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring1: vdev0vring1@10041000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10041000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0buffer: vdev0buffer@10042000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10042000 0x4000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- mcuram: mcuram@30000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x30000000 0x40000>;
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
no-map;
|
|
};
|
|
|
|
- retram: retram@38000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x38000000 0x10000>;
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
no-map;
|
|
};
|
|
-
|
|
- gpu_reserved: gpu@d4000000 {
|
|
- reg = <0xd4000000 0x4000000>;
|
|
- no-map;
|
|
- };
|
|
- };
|
|
-
|
|
- led {
|
|
- compatible = "gpio-leds";
|
|
- blue {
|
|
- label = "heartbeat";
|
|
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
|
- linux,default-trigger = "heartbeat";
|
|
- default-state = "off";
|
|
- };
|
|
- };
|
|
-
|
|
- sound {
|
|
- compatible = "audio-graph-card";
|
|
- label = "STM32MP1-DK";
|
|
- routing =
|
|
- "Playback" , "MCLK",
|
|
- "Capture" , "MCLK",
|
|
- "MICL" , "Mic Bias";
|
|
- dais = <&sai2a_port &sai2b_port>;
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&cec {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&cec_pins_b>;
|
|
- pinctrl-1 = <&cec_pins_sleep_b>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-ðernet0 {
|
|
- status = "okay";
|
|
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- phy-mode = "rgmii-id";
|
|
- max-speed = <1000>;
|
|
- phy-handle = <&phy0>;
|
|
-
|
|
- mdio0 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "snps,dwmac-mdio";
|
|
- phy0: ethernet-phy@0 {
|
|
- reg = <0>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&gpu {
|
|
- contiguous-area = <&gpu_reserved>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&i2c1 {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&i2c1_pins_a>;
|
|
- pinctrl-1 = <&i2c1_pins_sleep_a>;
|
|
- i2c-scl-rising-time-ns = <100>;
|
|
- i2c-scl-falling-time-ns = <7>;
|
|
- status = "okay";
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- hdmi-transmitter@39 {
|
|
- compatible = "sil,sii9022";
|
|
- reg = <0x39>;
|
|
- iovcc-supply = <&v3v3_hdmi>;
|
|
- cvcc12-supply = <&v1v2_hdmi>;
|
|
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
|
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-parent = <&gpiog>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <<dc_pins_a>;
|
|
- pinctrl-1 = <<dc_pins_sleep_a>;
|
|
- status = "okay";
|
|
-
|
|
- ports {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- port@0 {
|
|
- reg = <0>;
|
|
- sii9022_in: endpoint {
|
|
- remote-endpoint = <<dc_ep0_out>;
|
|
- };
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- cs42l51: cs42l51@4a {
|
|
- compatible = "cirrus,cs42l51";
|
|
- reg = <0x4a>;
|
|
- #sound-dai-cells = <0>;
|
|
- VL-supply = <&v3v3>;
|
|
- VD-supply = <&v1v8_audio>;
|
|
- VA-supply = <&v1v8_audio>;
|
|
- VAHP-supply = <&v1v8_audio>;
|
|
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
|
- clocks = <&sai2a>;
|
|
- clock-names = "MCLK";
|
|
- status = "okay";
|
|
-
|
|
- cs42l51_port: port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- cs42l51_tx_endpoint: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&sai2a_endpoint>;
|
|
- frame-master;
|
|
- bitclock-master;
|
|
- };
|
|
-
|
|
- cs42l51_rx_endpoint: endpoint@1 {
|
|
- reg = <1>;
|
|
- remote-endpoint = <&sai2b_endpoint>;
|
|
- frame-master;
|
|
- bitclock-master;
|
|
- };
|
|
- };
|
|
};
|
|
};
|
|
|
|
-&i2c4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c4_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- pmic: stpmic@33 {
|
|
- compatible = "st,stpmic1";
|
|
- reg = <0x33>;
|
|
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- status = "okay";
|
|
-
|
|
- regulators {
|
|
- compatible = "st,stpmic1-regulators";
|
|
- ldo1-supply = <&v3v3>;
|
|
- ldo3-supply = <&vdd_ddr>;
|
|
- ldo6-supply = <&v3v3>;
|
|
- pwr_sw1-supply = <&bst_out>;
|
|
- pwr_sw2-supply = <&bst_out>;
|
|
-
|
|
- vddcore: buck1 {
|
|
- regulator-name = "vddcore";
|
|
- regulator-min-microvolt = <800000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_ddr: buck2 {
|
|
- regulator-name = "vdd_ddr";
|
|
- regulator-min-microvolt = <1350000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd: buck3 {
|
|
- regulator-name = "vdd";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- st,mask-reset;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- v3v3: buck4 {
|
|
- regulator-name = "v3v3";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- regulator-initial-mode = <0>;
|
|
- };
|
|
-
|
|
- v1v8_audio: ldo1 {
|
|
- regulator-name = "v1v8_audio";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO1 0>;
|
|
- };
|
|
-
|
|
- v3v3_hdmi: ldo2 {
|
|
- regulator-name = "v3v3_hdmi";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO2 0>;
|
|
- };
|
|
-
|
|
- vtt_ddr: ldo3 {
|
|
- regulator-name = "vtt_ddr";
|
|
- regulator-min-microvolt = <500000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_usb: ldo4 {
|
|
- regulator-name = "vdd_usb";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- interrupts = <IT_CURLIM_LDO4 0>;
|
|
- };
|
|
-
|
|
- vdda: ldo5 {
|
|
- regulator-name = "vdda";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO5 0>;
|
|
- regulator-boot-on;
|
|
- };
|
|
-
|
|
- v1v2_hdmi: ldo6 {
|
|
- regulator-name = "v1v2_hdmi";
|
|
- regulator-min-microvolt = <1200000>;
|
|
- regulator-max-microvolt = <1200000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO6 0>;
|
|
- };
|
|
-
|
|
- vref_ddr: vref_ddr {
|
|
- regulator-name = "vref_ddr";
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- bst_out: boost {
|
|
- regulator-name = "bst_out";
|
|
- interrupts = <IT_OCP_BOOST 0>;
|
|
- };
|
|
-
|
|
- vbus_otg: pwr_sw1 {
|
|
- regulator-name = "vbus_otg";
|
|
- interrupts = <IT_OCP_OTG 0>;
|
|
- };
|
|
-
|
|
- vbus_sw: pwr_sw2 {
|
|
- regulator-name = "vbus_sw";
|
|
- interrupts = <IT_OCP_SWOUT 0>;
|
|
- regulator-active-discharge;
|
|
- };
|
|
- };
|
|
-
|
|
- onkey {
|
|
- compatible = "st,stpmic1-onkey";
|
|
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
- interrupt-names = "onkey-falling", "onkey-rising";
|
|
- power-off-time-sec = <10>;
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- watchdog {
|
|
- compatible = "st,stpmic1-wdt";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&ipcc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&iwdg2 {
|
|
- timeout-sec = <32>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-<dc {
|
|
- status = "okay";
|
|
-
|
|
- port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- ltdc_ep0_out: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&sii9022_in>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&m4_rproc {
|
|
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
- <&vdev0vring1>, <&vdev0buffer>;
|
|
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
- mbox-names = "vq0", "vq1", "shutdown";
|
|
- interrupt-parent = <&exti>;
|
|
- interrupts = <68 1>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rng1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rtc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sai2 {
|
|
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
- clock-names = "pclk", "x8k", "x11k";
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
|
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
|
- status = "okay";
|
|
-
|
|
- sai2a: audio-controller@4400b004 {
|
|
- #clock-cells = <0>;
|
|
- dma-names = "tx";
|
|
- clocks = <&rcc SAI2_K>;
|
|
- clock-names = "sai_ck";
|
|
- status = "okay";
|
|
-
|
|
- sai2a_port: port {
|
|
- sai2a_endpoint: endpoint {
|
|
- remote-endpoint = <&cs42l51_tx_endpoint>;
|
|
- format = "i2s";
|
|
- mclk-fs = <256>;
|
|
- dai-tdm-slot-num = <2>;
|
|
- dai-tdm-slot-width = <32>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b: audio-controller@4400b024 {
|
|
- dma-names = "rx";
|
|
- st,sync = <&sai2a 2>;
|
|
- clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
- clock-names = "sai_ck", "MCLK";
|
|
- status = "okay";
|
|
-
|
|
- sai2b_port: port {
|
|
- sai2b_endpoint: endpoint {
|
|
- remote-endpoint = <&cs42l51_rx_endpoint>;
|
|
- format = "i2s";
|
|
- mclk-fs = <256>;
|
|
- dai-tdm-slot-num = <2>;
|
|
- dai-tdm-slot-width = <32>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- pinctrl-names = "default", "opendrain", "sleep";
|
|
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
|
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
- broken-cd;
|
|
- st,neg-edge;
|
|
- bus-width = <4>;
|
|
- vmmc-supply = <&v3v3>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&uart4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&uart4_pins_a>;
|
|
+&optee {
|
|
status = "okay";
|
|
};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157a-ed1.dts b/arch/arm/boot/dts/stm32mp157a-ed1.dts
|
|
new file mode 100644
|
|
index 000000000..5dca95684
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157a-ed1.dts
|
|
@@ -0,0 +1,52 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157A eval daughter";
|
|
+ compatible = "st,stm32mp157a-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157a-ev1.dts b/arch/arm/boot/dts/stm32mp157a-ev1.dts
|
|
new file mode 100644
|
|
index 000000000..29ecd15c3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157a-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157a-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157A eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
|
|
new file mode 100644
|
|
index 000000000..1bffbc629
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
|
|
@@ -0,0 +1,46 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157c-dk2.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157C-DK2 configured to run Linux A7 examples";
|
|
+ compatible = "st,stm32mp157c-dk2-a7-examples", "st,stm32mp157c-dk2", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers4 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers5 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
|
|
new file mode 100644
|
|
index 000000000..14eac740d
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
|
|
@@ -0,0 +1,129 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157c-dk2.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157C-DK2 configured to run M4 examples";
|
|
+ compatible = "st,stm32mp157c-dk2-m4-examples", "st,stm32mp157c-dk2", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dmamux1 {
|
|
+ dma-masters = <&dma1>;
|
|
+ dma-channels = <8>;
|
|
+};
|
|
+
|
|
+&m4_adc {
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dac {
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dma2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_crc2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_cryp2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_hash2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_i2c5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_i2c5_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rng2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ status = "okay";
|
|
+
|
|
+ button {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ interrupt-parent = <&gpioa>;
|
|
+ interrupts = <14 2>;
|
|
+ interrupt-names = "irq";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ m4_led: m4_led {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_leds_orange_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_spi4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_spi4_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+&m4_timers2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_timers1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_uart7 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_uart7_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ m4_leds_orange_pins: m4-leds-orange-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ status = "disabled";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
|
|
index 20ea601a5..a7d5e86a1 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
|
|
@@ -6,26 +6,55 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157a-dk1.dts"
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xc.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+#include <dt-bindings/rtc/rtc-stm32.h>
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
|
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
|
|
|
- reg18: reg18 {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "reg18";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-always-on;
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ serial3 = &usart2;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
+};
|
|
+
|
|
&dsi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
- phy-dsi-supply = <®18>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
@@ -46,7 +75,7 @@
|
|
};
|
|
};
|
|
|
|
- panel@0 {
|
|
+ panel_otm8009a: panel-otm8009a@0 {
|
|
compatible = "orisetech,otm8009a";
|
|
reg = <0>;
|
|
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
|
@@ -61,6 +90,31 @@
|
|
};
|
|
};
|
|
|
|
+&i2c1 {
|
|
+ touchscreen@2a {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x2a>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ touchscreen@38 {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x38>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
<dc {
|
|
status = "okay";
|
|
|
|
@@ -74,3 +128,57 @@
|
|
};
|
|
};
|
|
};
|
|
+
|
|
+&rtc {
|
|
+ st,lsco = <RTC_OUT2_RMP>;
|
|
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+/* Wifi */
|
|
+&sdmmc2 {
|
|
+ arm,primecell-periphid = <0x10153180>;
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ brcmf: bcrmf@1 {
|
|
+ reg = <1>;
|
|
+ compatible = "brcm,bcm4329-fmac";
|
|
+ };
|
|
+};
|
|
+
|
|
+/* Bluetooth */
|
|
+&usart2 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart2_pins_a>;
|
|
+ pinctrl-1 = <&usart2_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart2_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
|
|
+ compatible = "brcm,bcm43438-bt";
|
|
+ max-speed = <3000000>;
|
|
+ vbat-supply = <&v3v3>;
|
|
+ vddio-supply = <&v3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee_memory {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
|
|
index 1d426ea8b..bf2d7e7b7 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
|
|
@@ -1,14 +1,17 @@
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xaa-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xc.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C eval daughter";
|
|
@@ -18,94 +21,29 @@
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
- memory@c0000000 {
|
|
- device_type = "memory";
|
|
- reg = <0xC0000000 0x40000000>;
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
};
|
|
|
|
reserved-memory {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges;
|
|
-
|
|
- mcuram2: mcuram2@10000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring0: vdev0vring0@10040000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10040000 0x1000>;
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
no-map;
|
|
};
|
|
|
|
- vdev0vring1: vdev0vring1@10041000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10041000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0buffer: vdev0buffer@10042000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10042000 0x4000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- mcuram: mcuram@30000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x30000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- retram: retram@38000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x38000000 0x10000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- gpu_reserved: gpu@e8000000 {
|
|
- reg = <0xe8000000 0x8000000>;
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
no-map;
|
|
};
|
|
};
|
|
+};
|
|
|
|
- aliases {
|
|
- serial0 = &uart4;
|
|
- };
|
|
-
|
|
- reg11: reg11 {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "reg11";
|
|
- regulator-min-microvolt = <1100000>;
|
|
- regulator-max-microvolt = <1100000>;
|
|
- regulator-always-on;
|
|
- };
|
|
-
|
|
- reg18: reg18 {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "reg18";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-always-on;
|
|
- };
|
|
-
|
|
- sd_switch: regulator-sd_switch {
|
|
- compatible = "regulator-gpio";
|
|
- regulator-name = "sd_switch";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- regulator-type = "voltage";
|
|
- regulator-always-on;
|
|
-
|
|
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
|
|
- gpios-states = <0>;
|
|
- states = <1800000 0x1 2900000 0x0>;
|
|
- };
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
};
|
|
|
|
-&dts {
|
|
- status = "okay";
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
};
|
|
|
|
&gpu {
|
|
@@ -113,219 +51,6 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&i2c4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c4_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
+&optee {
|
|
status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- pmic: stpmic@33 {
|
|
- compatible = "st,stpmic1";
|
|
- reg = <0x33>;
|
|
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- status = "okay";
|
|
-
|
|
- regulators {
|
|
- compatible = "st,stpmic1-regulators";
|
|
- ldo1-supply = <&v3v3>;
|
|
- ldo2-supply = <&v3v3>;
|
|
- ldo3-supply = <&vdd_ddr>;
|
|
- ldo5-supply = <&v3v3>;
|
|
- ldo6-supply = <&v3v3>;
|
|
- pwr_sw1-supply = <&bst_out>;
|
|
- pwr_sw2-supply = <&bst_out>;
|
|
-
|
|
- vddcore: buck1 {
|
|
- regulator-name = "vddcore";
|
|
- regulator-min-microvolt = <800000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_ddr: buck2 {
|
|
- regulator-name = "vdd_ddr";
|
|
- regulator-min-microvolt = <1350000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd: buck3 {
|
|
- regulator-name = "vdd";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- st,mask-reset;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- v3v3: buck4 {
|
|
- regulator-name = "v3v3";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- regulator-initial-mode = <0>;
|
|
- };
|
|
-
|
|
- vdda: ldo1 {
|
|
- regulator-name = "vdda";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO1 0>;
|
|
- };
|
|
-
|
|
- v2v8: ldo2 {
|
|
- regulator-name = "v2v8";
|
|
- regulator-min-microvolt = <2800000>;
|
|
- regulator-max-microvolt = <2800000>;
|
|
- interrupts = <IT_CURLIM_LDO2 0>;
|
|
- };
|
|
-
|
|
- vtt_ddr: ldo3 {
|
|
- regulator-name = "vtt_ddr";
|
|
- regulator-min-microvolt = <500000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_usb: ldo4 {
|
|
- regulator-name = "vdd_usb";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- interrupts = <IT_CURLIM_LDO4 0>;
|
|
- };
|
|
-
|
|
- vdd_sd: ldo5 {
|
|
- regulator-name = "vdd_sd";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO5 0>;
|
|
- regulator-boot-on;
|
|
- };
|
|
-
|
|
- v1v8: ldo6 {
|
|
- regulator-name = "v1v8";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- interrupts = <IT_CURLIM_LDO6 0>;
|
|
- };
|
|
-
|
|
- vref_ddr: vref_ddr {
|
|
- regulator-name = "vref_ddr";
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- bst_out: boost {
|
|
- regulator-name = "bst_out";
|
|
- interrupts = <IT_OCP_BOOST 0>;
|
|
- };
|
|
-
|
|
- vbus_otg: pwr_sw1 {
|
|
- regulator-name = "vbus_otg";
|
|
- interrupts = <IT_OCP_OTG 0>;
|
|
- };
|
|
-
|
|
- vbus_sw: pwr_sw2 {
|
|
- regulator-name = "vbus_sw";
|
|
- interrupts = <IT_OCP_SWOUT 0>;
|
|
- regulator-active-discharge;
|
|
- };
|
|
- };
|
|
-
|
|
- onkey {
|
|
- compatible = "st,stpmic1-onkey";
|
|
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
- interrupt-names = "onkey-falling", "onkey-rising";
|
|
- power-off-time-sec = <10>;
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- watchdog {
|
|
- compatible = "st,stpmic1-wdt";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&ipcc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&iwdg2 {
|
|
- timeout-sec = <32>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&m4_rproc {
|
|
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
- <&vdev0vring1>, <&vdev0buffer>;
|
|
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
- mbox-names = "vq0", "vq1", "shutdown";
|
|
- interrupt-parent = <&exti>;
|
|
- interrupts = <68 1>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rng1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rtc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- pinctrl-names = "default", "opendrain", "sleep";
|
|
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
|
- broken-cd;
|
|
- st,sig-dir;
|
|
- st,neg-edge;
|
|
- st,use-ckin;
|
|
- bus-width = <4>;
|
|
- vmmc-supply = <&vdd_sd>;
|
|
- vqmmc-supply = <&sd_switch>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&timers6 {
|
|
- status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- timer@5 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&uart4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&uart4_pins_a>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbphyc_port0 {
|
|
- phy-supply = <&vdd_usb>;
|
|
- vdda1v1-supply = <®11>;
|
|
- vdda1v8-supply = <®18>;
|
|
-};
|
|
-
|
|
-&usbphyc_port1 {
|
|
- phy-supply = <&vdd_usb>;
|
|
- vdda1v1-supply = <®11>;
|
|
- vdda1v8-supply = <®18>;
|
|
};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
|
|
new file mode 100644
|
|
index 000000000..25c9f4f2f
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
|
|
@@ -0,0 +1,53 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157c-ev1.dts"
|
|
+#include <dt-bindings/input/input.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157C-EV1 configured to run Linux A7 examples";
|
|
+ compatible = "st,stm32mp157c-ev1-a7-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
|
+
|
|
+ test_keys {
|
|
+ compatible = "gpio-keys";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ autorepeat;
|
|
+ status = "okay";
|
|
+ /* gpio needs vdd core in retention for wakeup */
|
|
+ power-domains = <&pd_core_ret>;
|
|
+
|
|
+ button@1 {
|
|
+ label = "PA13";
|
|
+ linux,code = <BTN_1>;
|
|
+ interrupts-extended = <&gpioa 13 IRQ_TYPE_EDGE_FALLING>;
|
|
+ status = "okay";
|
|
+ wakeup-source;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers8 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
|
|
new file mode 100644
|
|
index 000000000..b1bb38efb
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
|
|
@@ -0,0 +1,146 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157c-ev1.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157C-EV1 configured to run M4 examples";
|
|
+ compatible = "st,stm32mp157c-ev1-m4-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dcmi {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dmamux1 {
|
|
+ dma-masters = <&dma1>;
|
|
+ dma-channels = <8>;
|
|
+};
|
|
+
|
|
+&fmc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&m4_adc {
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_crc2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_cryp2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dac {
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dma2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_hash2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_i2c5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_i2c5_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_qspi {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a
|
|
+ &m4_qspi_bk2_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ status = "okay";
|
|
+
|
|
+ /* button {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ interrupt-parent = <&gpioa>;
|
|
+ interrupts = <14 2>;
|
|
+ interrupt-names = "irq";
|
|
+ status = "okay";
|
|
+ };*/
|
|
+
|
|
+ m4_led: m4_led {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_leds_orange_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_rng2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_spi1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_spi1_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+&m4_timers2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_pwm2_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_usart3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_usart3_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ m4_leds_orange_pins: m4-leds-orange-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 8, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sai2b {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ status = "disabled";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
|
|
index 91fc0a315..c60727d9b 100644
|
|
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
|
|
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
|
|
@@ -1,13 +1,14 @@
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "stm32mp157c-ed1.dts"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
|
@@ -18,90 +19,14 @@
|
|
};
|
|
|
|
aliases {
|
|
- serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
ethernet0 = ðernet0;
|
|
};
|
|
-
|
|
- clocks {
|
|
- clk_ext_camera: clk-ext-camera {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <24000000>;
|
|
- };
|
|
- };
|
|
-
|
|
- joystick {
|
|
- compatible = "gpio-keys";
|
|
- #size-cells = <0>;
|
|
- pinctrl-0 = <&joystick_pins>;
|
|
- pinctrl-names = "default";
|
|
- button-0 {
|
|
- label = "JoySel";
|
|
- linux,code = <KEY_ENTER>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-1 {
|
|
- label = "JoyDown";
|
|
- linux,code = <KEY_DOWN>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-2 {
|
|
- label = "JoyLeft";
|
|
- linux,code = <KEY_LEFT>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-3 {
|
|
- label = "JoyRight";
|
|
- linux,code = <KEY_RIGHT>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-4 {
|
|
- label = "JoyUp";
|
|
- linux,code = <KEY_UP>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- };
|
|
-
|
|
- panel_backlight: panel-backlight {
|
|
- compatible = "gpio-backlight";
|
|
- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
|
- default-on;
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&cec {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&cec_pins_a>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&dcmi {
|
|
- status = "okay";
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&dcmi_pins_a>;
|
|
- pinctrl-1 = <&dcmi_sleep_pins_a>;
|
|
-
|
|
- port {
|
|
- dcmi_0: endpoint {
|
|
- remote-endpoint = <&ov5640_0>;
|
|
- bus-width = <8>;
|
|
- hsync-active = <0>;
|
|
- vsync-active = <0>;
|
|
- pclk-sample = <1>;
|
|
- };
|
|
- };
|
|
};
|
|
|
|
&dsi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
- phy-dsi-supply = <®18>;
|
|
status = "okay";
|
|
|
|
ports {
|
|
@@ -123,7 +48,7 @@
|
|
};
|
|
};
|
|
|
|
- panel-dsi@0 {
|
|
+ panel_dsi: panel-dsi@0 {
|
|
compatible = "raydium,rm68200";
|
|
reg = <0>;
|
|
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
@@ -139,113 +64,17 @@
|
|
};
|
|
};
|
|
|
|
-ðernet0 {
|
|
- status = "okay";
|
|
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- phy-mode = "rgmii-id";
|
|
- max-speed = <1000>;
|
|
- phy-handle = <&phy0>;
|
|
-
|
|
- mdio0 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "snps,dwmac-mdio";
|
|
- phy0: ethernet-phy@0 {
|
|
- reg = <0>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&fmc {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&fmc_pins_a>;
|
|
- pinctrl-1 = <&fmc_sleep_pins_a>;
|
|
- status = "okay";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- nand@0 {
|
|
- reg = <0>;
|
|
- nand-on-flash-bbt;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-};
|
|
-
|
|
&i2c2 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c2_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
-
|
|
- ov5640: camera@3c {
|
|
- compatible = "ovti,ov5640";
|
|
- reg = <0x3c>;
|
|
- clocks = <&clk_ext_camera>;
|
|
- clock-names = "xclk";
|
|
- DOVDD-supply = <&v2v8>;
|
|
- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
|
|
- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
|
|
- rotation = <180>;
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
- port {
|
|
- ov5640_0: endpoint {
|
|
- remote-endpoint = <&dcmi_0>;
|
|
- bus-width = <8>;
|
|
- data-shift = <2>; /* lines 9:2 are used */
|
|
- hsync-active = <0>;
|
|
- vsync-active = <0>;
|
|
- pclk-sample = <1>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- stmfx: stmfx@42 {
|
|
- compatible = "st,stmfx-0300";
|
|
- reg = <0x42>;
|
|
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
|
- interrupt-parent = <&gpioi>;
|
|
- vdd-supply = <&v3v3>;
|
|
-
|
|
- stmfx_pinctrl: stmfx-pin-controller {
|
|
- compatible = "st,stmfx-0300-pinctrl";
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
|
-
|
|
- joystick_pins: joystick {
|
|
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
|
- bias-pull-down;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c5 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c5_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-<dc {
|
|
- status = "okay";
|
|
-
|
|
- port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- ltdc_ep0_out: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&dsi_in>;
|
|
- };
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
};
|
|
};
|
|
|
|
@@ -255,97 +84,3 @@
|
|
pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&qspi {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
|
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
|
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "okay";
|
|
-
|
|
- flash0: mx66l51235l@0 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <0>;
|
|
- spi-rx-bus-width = <4>;
|
|
- spi-max-frequency = <108000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-
|
|
- flash1: mx66l51235l@1 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <1>;
|
|
- spi-rx-bus-width = <4>;
|
|
- spi-max-frequency = <108000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-};
|
|
-
|
|
-&spi1 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&spi1_pins_a>;
|
|
- status = "disabled";
|
|
-};
|
|
-
|
|
-&timers2 {
|
|
- /* spare dmas for other usage (un-delete to enable pwm capture) */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm2_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@1 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&timers8 {
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm8_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@7 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&timers12 {
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm12_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@11 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&usbh_ehci {
|
|
- phys = <&usbphyc_port0>;
|
|
- phy-names = "usb";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbotg_hs {
|
|
- dr_mode = "peripheral";
|
|
- phys = <&usbphyc_port1 0>;
|
|
- phy-names = "usb2-phy";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbphyc {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157d-dk1.dts b/arch/arm/boot/dts/stm32mp157d-dk1.dts
|
|
new file mode 100644
|
|
index 000000000..c7d65a65e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157d-dk1.dts
|
|
@@ -0,0 +1,44 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xd.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
|
|
+ compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157d-ed1.dts b/arch/arm/boot/dts/stm32mp157d-ed1.dts
|
|
new file mode 100644
|
|
index 000000000..ee55ac8f3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157d-ed1.dts
|
|
@@ -0,0 +1,52 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xd.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D eval daughter";
|
|
+ compatible = "st,stm32mp157d-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157d-ev1.dts b/arch/arm/boot/dts/stm32mp157d-ev1.dts
|
|
new file mode 100644
|
|
index 000000000..a4752c100
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157d-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157d-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
|
|
new file mode 100644
|
|
index 000000000..2a8c46059
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
|
|
@@ -0,0 +1,46 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-dk2.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-DK2 configured to run Linux A7 examples";
|
|
+ compatible = "st,stm32mp157f-dk2-a7-examples", "st,stm32mp157f-dk2", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers4 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers5 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
|
|
new file mode 100644
|
|
index 000000000..726522997
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
|
|
@@ -0,0 +1,129 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-dk2.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-DK2 configured to run M4 examples";
|
|
+ compatible = "st,stm32mp157f-dk2-m4-examples", "st,stm32mp157f-dk2", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dmamux1 {
|
|
+ dma-masters = <&dma1>;
|
|
+ dma-channels = <8>;
|
|
+};
|
|
+
|
|
+&m4_adc {
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dac {
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dma2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_crc2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_cryp2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_hash2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_i2c5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_i2c5_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rng2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ status = "okay";
|
|
+
|
|
+ button {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ interrupt-parent = <&gpioa>;
|
|
+ interrupts = <14 2>;
|
|
+ interrupt-names = "irq";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ m4_led: m4_led {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_leds_orange_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_spi4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_spi4_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+&m4_timers2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_timers1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_uart7 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_uart7_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ m4_leds_orange_pins: m4-leds-orange-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ status = "disabled";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2.dts b/arch/arm/boot/dts/stm32mp157f-dk2.dts
|
|
new file mode 100644
|
|
index 000000000..b57db3037
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-dk2.dts
|
|
@@ -0,0 +1,185 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xf.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+#include <dt-bindings/rtc/rtc-stm32.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
|
|
+ compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ serial3 = &usart2;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep1_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_otm8009a: panel-otm8009a@0 {
|
|
+ compatible = "orisetech,otm8009a";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ touchscreen@2a {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x2a>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ touchscreen@38 {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x38>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep1_out: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&dsi_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ st,lsco = <RTC_OUT2_RMP>;
|
|
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+/* Wifi */
|
|
+&sdmmc2 {
|
|
+ arm,primecell-periphid = <0x10153180>;
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ brcmf: bcrmf@1 {
|
|
+ reg = <1>;
|
|
+ compatible = "brcm,bcm4329-fmac";
|
|
+ };
|
|
+};
|
|
+
|
|
+/* Bluetooth */
|
|
+&usart2 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart2_pins_a>;
|
|
+ pinctrl-1 = <&usart2_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart2_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
|
|
+ compatible = "brcm,bcm43438-bt";
|
|
+ max-speed = <3000000>;
|
|
+ vbat-supply = <&v3v3>;
|
|
+ vddio-supply = <&v3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee_memory {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-ed1.dts b/arch/arm/boot/dts/stm32mp157f-ed1.dts
|
|
new file mode 100644
|
|
index 000000000..65380693c
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-ed1.dts
|
|
@@ -0,0 +1,56 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xf.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F eval daughter";
|
|
+ compatible = "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xfe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
|
|
new file mode 100644
|
|
index 000000000..17d92b7be
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
|
|
@@ -0,0 +1,53 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-ev1.dts"
|
|
+#include <dt-bindings/input/input.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-EV1 configured to run Linux A7 examples";
|
|
+ compatible = "st,stm32mp157f-ev1-a7-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+
|
|
+ test_keys {
|
|
+ compatible = "gpio-keys";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ autorepeat;
|
|
+ status = "okay";
|
|
+ /* gpio needs vdd core in retention for wakeup */
|
|
+ power-domains = <&pd_core_ret>;
|
|
+
|
|
+ button@1 {
|
|
+ label = "PA13";
|
|
+ linux,code = <BTN_1>;
|
|
+ interrupts-extended = <&gpioa 13 IRQ_TYPE_EDGE_FALLING>;
|
|
+ status = "okay";
|
|
+ wakeup-source;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers8 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
|
|
new file mode 100644
|
|
index 000000000..d508be276
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
|
|
@@ -0,0 +1,146 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-ev1.dts"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-EV1 configured to run M4 examples";
|
|
+ compatible = "st,stm32mp157f-ev1-m4-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dcmi {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dmamux1 {
|
|
+ dma-masters = <&dma1>;
|
|
+ dma-channels = <8>;
|
|
+};
|
|
+
|
|
+&fmc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&m4_adc {
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_crc2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_cryp2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dac {
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_dma2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_hash2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_i2c5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_i2c5_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_qspi {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a
|
|
+ &m4_qspi_bk2_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ status = "okay";
|
|
+
|
|
+ /* button {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ interrupt-parent = <&gpioa>;
|
|
+ interrupts = <14 2>;
|
|
+ interrupt-names = "irq";
|
|
+ status = "okay";
|
|
+ };*/
|
|
+
|
|
+ m4_led: m4_led {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_leds_orange_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_rng2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_spi1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_spi1_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+
|
|
+&m4_timers2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_pwm2_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_usart3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&m4_usart3_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ m4_leds_orange_pins: m4-leds-orange-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 8, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sai2b {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ status = "disabled";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1.dts b/arch/arm/boot/dts/stm32mp157f-ev1.dts
|
|
new file mode 100644
|
|
index 000000000..0c18333c0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp157f-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 875adf5e1..000000000
|
|
--- a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,90 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AA>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 80 16>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 96 16>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 112 16>;
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 128 16>;
|
|
- };
|
|
-
|
|
- gpioj: gpio@5000b000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 144 16>;
|
|
- };
|
|
-
|
|
- gpiok: gpio@5000c000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl 0 160 8>;
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- st,package = <STM32MP_PKG_AA>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 961fa12a5..000000000
|
|
--- a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,62 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AB>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <6>;
|
|
- gpio-ranges = <&pinctrl 6 86 6>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <10>;
|
|
- gpio-ranges = <&pinctrl 6 102 10>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <2>;
|
|
- gpio-ranges = <&pinctrl 0 112 2>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 26600f188..000000000
|
|
--- a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,78 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AC>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 80 16>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 96 16>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 112 16>;
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- status = "okay";
|
|
- ngpios = <12>;
|
|
- gpio-ranges = <&pinctrl 0 128 12>;
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- st,package = <STM32MP_PKG_AC>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 910113f3e..000000000
|
|
--- a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,62 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AD>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <6>;
|
|
- gpio-ranges = <&pinctrl 6 86 6>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <10>;
|
|
- gpio-ranges = <&pinctrl 6 102 10>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <2>;
|
|
- gpio-ranges = <&pinctrl 0 112 2>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xa.dtsi b/arch/arm/boot/dts/stm32mp15xa.dtsi
|
|
new file mode 100644
|
|
index 000000000..5ed7e594f
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xa.dtsi
|
|
@@ -0,0 +1,13 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ opp-650000000 {
|
|
+ opp-hz = /bits/ 64 <650000000>;
|
|
+ opp-microvolt = <1200000>;
|
|
+ opp-supported-hw = <0x1>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
|
|
new file mode 100644
|
|
index 000000000..adc1568a7
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
|
|
@@ -0,0 +1,20 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xa.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ cryp1: cryp@54001000 {
|
|
+ compatible = "st,stm32mp1-cryp";
|
|
+ reg = <0x54001000 0x400>;
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_CRYP1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xd.dtsi b/arch/arm/boot/dts/stm32mp15xd.dtsi
|
|
new file mode 100644
|
|
index 000000000..faa039ea2
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xd.dtsi
|
|
@@ -0,0 +1,42 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ opp-800000000 {
|
|
+ opp-hz = /bits/ 64 <800000000>;
|
|
+ opp-microvolt = <1350000>;
|
|
+ opp-supported-hw = <0x2>;
|
|
+ };
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <1200000>;
|
|
+ opp-supported-hw = <0x2>;
|
|
+ opp-suspend;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu_thermal {
|
|
+ trips {
|
|
+ cpu-crit {
|
|
+ temperature = <105000>;
|
|
+ hysteresis = <0>;
|
|
+ type = "critical";
|
|
+ };
|
|
+
|
|
+ cpu_alert: cpu-alert {
|
|
+ temperature = <950000>;
|
|
+ hysteresis = <10000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device = <&cpu0 1 1>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xf.dtsi b/arch/arm/boot/dts/stm32mp15xf.dtsi
|
|
new file mode 100644
|
|
index 000000000..77f50b9bd
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xf.dtsi
|
|
@@ -0,0 +1,20 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xd.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ cryp1: cryp@54001000 {
|
|
+ compatible = "st,stm32mp1-cryp";
|
|
+ reg = <0x54001000 0x400>;
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_CRYP1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
|
|
new file mode 100644
|
|
index 000000000..35169385f
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
|
|
@@ -0,0 +1,768 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+
|
|
+/ {
|
|
+ memory@c0000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0xc0000000 0x20000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ mcuram2: mcuram2@10000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring0: vdev0vring0@10040000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10040000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring1: vdev0vring1@10041000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10041000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0buffer: vdev0buffer@10042000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10042000 0x4000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ mcuram: mcuram@30000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x30000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ retram: retram@38000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x38000000 0x10000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ compatible = "gpio-leds";
|
|
+ blue {
|
|
+ label = "heartbeat";
|
|
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "heartbeat";
|
|
+ default-state = "off";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ compatible = "audio-graph-card";
|
|
+ label = "STM32MP1-DK";
|
|
+ routing =
|
|
+ "Playback" , "MCLK",
|
|
+ "Capture" , "MCLK",
|
|
+ "MICL" , "Mic Bias";
|
|
+ dais = <&sai2a_port &sai2b_port &i2s2_port>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ usb_phy_tuning: usb-phy-tuning {
|
|
+ st,hs-dc-level = <2>;
|
|
+ st,fs-rftime-tuning;
|
|
+ st,hs-rftime-reduction;
|
|
+ st,hs-current-trim = <15>;
|
|
+ st,hs-impedance-trim = <1>;
|
|
+ st,squelch-level = <3>;
|
|
+ st,hs-rx-offset = <2>;
|
|
+ st,no-lsfs-sc;
|
|
+ };
|
|
+
|
|
+ vin: vin {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vin";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdda-supply = <&vdd>;
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "disabled";
|
|
+ adc1: adc@0 {
|
|
+ /*
|
|
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
|
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
|
+ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
|
+ * Use arbitrary margin here (e.g. 5us).
|
|
+ */
|
|
+ st,min-sample-time-nsecs = <5000>;
|
|
+ /* AIN connector, USB Type-C CC1 & CC2 */
|
|
+ st,adc-channels = <0 1 6 13 18 19>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ adc2: adc@100 {
|
|
+ /* AIN connector, USB Type-C CC1 & CC2 */
|
|
+ st,adc-channels = <0 1 2 6 18 19>;
|
|
+ st,min-sample-time-nsecs = <5000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&cec_pins_b>;
|
|
+ pinctrl-1 = <&cec_pins_sleep_b>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&cpu0{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&crc1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dma1 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dts {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+ðernet0 {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ phy-mode = "rgmii-id";
|
|
+ max-speed = <1000>;
|
|
+ phy-handle = <&phy0>;
|
|
+
|
|
+ mdio0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ phy0: ethernet-phy@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c1_pins_a>;
|
|
+ pinctrl-1 = <&i2c1_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <100>;
|
|
+ i2c-scl-falling-time-ns = <7>;
|
|
+ status = "okay";
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ hdmi-transmitter@39 {
|
|
+ compatible = "sil,sii9022";
|
|
+ reg = <0x39>;
|
|
+ iovcc-supply = <&v3v3_hdmi>;
|
|
+ cvcc12-supply = <&v1v2_hdmi>;
|
|
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
|
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-parent = <&gpiog>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ sii9022_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@3 {
|
|
+ reg = <3>;
|
|
+ sii9022_tx_endpoint: endpoint {
|
|
+ remote-endpoint = <&i2s2_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cs42l51: cs42l51@4a {
|
|
+ compatible = "cirrus,cs42l51";
|
|
+ reg = <0x4a>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ VL-supply = <&v3v3>;
|
|
+ VD-supply = <&v1v8_audio>;
|
|
+ VA-supply = <&v1v8_audio>;
|
|
+ VAHP-supply = <&v1v8_audio>;
|
|
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
|
+ clocks = <&sai2a>;
|
|
+ clock-names = "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ cs42l51_port: port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cs42l51_tx_endpoint: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&sai2a_endpoint>;
|
|
+ frame-master;
|
|
+ bitclock-master;
|
|
+ };
|
|
+
|
|
+ cs42l51_rx_endpoint: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&sai2b_endpoint>;
|
|
+ frame-master;
|
|
+ bitclock-master;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ pinctrl-1 = <&i2c4_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ stusb1600@28 {
|
|
+ compatible = "st,stusb1600";
|
|
+ reg = <0x28>;
|
|
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-parent = <&gpioi>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&stusb1600_pins_a>;
|
|
+ status = "okay";
|
|
+ vdd-supply = <&vin>;
|
|
+
|
|
+ connector {
|
|
+ compatible = "usb-c-connector";
|
|
+ label = "USB-C";
|
|
+ power-role = "dual";
|
|
+ power-opmode = "default";
|
|
+
|
|
+ port {
|
|
+ con_usbotg_hs_ep: endpoint {
|
|
+ remote-endpoint = <&usbotg_hs_ep>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic: stpmic@33 {
|
|
+ compatible = "st,stpmic1";
|
|
+ reg = <0x33>;
|
|
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ status = "okay";
|
|
+
|
|
+ regulators {
|
|
+ compatible = "st,stpmic1-regulators";
|
|
+ buck1-supply = <&vin>;
|
|
+ buck2-supply = <&vin>;
|
|
+ buck3-supply = <&vin>;
|
|
+ buck4-supply = <&vin>;
|
|
+ ldo1-supply = <&v3v3>;
|
|
+ ldo2-supply = <&vin>;
|
|
+ ldo3-supply = <&vdd_ddr>;
|
|
+ ldo4-supply = <&vin>;
|
|
+ ldo5-supply = <&vin>;
|
|
+ ldo6-supply = <&v3v3>;
|
|
+ vref_ddr-supply = <&vin>;
|
|
+ boost-supply = <&vin>;
|
|
+ pwr_sw1-supply = <&bst_out>;
|
|
+ pwr_sw2-supply = <&bst_out>;
|
|
+
|
|
+ vddcore: buck1 {
|
|
+ regulator-name = "vddcore";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_ddr: buck2 {
|
|
+ regulator-name = "vdd_ddr";
|
|
+ regulator-min-microvolt = <1350000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd: buck3 {
|
|
+ regulator-name = "vdd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ st,mask-reset;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ v3v3: buck4 {
|
|
+ regulator-name = "v3v3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ regulator-initial-mode = <0>;
|
|
+ };
|
|
+
|
|
+ v1v8_audio: ldo1 {
|
|
+ regulator-name = "v1v8_audio";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO1 0>;
|
|
+ };
|
|
+
|
|
+ v3v3_hdmi: ldo2 {
|
|
+ regulator-name = "v3v3_hdmi";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO2 0>;
|
|
+ };
|
|
+
|
|
+ vtt_ddr: ldo3 {
|
|
+ regulator-name = "vtt_ddr";
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_usb: ldo4 {
|
|
+ regulator-name = "vdd_usb";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ interrupts = <IT_CURLIM_LDO4 0>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ vdda: ldo5 {
|
|
+ regulator-name = "vdda";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO5 0>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+
|
|
+ v1v2_hdmi: ldo6 {
|
|
+ regulator-name = "v1v2_hdmi";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO6 0>;
|
|
+ };
|
|
+
|
|
+ vref_ddr: vref_ddr {
|
|
+ regulator-name = "vref_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ bst_out: boost {
|
|
+ regulator-name = "bst_out";
|
|
+ interrupts = <IT_OCP_BOOST 0>;
|
|
+ };
|
|
+
|
|
+ vbus_otg: pwr_sw1 {
|
|
+ regulator-name = "vbus_otg";
|
|
+ interrupts = <IT_OCP_OTG 0>;
|
|
+ };
|
|
+
|
|
+ vbus_sw: pwr_sw2 {
|
|
+ regulator-name = "vbus_sw";
|
|
+ interrupts = <IT_OCP_SWOUT 0>;
|
|
+ regulator-active-discharge = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ onkey {
|
|
+ compatible = "st,stpmic1-onkey";
|
|
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
+ interrupt-names = "onkey-falling", "onkey-rising";
|
|
+ power-off-time-sec = <10>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ watchdog {
|
|
+ compatible = "st,stpmic1-wdt";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c5_pins_a>;
|
|
+ pinctrl-1 = <&i2c5_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&i2s2 {
|
|
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2s2_pins_a>;
|
|
+ pinctrl-1 = <&i2s2_pins_sleep_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ i2s2_port: port {
|
|
+ i2s2_endpoint: endpoint {
|
|
+ remote-endpoint = <&sii9022_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ipcc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ timeout-sec = <32>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <<dc_pins_a>;
|
|
+ pinctrl-1 = <<dc_pins_sleep_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep0_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&sii9022_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
+ <&vdev0vring1>, <&vdev0buffer>;
|
|
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
+ mbox-names = "vq0", "vq1", "shutdown";
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <68 1>;
|
|
+ wakeup-source;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
|
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a: audio-controller@4400b004 {
|
|
+ #clock-cells = <0>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a_port: port {
|
|
+ sai2a_endpoint: endpoint {
|
|
+ remote-endpoint = <&cs42l51_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ dai-tdm-slot-num = <2>;
|
|
+ dai-tdm-slot-width = <32>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b: audio-controller@4400b024 {
|
|
+ dma-names = "rx";
|
|
+ st,sync = <&sai2a 2>;
|
|
+ clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
+ clock-names = "sai_ck", "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2b_port: port {
|
|
+ sai2b_endpoint: endpoint {
|
|
+ remote-endpoint = <&cs42l51_rx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ dai-tdm-slot-num = <2>;
|
|
+ dai-tdm-slot-width = <32>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
+ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
+ disable-wp;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc3 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
+ broken-cd;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spi4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi4_pins_a>;
|
|
+ pinctrl-1 = <&spi4_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spi5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi5_pins_a>;
|
|
+ pinctrl-1 = <&spi5_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sram {
|
|
+ dma_pool: dma_pool@0 {
|
|
+ reg = <0x50000 0x10000>;
|
|
+ pool;
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm1_pins_a>;
|
|
+ pinctrl-1 = <&pwm1_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@0 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers3 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm3_pins_a>;
|
|
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@2 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers4 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
|
|
+ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@3 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers5 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm5_pins_a>;
|
|
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@4 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ timer@5 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm12_pins_a>;
|
|
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@11 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ pinctrl-1 = <&uart4_sleep_pins_a>;
|
|
+ pinctrl-2 = <&uart4_idle_pins_a>;
|
|
+ pinctrl-3 = <&uart4_pins_a>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart7 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart7_pins_b>;
|
|
+ pinctrl-1 = <&uart7_sleep_pins_b>;
|
|
+ pinctrl-2 = <&uart7_idle_pins_b>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usart3 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart3_pins_b>;
|
|
+ pinctrl-1 = <&usart3_sleep_pins_b>;
|
|
+ pinctrl-2 = <&usart3_idle_pins_b>;
|
|
+ uart-has-rtscts;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usbh_ehci {
|
|
+ phys = <&usbphyc_port0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ phys = <&usbphyc_port1 0>;
|
|
+ phy-names = "usb2-phy";
|
|
+ usb-role-switch;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ usbotg_hs_ep: endpoint {
|
|
+ remote-endpoint = <&con_usbotg_hs_ep>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&usbphyc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&vrefbuf {
|
|
+ regulator-min-microvolt = <2500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ vdda-supply = <&vdd>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xx-edx.dtsi b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi
|
|
new file mode 100644
|
|
index 000000000..7ed6b14d7
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi
|
|
@@ -0,0 +1,408 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+
|
|
+/ {
|
|
+ memory@c0000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0xC0000000 0x40000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ mcuram2: mcuram2@10000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring0: vdev0vring0@10040000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10040000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring1: vdev0vring1@10041000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10041000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0buffer: vdev0buffer@10042000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10042000 0x4000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ mcuram: mcuram@30000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x30000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ retram: retram@38000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x38000000 0x10000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ compatible = "gpio-leds";
|
|
+ blue {
|
|
+ label = "heartbeat";
|
|
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "heartbeat";
|
|
+ default-state = "off";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sd_switch: regulator-sd_switch {
|
|
+ compatible = "regulator-gpio";
|
|
+ regulator-name = "sd_switch";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ regulator-type = "voltage";
|
|
+ regulator-always-on;
|
|
+
|
|
+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
|
|
+ gpios-states = <0>;
|
|
+ states = <1800000 0x1 2900000 0x0>;
|
|
+ };
|
|
+
|
|
+ vin: vin {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vin";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
|
|
+ pinctrl-0 = <&adc1_in6_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdda-supply = <&vdda>;
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "disabled";
|
|
+ adc1: adc@0 {
|
|
+ st,adc-channels = <0 1 6>;
|
|
+ /* 16.5 ck_cycles sampling time */
|
|
+ st,min-sample-time-nsecs = <400>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&crc1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "disabled";
|
|
+ dac1: dac@1 {
|
|
+ status = "okay";
|
|
+ };
|
|
+ dac2: dac@2 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&dma1 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dts {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ pinctrl-1 = <&i2c4_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ pmic: stpmic@33 {
|
|
+ compatible = "st,stpmic1";
|
|
+ reg = <0x33>;
|
|
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ status = "okay";
|
|
+
|
|
+ regulators {
|
|
+ compatible = "st,stpmic1-regulators";
|
|
+ buck1-supply = <&vin>;
|
|
+ buck2-supply = <&vin>;
|
|
+ buck3-supply = <&vin>;
|
|
+ buck4-supply = <&vin>;
|
|
+ ldo1-supply = <&v3v3>;
|
|
+ ldo2-supply = <&v3v3>;
|
|
+ ldo3-supply = <&vdd_ddr>;
|
|
+ ldo4-supply = <&vin>;
|
|
+ ldo5-supply = <&v3v3>;
|
|
+ ldo6-supply = <&v3v3>;
|
|
+ vref_ddr-supply = <&vin>;
|
|
+ boost-supply = <&vin>;
|
|
+ pwr_sw1-supply = <&bst_out>;
|
|
+ pwr_sw2-supply = <&bst_out>;
|
|
+
|
|
+ vddcore: buck1 {
|
|
+ regulator-name = "vddcore";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_ddr: buck2 {
|
|
+ regulator-name = "vdd_ddr";
|
|
+ regulator-min-microvolt = <1350000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd: buck3 {
|
|
+ regulator-name = "vdd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ st,mask-reset;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ v3v3: buck4 {
|
|
+ regulator-name = "v3v3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ regulator-initial-mode = <0>;
|
|
+ };
|
|
+
|
|
+ vdda: ldo1 {
|
|
+ regulator-name = "vdda";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO1 0>;
|
|
+ };
|
|
+
|
|
+ v2v8: ldo2 {
|
|
+ regulator-name = "v2v8";
|
|
+ regulator-min-microvolt = <2800000>;
|
|
+ regulator-max-microvolt = <2800000>;
|
|
+ interrupts = <IT_CURLIM_LDO2 0>;
|
|
+ };
|
|
+
|
|
+ vtt_ddr: ldo3 {
|
|
+ regulator-name = "vtt_ddr";
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_usb: ldo4 {
|
|
+ regulator-name = "vdd_usb";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ interrupts = <IT_CURLIM_LDO4 0>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ vdd_sd: ldo5 {
|
|
+ regulator-name = "vdd_sd";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO5 0>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+
|
|
+ v1v8: ldo6 {
|
|
+ regulator-name = "v1v8";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ interrupts = <IT_CURLIM_LDO6 0>;
|
|
+ };
|
|
+
|
|
+ vref_ddr: vref_ddr {
|
|
+ regulator-name = "vref_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ bst_out: boost {
|
|
+ regulator-name = "bst_out";
|
|
+ interrupts = <IT_OCP_BOOST 0>;
|
|
+ };
|
|
+
|
|
+ vbus_otg: pwr_sw1 {
|
|
+ regulator-name = "vbus_otg";
|
|
+ interrupts = <IT_OCP_OTG 0>;
|
|
+ };
|
|
+
|
|
+ vbus_sw: pwr_sw2 {
|
|
+ regulator-name = "vbus_sw";
|
|
+ interrupts = <IT_OCP_SWOUT 0>;
|
|
+ regulator-active-discharge = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ onkey {
|
|
+ compatible = "st,stpmic1-onkey";
|
|
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
+ interrupt-names = "onkey-falling", "onkey-rising";
|
|
+ power-off-time-sec = <10>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ watchdog {
|
|
+ compatible = "st,stpmic1-wdt";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ipcc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ timeout-sec = <32>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
+ <&vdev0vring1>, <&vdev0buffer>;
|
|
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
+ mbox-names = "vq0", "vq1", "shutdown";
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <68 1>;
|
|
+ wakeup-source;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
|
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
+ disable-wp;
|
|
+ st,sig-dir;
|
|
+ st,neg-edge;
|
|
+ st,use-ckin;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&vdd_sd>;
|
|
+ vqmmc-supply = <&sd_switch>;
|
|
+ sd-uhs-sdr12;
|
|
+ sd-uhs-sdr25;
|
|
+ sd-uhs-sdr50;
|
|
+ sd-uhs-ddr50;
|
|
+ sd-uhs-sdr104;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ no-sd;
|
|
+ no-sdio;
|
|
+ st,neg-edge;
|
|
+ bus-width = <8>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ vqmmc-supply = <&vdd>;
|
|
+ mmc-ddr-3_3v;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sram {
|
|
+ dma_pool: dma_pool@0 {
|
|
+ reg = <0x50000 0x10000>;
|
|
+ pool;
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ timer@5 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ pinctrl-1 = <&uart4_sleep_pins_a>;
|
|
+ pinctrl-2 = <&uart4_idle_pins_a>;
|
|
+ pinctrl-3 = <&uart4_pins_a>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ vbus-supply = <&vbus_otg>;
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xx-evx.dtsi b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi
|
|
new file mode 100644
|
|
index 000000000..07cb93db9
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi
|
|
@@ -0,0 +1,680 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ clocks {
|
|
+ clk_ext_camera: clk-ext-camera {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ joystick {
|
|
+ compatible = "gpio-keys";
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-0 = <&joystick_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ button-0 {
|
|
+ label = "JoySel";
|
|
+ linux,code = <KEY_ENTER>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-1 {
|
|
+ label = "JoyDown";
|
|
+ linux,code = <KEY_DOWN>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-2 {
|
|
+ label = "JoyLeft";
|
|
+ linux,code = <KEY_LEFT>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-3 {
|
|
+ label = "JoyRight";
|
|
+ linux,code = <KEY_RIGHT>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-4 {
|
|
+ label = "JoyUp";
|
|
+ linux,code = <KEY_UP>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_backlight: panel-backlight {
|
|
+ compatible = "gpio-backlight";
|
|
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
|
+ default-on;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ status = "okay";
|
|
+
|
|
+ spdif_out_port: port {
|
|
+ spdif_out_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai4a_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_in: spdif-in {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dir";
|
|
+ status = "okay";
|
|
+
|
|
+ spdif_in_port: port {
|
|
+ spdif_in_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdifrx_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ compatible = "audio-graph-card";
|
|
+ label = "STM32MP1-EV";
|
|
+ routing =
|
|
+ "AIF1CLK" , "MCLK1",
|
|
+ "AIF2CLK" , "MCLK1",
|
|
+ "IN1LN" , "MICBIAS2",
|
|
+ "DMIC2DAT" , "MICBIAS1",
|
|
+ "DMIC1DAT" , "MICBIAS1";
|
|
+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port
|
|
+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ dmic0: dmic-0 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic0";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic0_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic1: dmic-1 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic1";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic1_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic2: dmic-2 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic2";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic2_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint2>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic3: dmic-3 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic3";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic3_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint3>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb_phy_tuning: usb-phy-tuning {
|
|
+ st,hs-dc-level = <2>;
|
|
+ st,fs-rftime-tuning;
|
|
+ st,hs-rftime-reduction;
|
|
+ st,hs-current-trim = <15>;
|
|
+ st,hs-impedance-trim = <1>;
|
|
+ st,squelch-level = <3>;
|
|
+ st,hs-rx-offset = <2>;
|
|
+ st,no-lsfs-sc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&cec_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dcmi {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&dcmi_pins_a>;
|
|
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
|
|
+
|
|
+ port {
|
|
+ dcmi_0: endpoint {
|
|
+ remote-endpoint = <&ov5640_0>;
|
|
+ bus-width = <8>;
|
|
+ hsync-active = <0>;
|
|
+ vsync-active = <0>;
|
|
+ pclk-sample = <1>;
|
|
+ pclk-max-frequency = <77000000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&dfsdm {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&dfsdm_clkout_pins_a
|
|
+ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>;
|
|
+ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a
|
|
+ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>;
|
|
+ spi-max-frequency = <2048000>;
|
|
+
|
|
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
|
|
+ clock-names = "dfsdm", "audio";
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm0: filter@0 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <3>;
|
|
+ st,adc-channel-names = "dmic_u1";
|
|
+ st,adc-channel-types = "SPI_R";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm0: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm0 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm0_port: port {
|
|
+ dfsdm_endpoint0: endpoint {
|
|
+ remote-endpoint = <&dmic0_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm1: filter@1 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <1>;
|
|
+ st,adc-channel-names = "dmic_u2";
|
|
+ st,adc-channel-types = "SPI_F";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm1: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm1 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm1_port: port {
|
|
+ dfsdm_endpoint1: endpoint {
|
|
+ remote-endpoint = <&dmic1_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm2: filter@2 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <3>;
|
|
+ st,adc-channel-names = "dmic_u3";
|
|
+ st,adc-channel-types = "SPI_F";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm2: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm2 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm2_port: port {
|
|
+ dfsdm_endpoint2: endpoint {
|
|
+ remote-endpoint = <&dmic2_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm3: filter@3 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <1>;
|
|
+ st,adc-channel-names = "dmic_u4";
|
|
+ st,adc-channel-types = "SPI_R";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm3: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm3 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm3_port: port {
|
|
+ dfsdm_endpoint3: endpoint {
|
|
+ remote-endpoint = <&dmic3_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+ðernet0 {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ phy-mode = "rgmii-id";
|
|
+ max-speed = <1000>;
|
|
+ phy-handle = <&phy0>;
|
|
+
|
|
+ mdio0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ phy0: ethernet-phy@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&fmc {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&fmc_pins_a>;
|
|
+ pinctrl-1 = <&fmc_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ nand-on-flash-bbt;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&hdp {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
|
|
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
|
|
+ status = "disabled";
|
|
+
|
|
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
|
|
+ STM32_HDP(6, HDP6_GPOVAL_6) |
|
|
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c2_pins_a>;
|
|
+ pinctrl-1 = <&i2c2_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ status = "okay";
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ wm8994: wm8994@1b {
|
|
+ compatible = "wlf,wm8994";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x1b>;
|
|
+ status = "okay";
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+
|
|
+ DBVDD-supply = <&vdd>;
|
|
+ SPKVDD1-supply = <&vdd>;
|
|
+ SPKVDD2-supply = <&vdd>;
|
|
+ AVDD2-supply = <&v1v8>;
|
|
+ CPVDD-supply = <&v1v8>;
|
|
+
|
|
+ wlf,ldoena-always-driven;
|
|
+
|
|
+ clocks = <&sai2a>;
|
|
+ clock-names = "MCLK1";
|
|
+
|
|
+ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ wm8994_tx_port: port@0 {
|
|
+ reg = <0>;
|
|
+ wm8994_tx_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai2a_endpoint>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wm8994_rx_port: port@1 {
|
|
+ reg = <1>;
|
|
+ wm8994_rx_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai2b_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ov5640: camera@3c {
|
|
+ compatible = "ovti,ov5640";
|
|
+ reg = <0x3c>;
|
|
+ clocks = <&clk_ext_camera>;
|
|
+ clock-names = "xclk";
|
|
+ DOVDD-supply = <&v2v8>;
|
|
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
|
|
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
|
|
+ rotation = <180>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ ov5640_0: endpoint {
|
|
+ remote-endpoint = <&dcmi_0>;
|
|
+ bus-width = <8>;
|
|
+ data-shift = <2>; /* lines 9:2 are used */
|
|
+ hsync-active = <0>;
|
|
+ vsync-active = <0>;
|
|
+ pclk-sample = <1>;
|
|
+ pclk-max-frequency = <77000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ stmfx: stmfx@42 {
|
|
+ compatible = "st,stmfx-0300";
|
|
+ reg = <0x42>;
|
|
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&gpioi>;
|
|
+ vdd-supply = <&v3v3>;
|
|
+
|
|
+ stmfx_pinctrl: stmfx-pin-controller {
|
|
+ compatible = "st,stmfx-0300-pinctrl";
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
|
+
|
|
+ goodix_pins: goodix {
|
|
+ pins = "gpio14";
|
|
+ bias-pull-down;
|
|
+ };
|
|
+
|
|
+ joystick_pins: joystick {
|
|
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
|
+ bias-pull-down;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pmic: stpmic@33 {
|
|
+ regulators {
|
|
+ v1v8: ldo6 {
|
|
+ regulator-enable-ramp-delay = <300000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c5_pins_a>;
|
|
+ pinctrl-1 = <&i2c5_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep0_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dsi_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
|
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ flash0: mx66l51235l@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+
|
|
+ flash1: mx66l51235l@1 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <1>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>;
|
|
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a: audio-controller@4400b004 {
|
|
+ #clock-cells = <0>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a_port: port {
|
|
+ sai2a_endpoint: endpoint {
|
|
+ remote-endpoint = <&wm8994_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b: audio-controller@4400b024 {
|
|
+ dma-names = "rx";
|
|
+ clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
+ clock-names = "sai_ck", "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2b_port: port {
|
|
+ sai2b_endpoint: endpoint {
|
|
+ remote-endpoint = <&wm8994_rx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sai4 {
|
|
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ status = "okay";
|
|
+
|
|
+ sai4a: audio-controller@50027004 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai4a_pins_a>;
|
|
+ pinctrl-1 = <&sai4a_sleep_pins_a>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ st,iec60958;
|
|
+ status = "okay";
|
|
+
|
|
+ sai4a_port: port {
|
|
+ sai4a_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdif_out_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc3 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ broken-cd;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spdifrx {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spdifrx_pins_a>;
|
|
+ pinctrl-1 = <&spdifrx_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ spdifrx_port: port {
|
|
+ spdifrx_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdif_in_endpoint>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi1_pins_a>;
|
|
+ pinctrl-1 = <&spi1_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm2_pins_a>;
|
|
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@1 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers8 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm8_pins_a>;
|
|
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@7 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm12_pins_a>;
|
|
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@11 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&usart3 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart3_pins_a>;
|
|
+ pinctrl-1 = <&usart3_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart3_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usbh_ehci {
|
|
+ phys = <&usbphyc_port0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ pinctrl-0 = <&usbotg_hs_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ phys = <&usbphyc_port1 0>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..64e566bf8
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
|
|
@@ -0,0 +1,85 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AA>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 80 16>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 96 16>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 112 16>;
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 128 16>;
|
|
+ };
|
|
+
|
|
+ gpioj: gpio@5000b000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 144 16>;
|
|
+ };
|
|
+
|
|
+ gpiok: gpio@5000c000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl 0 160 8>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ st,package = <STM32MP_PKG_AA>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..d29af8986
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
|
|
@@ -0,0 +1,57 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AB>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <6>;
|
|
+ gpio-ranges = <&pinctrl 6 86 6>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <10>;
|
|
+ gpio-ranges = <&pinctrl 6 102 10>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 112 2>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..5d8199fd1
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
|
|
@@ -0,0 +1,73 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AC>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 80 16>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 96 16>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 112 16>;
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ status = "okay";
|
|
+ ngpios = <12>;
|
|
+ gpio-ranges = <&pinctrl 0 128 12>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ st,package = <STM32MP_PKG_AC>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 000000000..023f5404c
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
|
|
@@ -0,0 +1,57 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AD>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <6>;
|
|
+ gpio-ranges = <&pinctrl 6 86 6>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <10>;
|
|
+ gpio-ranges = <&pinctrl 6 102 10>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 112 2>;
|
|
+ };
|
|
+};
|
|
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
|
|
index 4cdaf1358..ec7b1a932 100644
|
|
--- a/include/dt-bindings/clock/stm32mp1-clks.h
|
|
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
|
|
@@ -179,6 +179,12 @@
|
|
#define DAC12_K 168
|
|
#define ETHPTP_K 169
|
|
|
|
+#define PCLK1 170
|
|
+#define PCLK2 171
|
|
+#define PCLK3 172
|
|
+#define PCLK4 173
|
|
+#define PCLK5 174
|
|
+
|
|
/* PLL */
|
|
#define PLL1 176
|
|
#define PLL2 177
|
|
@@ -248,4 +254,31 @@
|
|
|
|
#define STM32MP1_LAST_CLK 232
|
|
|
|
+/* SCMI clock identifiers */
|
|
+#define CK_SCMI0_HSE 0
|
|
+#define CK_SCMI0_HSI 1
|
|
+#define CK_SCMI0_CSI 2
|
|
+#define CK_SCMI0_LSE 3
|
|
+#define CK_SCMI0_LSI 4
|
|
+#define CK_SCMI0_PLL2_Q 5
|
|
+#define CK_SCMI0_PLL2_R 6
|
|
+#define CK_SCMI0_MPU 7
|
|
+#define CK_SCMI0_AXI 8
|
|
+#define CK_SCMI0_BSEC 9
|
|
+#define CK_SCMI0_CRYP1 10
|
|
+#define CK_SCMI0_GPIOZ 11
|
|
+#define CK_SCMI0_HASH1 12
|
|
+#define CK_SCMI0_I2C4 13
|
|
+#define CK_SCMI0_I2C6 14
|
|
+#define CK_SCMI0_IWDG1 15
|
|
+#define CK_SCMI0_RNG1 16
|
|
+#define CK_SCMI0_RTC 17
|
|
+#define CK_SCMI0_RTCAPB 18
|
|
+#define CK_SCMI0_SPI6 19
|
|
+#define CK_SCMI0_USART1 20
|
|
+
|
|
+#define CK_SCMI1_PLL3_Q 0
|
|
+#define CK_SCMI1_PLL3_R 1
|
|
+#define CK_SCMI1_MCU 2
|
|
+
|
|
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
|
|
diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h
|
|
index 309e8c79f..36448a561 100644
|
|
--- a/include/dt-bindings/mfd/stm32f4-rcc.h
|
|
+++ b/include/dt-bindings/mfd/stm32f4-rcc.h
|
|
@@ -34,7 +34,6 @@
|
|
#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
|
|
#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
|
|
|
|
-
|
|
/* AHB2 */
|
|
#define STM32F4_RCC_AHB2_DCMI 0
|
|
#define STM32F4_RCC_AHB2_CRYP 4
|
|
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
|
|
index e6fb8ada3..370a25a93 100644
|
|
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
|
|
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
|
|
@@ -26,6 +26,7 @@
|
|
#define AF14 0xf
|
|
#define AF15 0x10
|
|
#define ANALOG 0x11
|
|
+#define RSVD 0x12
|
|
|
|
/* define Pins number*/
|
|
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
|
|
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
|
|
index f0c3aaef6..bc71924fa 100644
|
|
--- a/include/dt-bindings/reset/stm32mp1-resets.h
|
|
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
|
|
@@ -105,4 +105,17 @@
|
|
#define GPIOJ_R 19785
|
|
#define GPIOK_R 19786
|
|
|
|
+/* SCMI reset domain identifiers */
|
|
+#define RST_SCMI0_SPI6 0
|
|
+#define RST_SCMI0_I2C4 1
|
|
+#define RST_SCMI0_I2C6 2
|
|
+#define RST_SCMI0_USART1 3
|
|
+#define RST_SCMI0_STGEN 4
|
|
+#define RST_SCMI0_GPIOZ 5
|
|
+#define RST_SCMI0_CRYP1 6
|
|
+#define RST_SCMI0_HASH1 7
|
|
+#define RST_SCMI0_RNG1 8
|
|
+#define RST_SCMI0_MDMA 9
|
|
+#define RST_SCMI0_MCU 10
|
|
+
|
|
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
|
|
diff --git a/include/dt-bindings/rtc/rtc-stm32.h b/include/dt-bindings/rtc/rtc-stm32.h
|
|
new file mode 100644
|
|
index 000000000..4373c4dea
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/rtc/rtc-stm32.h
|
|
@@ -0,0 +1,13 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/*
|
|
+ * This header provides constants for STM32_RTC bindings.
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_RTC_RTC_STM32_H
|
|
+#define _DT_BINDINGS_RTC_RTC_STM32_H
|
|
+
|
|
+#define RTC_OUT1 0
|
|
+#define RTC_OUT2 1
|
|
+#define RTC_OUT2_RMP 2
|
|
+
|
|
+#endif
|
|
diff --git a/include/dt-bindings/soc/stm32-hdp.h b/include/dt-bindings/soc/stm32-hdp.h
|
|
new file mode 100644
|
|
index 000000000..d98665327
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/soc/stm32-hdp.h
|
|
@@ -0,0 +1,108 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
|
+ * Author: Roullier Christophe <christophe.roullier@st.com>
|
|
+ * for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_STM32_HDP_H
|
|
+#define _DT_BINDINGS_STM32_HDP_H
|
|
+
|
|
+#define STM32_HDP(port, value) ((value) << ((port) * 4))
|
|
+
|
|
+/* define HDP Pins number*/
|
|
+#define HDP0_PWR_PWRWAKE_SYS 0
|
|
+#define HDP0_CM4_SLEEPDEEP 1
|
|
+#define HDP0_PWR_STDBY_WKUP 2
|
|
+#define HDP0_PWR_ENCOMP_VDDCORE 3
|
|
+#define HDP0_BSEC_OUT_SEC_NIDEN 4
|
|
+#define HDP0_RCC_CM4_SLEEPDEEP 6
|
|
+#define HDP0_GPU_DBG7 7
|
|
+#define HDP0_DDRCTRL_LP_REQ 8
|
|
+#define HDP0_PWR_DDR_RET_ENABLE_N 9
|
|
+#define HDP0_GPOVAL_0 15
|
|
+
|
|
+#define HDP1_PWR_PWRWAKE_MCU 0
|
|
+#define HDP1_CM4_HALTED 1
|
|
+#define HDP1_CA7_NAXIERRIRQ 2
|
|
+#define HDP1_PWR_OKIN_MR 3
|
|
+#define HDP1_BSEC_OUT_SEC_DBGEN 4
|
|
+#define HDP1_EXTI_SYS_WAKEUP 5
|
|
+#define HDP1_RCC_PWRDS_MPU 6
|
|
+#define HDP1_GPU_DBG6 7
|
|
+#define HDP1_DDRCTRL_DFI_CTRLUPD_REQ 8
|
|
+#define HDP1_DDRCTRL_CACTIVE_DDRC_ASR 9
|
|
+#define HDP1_GPOVAL_1 15
|
|
+
|
|
+#define HDP2_PWR_PWRWAKE_MPU 0
|
|
+#define HDP2_CM4_RXEV 1
|
|
+#define HDP2_CA7_NPMUIRQ1 2
|
|
+#define HDP2_CA7_NFIQOUT1 3
|
|
+#define HDP2_BSEC_IN_RSTCORE_N 4
|
|
+#define HDP2_EXTI_C2_WAKEUP 5
|
|
+#define HDP2_RCC_PWRDS_MCU 6
|
|
+#define HDP2_GPU_DBG5 7
|
|
+#define HDP2_DDRCTRL_DFI_INIT_COMPLETE 8
|
|
+#define HDP2_DDRCTRL_PERF_OP_IS_REFRESH 9
|
|
+#define HDP2_DDRCTRL_GSKP_DFI_LP_REQ 10
|
|
+#define HDP2_GPOVAL_2 15
|
|
+
|
|
+#define HDP3_PWR_SEL_VTH_VDD_CORE 0
|
|
+#define HDP3_CM4_TXEV 1
|
|
+#define HDP3_CA7_NPMUIRQ0 2
|
|
+#define HDP3_CA7_NFIQOUT0 3
|
|
+#define HDP3_BSEC_OUT_SEC_DFTLOCK 4
|
|
+#define HDP3_EXTI_C1_WAKEUP 5
|
|
+#define HDP3_RCC_PWRDS_SYS 6
|
|
+#define HDP3_GPU_DBG4 7
|
|
+#define HDP3_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE0 8
|
|
+#define HDP3_DDRCTRL_CACTIVE_1 9
|
|
+#define HDP3_GPOVAL_3 15
|
|
+
|
|
+#define HDP4_PWR_PDDS 0
|
|
+#define HDP4_CM4_SLEEPING 1
|
|
+#define HDP4_CA7_NRESET1 2
|
|
+#define HDP4_CA7_NIRQOUT1 3
|
|
+#define HDP4_BSEC_OUT_SEC_DFTEN 4
|
|
+#define HDP4_BSEC_OUT_SEC_DBGSWENABLE 5
|
|
+#define HDP4_ETH_OUT_PMT_INTR_O 6
|
|
+#define HDP4_GPU_DBG3 7
|
|
+#define HDP4_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE1 8
|
|
+#define HDP4_DDRCTRL_CACTIVE_0 9
|
|
+#define HDP4_GPOVAL_4 15
|
|
+
|
|
+#define HDP5_CA7_STANDBYWFIL2 0
|
|
+#define HDP5_PWR_VTH_VDDCORE_ACK 1
|
|
+#define HDP5_CA7_NRESET0 2
|
|
+#define HDP5_CA7_NIRQOUT0 3
|
|
+#define HDP5_BSEC_IN_PWROK 4
|
|
+#define HDP5_BSEC_OUT_SEC_DEVICEEN 5
|
|
+#define HDP5_ETH_OUT_LPI_INTR_O 6
|
|
+#define HDP5_GPU_DBG2 7
|
|
+#define HDP5_DDRCTRL_CACTIVE_DDRC 8
|
|
+#define HDP5_DDRCTRL_WR_CREDIT_CNT 9
|
|
+#define HDP5_GPOVAL_5 15
|
|
+
|
|
+#define HDP6_CA7_STANDBYWFI1 0
|
|
+#define HDP6_CA7_STANDBYWFE1 1
|
|
+#define HDP6_CA7_EVENT0 2
|
|
+#define HDP6_CA7_DBGACK1 3
|
|
+#define HDP6_BSEC_OUT_SEC_SPNIDEN 5
|
|
+#define HDP6_ETH_OUT_MAC_SPEED_O1 6
|
|
+#define HDP6_GPU_DBG1 7
|
|
+#define HDP6_DDRCTRL_CSYSACK_DDRC 8
|
|
+#define HDP6_DDRCTRL_LPR_CREDIT_CNT 9
|
|
+#define HDP6_GPOVAL_6 15
|
|
+
|
|
+#define HDP7_CA7_STANDBYWFI0 0
|
|
+#define HDP7_CA7_STANDBYWFE0 1
|
|
+#define HDP7_CA7_DBGACK0 3
|
|
+#define HDP7_BSEC_OUT_FUSE_OK 4
|
|
+#define HDP7_BSEC_OUT_SEC_SPIDEN 5
|
|
+#define HDP7_ETH_OUT_MAC_SPEED_O0 6
|
|
+#define HDP7_GPU_DBG0 7
|
|
+#define HDP7_DDRCTRL_CSYSREQ_DDRC 8
|
|
+#define HDP7_DDRCTRL_HPR_CREDIT_CNT 9
|
|
+#define HDP7_GPOVAL_7 15
|
|
+
|
|
+#endif /* _DT_BINDINGS_STM32_HDP_H */
|
|
--
|
|
2.17.1
|
|
|