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From 1f4593f966441e5ea3477f974eea8043b75c003c Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@st.com>
Date: Tue, 27 Oct 2020 11:47:53 +0100
Subject: [PATCH 06/10] ARM-v2020.01-stm32mp-r2-DEVICETREE
---
arch/arm/dts/stm32mp15-no-scmi.dtsi | 11 ++--
arch/arm/dts/stm32mp15-pinctrl.dtsi | 8 +--
arch/arm/dts/stm32mp15-u-boot.dtsi | 57 +++++++++++------
arch/arm/dts/stm32mp151.dtsi | 81 +++++++++++++++---------
arch/arm/dts/stm32mp157a-avenger96.dts | 3 +
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 15 +++++
arch/arm/dts/stm32mp157a-dk1.dts | 9 ---
arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 14 ++++
arch/arm/dts/stm32mp157a-ed1.dts | 9 ---
arch/arm/dts/stm32mp157c-dk2.dts | 13 ----
arch/arm/dts/stm32mp157c-ed1.dts | 9 ---
arch/arm/dts/stm32mp157d-dk1.dts | 9 ---
arch/arm/dts/stm32mp157d-ed1.dts | 9 ---
arch/arm/dts/stm32mp157f-dk2.dts | 14 ----
arch/arm/dts/stm32mp157f-ed1.dts | 9 ---
arch/arm/dts/stm32mp15xd.dtsi | 2 +-
arch/arm/dts/stm32mp15xx-dkx.dtsi | 2 +
arch/arm/dts/stm32mp15xx-edx.dtsi | 1 -
arch/arm/dts/stm32mp15xx-evx.dtsi | 25 +++++---
19 files changed, 147 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi
index 3bb96ab8a2..b58b4b0526 100644
--- a/arch/arm/dts/stm32mp15-no-scmi.dtsi
+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi
@@ -61,11 +61,15 @@
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
};
+
+ dsi: dsi@5a000000 {
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ };
};
mlahb {
m4_rproc: m4@10000000 {
- resets = <&rcc MCU_R>;
+ resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>;
m4_system_resources {
m4_cec: cec@40016000 {
@@ -100,10 +104,6 @@
clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
};
-&dsi {
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
-};
-
&gpioz {
clocks = <&rcc GPIOZ>;
};
@@ -153,5 +153,4 @@
&usart1 {
clocks = <&rcc USART1_K>;
- resets = <&rcc USART1_R>;
};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index b8e82adeca..9d51384c18 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1225,7 +1225,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1235,7 +1235,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1329,7 +1329,7 @@
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1341,7 +1341,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index 823e281906..02f9d836ec 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -164,6 +164,38 @@
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
+&usart1 {
+ resets = <&scmi0_reset RST_SCMI0_USART1>;
+};
+
+&usart2 {
+ resets = <&rcc USART2_R>;
+};
+
+&usart3 {
+ resets = <&rcc USART3_R>;
+};
+
+&uart4 {
+ resets = <&rcc UART4_R>;
+};
+
+&uart5 {
+ resets = <&rcc UART5_R>;
+};
+
+&usart6 {
+ resets = <&rcc USART6_R>;
+};
+
+&uart7 {
+ resets = <&rcc UART7_R>;
+};
+
+&uart8{
+ resets = <&rcc UART8_R>;
+};
+
/* NO MORE USE SCMI SUPPORT for BASIC boot chain */
#ifndef CONFIG_STM32MP1_TRUSTED
@@ -172,26 +204,6 @@
/ {
clocks {
u-boot,dm-pre-reloc;
-
- clk_hse: clk-hse {
- u-boot,dm-pre-reloc;
- };
-
- clk_hsi: clk-hsi {
- u-boot,dm-pre-reloc;
- };
-
- clk_lse: clk-lse {
- u-boot,dm-pre-reloc;
- };
-
- clk_lsi: clk-lsi {
- u-boot,dm-pre-reloc;
- };
-
- clk_csi: clk-csi {
- u-boot,dm-pre-reloc;
- };
};
reboot {
@@ -228,4 +240,9 @@
u-boot,dm-spl;
};
};
+
+&usart1 {
+ resets = <&rcc USART1_R>;
+};
+
#endif /* CONFIG_STM32MP1_TRUSTED */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index c516e2ed03..f0211917bb 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -106,12 +106,6 @@
#clock-cells = <1>;
};
};
-
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- status = "disabled";
- };
};
psci {
@@ -444,8 +438,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -536,7 +533,6 @@
reg = <0x4000e000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
- resets = <&rcc USART2_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 43 0x400 0x5>,
@@ -550,7 +546,6 @@
reg = <0x4000f000 0x400>;
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
- resets = <&rcc USART3_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 45 0x400 0x5>,
@@ -564,7 +559,6 @@
reg = <0x40010000 0x400>;
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
- resets = <&rcc UART4_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 63 0x400 0x5>,
@@ -578,7 +572,6 @@
reg = <0x40011000 0x400>;
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
- resets = <&rcc UART5_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 65 0x400 0x5>,
@@ -701,7 +694,6 @@
reg = <0x40018000 0x400>;
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
- resets = <&rcc UART7_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 79 0x400 0x5>,
@@ -715,7 +707,6 @@
reg = <0x40019000 0x400>;
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
- resets = <&rcc UART8_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 81 0x400 0x5>,
@@ -801,7 +792,6 @@
reg = <0x44003000 0x400>;
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
- resets = <&rcc USART6_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 71 0x400 0x5>,
@@ -1365,8 +1355,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1392,8 +1385,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1412,8 +1408,11 @@
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1426,8 +1425,11 @@
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1526,23 +1528,38 @@
dma-requests = <48>;
};
- fmc: nand-controller@58002000 {
- compatible = "st,stm32mp15-fmc2";
- reg = <0x58002000 0x1000>,
- <0x80000000 0x1000>,
- <0x88010000 0x1000>,
- <0x88020000 0x1000>,
- <0x81000000 0x1000>,
- <0x89010000 0x1000>,
- <0x89020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
};
qspi: spi@58003000 {
@@ -1703,7 +1720,6 @@
reg = <0x5c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi0_clk CK_SCMI0_USART1>;
- resets = <&scmi0_reset RST_SCMI0_USART1>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -1768,6 +1784,9 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac_address: mac@e4 {
+ reg = <0xe4 0x6>;
+ };
};
i2c6: i2c@5c009000 {
@@ -1980,9 +1999,9 @@
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&scmi0_reset RST_SCMI0_MCU>;
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
+ resets = <&scmi0_reset RST_SCMI0_MCU>,
+ <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
index 941963ccc2..75efd45179 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -92,6 +92,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+
phy0: ethernet-phy@7 {
reg = <7>;
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 62d7062885..0edcbe9620 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -21,6 +21,7 @@
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
+
led {
red {
label = "error";
@@ -29,6 +30,20 @@
status = "okay";
};
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ optee@de000000 {
+ reg = <0xde000000 0x02000000>;
+ no-map;
+ };
+ };
};
&adc {
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index baff3f6944..1f265fed2c 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -31,14 +31,5 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
index 0f163bc566..23affacad0 100644
--- a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
@@ -30,6 +30,20 @@
status = "okay";
};
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ optee@fe000000 {
+ reg = <0xfe000000 0x02000000>;
+ no-map;
+ };
+ };
};
#ifndef CONFIG_STM32MP1_TRUSTED
diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts
index 5dca956843..e7fad7d394 100644
--- a/arch/arm/dts/stm32mp157a-ed1.dts
+++ b/arch/arm/dts/stm32mp157a-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -46,7 +41,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index a7d5e86a14..ba1d15de2f 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -34,11 +34,6 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
wifi_pwrseq: wifi-pwrseq {
@@ -174,11 +169,3 @@
vddio-supply = <&v3v3>;
};
};
-
-&optee_memory {
- status = "okay";
-};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index bf2d7e7b7d..16ddc0e9f8 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -50,7 +45,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
index c7d65a65e4..aa98012fd3 100644
--- a/arch/arm/dts/stm32mp157d-dk1.dts
+++ b/arch/arm/dts/stm32mp157d-dk1.dts
@@ -31,14 +31,5 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts
index ee55ac8f33..aaf9adf51c 100644
--- a/arch/arm/dts/stm32mp157d-ed1.dts
+++ b/arch/arm/dts/stm32mp157d-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -46,7 +41,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts
index b57db3037d..1123d0f3ed 100644
--- a/arch/arm/dts/stm32mp157f-dk2.dts
+++ b/arch/arm/dts/stm32mp157f-dk2.dts
@@ -34,12 +34,6 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- status = "disabled";
- };
};
wifi_pwrseq: wifi-pwrseq {
@@ -175,11 +169,3 @@
vddio-supply = <&v3v3>;
};
};
-
-&optee_memory {
- status = "okay";
-};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts
index 65380693c8..7ddb96a0ef 100644
--- a/arch/arm/dts/stm32mp157f-ed1.dts
+++ b/arch/arm/dts/stm32mp157f-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@0xfe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -50,7 +45,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi
index faa039ea24..e2f8b1297c 100644
--- a/arch/arm/dts/stm32mp15xd.dtsi
+++ b/arch/arm/dts/stm32mp15xd.dtsi
@@ -27,7 +27,7 @@
};
cpu_alert: cpu-alert {
- temperature = <950000>;
+ temperature = <95000>;
hysteresis = <10000>;
type = "passive";
};
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 35169385fd..685a82161c 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -163,6 +163,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi
index 7ed6b14d77..c67d57cc02 100644
--- a/arch/arm/dts/stm32mp15xx-edx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi
@@ -389,7 +389,6 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
- pinctrl-3 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi
index 07cb93db93..1a2b49cada 100644
--- a/arch/arm/dts/stm32mp15xx-evx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi
@@ -223,11 +223,12 @@
dfsdm1: filter@1 {
compatible = "st,stm32-dfsdm-dmic";
- st,adc-channels = <1>;
+ st,adc-channels = <0>;
st,adc-channel-names = "dmic_u2";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
st,filter-order = <3>;
+ st,adc-alt-channel = <1>;
status = "okay";
asoc_pdm1: dfsdm-dai {
@@ -246,10 +247,11 @@
dfsdm2: filter@2 {
compatible = "st,stm32-dfsdm-dmic";
- st,adc-channels = <3>;
+ st,adc-channels = <2>;
st,adc-channel-names = "dmic_u3";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
+ st,adc-alt-channel = <1>;
st,filter-order = <3>;
status = "okay";
@@ -299,6 +301,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
@@ -315,14 +319,16 @@
pinctrl-0 = <&fmc_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_a>;
status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
@@ -673,6 +679,7 @@
&usbphyc_port0 {
st,phy-tuning = <&usb_phy_tuning>;
+ vbus-supply = <&vbus_sw>;
};
&usbphyc_port1 {
--
2.17.1
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