238 lines
6.9 KiB
Diff
238 lines
6.9 KiB
Diff
From 761f1ccf48cd083baa2bf3a120f8f1da993af217 Mon Sep 17 00:00:00 2001
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From: christophe montaud <christophe.montaud@st.com>
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Date: Mon, 28 Jan 2019 11:04:22 +0100
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Subject: [PATCH 6/8] ARM v2018.11 stm32mp r2 MACHINE
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---
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arch/arm/mach-stm32mp/Kconfig | 13 +++
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arch/arm/mach-stm32mp/Makefile | 1 +
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.../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 22 ++++
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arch/arm/mach-stm32mp/include/mach/stm32.h | 3 +
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arch/arm/mach-stm32mp/stm32mp1_helper_dgb.S | 124 +++++++++++++++++++++
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5 files changed, 163 insertions(+)
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create mode 100644 arch/arm/mach-stm32mp/stm32mp1_helper_dgb.S
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diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
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index 0c68c24..fbc8195 100644
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--- a/arch/arm/mach-stm32mp/Kconfig
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+++ b/arch/arm/mach-stm32mp/Kconfig
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@@ -47,6 +47,19 @@ config TARGET_STM32MP1
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STMicroelectronics MPU with core ARMv7
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dual core A7 for STM32MP153, monocore for STM32MP151
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+config STM32MP1_RESET_HALT_WORKAROUND
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+ bool "workaround for reset halt deubg on stm32mp15x"
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+ depends on TARGET_STM32MP1
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+ default y
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+ help
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+ Activate a workaround for current STM32MP15x revision B
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+ limitation on debug reset halt not handle by ROM code:
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+ add a delay loop early in the SPL boot process to wait for
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+ the debugger to attach
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+ it can be removed when using the Soc revision
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+ that fixes the limitation.
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+
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+
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config STM32MP1_TRUSTED
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bool "Support trusted boot with TF-A"
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default y if !SPL
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diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
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index 09636db..c67bcce 100644
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--- a/arch/arm/mach-stm32mp/Makefile
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+++ b/arch/arm/mach-stm32mp/Makefile
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@@ -9,6 +9,7 @@ obj-y += syscon.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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+obj-$(CONFIG_STM32MP1_RESET_HALT_WORKAROUND) += stm32mp1_helper_dgb.o
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else
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obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/
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obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
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diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
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index d1c07dc..a6ee0f2 100644
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--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
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+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
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@@ -10,6 +10,26 @@
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DECLARE_GLOBAL_DATA_PTR;
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+static void enable_vidconsole(void)
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+{
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+#ifdef CONFIG_DM_VIDEO
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+ char *stdname;
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+ char buf[64];
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+
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+ stdname = env_get("stdout");
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+ if (!strstr(stdname, "vidconsole")) {
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+ snprintf(buf, sizeof(buf), "%s,vidconsole", stdname);
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+ env_set("stdout", buf);
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+ }
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+
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+ stdname = env_get("stderr");
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+ if (!strstr(stdname, "vidconsole")) {
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+ snprintf(buf, sizeof(buf), "%s,vidconsole", stdname);
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+ env_set("stderr", buf);
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+ }
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+#endif
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+}
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+
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static int do_stm32prog(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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@@ -44,6 +64,8 @@ static int do_stm32prog(cmd_tbl_t *cmdtp, int flag, int argc,
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if (argc > 4)
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size = simple_strtoul(argv[4], NULL, 16);
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+ enable_vidconsole();
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+
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data = stm32prog_init(link, dev, addr, size);
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if (!data)
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return CMD_RET_FAILURE;
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diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
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index 4147873..36b885b 100644
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--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
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+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
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@@ -35,6 +35,9 @@
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#define STM32_DDR_BASE 0xC0000000
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#define STM32_DDR_SIZE SZ_1G
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+#define STM32_RETRAM_BASE 0x38000000
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+#define STM32_RETRAM_SIZE 0x00010000
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+
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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diff --git a/arch/arm/mach-stm32mp/stm32mp1_helper_dgb.S b/arch/arm/mach-stm32mp/stm32mp1_helper_dgb.S
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new file mode 100644
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index 0000000..29f8e1f
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--- /dev/null
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+++ b/arch/arm/mach-stm32mp/stm32mp1_helper_dgb.S
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@@ -0,0 +1,124 @@
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+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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+/*
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+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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+ *
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+ */
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+
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+/*****************************************************************************
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+ * This file is only needed for current Soc revision which has a limitation on
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+ * debug reset halt. This can be removed when using the Soc revision that
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+ * fixes the limitation. Anyway, this source code identifies the Soc revision
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+ * and is only executed if it corresponds, so it can be kept on other
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+ * revisions without any consequence.
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+ ****************************************************************************/
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+
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+#include <linux/linkage.h>
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+#include <asm/macro.h>
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+
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+#define BIT(nr) (1 << (nr))
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+
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+#define DBG_DSCR_ADDR 0x500D0088
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+#define DBG_DSCR_HDBGEN BIT(14)
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+
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+#define RCC_DBGCFGR_ADDR 0x5000080C
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+#define RCC_DBGCFGR_DBGCKEN BIT(8)
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+
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+#define PWR_CR1_ADDR 0x50001000
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+#define PWR_CR1_DBP BIT(8)
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+
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+#define DBGMCU_IDC_ADDR 0x50081000
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+#define DBGMCU_IDC_MASK 0xFFFF0FFF
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+#define DBGMCU_IDC_VALUE 0x20000500
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+
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+#define TAMP_BKP_REGISTER_20 (0x5C00A100 + (20 << 2))
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+
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+
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+ .globl save_boot_params
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+
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+ENTRY(save_boot_params)
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+ /*
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+ * This function is the first call after reset.
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+ * Boot rom parameters are stored in r0..r3, so we mustn't use them
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+ * here. And because they are saved in r9..r12 just after the
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+ * execution of this function, we should firstly use these registers.
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+ * And then, if more registers needed, we have to start by using
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+ * r8, and then r7 and so on. By this way, debug will be done in
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+ * conditions closed to the initial context.
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+ */
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+
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+ /* Check Soc revision */
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+ ldr r12, =RCC_DBGCFGR_ADDR
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+ ldr r11, [r12] /* read RCC_DBGCFGR (r11) */
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+ orr r10, r11, #RCC_DBGCFGR_DBGCKEN
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+ str r10, [r12] /* update RCC_DBGCFGR */
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+ ldr r10, =DBGMCU_IDC_ADDR
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+ ldr r10, [r10] /* read DBGMCU_IDC (r10) */
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+ str r11, [r12] /* restore RCC_DBGCFGR (r11) */
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+ ldr r12, =DBGMCU_IDC_MASK
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+ and r10, r12 /* mask reserved bits */
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+ ldr r11, =DBGMCU_IDC_VALUE
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+ teq r10, r11 /* test DBGMCU_IDC */
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+ bne func_exit
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+
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+ /* Disable the backup domain write protection */
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+ ldr r12, =PWR_CR1_ADDR
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+ ldr r11, [r12]
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+ orr r11, r11, #PWR_CR1_DBP
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+ str r11, [r12]
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+poll_dbp:
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+ ldr r11, [r12]
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+ tst r11, #PWR_CR1_DBP
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+ beq poll_dbp
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+
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+ /* Clear tamper 20 bit 16 if set */
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+ ldr r12, =TAMP_BKP_REGISTER_20
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+ ldr r11, [r12]
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+ tst r11, #(BIT(16))
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+ beq func_exit
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+ bic r11, #(BIT(16))
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+ str r11, [r12]
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+
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+ /* Re-enable the backup domain write protection */
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+ ldr r12, =PWR_CR1_ADDR
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+ ldr r11, [r12]
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+ bic r11, #PWR_CR1_DBP
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+ str r11, [r12]
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+poll_dbp_2:
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+ ldr r11, [r12]
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+ tst r11, #PWR_CR1_DBP
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+ bne poll_dbp_2
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+
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+ /* Get current time + 1 second */
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+ /* CNTFRQ */
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+ mrc p15, 0, r12, c14, c0, 0
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+ /* CNTPCT_64 */
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+ mrrc p15, 0, r11, r10, c14
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+ add r12, r12, r11
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+
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+loop:
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+ /* Check A7 DBG_DSCR HDBGEN bit value */
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+ ldr r10, =DBG_DSCR_ADDR
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+ ldr r10, [r10]
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+ tst r10, #DBG_DSCR_HDBGEN
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+ beq loop_continue
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+ /* Sw break */
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+ bkpt 5
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+ /* Jump entrypoint */
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+ b reset
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+loop_continue:
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+ /* Check 1 second expiration */
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+ mrrc p15, 0, r10, r9, c14
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+ /* Check if MSB 64-bit increment needed */
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+ cmp r12, r11
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+ bmi msb_incr
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+ cmp r12, r10
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+ bmi func_exit
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+ b loop
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+msb_incr:
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+ cmp r12, r10
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+ bpl loop
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+ cmp r11, r10
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+ bmi loop
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+func_exit:
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+ b save_boot_params_ret
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+ENDPROC(save_boot_params)
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--
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2.7.4
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