public
/
meta-st-stm32mp
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
meta-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0016-ARM-v2018.11-stm32mp-r...

1192 lines
34 KiB
Diff
Raw Blame History

From 6220cbc776b6bfb9d88646eb98dc4f928e05374b Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 30 Jan 2020 14:57:26 +0100
Subject: [PATCH 16/17] ARM v2018.11 stm32mp r4 DEVICETREE
---
arch/arm/dts/stm32mp157-u-boot.dtsi | 12 +-
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 7 -
arch/arm/dts/stm32mp157a-dk1.dts | 33 +-
arch/arm/dts/stm32mp157c-dk2.dts | 4 +-
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 7 -
arch/arm/dts/stm32mp157c-ed1.dts | 25 +-
arch/arm/dts/stm32mp157c-ev1.dts | 8 +-
arch/arm/dts/stm32mp157c-m4-srm.dtsi | 525 +++++++++++++++++++++++++
arch/arm/dts/stm32mp157c.dtsi | 109 +++--
doc/device-tree-bindings/clock/st,stm32mp1.txt | 4 +
include/dt-bindings/mfd/st,stpmic1.h | 4 +
include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 +
12 files changed, 673 insertions(+), 66 deletions(-)
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
index 98cf1aa..1c1a7cc 100644
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -47,7 +47,7 @@
};
&bsec {
- u-boot,dm-pre-proper;
+ u-boot,dm-pre-reloc;
};
&clk_csi {
@@ -70,6 +70,16 @@
u-boot,dm-pre-reloc;
};
+&cpu0_opp_table {
+ u-boot,dm-spl;
+ opp-650000000 {
+ u-boot,dm-spl;
+ };
+ opp-800000000 {
+ u-boot,dm-spl;
+ };
+};
+
&gpioa {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 757df24..7bc2b7f 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -121,13 +121,6 @@
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 2b01a01..9ec45de 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -7,8 +7,8 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157c-m4-srm.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
+#include "stm32mp157c-m4-srm.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -162,6 +162,14 @@
status = "okay";
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
&dma1 {
sram = <&dma_pool>;
};
@@ -252,9 +260,6 @@
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiog>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&ltdc_pins_a>;
- pinctrl-1 = <&ltdc_pins_sleep_a>;
status = "okay";
ports {
@@ -284,6 +289,7 @@
pinctrl-1 = <&i2c4_pins_sleep_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
@@ -312,10 +318,7 @@
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
-
- st,main-control-register = <0x04>;
- st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x20>;
+ wakeup-source;
regulators {
compatible = "st,stpmic1-regulators";
@@ -427,20 +430,20 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
status = "okay";
};
@@ -487,6 +490,9 @@
};
&ltdc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_pins_sleep_a>;
status = "okay";
port {
@@ -703,6 +709,8 @@
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
pinctrl-3 = <&uart4_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "okay";
};
@@ -711,6 +719,8 @@
pinctrl-0 = <&uart7_pins_a>;
pinctrl-1 = <&uart7_sleep_pins_a>;
pinctrl-2 = <&uart7_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
};
@@ -719,6 +729,7 @@
pinctrl-0 = <&usart3_pins_b>;
pinctrl-1 = <&usart3_sleep_pins_b>;
pinctrl-2 = <&usart3_idle_pins_b>;
+ st,hw-flow-ctrl;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index d11fbb8..5523dc3 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -47,7 +47,7 @@
};
};
- panel@0 {
+ panel: panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@@ -71,6 +71,7 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
+ panel = <&panel>;
status = "okay";
};
touchscreen@38 {
@@ -81,6 +82,7 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
+ panel = <&panel>;
status = "okay";
};
};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 5ab4eeb..898155f 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -119,13 +119,6 @@
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- u-boot,dm-pre-reloc;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index c9eabc1..f5e685d 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -6,8 +6,8 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157c-m4-srm.dtsi"
#include "stm32mp157caa-pinctrl.dtsi"
+#include "stm32mp157c-m4-srm.dtsi"
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
@@ -137,6 +137,14 @@
};
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
@@ -173,6 +181,7 @@
pinctrl-1 = <&i2c4_pins_sleep_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
@@ -184,14 +193,10 @@
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
-
- st,main-control-register = <0x04>;
- st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x20>;
+ wakeup-source;
regulators {
compatible = "st,stpmic1-regulators";
-
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
@@ -295,20 +300,20 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
status = "okay";
};
@@ -408,6 +413,8 @@
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
pinctrl-3 = <&uart4_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 559b9b9..7323f40 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -98,7 +98,7 @@
};
};
- sound {
+ sound: sound {
compatible = "audio-graph-card";
label = "STM32MP1-EV";
routing =
@@ -325,7 +325,7 @@
};
};
- panel-dsi@0 {
+ panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@@ -495,6 +495,7 @@
gt9147: goodix_ts@5d {
compatible = "goodix,gt9147";
reg = <0x5d>;
+ panel = <&panel_dsi>;
status = "okay";
irq-gpios = <&stmfx_pinctrl 14 GPIO_ACTIVE_HIGH>;
@@ -649,7 +650,7 @@
&spdifrx {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spdifrx_pins_a>;
- pinctrl-1 = <&spdifrx_sleep_pins_a>;
+ pinctrl-1 = <&spdifrx_pins_a>;
status = "okay";
spdifrx_port: port {
@@ -717,6 +718,7 @@
pinctrl-0 = <&usart3_pins_a>;
pinctrl-1 = <&usart3_sleep_pins_a>;
pinctrl-2 = <&usart3_idle_pins_a>;
+ st,hw-flow-ctrl;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157c-m4-srm.dtsi b/arch/arm/dts/stm32mp157c-m4-srm.dtsi
index 9ea9736..4d641a9 100644
--- a/arch/arm/dts/stm32mp157c-m4-srm.dtsi
+++ b/arch/arm/dts/stm32mp157c-m4-srm.dtsi
@@ -1,3 +1,528 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ m4_adc1_in6_pins_a: m4-adc1-in6 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, RSVD)>;
+ };
+ };
+
+ m4_adc12_ain_pins_a: m4-adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
+ };
+ };
+
+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
+ <STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
+ };
+ };
+
+ m4_cec_pins_a: m4-cec-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>;
+ };
+ };
+
+ m4_cec_pins_b: m4-cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, RSVD)>;
+ };
+ };
+
+ m4_dac_ch1_pins_a: m4-dac-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>;
+ };
+ };
+
+ m4_dac_ch2_pins_a: m4-dac-ch2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, RSVD)>;
+ };
+ };
+
+ m4_dcmi_pins_a: m4-dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
+ };
+ };
+
+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ m4_fmc_pins_a: m4-fmc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
+ <STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
+ };
+ };
+
+ m4_hdp0_pins_a: m4-hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
+ };
+ };
+
+ m4_hdp6_pins_a: m4-hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
+ };
+ };
+
+ m4_hdp7_pins_a: m4-hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
+ };
+ };
+
+ m4_i2c1_pins_a: m4-i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
+ };
+ };
+
+ m4_i2c2_pins_a: m4-i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
+ };
+ };
+
+ m4_i2c5_pins_a: m4-i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
+ };
+ };
+
+ m4_i2s2_pins_a: m4-i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
+ };
+ };
+
+ m4_ltdc_pins_a: m4-ltdc-a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_ltdc_pins_b: m4-ltdc-b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_m_can1_pins_a: m4-m-can1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
+ };
+ };
+
+ m4_pwm1_pins_a: m4-pwm1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
+ };
+ };
+
+ m4_pwm2_pins_a: m4-pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
+ };
+ };
+
+ m4_pwm3_pins_a: m4-pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
+ };
+ };
+
+ m4_pwm4_pins_a: m4-pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
+ };
+ };
+
+ m4_pwm4_pins_b: m4-pwm4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
+ };
+ };
+
+ m4_pwm5_pins_a: m4-pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
+ };
+ };
+
+ m4_pwm8_pins_a: m4-pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
+ };
+ };
+
+ m4_pwm12_pins_a: m4-pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ m4_qspi_clk_pins_a: m4-qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
+ };
+ };
+
+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
+ };
+ };
+
+ m4_sai2a_pins_a: m4-sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ m4_sai2b_pins_a: m4-sai2b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
+ <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai2b_pins_b: m4-sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai4a_pins_a: m4-sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
+ };
+ };
+
+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
+ <STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
+ };
+ };
+
+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
+ };
+ };
+
+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
+ };
+ };
+
+ m4_spdifrx_pins_a: m4-spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
+ };
+ };
+
+ m4_spi4_pins_a: m4-spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
+ <STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
+ };
+ };
+
+ m4_spi5_pins_a: m4-spi5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
+ <STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
+ };
+ };
+
+ m4_stusb1600_pins_a: m4-stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, RSVD)>;
+ };
+ };
+
+ m4_uart4_pins_a: m4-uart4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
+ };
+ };
+
+ m4_uart7_pins_a: m4-uart7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
+ <STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
+ };
+ };
+
+ m4_usart2_pins_a: m4-usart2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_a: m4-usart3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_b: m4-usart3-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
+ };
+ };
+
+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
+ };
+ };
+};
+
+&pinctrl_z {
+ m4_i2c4_pins_a: m4-i2c4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ };
+ };
+
+ m4_spi1_pins_a: m4-spi1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 2, AF5)>, /* SPI1_MOSI */
+ <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
+ };
+ };
+};
+
&m4_rproc {
m4_system_resources {
#address-cells = <1>;
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index c94a1f25..d56e0f9 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -20,14 +20,36 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clock-frequency = <650000000>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
- clock-frequency = <650000000>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
};
};
@@ -500,6 +522,9 @@
resets = <&rcc USART2_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 43 0x400 0x21>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -513,6 +538,9 @@
resets = <&rcc USART3_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 45 0x400 0x21>,
+ <&dmamux1 46 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -526,6 +554,9 @@
resets = <&rcc UART4_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 63 0x400 0x21>,
+ <&dmamux1 64 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -539,6 +570,9 @@
resets = <&rcc UART5_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 65 0x400 0x21>,
+ <&dmamux1 66 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -666,6 +700,9 @@
resets = <&rcc UART7_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 79 0x400 0x21>,
+ <&dmamux1 80 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -679,6 +716,9 @@
resets = <&rcc UART8_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 81 0x400 0x21>,
+ <&dmamux1 82 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -754,6 +794,9 @@
resets = <&rcc USART6_R>;
wakeup-source;
power-domains = <&pd_core>;
+ dmas = <&dmamux1 71 0x400 0x21>,
+ <&dmamux1 72 0x400 0x1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1060,7 +1103,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@@ -1073,7 +1116,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
@@ -1095,14 +1138,14 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
- dmas = <&mdma1 0 0x11 0x1200000a 0x48000008 0x00000020 1>,
- <&mdma1 1 0x11 0x1200000a 0x48000008 0x00000800 1>,
- <&mdma1 2 0x11 0x1200000a 0x48000008 0x00200000 1>,
- <&mdma1 3 0x11 0x1200000a 0x48000008 0x08000000 1>,
- <&mdma1 4 0x11 0x1200000a 0x4800000C 0x00000020 1>,
- <&mdma1 5 0x11 0x1200000a 0x4800000C 0x00000800 1>,
- <&mdma1 6 0x11 0x1200000a 0x4800000C 0x00200000 1>,
- <&mdma1 7 0x11 0x1200000a 0x4800000C 0x08000000 1>;
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
@@ -1122,14 +1165,14 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
- dmas = <&mdma1 8 0x11 0x1200000a 0x48001008 0x00000020 1>,
- <&mdma1 9 0x11 0x1200000a 0x48001008 0x00000800 1>,
- <&mdma1 10 0x11 0x1200000a 0x48001008 0x00200000 1>,
- <&mdma1 11 0x11 0x1200000a 0x48001008 0x08000000 1>,
- <&mdma1 12 0x11 0x1200000a 0x4800100C 0x00000020 1>,
- <&mdma1 13 0x11 0x1200000a 0x4800100C 0x00000800 1>,
- <&mdma1 14 0x11 0x1200000a 0x4800100C 0x00200000 1>,
- <&mdma1 15 0x11 0x1200000a 0x4800100C 0x08000000 1>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
@@ -1309,6 +1352,13 @@
interrupt-controller;
#interrupt-cells = <3>;
+ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>,
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
+
pwr-regulators {
compatible = "st,stm32mp1,pwr-reg";
st,tzcr = <&rcc 0x0 0x1>;
@@ -1655,7 +1705,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@@ -1690,22 +1740,22 @@
<0x89010000 0x1000>,
<0x89020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x10 0x12000A02 0x0 0x0 0>,
- <&mdma1 20 0x10 0x12000A08 0x0 0x0 0>,
- <&mdma1 21 0x10 0x12000A0A 0x0 0x0 0>;
+ dmas = <&mdma1 20 0x2 0x12000A02 0x0 0x0 0>,
+ <&mdma1 20 0x2 0x12000A08 0x0 0x0 0>,
+ <&mdma1 21 0x2 0x12000A0A 0x0 0x0 0>;
dma-names = "tx", "rx", "ecc";
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
};
- qspi: qspi@58003000 {
+ qspi: spi@58003000 {
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,
- <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
+ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1941,6 +1991,10 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x1>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
@@ -2001,6 +2055,7 @@
st,syscfg-pdds = <&pwr 0x014 0x1>;
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
status = "disabled";
m4_system_resources {
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index ec1d703..a703318 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -84,6 +84,10 @@ Optional Properties:
are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
PLLx is off when the associated node is absent.
+ For PLL1, when the node is absent, the frequency of the OPP node is used
+ to compute the PLL setting (see compatible "operating-points-v2" in
+ opp/opp.txt for details).
+
Here are the available properties for each PLL node:
- cfg: The parameters for PLL configuration in the following order:
diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h
index b2d6c83..321cd08 100644
--- a/include/dt-bindings/mfd/st,stpmic1.h
+++ b/include/dt-bindings/mfd/st,stpmic1.h
@@ -43,4 +43,8 @@
#define IT_SWIN_F 30
#define IT_SWIN_R 31
+/* BUCK MODES definitions */
+#define STPMIC1_BUCK_MODE_NORMAL 0
+#define STPMIC1_BUCK_MODE_LP 2
+
#endif /* __DT_BINDINGS_STPMIC1_H__ */
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index e928aea..e3b45a8 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -26,6 +26,7 @@
#define AF14 0xf
#define AF15 0x10
#define ANALOG 0x11
+#define RSVD 0x12
/* define Pins number*/
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
--
2.7.4
Reference in New Issue View Git Blame Copy Permalink