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meta-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/4.19.9/0044-ARM-stm32mp1-r0-rc3-DE...

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From 494124b8ba0cd0d06a1cf099df668a93ee5e3f23 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Mon, 10 Dec 2018 15:53:27 +0100
Subject: [PATCH 44/52] ARM: stm32mp1-r0-rc3: DEVICETREE
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 375 +++++++++++++++++++---
arch/arm/boot/dts/stm32mp157a-dk1.dts | 47 ++-
arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts | 14 +
arch/arm/boot/dts/stm32mp157c-dk2.dts | 10 +
arch/arm/boot/dts/stm32mp157c-ed1.dts | 66 +++-
arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts | 15 +
arch/arm/boot/dts/stm32mp157c-ev1.dts | 46 ++-
arch/arm/boot/dts/stm32mp157c.dtsi | 221 ++++++++++++-
8 files changed, 705 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 659094e..183d7ba 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -295,7 +295,7 @@
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
@@ -345,7 +345,7 @@
<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
bias-disable;
drive-push-pull;
- slew-rate = <2>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
@@ -372,6 +372,246 @@
};
};
+ hdp0_pins_a: hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp0_pins_sleep_a: hdp0-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
+ };
+ };
+
+ hdp0_pins_b: hdp0-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 10, AF0)>; /* HDP0 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp0_pins_sleep_b: hdp0-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 10, ANALOG)>; /* HDP0 */
+ };
+ };
+
+ hdp1_pins_a: hdp1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 13, AF2)>; /* HDP1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp1_pins_sleep_a: hdp1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 13, ANALOG)>; /* HDP1 */
+ };
+ };
+
+ hdp1_pins_b: hdp1-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 9, AF0)>; /* HDP1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp1_pins_sleep_b: hdp1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 9, ANALOG)>; /* HDP1 */
+ };
+ };
+
+ hdp2_pins_a: hdp2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 5, AF2)>; /* HDP2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp2_pins_sleep_a: hdp2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 5, ANALOG)>; /* HDP2 */
+ };
+ };
+
+ hdp2_pins_b: hdp2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 13, AF0)>; /* HDP2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp2_pins_sleep_b: hdp2-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 13, ANALOG)>; /* HDP2 */
+ };
+ };
+
+ hdp3_pins_a: hdp3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 6, AF2)>; /* HDP3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp3_pins_sleep_a: hdp3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('J', 6, ANALOG)>; /* HDP3 */
+ };
+ };
+
+ hdp3_pins_b: hdp3-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 15, AF0)>; /* HDP3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp3_pins_sleep_b: hdp3-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 15, ANALOG)>; /* HDP3 */
+ };
+ };
+
+ hdp4_pins_a: hdp4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 1, AF2)>; /* HDP4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp4_pins_sleep_a: hdp4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 1, ANALOG)>; /* HDP4 */
+ };
+ };
+
+ hdp4_pins_b: hdp4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF0)>; /* HDP4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp4_pins_sleep_b: hdp4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* HDP4 */
+ };
+ };
+
+ hdp5_pins_a: hdp5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 2, AF2)>; /* HDP5 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp5_pins_sleep_a: hdp5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 2, ANALOG)>; /* HDP5 */
+ };
+ };
+
+ hdp5_pins_b: hdp5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 3, AF0)>; /* HDP5 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp5_pins_sleep_b: hdp5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* HDP5 */
+ };
+ };
+
+ hdp6_pins_a: hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp6_pins_sleep_a: hdp6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
+ };
+ };
+
+ hdp6_pins_b: hdp6-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, AF0)>; /* HDP6 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp6_pins_sleep_b: hdp6-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* HDP6 */
+ };
+ };
+
+ hdp7_pins_a: hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp7_pins_sleep_a: hdp7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
+ };
+ };
+
+ hdp7_pins_b: hdp7-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF0)>; /* HDP7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp7_pins_sleep_b: hdp7-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* HDP7 */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -475,7 +715,7 @@
<STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
- slew-rate = <2>;
+ slew-rate = <1>;
};
};
@@ -544,7 +784,7 @@
<STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
- slew-rate = <2>;
+ slew-rate = <1>;
};
};
@@ -584,7 +824,7 @@
m_can1_pins_a: m-can1-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
+ slew-rate = <0>;
drive-push-pull;
bias-disable;
};
@@ -735,13 +975,13 @@
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
@@ -763,13 +1003,13 @@
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
@@ -805,17 +1045,12 @@
};
sai2a_pins_a: sai2a-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>; /* SAI2_FS_A */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
- slew-rate = <2>;
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
+ slew-rate = <0>;
drive-push-pull;
bias-disable;
};
@@ -833,18 +1068,13 @@
sai2b_pins_a: sai2b-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, AF10)>; /* SAI2_FS_B */
- slew-rate = <1>;
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
drive-push-pull;
bias-disable;
};
pins2 {
- pinmux = <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
@@ -875,7 +1105,7 @@
sai4a_pins_a: sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
- slew-rate = <1>;
+ slew-rate = <0>;
drive-push-pull;
bias-disable;
};
@@ -888,14 +1118,19 @@
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
+ pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
drive-push-pull;
bias-disable;
};
@@ -906,15 +1141,20 @@
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-open-drain;
bias-disable;
};
@@ -936,7 +1176,7 @@
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
@@ -956,14 +1196,19 @@
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
+ pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
@@ -974,15 +1219,20 @@
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <3>;
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
@@ -1005,7 +1255,7 @@
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
@@ -1021,19 +1271,48 @@
};
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
- pins {
+ pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
- <STM32_PINMUX('G', 15, AF10)>, /* SDMMC3_CK */
<STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
};
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
@@ -1140,7 +1419,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -1264,7 +1543,7 @@
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- hwlocks = <&hsem 1>;
+ hwlocks = <&hsem 0>;
gpioz: gpio@54004000 {
gpio-controller;
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 2f01e97..0a6cf35 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -35,9 +35,39 @@
#size-cells = <1>;
ranges;
- ipc_share: sram_rproc@10040000 {
+ retram: retram@0x38000000 {
compatible = "shared-dma-pool";
- reg = <0x10040000 0x10000>;
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ mcuram: mcuram@0x30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ mcuram2: mcuram2@0x10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x2000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x2000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10044000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10044000 0x4000>;
no-map;
};
@@ -77,6 +107,7 @@
sound {
compatible = "audio-graph-card";
+ label = "STM32MP1-DK";
routing =
"Playback" , "MCLK",
"Capture" , "MCLK",
@@ -306,7 +337,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -316,7 +347,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
@@ -402,12 +433,13 @@
watchdog {
compatible = "st,stpmic1-wdt";
+ status = "disabled";
};
};
};
&i2s2 {
- clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL4_Q>;
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2s2_pins_a>;
@@ -447,7 +479,8 @@
};
&m4_rproc {
- memory-region = <&ipc_share>;
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
@@ -470,7 +503,7 @@
};
&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_Q>;
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
new file mode 100644
index 0000000..9c89733
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157c-dk2-a7-examples", "st,stm32mp157c-dk2", "st,stm32mp157";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index fd00386..c276c59 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -72,6 +72,16 @@
touchscreen-size-y = <800>;
status = "okay";
};
+ touchscreen@38 {
+ compatible = "focaltech,ft6336";
+ reg = <0x38>;
+ interrupts = <2 2>;
+ interrupt-parent = <&gpiof>;
+ interrupt-controller;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
};
&ltdc {
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 4f46b41..798580e 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -28,9 +28,39 @@
#size-cells = <1>;
ranges;
- ipc_share: sram_rproc@10040000 {
+ retram: retram@0x38000000 {
compatible = "shared-dma-pool";
- reg = <0x10040000 0x10000>;
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ mcuram: mcuram@0x30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ mcuram2: mcuram2@0x10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x2000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x2000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10044000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10044000 0x4000>;
no-map;
};
@@ -71,6 +101,19 @@
default-state = "off";
};
};
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1 2900000 0x0>;
+ };
};
&adc {
@@ -121,6 +164,10 @@
sram = <&dma_pool>;
};
+&dts {
+ status = "okay";
+};
+
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
@@ -187,7 +234,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -197,7 +244,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
};
vdda: ldo1 {
@@ -277,6 +324,7 @@
watchdog {
compatible = "st,stpmic1-wdt";
+ status = "disabled";
};
};
};
@@ -291,7 +339,8 @@
};
&m4_rproc {
- memory-region = <&ipc_share>;
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
@@ -324,6 +373,12 @@
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -339,6 +394,7 @@
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
+ mmc-ddr-3_3v;
status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
new file mode 100644
index 0000000..5682fb3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-ev1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-EV1 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157c-ev1-a7-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+};
+
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index b60bffc..49a62aa 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -8,6 +8,7 @@
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/stm32-hdp.h>
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
@@ -100,19 +101,15 @@
sound {
compatible = "audio-graph-card";
+ label = "STM32MP1-EV";
routing =
"AIF1CLK" , "MCLK1",
"AIF2CLK" , "MCLK1",
"IN1LN" , "MICBIAS2",
"DMIC2DAT" , "MICBIAS1",
"DMIC1DAT" , "MICBIAS1";
- dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port>;
- status = "okay";
- };
-
- dmics {
- compatible = "audio-graph-card";
- dais = <&cpu_port0 &cpu_port1 &cpu_port2 &cpu_port3>;
+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port
+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>;
status = "okay";
};
@@ -228,7 +225,7 @@
io-channels = <&dfsdm0 0>;
status = "okay";
- cpu_port0: port {
+ dfsdm0_port: port {
dfsdm_endpoint0: endpoint {
remote-endpoint = <&dmic0_endpoint>;
};
@@ -251,7 +248,7 @@
io-channels = <&dfsdm1 0>;
status = "okay";
- cpu_port1: port {
+ dfsdm1_port: port {
dfsdm_endpoint1: endpoint {
remote-endpoint = <&dmic1_endpoint>;
};
@@ -274,7 +271,7 @@
io-channels = <&dfsdm2 0>;
status = "okay";
- cpu_port2: port {
+ dfsdm2_port: port {
dfsdm_endpoint2: endpoint {
remote-endpoint = <&dmic2_endpoint>;
};
@@ -297,7 +294,7 @@
io-channels = <&dfsdm3 0>;
status = "okay";
- cpu_port3: port {
+ dfsdm3_port: port {
dfsdm_endpoint3: endpoint {
remote-endpoint = <&dmic3_endpoint>;
};
@@ -381,6 +378,17 @@
};
};
+&hdp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
+ status = "disabled";
+
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
+ STM32_HDP(6, HDP6_GPOVAL_6) |
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
+};
+
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
@@ -577,7 +585,7 @@
};
&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL4_Q>;
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>;
pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>;
@@ -617,7 +625,7 @@
};
&sai4 {
- clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL4_Q>;
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "x8k", "x11k";
status = "okay";
@@ -639,6 +647,18 @@
};
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ vmmc-supply = <&v3v3>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ status = "disabled";
+};
+
&spdifrx {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spdifrx_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index cef7b3e..7a7ef47 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -156,6 +156,29 @@
mask = <0x1>;
};
+ replicator {
+ /*
+ * non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell"
+ */
+ compatible = "arm,coresight-replicator";
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&funnel_in_port4>;
+ };
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -471,6 +494,7 @@
interrupts-extended = <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<&exti 27 1>;
clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -483,6 +507,7 @@
interrupts-extended = <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<&exti 28 1>;
clocks = <&rcc USART3_K>;
+ resets = <&rcc USART3_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -495,6 +520,7 @@
interrupts-extended = <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<&exti 30 1>;
clocks = <&rcc UART4_K>;
+ resets = <&rcc UART4_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -507,6 +533,7 @@
interrupts-extended = <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<&exti 31 1>;
clocks = <&rcc UART5_K>;
+ resets = <&rcc UART5_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -629,6 +656,7 @@
interrupts-extended = <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&exti 32 1>;
clocks = <&rcc UART7_K>;
+ resets = <&rcc UART7_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -641,6 +669,7 @@
interrupts-extended = <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&exti 33 1>;
clocks = <&rcc UART8_K>;
+ resets = <&rcc UART8_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -713,6 +742,7 @@
interrupts-extended = <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<&exti 29 1>;
clocks = <&rcc USART6_K>;
+ resets = <&rcc USART6_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -1110,7 +1140,7 @@
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x01>;
+ dmas = <&dmamux1 9 0x400 0x05>;
dma-names = "rx";
status = "disabled";
};
@@ -1121,7 +1151,7 @@
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
- dmas = <&dmamux1 10 0x400 0x01>;
+ dmas = <&dmamux1 10 0x400 0x05>;
dma-names = "rx";
/* temperature sensor */
st,adc-channels = <12>;
@@ -1165,8 +1195,8 @@
sdmmc3: sdmmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x48004000 0x400>;
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC3_K>;
@@ -1278,7 +1308,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
- hwlocks = <&hsem 2>;
+ hwlocks = <&hsem 1>;
/* exti_pwr is an extra interrupt controller used for
* EXTI 55 to 60. It's mapped on pwr interrupt
@@ -1427,6 +1457,157 @@
status = "disabled";
};
+ hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+ status = "disabled";
+ };
+
+ funnel: funnel@50091000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x50091000 0x1000>;
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ slave-mode; /* A7-1 input */
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ slave-mode; /* A7-2 input */
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_in_port4: endpoint {
+ slave-mode; /* REPLICATOR input */
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+
+ port@5 {
+ reg = <0>;
+ funnel_out_port0: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ etf: etf@50092000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel_out_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ tpiu: tpiu@50093000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpiu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+
+ stm: stm@500a0000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x500a0000 0x1000>, <0x90000000 0x1000000>,
+ <0x50094000 0x1000>;
+ reg-names = "stm-base", "stm-stimulus-base", "cti-base";
+
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ stm_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ /* Cortex A7-1 */
+ etm1: etm@500dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
+
+ /* Cortex A7-2 */
+ etm2: etm@500dd000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dd000 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&rcc CK_TRACE>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port2>;
+ };
+ };
+ };
+
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
@@ -1490,6 +1671,9 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,
+ <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
+ dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
@@ -1497,8 +1681,8 @@
sdmmc1: sdmmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x58005000 0x1000>;
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
@@ -1512,8 +1696,8 @@
sdmmc2: sdmmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x58007000 0x1000>;
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
@@ -1551,16 +1735,15 @@
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
- "ethstp",
- "syscfg-clk";
+ "ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
- <&rcc ETHSTP>,
- <&rcc SYSCFG>;
+ <&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
+ snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
power-domains = <&pd_core>;
@@ -1573,6 +1756,7 @@
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1583,6 +1767,7 @@
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1656,6 +1841,7 @@
interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<&exti 26 1>;
clocks = <&rcc USART1_K>;
+ resets = <&rcc USART1_R>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -1758,9 +1944,12 @@
m4_rproc: m4@0 {
compatible = "st,stm32mp1-rproc";
- reg = <0x38000000 0x10000>,
- <0x10000000 0x40000>;
- reg-names = "retram", "mcusram";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x00000000 0x38000000 0x10000>,
+ <0x30000000 0x30000000 0x60000>,
+ <0x10000000 0x10000000 0x60000>;
resets = <&rcc MCU_R>;
reset-names = "mcu_rst";
st,syscfg-pdds = <&pwr 0x014 0x1>;
--
2.7.4
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