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meta-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0011-ARM-v2018.11-stm32mp-r...

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From 0317a782b980c961af443f46c185f57bbebc941f Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Tue, 17 Sep 2019 13:55:43 +0200
Subject: [PATCH 11/13] ARM v2018.11 stm32mp r3 DEVICETREE
---
arch/arm/dts/stm32429i-eval-u-boot.dtsi | 11 -
arch/arm/dts/stm32f429-disco-u-boot.dtsi | 11 -
arch/arm/dts/stm32f469-disco-u-boot.dtsi | 11 -
arch/arm/dts/stm32f746.dtsi | 11 -
arch/arm/dts/stm32h743-pinctrl.dtsi | 11 -
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binF.dtsi | 12 +-
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 13 +-
arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binF.dtsi | 8 +-
arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 10 +-
arch/arm/dts/stm32mp157-pinctrl.dtsi | 294 +++++++----------------
arch/arm/dts/stm32mp157-u-boot.dtsi | 35 +--
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 24 +-
arch/arm/dts/stm32mp157a-dk1.dts | 83 +++++--
arch/arm/dts/stm32mp157c-dk2.dts | 11 +-
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 12 +-
arch/arm/dts/stm32mp157c-ed1.dts | 13 +-
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 4 -
arch/arm/dts/stm32mp157c-ev1.dts | 19 +-
arch/arm/dts/stm32mp157c-m4-srm.dtsi | 4 +-
arch/arm/dts/stm32mp157c.dtsi | 90 +++++--
20 files changed, 291 insertions(+), 396 deletions(-)
diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
index 6da0a63..fe437bb 100644
--- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
@@ -92,57 +92,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
index 10e0950..399d4c9 100644
--- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -87,57 +87,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 774f1b5..d370ca7 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -92,57 +92,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index afa7832..4bae1a1 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -130,7 +130,6 @@
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
@@ -140,7 +139,6 @@
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
@@ -151,7 +149,6 @@
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
@@ -161,7 +158,6 @@
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
@@ -171,7 +167,6 @@
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
@@ -181,7 +176,6 @@
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
@@ -191,7 +185,6 @@
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
@@ -201,7 +194,6 @@
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
@@ -211,7 +203,6 @@
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
@@ -221,7 +212,6 @@
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
@@ -231,7 +221,6 @@
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi
index e4f4aa5..65d6ca2 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -54,7 +54,6 @@
gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
@@ -63,7 +62,6 @@
gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
@@ -72,7 +70,6 @@
gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
@@ -81,7 +78,6 @@
gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
@@ -90,7 +86,6 @@
gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
@@ -99,7 +94,6 @@
gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
@@ -108,7 +102,6 @@
gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
@@ -117,7 +110,6 @@
gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
@@ -126,7 +118,6 @@
gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
@@ -135,7 +126,6 @@
gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
@@ -144,7 +134,6 @@
gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binF.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binF.dtsi
index da83310..43edbfe 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binF.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binF.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-/* STM32MP157C DK1/DK2 BOARD configuration
+ *
+ * STM32MP157C DK1/DK2 BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -16,7 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066/777 bin F 1x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/777 bin F 1x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
@@ -89,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x36D477D0
#define DDR_DTPR1 0x098B00D8
@@ -108,11 +108,11 @@
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 16b8cf6..11e8f2b 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-/* STM32MP157C DK1/DK2 BOARD configuration
+ *
+ * STM32MP157C DK1/DK2 BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -16,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
@@ -90,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
@@ -109,11 +108,11 @@
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binF.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binF.dtsi
index 82781e7..e0644a3 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binF.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binF.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-/* STM32MP157C ED1 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -16,7 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066/777 bin F 2x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/777 bin F 2x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
@@ -89,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x36D477D0
#define DDR_DTPR1 0x098B00D8
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 82e7104..4b70b60 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -17,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
@@ -91,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index 183d7ba..dd796ec 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -248,7 +248,7 @@
pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
bias-disable;
drive-push-pull;
- slew-rate = <1>;
+ slew-rate = <0>;
};
};
@@ -291,13 +291,18 @@
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
@@ -387,171 +392,6 @@
};
};
- hdp0_pins_b: hdp0-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 10, AF0)>; /* HDP0 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp0_pins_sleep_b: hdp0-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 10, ANALOG)>; /* HDP0 */
- };
- };
-
- hdp1_pins_a: hdp1-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 13, AF2)>; /* HDP1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp1_pins_sleep_a: hdp1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 13, ANALOG)>; /* HDP1 */
- };
- };
-
- hdp1_pins_b: hdp1-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 9, AF0)>; /* HDP1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp1_pins_sleep_b: hdp1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 9, ANALOG)>; /* HDP1 */
- };
- };
-
- hdp2_pins_a: hdp2-0 {
- pins {
- pinmux = <STM32_PINMUX('J', 5, AF2)>; /* HDP2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp2_pins_sleep_a: hdp2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('J', 5, ANALOG)>; /* HDP2 */
- };
- };
-
- hdp2_pins_b: hdp2-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 13, AF0)>; /* HDP2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp2_pins_sleep_b: hdp2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 13, ANALOG)>; /* HDP2 */
- };
- };
-
- hdp3_pins_a: hdp3-0 {
- pins {
- pinmux = <STM32_PINMUX('J', 6, AF2)>; /* HDP3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp3_pins_sleep_a: hdp3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('J', 6, ANALOG)>; /* HDP3 */
- };
- };
-
- hdp3_pins_b: hdp3-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 15, AF0)>; /* HDP3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp3_pins_sleep_b: hdp3-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 15, ANALOG)>; /* HDP3 */
- };
- };
-
- hdp4_pins_a: hdp4-0 {
- pins {
- pinmux = <STM32_PINMUX('K', 1, AF2)>; /* HDP4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp4_pins_sleep_a: hdp4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('K', 1, ANALOG)>; /* HDP4 */
- };
- };
-
- hdp4_pins_b: hdp4-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, AF0)>; /* HDP4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp4_pins_sleep_b: hdp4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* HDP4 */
- };
- };
-
- hdp5_pins_a: hdp5-0 {
- pins {
- pinmux = <STM32_PINMUX('K', 2, AF2)>; /* HDP5 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp5_pins_sleep_a: hdp5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('K', 2, ANALOG)>; /* HDP5 */
- };
- };
-
- hdp5_pins_b: hdp5-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 3, AF0)>; /* HDP5 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp5_pins_sleep_b: hdp5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* HDP5 */
- };
- };
-
hdp6_pins_a: hdp6-0 {
pins {
pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
@@ -567,21 +407,6 @@
};
};
- hdp6_pins_b: hdp6-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 8, AF0)>; /* HDP6 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp6_pins_sleep_b: hdp6-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* HDP6 */
- };
- };
-
hdp7_pins_a: hdp7-0 {
pins {
pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
@@ -597,21 +422,6 @@
};
};
- hdp7_pins_b: hdp7-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF0)>; /* HDP7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- hdp7_pins_sleep_b: hdp7-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* HDP7 */
- };
- };
-
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -1249,6 +1059,49 @@
};
};
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@@ -1383,6 +1236,13 @@
};
};
+ stusb1600_pins_a: stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ bias-pull-up;
+ };
+ };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -1413,6 +1273,36 @@
};
};
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* USART7_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
+ <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
@@ -1557,16 +1447,6 @@
status = "disabled";
};
- btreg: bt_reg_on-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 6, GPIO)>;
- drive-push-pull;
- bias-pull-up;
- output-high;
- slew-rate = <0>;
- };
- };
-
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
index 035b1c6..98cf1aa 100644
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -21,11 +21,12 @@
pinctrl1 = &pinctrl_z;
};
- clocks {
- u-boot,dm-pre-reloc;
+ /* need PSCI for sysreset during board_f */
+ psci {
+ u-boot,dm-pre-proper;
};
- config {
+ clocks {
u-boot,dm-pre-reloc;
};
@@ -36,12 +37,6 @@
soc {
u-boot,dm-pre-reloc;
- etzpc: etzpc@5C007000 {
- compatible = "st,stm32mp1-etzpc";
- reg = <0x5C007000 0x400>;
- status = "okay";
- };
-
stgen: stgen@5C008000 {
compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>;
@@ -52,7 +47,7 @@
};
&bsec {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
};
&clk_csi {
@@ -76,62 +71,50 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioz {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
@@ -141,7 +124,7 @@
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
};
&pinctrl {
@@ -161,13 +144,13 @@
};
&sdmmc1 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc2 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc3 {
- compatible = "st,stm32-sdmmc2";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 0f9ed9f..757df24 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -33,19 +33,16 @@
};
};
+&adc {
+ status = "okay";
+};
+
&clk_hse {
st,digbypass;
};
&i2c4 {
u-boot,dm-pre-reloc;
-
- stusb1600: typec@28 {
- #extcon-cells = <0>;
- compatible = "st,stusb1600";
- reg = <0x28>;
- status = "okay";
- };
};
&i2c4_pins_a {
@@ -112,7 +109,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
@@ -177,14 +174,7 @@
};
pins2 {
u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
};
};
-
-&usbotg_hs {
- usb1600;
- hnp-srp-disable;
-};
-
-&v3v3 {
- regulator-always-on;
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 8e09447..2b01a01 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -9,7 +9,6 @@
#include "stm32mp157c.dtsi"
#include "stm32mp157c-m4-srm.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -20,6 +19,8 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
};
chosen {
@@ -71,8 +72,8 @@
no-map;
};
- gpu_reserved: gpu@dc000000 {
- reg = <0xdc000000 0x4000000>;
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
no-map;
};
};
@@ -125,11 +126,11 @@
&adc {
pinctrl-names = "default";
- pinctrl-0 = <&adc12_usb_pwr_pins_a>;
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_pwr_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
- status = "okay";
+ status = "disabled";
adc1: adc@0 {
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
@@ -138,13 +139,13 @@
* Use arbitrary margin here (e.g. 5µs).
*/
st,min-sample-time-nsecs = <5000>;
- /* ANA0, ANA1, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 18 19>;
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 6 13 18 19>;
status = "okay";
};
adc2: adc@100 {
- /* ANA0, ANA1, temp sensor, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 12 18 19>;
+ /* AIN connector, temp sensor, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 2 6 12 18 19>;
/* temperature sensor min sample time */
st,min-sample-time-nsecs = <10000>;
status = "okay";
@@ -178,7 +179,7 @@
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
@@ -287,6 +288,23 @@
/delete-property/dmas;
/delete-property/dma-names;
+ typec: stusb1600@28 {
+ compatible = "st,stusb1600";
+ reg = <0x28>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&stusb1600_pins_a>;
+ status = "okay";
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ power-opmode = "default";
+ };
+ };
+
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
@@ -297,7 +315,7 @@
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x30>;
+ st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
@@ -433,6 +451,15 @@
};
};
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_pins_sleep_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
@@ -481,12 +508,16 @@
interrupt-parent = <&exti>;
interrupts = <68 1>;
interrupt-names = "wdg";
+ wakeup-source;
recovery;
status = "okay";
};
&pwr {
- pwr-supply = <&vdd>;
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ };
};
&rng1 {
@@ -554,6 +585,18 @@
status = "okay";
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
&spi4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi4_pins_a>;
@@ -572,6 +615,7 @@
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
+ status = "disabled";
pwm {
pinctrl-0 = <&pwm1_pins_a>;
pinctrl-1 = <&pwm1_sleep_pins_a>;
@@ -586,6 +630,7 @@
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
+ status = "disabled";
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
@@ -600,6 +645,7 @@
&timers4 {
/delete-property/dmas;
/delete-property/dma-names;
+ status = "disabled";
pwm {
pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
@@ -614,6 +660,7 @@
&timers5 {
/delete-property/dmas;
/delete-property/dma-names;
+ status = "disabled";
pwm {
pinctrl-0 = <&pwm5_pins_a>;
pinctrl-1 = <&pwm5_sleep_pins_a>;
@@ -638,6 +685,7 @@
&timers12 {
/delete-property/dmas;
/delete-property/dma-names;
+ status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
pinctrl-1 = <&pwm12_sleep_pins_a>;
@@ -658,6 +706,14 @@
status = "okay";
};
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-1 = <&uart7_sleep_pins_a>;
+ pinctrl-2 = <&uart7_idle_pins_a>;
+ status = "disabled";
+};
+
&usart3 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart3_pins_b>;
@@ -673,8 +729,7 @@
};
&usbotg_hs {
- dr_mode = "peripheral";
- force-b-session-valid;
+ extcon = <&typec>;
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index c276c59..d11fbb8 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -14,7 +14,7 @@
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
- serial1 = &usart2;
+ serial3 = &usart2;
};
wifi_pwrseq: wifi-pwrseq {
@@ -51,6 +51,7 @@
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
status = "okay";
port {
@@ -106,9 +107,10 @@
/* Wifi */
&sdmmc2 {
+ arm,primecell-periphid = <0x10153180>;
pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+ pinctrl-0 = <&sdmmc2_b4_pins_b>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_b>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
st,neg-edge;
@@ -136,8 +138,7 @@
status = "okay";
bluetooth {
- pinctrl-names = "default";
- pinctrl-0 = <&btreg>;
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index b6bf6f1..5ab4eeb 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -16,11 +16,19 @@
config {
u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
led {
+ red {
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+
blue {
default-state = "on";
};
@@ -99,7 +107,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
@@ -195,5 +203,7 @@
};
pins2 {
u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
};
};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 0f70bb7..c9eabc1 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -8,7 +8,6 @@
#include "stm32mp157c.dtsi"
#include "stm32mp157c-m4-srm.dtsi"
#include "stm32mp157caa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
@@ -64,8 +63,8 @@
no-map;
};
- gpu_reserved: gpu@f8000000 {
- reg = <0xf8000000 0x8000000>;
+ gpu_reserved: gpu@e8000000 {
+ reg = <0xe8000000 0x8000000>;
no-map;
};
};
@@ -188,7 +187,7 @@
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x30>;
+ st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
@@ -337,12 +336,16 @@
interrupt-parent = <&exti>;
interrupts = <68 1>;
interrupt-names = "wdg";
+ wakeup-source;
recovery;
status = "okay";
};
&pwr {
- pwr-supply = <&vdd>;
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ };
};
&rng1 {
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index ec08813..86039d6 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -54,7 +54,3 @@
u-boot,dm-spl;
};
};
-
-&usbotg_hs {
- g-tx-fifo-size = <576>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 18742e8..559b9b9 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -7,7 +7,6 @@
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/soc/stm32-hdp.h>
/ {
@@ -330,7 +329,7 @@
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
- power-supply = <&v1v8>;
+ power-supply = <&v3v3>;
backlight = <&panel_backlight>;
status = "okay";
@@ -347,7 +346,7 @@
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
@@ -442,14 +441,12 @@
ov5640: camera@3c {
compatible = "ovti,ov5640";
- pinctrl-names = "default";
- pinctrl-0 = <&ov5640_pins>;
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
status = "okay";
@@ -485,21 +482,13 @@
hog_pins: hog {
pins = "gpio14";
- drive-push-pull;
bias-pull-down;
};
joystick_pins: joystick {
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
bias-pull-down;
};
-
- ov5640_pins: camera {
- pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
- drive-push-pull;
- output-low;
- };
};
};
diff --git a/arch/arm/dts/stm32mp157c-m4-srm.dtsi b/arch/arm/dts/stm32mp157c-m4-srm.dtsi
index 5ebe24b..9ea9736 100644
--- a/arch/arm/dts/stm32mp157c-m4-srm.dtsi
+++ b/arch/arm/dts/stm32mp157c-m4-srm.dtsi
@@ -295,14 +295,14 @@
m4_m_can1: can@4400e000 {
compatible = "rproc-srm-dev";
reg = <0x4400e000>, <0x44011000>;
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
status = "disabled";
};
m4_m_can2: can@4400f000 {
compatible = "rproc-srm-dev";
reg = <0x4400f000>, <0x44011000>;
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 4de499e..c94a1f25 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
/ {
@@ -58,6 +59,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
+ always-on;
};
clocks {
@@ -131,12 +133,6 @@
thermal-sensors = <&dts>;
trips {
- cpu_alert1: cpu-alert1 {
- temperature = <85000>;
- hysteresis = <0>;
- type = "passive";
- };
-
cpu-crit {
temperature = <120000>;
hysteresis = <0>;
@@ -203,6 +199,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -231,6 +228,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -257,6 +255,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -285,6 +284,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -342,6 +342,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -363,6 +364,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -384,6 +386,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -430,8 +433,8 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI2_K>;
resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
status = "disabled";
@@ -456,8 +459,8 @@
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI3_K>;
resets = <&rcc SPI3_R>;
- dmas = <&dmamux1 61 0x400 0x05>,
- <&dmamux1 62 0x400 0x05>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
status = "disabled";
@@ -555,6 +558,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x1>;
status = "disabled";
};
@@ -574,6 +578,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x2>;
status = "disabled";
};
@@ -593,6 +598,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x4>;
status = "disabled";
};
@@ -612,6 +618,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x10>;
status = "disabled";
};
@@ -619,7 +626,7 @@
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CEC_K>, <&clk_lse>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec";
power-domains = <&pd_core>;
status = "disabled";
@@ -695,6 +702,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -725,6 +733,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -756,8 +765,8 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI1_K>;
resets = <&rcc SPI1_R>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
status = "disabled";
@@ -782,8 +791,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
- dmas = <&dmamux1 83 0x400 0x05>,
- <&dmamux1 84 0x400 0x05>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
status = "disabled";
@@ -805,6 +814,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -829,6 +839,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
timer@15 {
@@ -852,6 +863,7 @@
pwm {
compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -870,8 +882,8 @@
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI5_K>;
resets = <&rcc SPI5_R>;
- dmas = <&dmamux1 85 0x400 0x05>,
- <&dmamux1 86 0x400 0x05>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
power-domains = <&pd_core>;
status = "disabled";
@@ -892,6 +904,8 @@
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 87 0x400 0x01>;
status = "disabled";
};
@@ -900,6 +914,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 88 0x400 0x01>;
status = "disabled";
};
@@ -919,6 +935,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 89 0x400 0x01>;
status = "disabled";
};
@@ -927,6 +945,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 90 0x400 0x01>;
status = "disabled";
};
@@ -946,6 +966,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x04 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 113 0x400 0x01>;
status = "disabled";
};
@@ -954,6 +976,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 114 0x400 0x01>;
status = "disabled";
};
@@ -1067,6 +1091,7 @@
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -1093,6 +1118,7 @@
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -1115,6 +1141,7 @@
dma-masters = <&dma1 &dma2>;
dma-channels = <16>;
clocks = <&rcc DMAMUX>;
+ resets = <&rcc DMAMUX_R>;
};
adc: adc@48003000 {
@@ -1215,13 +1242,16 @@
clock-names = "otg";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 44 1>;
+ interrupt-names = "event", "wakeup";
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
dr_mode = "otg";
usb33d-supply = <&usb33>;
power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
@@ -1257,7 +1287,7 @@
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0xd>;
+ dmas = <&dmamux1 75 0x400 0x1d>;
dma-names = "tx";
status = "disabled";
};
@@ -1442,6 +1472,8 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
dmas = <&dmamux1 100 0x400 0x01>;
status = "disabled";
};
@@ -1623,7 +1655,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0 0x0>;
+ dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@@ -1642,6 +1674,7 @@
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
+ resets = <&rcc MDMA_R>;
#dma-cells = <6>;
dma-channels = <32>;
dma-requests = <48>;
@@ -1756,7 +1789,6 @@
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_core>;
status = "disabled";
};
@@ -1765,9 +1797,12 @@
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 43 1>;
+ interrupt-names = "event", "wakeup";
companion = <&usbh_ohci>;
power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
@@ -1834,6 +1869,15 @@
};
};
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
+ clock-names = "bus", "ddr";
+ resets = <&rcc DDRPERFM_R>;
+ status = "okay";
+ };
+
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
@@ -1878,6 +1922,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x8>;
status = "disabled";
};
@@ -1920,6 +1965,7 @@
dma-names = "rx", "tx";
power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x20>;
status = "disabled";
};
--
2.7.4
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