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meta-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0004-ARM-v2021.10-stm32mp-r...

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From e28e03b91ec6d89fdf9463ca581510dff6b091ac Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@foss.st.com>
Date: Mon, 30 May 2022 09:47:18 +0200
Subject: [PATCH 4/5] ARM-v2021.10-stm32mp-r1-DEVICETREE
---
arch/arm/dts/Makefile | 14 +-
arch/arm/dts/stm32429i-eval-u-boot.dtsi | 2 +-
arch/arm/dts/stm32746g-eval-u-boot.dtsi | 2 +-
arch/arm/dts/stm32f429-disco-u-boot.dtsi | 2 +-
arch/arm/dts/stm32f469-disco-u-boot.dtsi | 6 +-
arch/arm/dts/stm32f7-u-boot.dtsi | 4 +-
arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +-
arch/arm/dts/stm32f746.dtsi | 4 +
arch/arm/dts/stm32f769-disco-u-boot.dtsi | 6 +-
arch/arm/dts/stm32h743.dtsi | 4 +
arch/arm/dts/stm32mp13-pinctrl.dtsi | 644 +++++++
arch/arm/dts/stm32mp13-u-boot.dtsi | 131 ++
arch/arm/dts/stm32mp131.dtsi | 1664 +++++++++++++++++
arch/arm/dts/stm32mp133.dtsi | 87 +
arch/arm/dts/stm32mp135.dtsi | 32 +
arch/arm/dts/stm32mp135d-dk-u-boot.dtsi | 70 +
arch/arm/dts/stm32mp135d-dk.dts | 687 +++++++
arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp135f-dk.dts | 689 +++++++
arch/arm/dts/stm32mp13xa.dtsi | 5 +
arch/arm/dts/stm32mp13xc.dtsi | 18 +
arch/arm/dts/stm32mp13xd.dtsi | 5 +
arch/arm/dts/stm32mp13xf.dtsi | 18 +
arch/arm/dts/stm32mp15-ddr.dtsi | 47 +-
.../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 12 -
.../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 12 -
.../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 12 -
.../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 12 -
.../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 12 -
.../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 12 -
arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi | 524 ++++++
arch/arm/dts/stm32mp15-m4-srm.dtsi | 447 +++++
arch/arm/dts/stm32mp15-no-scmi.dtsi | 152 ++
arch/arm/dts/stm32mp15-pinctrl.dtsi | 184 +-
arch/arm/dts/stm32mp15-u-boot.dtsi | 181 +-
arch/arm/dts/stm32mp151.dtsi | 576 ++++--
arch/arm/dts/stm32mp153.dtsi | 15 +-
arch/arm/dts/stm32mp157.dtsi | 3 +-
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 29 +-
arch/arm/dts/stm32mp157a-dk1.dts | 8 +-
arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 211 +++
arch/arm/dts/stm32mp157a-ed1.dts | 32 +
arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi | 61 +
arch/arm/dts/stm32mp157a-ev1.dts | 103 +
.../stm32mp157a-icore-stm32mp1-u-boot.dtsi | 2 +
.../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 2 +
arch/arm/dts/stm32mp157c-dk2.dts | 65 +-
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 222 +--
arch/arm/dts/stm32mp157c-ed1.dts | 382 +---
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 49 +-
arch/arm/dts/stm32mp157c-ev1.dts | 326 +---
.../dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 +
arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157d-dk1.dts | 26 +
arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157d-ed1.dts | 32 +
arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157d-ev1.dts | 103 +
arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157f-dk2.dts | 152 ++
arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157f-ed1.dts | 36 +
arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp157f-ev1.dts | 99 +
arch/arm/dts/stm32mp15xa.dtsi | 13 +
arch/arm/dts/stm32mp15xc.dtsi | 6 +-
arch/arm/dts/stm32mp15xd.dtsi | 42 +
arch/arm/dts/stm32mp15xf.dtsi | 20 +
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 15 +-
.../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 15 +
arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 11 +-
arch/arm/dts/stm32mp15xx-dkx.dtsi | 144 +-
arch/arm/dts/stm32mp15xx-edx.dtsi | 419 +++++
arch/arm/dts/stm32mp15xx-evx.dtsi | 690 +++++++
74 files changed, 8228 insertions(+), 1430 deletions(-)
create mode 100644 arch/arm/dts/stm32mp13-pinctrl.dtsi
create mode 100644 arch/arm/dts/stm32mp13-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp131.dtsi
create mode 100644 arch/arm/dts/stm32mp133.dtsi
create mode 100644 arch/arm/dts/stm32mp135.dtsi
create mode 100644 arch/arm/dts/stm32mp135d-dk-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp135d-dk.dts
create mode 100644 arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp135f-dk.dts
create mode 100644 arch/arm/dts/stm32mp13xa.dtsi
create mode 100644 arch/arm/dts/stm32mp13xc.dtsi
create mode 100644 arch/arm/dts/stm32mp13xd.dtsi
create mode 100644 arch/arm/dts/stm32mp13xf.dtsi
create mode 100644 arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi
create mode 100644 arch/arm/dts/stm32mp15-m4-srm.dtsi
create mode 100644 arch/arm/dts/stm32mp15-no-scmi.dtsi
create mode 100644 arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157a-ed1.dts
create mode 100644 arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157a-ev1.dts
create mode 100644 arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157d-dk1.dts
create mode 100644 arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157d-ed1.dts
create mode 100644 arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157d-ev1.dts
create mode 100644 arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157f-dk2.dts
create mode 100644 arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157f-ed1.dts
create mode 100644 arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp157f-ev1.dts
create mode 100644 arch/arm/dts/stm32mp15xa.dtsi
create mode 100644 arch/arm/dts/stm32mp15xd.dtsi
create mode 100644 arch/arm/dts/stm32mp15xf.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-edx.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-evx.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fc16a57e60..cb6e07726e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1074,9 +1074,15 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_STM32MP13x) += \
+ stm32mp135d-dk.dtb \
+ stm32mp135f-dk.dtb
+
dtb-$(CONFIG_STM32MP15x) += \
- stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
+ stm32mp157a-dk1.dtb \
+ stm32mp157a-ed1.dtb \
+ stm32mp157a-ev1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
@@ -1086,6 +1092,12 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-ev1.dtb \
stm32mp157c-odyssey.dtb \
stm32mp15xx-dhcom-drc02.dtb \
+ stm32mp157d-dk1.dtb \
+ stm32mp157d-ed1.dtb \
+ stm32mp157d-ev1.dtb \
+ stm32mp157f-dk2.dtb \
+ stm32mp157f-ed1.dtb \
+ stm32mp157f-ev1.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
index 09d9d9ab9b..fcab9ae977 100644
--- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
@@ -33,7 +33,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;
diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
index f2195a6c51..8550ef7863 100644
--- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
@@ -177,7 +177,7 @@
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
qflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
index 297cc56144..c993f86be8 100644
--- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -33,7 +33,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 9eda8f535b..cd173623ef 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -34,7 +34,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;
@@ -70,7 +70,7 @@
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <91>;
spi-max-frequency = <108000000>;
@@ -236,7 +236,7 @@
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
flash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 46bd1102df..c1b2ac25c3 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -7,7 +7,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
+ reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
@@ -46,7 +46,7 @@
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <108000000>;
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 4f34fc9a8c..f88466fa60 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -228,7 +228,7 @@
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
qflash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index ba9b3cd03c..78facde2b5 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -313,6 +313,7 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -325,6 +326,7 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -337,6 +339,7 @@
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -349,6 +352,7 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index 7dfe430a40..5589b41652 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -53,9 +53,9 @@
soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
- reg = <0x40016C00 0x800>;
+ reg = <0x40016c00 0x800>;
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
@@ -227,7 +227,7 @@
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l@0 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index ed6857512f..dbfebf07f2 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -124,6 +124,7 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -136,6 +137,7 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -148,6 +150,7 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -395,6 +398,7 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
new file mode 100644
index 0000000000..b8d53065ae
--- /dev/null
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -0,0 +1,644 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
+ dcmipp_pins_a: dcmi-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmipp_sleep_pins_a: dcmi-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_CKOUT */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ dfsdm_datin1_pins_a: dfsdm-datin1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, AF6)>; /* DFSDM_DATIN1 */
+ };
+ };
+
+ dfsdm_datin1_sleep_pins_a: dfsdm-datin1-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* DFSDM_DATIN1 */
+ };
+ };
+
+ dfsdm_datin3_pins_a: dfsdm-datin3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATIN3 */
+ };
+ };
+
+ dfsdm_datin3_sleep_pins_a: dfsdm-datin3-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATIN3 */
+ };
+ };
+
+ eth1_rmii_pins_a: eth1-rmii-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ eth2_rmii_pins_a: eth2-rmii-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ goodix_pins_a: goodix-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, GPIO)>;
+ bias-pull-down;
+ };
+ };
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_a: i2c1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c5_pins_a: i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_a: i2c5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
+ <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
+ <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
+ <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
+ <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
+ <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
+ <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ mcp23017_pins_a: mcp23017-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 1, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 3, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 1, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('G', 3, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
+ };
+ };
+
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
+ };
+ };
+
+ pwm14_pins_a: pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm14_sleep_pins_a: pwm12-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
+ };
+ };
+
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
+ };
+ };
+
+ sai1_pins_a: sai1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
+ <STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1_sleep_pins_a: sai1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
+ <STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
+ <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ spi5_sleep_pins_a: spi5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
+ <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
+ <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
+ };
+ };
+
+ stm32g0_intn_pins_a: stm32g0-intn-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_idle_pins_a: uart8-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_sleep_pins_a: uart8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
+ };
+ };
+
+ usart1_pins_a: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
+ <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_a: usart1-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_a: usart1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
+ <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
+ };
+ };
+
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
new file mode 100644
index 0000000000..4a6d261638
--- /dev/null
+++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2020
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ pinctrl0 = &pinctrl;
+ };
+
+ firmware {
+ optee {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ u-boot,dm-pre-proper;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ddr: ddr@5a003000 {
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp13-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ status = "okay";
+ };
+ };
+};
+
+&bsec {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ u-boot,dm-pre-reloc;
+};
+
+&iwdg2 {
+ u-boot,dm-pre-reloc;
+};
+
+/* pre-reloc probe = reserve video frame buffer in video_reserve() */
+&ltdc {
+ u-boot,dm-pre-proper;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi_reset {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi_shm {
+ u-boot,dm-pre-reloc;
+};
+
+&scmi_sram {
+ u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+ u-boot,dm-pre-reloc;
+};
+
+&usbphyc {
+ /* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
new file mode 100644
index 0000000000..d19cf69401
--- /dev/null
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -0,0 +1,1664 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <dt-bindings/reset/stm32mp13-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&scmi_perf 0>;
+ clock-names = "cpu";
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi_shm@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
+ };
+ };
+
+ firmware {
+ optee {
+ method = "smc";
+ compatible = "linaro,optee-tz";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+
+ scmi_voltd: protocol@17 {
+ reg = <0x17>;
+
+ scmi_regu: regulators {
+ scmi_reg11: voltd-reg11 {
+ voltd-name = "reg11";
+ regulator-name = "reg11";
+ };
+ scmi_reg18: voltd-reg18 {
+ voltd-name = "reg18";
+ regulator-name = "reg18";
+ };
+ scmi_usb33: voltd-usb33 {
+ voltd-name = "usb33";
+ regulator-name = "usb33";
+ };
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ always-on;
+ };
+
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&dts>;
+
+ trips {
+ cpu-crit {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ sram: sram@30000000 {
+ compatible = "mmio-sram";
+ reg = <0x30000000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x30000000 0x8000>;
+ };
+
+ timers2: timer@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc TIM2_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 18 0x400 0x80000001>,
+ <&dmamux1 19 0x400 0x80000001>,
+ <&dmamux1 20 0x400 0x80000001>,
+ <&dmamux1 21 0x400 0x80000001>,
+ <&dmamux1 22 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers3: timer@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc TIM3_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 23 0x400 0x80000001>,
+ <&dmamux1 24 0x400 0x80000001>,
+ <&dmamux1 25 0x400 0x80000001>,
+ <&dmamux1 26 0x400 0x80000001>,
+ <&dmamux1 27 0x400 0x80000001>,
+ <&dmamux1 28 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers4: timer@40002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc TIM4_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 29 0x400 0x80000001>,
+ <&dmamux1 30 0x400 0x80000001>,
+ <&dmamux1 31 0x400 0x80000001>,
+ <&dmamux1 32 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers5: timer@40003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40003000 0x400>;
+ clocks = <&rcc TIM5_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 55 0x400 0x80000001>,
+ <&dmamux1 56 0x400 0x80000001>,
+ <&dmamux1 57 0x400 0x80000001>,
+ <&dmamux1 58 0x400 0x80000001>,
+ <&dmamux1 59 0x400 0x80000001>,
+ <&dmamux1 60 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers6: timer@40004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40004000 0x400>;
+ clocks = <&rcc TIM6_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 69 0x400 0x80000001>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@5 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timers7: timer@40005000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40005000 0x400>;
+ clocks = <&rcc TIM7_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 70 0x400 0x80000001>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@6 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ lptimer1: timer@40009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi2: spi@4000b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI2_K>;
+ resets = <&rcc SPI2_R>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s3: audio-controller@4000c000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi3: spi@4000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI3_K>;
+ resets = <&rcc SPI3_R>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdifrx: audio-controller@4000d000 {
+ compatible = "st,stm32h7-spdifrx";
+ #sound-dai-cells = <0>;
+ reg = <0x4000d000 0x400>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 93 0x400 0x01>,
+ <&dmamux1 94 0x400 0x01>;
+ dma-names = "rx", "rx-ctrl";
+ status = "disabled";
+ };
+
+ usart3: serial@4000f000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000f000 0x400>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART3_K>;
+ resets = <&rcc USART3_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 45 0x400 0x5>,
+ <&dmamux1 46 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART4_K>;
+ resets = <&rcc UART4_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 63 0x400 0x5>,
+ <&dmamux1 64 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@40011000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART5_K>;
+ resets = <&rcc UART5_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 65 0x400 0x5>,
+ <&dmamux1 66 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@40012000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40012000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C1_K>;
+ resets = <&rcc I2C1_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 33 0x400 0x80000001>,
+ <&dmamux1 34 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40013000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40013000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C2_K>;
+ resets = <&rcc I2C2_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 35 0x400 0x80000001>,
+ <&dmamux1 36 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ uart7: serial@40018000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40018000 0x400>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART7_K>;
+ resets = <&rcc UART7_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 79 0x400 0x5>,
+ <&dmamux1 80 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart8: serial@40019000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40019000 0x400>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART8_K>;
+ resets = <&rcc UART8_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 81 0x400 0x5>,
+ <&dmamux1 82 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ timers1: timer@44000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44000000 0x400>;
+ clocks = <&rcc TIM1_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 11 0x400 0x80000001>,
+ <&dmamux1 12 0x400 0x80000001>,
+ <&dmamux1 13 0x400 0x80000001>,
+ <&dmamux1 14 0x400 0x80000001>,
+ <&dmamux1 15 0x400 0x80000001>,
+ <&dmamux1 16 0x400 0x80000001>,
+ <&dmamux1 17 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers8: timer@44001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44001000 0x400>;
+ clocks = <&rcc TIM8_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 47 0x400 0x80000001>,
+ <&dmamux1 48 0x400 0x80000001>,
+ <&dmamux1 49 0x400 0x80000001>,
+ <&dmamux1 50 0x400 0x80000001>,
+ <&dmamux1 51 0x400 0x80000001>,
+ <&dmamux1 52 0x400 0x80000001>,
+ <&dmamux1 53 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ usart6: serial@44003000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x44003000 0x400>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART6_K>;
+ resets = <&rcc USART6_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 71 0x400 0x5>,
+ <&dmamux1 72 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi1: spi@44004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI1_K>;
+ resets = <&rcc SPI1_R>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai1: sai@4400a000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400a000 0x400>;
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+ #sound-dai-cells = <0>;
+
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai1b: audio-controller@4400a024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400b000 0x400>;
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai2b: audio-controller@4400b024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ dfsdm: dfsdm@4400d000 {
+ compatible = "st,stm32mp1-dfsdm";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>;
+ clock-names = "dfsdm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-adc";
+ #io-channel-cells = <1>;
+ reg = <0>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 101 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ dfsdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-adc";
+ #io-channel-cells = <1>;
+ reg = <1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 102 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
+ dma1: dma-controller@48000000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48000000 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ dmas = <&mdma 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
+ <&mdma 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
+ <&mdma 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
+ <&mdma 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
+ <&mdma 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
+ <&mdma 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
+ <&mdma 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
+ <&mdma 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ };
+
+ dma2: dma-controller@48001000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48001000 0x400>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ dmas = <&mdma 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
+ <&mdma 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
+ <&mdma 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
+ <&mdma 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
+ <&mdma 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
+ <&mdma 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
+ <&mdma 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
+ <&mdma 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ };
+
+ dmamux1: dma-router@48002000 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x48002000 0x40>;
+ clocks = <&rcc DMAMUX1>;
+ resets = <&rcc DMAMUX1_R>;
+ #dma-cells = <3>;
+ dma-masters = <&dma1 &dma2>;
+ dma-requests = <128>;
+ dma-channels = <16>;
+ };
+
+ adc_2: adc@48004000 {
+ reg = <0x48004000 0x400>;
+ compatible = "st,stm32mp13-adc-core";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc2: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_2>;
+ interrupts = <0>;
+ dmas = <&dmamux1 10 0x400 0x80000001>;
+ dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
+ status = "disabled";
+ };
+ };
+
+ usbotg_hs: usb-otg@49000000 {
+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+ reg = <0x49000000 0x40000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+ dr_mode = "otg";
+ otg-rev = <0x200>;
+ usb33d-supply = <&scmi_usb33>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ usart1: serial@4c000000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c000000 0x400>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART1_K>;
+ resets = <&rcc USART1_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 41 0x400 0x5>,
+ <&dmamux1 42 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ usart2: serial@4c001000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c001000 0x400>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s4: audio-controller@4c002000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4c002000 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi4: spi@4c002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c002000 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI4_K>;
+ resets = <&rcc SPI4_R>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi5: spi@4c003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c003000 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI5_K>;
+ resets = <&rcc SPI5_R>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@4c004000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c004000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C3_K>;
+ resets = <&rcc I2C3_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 73 0x400 0x80000001>,
+ <&dmamux1 74 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4c005000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c005000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C4_K>;
+ resets = <&rcc I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 75 0x400 0x80000001>,
+ <&dmamux1 76 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c5: i2c@4c006000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c006000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C5_K>;
+ resets = <&rcc I2C5_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 115 0x400 0x80000001>,
+ <&dmamux1 116 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ timers12: timer@4c007000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c007000 0x400>;
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timer@4c008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c008000 0x400>;
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@12 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <12>;
+ status = "disabled";
+ };
+ };
+
+ timers14: timer@4c009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c009000 0x400>;
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@13 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <13>;
+ status = "disabled";
+ };
+ };
+
+ timers15: timer@4c00a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00a000 0x400>;
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 105 0x400 0x80000001>,
+ <&dmamux1 106 0x400 0x80000001>,
+ <&dmamux1 107 0x400 0x80000001>,
+ <&dmamux1 108 0x400 0x80000001>;
+ dma-names = "ch1", "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@14 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <14>;
+ status = "disabled";
+ };
+ };
+
+ timers16: timer@4c00b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00b000 0x400>;
+ clocks = <&rcc TIM16_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 109 0x400 0x80000001>,
+ <&dmamux1 110 0x400 0x80000001>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@15 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <15>;
+ status = "disabled";
+ };
+ };
+
+ timers17: timer@4c00c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00c000 0x400>;
+ clocks = <&rcc TIM17_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 111 0x400 0x80000001>,
+ <&dmamux1 112 0x400 0x80000001>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@16 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <16>;
+ status = "disabled";
+ };
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+ };
+
+ exti: interrupt-controller@5000d000 {
+ compatible = "st,stm32mp13-exti", "syscon";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000d000 0x400>;
+ };
+
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ clocks = <&rcc SYSCFG>;
+ };
+
+ lptimer2: timer@50021000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer3: timer@50022000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@50023000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@50024000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ dts: thermal@50028000 {
+ compatible = "st,stm32-thermal";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DTS>;
+ clock-names = "pclk";
+ #thermal-sensor-cells = <0>;
+ reg = <0x50028000 0x100>;
+ status = "disabled";
+ };
+
+ hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+ status = "disabled";
+ };
+
+ hash: hash@54003000 {
+ compatible = "st,stm32mp13-hash";
+ reg = <0x54003000 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc HASH1>;
+ resets = <&rcc HASH1_R>;
+ dmas = <&mdma 30 0x2 0x1000A02 0x0 0x0 0x0>;
+ dma-names = "in";
+ status = "disabled";
+ };
+
+ rng: rng@54004000 {
+ compatible = "st,stm32mp13-rng";
+ reg = <0x54004000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
+ status = "disabled";
+ };
+
+ mdma: dma-controller@58000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x58000000 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc MDMA>;
+ #dma-cells = <6>;
+ dma-channels = <32>;
+ dma-requests = <48>;
+ };
+
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma 24 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma 25 0x2 0x12000a0a 0x0 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
+ };
+
+ qspi: spi@58003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0 0x0>,
+ <&mdma 26 0x2 0x10100008 0x0 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@58005000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC1_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: mmc@58007000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ crc1: crc@58009000 {
+ compatible = "st,stm32f7-crc";
+ reg = <0x58009000 0x400>;
+ clocks = <&rcc CRC1>;
+ status = "disabled";
+ };
+
+ stmmac_axi_config_0: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH1MAC>,
+ <&rcc ETH1TX>,
+ <&rcc ETH1RX>,
+ <&rcc ETH1STP>,
+ <&rcc ETH1CK_K>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_0>;
+ snps,tso;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ usbh_ohci: usbh-ohci@5800c000 {
+ compatible = "generic-ohci";
+ reg = <0x5800c000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ usbh_ehci: usbh-ehci@5800d000 {
+ compatible = "generic-ehci";
+ reg = <0x5800d000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ companion = <&usbh_ohci>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ iwdg2: watchdog@5a002000 {
+ compatible = "st,stm32mp1-iwdg";
+ reg = <0x5a002000 0x400>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+ clock-names = "pclk", "lsi";
+ status = "disabled";
+ };
+
+ usbphyc: usbphyc@5a006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc USBPHY_K>;
+ resets = <&rcc USBPHY_R>;
+ vdda1v1-supply = <&scmi_reg11>;
+ vdda1v8-supply = <&scmi_reg18>;
+ status = "disabled";
+
+ usbphyc_port0: usb-phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+ interrupts-extended = <&exti 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ status = "disabled";
+ };
+
+ rtc: rtc@5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+ <&scmi_clk CK_SCMI_RTC>;
+ clock-names = "pclk", "rtc_ck";
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ bsec: efuse@5c005000 {
+ compatible = "st,stm32mp13-bsec";
+ reg = <0x5c005000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x2>;
+ };
+ vrefint: vrefin_cal@52 {
+ reg = <0x52 0x2>;
+ };
+ ts_cal1: calib@5c {
+ reg = <0x5c 0x2>;
+ };
+ ts_cal2: calib@5e {
+ reg = <0x5e 0x2>;
+ };
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
+ };
+
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+ */
+ pinctrl: pin-controller@50002000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp135-pinctrl";
+ ranges = <0 0x50002000 0x8400>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc GPIOA>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc GPIOB>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc GPIOC>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc GPIOD>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc GPIOE>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc GPIOF>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc GPIOG>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc GPIOH>;
+ st,bank-name = "GPIOH";
+ ngpios = <15>;
+ gpio-ranges = <&pinctrl 0 112 15>;
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc GPIOI>;
+ st,bank-name = "GPIOI";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 128 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
new file mode 100644
index 0000000000..e00c30cb6e
--- /dev/null
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp131.dtsi"
+
+/ {
+ soc {
+ adc_1: adc@48003000 {
+ compatible = "st,stm32mp13-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_1>;
+ interrupts = <0>;
+ dmas = <&dmamux1 9 0x400 0x80000001>;
+ dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
+ status = "disabled";
+ };
+ };
+
+ m_can1: can@4400e000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ m_can2: can@4400f000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH2MAC>,
+ <&rcc ETH2TX>,
+ <&rcc ETH2RX>,
+ <&rcc ETH2STP>,
+ <&rcc ETH2CK_K>;
+ st,syscon = <&syscfg 0x4 0xff000000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_0>;
+ snps,tso;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi
new file mode 100644
index 0000000000..61052a87d5
--- /dev/null
+++ b/arch/arm/dts/stm32mp135.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp133.dtsi"
+
+/ {
+ soc {
+ dcmipp: dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+ clock-names = "kclk";
+ status = "disabled";
+ };
+
+ ltdc: display-controller@5a001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x5a001000 0x400>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LTDC_PX>;
+ clock-names = "lcd";
+ resets = <&scmi_reset RST_SCMI_LTDC>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi
new file mode 100644
index 0000000000..b969add65c
--- /dev/null
+++ b/arch/arm/dts/stm32mp135d-dk-u-boot.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ */
+
+#include "stm32mp13-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ usb0 = &usbotg_hs;
+ };
+
+ config {
+ u-boot,boot-led = "led-blue";
+ u-boot,error-led = "led-red";
+ u-boot,mmc-env-partition = "u-boot-env";
+ st,adc_usb_pd = <&adc1 6>, <&adc1 12>;
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ leds {
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&adc_1 {
+ status = "okay";
+};
+
+&panel_rgb {
+ compatible = "rocktech,rk043fn48h","simple-panel";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <10000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <10>;
+ hback-porch = <10>;
+ hsync-len = <52>;
+ vfront-porch = <10>;
+ vback-porch = <10>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/stm32mp135d-dk.dts b/arch/arm/dts/stm32mp135d-dk.dts
new file mode 100644
index 0000000000..d56874fb3d
--- /dev/null
+++ b/arch/arm/dts/stm32mp135d-dk.dts
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/rtc/rtc-stm32.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xd.dtsi"
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP135D-DK Discovery Board";
+ compatible = "st,stm32mp135d-dk", "st,stm32mp135";
+
+ aliases {
+ ethernet0 = &eth1;
+ ethernet1 = &eth2;
+ serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_mco1: clk-mco1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pa13 {
+ label = "User-PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee_framebuffer@dd000000 {
+ reg = <0xdd000000 0x1000000>;
+ no-map;
+ };
+
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
+ };
+
+ v3v3_ao: v3v3_ao {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_ao";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h", "panel-dpi";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ data-mapping = "bgr666";
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <&ltdc_out_rgb>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <10000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <52>;
+ hfront-porch = <10>;
+ hback-porch = <10>;
+ vsync-len = <10>;
+ vfront-porch = <10>;
+ vback-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_usb_cc_pins_a>;
+ vdda-supply = <&scmi_vdd_adc>;
+ vref-supply = <&scmi_vdd_adc>;
+ status = "okay";
+ adc1: adc@0 {
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ st,min-sample-time-nsecs = <5000>;
+ /* USB Type-C CC1 & CC2 */
+ st,adc-channels = <6 12>;
+ status = "okay";
+ };
+};
+
+&crc1 {
+ status = "okay";
+};
+
+&dcmipp {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmipp_pins_a>;
+ pinctrl-1 = <&dcmipp_sleep_pins_a>;
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ pclk-max-frequency = <120000000>;
+ };
+ };
+};
+
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&eth1 {
+ status = "okay";
+ pinctrl-0 = <&eth1_rmii_pins_a>;
+ pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth1>;
+ nvmem-cells = <&ethernet_mac1_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0_eth1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+};
+
+&eth2 {
+ status = "okay";
+ pinctrl-0 = <&eth2_rmii_pins_a>;
+ pinctrl-1 = <&eth2_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth2>;
+ st,ext-phyclk;
+ phy-supply = <&scmi_v3v3_sw>;
+ nvmem-cells = <&ethernet_mac2_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0_eth2: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <1000000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ mcp23017: pinctrl@21 {
+ compatible = "microchip,mcp23017";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp23017_pins_a>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ microchip,irq-mirror;
+ };
+
+ stm32g0@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on PI2 */
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+ /* Internal pull-up on PI2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&stm32g0_intn_pins_a>;
+ firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
+ power-domains = <&pd_core>;
+ wakeup-source;
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_g0_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <170>;
+ i2c-scl-falling-time-ns = <5>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ gc2145: gc2145@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ IOVDD-supply = <&scmi_v3v3_sw>;
+ AVDD-supply = <&scmi_v3v3_sw>;
+ DVDD-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ status = "okay";
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ goodix: goodix_ts@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&goodix_pins_a>;
+ interrupt-parent = <&gpiof>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
+ AVDD28-supply = <&scmi_v3v3_sw>;
+ VDDIO-supply = <&scmi_v3v3_sw>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <272>;
+ status = "okay" ;
+ };
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&scmi_v3v3_sw>;
+ status = "disabled";
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ ov5640_0: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ stmipi: stmipi@14 {
+ compatible = "st,st-mipid02";
+ reg = <0x14>;
+ status = "okay";
+ clocks = <&clk_mco1>;
+ clock-names = "xclk";
+ VDDE-supply = <&scmi_v1v8_periph>;
+ VDDIN-supply = <&scmi_v1v8_periph>;
+ reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ mipid02_0: endpoint {
+ data-lanes = <1 2>;
+ lane-polarities = <0 0 0>;
+ remote-endpoint = <&gc2145_ep>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+
+ mipid02_2: endpoint {
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ remote-endpoint = <&dcmipp_0>;
+ };
+ };
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&ltdc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_out_rgb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scmi_regu {
+ scmi_vddcpu: voltd-vddcpu {
+ voltd-name = "vddcpu";
+ regulator-name = "vddcpu";
+ };
+ scmi_vdd: voltd-vdd {
+ voltd-name = "vdd";
+ regulator-name = "vdd";
+ };
+ scmi_vddcore: voltd-vddcore {
+ voltd-name = "vddcore";
+ regulator-name = "vddcore";
+ };
+ scmi_vdd_adc: voltd-vdd_adc {
+ voltd-name = "vdd_adc";
+ regulator-name = "vdd_adc";
+ };
+ scmi_vdd_usb: voltd-vdd_usb {
+ voltd-name = "vdd_usb";
+ regulator-name = "vdd_usb";
+ };
+ scmi_vdd_sd: voltd-vdd_sd {
+ voltd-name = "vdd_sd";
+ regulator-name = "vdd_sd";
+ };
+ scmi_v1v8_periph: voltd-v1v8_periph {
+ voltd-name = "v1v8_periph";
+ regulator-name = "v1v8_periph";
+ };
+ scmi_v3v3_sw: voltd-v3v3_sw {
+ voltd-name = "v3v3_sw";
+ regulator-name = "v3v3_sw";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&scmi_vdd_sd>;
+ status = "okay";
+};
+
+/* Wifi */
+&sdmmc2 {
+ arm,primecell-periphid = <0x10153180>;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3_ao>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&sram {
+ dma_pool: dma-sram@0 {
+ reg = <0x0 0x4000>;
+ pool;
+ };
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers14 {
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm14_pins_a>;
+ pinctrl-1 = <&pwm14_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@13 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart8_pins_a>;
+ pinctrl-1 = <&uart8_sleep_pins_a>;
+ pinctrl-2 = <&uart8_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&usart1 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-1 = <&usart1_sleep_pins_a>;
+ pinctrl-2 = <&usart1_idle_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ pinctrl-2 = <&usart2_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3_ao>;
+ vddio-supply = <&v3v3_ao>;
+ };
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ status = "okay";
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_g0_ep>;
+ };
+ };
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active if wakeup source is enabled
+ * otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&scmi_v3v3_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+};
diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
new file mode 100644
index 0000000000..2b21966ece
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ */
+
+#include "stm32mp135d-dk-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
new file mode 100644
index 0000000000..ef2d9f1374
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -0,0 +1,689 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/rtc/rtc-stm32.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP135F-DK Discovery Board";
+ compatible = "st,stm32mp135f-dk", "st,stm32mp135";
+
+ aliases {
+ ethernet0 = &eth1;
+ ethernet1 = &eth2;
+ serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_mco1: clk-mco1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pa13 {
+ label = "User-PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee_framebuffer@dd000000 {
+ reg = <0xdd000000 0x1000000>;
+ no-map;
+ };
+
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
+ };
+
+ v3v3_ao: v3v3_ao {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_ao";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h", "panel-dpi";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ data-mapping = "bgr666";
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <&ltdc_out_rgb>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <10000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <52>;
+ hfront-porch = <10>;
+ hback-porch = <10>;
+ vsync-len = <10>;
+ vfront-porch = <10>;
+ vback-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_usb_cc_pins_a>;
+ vdda-supply = <&scmi_vdd_adc>;
+ vref-supply = <&scmi_vdd_adc>;
+ status = "okay";
+ adc1: adc@0 {
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ st,min-sample-time-nsecs = <5000>;
+ /* USB Type-C CC1 & CC2 */
+ st,adc-channels = <6 12>;
+ status = "okay";
+ };
+};
+
+&crc1 {
+ status = "okay";
+};
+
+&cryp {
+ status = "okay";
+};
+
+&dcmipp {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmipp_pins_a>;
+ pinctrl-1 = <&dcmipp_sleep_pins_a>;
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ pclk-max-frequency = <120000000>;
+ };
+ };
+};
+
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&eth1 {
+ status = "okay";
+ pinctrl-0 = <&eth1_rmii_pins_a>;
+ pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth1>;
+ nvmem-cells = <&ethernet_mac1_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0_eth1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ };
+ };
+};
+
+&eth2 {
+ status = "okay";
+ pinctrl-0 = <&eth2_rmii_pins_a>;
+ pinctrl-1 = <&eth2_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth2>;
+ st,ext-phyclk;
+ phy-supply = <&scmi_v3v3_sw>;
+ nvmem-cells = <&ethernet_mac2_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0_eth2: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <1000000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ mcp23017: pinctrl@21 {
+ compatible = "microchip,mcp23017";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp23017_pins_a>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ microchip,irq-mirror;
+ };
+
+ stm32g0@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on PI2 */
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+ /* Internal pull-up on PI2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&stm32g0_intn_pins_a>;
+ firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
+ power-domains = <&pd_core>;
+ wakeup-source;
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_g0_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <170>;
+ i2c-scl-falling-time-ns = <5>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ gc2145: gc2145@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ IOVDD-supply = <&scmi_v3v3_sw>;
+ AVDD-supply = <&scmi_v3v3_sw>;
+ DVDD-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ status = "okay";
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ goodix: goodix_ts@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&goodix_pins_a>;
+ interrupt-parent = <&gpiof>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
+ AVDD28-supply = <&scmi_v3v3_sw>;
+ VDDIO-supply = <&scmi_v3v3_sw>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <272>;
+ status = "okay" ;
+ };
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&scmi_v3v3_sw>;
+ status = "disabled";
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ ov5640_0: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ stmipi: stmipi@14 {
+ compatible = "st,st-mipid02";
+ reg = <0x14>;
+ status = "okay";
+ clocks = <&clk_mco1>;
+ clock-names = "xclk";
+ VDDE-supply = <&scmi_v1v8_periph>;
+ VDDIN-supply = <&scmi_v1v8_periph>;
+ reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ mipid02_0: endpoint {
+ data-lanes = <1 2>;
+ lane-polarities = <0 0 0>;
+ remote-endpoint = <&gc2145_ep>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+
+ mipid02_2: endpoint {
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ remote-endpoint = <&dcmipp_0>;
+ };
+ };
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&ltdc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_out_rgb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scmi_regu {
+ scmi_vddcpu: voltd-vddcpu {
+ voltd-name = "vddcpu";
+ regulator-name = "vddcpu";
+ };
+ scmi_vdd: voltd-vdd {
+ voltd-name = "vdd";
+ regulator-name = "vdd";
+ };
+ scmi_vddcore: voltd-vddcore {
+ voltd-name = "vddcore";
+ regulator-name = "vddcore";
+ };
+ scmi_vdd_adc: voltd-vdd_adc {
+ voltd-name = "vdd_adc";
+ regulator-name = "vdd_adc";
+ };
+ scmi_vdd_usb: voltd-vdd_usb {
+ voltd-name = "vdd_usb";
+ regulator-name = "vdd_usb";
+ };
+ scmi_vdd_sd: voltd-vdd_sd {
+ voltd-name = "vdd_sd";
+ regulator-name = "vdd_sd";
+ };
+ scmi_v1v8_periph: voltd-v1v8_periph {
+ voltd-name = "v1v8_periph";
+ regulator-name = "v1v8_periph";
+ };
+ scmi_v3v3_sw: voltd-v3v3_sw {
+ voltd-name = "v3v3_sw";
+ regulator-name = "v3v3_sw";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&scmi_vdd_sd>;
+ status = "okay";
+};
+
+/* Wifi */
+&sdmmc2 {
+ arm,primecell-periphid = <0x10153180>;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3_ao>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&sram {
+ dma_pool: dma-sram@0 {
+ reg = <0x0 0x4000>;
+ pool;
+ };
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers14 {
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm14_pins_a>;
+ pinctrl-1 = <&pwm14_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@13 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart8_pins_a>;
+ pinctrl-1 = <&uart8_sleep_pins_a>;
+ pinctrl-2 = <&uart8_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&usart1 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-1 = <&usart1_sleep_pins_a>;
+ pinctrl-2 = <&usart1_idle_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ pinctrl-2 = <&usart2_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3_ao>;
+ vddio-supply = <&v3v3_ao>;
+ };
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ status = "okay";
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_g0_ep>;
+ };
+ };
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active if wakeup source is enabled
+ * otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&scmi_v3v3_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+};
diff --git a/arch/arm/dts/stm32mp13xa.dtsi b/arch/arm/dts/stm32mp13xa.dtsi
new file mode 100644
index 0000000000..20e52cd271
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xa.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi
new file mode 100644
index 0000000000..4d00e75928
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xc.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp13xd.dtsi b/arch/arm/dts/stm32mp13xd.dtsi
new file mode 100644
index 0000000000..aa8e235686
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xd.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi
new file mode 100644
index 0000000000..4d00e75928
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xf.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 2a139c54e9..e760da8dca 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -4,10 +4,24 @@
*/
#include <linux/stringify.h>
+#ifdef CONFIG_SPL
&ddr {
+ clocks = <&rcc AXIDCG>,
+ <&rcc DDRC1>,
+ <&rcc DDRC2>,
+ <&rcc DDRPHYC>,
+ <&rcc DDRCAPB>,
+ <&rcc DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
config-DDR_MEM_COMPATIBLE {
u-boot,dm-pre-reloc;
-
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
st,mem-name = DDR_MEM_NAME;
@@ -116,27 +130,10 @@
DDR_MR3
>;
-#ifdef DDR_PHY_CAL_SKIP
- st,phy-cal = <
- DDR_DX0DLLCR
- DDR_DX0DQTR
- DDR_DX0DQSTR
- DDR_DX1DLLCR
- DDR_DX1DQTR
- DDR_DX1DQSTR
- DDR_DX2DLLCR
- DDR_DX2DQTR
- DDR_DX2DQSTR
- DDR_DX3DLLCR
- DDR_DX3DQTR
- DDR_DX3DQSTR
- >;
-
-#endif
-
status = "okay";
};
};
+#endif
#undef DDR_MEM_COMPATIBLE
#undef DDR_MEM_NAME
@@ -224,18 +221,6 @@
#undef DDR_ODTCR
#undef DDR_ZQ0CR1
#undef DDR_DX0GCR
-#undef DDR_DX0DLLCR
-#undef DDR_DX0DQTR
-#undef DDR_DX0DQSTR
#undef DDR_DX1GCR
-#undef DDR_DX1DLLCR
-#undef DDR_DX1DQTR
-#undef DDR_DX1DQSTR
#undef DDR_DX2GCR
-#undef DDR_DX2DLLCR
-#undef DDR_DX2DQTR
-#undef DDR_DX2DQSTR
#undef DDR_DX3GCR
-#undef DDR_DX3DLLCR
-#undef DDR_DX3DQTR
-#undef DDR_DX3DQSTR
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 978331b279..e60d0ae606 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE80
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE80
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 426be21f42..1a6fa80edf 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
index b3eb280f96..0a277cd675 100644
--- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi
@@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
index ed3a5248f8..92774fffb9 100644
--- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi
@@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
index d5813d64b0..e53ab18a69 100644
--- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
@@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
index 24c81269b0..ff582ac6af 100644
--- a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
@@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
-#define DDR_DX0DLLCR 0x40000000
-#define DDR_DX0DQTR 0xFFFFFFFF
-#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
-#define DDR_DX1DLLCR 0x40000000
-#define DDR_DX1DQTR 0xFFFFFFFF
-#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
-#define DDR_DX2DLLCR 0x40000000
-#define DDR_DX2DQTR 0xFFFFFFFF
-#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
-#define DDR_DX3DLLCR 0x40000000
-#define DDR_DX3DQTR 0xFFFFFFFF
-#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi
new file mode 100644
index 0000000000..b4030e5c94
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ m4_adc1_in6_pins_a: m4-adc1-in6 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, RSVD)>;
+ };
+ };
+
+ m4_adc12_ain_pins_a: m4-adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
+ };
+ };
+
+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
+ <STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
+ };
+ };
+
+ m4_cec_pins_a: m4-cec-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>;
+ };
+ };
+
+ m4_cec_pins_b: m4-cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, RSVD)>;
+ };
+ };
+
+ m4_dac_ch1_pins_a: m4-dac-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>;
+ };
+ };
+
+ m4_dac_ch2_pins_a: m4-dac-ch2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, RSVD)>;
+ };
+ };
+
+ m4_dcmi_pins_a: m4-dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
+ };
+ };
+
+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ m4_fmc_pins_a: m4-fmc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
+ <STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
+ };
+ };
+
+ m4_hdp0_pins_a: m4-hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
+ };
+ };
+
+ m4_hdp6_pins_a: m4-hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
+ };
+ };
+
+ m4_hdp7_pins_a: m4-hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
+ };
+ };
+
+ m4_i2c1_pins_a: m4-i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
+ };
+ };
+
+ m4_i2c2_pins_a: m4-i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
+ };
+ };
+
+ m4_i2c5_pins_a: m4-i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
+ };
+ };
+
+ m4_i2s2_pins_a: m4-i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
+ };
+ };
+
+ m4_ltdc_pins_a: m4-ltdc-a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_ltdc_pins_b: m4-ltdc-b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_m_can1_pins_a: m4-m-can1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
+ };
+ };
+
+ m4_pwm1_pins_a: m4-pwm1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
+ };
+ };
+
+ m4_pwm2_pins_a: m4-pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
+ };
+ };
+
+ m4_pwm3_pins_a: m4-pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
+ };
+ };
+
+ m4_pwm4_pins_a: m4-pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
+ };
+ };
+
+ m4_pwm4_pins_b: m4-pwm4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
+ };
+ };
+
+ m4_pwm5_pins_a: m4-pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
+ };
+ };
+
+ m4_pwm8_pins_a: m4-pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
+ };
+ };
+
+ m4_pwm12_pins_a: m4-pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ m4_qspi_clk_pins_a: m4-qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
+ };
+ };
+
+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
+ };
+ };
+
+ m4_sai2a_pins_a: m4-sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ m4_sai2b_pins_a: m4-sai2b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
+ <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai2b_pins_b: m4-sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai4a_pins_a: m4-sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
+ };
+ };
+
+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
+ <STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
+ };
+ };
+
+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
+ };
+ };
+
+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
+ };
+ };
+
+ m4_spdifrx_pins_a: m4-spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
+ };
+ };
+
+ m4_spi4_pins_a: m4-spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
+ <STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
+ };
+ };
+
+ m4_spi5_pins_a: m4-spi5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
+ <STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
+ };
+ };
+
+ m4_stusb1600_pins_a: m4-stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, RSVD)>;
+ };
+ };
+
+ m4_uart4_pins_a: m4-uart4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
+ };
+ };
+
+ m4_uart7_pins_a: m4-uart7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
+ <STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
+ };
+ };
+
+ m4_usart2_pins_a: m4-usart2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_a: m4-usart3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_b: m4-usart3-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
+ };
+ };
+
+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
+ };
+ };
+};
+
+&pinctrl_z {
+ m4_i2c4_pins_a: m4-i2c4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
+ };
+ };
+
+ m4_spi1_pins_a: m4-spi1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
+ <STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-m4-srm.dtsi b/arch/arm/dts/stm32mp15-m4-srm.dtsi
new file mode 100644
index 0000000000..7fa3ca411a
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-m4-srm.dtsi
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+&m4_rproc {
+ m4_system_resources {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m4_timers2: timer@40000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc TIM2_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers3: timer@40001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc TIM3_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers4: timer@40002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc TIM4_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers5: timer@40003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40003000 0x400>;
+ clocks = <&rcc TIM5_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers6: timer@40004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40004000 0x400>;
+ clocks = <&rcc TIM6_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers7: timer@40005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40005000 0x400>;
+ clocks = <&rcc TIM7_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers12: timer@40006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40006000 0x400>;
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers13: timer@40007000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40007000 0x400>;
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers14: timer@40008000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40008000 0x400>;
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_lptimer1: timer@40009000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40009000 0x400>;
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_spi2: spi@4000b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000b000 0x400>;
+ clocks = <&rcc SPI2_K>;
+ status = "disabled";
+ };
+ m4_i2s2: audio-controller@4000b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000b000 0x400>;
+ status = "disabled";
+ };
+ m4_spi3: spi@4000c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000c000 0x400>;
+ clocks = <&rcc SPI3_K>;
+ status = "disabled";
+ };
+ m4_i2s3: audio-controller@4000c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000c000 0x400>;
+ status = "disabled";
+ };
+ m4_spdifrx: audio-controller@4000d000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000d000 0x400>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ status = "disabled";
+ };
+ m4_usart2: serial@4000e000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000e000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <27 1>;
+ clocks = <&rcc USART2_K>;
+ status = "disabled";
+ };
+ m4_usart3: serial@4000f000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000f000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <28 1>;
+ clocks = <&rcc USART3_K>;
+ status = "disabled";
+ };
+ m4_uart4: serial@40010000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40010000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <30 1>;
+ clocks = <&rcc UART4_K>;
+ status = "disabled";
+ };
+ m4_uart5: serial@40011000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40011000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <31 1>;
+ clocks = <&rcc UART5_K>;
+ status = "disabled";
+ };
+ m4_i2c1: i2c@40012000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40012000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <21 1>;
+ clocks = <&rcc I2C1_K>;
+ status = "disabled";
+ };
+ m4_i2c2: i2c@40013000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40013000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <22 1>;
+ clocks = <&rcc I2C2_K>;
+ status = "disabled";
+ };
+ m4_i2c3: i2c@40014000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40014000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <23 1>;
+ clocks = <&rcc I2C3_K>;
+ status = "disabled";
+ };
+ m4_i2c5: i2c@40015000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40015000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <25 1>;
+ clocks = <&rcc I2C5_K>;
+ status = "disabled";
+ };
+ m4_cec: cec@40016000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40016000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <69 1>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
+ clock-names = "cec", "hdmi-cec";
+ status = "disabled";
+ };
+ m4_dac: dac@40017000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40017000 0x400>;
+ clocks = <&rcc DAC12>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+ m4_uart7: serial@40018000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40018000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <32 1>;
+ clocks = <&rcc UART7_K>;
+ status = "disabled";
+ };
+ m4_uart8: serial@40019000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40019000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <33 1>;
+ clocks = <&rcc UART8_K>;
+ status = "disabled";
+ };
+ m4_timers1: timer@44000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44000000 0x400>;
+ clocks = <&rcc TIM1_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers8: timer@44001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44001000 0x400>;
+ clocks = <&rcc TIM8_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_usart6: serial@44003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44003000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <29 1>;
+ clocks = <&rcc USART6_K>;
+ status = "disabled";
+ };
+ m4_spi1: spi@44004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44004000 0x400>;
+ clocks = <&rcc SPI1_K>;
+ status = "disabled";
+ };
+ m4_i2s1: audio-controller@44004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44004000 0x400>;
+ status = "disabled";
+ };
+ m4_spi4: spi@44005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44005000 0x400>;
+ clocks = <&rcc SPI4_K>;
+ status = "disabled";
+ };
+ m4_timers15: timer@44006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44006000 0x400>;
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers16: timer@44007000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44007000 0x400>;
+ clocks = <&rcc TIM16_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers17: timer@44008000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44008000 0x400>;
+ clocks = <&rcc TIM17_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_spi5: spi@44009000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44009000 0x400>;
+ clocks = <&rcc SPI5_K>;
+ status = "disabled";
+ };
+ m4_sai1: sai@4400a000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400a000 0x4>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_sai2: sai@4400b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400b000 0x4>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_sai3: sai@4400c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400c000 0x4>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_dfsdm: dfsdm@4400d000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+ clock-names = "dfsdm", "audio";
+ status = "disabled";
+ };
+ m4_m_can1: can@4400e000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ status = "disabled";
+ };
+ m4_m_can2: can@4400f000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ status = "disabled";
+ };
+ m4_dma1: dma@48000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48000000 0x400>;
+ clocks = <&rcc DMA1>;
+ status = "disabled";
+ };
+ m4_dma2: dma@48001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48001000 0x400>;
+ clocks = <&rcc DMA2>;
+ status = "disabled";
+ };
+ m4_dmamux1: dma-router@48002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48002000 0x1c>;
+ clocks = <&rcc DMAMUX>;
+ status = "disabled";
+ };
+ m4_adc: adc@48003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48003000 0x400>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ status = "disabled";
+ };
+ m4_sdmmc3: sdmmc@48004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
+ clocks = <&rcc SDMMC3_K>;
+ status = "disabled";
+ };
+ m4_usbotg_hs: usb-otg@49000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x49000000 0x10000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+ m4_hash2: hash@4c002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c002000 0x400>;
+ clocks = <&rcc HASH2>;
+ status = "disabled";
+ };
+ m4_rng2: rng@4c003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c003000 0x400>;
+ clocks = <&rcc RNG2_K>;
+ status = "disabled";
+ };
+ m4_crc2: crc@4c004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c004000 0x400>;
+ clocks = <&rcc CRC2>;
+ status = "disabled";
+ };
+ m4_cryp2: cryp@4c005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c005000 0x400>;
+ clocks = <&rcc CRYP2>;
+ status = "disabled";
+ };
+ m4_dcmi: dcmi@4c006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c006000 0x400>;
+ clocks = <&rcc DCMI>;
+ clock-names = "mclk";
+ status = "disabled";
+ };
+ m4_lptimer2: timer@50021000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50021000 0x400>;
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer3: timer@50022000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50022000 0x400>;
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer4: timer@50023000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50023000 0x400>;
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer5: timer@50024000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50024000 0x400>;
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_sai4: sai@50027000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50027000 0x4>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_fmc: memory-controller@58002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x5800200 0x1000>;
+ clocks = <&rcc FMC_K>;
+ status = "disabled";
+ };
+ m4_qspi: qspi@58003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ clocks = <&rcc QSPI_K>;
+ status = "disabled";
+ };
+ m4_ethernet0: ethernet@5800a000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x5800a000 0x2000>;
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "syscfg-clk";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
+ <&rcc ETHSTP>,
+ <&rcc SYSCFG>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi
new file mode 100644
index 0000000000..43b8a17230
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+/ {
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ clocks = <&rcc CK_MPU>;
+ };
+
+ cpu1: cpu@1 {
+ clocks = <&rcc CK_MPU>;
+ };
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&rcc>;
+ offset = <0x404>;
+ mask = <0x1>;
+ };
+
+ soc {
+ m_can1: can@4400e000 {
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ };
+
+ m_can2: can@4400f000 {
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ };
+
+ cryp1: cryp@54001000 {
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ };
+
+ dsi: dsi@5a000000 {
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ };
+ };
+
+ ahb {
+ m4_rproc: m4@10000000 {
+ resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>;
+
+ m4_system_resources {
+ m4_m_can1: can@4400e000 {
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ };
+
+ m4_m_can2: can@4400f000 {
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ /delete-node/ scmi;
+ };
+ /delete-node/ sram@2ffff000;
+};
+
+&bsec {
+ clocks = <&rcc BSEC>;
+};
+
+&gpioz {
+ clocks = <&rcc GPIOZ>;
+};
+
+&hash1 {
+ clocks = <&rcc HASH1>;
+ resets = <&rcc HASH1_R>;
+};
+
+&i2c4 {
+ clocks = <&rcc I2C4_K>;
+ resets = <&rcc I2C4_R>;
+};
+
+&i2c6 {
+ clocks = <&rcc I2C6_K>;
+ resets = <&rcc I2C6_R>;
+};
+
+&iwdg2 {
+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+};
+
+&mdma1 {
+ clocks = <&rcc MDMA>;
+ resets = <&rcc MDMA_R>;
+};
+
+&rcc {
+ compatible = "st,stm32mp1-rcc", "syscon";
+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;
+};
+
+&rng1 {
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
+};
+
+&rtc {
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
+};
+
+&spi6 {
+ clocks = <&rcc SPI6_K>;
+ resets = <&rcc SPI6_R>;
+};
+
+&usart1 {
+ clocks = <&rcc USART1_K>;
+};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 5b60ecbd71..d2f2cc8f36 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -151,6 +151,45 @@
};
};
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -437,6 +476,51 @@
};
};
+ hdp0_pins_a: hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp0_pins_sleep_a: hdp0-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
+ };
+ };
+
+ hdp6_pins_a: hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp6_pins_sleep_a: hdp6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
+ };
+ };
+
+ hdp7_pins_a: hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp7_pins_sleep_a: hdp7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -1139,6 +1223,12 @@
};
};
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
+ };
+ };
+
sai2a_pins_a: sai2a-0 {
pins {
pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
@@ -1179,7 +1269,7 @@
};
};
- sai2a_pins_c: sai2a-4 {
+ sai2a_pins_c: sai2a-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
@@ -1190,7 +1280,7 @@
};
};
- sai2a_sleep_pins_c: sai2a-5 {
+ sai2a_sleep_pins_c: sai2a-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
@@ -1235,14 +1325,14 @@
};
};
- sai2b_pins_c: sai2a-4 {
+ sai2b_pins_c: sai2b-2 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
- sai2b_sleep_pins_c: sai2a-sleep-5 {
+ sai2b_sleep_pins_c: sai2b-sleep-2 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
@@ -1716,9 +1806,55 @@
};
};
+ spi4_pins_b: spi4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+ bias-disable;
+ };
+ };
+
+ spi4_sleep_pins_b: spi4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
+ };
+ };
+
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ spi5_sleep_pins_a: spi5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
+ };
+ };
+
stusb1600_pins_a: stusb1600-0 {
pins {
- pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ pinmux = <STM32_PINMUX('I', 11, GPIO)>;
bias-pull-up;
};
};
@@ -1737,20 +1873,20 @@
};
uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
};
uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
+ pins {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
+ };
};
uart4_pins_b: uart4-1 {
@@ -1816,7 +1952,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1826,7 +1962,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1912,7 +2048,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -1930,7 +2066,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2012,7 +2148,7 @@
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
@@ -2029,7 +2165,7 @@
};
pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -2120,4 +2256,12 @@
bias-disable;
};
};
+
+ spi1_sleep_pins_a: spi1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
+ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index 43a7909978..b684ff550d 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -21,8 +21,14 @@
pinctrl1 = &pinctrl_z;
};
- clocks {
- u-boot,dm-pre-reloc;
+ binman: binman {
+ multiple-images;
+ };
+
+ firmware {
+ optee {
+ u-boot,dm-pre-reloc;
+ };
};
/* need PSCI for sysreset during board_f */
@@ -30,14 +36,6 @@
u-boot,dm-pre-proper;
};
- reboot {
- u-boot,dm-pre-reloc;
- compatible = "syscon-reboot";
- regmap = <&rcc>;
- offset = <0x404>;
- mask = <0x1>;
- };
-
soc {
u-boot,dm-pre-reloc;
@@ -49,20 +47,6 @@
reg = <0x5A003000 0x550
0x5A004000 0x234>;
- clocks = <&rcc AXIDCG>,
- <&rcc DDRC1>,
- <&rcc DDRC2>,
- <&rcc DDRPHYC>,
- <&rcc DDRCAPB>,
- <&rcc DDRPHYCAPB>;
-
- clock-names = "axidcg",
- "ddrc1",
- "ddrc2",
- "ddrphyc",
- "ddrcapb",
- "ddrphycapb";
-
status = "okay";
};
};
@@ -72,36 +56,6 @@
u-boot,dm-pre-reloc;
};
-&clk_csi {
- u-boot,dm-pre-reloc;
-};
-
-&clk_hsi {
- u-boot,dm-pre-reloc;
-};
-
-&clk_hse {
- u-boot,dm-pre-reloc;
-};
-
-&clk_lsi {
- u-boot,dm-pre-reloc;
-};
-
-&clk_lse {
- u-boot,dm-pre-reloc;
-};
-
-&cpu0_opp_table {
- u-boot,dm-spl;
- opp-650000000 {
- u-boot,dm-spl;
- };
- opp-800000000 {
- u-boot,dm-spl;
- };
-};
-
&gpioa {
u-boot,dm-pre-reloc;
};
@@ -159,13 +113,6 @@
u-boot,dm-pre-proper;
};
-/* temp = waiting kernel update */
-&m4_rproc {
- resets = <&rcc MCU_R>,
- <&rcc MCU_HOLD_BOOT_R>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
&pinctrl {
u-boot,dm-pre-reloc;
};
@@ -174,30 +121,34 @@
u-boot,dm-pre-reloc;
};
-&pwr_regulators {
+&rcc {
u-boot,dm-pre-reloc;
};
-&rcc {
+#ifdef CONFIG_TFABOOT
+&scmi {
u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <0>;
};
-&sdmmc1 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+&scmi_clk {
+ u-boot,dm-pre-reloc;
};
-&sdmmc2 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+&scmi_reset {
+ u-boot,dm-pre-reloc;
};
-&sdmmc3 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+&scmi_shm {
+ u-boot,dm-pre-reloc;
};
+&scmi_sram {
+ u-boot,dm-pre-reloc;
+};
+#endif
+
&usart1 {
- resets = <&rcc USART1_R>;
+ resets = <&scmi_reset RST_SCMI_USART1>;
};
&usart2 {
@@ -228,3 +179,89 @@
resets = <&rcc UART8_R>;
};
+#if defined(CONFIG_STM32MP15x_STM32IMAGE)
+&binman {
+ u-boot-stm32 {
+ filename = "u-boot.stm32";
+ mkimage {
+ args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
+ u-boot {
+ };
+ };
+ };
+};
+#endif
+
+#if defined(CONFIG_SPL)
+&binman {
+ spl-stm32 {
+ filename = "u-boot-spl.stm32";
+ mkimage {
+ args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
+ u-boot-spl {
+ };
+ };
+ };
+};
+#endif
+
+/* NO MORE USE SCMI SUPPORT for BASIC boot chain */
+#ifndef CONFIG_TFABOOT
+
+#include "stm32mp15-no-scmi.dtsi"
+
+/ {
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ clk_hse: clk-hse {
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_hsi: clk-hsi {
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_lse: clk-lse {
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_lsi: clk-lsi {
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_csi: clk-csi {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ reboot {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpu0_opp_table {
+ u-boot,dm-spl;
+ opp-650000000 {
+ u-boot,dm-spl;
+ };
+ opp-800000000 {
+ u-boot,dm-spl;
+ };
+};
+
+/* only for vdd-supply in sysconf_init() */
+&pwr_regulators {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&usart1 {
+ resets = <&rcc USART1_R>;
+};
+
+#endif /* CONFIG_TFABOOT */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 8e0a0bc1dd..2d403bb090 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
/ {
@@ -17,35 +18,65 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
device_type = "cpu";
reg = <0>;
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+ clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
nvmem-cells = <&part_number_otp>;
nvmem-cell-names = "part_number";
+ #cooling-cells = <2>;
};
};
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
- opp-650000000 {
- opp-hz = /bits/ 64 <650000000>;
- opp-microvolt = <1200000>;
- opp-supported-hw = <0x1>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1350000>;
- opp-supported-hw = <0x2>;
+ };
+
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi_shm@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
};
};
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
};
psci {
@@ -63,45 +94,13 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_csi: clk-csi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4000000>;
- };
- };
-
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@@ -109,12 +108,6 @@
thermal-sensors = <&dts>;
trips {
- cpu_alert1: cpu-alert1 {
- temperature = <85000>;
- hysteresis = <0>;
- type = "passive";
- };
-
cpu-crit {
temperature = <120000>;
hysteresis = <0>;
@@ -133,6 +126,26 @@
status = "disabled";
};
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -140,6 +153,14 @@
interrupt-parent = <&intc>;
ranges;
+ sram: sram@10000000 {
+ compatible = "mmio-sram";
+ reg = <0x10000000 0x60000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10000000 0x60000>;
+ };
+
timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -147,11 +168,11 @@
reg = <0x40000000 0x400>;
clocks = <&rcc TIM2_K>;
clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
+ dmas = <&dmamux1 18 0x400 0x80000001>,
+ <&dmamux1 19 0x400 0x80000001>,
+ <&dmamux1 20 0x400 0x80000001>,
+ <&dmamux1 21 0x400 0x80000001>,
+ <&dmamux1 22 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up";
status = "disabled";
@@ -180,12 +201,12 @@
reg = <0x40001000 0x400>;
clocks = <&rcc TIM3_K>;
clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
+ dmas = <&dmamux1 23 0x400 0x80000001>,
+ <&dmamux1 24 0x400 0x80000001>,
+ <&dmamux1 25 0x400 0x80000001>,
+ <&dmamux1 26 0x400 0x80000001>,
+ <&dmamux1 27 0x400 0x80000001>,
+ <&dmamux1 28 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
@@ -214,10 +235,10 @@
reg = <0x40002000 0x400>;
clocks = <&rcc TIM4_K>;
clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
+ dmas = <&dmamux1 29 0x400 0x80000001>,
+ <&dmamux1 30 0x400 0x80000001>,
+ <&dmamux1 31 0x400 0x80000001>,
+ <&dmamux1 32 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4";
status = "disabled";
@@ -246,12 +267,12 @@
reg = <0x40003000 0x400>;
clocks = <&rcc TIM5_K>;
clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
+ dmas = <&dmamux1 55 0x400 0x80000001>,
+ <&dmamux1 56 0x400 0x80000001>,
+ <&dmamux1 57 0x400 0x80000001>,
+ <&dmamux1 58 0x400 0x80000001>,
+ <&dmamux1 59 0x400 0x80000001>,
+ <&dmamux1 60 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
@@ -280,7 +301,7 @@
reg = <0x40004000 0x400>;
clocks = <&rcc TIM6_K>;
clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
+ dmas = <&dmamux1 69 0x400 0x80000001>;
dma-names = "up";
status = "disabled";
@@ -298,7 +319,7 @@
reg = <0x40005000 0x400>;
clocks = <&rcc TIM7_K>;
clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
+ dmas = <&dmamux1 70 0x400 0x80000001>;
dma-names = "up";
status = "disabled";
@@ -383,6 +404,7 @@
interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -402,6 +424,11 @@
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
spi2: spi@4000b000 {
@@ -412,8 +439,8 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI2_K>;
resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -437,8 +464,8 @@
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI3_K>;
resets = <&rcc SPI3_R>;
- dmas = <&dmamux1 61 0x400 0x05>,
- <&dmamux1 62 0x400 0x05>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -473,6 +500,10 @@
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 43 0x400 0x15>,
+ <&dmamux1 44 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -482,6 +513,10 @@
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 45 0x400 0x15>,
+ <&dmamux1 46 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -491,6 +526,10 @@
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 63 0x400 0x15>,
+ <&dmamux1 64 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -500,6 +539,10 @@
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 65 0x400 0x15>,
+ <&dmamux1 66 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -507,12 +550,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40012000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C1_K>;
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 33 0x400 0x80000001>,
+ <&dmamux1 34 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
i2c-analog-filter;
@@ -523,12 +570,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C2_K>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 35 0x400 0x80000001>,
+ <&dmamux1 36 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
i2c-analog-filter;
@@ -539,12 +590,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40014000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 73 0x400 0x80000001>,
+ <&dmamux1 74 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
i2c-analog-filter;
@@ -555,12 +610,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40015000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 115 0x400 0x80000001>,
+ <&dmamux1 116 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
i2c-analog-filter;
@@ -571,7 +630,7 @@
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CEC_K>, <&clk_lse>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
@@ -606,6 +665,10 @@
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 79 0x400 0x15>,
+ <&dmamux1 80 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -615,6 +678,10 @@
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 81 0x400 0x15>,
+ <&dmamux1 82 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -625,13 +692,13 @@
reg = <0x44000000 0x400>;
clocks = <&rcc TIM1_K>;
clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
+ dmas = <&dmamux1 11 0x400 0x80000001>,
+ <&dmamux1 12 0x400 0x80000001>,
+ <&dmamux1 13 0x400 0x80000001>,
+ <&dmamux1 14 0x400 0x80000001>,
+ <&dmamux1 15 0x400 0x80000001>,
+ <&dmamux1 16 0x400 0x80000001>,
+ <&dmamux1 17 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
status = "disabled";
@@ -661,13 +728,13 @@
reg = <0x44001000 0x400>;
clocks = <&rcc TIM8_K>;
clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
+ dmas = <&dmamux1 47 0x400 0x80000001>,
+ <&dmamux1 48 0x400 0x80000001>,
+ <&dmamux1 49 0x400 0x80000001>,
+ <&dmamux1 50 0x400 0x80000001>,
+ <&dmamux1 51 0x400 0x80000001>,
+ <&dmamux1 52 0x400 0x80000001>,
+ <&dmamux1 53 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
status = "disabled";
@@ -696,6 +763,10 @@
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 71 0x400 0x15>,
+ <&dmamux1 72 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -707,8 +778,8 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI1_K>;
resets = <&rcc SPI1_R>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -732,8 +803,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
- dmas = <&dmamux1 83 0x400 0x05>,
- <&dmamux1 84 0x400 0x05>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -745,10 +816,10 @@
reg = <0x44006000 0x400>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
+ dmas = <&dmamux1 105 0x400 0x80000001>,
+ <&dmamux1 106 0x400 0x80000001>,
+ <&dmamux1 107 0x400 0x80000001>,
+ <&dmamux1 108 0x400 0x80000001>;
dma-names = "ch1", "up", "trig", "com";
status = "disabled";
@@ -772,8 +843,8 @@
reg = <0x44007000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
+ dmas = <&dmamux1 109 0x400 0x80000001>,
+ <&dmamux1 110 0x400 0x80000001>;
dma-names = "ch1", "up";
status = "disabled";
@@ -796,8 +867,8 @@
reg = <0x44008000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
+ dmas = <&dmamux1 111 0x400 0x80000001>,
+ <&dmamux1 112 0x400 0x80000001>;
dma-names = "ch1", "up";
status = "disabled";
@@ -822,8 +893,8 @@
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI5_K>;
resets = <&rcc SPI5_R>;
- dmas = <&dmamux1 85 0x400 0x05>,
- <&dmamux1 86 0x400 0x05>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -842,7 +913,7 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x1c>;
+ reg = <0x4 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 87 0x400 0x01>;
@@ -852,7 +923,7 @@
sai1b: audio-controller@4400a024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 88 0x400 0x01>;
@@ -873,7 +944,7 @@
sai2a: audio-controller@4400b004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x1c>;
+ reg = <0x4 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 89 0x400 0x01>;
@@ -883,7 +954,7 @@
sai2b: audio-controller@4400b024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 90 0x400 0x01>;
@@ -904,7 +975,7 @@
sai3a: audio-controller@4400c004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x1c>;
+ reg = <0x04 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 113 0x400 0x01>;
@@ -914,7 +985,7 @@
sai3b: audio-controller@4400c024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 114 0x400 0x01>;
@@ -1008,6 +1079,15 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
dma2: dma-controller@48001000 {
@@ -1026,6 +1106,15 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
dmamux1: dma-router@48002000 {
@@ -1059,7 +1148,7 @@
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x01>;
+ dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
};
@@ -1070,14 +1159,16 @@
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
- dmas = <&dmamux1 10 0x400 0x01>;
+ dmas = <&dmamux1 10 0x400 0x80000001>;
dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
status = "disabled";
};
};
sdmmc3: mmc@48004000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@@ -1098,21 +1189,24 @@
clock-names = "otg";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
+ otg-rev = <0x200>;
usb33d-supply = <&usb33>;
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
- hwspinlock: hwspinlock@4c000000 {
+ hsem: hwspinlock@4c000000 {
compatible = "st,stm32-hwspinlock";
- #hwlock-cells = <1>;
+ #hwlock-cells = <2>;
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
- clock-names = "hwspinlock";
+ clock-names = "hsem";
};
ipcc: mailbox@4c001000 {
@@ -1121,12 +1215,12 @@
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 61 1>;
- interrupt-names = "rx", "tx", "wakeup";
+ <&exti 61 1>,
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;
wakeup-source;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1137,25 +1231,29 @@
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0x01>;
+ dmas = <&dmamux1 75 0x400 0xe0000001>;
dma-names = "tx";
status = "disabled";
};
rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
- <&clk_lse>, <&clk_lsi>;
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
};
pwr_regulators: pwr@50001000 {
compatible = "st,stm32mp1,pwr-reg";
reg = <0x50001000 0x10>;
+ st,tzcr = <&rcc 0x0 0x1>;
reg11: reg11 {
regulator-name = "reg11";
@@ -1181,11 +1279,38 @@
reg = <0x50001014 0x4>;
};
+ pwr_irq: pwr@50001020 {
+ compatible = "st,stm32mp1-pwr";
+ reg = <0x50001020 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ st,wakeup-pins = <&gpioa 0 GPIO_ACTIVE_HIGH>,
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
+ hwlocks = <&hsem 1 1>;
+
+ /* exti_pwr is an extra interrupt controller used for
+ * EXTI 55 to 60. It's mapped on pwr interrupt
+ * controller.
+ */
+ exti_pwr: exti-pwr {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&pwr_irq>;
+ st,irq-number = <6>;
+ };
};
syscfg: syscon@50020000 {
@@ -1202,6 +1327,7 @@
interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1221,6 +1347,11 @@
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer3: timer@50022000 {
@@ -1231,6 +1362,7 @@
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1245,6 +1377,11 @@
reg = <2>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer4: timer@50023000 {
@@ -1253,6 +1390,7 @@
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1261,6 +1399,11 @@
#pwm-cells = <3>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer5: timer@50024000 {
@@ -1269,6 +1412,7 @@
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1277,6 +1421,11 @@
#pwm-cells = <3>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
vrefbuf: vrefbuf@50025000 {
@@ -1301,7 +1450,7 @@
sai4a: audio-controller@50027004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x1c>;
+ reg = <0x04 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 99 0x400 0x01>;
@@ -1311,7 +1460,7 @@
sai4b: audio-controller@50027024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 100 0x400 0x01>;
@@ -1329,13 +1478,21 @@
status = "disabled";
};
+ hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+ status = "disabled";
+ };
+
hash1: hash@54002000 {
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc HASH1>;
- resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@@ -1344,8 +1501,8 @@
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
status = "disabled";
};
@@ -1354,8 +1511,8 @@
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
- resets = <&rcc MDMA_R>;
- #dma-cells = <5>;
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+ #dma-cells = <6>;
dma-channels = <32>;
dma-requests = <48>;
};
@@ -1386,9 +1543,9 @@
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
status = "disabled";
};
@@ -1399,8 +1556,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
- <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0 0x0>,
+ <&mdma1 22 0x2 0x10100008 0x0 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1410,7 +1567,7 @@
};
sdmmc1: mmc@58005000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -1425,7 +1582,7 @@
};
sdmmc2: mmc@58007000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -1450,8 +1607,10 @@
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_wake_irq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
@@ -1471,6 +1630,7 @@
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
+ power-domains = <&pd_core>;
stmmac_axi_config_0: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
@@ -1482,7 +1642,7 @@
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
- clocks = <&rcc USBH>;
+ clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1491,10 +1651,12 @@
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
- clocks = <&rcc USBH>;
+ clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
@@ -1517,7 +1679,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
@@ -1545,12 +1707,22 @@
};
};
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ status = "disabled";
+ };
+
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
+ clocks = <&scmi_clk CK_SCMI_USART1>;
+ resets = <&scmi_reset RST_SCMI_USART1>;
wakeup-source;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1560,10 +1732,10 @@
compatible = "st,stm32h7-spi";
reg = <0x5c001000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI6_K>;
- resets = <&rcc SPI6_R>;
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
+ clocks = <&scmi_clk CK_SCMI_SPI6>;
+ resets = <&scmi_reset RST_SCMI_SPI6>;
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1572,12 +1744,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
i2c-analog-filter;
@@ -1587,38 +1763,50 @@
rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+ <&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_BSEC>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part_number_otp@4 {
reg = <0x4 0x1>;
};
+ vrefint: calib@52 {
+ reg = <0x52 0x2>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac_address: mac@e4 {
+ reg = <0xe4 0x6>;
+ };
};
i2c6: i2c@5c009000 {
compatible = "st,stm32mp15-i2c";
reg = <0x5c009000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C6_K>;
- resets = <&rcc I2C6_R>;
+ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_I2C6>;
+ resets = <&scmi_reset RST_SCMI_I2C6>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
i2c-analog-filter;
@@ -1628,6 +1816,19 @@
tamp: tamp@5c00a000 {
compatible = "st,stm32-tamp", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x150>; /* reg20 */
+ mask = <0xff>;
+ mode-normal = <0>;
+ mode-fastboot = <0x1>;
+ mode-recovery = <0x2>;
+ mode-stm32cubeprogrammer = <0x3>;
+ mode-ums_mmc0 = <0x10>;
+ mode-ums_mmc1 = <0x11>;
+ mode-ums_mmc2 = <0x12>;
+ };
};
/*
@@ -1641,7 +1842,7 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- hwlocks = <&hwspinlock 0>;
+ hwlocks = <&hsem 0 1>;
pins-are-numbered;
gpioa: gpio@50002000 {
@@ -1774,7 +1975,7 @@
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- hwlocks = <&hwspinlock 0>;
+ hwlocks = <&hsem 0 1>;
gpioz: gpio@54004000 {
gpio-controller;
@@ -1782,7 +1983,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
@@ -1804,13 +2005,18 @@
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
status = "disabled";
+
+ m4_system_resources {
+ compatible = "rproc-srm-core";
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi
index 1c1889b194..56ff32b4a4 100644
--- a/arch/arm/dts/stm32mp153.dtsi
+++ b/arch/arm/dts/stm32mp153.dtsi
@@ -10,9 +10,11 @@
cpus {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
device_type = "cpu";
reg = <1>;
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -22,6 +24,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+ timer {
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
@@ -30,7 +39,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@@ -43,7 +52,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index 54e73ccea4..1d82868f36 100644
--- a/arch/arm/dts/stm32mp157.dtsi
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -20,7 +20,8 @@
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ phy-dsi-supply = <&reg18>;
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 15a04ae927..a8573b94d2 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -15,7 +15,7 @@
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
- u-boot,mmc-env-partition = "fip";
+ u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
@@ -27,28 +27,16 @@
};
#endif
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
- /* only needed for boot with TF-A, witout FIP support */
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
reserved-memory {
u-boot,dm-spl;
optee@de000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
u-boot,dm-spl;
};
};
-#endif
led {
- red {
+ led-red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
@@ -61,6 +49,7 @@
status = "okay";
};
+#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
@@ -76,6 +65,10 @@
};
};
+&i2s2 {
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+};
+
&pmic {
u-boot,dm-pre-reloc;
};
@@ -172,6 +165,10 @@
};
};
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+};
+
&sdmmc1 {
u-boot,dm-spl;
};
@@ -185,6 +182,7 @@
u-boot,dm-spl;
};
};
+#endif
&uart4 {
u-boot,dm-pre-reloc;
@@ -202,6 +200,3 @@
};
};
-&usbotg_hs {
- u-boot,force-b-session-valid;
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 4c8be9c8eb..f48207dad5 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
@@ -15,13 +16,6 @@
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
- aliases {
- ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
new file mode 100644
index 0000000000..bbcd5053df
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2018
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ i2c3 = &i2c4;
+ };
+
+ config {
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
+ u-boot,mmc-env-partition = "u-boot-env";
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ led {
+ led-red {
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+
+#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
+ config {
+ u-boot,mmc-env-partition = "ssbl";
+ };
+#endif
+};
+
+#ifndef CONFIG_TFABOOT
+&clk_hse {
+ st,digbypass;
+};
+
+&i2c4 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&pmic {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+ frac = < 0x1a04 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-spl;
+};
+
+&sdmmc1_b4_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1_dir_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2 {
+ u-boot,dm-spl;
+};
+
+&sdmmc2_b4_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2_d47_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+#endif
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts
new file mode 100644
index 0000000000..0213ca5c17
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157A eval daughter";
+ compatible = "st,stm32mp157a-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
new file mode 100644
index 0000000000..e18d71dbef
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2018
+ */
+
+#include "stm32mp157c-ed1-u-boot.dtsi"
+
+/ {
+ aliases {
+ gpio26 = &stmfx_pinctrl;
+ i2c1 = &i2c2;
+ i2c4 = &i2c5;
+ pinctrl2 = &stmfx_pinctrl;
+ spi0 = &qspi;
+ usb0 = &usbotg_hs;
+ };
+};
+
+#ifndef CONFIG_TFABOOT
+&flash0 {
+ u-boot,dm-spl;
+};
+
+&qspi {
+ u-boot,dm-spl;
+};
+
+&qspi_clk_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi_bk1_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi_bk2_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+};
+
+&sai4 {
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+};
+#endif
diff --git a/arch/arm/dts/stm32mp157a-ev1.dts b/arch/arm/dts/stm32mp157a-ev1.dts
new file mode 100644
index 0000000000..a96fbc8406
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-ev1.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157a-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157A eval daughter on eval mother";
+ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
index d62c24d4ce..6e02b966cf 100644
--- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
@@ -53,6 +53,7 @@
u-boot,dm-pre-reloc;
};
+#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@@ -144,3 +145,4 @@
u-boot,dm-pre-reloc;
};
};
+#endif
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
index 836df6f746..b7c6d3e821 100644
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
@@ -25,6 +25,7 @@
u-boot,dm-pre-reloc;
};
+#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@@ -116,3 +117,4 @@
u-boot,dm-pre-reloc;
};
};
+#endif
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 2bc92ef3ae..a46941d6f7 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -11,21 +11,32 @@
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
+#include <dt-bindings/rtc/rtc-stm32.h>
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
- ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
serial3 = &usart2;
};
chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
};
};
@@ -35,7 +46,6 @@
&dsi {
status = "okay";
- phy-dsi-supply = <&reg18>;
ports {
port@0 {
@@ -53,7 +63,7 @@
};
};
- panel@0 {
+ panel_otm8009a: panel-otm8009a@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@@ -77,6 +87,9 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
+ panel = <&panel_otm8009a>;
+ vcc-supply = <&v3v3>;
+ iovcc-supply = <&v3v3>;
status = "okay";
};
};
@@ -92,10 +105,48 @@
};
};
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+};
+
+/* Wifi */
+&sdmmc2 {
+ arm,primecell-periphid = <0x10153180>;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
- status = "disabled";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3>;
+ vddio-supply = <&v3v3>;
+ };
};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 408abaf52f..44a689bbec 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -3,224 +3,4 @@
* Copyright : STMicroelectronics 2018
*/
-#include <dt-bindings/clock/stm32mp1-clksrc.h>
-#include "stm32mp15-u-boot.dtsi"
-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
-
-/ {
- aliases {
- i2c3 = &i2c4;
- };
-
- config {
- u-boot,boot-led = "heartbeat";
- u-boot,error-led = "error";
- u-boot,mmc-env-partition = "fip";
- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
-
-#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
- config {
- u-boot,mmc-env-partition = "ssbl";
- };
-#endif
-
-#ifdef CONFIG_STM32MP15x_STM32IMAGE
- /* only needed for boot with TF-A, witout FIP support */
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
- reserved-memory {
- optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
- };
-#endif
-
- led {
- red {
- label = "error";
- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- status = "okay";
- };
- };
-};
-
-&clk_hse {
- st,digbypass;
-};
-
-&i2c4 {
- u-boot,dm-pre-reloc;
-};
-
-&i2c4_pins_a {
- u-boot,dm-pre-reloc;
- pins {
- u-boot,dm-pre-reloc;
- };
-};
-
-&pmic {
- u-boot,dm-pre-reloc;
-};
-
-&rcc {
- st,clksrc = <
- CLK_MPU_PLL1P
- CLK_AXI_PLL2P
- CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
- CLK_RTC_LSE
- CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
- CLK_CKPER_HSE
- CLK_FMC_ACLK
- CLK_QSPI_ACLK
- CLK_ETH_DISABLED
- CLK_SDMMC12_PLL4P
- CLK_DSI_DSIPLL
- CLK_STGEN_HSE
- CLK_USBPHY_HSE
- CLK_SPI2S1_PLL3Q
- CLK_SPI2S23_PLL3Q
- CLK_SPI45_HSI
- CLK_SPI6_HSI
- CLK_I2C46_HSI
- CLK_SDMMC3_PLL4P
- CLK_USBO_USBPHY
- CLK_ADC_CKPER
- CLK_CEC_LSE
- CLK_I2C12_HSI
- CLK_I2C35_HSI
- CLK_UART1_HSI
- CLK_UART24_HSI
- CLK_UART35_HSI
- CLK_UART6_HSI
- CLK_UART78_HSI
- CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4R
- CLK_SAI1_PLL3Q
- CLK_SAI2_PLL3Q
- CLK_SAI3_PLL3Q
- CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
- CLK_RNG2_LSI
- CLK_LPTIM1_PCLK1
- CLK_LPTIM23_PCLK3
- CLK_LPTIM45_LSE
- >;
-
- /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
- pll2: st,pll@1 {
- compatible = "st,stm32mp1-pll";
- reg = <1>;
- cfg = < 2 65 1 0 0 PQR(1,1,1) >;
- frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
- };
-
- /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
- pll3: st,pll@2 {
- compatible = "st,stm32mp1-pll";
- reg = <2>;
- cfg = < 1 33 1 16 36 PQR(1,1,1) >;
- frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
- };
-
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
- pll4: st,pll@3 {
- compatible = "st,stm32mp1-pll";
- reg = <3>;
- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
- };
-};
-
-&sdmmc1 {
- u-boot,dm-spl;
-};
-
-&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
- u-boot,dm-spl;
- };
- pins2 {
- u-boot,dm-spl;
- };
-};
-
-&sdmmc1_dir_pins_a {
- u-boot,dm-spl;
- pins1 {
- u-boot,dm-spl;
- };
- pins2 {
- u-boot,dm-spl;
- };
-};
-
-&sdmmc2 {
- u-boot,dm-spl;
-};
-
-&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
- u-boot,dm-spl;
- };
- pins2 {
- u-boot,dm-spl;
- };
-};
-
-&sdmmc2_d47_pins_a {
- u-boot,dm-spl;
- pins {
- u-boot,dm-spl;
- };
-};
-
-&uart4 {
- u-boot,dm-pre-reloc;
-};
-
-&uart4_pins_a {
- u-boot,dm-pre-reloc;
- pins1 {
- u-boot,dm-pre-reloc;
- };
- pins2 {
- u-boot,dm-pre-reloc;
- /* pull-up on rx to avoid floating level */
- bias-pull-up;
- };
-};
+#include "stm32mp157a-ed1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 6e89f88a17..d2c24803b9 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
@@ -9,8 +9,7 @@
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
+#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter";
@@ -20,389 +19,18 @@
stdout-path = "serial0:115200n8";
};
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x40000000>;
- };
-
reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
-
- gpu_reserved: gpu@e8000000 {
- reg = <0xe8000000 0x8000000>;
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
no-map;
};
};
-
- aliases {
- serial0 = &uart4;
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
- pinctrl-0 = <&adc1_in6_pins_a>;
- pinctrl-names = "default";
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "disabled";
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- /* 16.5 ck_cycles sampling time */
- st,min-sample-time-nsecs = <400>;
- status = "okay";
- };
-};
-
-&cpu0{
- cpu-supply = <&vddcore>;
-};
-
-&cpu1{
- cpu-supply = <&vddcore>;
-};
-
-&crc1 {
- status = "okay";
};
&cryp1 {
status = "okay";
};
-&dac {
- pinctrl-names = "default";
- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
- vref-supply = <&vdda>;
- status = "disabled";
- dac1: dac@1 {
- status = "okay";
- };
- dac2: dac@2 {
- status = "okay";
- };
-};
-
-&dts {
- status = "okay";
-};
-
&gpu {
contiguous-area = <&gpu_reserved>;
};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&timers6 {
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- timer@5 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- status = "okay";
-};
-
-&usbotg_hs {
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index ec60486f41..cc028066ec 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -3,51 +3,4 @@
* Copyright : STMicroelectronics 2018
*/
-#include "stm32mp157c-ed1-u-boot.dtsi"
-
-/ {
- aliases {
- gpio26 = &stmfx_pinctrl;
- i2c1 = &i2c2;
- i2c4 = &i2c5;
- pinctrl2 = &stmfx_pinctrl;
- spi0 = &qspi;
- usb0 = &usbotg_hs;
- };
-};
-
-&flash0 {
- u-boot,dm-spl;
-};
-
-&qspi {
- u-boot,dm-spl;
-};
-
-&qspi_clk_pins_a {
- u-boot,dm-spl;
- pins {
- u-boot,dm-spl;
- };
-};
-
-&qspi_bk1_pins_a {
- u-boot,dm-spl;
- pins1 {
- u-boot,dm-spl;
- };
- pins2 {
- u-boot,dm-spl;
- };
-};
-
-&qspi_bk2_pins_a {
- u-boot,dm-spl;
- pins1 {
- u-boot,dm-spl;
- };
- pins2 {
- u-boot,dm-spl;
- };
-};
-
+#include "stm32mp157a-ev1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 5c5b1ddf7b..17434d903f 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -1,69 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157c-ed1.dts"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- ethernet0 = &ethernet0;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
};
};
@@ -75,35 +33,15 @@
};
};
-&cec {
- pinctrl-names = "default";
- pinctrl-0 = <&cec_pins_a>;
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dcmi_pins_a>;
- pinctrl-1 = <&dcmi_sleep_pins_a>;
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov5640_0>;
- bus-type = <5>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
&dsi {
- phy-dsi-supply = <&reg18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
port@0 {
reg = <0>;
dsi_in: endpoint {
@@ -119,7 +57,7 @@
};
};
- panel-dsi@0 {
+ panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@@ -135,106 +73,20 @@
};
};
-&ethernet0 {
- status = "okay";
- pinctrl-0 = <&ethernet0_rgmii_pins_a>;
- pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
&i2c2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- ov5640: camera@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- DOVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
- rotation = <180>;
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
status = "okay";
- port {
- ov5640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
- };
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick-pins {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- bias-pull-down;
- };
- };
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
};
};
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
&ltdc {
status = "okay";
@@ -245,133 +97,3 @@
};
};
};
-
-&m_can1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: mx66l51235l@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- flash1: mx66l51235l@1 {
- compatible = "jedec,spi-nor";
- reg = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "disabled";
-};
-
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-1 = <&pwm2_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_b>;
- pinctrl-1 = <&usart3_sleep_pins_b>;
- pinctrl-2 = <&usart3_idle_pins_b>;
- /*
- * HW flow control USART3_RTS is optional, and isn't default wired to
- * the connector. SB23 needs to be soldered in order to use it, and R77
- * (ETH_CLK) should be removed.
- */
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index 4ff848350d..8ae679bf90 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -13,9 +13,11 @@
};
};
+#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
+#endif
&i2c2 {
u-boot,dm-pre-reloc;
@@ -32,6 +34,7 @@
u-boot,dm-pre-reloc;
};
+#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@@ -144,3 +147,4 @@
u-boot,dm-spl;
};
};
+#endif
diff --git a/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
new file mode 100644
index 0000000000..4f9b7a99ce
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157a-dk1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
new file mode 100644
index 0000000000..99a4e0f9c4
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-dk1.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xd.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
+ compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
new file mode 100644
index 0000000000..70d9afc6b9
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157a-ed1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts
new file mode 100644
index 0000000000..18d8074376
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xd.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D eval daughter";
+ compatible = "st,stm32mp157d-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
new file mode 100644
index 0000000000..77168a4cdb
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157a-ev1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157d-ev1.dts b/arch/arm/dts/stm32mp157d-ev1.dts
new file mode 100644
index 0000000000..f19ca6ada2
--- /dev/null
+++ b/arch/arm/dts/stm32mp157d-ev1.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157d-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D eval daughter on eval mother";
+ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
new file mode 100644
index 0000000000..1bed79cdf4
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157c-dk2-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts
new file mode 100644
index 0000000000..3cd2e73034
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-dk2.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xf.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
+#include <dt-bindings/rtc/rtc-stm32.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
+ compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
+
+ aliases {
+ serial3 = &usart2;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cryp1 {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel_otm8009a: panel-otm8009a@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ touchscreen@38 {
+ compatible = "focaltech,ft6236";
+ reg = <0x38>;
+ interrupts = <2 2>;
+ interrupt-parent = <&gpiof>;
+ interrupt-controller;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ panel = <&panel_otm8009a>;
+ vcc-supply = <&v3v3>;
+ iovcc-supply = <&v3v3>;
+ status = "okay";
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep1_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
+
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+};
+
+/* Wifi */
+&sdmmc2 {
+ arm,primecell-periphid = <0x10153180>;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
+ pinctrl-1 = <&usart2_sleep_pins_c>;
+ pinctrl-2 = <&usart2_idle_pins_c>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3>;
+ vddio-supply = <&v3v3>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
new file mode 100644
index 0000000000..2b8d2afd55
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157c-ed1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts
new file mode 100644
index 0000000000..bb3f8dfdcb
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-ed1.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xf.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157F eval daughter";
+ compatible = "st,stm32mp157f-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&cryp1 {
+ status = "okay";
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
new file mode 100644
index 0000000000..0e415a141d
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2019
+ */
+
+#include "stm32mp157c-ev1-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp157f-ev1.dts b/arch/arm/dts/stm32mp157f-ev1.dts
new file mode 100644
index 0000000000..b831f04532
--- /dev/null
+++ b/arch/arm/dts/stm32mp157f-ev1.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157f-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157F eval daughter on eval mother";
+ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi
new file mode 100644
index 0000000000..5ed7e594f4
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xa.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&cpu0_opp_table {
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi
index b06a55a2fa..67d38d1333 100644
--- a/arch/arm/dts/stm32mp15xc.dtsi
+++ b/arch/arm/dts/stm32mp15xc.dtsi
@@ -4,14 +4,16 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
+#include "stm32mp15xa.dtsi"
+
/ {
soc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi
new file mode 100644
index 0000000000..e2f8b1297c
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xd.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&cpu0_opp_table {
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x2>;
+ opp-suspend;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu-crit {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_alert: cpu-alert {
+ temperature = <95000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 1 1>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi
new file mode 100644
index 0000000000..f4a77bf9a4
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xf.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp15xd.dtsi"
+
+/ {
+ soc {
+ cryp1: cryp@54001000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54001000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 11bc247065..1ec4702585 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -50,15 +50,6 @@
};
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
@@ -131,6 +122,7 @@
};
};
+#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@@ -222,9 +214,14 @@
u-boot,dm-pre-reloc;
};
};
+#endif
&sdmmc1 {
u-boot,dm-spl;
+ st,use-ckin;
+ st,cmd-gpios = <&gpiod 2 0>;
+ st,ck-gpios = <&gpioc 12 0>;
+ st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
index 8b275e4950..c96eba99c5 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
@@ -19,8 +19,23 @@
};
};
+
+&ethernet0 {
+ mdio0 {
+ ethernet-phy@7 {
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <1000>;
+ };
+ };
+};
+
&sdmmc1 {
u-boot,dm-spl;
+ st,use-ckin;
+ st,cmd-gpios = <&gpiod 2 0>;
+ st,ck-gpios = <&gpioc 12 0>;
+ st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 9d3db20876..48a046ecc6 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -25,15 +25,6 @@
u-boot,dm-spl;
};
-&gpiof {
- snor-nwp {
- gpio-hog;
- gpios = <7 0>;
- output-high;
- line-name = "spi-nor-nwp";
- };
-};
-
&i2c4 {
u-boot,dm-pre-reloc;
};
@@ -70,6 +61,7 @@
};
};
+#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@@ -161,3 +153,4 @@
u-boot,dm-pre-reloc;
};
};
+#endif
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 68987f64c5..d5abbfd510 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -4,10 +4,19 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
+#include "stm32mp15-m4-srm.dtsi"
+#include "stm32mp15-m4-srm-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -42,6 +51,12 @@
no-map;
};
+ mcu_rsc_table: mcu_rsc_table@10048000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
@@ -58,6 +73,11 @@
reg = <0xd4000000 0x4000000>;
no-map;
};
+
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
};
led {
@@ -70,9 +90,9 @@
};
};
- sound {
+ sound: sound {
compatible = "audio-graph-card";
- label = "STM32MP1-DK";
+ label = "STM32MP15-DK";
routing =
"Playback" , "MCLK",
"Capture" , "MCLK",
@@ -92,11 +112,11 @@
&adc {
pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ pinctrl-0 = <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
- status = "disabled";
+ status = "okay";
adc1: adc@0 {
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
@@ -105,13 +125,13 @@
* Use arbitrary margin here (e.g. 5us).
*/
st,min-sample-time-nsecs = <5000>;
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 6 13 18 19>;
+ /* USB Type-C CC1 & CC2 */
+ st,adc-channels = <18 19>;
status = "okay";
};
adc2: adc@100 {
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 2 6 18 19>;
+ /* USB Type-C CC1 & CC2 */
+ st,adc-channels = <18 19>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
@@ -124,20 +144,28 @@
status = "okay";
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
&crc1 {
status = "okay";
};
-&dts {
- status = "okay";
+&dma1 {
+ sram = <&dma_pool>;
};
-&cpu0{
- cpu-supply = <&vddcore>;
+&dma2 {
+ sram = <&dma_pool>;
};
-&cpu1{
- cpu-supply = <&vddcore>;
+&dts {
+ status = "okay";
};
&ethernet0 {
@@ -148,6 +176,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
@@ -228,15 +258,15 @@
cs42l51_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_tx_endpoint>;
+ bitclock-master = <&cs42l51_tx_endpoint>;
};
cs42l51_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
- frame-master;
- bitclock-master;
+ frame-master = <&cs42l51_rx_endpoint>;
+ bitclock-master = <&cs42l51_rx_endpoint>;
};
};
};
@@ -257,7 +287,7 @@
stusb1600@28 {
compatible = "st,stusb1600";
reg = <0x28>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpioi>;
pinctrl-names = "default";
pinctrl-0 = <&stusb1600_pins_a>;
@@ -281,7 +311,7 @@
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
@@ -390,21 +420,21 @@
regulator-always-on;
};
- bst_out: boost {
+ bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
- };
+ };
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- };
+ };
- vbus_sw: pwr_sw2 {
+ vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
- };
+ };
};
onkey {
@@ -477,11 +507,12 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
+ wakeup-source;
status = "okay";
};
@@ -490,10 +521,6 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
-&rng1 {
- status = "okay";
-};
-
&rtc {
status = "okay";
};
@@ -509,8 +536,6 @@
sai2a: audio-controller@4400b004 {
#clock-cells = <0>;
dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
status = "okay";
sai2a_port: port {
@@ -568,6 +593,27 @@
status = "disabled";
};
+&spi4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi4_pins_b>;
+ pinctrl-1 = <&spi4_sleep_pins_b>;
+ status = "disabled";
+};
+
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&sram {
+ dma_pool: dma_pool@0 {
+ reg = <0x50000 0x10000>;
+ pool;
+ };
+};
+
&timers1 {
/* spare dmas for other usage */
/delete-property/dmas;
@@ -658,6 +704,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "okay";
};
@@ -666,6 +714,8 @@
pinctrl-0 = <&uart7_pins_c>;
pinctrl-1 = <&uart7_sleep_pins_c>;
pinctrl-2 = <&uart7_idle_pins_c>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
};
@@ -702,10 +752,36 @@
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active until all connected devices are suspended
+ * otherwise the hub will be powered off as soon as the v3v3 is disabled
+ * and it can disturb connected devices.
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&v3v3>;
+ };
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
&vrefbuf {
diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi
new file mode 100644
index 0000000000..db0f911353
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp15-m4-srm.dtsi"
+#include "stm32mp15-m4-srm-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xC0000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcu_rsc_table: mcu_rsc_table@10048000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ optee@fe000000 {
+ reg = <0xfe000000 0x2000000>;
+ no-map;
+ };
+ };
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led-blue {
+ label = "heartbeat";
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&adc {
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
+ pinctrl-0 = <&adc1_in6_pins_a>;
+ pinctrl-names = "default";
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ /* 16.5 ck_cycles sampling time */
+ st,min-sample-time-nsecs = <400>;
+ status = "okay";
+ };
+};
+
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
+&crc1 {
+ status = "okay";
+};
+
+&dac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ dac1: dac@1 {
+ status = "okay";
+ };
+ dac2: dac@2 {
+ status = "okay";
+ };
+};
+
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&hash1 {
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ wakeup-source;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
+&sram {
+ dma_pool: dma_pool@0 {
+ reg = <0x50000 0x10000>;
+ pool;
+ };
+};
+
+&timers6 {
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ timer@5 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&usbotg_hs {
+ vbus-supply = <&vbus_otg>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi
new file mode 100644
index 0000000000..fa453817aa
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/stm32-hdp.h>
+
+/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ serial1 = &usart3;
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ joystick {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&joystick_pins>;
+ pinctrl-names = "default";
+ button-0 {
+ label = "JoySel";
+ linux,code = <KEY_ENTER>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-1 {
+ label = "JoyDown";
+ linux,code = <KEY_DOWN>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-2 {
+ label = "JoyLeft";
+ linux,code = <KEY_LEFT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-3 {
+ label = "JoyRight";
+ linux,code = <KEY_RIGHT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-4 {
+ label = "JoyUp";
+ linux,code = <KEY_UP>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+
+ spdif_out_port: port {
+ spdif_out_endpoint: endpoint {
+ remote-endpoint = <&sai4a_endpoint>;
+ };
+ };
+ };
+
+ spdif_in: spdif-in {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dir";
+ status = "okay";
+
+ spdif_in_port: port {
+ spdif_in_endpoint: endpoint {
+ remote-endpoint = <&spdifrx_endpoint>;
+ };
+ };
+ };
+
+ sound: sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP15-EV";
+ routing =
+ "AIF1CLK" , "MCLK1",
+ "AIF2CLK" , "MCLK1",
+ "IN1LN" , "MICBIAS2",
+ "DMIC2DAT" , "MICBIAS1",
+ "DMIC1DAT" , "MICBIAS1";
+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port
+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>;
+ status = "okay";
+ };
+
+ dmic0: dmic-0 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic0";
+ status = "okay";
+
+ port {
+ dmic0_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint0>;
+ };
+ };
+ };
+
+ dmic1: dmic-1 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic1";
+ status = "okay";
+
+ port {
+ dmic1_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint1>;
+ };
+ };
+ };
+
+ dmic2: dmic-2 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic2";
+ status = "okay";
+
+ port {
+ dmic2_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint2>;
+ };
+ };
+ };
+
+ dmic3: dmic-3 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic3";
+ status = "okay";
+
+ port {
+ dmic3_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint3>;
+ };
+ };
+ };
+
+};
+
+&cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cec_pins_a>;
+ status = "okay";
+};
+
+&dcmi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_a>;
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov5640_0>;
+ bus-type = <5>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ pclk-max-frequency = <77000000>;
+ };
+ };
+};
+
+&dfsdm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dfsdm_clkout_pins_a
+ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>;
+ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a
+ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>;
+ spi-max-frequency = <2048000>;
+
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+ clock-names = "dfsdm", "audio";
+ status = "okay";
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <3>;
+ st,adc-channel-names = "dmic_u1";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm0: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm0 0>;
+ status = "okay";
+
+ dfsdm0_port: port {
+ dfsdm_endpoint0: endpoint {
+ remote-endpoint = <&dmic0_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <0>;
+ st,adc-channel-names = "dmic_u2";
+ st,adc-channel-types = "SPI_F";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ st,adc-alt-channel = <1>;
+ status = "okay";
+
+ asoc_pdm1: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm1 0>;
+ status = "okay";
+
+ dfsdm1_port: port {
+ dfsdm_endpoint1: endpoint {
+ remote-endpoint = <&dmic1_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm2: filter@2 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <2>;
+ st,adc-channel-names = "dmic_u3";
+ st,adc-channel-types = "SPI_F";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,adc-alt-channel = <1>;
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm2: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm2 0>;
+ status = "okay";
+
+ dfsdm2_port: port {
+ dfsdm_endpoint2: endpoint {
+ remote-endpoint = <&dmic2_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm3: filter@3 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic_u4";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm3: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm3 0>;
+ status = "okay";
+
+ dfsdm3_port: port {
+ dfsdm_endpoint3: endpoint {
+ remote-endpoint = <&dmic3_endpoint>;
+ };
+ };
+ };
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+ pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&fmc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&fmc_pins_a>;
+ pinctrl-1 = <&fmc_sleep_pins_a>;
+ status = "okay";
+
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&hdp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
+ status = "disabled";
+
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
+ STM32_HDP(6, HDP6_GPOVAL_6) |
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-1 = <&i2c2_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ wm8994: wm8994@1b {
+ compatible = "wlf,wm8994";
+ #sound-dai-cells = <0>;
+ reg = <0x1b>;
+ status = "okay";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ DBVDD-supply = <&vdd>;
+ SPKVDD1-supply = <&vdd>;
+ SPKVDD2-supply = <&vdd>;
+ AVDD2-supply = <&v1v8>;
+ CPVDD-supply = <&v1v8>;
+
+ wlf,ldoena-always-driven;
+
+ clocks = <&sai2a>;
+ clock-names = "MCLK1";
+
+ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wm8994_tx_port: port@0 {
+ reg = <0>;
+ wm8994_tx_endpoint: endpoint {
+ remote-endpoint = <&sai2a_endpoint>;
+ };
+ };
+
+ wm8994_rx_port: port@1 {
+ reg = <1>;
+ wm8994_rx_endpoint: endpoint {
+ remote-endpoint = <&sai2b_endpoint>;
+ };
+ };
+ };
+ };
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&v2v8>;
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ rotation = <180>;
+ status = "okay";
+
+ port {
+ ov5640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ pclk-max-frequency = <77000000>;
+ };
+ };
+ };
+
+ stmfx: stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+ vdd-supply = <&v3v3>;
+
+ stmfx_pinctrl: pinctrl {
+ compatible = "st,stmfx-0300-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ goodix_pins: goodix {
+ pins = "gpio14";
+ bias-pull-down;
+ };
+
+ joystick_pins: joystick-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ bias-pull-down;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pmic: stpmic@33 {
+ regulators {
+ v1v8: ldo6 {
+ regulator-enable-ramp-delay = <300000>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash1: mx66l51235l@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>;
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&wm8994_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+ };
+
+ sai2b: audio-controller@4400b024 {
+ dma-names = "rx";
+ clocks = <&rcc SAI2_K>, <&sai2a>;
+ clock-names = "sai_ck", "MCLK";
+ status = "okay";
+
+ sai2b_port: port {
+ sai2b_endpoint: endpoint {
+ remote-endpoint = <&wm8994_rx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+ };
+};
+
+&sai4 {
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+
+ sai4a: audio-controller@50027004 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai4a_pins_a>;
+ pinctrl-1 = <&sai4a_sleep_pins_a>;
+ dma-names = "tx";
+ st,iec60958;
+ status = "okay";
+
+ sai4a_port: port {
+ sai4a_endpoint: endpoint {
+ remote-endpoint = <&spdif_out_endpoint>;
+ };
+ };
+ };
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
+&spdifrx {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spdifrx_pins_a>;
+ pinctrl-1 = <&spdifrx_sleep_pins_a>;
+ status = "okay";
+
+ spdifrx_port: port {
+ spdifrx_endpoint: endpoint {
+ remote-endpoint = <&spdif_in_endpoint>;
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_a>;
+ pinctrl-1 = <&spi1_sleep_pins_a>;
+ status = "disabled";
+};
+
+&timers2 {
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@1 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_b>;
+ pinctrl-1 = <&usart3_sleep_pins_b>;
+ pinctrl-2 = <&usart3_idle_pins_b>;
+ /*
+ * HW flow control USART3_RTS is optional, and isn't default wired to
+ * the connector. SB23 needs to be soldered in order to use it, and R77
+ * (ETH_CLK) should be removed.
+ */
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active until all connected devices are suspended
+ * otherwise the hub will be powered off as soon as the v3v3 is disabled
+ * and it can disturb connected devices.
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&v3v3>;
+ };
+};
+
+&usbphyc_port1 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+};
--
2.25.1
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