14428 lines
340 KiB
Diff
14428 lines
340 KiB
Diff
From 362734e9999cbf5ffe6a8b2f81d29a51c011feff Mon Sep 17 00:00:00 2001
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From: Romuald JEANNE <romuald.jeanne@st.com>
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Date: Fri, 5 Jun 2020 13:45:44 +0200
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Subject: [PATCH 4/5] ARM v2020.01-stm32mp-r1 DEVICETREE
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---
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arch/arm/dts/Makefile | 15 +-
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arch/arm/dts/stm32mp15-ddr.dtsi | 7 +-
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arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 49 +-
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arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 49 +-
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arch/arm/dts/stm32mp15-no-scmi.dtsi | 157 ++
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arch/arm/dts/stm32mp15-pinctrl.dtsi | 1426 +++++++++++++++
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arch/arm/dts/stm32mp15-u-boot.dtsi | 231 +++
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arch/arm/dts/stm32mp151.dtsi | 1997 ++++++++++++++++++++++
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arch/arm/dts/stm32mp153.dtsi | 54 +
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arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi | 524 ++++++
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arch/arm/dts/stm32mp157-m4-srm.dtsi | 442 +++++
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arch/arm/dts/stm32mp157-pinctrl.dtsi | 1036 -----------
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arch/arm/dts/stm32mp157-u-boot.dtsi | 153 --
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arch/arm/dts/stm32mp157.dtsi | 32 +
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arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 32 +-
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arch/arm/dts/stm32mp157a-avenger96.dts | 20 +-
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arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 56 +-
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arch/arm/dts/stm32mp157a-dk1.dts | 488 +-----
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arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 207 +++
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arch/arm/dts/stm32mp157a-ed1.dts | 52 +
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arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi | 69 +
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arch/arm/dts/stm32mp157a-ev1.dts | 86 +
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arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 6 -
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arch/arm/dts/stm32mp157c-dk2.dts | 122 +-
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arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 202 +--
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arch/arm/dts/stm32mp157c-ed1.dts | 324 +---
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arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 49 +-
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arch/arm/dts/stm32mp157c-ev1.dts | 300 +---
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arch/arm/dts/stm32mp157c.dtsi | 1592 -----------------
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arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157d-dk1.dts | 44 +
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arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157d-ed1.dts | 52 +
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arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157d-ev1.dts | 86 +
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arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157f-dk2.dts | 185 ++
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arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157f-ed1.dts | 56 +
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arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp157f-ev1.dts | 86 +
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arch/arm/dts/stm32mp157xaa-pinctrl.dtsi | 90 -
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arch/arm/dts/stm32mp157xab-pinctrl.dtsi | 62 -
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arch/arm/dts/stm32mp157xac-pinctrl.dtsi | 78 -
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arch/arm/dts/stm32mp157xad-pinctrl.dtsi | 62 -
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arch/arm/dts/stm32mp15xa.dtsi | 13 +
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arch/arm/dts/stm32mp15xc.dtsi | 20 +
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arch/arm/dts/stm32mp15xd.dtsi | 42 +
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arch/arm/dts/stm32mp15xf.dtsi | 20 +
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arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi | 6 +
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arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 88 +
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arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 249 +++
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arch/arm/dts/stm32mp15xx-dhcom.dtsi | 379 ++++
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arch/arm/dts/stm32mp15xx-dkx.dtsi | 768 +++++++++
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arch/arm/dts/stm32mp15xx-edx.dtsi | 408 +++++
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arch/arm/dts/stm32mp15xx-evx.dtsi | 680 ++++++++
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arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi | 85 +
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arch/arm/dts/stm32mp15xxab-pinctrl.dtsi | 57 +
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arch/arm/dts/stm32mp15xxac-pinctrl.dtsi | 73 +
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arch/arm/dts/stm32mp15xxad-pinctrl.dtsi | 57 +
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60 files changed, 9051 insertions(+), 4508 deletions(-)
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create mode 100644 arch/arm/dts/stm32mp15-no-scmi.dtsi
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create mode 100644 arch/arm/dts/stm32mp15-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp15-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp151.dtsi
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create mode 100644 arch/arm/dts/stm32mp153.dtsi
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create mode 100644 arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp157-m4-srm.dtsi
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delete mode 100644 arch/arm/dts/stm32mp157-pinctrl.dtsi
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delete mode 100644 arch/arm/dts/stm32mp157-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157.dtsi
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create mode 100644 arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157a-ed1.dts
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create mode 100644 arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157a-ev1.dts
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delete mode 100644 arch/arm/dts/stm32mp157c.dtsi
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create mode 100644 arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157d-dk1.dts
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create mode 100644 arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157d-ed1.dts
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create mode 100644 arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157d-ev1.dts
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create mode 100644 arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157f-dk2.dts
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create mode 100644 arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157f-ed1.dts
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create mode 100644 arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp157f-ev1.dts
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delete mode 100644 arch/arm/dts/stm32mp157xaa-pinctrl.dtsi
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delete mode 100644 arch/arm/dts/stm32mp157xab-pinctrl.dtsi
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delete mode 100644 arch/arm/dts/stm32mp157xac-pinctrl.dtsi
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delete mode 100644 arch/arm/dts/stm32mp157xad-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xa.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xc.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xd.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xf.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
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create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-dhcom.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-dkx.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-edx.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xx-evx.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
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create mode 100644 arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 0127a91..c3fd89b 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -823,12 +823,21 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
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dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
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-dtb-$(CONFIG_TARGET_STM32MP1) += \
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- stm32mp157a-dk1.dtb \
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+dtb-$(CONFIG_STM32MP15x) += \
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stm32mp157a-avenger96.dtb \
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+ stm32mp157a-dk1.dtb \
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+ stm32mp157a-ed1.dtb \
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+ stm32mp157a-ev1.dtb \
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stm32mp157c-dk2.dtb \
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stm32mp157c-ed1.dtb \
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- stm32mp157c-ev1.dtb
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+ stm32mp157c-ev1.dtb \
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+ stm32mp157d-dk1.dtb \
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+ stm32mp157d-ed1.dtb \
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+ stm32mp157d-ev1.dtb \
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+ stm32mp157f-dk2.dtb \
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+ stm32mp157f-ed1.dtb \
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+ stm32mp157f-ev1.dtb \
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+ stm32mp15xx-dhcom-pdk2.dtb
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
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index 479b700..cc604c0 100644
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--- a/arch/arm/dts/stm32mp15-ddr.dtsi
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+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
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@@ -5,7 +5,7 @@
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/ {
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soc {
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- ddr: ddr@5A003000 {
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+ ddr: ddr@5a003000 {
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-ddr";
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@@ -31,6 +31,7 @@
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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+#ifndef CONFIG_STM32MP1_TRUSTED
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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@@ -133,6 +134,7 @@
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DDR_MR3
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>;
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+#ifdef DDR_PHY_CAL_SKIP
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st,phy-cal = <
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DDR_DX0DLLCR
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DDR_DX0DQTR
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@@ -147,6 +149,9 @@
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DDR_DX3DQTR
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DDR_DX3DQSTR
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>;
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+#endif
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+
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+#endif
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status = "okay";
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};
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diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
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index 11e8f2b..c0fc1f7 100644
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--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
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+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
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@@ -1,24 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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+ */
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+
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+/*
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+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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+ * DDR type: DDR3 / DDR3L
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+ * DDR width: 16bits
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+ * DDR density: 4Gb
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+ * System frequency: 533000Khz
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+ * Relaxed Timing Mode: false
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+ * Address mapping type: RBC
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*
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- * STM32MP157C DK1/DK2 BOARD configuration
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- * 1x DDR3L 4Gb, 16-bit, 533MHz.
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- * Reference used NT5CC256M16DP-DI from NANYA
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- *
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- * DDR type / Platform DDR3/3L
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- * freq 533MHz
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- * width 16
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- * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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- * DDR density 4
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- * timing mode optimized
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- * Scheduling/QoS options : type = 2
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- * address mapping : RBC
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- * Tc > + 85C : N
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+ * Save Date: 2020.02.20, save Time: 18:45:20
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*/
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-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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-#define DDR_MEM_SPEED 533000
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-#define DDR_MEM_SIZE 0x20000000
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+
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+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
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+#define DDR_MEM_SPEED 533000
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+#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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@@ -50,15 +49,6 @@
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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-#define DDR_ADDRMAP1 0x00070707
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-#define DDR_ADDRMAP2 0x00000000
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-#define DDR_ADDRMAP3 0x1F000000
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-#define DDR_ADDRMAP4 0x00001F1F
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-#define DDR_ADDRMAP5 0x06060606
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-#define DDR_ADDRMAP6 0x0F060606
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-#define DDR_ADDRMAP9 0x00000000
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-#define DDR_ADDRMAP10 0x00000000
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-#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@@ -83,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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+#define DDR_ADDRMAP1 0x00070707
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+#define DDR_ADDRMAP2 0x00000000
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+#define DDR_ADDRMAP3 0x1F000000
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+#define DDR_ADDRMAP4 0x00001F1F
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+#define DDR_ADDRMAP5 0x06060606
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+#define DDR_ADDRMAP6 0x0F060606
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+#define DDR_ADDRMAP9 0x00000000
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+#define DDR_ADDRMAP10 0x00000000
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+#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
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index 4b70b60..fc226d2 100644
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--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
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+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
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@@ -1,24 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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|
/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
|
|
+ */
|
|
+
|
|
+/*
|
|
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
|
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+ * DDR type: DDR3 / DDR3L
|
|
+ * DDR width: 32bits
|
|
+ * DDR density: 8Gb
|
|
+ * System frequency: 533000Khz
|
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+ * Relaxed Timing Mode: false
|
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+ * Address mapping type: RBC
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*
|
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- * STM32MP157C ED1 BOARD configuration
|
|
- * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
|
|
- * Reference used NT5CC256M16DP-DI from NANYA
|
|
- *
|
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- * DDR type / Platform DDR3/3L
|
|
- * freq 533MHz
|
|
- * width 32
|
|
- * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
|
|
- * DDR density 8
|
|
- * timing mode optimized
|
|
- * Scheduling/QoS options : type = 2
|
|
- * address mapping : RBC
|
|
- * Tc > + 85C : N
|
|
+ * Save Date: 2020.02.20, save Time: 18:49:33
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*/
|
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-#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
|
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-#define DDR_MEM_SPEED 533000
|
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-#define DDR_MEM_SIZE 0x40000000
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+
|
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+#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
|
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+#define DDR_MEM_SPEED 533000
|
|
+#define DDR_MEM_SIZE 0x40000000
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|
|
|
#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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@@ -50,15 +49,6 @@
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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|
-#define DDR_ADDRMAP1 0x00080808
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-#define DDR_ADDRMAP2 0x00000000
|
|
-#define DDR_ADDRMAP3 0x00000000
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-#define DDR_ADDRMAP4 0x00001F1F
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-#define DDR_ADDRMAP5 0x07070707
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-#define DDR_ADDRMAP6 0x0F070707
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|
-#define DDR_ADDRMAP9 0x00000000
|
|
-#define DDR_ADDRMAP10 0x00000000
|
|
-#define DDR_ADDRMAP11 0x00000000
|
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@@ -83,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
|
|
+#define DDR_ADDRMAP1 0x00080808
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|
+#define DDR_ADDRMAP2 0x00000000
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|
+#define DDR_ADDRMAP3 0x00000000
|
|
+#define DDR_ADDRMAP4 0x00001F1F
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+#define DDR_ADDRMAP5 0x07070707
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+#define DDR_ADDRMAP6 0x0F070707
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+#define DDR_ADDRMAP9 0x00000000
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+#define DDR_ADDRMAP10 0x00000000
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+#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
|
|
#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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|
diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi
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new file mode 100644
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index 0000000..3bb96ab
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--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi
|
|
@@ -0,0 +1,157 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
|
|
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/ {
|
|
+
|
|
+ clocks {
|
|
+ clk_hse: clk-hse {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ };
|
|
+
|
|
+ clk_hsi: clk-hsi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <64000000>;
|
|
+ };
|
|
+
|
|
+ clk_lse: clk-lse {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ };
|
|
+
|
|
+ clk_lsi: clk-lsi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32000>;
|
|
+ };
|
|
+
|
|
+ clk_csi: clk-csi {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <4000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ cpu0: cpu@0 {
|
|
+ clocks = <&rcc CK_MPU>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@1 {
|
|
+ clocks = <&rcc CK_MPU>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ m_can1: can@4400e000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ m_can2: can@4400f000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ cryp1: cryp@54001000 {
|
|
+ clocks = <&rcc CRYP1>;
|
|
+ resets = <&rcc CRYP1_R>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mlahb {
|
|
+ m4_rproc: m4@10000000 {
|
|
+ resets = <&rcc MCU_R>;
|
|
+
|
|
+ m4_system_resources {
|
|
+ m4_cec: cec@40016000 {
|
|
+ clocks = <&rcc CEC_K>, <&rcc CK_LSE>;
|
|
+ };
|
|
+
|
|
+ m4_m_can1: can@4400e000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+
|
|
+ m4_m_can2: can@4400f000 {
|
|
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ /delete-node/ scmi-0;
|
|
+ /delete-node/ scmi-1;
|
|
+ };
|
|
+ /delete-node/ sram@2ffff000;
|
|
+ /delete-node/ mailbox-0;
|
|
+ /delete-node/ mailbox-1;
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ clocks = <&rcc CEC_K>, <&clk_lse>;
|
|
+};
|
|
+
|
|
+&ddrperfm {
|
|
+ clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
+};
|
|
+
|
|
+&gpioz {
|
|
+ clocks = <&rcc GPIOZ>;
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ clocks = <&rcc HASH1>;
|
|
+ resets = <&rcc HASH1_R>;
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ clocks = <&rcc I2C4_K>;
|
|
+ resets = <&rcc I2C4_R>;
|
|
+};
|
|
+
|
|
+&i2c6 {
|
|
+ clocks = <&rcc I2C6_K>;
|
|
+ resets = <&rcc I2C6_R>;
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
+};
|
|
+
|
|
+&mdma1 {
|
|
+ clocks = <&rcc MDMA>;
|
|
+ resets = <&rcc MDMA_R>;
|
|
+};
|
|
+
|
|
+&rcc {
|
|
+ compatible = "st,stm32mp1-rcc", "syscon";
|
|
+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ clocks = <&rcc RNG1_K>;
|
|
+ resets = <&rcc RNG1_R>;
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
+};
|
|
+
|
|
+&spi6 {
|
|
+ clocks = <&rcc SPI6_K>;
|
|
+ resets = <&rcc SPI6_R>;
|
|
+};
|
|
+
|
|
+&usart1 {
|
|
+ clocks = <&rcc USART1_K>;
|
|
+ resets = <&rcc USART1_R>;
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..b8e82ad
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
|
|
@@ -0,0 +1,1426 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
+
|
|
+&pinctrl {
|
|
+ adc1_in6_pins_a: adc1-in6 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ adc12_ain_pins_a: adc12-ain-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
|
|
+ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
|
|
+ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
|
|
+ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
|
|
+ <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_a: cec-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_sleep_a: cec-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_b: cec-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, AF5)>;
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cec_pins_sleep_b: cec-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dac_ch1_pins_a: dac-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dac_ch2_pins_a: dac-ch2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcmi_pins_a: dcmi-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet0_rgmii_pins_a: rgmii-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
|
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
|
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fmc_pins_a: fmc-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fmc_sleep_pins_a: fmc-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
|
|
+ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp0_pins_a: hdp0-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp0_pins_sleep_a: hdp0-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp6_pins_a: hdp6-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp6_pins_sleep_a: hdp6-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp7_pins_a: hdp7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdp7_pins_sleep_a: hdp7-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_a: i2c1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_sleep_a: i2c1-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_b: i2c1-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins_sleep_b: i2c1-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_a: i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_a: i2c2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_b1: i2c2-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_b1: i2c2-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c5_pins_a: i2c5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c5_pins_sleep_a: i2c5-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
|
|
+
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s2_pins_a: i2s2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2s2_pins_sleep_a: i2s2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_a: ltdc-a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_sleep_a: ltdc-a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_b: ltdc-b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ltdc_pins_sleep_b: ltdc-b-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m_can1_pins_a: m-can1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
|
|
+ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm1_pins_a: pwm1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm1_sleep_pins_a: pwm1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm2_pins_a: pwm2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm3_pins_a: pwm3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_pins_a: pwm4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_pins_b: pwm4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm4_sleep_pins_b: pwm4-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm5_pins_a: pwm5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm8_pins_a: pwm8-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm12_pins_a: pwm12-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
|
+ bias-pull-down;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm12_sleep_pins_a: pwm12-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_clk_pins_a: qspi-clk-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <3>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk1_pins_a: qspi-bk1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
+ bias-pull-up;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
|
|
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk2_pins_a: qspi-bk2-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
+ bias-pull-up;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
|
|
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2a_pins_a: sai2a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2a_sleep_pins_a: sai2a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_pins_a: sai2b-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_sleep_pins_a: sai2b-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
|
|
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_pins_b: sai2b-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b_sleep_pins_b: sai2b-3 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai4a_pins_a: sai4a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
|
|
+ slew-rate = <0>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai4a_sleep_pins_a: sai4a-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
|
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2{
|
|
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
|
|
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
|
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-disable;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
|
|
+ slew-rate = <1>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
|
|
+ slew-rate = <2>;
|
|
+ drive-push-pull;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ pins3 {
|
|
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
|
|
+ slew-rate = <1>;
|
|
+ drive-open-drain;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
|
|
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdifrx_pins_a: spdifrx-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdifrx_sleep_pins_a: spdifrx-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi2_pins_a: spi2-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
|
|
+ <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
|
|
+ <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <3>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi4_pins_a: spi4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi4_sleep_pins_a: spi4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
|
|
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi5_pins_a: spi5-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi5_sleep_pins_a: spi5-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
|
|
+ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ stusb1600_pins_a: stusb1600-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_pins_a: uart4-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_idle_pins_a: uart4-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_sleep_pins_a: uart4-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
|
|
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart4_pins_b: uart4-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_pins_a: uart7-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
|
|
+ <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
|
|
+ <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_pins_b: uart7-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_idle_pins_b: uart7-idle-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* USART7_TX */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7_sleep_pins_b: uart7-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
|
|
+ <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_pins_a: usart2-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <3>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_idle_pins_a: usart2-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart2_sleep_pins_a: usart2-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_pins_a: usart3-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_idle_pins_a: usart3-idle-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_sleep_pins_a: usart3-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_pins_b: usart3-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_idle_pins_b: usart3-idle-1 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart3_sleep_pins_b: usart3-sleep-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbotg_hs_pins_a: usbotg_hs-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
|
|
+ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ i2c2_pins_b2: i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_pins_sleep_b2: i2c2-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c4_pins_a: i2c4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
+ bias-disable;
|
|
+ drive-open-drain;
|
|
+ slew-rate = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c4_pins_sleep_a: i2c4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi1_pins_a: spi1-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <1>;
|
|
+ };
|
|
+
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi1_sleep_pins_a: spi1-sleep-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
|
|
+ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..823e281
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
|
|
@@ -0,0 +1,231 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2018
|
|
+ */
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ gpio0 = &gpioa;
|
|
+ gpio1 = &gpiob;
|
|
+ gpio2 = &gpioc;
|
|
+ gpio3 = &gpiod;
|
|
+ gpio4 = &gpioe;
|
|
+ gpio5 = &gpiof;
|
|
+ gpio6 = &gpiog;
|
|
+ gpio7 = &gpioh;
|
|
+ gpio8 = &gpioi;
|
|
+ gpio9 = &gpioj;
|
|
+ gpio10 = &gpiok;
|
|
+ gpio25 = &gpioz;
|
|
+ pinctrl0 = &pinctrl;
|
|
+ pinctrl1 = &pinctrl_z;
|
|
+ };
|
|
+
|
|
+ /* need PSCI for sysreset during board_f */
|
|
+ psci {
|
|
+ u-boot,dm-pre-proper;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&bsec {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioa {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpiob {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioc {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpiod {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioe {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpiof {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpiog {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioh {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioj {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpiok {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&gpioz {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+/* pre-reloc probe = reserve video frame buffer in video_reserve() */
|
|
+<dc {
|
|
+ u-boot,dm-pre-proper;
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&rcc {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_STM32MP1_TRUSTED
|
|
+&scmi0 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi0_clk {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi0_mbox {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi0_reset {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi0_shm {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi1 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi1_clk {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi1_mbox {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi1_shm {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&scmi_sram {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+#endif
|
|
+
|
|
+&sdmmc1 {
|
|
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
+};
|
|
+
|
|
+&sdmmc3 {
|
|
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
+};
|
|
+
|
|
+/* NO MORE USE SCMI SUPPORT for BASIC boot chain */
|
|
+#ifndef CONFIG_STM32MP1_TRUSTED
|
|
+
|
|
+#include "stm32mp15-no-scmi.dtsi"
|
|
+
|
|
+/ {
|
|
+ clocks {
|
|
+ u-boot,dm-pre-reloc;
|
|
+
|
|
+ clk_hse: clk-hse {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ clk_hsi: clk-hsi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ clk_lse: clk-lse {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ clk_lsi: clk-lsi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ clk_csi: clk-csi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reboot {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&clk_hse {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&clk_hsi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&clk_lse {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&clk_lsi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&clk_csi {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ u-boot,dm-spl;
|
|
+ opp-650000000 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ opp-800000000 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+#endif /* CONFIG_STM32MP1_TRUSTED */
|
|
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
|
|
new file mode 100644
|
|
index 0000000..c516e2e
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp151.dtsi
|
|
@@ -0,0 +1,1997 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/clock/stm32mp1-clks.h>
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/reset/stm32mp1-resets.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+
|
|
+
|
|
+/ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <0>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_MPU>;
|
|
+ clock-names = "cpu";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ nvmem-cells = <&part_number_otp>;
|
|
+ nvmem-cell-names = "part_number";
|
|
+ #cooling-cells = <2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpu0_opp_table: cpu0-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ compatible = "arm,cortex-a7-pmu";
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>;
|
|
+ interrupt-parent = <&intc>;
|
|
+ };
|
|
+
|
|
+ scmi_sram: sram@2ffff000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x2ffff000 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x2ffff000 0x1000>;
|
|
+
|
|
+ scmi0_shm: scmi_shm@0 {
|
|
+ reg = <0 0x80>;
|
|
+ };
|
|
+
|
|
+ scmi1_shm: scmi_shm@200 {
|
|
+ reg = <0x200 0x80>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ scmi0_mbox: mailbox-0 {
|
|
+ #mbox-cells = <0>;
|
|
+ compatible = "arm,smc-mbox";
|
|
+ arm,func-id = <0x82002000>;
|
|
+ };
|
|
+
|
|
+ scmi1_mbox: mailbox-1 {
|
|
+ #mbox-cells = <0>;
|
|
+ compatible = "arm,smc-mbox";
|
|
+ arm,func-id = <0x82002001>;
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ scmi0: scmi-0 {
|
|
+ compatible = "arm,scmi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mboxes = <&scmi0_mbox 0>;
|
|
+ mbox-names = "txrx";
|
|
+ shmem = <&scmi0_shm>;
|
|
+
|
|
+ scmi0_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+ scmi0_reset: protocol@16 {
|
|
+ reg = <0x16>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ scmi1: scmi-1 {
|
|
+ compatible = "arm,scmi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ mboxes = <&scmi1_mbox 0>;
|
|
+ mbox-names = "txrx";
|
|
+ shmem = <&scmi1_shm>;
|
|
+
|
|
+ scmi1_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ optee: optee {
|
|
+ compatible = "linaro,optee-tz";
|
|
+ method = "smc";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ psci {
|
|
+ compatible = "arm,psci-1.0";
|
|
+ method = "smc";
|
|
+ };
|
|
+
|
|
+ intc: interrupt-controller@a0021000 {
|
|
+ compatible = "arm,cortex-a7-gic";
|
|
+ #interrupt-cells = <3>;
|
|
+ interrupt-controller;
|
|
+ reg = <0xa0021000 0x1000>,
|
|
+ <0xa0022000 0x2000>;
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv7-timer";
|
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
+ interrupt-parent = <&intc>;
|
|
+ always-on;
|
|
+ };
|
|
+
|
|
+ thermal-zones {
|
|
+ cpu_thermal: cpu-thermal {
|
|
+ polling-delay-passive = <0>;
|
|
+ polling-delay = <0>;
|
|
+ thermal-sensors = <&dts>;
|
|
+
|
|
+ trips {
|
|
+ cpu-crit {
|
|
+ temperature = <120000>;
|
|
+ hysteresis = <0>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ booster: regulator-booster {
|
|
+ compatible = "st,stm32mp1-booster";
|
|
+ st,syscfg = <&syscfg>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pm_domain {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32mp157c-pd";
|
|
+
|
|
+ pd_core_ret: core-ret-power-domain@1 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <1>;
|
|
+ #power-domain-cells = <0>;
|
|
+ label = "CORE-RETENTION";
|
|
+
|
|
+ pd_core: core-power-domain@2 {
|
|
+ reg = <2>;
|
|
+ #power-domain-cells = <0>;
|
|
+ label = "CORE";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reboot {
|
|
+ compatible = "syscon-reboot";
|
|
+ regmap = <&rcc>;
|
|
+ offset = <0x404>;
|
|
+ mask = <0x1>;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ interrupt-parent = <&intc>;
|
|
+ ranges;
|
|
+
|
|
+ sram: sram@10000000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x10000000 0x60000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x10000000 0x60000>;
|
|
+ };
|
|
+
|
|
+ timers2: timer@40000000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40000000 0x400>;
|
|
+ clocks = <&rcc TIM2_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 18 0x400 0x80000001>,
|
|
+ <&dmamux1 19 0x400 0x80000001>,
|
|
+ <&dmamux1 20 0x400 0x80000001>,
|
|
+ <&dmamux1 21 0x400 0x80000001>,
|
|
+ <&dmamux1 22 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@1 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers3: timer@40001000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40001000 0x400>;
|
|
+ clocks = <&rcc TIM3_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 23 0x400 0x80000001>,
|
|
+ <&dmamux1 24 0x400 0x80000001>,
|
|
+ <&dmamux1 25 0x400 0x80000001>,
|
|
+ <&dmamux1 26 0x400 0x80000001>,
|
|
+ <&dmamux1 27 0x400 0x80000001>,
|
|
+ <&dmamux1 28 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@2 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers4: timer@40002000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40002000 0x400>;
|
|
+ clocks = <&rcc TIM4_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 29 0x400 0x80000001>,
|
|
+ <&dmamux1 30 0x400 0x80000001>,
|
|
+ <&dmamux1 31 0x400 0x80000001>,
|
|
+ <&dmamux1 32 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@3 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers5: timer@40003000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40003000 0x400>;
|
|
+ clocks = <&rcc TIM5_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 55 0x400 0x80000001>,
|
|
+ <&dmamux1 56 0x400 0x80000001>,
|
|
+ <&dmamux1 57 0x400 0x80000001>,
|
|
+ <&dmamux1 58 0x400 0x80000001>,
|
|
+ <&dmamux1 59 0x400 0x80000001>,
|
|
+ <&dmamux1 60 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@4 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <4>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers6: timer@40004000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40004000 0x400>;
|
|
+ clocks = <&rcc TIM6_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 69 0x400 0x80000001>;
|
|
+ dma-names = "up";
|
|
+ status = "disabled";
|
|
+
|
|
+ timer@5 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <5>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers7: timer@40005000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40005000 0x400>;
|
|
+ clocks = <&rcc TIM7_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 70 0x400 0x80000001>;
|
|
+ dma-names = "up";
|
|
+ status = "disabled";
|
|
+
|
|
+ timer@6 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers12: timer@40006000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40006000 0x400>;
|
|
+ clocks = <&rcc TIM12_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@11 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <11>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers13: timer@40007000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40007000 0x400>;
|
|
+ clocks = <&rcc TIM13_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@12 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <12>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers14: timer@40008000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x40008000 0x400>;
|
|
+ clocks = <&rcc TIM14_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@13 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <13>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lptimer1: timer@40009000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-lptimer";
|
|
+ reg = <0x40009000 0x400>;
|
|
+ clocks = <&rcc LPTIM1_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ trigger@0 {
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
+ reg = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-lptimer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi2: spi@4000b000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc SPI2_K>;
|
|
+ resets = <&rcc SPI2_R>;
|
|
+ dmas = <&dmamux1 39 0x400 0x01>,
|
|
+ <&dmamux1 40 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s2: audio-controller@4000b000 {
|
|
+ compatible = "st,stm32h7-i2s";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 39 0x400 0x01>,
|
|
+ <&dmamux1 40 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi3: spi@4000c000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc SPI3_K>;
|
|
+ resets = <&rcc SPI3_R>;
|
|
+ dmas = <&dmamux1 61 0x400 0x01>,
|
|
+ <&dmamux1 62 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s3: audio-controller@4000c000 {
|
|
+ compatible = "st,stm32h7-i2s";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 61 0x400 0x01>,
|
|
+ <&dmamux1 62 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spdifrx: audio-controller@4000d000 {
|
|
+ compatible = "st,stm32h7-spdifrx";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x4000d000 0x400>;
|
|
+ clocks = <&rcc SPDIF_K>;
|
|
+ clock-names = "kclk";
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 93 0x400 0x01>,
|
|
+ <&dmamux1 94 0x400 0x01>;
|
|
+ dma-names = "rx", "rx-ctrl";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usart2: serial@4000e000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x4000e000 0x400>;
|
|
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc USART2_K>;
|
|
+ resets = <&rcc USART2_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 43 0x400 0x5>,
|
|
+ <&dmamux1 44 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usart3: serial@4000f000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x4000f000 0x400>;
|
|
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc USART3_K>;
|
|
+ resets = <&rcc USART3_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 45 0x400 0x5>,
|
|
+ <&dmamux1 46 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@40010000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x40010000 0x400>;
|
|
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc UART4_K>;
|
|
+ resets = <&rcc UART4_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 63 0x400 0x5>,
|
|
+ <&dmamux1 64 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@40011000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x40011000 0x400>;
|
|
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc UART5_K>;
|
|
+ resets = <&rcc UART5_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 65 0x400 0x5>,
|
|
+ <&dmamux1 66 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@40012000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x40012000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc I2C1_K>;
|
|
+ resets = <&rcc I2C1_R>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&dmamux1 33 0x400 0x80000001>,
|
|
+ <&dmamux1 34 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@40013000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x40013000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc I2C2_K>;
|
|
+ resets = <&rcc I2C2_R>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&dmamux1 35 0x400 0x80000001>,
|
|
+ <&dmamux1 36 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@40014000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x40014000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc I2C3_K>;
|
|
+ resets = <&rcc I2C3_R>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&dmamux1 73 0x400 0x80000001>,
|
|
+ <&dmamux1 74 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c5: i2c@40015000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x40015000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc I2C5_K>;
|
|
+ resets = <&rcc I2C5_R>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&dmamux1 115 0x400 0x80000001>,
|
|
+ <&dmamux1 116 0x400 0x80000001>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ cec: cec@40016000 {
|
|
+ compatible = "st,stm32-cec";
|
|
+ reg = <0x40016000 0x400>;
|
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
|
|
+ clock-names = "cec", "hdmi-cec";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dac: dac@40017000 {
|
|
+ compatible = "st,stm32h7-dac-core";
|
|
+ reg = <0x40017000 0x400>;
|
|
+ clocks = <&rcc DAC12>;
|
|
+ clock-names = "pclk";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ dac1: dac@1 {
|
|
+ compatible = "st,stm32-dac";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dac2: dac@2 {
|
|
+ compatible = "st,stm32-dac";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart7: serial@40018000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x40018000 0x400>;
|
|
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc UART7_K>;
|
|
+ resets = <&rcc UART7_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 79 0x400 0x5>,
|
|
+ <&dmamux1 80 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart8: serial@40019000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x40019000 0x400>;
|
|
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc UART8_K>;
|
|
+ resets = <&rcc UART8_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 81 0x400 0x5>,
|
|
+ <&dmamux1 82 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timers1: timer@44000000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x44000000 0x400>;
|
|
+ clocks = <&rcc TIM1_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 11 0x400 0x80000001>,
|
|
+ <&dmamux1 12 0x400 0x80000001>,
|
|
+ <&dmamux1 13 0x400 0x80000001>,
|
|
+ <&dmamux1 14 0x400 0x80000001>,
|
|
+ <&dmamux1 15 0x400 0x80000001>,
|
|
+ <&dmamux1 16 0x400 0x80000001>,
|
|
+ <&dmamux1 17 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
+ "up", "trig", "com";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@0 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers8: timer@44001000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x44001000 0x400>;
|
|
+ clocks = <&rcc TIM8_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 47 0x400 0x80000001>,
|
|
+ <&dmamux1 48 0x400 0x80000001>,
|
|
+ <&dmamux1 49 0x400 0x80000001>,
|
|
+ <&dmamux1 50 0x400 0x80000001>,
|
|
+ <&dmamux1 51 0x400 0x80000001>,
|
|
+ <&dmamux1 52 0x400 0x80000001>,
|
|
+ <&dmamux1 53 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
+ "up", "trig", "com";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@7 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <7>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-timer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usart6: serial@44003000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x44003000 0x400>;
|
|
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc USART6_K>;
|
|
+ resets = <&rcc USART6_R>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ dmas = <&dmamux1 71 0x400 0x5>,
|
|
+ <&dmamux1 72 0x400 0x1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi1: spi@44004000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x44004000 0x400>;
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc SPI1_K>;
|
|
+ resets = <&rcc SPI1_R>;
|
|
+ dmas = <&dmamux1 37 0x400 0x01>,
|
|
+ <&dmamux1 38 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s1: audio-controller@44004000 {
|
|
+ compatible = "st,stm32h7-i2s";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x44004000 0x400>;
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 37 0x400 0x01>,
|
|
+ <&dmamux1 38 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi4: spi@44005000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x44005000 0x400>;
|
|
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc SPI4_K>;
|
|
+ resets = <&rcc SPI4_R>;
|
|
+ dmas = <&dmamux1 83 0x400 0x01>,
|
|
+ <&dmamux1 84 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timers15: timer@44006000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x44006000 0x400>;
|
|
+ clocks = <&rcc TIM15_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 105 0x400 0x80000001>,
|
|
+ <&dmamux1 106 0x400 0x80000001>,
|
|
+ <&dmamux1 107 0x400 0x80000001>,
|
|
+ <&dmamux1 108 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "up", "trig", "com";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@14 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <14>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers16: timer@44007000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x44007000 0x400>;
|
|
+ clocks = <&rcc TIM16_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 109 0x400 0x80000001>,
|
|
+ <&dmamux1 110 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "up";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ timer@15 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <15>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timers17: timer@44008000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-timers";
|
|
+ reg = <0x44008000 0x400>;
|
|
+ clocks = <&rcc TIM17_K>;
|
|
+ clock-names = "int";
|
|
+ dmas = <&dmamux1 111 0x400 0x80000001>,
|
|
+ <&dmamux1 112 0x400 0x80000001>;
|
|
+ dma-names = "ch1", "up";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ timer@16 {
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
+ reg = <16>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi5: spi@44009000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x44009000 0x400>;
|
|
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc SPI5_K>;
|
|
+ resets = <&rcc SPI5_R>;
|
|
+ dmas = <&dmamux1 85 0x400 0x01>,
|
|
+ <&dmamux1 86 0x400 0x01>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai1: sai@4400a000 {
|
|
+ compatible = "st,stm32h7-sai";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x4400a000 0x400>;
|
|
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
|
|
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ resets = <&rcc SAI1_R>;
|
|
+ status = "disabled";
|
|
+
|
|
+ sai1a: audio-controller@4400a004 {
|
|
+ #sound-dai-cells = <0>;
|
|
+
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
+ reg = <0x4 0x1c>;
|
|
+ clocks = <&rcc SAI1_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 87 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai1b: audio-controller@4400a024 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
+ reg = <0x24 0x1c>;
|
|
+ clocks = <&rcc SAI1_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 88 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2: sai@4400b000 {
|
|
+ compatible = "st,stm32h7-sai";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x4400b000 0x400>;
|
|
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
|
|
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ resets = <&rcc SAI2_R>;
|
|
+ status = "disabled";
|
|
+
|
|
+ sai2a: audio-controller@4400b004 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
+ reg = <0x4 0x1c>;
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 89 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai2b: audio-controller@4400b024 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
+ reg = <0x24 0x1c>;
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 90 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai3: sai@4400c000 {
|
|
+ compatible = "st,stm32h7-sai";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x4400c000 0x400>;
|
|
+ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
|
|
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ resets = <&rcc SAI3_R>;
|
|
+ status = "disabled";
|
|
+
|
|
+ sai3a: audio-controller@4400c004 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
+ reg = <0x04 0x1c>;
|
|
+ clocks = <&rcc SAI3_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 113 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai3b: audio-controller@4400c024 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
+ reg = <0x24 0x1c>;
|
|
+ clocks = <&rcc SAI3_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 114 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm: dfsdm@4400d000 {
|
|
+ compatible = "st,stm32mp1-dfsdm";
|
|
+ reg = <0x4400d000 0x800>;
|
|
+ clocks = <&rcc DFSDM_K>;
|
|
+ clock-names = "dfsdm";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ dfsdm0: filter@0 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <0>;
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 101 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfsdm1: filter@1 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <1>;
|
|
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 102 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfsdm2: filter@2 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <2>;
|
|
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 103 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfsdm3: filter@3 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <3>;
|
|
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 104 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfsdm4: filter@4 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <4>;
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 91 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dfsdm5: filter@5 {
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <5>;
|
|
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&dmamux1 92 0x400 0x01>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dma1: dma@48000000 {
|
|
+ compatible = "st,stm32-dma";
|
|
+ reg = <0x48000000 0x400>;
|
|
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc DMA1>;
|
|
+ resets = <&rcc DMA1_R>;
|
|
+ #dma-cells = <4>;
|
|
+ st,mem2mem;
|
|
+ dma-requests = <8>;
|
|
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
|
|
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
|
|
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
|
|
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
|
|
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
|
|
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
|
|
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
|
|
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
+ };
|
|
+
|
|
+ dma2: dma@48001000 {
|
|
+ compatible = "st,stm32-dma";
|
|
+ reg = <0x48001000 0x400>;
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc DMA2>;
|
|
+ resets = <&rcc DMA2_R>;
|
|
+ #dma-cells = <4>;
|
|
+ st,mem2mem;
|
|
+ dma-requests = <8>;
|
|
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
|
|
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
|
|
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
|
|
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
|
|
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
|
|
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
|
|
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
|
|
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
+ };
|
|
+
|
|
+ dmamux1: dma-router@48002000 {
|
|
+ compatible = "st,stm32h7-dmamux";
|
|
+ reg = <0x48002000 0x40>;
|
|
+ #dma-cells = <3>;
|
|
+ dma-requests = <128>;
|
|
+ dma-masters = <&dma1 &dma2>;
|
|
+ dma-channels = <16>;
|
|
+ clocks = <&rcc DMAMUX>;
|
|
+ resets = <&rcc DMAMUX_R>;
|
|
+ };
|
|
+
|
|
+ adc: adc@48003000 {
|
|
+ compatible = "st,stm32mp1-adc-core";
|
|
+ reg = <0x48003000 0x400>;
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
+ clock-names = "bus", "adc";
|
|
+ interrupt-controller;
|
|
+ st,syscfg = <&syscfg>;
|
|
+ #interrupt-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ adc1: adc@0 {
|
|
+ compatible = "st,stm32mp1-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <0x0>;
|
|
+ interrupt-parent = <&adc>;
|
|
+ interrupts = <0>;
|
|
+ dmas = <&dmamux1 9 0x400 0x80000001>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ adc2: adc@100 {
|
|
+ compatible = "st,stm32mp1-adc";
|
|
+ #io-channel-cells = <1>;
|
|
+ reg = <0x100>;
|
|
+ interrupt-parent = <&adc>;
|
|
+ interrupts = <1>;
|
|
+ dmas = <&dmamux1 10 0x400 0x80000001>;
|
|
+ dma-names = "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdmmc3: sdmmc@48004000 {
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cmd_irq";
|
|
+ clocks = <&rcc SDMMC3_K>;
|
|
+ clock-names = "apb_pclk";
|
|
+ resets = <&rcc SDMMC3_R>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbotg_hs: usb-otg@49000000 {
|
|
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
+ reg = <0x49000000 0x10000>;
|
|
+ clocks = <&rcc USBO_K>;
|
|
+ clock-names = "otg";
|
|
+ resets = <&rcc USBO_R>;
|
|
+ reset-names = "dwc2";
|
|
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ g-rx-fifo-size = <512>;
|
|
+ g-np-tx-fifo-size = <32>;
|
|
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
|
|
+ dr_mode = "otg";
|
|
+ usb33d-supply = <&usb33>;
|
|
+ power-domains = <&pd_core>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hsem: hwspinlock@4c000000 {
|
|
+ compatible = "st,stm32-hwspinlock";
|
|
+ #hwlock-cells = <2>;
|
|
+ reg = <0x4c000000 0x400>;
|
|
+ clocks = <&rcc HSEM>;
|
|
+ clock-names = "hsem";
|
|
+ };
|
|
+
|
|
+ ipcc: mailbox@4c001000 {
|
|
+ compatible = "st,stm32mp1-ipcc";
|
|
+ #mbox-cells = <1>;
|
|
+ reg = <0x4c001000 0x400>;
|
|
+ st,proc-id = <0>;
|
|
+ interrupts-extended =
|
|
+ <&exti 61 1>,
|
|
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rx", "tx";
|
|
+ clocks = <&rcc IPCC>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dcmi: dcmi@4c006000 {
|
|
+ compatible = "st,stm32-dcmi";
|
|
+ reg = <0x4c006000 0x400>;
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ resets = <&rcc CAMITF_R>;
|
|
+ clocks = <&rcc DCMI>;
|
|
+ clock-names = "mclk";
|
|
+ dmas = <&dmamux1 75 0x400 0xe0000001>;
|
|
+ dma-names = "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rcc: rcc@50000000 {
|
|
+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
|
|
+ reg = <0x50000000 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
+
|
|
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>,
|
|
+ <&scmi0_clk CK_SCMI0_HSI>,
|
|
+ <&scmi0_clk CK_SCMI0_CSI>,
|
|
+ <&scmi0_clk CK_SCMI0_LSE>,
|
|
+ <&scmi0_clk CK_SCMI0_LSI>;
|
|
+ };
|
|
+
|
|
+ pwr_regulators: pwr@50001000 {
|
|
+ compatible = "st,stm32mp1,pwr-reg";
|
|
+ reg = <0x50001000 0x10>;
|
|
+ st,tzcr = <&rcc 0x0 0x1>;
|
|
+
|
|
+ reg11: reg11 {
|
|
+ regulator-name = "reg11";
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ };
|
|
+
|
|
+ reg18: reg18 {
|
|
+ regulator-name = "reg18";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ };
|
|
+
|
|
+ usb33: usb33 {
|
|
+ regulator-name = "usb33";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwr_mcu: pwr_mcu@50001014 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x50001014 0x4>;
|
|
+ };
|
|
+
|
|
+ pwr_irq: pwr@50001020 {
|
|
+ compatible = "st,stm32mp1-pwr";
|
|
+ reg = <0x50001020 0x100>;
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+
|
|
+ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
|
|
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ exti: interrupt-controller@5000d000 {
|
|
+ compatible = "st,stm32mp1-exti", "syscon";
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x5000d000 0x400>;
|
|
+ hwlocks = <&hsem 1 1>;
|
|
+
|
|
+ /* exti_pwr is an extra interrupt controller used for
|
|
+ * EXTI 55 to 60. It's mapped on pwr interrupt
|
|
+ * controller.
|
|
+ */
|
|
+ exti_pwr: exti-pwr {
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ interrupt-parent = <&pwr_irq>;
|
|
+ st,irq-number = <6>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ syscfg: syscon@50020000 {
|
|
+ compatible = "st,stm32mp157-syscfg", "syscon";
|
|
+ reg = <0x50020000 0x400>;
|
|
+ clocks = <&rcc SYSCFG>;
|
|
+ };
|
|
+
|
|
+ lptimer2: timer@50021000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-lptimer";
|
|
+ reg = <0x50021000 0x400>;
|
|
+ clocks = <&rcc LPTIM2_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ trigger@1 {
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
+ reg = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ counter {
|
|
+ compatible = "st,stm32-lptimer-counter";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lptimer3: timer@50022000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32-lptimer";
|
|
+ reg = <0x50022000 0x400>;
|
|
+ clocks = <&rcc LPTIM3_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ trigger@2 {
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
+ reg = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lptimer4: timer@50023000 {
|
|
+ compatible = "st,stm32-lptimer";
|
|
+ reg = <0x50023000 0x400>;
|
|
+ clocks = <&rcc LPTIM4_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lptimer5: timer@50024000 {
|
|
+ compatible = "st,stm32-lptimer";
|
|
+ reg = <0x50024000 0x400>;
|
|
+ clocks = <&rcc LPTIM5_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+
|
|
+ pwm {
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vrefbuf: vrefbuf@50025000 {
|
|
+ compatible = "st,stm32-vrefbuf";
|
|
+ reg = <0x50025000 0x8>;
|
|
+ regulator-min-microvolt = <1500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ clocks = <&rcc VREF>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai4: sai@50027000 {
|
|
+ compatible = "st,stm32h7-sai";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x50027000 0x400>;
|
|
+ reg = <0x50027000 0x4>, <0x500273f0 0x10>;
|
|
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ resets = <&rcc SAI4_R>;
|
|
+ status = "disabled";
|
|
+
|
|
+ sai4a: audio-controller@50027004 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
+ reg = <0x04 0x1c>;
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 99 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sai4b: audio-controller@50027024 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
+ reg = <0x24 0x1c>;
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ dmas = <&dmamux1 100 0x400 0x01>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dts: thermal@50028000 {
|
|
+ compatible = "st,stm32-thermal";
|
|
+ reg = <0x50028000 0x100>;
|
|
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc TMPSENS>;
|
|
+ clock-names = "pclk";
|
|
+ #thermal-sensor-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hdp: hdp@5002a000 {
|
|
+ compatible = "st,stm32mp1-hdp";
|
|
+ reg = <0x5002a000 0x400>;
|
|
+ clocks = <&rcc HDP>;
|
|
+ clock-names = "hdp";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hash1: hash@54002000 {
|
|
+ compatible = "st,stm32f756-hash";
|
|
+ reg = <0x54002000 0x400>;
|
|
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HASH1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_HASH1>;
|
|
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
|
|
+ dma-names = "in";
|
|
+ dma-maxburst = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rng1: rng@54003000 {
|
|
+ compatible = "st,stm32-rng";
|
|
+ reg = <0x54003000 0x400>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_RNG1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_RNG1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mdma1: dma@58000000 {
|
|
+ compatible = "st,stm32h7-mdma";
|
|
+ reg = <0x58000000 0x1000>;
|
|
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc MDMA>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_MDMA>;
|
|
+ #dma-cells = <6>;
|
|
+ dma-channels = <32>;
|
|
+ dma-requests = <48>;
|
|
+ };
|
|
+
|
|
+ fmc: nand-controller@58002000 {
|
|
+ compatible = "st,stm32mp15-fmc2";
|
|
+ reg = <0x58002000 0x1000>,
|
|
+ <0x80000000 0x1000>,
|
|
+ <0x88010000 0x1000>,
|
|
+ <0x88020000 0x1000>,
|
|
+ <0x81000000 0x1000>,
|
|
+ <0x89010000 0x1000>,
|
|
+ <0x89020000 0x1000>;
|
|
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
|
|
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
|
|
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
|
|
+ dma-names = "tx", "rx", "ecc";
|
|
+ clocks = <&rcc FMC_K>;
|
|
+ resets = <&rcc FMC_R>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ qspi: spi@58003000 {
|
|
+ compatible = "st,stm32f469-qspi";
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
+ reg-names = "qspi", "qspi_mm";
|
|
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
|
|
+ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
|
|
+ dma-names = "tx", "rx";
|
|
+ clocks = <&rcc QSPI_K>;
|
|
+ resets = <&rcc QSPI_R>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc1: sdmmc@58005000 {
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
|
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cmd_irq";
|
|
+ clocks = <&rcc SDMMC1_K>;
|
|
+ clock-names = "apb_pclk";
|
|
+ resets = <&rcc SDMMC1_R>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc2: sdmmc@58007000 {
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
|
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "cmd_irq";
|
|
+ clocks = <&rcc SDMMC2_K>;
|
|
+ clock-names = "apb_pclk";
|
|
+ resets = <&rcc SDMMC2_R>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ max-frequency = <120000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ crc1: crc@58009000 {
|
|
+ compatible = "st,stm32f7-crc";
|
|
+ reg = <0x58009000 0x400>;
|
|
+ clocks = <&rcc CRC1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ stmmac_axi_config_0: stmmac-axi-config {
|
|
+ snps,wr_osr_lmt = <0x7>;
|
|
+ snps,rd_osr_lmt = <0x7>;
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ };
|
|
+
|
|
+ ethernet0: ethernet@5800a000 {
|
|
+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x5800a000 0x2000>;
|
|
+ reg-names = "stmmaceth";
|
|
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq",
|
|
+ "eth_wake_irq";
|
|
+ clock-names = "stmmaceth",
|
|
+ "mac-clk-tx",
|
|
+ "mac-clk-rx",
|
|
+ "ethstp";
|
|
+ clocks = <&rcc ETHMAC>,
|
|
+ <&rcc ETHTX>,
|
|
+ <&rcc ETHRX>,
|
|
+ <&rcc ETHSTP>;
|
|
+ st,syscon = <&syscfg 0x4>;
|
|
+ snps,mixed-burst;
|
|
+ snps,pbl = <2>;
|
|
+ snps,en-tx-lpi-clockgating;
|
|
+ snps,axi-config = <&stmmac_axi_config_0>;
|
|
+ snps,tso;
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbh_ohci: usbh-ohci@5800c000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x5800c000 0x1000>;
|
|
+ clocks = <&rcc USBH>;
|
|
+ resets = <&rcc USBH_R>;
|
|
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbh_ehci: usbh-ehci@5800d000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x5800d000 0x1000>;
|
|
+ clocks = <&rcc USBH>;
|
|
+ resets = <&rcc USBH_R>;
|
|
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ companion = <&usbh_ohci>;
|
|
+ power-domains = <&pd_core>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ltdc: display-controller@5a001000 {
|
|
+ compatible = "st,stm32-ltdc";
|
|
+ reg = <0x5a001000 0x400>;
|
|
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc LTDC_PX>;
|
|
+ clock-names = "lcd";
|
|
+ resets = <&rcc LTDC_R>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ iwdg2: watchdog@5a002000 {
|
|
+ compatible = "st,stm32mp1-iwdg";
|
|
+ reg = <0x5a002000 0x400>;
|
|
+ clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>;
|
|
+ clock-names = "pclk", "lsi";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbphyc: usbphyc@5a006000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "st,stm32mp1-usbphyc";
|
|
+ reg = <0x5a006000 0x1000>;
|
|
+ clocks = <&rcc USBPHY_K>;
|
|
+ resets = <&rcc USBPHY_R>;
|
|
+ vdda1v1-supply = <®11>;
|
|
+ vdda1v8-supply = <®18>;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbphyc_port0: usb-phy@0 {
|
|
+ #phy-cells = <0>;
|
|
+ reg = <0>;
|
|
+ };
|
|
+
|
|
+ usbphyc_port1: usb-phy@1 {
|
|
+ #phy-cells = <1>;
|
|
+ reg = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ddrperfm: perf@5a007000 {
|
|
+ compatible = "st,stm32-ddr-pmu";
|
|
+ reg = <0x5a007000 0x400>;
|
|
+ clocks = <&rcc DDRPERFM>, <&scmi0_clk CK_SCMI0_PLL2_R>;
|
|
+ clock-names = "bus", "ddr";
|
|
+ resets = <&rcc DDRPERFM_R>;
|
|
+ };
|
|
+
|
|
+ usart1: serial@5c000000 {
|
|
+ compatible = "st,stm32h7-uart";
|
|
+ reg = <0x5c000000 0x400>;
|
|
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_USART1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_USART1>;
|
|
+ wakeup-source;
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi6: spi@5c001000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "st,stm32h7-spi";
|
|
+ reg = <0x5c001000 0x400>;
|
|
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_SPI6>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_SPI6>;
|
|
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
|
|
+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@5c002000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x5c002000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_I2C4>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_I2C4>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
|
|
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rtc: rtc@5c004000 {
|
|
+ compatible = "st,stm32mp1-rtc";
|
|
+ reg = <0x5c004000 0x400>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_RTCAPB>,
|
|
+ <&scmi0_clk CK_SCMI0_RTC>;
|
|
+ clock-names = "pclk", "rtc_ck";
|
|
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ bsec: nvmem@5c005000 {
|
|
+ compatible = "st,stm32mp15-bsec";
|
|
+ reg = <0x5c005000 0x400>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ part_number_otp: part_number_otp@4 {
|
|
+ reg = <0x4 0x1>;
|
|
+ };
|
|
+ ts_cal1: calib@5c {
|
|
+ reg = <0x5c 0x2>;
|
|
+ };
|
|
+ ts_cal2: calib@5e {
|
|
+ reg = <0x5e 0x2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c6: i2c@5c009000 {
|
|
+ compatible = "st,stm32mp15-i2c";
|
|
+ reg = <0x5c009000 0x400>;
|
|
+ interrupt-names = "event", "error";
|
|
+ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_I2C6>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_I2C6>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
|
|
+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ power-domains = <&pd_core>;
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
|
+ wakeup-source;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ tamp: tamp@5c00a000 {
|
|
+ compatible = "simple-bus", "syscon", "simple-mfd";
|
|
+ reg = <0x5c00a000 0x400>;
|
|
+
|
|
+ reboot-mode {
|
|
+ compatible = "syscon-reboot-mode";
|
|
+ offset = <0x150>; /* reg20 */
|
|
+ mask = <0xff>;
|
|
+ mode-normal = <0>;
|
|
+ mode-fastboot = <0x1>;
|
|
+ mode-recovery = <0x2>;
|
|
+ mode-stm32cubeprogrammer = <0x3>;
|
|
+ mode-ums_mmc0 = <0x10>;
|
|
+ mode-ums_mmc1 = <0x11>;
|
|
+ mode-ums_mmc2 = <0x12>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ /*
|
|
+ * Break node order to solve dependency probe issue between
|
|
+ * pinctrl and exti.
|
|
+ */
|
|
+ pinctrl: pin-controller@50002000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "st,stm32mp157-pinctrl";
|
|
+ ranges = <0 0x50002000 0xa400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ st,syscfg = <&exti 0x60 0xff>;
|
|
+ hwlocks = <&hsem 0 1>;
|
|
+ pins-are-numbered;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x0 0x400>;
|
|
+ clocks = <&rcc GPIOA>;
|
|
+ st,bank-name = "GPIOA";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x1000 0x400>;
|
|
+ clocks = <&rcc GPIOB>;
|
|
+ st,bank-name = "GPIOB";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x2000 0x400>;
|
|
+ clocks = <&rcc GPIOC>;
|
|
+ st,bank-name = "GPIOC";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x3000 0x400>;
|
|
+ clocks = <&rcc GPIOD>;
|
|
+ st,bank-name = "GPIOD";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x4000 0x400>;
|
|
+ clocks = <&rcc GPIOE>;
|
|
+ st,bank-name = "GPIOE";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x5000 0x400>;
|
|
+ clocks = <&rcc GPIOF>;
|
|
+ st,bank-name = "GPIOF";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x6000 0x400>;
|
|
+ clocks = <&rcc GPIOG>;
|
|
+ st,bank-name = "GPIOG";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x7000 0x400>;
|
|
+ clocks = <&rcc GPIOH>;
|
|
+ st,bank-name = "GPIOH";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x8000 0x400>;
|
|
+ clocks = <&rcc GPIOI>;
|
|
+ st,bank-name = "GPIOI";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpioj: gpio@5000b000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x9000 0x400>;
|
|
+ clocks = <&rcc GPIOJ>;
|
|
+ st,bank-name = "GPIOJ";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpiok: gpio@5000c000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0xa000 0x400>;
|
|
+ clocks = <&rcc GPIOK>;
|
|
+ st,bank-name = "GPIOK";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pinctrl_z: pin-controller-z@54004000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "st,stm32mp157-z-pinctrl";
|
|
+ ranges = <0 0x54004000 0x400>;
|
|
+ pins-are-numbered;
|
|
+ interrupt-parent = <&exti>;
|
|
+ st,syscfg = <&exti 0x60 0xff>;
|
|
+ hwlocks = <&hsem 0 1>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0 0x400>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_GPIOZ>;
|
|
+ st,bank-name = "GPIOZ";
|
|
+ st,bank-ioport = <11>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mlahb {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ dma-ranges = <0x00000000 0x38000000 0x10000>,
|
|
+ <0x10000000 0x10000000 0x60000>,
|
|
+ <0x30000000 0x30000000 0x60000>;
|
|
+
|
|
+ m4_rproc: m4@10000000 {
|
|
+ compatible = "st,stm32mp1-m4";
|
|
+ reg = <0x10000000 0x40000>,
|
|
+ <0x30000000 0x40000>,
|
|
+ <0x38000000 0x10000>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_MCU>;
|
|
+ st,syscfg-holdboot = <&rcc 0x10C 0x1>;
|
|
+ st,syscfg-tz = <&rcc 0x000 0x1>;
|
|
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
|
|
+ st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>;
|
|
+ st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
|
|
+ status = "disabled";
|
|
+
|
|
+ m4_system_resources {
|
|
+ compatible = "rproc-srm-core";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi
|
|
new file mode 100644
|
|
index 0000000..cf16b84
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp153.dtsi
|
|
@@ -0,0 +1,54 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp151.dtsi"
|
|
+
|
|
+/ {
|
|
+ cpus {
|
|
+ cpu1: cpu@1 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <1>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_MPU>;
|
|
+ clock-names = "cpu";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>, <&cpu1>;
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ m_can1: can@4400e000 {
|
|
+ compatible = "bosch,m_can";
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
+ reg-names = "m_can", "message_ram";
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "int0", "int1";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ m_can2: can@4400f000 {
|
|
+ compatible = "bosch,m_can";
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
+ reg-names = "m_can", "message_ram";
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "int0", "int1";
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi b/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..b4030e5
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157-m4-srm-pinctrl.dtsi
|
|
@@ -0,0 +1,524 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ m4_adc1_in6_pins_a: m4-adc1-in6 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 12, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_adc12_ain_pins_a: m4-adc12-ain-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
|
|
+ <STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
|
|
+ <STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
|
|
+ <STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
|
|
+ <STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_cec_pins_a: m4-cec-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_cec_pins_b: m4-cec-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 6, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dac_ch1_pins_a: m4-dac-ch1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dac_ch2_pins_a: m4-dac-ch2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 5, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dcmi_pins_a: m4-dcmi-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
|
|
+ <STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
|
|
+ <STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
|
|
+ <STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
|
|
+ <STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
|
|
+ <STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
|
|
+ <STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
|
|
+ <STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
|
|
+ <STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
|
|
+ <STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
|
|
+ <STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
|
|
+ <STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
|
|
+ <STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
|
|
+ <STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
|
|
+ <STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ethernet0_rgmii_pins_a: m4-rgmii-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
|
|
+ <STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
|
|
+ <STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
|
|
+ <STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
|
|
+ <STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
|
|
+ <STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
|
|
+ <STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
|
|
+ <STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
|
|
+ <STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
|
|
+ <STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
|
|
+ <STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
|
|
+ <STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
|
|
+ <STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_fmc_pins_a: m4-fmc-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
|
|
+ <STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
|
|
+ <STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
|
|
+ <STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
|
|
+ <STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
|
|
+ <STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
|
|
+ <STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
|
|
+ <STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
|
|
+ <STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
|
|
+ <STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
|
|
+ <STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
|
|
+ <STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
|
|
+ <STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
|
|
+ <STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp0_pins_a: m4-hdp0-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp6_pins_a: m4-hdp6-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_hdp7_pins_a: m4-hdp7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c1_pins_a: m4-i2c1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
|
|
+ <STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c2_pins_a: m4-i2c2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
|
|
+ <STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2c5_pins_a: m4-i2c5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
|
|
+ <STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_i2s2_pins_a: m4-i2s2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
|
|
+ <STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
|
|
+ <STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ltdc_pins_a: m4-ltdc-a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_ltdc_pins_b: m4-ltdc-b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
|
|
+ <STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
|
|
+ <STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
|
|
+ <STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
|
|
+ <STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
|
|
+ <STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
|
|
+ <STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
|
|
+ <STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
|
|
+ <STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
|
|
+ <STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
|
|
+ <STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
|
|
+ <STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
|
|
+ <STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
|
|
+ <STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
|
|
+ <STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
|
|
+ <STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
|
|
+ <STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
|
|
+ <STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
|
|
+ <STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
|
|
+ <STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
|
|
+ <STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
|
|
+ <STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
|
|
+ <STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
|
|
+ <STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
|
|
+ <STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
|
|
+ <STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
|
|
+ <STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
|
|
+ <STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_m_can1_pins_a: m4-m-can1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
|
|
+ <STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm1_pins_a: m4-pwm1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
|
|
+ <STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm2_pins_a: m4-pwm2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm3_pins_a: m4-pwm3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm4_pins_a: m4-pwm4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
|
|
+ <STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm4_pins_b: m4-pwm4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm5_pins_a: m4-pwm5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm8_pins_a: m4-pwm8-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_pwm12_pins_a: m4-pwm12-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
|
|
+ <STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
|
|
+ <STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
|
|
+ <STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
|
|
+ <STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
|
|
+ <STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
|
|
+ <STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
|
|
+ <STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
|
|
+ <STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_qspi_clk_pins_a: m4-qspi-clk-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2a_pins_a: m4-sai2a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
|
|
+ <STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
|
|
+ <STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
|
|
+ <STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2b_pins_a: m4-sai2b-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
|
|
+ <STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
|
|
+ <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai2b_pins_b: m4-sai2b-2 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sai4a_pins_a: m4-sai4a-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
|
|
+ <STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
|
|
+ <STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
|
|
+ <STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
|
|
+ <STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
|
|
+ <STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
|
|
+ <STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
|
|
+ <STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
|
|
+ <STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
|
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
|
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
|
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
|
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
|
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
|
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
|
|
+ <STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
|
|
+ <STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
|
|
+ <STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
|
|
+ <STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
|
|
+ <STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
|
|
+ <STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
|
|
+ <STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
|
|
+ <STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spdifrx_pins_a: m4-spdifrx-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi4_pins_a: m4-spi4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
|
|
+ <STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
|
|
+ <STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi5_pins_a: m4-spi5-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
|
|
+ <STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
|
|
+ <STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_stusb1600_pins_a: m4-stusb1600-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('I', 11, RSVD)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_uart4_pins_a: m4-uart4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
|
|
+ <STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_uart7_pins_a: m4-uart7-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
|
|
+ <STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart2_pins_a: m4-usart2-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
|
|
+ <STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
|
|
+ <STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
|
|
+ <STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart3_pins_a: m4-usart3-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usart3_pins_b: m4-usart3-1 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
|
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
|
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
|
+ <STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
|
|
+ <STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ m4_i2c4_pins_a: m4-i2c4-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
|
|
+ <STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ m4_spi1_pins_a: m4-spi1-0 {
|
|
+ pins {
|
|
+ pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
|
|
+ <STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
|
|
+ <STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157-m4-srm.dtsi b/arch/arm/dts/stm32mp157-m4-srm.dtsi
|
|
new file mode 100644
|
|
index 0000000..60454ae
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157-m4-srm.dtsi
|
|
@@ -0,0 +1,442 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&m4_rproc {
|
|
+ m4_system_resources {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ m4_timers2: timer@40000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40000000 0x400>;
|
|
+ clocks = <&rcc TIM2_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers3: timer@40001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40001000 0x400>;
|
|
+ clocks = <&rcc TIM3_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers4: timer@40002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40002000 0x400>;
|
|
+ clocks = <&rcc TIM4_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers5: timer@40003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40003000 0x400>;
|
|
+ clocks = <&rcc TIM5_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers6: timer@40004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40004000 0x400>;
|
|
+ clocks = <&rcc TIM6_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers7: timer@40005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40005000 0x400>;
|
|
+ clocks = <&rcc TIM7_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers12: timer@40006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40006000 0x400>;
|
|
+ clocks = <&rcc TIM12_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers13: timer@40007000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40007000 0x400>;
|
|
+ clocks = <&rcc TIM13_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers14: timer@40008000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40008000 0x400>;
|
|
+ clocks = <&rcc TIM14_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer1: timer@40009000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40009000 0x400>;
|
|
+ clocks = <&rcc LPTIM1_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi2: spi@4000b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ clocks = <&rcc SPI2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s2: audio-controller@4000b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000b000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi3: spi@4000c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ clocks = <&rcc SPI3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s3: audio-controller@4000c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000c000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spdifrx: audio-controller@4000d000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000d000 0x400>;
|
|
+ clocks = <&rcc SPDIF_K>;
|
|
+ clock-names = "kclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart2: serial@4000e000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000e000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <27 1>;
|
|
+ clocks = <&rcc USART2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart3: serial@4000f000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4000f000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <28 1>;
|
|
+ clocks = <&rcc USART3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart4: serial@40010000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40010000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <30 1>;
|
|
+ clocks = <&rcc UART4_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart5: serial@40011000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40011000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <31 1>;
|
|
+ clocks = <&rcc UART5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c1: i2c@40012000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40012000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <21 1>;
|
|
+ clocks = <&rcc I2C1_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c2: i2c@40013000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40013000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <22 1>;
|
|
+ clocks = <&rcc I2C2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c3: i2c@40014000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40014000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <23 1>;
|
|
+ clocks = <&rcc I2C3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2c5: i2c@40015000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40015000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <25 1>;
|
|
+ clocks = <&rcc I2C5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_cec: cec@40016000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40016000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <69 1>;
|
|
+ clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
|
|
+ clock-names = "cec", "hdmi-cec";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dac: dac@40017000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40017000 0x400>;
|
|
+ clocks = <&rcc DAC12>;
|
|
+ clock-names = "pclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart7: serial@40018000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40018000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <32 1>;
|
|
+ clocks = <&rcc UART7_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_uart8: serial@40019000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x40019000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <33 1>;
|
|
+ clocks = <&rcc UART8_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers1: timer@44000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44000000 0x400>;
|
|
+ clocks = <&rcc TIM1_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers8: timer@44001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44001000 0x400>;
|
|
+ clocks = <&rcc TIM8_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usart6: serial@44003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44003000 0x400>;
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <29 1>;
|
|
+ clocks = <&rcc USART6_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi1: spi@44004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44004000 0x400>;
|
|
+ clocks = <&rcc SPI1_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_i2s1: audio-controller@44004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44004000 0x400>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi4: spi@44005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44005000 0x400>;
|
|
+ clocks = <&rcc SPI4_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers15: timer@44006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44006000 0x400>;
|
|
+ clocks = <&rcc TIM15_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers16: timer@44007000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44007000 0x400>;
|
|
+ clocks = <&rcc TIM16_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_timers17: timer@44008000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44008000 0x400>;
|
|
+ clocks = <&rcc TIM17_K>;
|
|
+ clock-names = "int";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_spi5: spi@44009000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x44009000 0x400>;
|
|
+ clocks = <&rcc SPI5_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai1: sai@4400a000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400a000 0x4>;
|
|
+ clocks = <&rcc SAI1_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai2: sai@4400b000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400b000 0x4>;
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai3: sai@4400c000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400c000 0x4>;
|
|
+ clocks = <&rcc SAI3_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dfsdm: dfsdm@4400d000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400d000 0x800>;
|
|
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
|
|
+ clock-names = "dfsdm", "audio";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_m_can1: can@4400e000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_m_can2: can@4400f000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>;
|
|
+ clock-names = "hclk", "cclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dma1: dma@48000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48000000 0x400>;
|
|
+ clocks = <&rcc DMA1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dma2: dma@48001000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48001000 0x400>;
|
|
+ clocks = <&rcc DMA2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dmamux1: dma-router@48002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48002000 0x1c>;
|
|
+ clocks = <&rcc DMAMUX>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_adc: adc@48003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48003000 0x400>;
|
|
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
+ clock-names = "bus", "adc";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sdmmc3: sdmmc@48004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
+ clocks = <&rcc SDMMC3_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_usbotg_hs: usb-otg@49000000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x49000000 0x10000>;
|
|
+ clocks = <&rcc USBO_K>;
|
|
+ clock-names = "otg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_hash2: hash@4c002000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c002000 0x400>;
|
|
+ clocks = <&rcc HASH2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_rng2: rng@4c003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c003000 0x400>;
|
|
+ clocks = <&rcc RNG2_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_crc2: crc@4c004000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c004000 0x400>;
|
|
+ clocks = <&rcc CRC2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_cryp2: cryp@4c005000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c005000 0x400>;
|
|
+ clocks = <&rcc CRYP2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_dcmi: dcmi@4c006000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x4c006000 0x400>;
|
|
+ clocks = <&rcc DCMI>;
|
|
+ clock-names = "mclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer2: timer@50021000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50021000 0x400>;
|
|
+ clocks = <&rcc LPTIM2_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer3: timer@50022000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50022000 0x400>;
|
|
+ clocks = <&rcc LPTIM3_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer4: timer@50023000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50023000 0x400>;
|
|
+ clocks = <&rcc LPTIM4_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_lptimer5: timer@50024000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50024000 0x400>;
|
|
+ clocks = <&rcc LPTIM5_K>;
|
|
+ clock-names = "mux";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_sai4: sai@50027000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x50027000 0x4>;
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_qspi: qspi@58003000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
+ clocks = <&rcc QSPI_K>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ m4_ethernet0: ethernet@5800a000 {
|
|
+ compatible = "rproc-srm-dev";
|
|
+ reg = <0x5800a000 0x2000>;
|
|
+ clock-names = "stmmaceth",
|
|
+ "mac-clk-tx",
|
|
+ "mac-clk-rx",
|
|
+ "ethstp",
|
|
+ "syscfg-clk";
|
|
+ clocks = <&rcc ETHMAC>,
|
|
+ <&rcc ETHTX>,
|
|
+ <&rcc ETHRX>,
|
|
+ <&rcc ETHSTP>,
|
|
+ <&rcc SYSCFG>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 0d53396..0000000
|
|
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,1036 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
- */
|
|
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
-
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- compatible = "st,stm32mp157-pinctrl";
|
|
- ranges = <0 0x50002000 0xa400>;
|
|
- interrupt-parent = <&exti>;
|
|
- st,syscfg = <&exti 0x60 0xff>;
|
|
- hwlocks = <&hwspinlock 0>;
|
|
- pins-are-numbered;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x0 0x400>;
|
|
- clocks = <&rcc GPIOA>;
|
|
- st,bank-name = "GPIOA";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x1000 0x400>;
|
|
- clocks = <&rcc GPIOB>;
|
|
- st,bank-name = "GPIOB";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x2000 0x400>;
|
|
- clocks = <&rcc GPIOC>;
|
|
- st,bank-name = "GPIOC";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x3000 0x400>;
|
|
- clocks = <&rcc GPIOD>;
|
|
- st,bank-name = "GPIOD";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x4000 0x400>;
|
|
- clocks = <&rcc GPIOE>;
|
|
- st,bank-name = "GPIOE";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x5000 0x400>;
|
|
- clocks = <&rcc GPIOF>;
|
|
- st,bank-name = "GPIOF";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x6000 0x400>;
|
|
- clocks = <&rcc GPIOG>;
|
|
- st,bank-name = "GPIOG";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x7000 0x400>;
|
|
- clocks = <&rcc GPIOH>;
|
|
- st,bank-name = "GPIOH";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x8000 0x400>;
|
|
- clocks = <&rcc GPIOI>;
|
|
- st,bank-name = "GPIOI";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpioj: gpio@5000b000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x9000 0x400>;
|
|
- clocks = <&rcc GPIOJ>;
|
|
- st,bank-name = "GPIOJ";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpiok: gpio@5000c000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0xa000 0x400>;
|
|
- clocks = <&rcc GPIOK>;
|
|
- st,bank-name = "GPIOK";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
|
|
- <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_a: cec-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_sleep_a: cec-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_b: cec-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- cec_pins_sleep_b: cec-sleep-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
|
|
- };
|
|
- };
|
|
-
|
|
- dcmi_pins_a: dcmi-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
|
|
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
|
|
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
|
|
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
|
|
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
|
|
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
|
|
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
|
|
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
|
|
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
|
|
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
|
|
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
|
|
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
|
|
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
|
|
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
|
|
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- dcmi_sleep_pins_a: dcmi-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
|
|
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
|
|
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
|
|
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
|
|
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
|
|
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
|
|
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
|
|
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
|
|
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
|
|
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
|
|
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
|
|
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
|
|
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
|
|
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
|
|
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
|
|
- };
|
|
- };
|
|
-
|
|
- ethernet0_rgmii_pins_a: rgmii-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
|
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
|
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
|
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
|
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
|
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
|
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
|
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <2>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins3 {
|
|
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
|
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
|
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
|
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
|
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
|
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
|
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
|
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
|
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
|
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
|
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
|
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
|
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
|
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
|
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
|
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
|
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
|
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
|
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
|
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
|
- };
|
|
- };
|
|
-
|
|
- fmc_pins_a: fmc-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
|
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
|
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
|
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
|
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
|
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
|
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
|
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
|
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
|
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
|
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
|
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
|
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- fmc_sleep_pins_a: fmc-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
|
|
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
|
|
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
|
|
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
|
|
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
|
|
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
|
|
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
|
|
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
|
|
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
|
|
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
|
|
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
|
|
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
|
|
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
|
|
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_a: i2c1-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_sleep_a: i2c1-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_b: i2c1-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c1_pins_sleep_b: i2c1-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
|
|
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_a: i2c2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
|
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_a: i2c2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
|
|
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_b1: i2c2-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_b1: i2c2-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c5_pins_a: i2c5-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
|
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c5_pins_sleep_a: i2c5-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
|
|
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
|
|
-
|
|
- };
|
|
- };
|
|
-
|
|
- i2s2_pins_a: i2s2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
|
|
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
|
|
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- i2s2_pins_sleep_a: i2s2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
|
|
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
|
|
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_a: ltdc-a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
|
|
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_sleep_a: ltdc-a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
|
|
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_b: ltdc-b-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
|
|
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- ltdc_pins_sleep_b: ltdc-b-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
|
|
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
|
|
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
|
|
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
|
|
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
|
|
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
|
|
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
|
|
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
|
|
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
|
|
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
|
|
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
|
|
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
|
|
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
|
|
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
|
|
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
|
|
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
|
|
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
|
|
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
|
|
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
|
|
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
|
|
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
|
|
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
|
|
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
|
|
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
|
|
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
|
|
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
|
|
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
|
|
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
|
|
- };
|
|
- };
|
|
-
|
|
- m_can1_pins_a: m-can1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- m_can1_sleep_pins_a: m_can1-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
|
|
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
|
|
- };
|
|
- };
|
|
-
|
|
- pwm2_pins_a: pwm2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- pwm8_pins_a: pwm8-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- pwm12_pins_a: pwm12-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
|
- bias-pull-down;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_clk_pins_a: qspi-clk-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk1_pins_a: qspi-bk1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
- bias-pull-up;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
|
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
|
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
|
|
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
|
|
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk2_pins_a: qspi-bk2-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
- bias-pull-up;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- };
|
|
-
|
|
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
|
|
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
|
|
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
|
|
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
|
|
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2a_pins_a: sai2a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
|
|
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
|
|
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
|
|
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2a_sleep_pins_a: sai2a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
|
|
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
|
|
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
|
|
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_pins_a: sai2b-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
|
|
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
|
|
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_sleep_pins_a: sai2b-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
|
|
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
|
|
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
|
|
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_pins_b: sai2b-2 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b_sleep_pins_b: sai2b-3 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
|
|
- };
|
|
- };
|
|
-
|
|
- sai4a_pins_a: sai4a-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
|
|
- slew-rate = <0>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sai4a_sleep_pins_a: sai4a-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
|
|
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-disable;
|
|
- };
|
|
- pins2{
|
|
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
|
- slew-rate = <3>;
|
|
- drive-open-drain;
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
|
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
|
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
|
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
|
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
|
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
|
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
|
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
|
- slew-rate = <3>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- pins2{
|
|
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
|
|
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
|
|
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
|
|
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
|
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
- slew-rate = <2>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
|
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
|
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
|
- <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
|
- slew-rate = <2>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- pins3 {
|
|
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
|
- slew-rate = <1>;
|
|
- drive-open-drain;
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
|
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
|
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
|
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
|
- <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
|
- <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
|
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
|
- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
|
- <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
|
- slew-rate = <1>;
|
|
- drive-push-pull;
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
|
|
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
|
|
- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
|
|
- <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
|
|
- };
|
|
- };
|
|
-
|
|
- spdifrx_pins_a: spdifrx-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- spdifrx_sleep_pins_a: spdifrx-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
|
|
- };
|
|
- };
|
|
-
|
|
- spi2_pins_a: spi2-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
|
|
- <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
|
|
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <3>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- stusb1600_pins_a: stusb1600-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
|
|
- bias-pull-up;
|
|
- };
|
|
- };
|
|
-
|
|
- uart4_pins_a: uart4-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- uart4_pins_b: uart4-1 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
-
|
|
- uart7_pins_a: uart7-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
|
|
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
|
|
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- compatible = "st,stm32mp157-z-pinctrl";
|
|
- ranges = <0 0x54004000 0x400>;
|
|
- pins-are-numbered;
|
|
- interrupt-parent = <&exti>;
|
|
- st,syscfg = <&exti 0x60 0xff>;
|
|
- hwlocks = <&hwspinlock 0>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0 0x400>;
|
|
- clocks = <&rcc GPIOZ>;
|
|
- st,bank-name = "GPIOZ";
|
|
- st,bank-ioport = <11>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c2_pins_b2: i2c2-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c2_pins_sleep_b2: i2c2-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
|
|
- };
|
|
- };
|
|
-
|
|
- i2c4_pins_a: i2c4-0 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
- bias-disable;
|
|
- drive-open-drain;
|
|
- slew-rate = <0>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c4_pins_sleep_a: i2c4-1 {
|
|
- pins {
|
|
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
|
|
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
|
|
- };
|
|
- };
|
|
-
|
|
- spi1_pins_a: spi1-0 {
|
|
- pins1 {
|
|
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
|
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
|
- bias-disable;
|
|
- drive-push-pull;
|
|
- slew-rate = <1>;
|
|
- };
|
|
-
|
|
- pins2 {
|
|
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
|
- bias-disable;
|
|
- };
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
|
|
deleted file mode 100644
|
|
index 0d1d387..0000000
|
|
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
|
|
+++ /dev/null
|
|
@@ -1,153 +0,0 @@
|
|
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
-/*
|
|
- * Copyright : STMicroelectronics 2018
|
|
- */
|
|
-
|
|
-/ {
|
|
- aliases {
|
|
- gpio0 = &gpioa;
|
|
- gpio1 = &gpiob;
|
|
- gpio2 = &gpioc;
|
|
- gpio3 = &gpiod;
|
|
- gpio4 = &gpioe;
|
|
- gpio5 = &gpiof;
|
|
- gpio6 = &gpiog;
|
|
- gpio7 = &gpioh;
|
|
- gpio8 = &gpioi;
|
|
- gpio9 = &gpioj;
|
|
- gpio10 = &gpiok;
|
|
- gpio25 = &gpioz;
|
|
- pinctrl0 = &pinctrl;
|
|
- pinctrl1 = &pinctrl_z;
|
|
- };
|
|
-
|
|
- clocks {
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
- /* need PSCI for sysreset during board_f */
|
|
- psci {
|
|
- u-boot,dm-pre-proper;
|
|
- };
|
|
-
|
|
- reboot {
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
- soc {
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-};
|
|
-
|
|
-&bsec {
|
|
- u-boot,dm-pre-proper;
|
|
-};
|
|
-
|
|
-&clk_csi {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&clk_hsi {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&clk_hse {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&clk_lsi {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&clk_lse {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioa {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpiob {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioc {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpiod {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioe {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpiof {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpiog {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioh {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioi {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioj {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpiok {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&gpioz {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&iwdg2 {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-/* pre-reloc probe = reserve video frame buffer in video_reserve() */
|
|
-<dc {
|
|
- u-boot,dm-pre-proper;
|
|
-};
|
|
-
|
|
-&pinctrl {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&pinctrl_z {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&pwr {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&rcc {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
-};
|
|
-
|
|
-&sdmmc2 {
|
|
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
-};
|
|
-
|
|
-&sdmmc3 {
|
|
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
|
-};
|
|
-
|
|
-&usbotg_hs {
|
|
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
|
|
new file mode 100644
|
|
index 0000000..ce1d83a
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157.dtsi
|
|
@@ -0,0 +1,32 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp153.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ gpu: gpu@59000000 {
|
|
+ compatible = "vivante,gc";
|
|
+ reg = <0x59000000 0x800>;
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
|
|
+ clock-names = "bus" ,"core";
|
|
+ resets = <&rcc GPU_R>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dsi: dsi@5a000000 {
|
|
+ compatible = "st,stm32-dsi";
|
|
+ reg = <0x5a000000 0x800>;
|
|
+ phy-dsi-supply = <®18>;
|
|
+ clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>;
|
|
+ clock-names = "pclk", "ref", "px_clk";
|
|
+ resets = <&rcc DSI_R>;
|
|
+ reset-names = "apb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
|
|
index 1104a70..e885b6d 100644
|
|
--- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
|
|
+++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
|
|
@@ -7,7 +7,7 @@
|
|
*/
|
|
|
|
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
-#include "stm32mp157-u-boot.dtsi"
|
|
+#include "stm32mp15-u-boot.dtsi"
|
|
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
|
|
/ {
|
|
@@ -20,6 +20,7 @@
|
|
config {
|
|
u-boot,boot-led = "led1";
|
|
u-boot,error-led = "led4";
|
|
+ u-boot,mmc-env-partition = "ssbl";
|
|
};
|
|
};
|
|
|
|
@@ -91,7 +92,7 @@
|
|
CLK_UART6_HSI
|
|
CLK_UART78_HSI
|
|
CLK_SPDIF_PLL4P
|
|
- CLK_FDCAN_PLL4Q
|
|
+ CLK_FDCAN_PLL4R
|
|
CLK_SAI1_PLL3Q
|
|
CLK_SAI2_PLL3Q
|
|
CLK_SAI3_PLL3Q
|
|
@@ -103,15 +104,10 @@
|
|
CLK_LPTIM45_LSE
|
|
>;
|
|
|
|
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
|
|
- pll1: st,pll@0 {
|
|
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
|
- frac = < 0x800 >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
pll2: st,pll@1 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <1>;
|
|
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
frac = < 0x1400 >;
|
|
u-boot,dm-pre-reloc;
|
|
@@ -119,6 +115,8 @@
|
|
|
|
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
pll3: st,pll@2 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <2>;
|
|
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
frac = < 0x1a04 >;
|
|
u-boot,dm-pre-reloc;
|
|
@@ -126,6 +124,8 @@
|
|
|
|
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
|
|
pll4: st,pll@3 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <3>;
|
|
cfg = < 1 39 3 11 4 PQR(1,1,1) >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
@@ -137,14 +137,20 @@
|
|
|
|
&sdmmc1_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
- pins {
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc1_dir_pins_a {
|
|
u-boot,dm-spl;
|
|
- pins {
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
@@ -188,7 +194,3 @@
|
|
u-boot,force-b-session-valid;
|
|
hnp-srp-disable;
|
|
};
|
|
-
|
|
-&v3v3 {
|
|
- regulator-always-on;
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
|
|
index 5b15a4a..941963c 100644
|
|
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
|
|
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
|
|
@@ -6,9 +6,10 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xac-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
#include <dt-bindings/mfd/st,stpmic1.h>
|
|
|
|
/ {
|
|
@@ -252,14 +253,13 @@
|
|
regulator-name = "vbus_otg";
|
|
interrupts = <IT_OCP_OTG 0>;
|
|
interrupt-parent = <&pmic>;
|
|
- regulator-active-discharge;
|
|
};
|
|
|
|
vbus_sw: pwr_sw2 {
|
|
regulator-name = "vbus_sw";
|
|
interrupts = <IT_OCP_SWOUT 0>;
|
|
interrupt-parent = <&pmic>;
|
|
- regulator-active-discharge;
|
|
+ regulator-active-discharge = <1>;
|
|
};
|
|
};
|
|
|
|
@@ -282,11 +282,9 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&pwr {
|
|
- pwr-regulators {
|
|
- vdd-supply = <&vdd>;
|
|
- vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
- };
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
};
|
|
|
|
&rng1 {
|
|
@@ -302,7 +300,7 @@
|
|
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
- broken-cd;
|
|
+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
st,sig-dir;
|
|
st,neg-edge;
|
|
st,use-ckin;
|
|
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
|
|
index dcaab3e..62d7062 100644
|
|
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
|
|
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
|
|
@@ -4,7 +4,7 @@
|
|
*/
|
|
|
|
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
-#include "stm32mp157-u-boot.dtsi"
|
|
+#include "stm32mp15-u-boot.dtsi"
|
|
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
|
|
|
/ {
|
|
@@ -16,6 +16,7 @@
|
|
config {
|
|
u-boot,boot-led = "heartbeat";
|
|
u-boot,error-led = "error";
|
|
+ u-boot,mmc-env-partition = "ssbl";
|
|
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
|
|
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
|
@@ -27,34 +28,14 @@
|
|
default-state = "off";
|
|
status = "okay";
|
|
};
|
|
-
|
|
- blue {
|
|
- default-state = "on";
|
|
- };
|
|
};
|
|
};
|
|
|
|
&adc {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&adc12_usb_pwr_pins_a>;
|
|
- vdd-supply = <&vdd>;
|
|
- vdda-supply = <&vdd>;
|
|
- vref-supply = <&vrefbuf>;
|
|
status = "okay";
|
|
- adc1: adc@0 {
|
|
- /*
|
|
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
|
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
|
- * 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
|
- * Use arbitrary margin here (e.g. 5µs).
|
|
- */
|
|
- st,min-sample-time-nsecs = <5000>;
|
|
- /* ANA0, ANA1, USB Type-C CC1 & CC2 */
|
|
- st,adc-channels = <0 1 18 19>;
|
|
- status = "okay";
|
|
- };
|
|
};
|
|
|
|
+#ifndef CONFIG_STM32MP1_TRUSTED
|
|
&clk_hse {
|
|
st,digbypass;
|
|
};
|
|
@@ -70,6 +51,10 @@
|
|
};
|
|
};
|
|
|
|
+&i2s2 {
|
|
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+};
|
|
+
|
|
&pmic {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
@@ -127,7 +112,7 @@
|
|
CLK_UART6_HSI
|
|
CLK_UART78_HSI
|
|
CLK_SPDIF_PLL4P
|
|
- CLK_FDCAN_PLL4Q
|
|
+ CLK_FDCAN_PLL4R
|
|
CLK_SAI1_PLL3Q
|
|
CLK_SAI2_PLL3Q
|
|
CLK_SAI3_PLL3Q
|
|
@@ -139,15 +124,10 @@
|
|
CLK_LPTIM45_LSE
|
|
>;
|
|
|
|
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
|
|
- pll1: st,pll@0 {
|
|
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
|
- frac = < 0x800 >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
pll2: st,pll@1 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <1>;
|
|
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
frac = < 0x1400 >;
|
|
u-boot,dm-pre-reloc;
|
|
@@ -155,6 +135,8 @@
|
|
|
|
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
pll3: st,pll@2 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <2>;
|
|
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
frac = < 0x1a04 >;
|
|
u-boot,dm-pre-reloc;
|
|
@@ -162,21 +144,31 @@
|
|
|
|
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
|
pll4: st,pll@3 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <3>;
|
|
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+};
|
|
+
|
|
&sdmmc1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&sdmmc1_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
- pins {
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
+#endif
|
|
|
|
&uart4 {
|
|
u-boot,dm-pre-reloc;
|
|
@@ -197,4 +189,6 @@
|
|
&usbotg_hs {
|
|
u-boot,force-b-session-valid;
|
|
hnp-srp-disable;
|
|
+ /* TEMP: force peripheral for USB OTG */
|
|
+ dr_mode = "peripheral";
|
|
};
|
|
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
|
|
index 4652253..baff3f6 100644
|
|
--- a/arch/arm/dts/stm32mp157a-dk1.dts
|
|
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
|
|
@@ -6,11 +6,11 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xac-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include <dt-bindings/mfd/st,stpmic1.h>
|
|
-
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
|
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
|
|
@@ -18,491 +18,27 @@
|
|
aliases {
|
|
ethernet0 = ðernet0;
|
|
serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
- memory@c0000000 {
|
|
- reg = <0xc0000000 0x20000000>;
|
|
- };
|
|
-
|
|
reserved-memory {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges;
|
|
-
|
|
- mcuram2: mcuram2@10000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring0: vdev0vring0@10040000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10040000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring1: vdev0vring1@10041000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10041000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0buffer: vdev0buffer@10042000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10042000 0x4000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- mcuram: mcuram@30000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x30000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- retram: retram@38000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x38000000 0x10000>;
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
no-map;
|
|
};
|
|
|
|
- gpu_reserved: gpu@d4000000 {
|
|
- reg = <0xd4000000 0x4000000>;
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
no-map;
|
|
};
|
|
};
|
|
-
|
|
- led {
|
|
- compatible = "gpio-leds";
|
|
- blue {
|
|
- label = "heartbeat";
|
|
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
|
- linux,default-trigger = "heartbeat";
|
|
- default-state = "off";
|
|
- };
|
|
- };
|
|
-
|
|
- sound {
|
|
- compatible = "audio-graph-card";
|
|
- label = "STM32MP1-DK";
|
|
- routing =
|
|
- "Playback" , "MCLK",
|
|
- "Capture" , "MCLK",
|
|
- "MICL" , "Mic Bias";
|
|
- dais = <&sai2a_port &sai2b_port>;
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&cec {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&cec_pins_b>;
|
|
- pinctrl-1 = <&cec_pins_sleep_b>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-ðernet0 {
|
|
- status = "okay";
|
|
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- phy-mode = "rgmii-id";
|
|
- max-speed = <1000>;
|
|
- phy-handle = <&phy0>;
|
|
-
|
|
- mdio0 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "snps,dwmac-mdio";
|
|
- phy0: ethernet-phy@0 {
|
|
- reg = <0>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&gpu {
|
|
- contiguous-area = <&gpu_reserved>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&i2c1 {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&i2c1_pins_a>;
|
|
- pinctrl-1 = <&i2c1_pins_sleep_a>;
|
|
- i2c-scl-rising-time-ns = <100>;
|
|
- i2c-scl-falling-time-ns = <7>;
|
|
- status = "okay";
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- hdmi-transmitter@39 {
|
|
- compatible = "sil,sii9022";
|
|
- reg = <0x39>;
|
|
- iovcc-supply = <&v3v3_hdmi>;
|
|
- cvcc12-supply = <&v1v2_hdmi>;
|
|
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
|
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-parent = <&gpiog>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <<dc_pins_a>;
|
|
- pinctrl-1 = <<dc_pins_sleep_a>;
|
|
- status = "okay";
|
|
-
|
|
- ports {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- port@0 {
|
|
- reg = <0>;
|
|
- sii9022_in: endpoint {
|
|
- remote-endpoint = <<dc_ep0_out>;
|
|
- };
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- cs42l51: cs42l51@4a {
|
|
- compatible = "cirrus,cs42l51";
|
|
- reg = <0x4a>;
|
|
- #sound-dai-cells = <0>;
|
|
- VL-supply = <&v3v3>;
|
|
- VD-supply = <&v1v8_audio>;
|
|
- VA-supply = <&v1v8_audio>;
|
|
- VAHP-supply = <&v1v8_audio>;
|
|
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
|
- clocks = <&sai2a>;
|
|
- clock-names = "MCLK";
|
|
- status = "okay";
|
|
-
|
|
- cs42l51_port: port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- cs42l51_tx_endpoint: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&sai2a_endpoint>;
|
|
- frame-master;
|
|
- bitclock-master;
|
|
- };
|
|
-
|
|
- cs42l51_rx_endpoint: endpoint@1 {
|
|
- reg = <1>;
|
|
- remote-endpoint = <&sai2b_endpoint>;
|
|
- frame-master;
|
|
- bitclock-master;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c4_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- typec: stusb1600@28 {
|
|
- compatible = "st,stusb1600";
|
|
- reg = <0x28>;
|
|
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-parent = <&gpioi>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&stusb1600_pins_a>;
|
|
-
|
|
- status = "okay";
|
|
-
|
|
- typec_con: connector {
|
|
- compatible = "usb-c-connector";
|
|
- label = "USB-C";
|
|
- power-role = "sink";
|
|
- power-opmode = "default";
|
|
- };
|
|
- };
|
|
-
|
|
- pmic: stpmic@33 {
|
|
- compatible = "st,stpmic1";
|
|
- reg = <0x33>;
|
|
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- status = "okay";
|
|
-
|
|
- regulators {
|
|
- compatible = "st,stpmic1-regulators";
|
|
- ldo1-supply = <&v3v3>;
|
|
- ldo3-supply = <&vdd_ddr>;
|
|
- ldo6-supply = <&v3v3>;
|
|
- pwr_sw1-supply = <&bst_out>;
|
|
- pwr_sw2-supply = <&bst_out>;
|
|
-
|
|
- vddcore: buck1 {
|
|
- regulator-name = "vddcore";
|
|
- regulator-min-microvolt = <800000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_ddr: buck2 {
|
|
- regulator-name = "vdd_ddr";
|
|
- regulator-min-microvolt = <1350000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd: buck3 {
|
|
- regulator-name = "vdd";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- st,mask-reset;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- v3v3: buck4 {
|
|
- regulator-name = "v3v3";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- regulator-initial-mode = <0>;
|
|
- };
|
|
-
|
|
- v1v8_audio: ldo1 {
|
|
- regulator-name = "v1v8_audio";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO1 0>;
|
|
- };
|
|
-
|
|
- v3v3_hdmi: ldo2 {
|
|
- regulator-name = "v3v3_hdmi";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO2 0>;
|
|
- };
|
|
-
|
|
- vtt_ddr: ldo3 {
|
|
- regulator-name = "vtt_ddr";
|
|
- regulator-min-microvolt = <500000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_usb: ldo4 {
|
|
- regulator-name = "vdd_usb";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- interrupts = <IT_CURLIM_LDO4 0>;
|
|
- };
|
|
-
|
|
- vdda: ldo5 {
|
|
- regulator-name = "vdda";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO5 0>;
|
|
- regulator-boot-on;
|
|
- };
|
|
-
|
|
- v1v2_hdmi: ldo6 {
|
|
- regulator-name = "v1v2_hdmi";
|
|
- regulator-min-microvolt = <1200000>;
|
|
- regulator-max-microvolt = <1200000>;
|
|
- regulator-always-on;
|
|
- interrupts = <IT_CURLIM_LDO6 0>;
|
|
- };
|
|
-
|
|
- vref_ddr: vref_ddr {
|
|
- regulator-name = "vref_ddr";
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- bst_out: boost {
|
|
- regulator-name = "bst_out";
|
|
- interrupts = <IT_OCP_BOOST 0>;
|
|
- };
|
|
-
|
|
- vbus_otg: pwr_sw1 {
|
|
- regulator-name = "vbus_otg";
|
|
- interrupts = <IT_OCP_OTG 0>;
|
|
- };
|
|
-
|
|
- vbus_sw: pwr_sw2 {
|
|
- regulator-name = "vbus_sw";
|
|
- interrupts = <IT_OCP_SWOUT 0>;
|
|
- regulator-active-discharge;
|
|
- };
|
|
- };
|
|
-
|
|
- onkey {
|
|
- compatible = "st,stpmic1-onkey";
|
|
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
- interrupt-names = "onkey-falling", "onkey-rising";
|
|
- power-off-time-sec = <10>;
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- watchdog {
|
|
- compatible = "st,stpmic1-wdt";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&ipcc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&iwdg2 {
|
|
- timeout-sec = <32>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-<dc {
|
|
- status = "okay";
|
|
-
|
|
- port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- ltdc_ep0_out: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&sii9022_in>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&m4_rproc {
|
|
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
- <&vdev0vring1>, <&vdev0buffer>;
|
|
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
- mbox-names = "vq0", "vq1", "shutdown";
|
|
- interrupt-parent = <&exti>;
|
|
- interrupts = <68 1>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pwr {
|
|
- pwr-regulators {
|
|
- vdd-supply = <&vdd>;
|
|
- vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
- };
|
|
-};
|
|
-
|
|
-&rng1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rtc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sai2 {
|
|
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
- clock-names = "pclk", "x8k", "x11k";
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
|
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
|
- status = "okay";
|
|
-
|
|
- sai2a: audio-controller@4400b004 {
|
|
- #clock-cells = <0>;
|
|
- dma-names = "tx";
|
|
- clocks = <&rcc SAI2_K>;
|
|
- clock-names = "sai_ck";
|
|
- status = "okay";
|
|
-
|
|
- sai2a_port: port {
|
|
- sai2a_endpoint: endpoint {
|
|
- remote-endpoint = <&cs42l51_tx_endpoint>;
|
|
- format = "i2s";
|
|
- mclk-fs = <256>;
|
|
- dai-tdm-slot-num = <2>;
|
|
- dai-tdm-slot-width = <32>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- sai2b: audio-controller@4400b024 {
|
|
- dma-names = "rx";
|
|
- st,sync = <&sai2a 2>;
|
|
- clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
- clock-names = "sai_ck", "MCLK";
|
|
- status = "okay";
|
|
-
|
|
- sai2b_port: port {
|
|
- sai2b_endpoint: endpoint {
|
|
- remote-endpoint = <&cs42l51_rx_endpoint>;
|
|
- format = "i2s";
|
|
- mclk-fs = <256>;
|
|
- dai-tdm-slot-num = <2>;
|
|
- dai-tdm-slot-width = <32>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- pinctrl-names = "default", "opendrain", "sleep";
|
|
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
|
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
- broken-cd;
|
|
- st,neg-edge;
|
|
- bus-width = <4>;
|
|
- vmmc-supply = <&v3v3>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&uart4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&uart4_pins_a>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbh_ehci {
|
|
- phys = <&usbphyc_port0>;
|
|
- phy-names = "usb";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbotg_hs {
|
|
- dr_mode = "peripheral";
|
|
- phys = <&usbphyc_port1 0>;
|
|
- phy-names = "usb2-phy";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbphyc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbphyc_port0 {
|
|
- phy-supply = <&vdd_usb>;
|
|
-};
|
|
-
|
|
-&usbphyc_port1 {
|
|
- phy-supply = <&vdd_usb>;
|
|
};
|
|
|
|
-&vrefbuf {
|
|
- regulator-min-microvolt = <2500000>;
|
|
- regulator-max-microvolt = <2500000>;
|
|
- vdda-supply = <&vdd>;
|
|
+&optee {
|
|
status = "okay";
|
|
};
|
|
diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..0f163bc
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
|
|
@@ -0,0 +1,207 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2018
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
+#include "stm32mp15-u-boot.dtsi"
|
|
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ i2c3 = &i2c4;
|
|
+ mmc0 = &sdmmc1;
|
|
+ mmc1 = &sdmmc2;
|
|
+ };
|
|
+
|
|
+ config {
|
|
+ u-boot,boot-led = "heartbeat";
|
|
+ u-boot,error-led = "error";
|
|
+ u-boot,mmc-env-partition = "ssbl";
|
|
+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ red {
|
|
+ label = "error";
|
|
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
+ default-state = "off";
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+#ifndef CONFIG_STM32MP1_TRUSTED
|
|
+&clk_hse {
|
|
+ st,digbypass;
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&i2c4_pins_a {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ pins {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pmic {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&rcc {
|
|
+ st,clksrc = <
|
|
+ CLK_MPU_PLL1P
|
|
+ CLK_AXI_PLL2P
|
|
+ CLK_MCU_PLL3P
|
|
+ CLK_PLL12_HSE
|
|
+ CLK_PLL3_HSE
|
|
+ CLK_PLL4_HSE
|
|
+ CLK_RTC_LSE
|
|
+ CLK_MCO1_DISABLED
|
|
+ CLK_MCO2_DISABLED
|
|
+ >;
|
|
+
|
|
+ st,clkdiv = <
|
|
+ 1 /*MPU*/
|
|
+ 0 /*AXI*/
|
|
+ 0 /*MCU*/
|
|
+ 1 /*APB1*/
|
|
+ 1 /*APB2*/
|
|
+ 1 /*APB3*/
|
|
+ 1 /*APB4*/
|
|
+ 2 /*APB5*/
|
|
+ 23 /*RTC*/
|
|
+ 0 /*MCO1*/
|
|
+ 0 /*MCO2*/
|
|
+ >;
|
|
+
|
|
+ st,pkcs = <
|
|
+ CLK_CKPER_HSE
|
|
+ CLK_FMC_ACLK
|
|
+ CLK_QSPI_ACLK
|
|
+ CLK_ETH_DISABLED
|
|
+ CLK_SDMMC12_PLL4P
|
|
+ CLK_DSI_DSIPLL
|
|
+ CLK_STGEN_HSE
|
|
+ CLK_USBPHY_HSE
|
|
+ CLK_SPI2S1_PLL3Q
|
|
+ CLK_SPI2S23_PLL3Q
|
|
+ CLK_SPI45_HSI
|
|
+ CLK_SPI6_HSI
|
|
+ CLK_I2C46_HSI
|
|
+ CLK_SDMMC3_PLL4P
|
|
+ CLK_USBO_USBPHY
|
|
+ CLK_ADC_CKPER
|
|
+ CLK_CEC_LSE
|
|
+ CLK_I2C12_HSI
|
|
+ CLK_I2C35_HSI
|
|
+ CLK_UART1_HSI
|
|
+ CLK_UART24_HSI
|
|
+ CLK_UART35_HSI
|
|
+ CLK_UART6_HSI
|
|
+ CLK_UART78_HSI
|
|
+ CLK_SPDIF_PLL4P
|
|
+ CLK_FDCAN_PLL4R
|
|
+ CLK_SAI1_PLL3Q
|
|
+ CLK_SAI2_PLL3Q
|
|
+ CLK_SAI3_PLL3Q
|
|
+ CLK_SAI4_PLL3Q
|
|
+ CLK_RNG1_LSI
|
|
+ CLK_RNG2_LSI
|
|
+ CLK_LPTIM1_PCLK1
|
|
+ CLK_LPTIM23_PCLK3
|
|
+ CLK_LPTIM45_LSE
|
|
+ >;
|
|
+
|
|
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
+ pll2: st,pll@1 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <1>;
|
|
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
+ frac = < 0x1400 >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
+ pll3: st,pll@2 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <2>;
|
|
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
+ frac = < 0x1a04 >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
|
+ pll4: st,pll@3 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <3>;
|
|
+ cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&sdmmc1_b4_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1_dir_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&sdmmc2_b4_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc2_d47_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+#endif
|
|
+
|
|
+&uart4 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&uart4_pins_a {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ pins1 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ /* pull-up on rx to avoid floating level */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts
|
|
new file mode 100644
|
|
index 0000000..5dca956
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157a-ed1.dts
|
|
@@ -0,0 +1,52 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xa.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157A eval daughter";
|
|
+ compatible = "st,stm32mp157a-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..f634c4c
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157a-ev1-u-boot.dtsi
|
|
@@ -0,0 +1,69 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2018
|
|
+ */
|
|
+
|
|
+#include "stm32mp157c-ed1-u-boot.dtsi"
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ gpio26 = &stmfx_pinctrl;
|
|
+ i2c1 = &i2c2;
|
|
+ i2c4 = &i2c5;
|
|
+ pinctrl2 = &stmfx_pinctrl;
|
|
+ spi0 = &qspi;
|
|
+ usb0 = &usbotg_hs;
|
|
+ };
|
|
+};
|
|
+
|
|
+#ifndef CONFIG_STM32MP1_TRUSTED
|
|
+&flash0 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&qspi_clk_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi_bk1_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi_bk2_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+};
|
|
+
|
|
+&sai4 {
|
|
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+};
|
|
+
|
|
+#endif
|
|
+
|
|
+/* TEMP: force peripheral for USB OTG */
|
|
+&usbotg_hs {
|
|
+ dr_mode = "peripheral";
|
|
+};
|
|
+
|
|
diff --git a/arch/arm/dts/stm32mp157a-ev1.dts b/arch/arm/dts/stm32mp157a-ev1.dts
|
|
new file mode 100644
|
|
index 0000000..29ecd15
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157a-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157a-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157A eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
|
|
index 18ac1e3..06ef3a4 100644
|
|
--- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
|
|
+++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
|
|
@@ -4,9 +4,3 @@
|
|
*/
|
|
|
|
#include "stm32mp157a-dk1-u-boot.dtsi"
|
|
-
|
|
-&i2c1 {
|
|
- hdmi-transmitter@39 {
|
|
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
|
|
index 020ea0f..a7d5e86 100644
|
|
--- a/arch/arm/dts/stm32mp157c-dk2.dts
|
|
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
|
|
@@ -6,18 +6,55 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157a-dk1.dts"
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xc.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+#include <dt-bindings/rtc/rtc-stm32.h>
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
|
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ serial3 = &usart2;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
};
|
|
|
|
&dsi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
- phy-dsi-supply = <®18>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
@@ -38,7 +75,7 @@
|
|
};
|
|
};
|
|
|
|
- panel@0 {
|
|
+ panel_otm8009a: panel-otm8009a@0 {
|
|
compatible = "orisetech,otm8009a";
|
|
reg = <0>;
|
|
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
|
@@ -53,6 +90,31 @@
|
|
};
|
|
};
|
|
|
|
+&i2c1 {
|
|
+ touchscreen@2a {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x2a>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ touchscreen@38 {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x38>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
<dc {
|
|
status = "okay";
|
|
|
|
@@ -66,3 +128,57 @@
|
|
};
|
|
};
|
|
};
|
|
+
|
|
+&rtc {
|
|
+ st,lsco = <RTC_OUT2_RMP>;
|
|
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+/* Wifi */
|
|
+&sdmmc2 {
|
|
+ arm,primecell-periphid = <0x10153180>;
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ brcmf: bcrmf@1 {
|
|
+ reg = <1>;
|
|
+ compatible = "brcm,bcm4329-fmac";
|
|
+ };
|
|
+};
|
|
+
|
|
+/* Bluetooth */
|
|
+&usart2 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart2_pins_a>;
|
|
+ pinctrl-1 = <&usart2_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart2_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
|
|
+ compatible = "brcm,bcm43438-bt";
|
|
+ max-speed = <3000000>;
|
|
+ vbat-supply = <&v3v3>;
|
|
+ vddio-supply = <&v3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee_memory {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
|
|
index b2ac494..44a689b 100644
|
|
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
|
|
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
|
|
@@ -3,204 +3,4 @@
|
|
* Copyright : STMicroelectronics 2018
|
|
*/
|
|
|
|
-#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
-#include "stm32mp157-u-boot.dtsi"
|
|
-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
-
|
|
-/ {
|
|
- aliases {
|
|
- i2c3 = &i2c4;
|
|
- mmc0 = &sdmmc1;
|
|
- mmc1 = &sdmmc2;
|
|
- };
|
|
-
|
|
- config {
|
|
- u-boot,boot-led = "heartbeat";
|
|
- u-boot,error-led = "error";
|
|
- st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
- st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- led {
|
|
- red {
|
|
- label = "error";
|
|
- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
- default-state = "off";
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- blue {
|
|
- default-state = "on";
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&clk_hse {
|
|
- st,digbypass;
|
|
-};
|
|
-
|
|
-&i2c4 {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&i2c4_pins_a {
|
|
- u-boot,dm-pre-reloc;
|
|
- pins {
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-};
|
|
-
|
|
-&pmic {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&rcc {
|
|
- st,clksrc = <
|
|
- CLK_MPU_PLL1P
|
|
- CLK_AXI_PLL2P
|
|
- CLK_MCU_PLL3P
|
|
- CLK_PLL12_HSE
|
|
- CLK_PLL3_HSE
|
|
- CLK_PLL4_HSE
|
|
- CLK_RTC_LSE
|
|
- CLK_MCO1_DISABLED
|
|
- CLK_MCO2_DISABLED
|
|
- >;
|
|
-
|
|
- st,clkdiv = <
|
|
- 1 /*MPU*/
|
|
- 0 /*AXI*/
|
|
- 0 /*MCU*/
|
|
- 1 /*APB1*/
|
|
- 1 /*APB2*/
|
|
- 1 /*APB3*/
|
|
- 1 /*APB4*/
|
|
- 2 /*APB5*/
|
|
- 23 /*RTC*/
|
|
- 0 /*MCO1*/
|
|
- 0 /*MCO2*/
|
|
- >;
|
|
-
|
|
- st,pkcs = <
|
|
- CLK_CKPER_HSE
|
|
- CLK_FMC_ACLK
|
|
- CLK_QSPI_ACLK
|
|
- CLK_ETH_DISABLED
|
|
- CLK_SDMMC12_PLL4P
|
|
- CLK_DSI_DSIPLL
|
|
- CLK_STGEN_HSE
|
|
- CLK_USBPHY_HSE
|
|
- CLK_SPI2S1_PLL3Q
|
|
- CLK_SPI2S23_PLL3Q
|
|
- CLK_SPI45_HSI
|
|
- CLK_SPI6_HSI
|
|
- CLK_I2C46_HSI
|
|
- CLK_SDMMC3_PLL4P
|
|
- CLK_USBO_USBPHY
|
|
- CLK_ADC_CKPER
|
|
- CLK_CEC_LSE
|
|
- CLK_I2C12_HSI
|
|
- CLK_I2C35_HSI
|
|
- CLK_UART1_HSI
|
|
- CLK_UART24_HSI
|
|
- CLK_UART35_HSI
|
|
- CLK_UART6_HSI
|
|
- CLK_UART78_HSI
|
|
- CLK_SPDIF_PLL4P
|
|
- CLK_FDCAN_PLL4Q
|
|
- CLK_SAI1_PLL3Q
|
|
- CLK_SAI2_PLL3Q
|
|
- CLK_SAI3_PLL3Q
|
|
- CLK_SAI4_PLL3Q
|
|
- CLK_RNG1_LSI
|
|
- CLK_RNG2_LSI
|
|
- CLK_LPTIM1_PCLK1
|
|
- CLK_LPTIM23_PCLK3
|
|
- CLK_LPTIM45_LSE
|
|
- >;
|
|
-
|
|
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
|
|
- pll1: st,pll@0 {
|
|
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
|
- frac = < 0x800 >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
- /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
- pll2: st,pll@1 {
|
|
- cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
- frac = < 0x1400 >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
- /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
- pll3: st,pll@2 {
|
|
- cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
- frac = < 0x1a04 >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-
|
|
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
|
- pll4: st,pll@3 {
|
|
- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- u-boot,dm-spl;
|
|
-};
|
|
-
|
|
-&sdmmc1_b4_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc1_dir_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins1 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
- pins2 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc2 {
|
|
- u-boot,dm-spl;
|
|
-};
|
|
-
|
|
-&sdmmc2_b4_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins1 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
- pins2 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&sdmmc2_d47_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&uart4 {
|
|
- u-boot,dm-pre-reloc;
|
|
-};
|
|
-
|
|
-&uart4_pins_a {
|
|
- u-boot,dm-pre-reloc;
|
|
- pins1 {
|
|
- u-boot,dm-pre-reloc;
|
|
- };
|
|
- pins2 {
|
|
- u-boot,dm-pre-reloc;
|
|
- /* pull-up on rx to avoid floating level */
|
|
- bias-pull-up;
|
|
- };
|
|
-};
|
|
+#include "stm32mp157a-ed1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
|
|
index bc4d7e1..bf2d7e7 100644
|
|
--- a/arch/arm/dts/stm32mp157c-ed1.dts
|
|
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
|
|
@@ -1,14 +1,17 @@
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
-#include "stm32mp157c.dtsi"
|
|
-#include "stm32mp157xaa-pinctrl.dtsi"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xc.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C eval daughter";
|
|
@@ -18,78 +21,29 @@
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
- memory@c0000000 {
|
|
- device_type = "memory";
|
|
- reg = <0xC0000000 0x40000000>;
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
};
|
|
|
|
reserved-memory {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges;
|
|
-
|
|
- mcuram2: mcuram2@10000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10000000 0x40000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring0: vdev0vring0@10040000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10040000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0vring1: vdev0vring1@10041000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10041000 0x1000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- vdev0buffer: vdev0buffer@10042000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x10042000 0x4000>;
|
|
- no-map;
|
|
- };
|
|
-
|
|
- mcuram: mcuram@30000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x30000000 0x40000>;
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
no-map;
|
|
};
|
|
|
|
- retram: retram@38000000 {
|
|
- compatible = "shared-dma-pool";
|
|
- reg = <0x38000000 0x10000>;
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
no-map;
|
|
};
|
|
-
|
|
- gpu_reserved: gpu@e8000000 {
|
|
- reg = <0xe8000000 0x8000000>;
|
|
- no-map;
|
|
- };
|
|
- };
|
|
-
|
|
- aliases {
|
|
- serial0 = &uart4;
|
|
};
|
|
+};
|
|
|
|
- sd_switch: regulator-sd_switch {
|
|
- compatible = "regulator-gpio";
|
|
- regulator-name = "sd_switch";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- regulator-type = "voltage";
|
|
- regulator-always-on;
|
|
-
|
|
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
|
|
- gpios-states = <0>;
|
|
- states = <1800000 0x1 2900000 0x0>;
|
|
- };
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
};
|
|
|
|
-&dts {
|
|
- status = "okay";
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
};
|
|
|
|
&gpu {
|
|
@@ -97,242 +51,6 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&i2c4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c4_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
+&optee {
|
|
status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
-
|
|
- pmic: stpmic@33 {
|
|
- compatible = "st,stpmic1";
|
|
- reg = <0x33>;
|
|
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- status = "okay";
|
|
-
|
|
- regulators {
|
|
- compatible = "st,stpmic1-regulators";
|
|
- ldo1-supply = <&v3v3>;
|
|
- ldo2-supply = <&v3v3>;
|
|
- ldo3-supply = <&vdd_ddr>;
|
|
- ldo5-supply = <&v3v3>;
|
|
- ldo6-supply = <&v3v3>;
|
|
- pwr_sw1-supply = <&bst_out>;
|
|
- pwr_sw2-supply = <&bst_out>;
|
|
-
|
|
- vddcore: buck1 {
|
|
- regulator-name = "vddcore";
|
|
- regulator-min-microvolt = <800000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_ddr: buck2 {
|
|
- regulator-name = "vdd_ddr";
|
|
- regulator-min-microvolt = <1350000>;
|
|
- regulator-max-microvolt = <1350000>;
|
|
- regulator-always-on;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd: buck3 {
|
|
- regulator-name = "vdd";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- st,mask-reset;
|
|
- regulator-initial-mode = <0>;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- v3v3: buck4 {
|
|
- regulator-name = "v3v3";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- regulator-initial-mode = <0>;
|
|
- };
|
|
-
|
|
- vdda: ldo1 {
|
|
- regulator-name = "vdda";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO1 0>;
|
|
- };
|
|
-
|
|
- v2v8: ldo2 {
|
|
- regulator-name = "v2v8";
|
|
- regulator-min-microvolt = <2800000>;
|
|
- regulator-max-microvolt = <2800000>;
|
|
- interrupts = <IT_CURLIM_LDO2 0>;
|
|
- };
|
|
-
|
|
- vtt_ddr: ldo3 {
|
|
- regulator-name = "vtt_ddr";
|
|
- regulator-min-microvolt = <500000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- vdd_usb: ldo4 {
|
|
- regulator-name = "vdd_usb";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- interrupts = <IT_CURLIM_LDO4 0>;
|
|
- };
|
|
-
|
|
- vdd_sd: ldo5 {
|
|
- regulator-name = "vdd_sd";
|
|
- regulator-min-microvolt = <2900000>;
|
|
- regulator-max-microvolt = <2900000>;
|
|
- interrupts = <IT_CURLIM_LDO5 0>;
|
|
- regulator-boot-on;
|
|
- };
|
|
-
|
|
- v1v8: ldo6 {
|
|
- regulator-name = "v1v8";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- interrupts = <IT_CURLIM_LDO6 0>;
|
|
- };
|
|
-
|
|
- vref_ddr: vref_ddr {
|
|
- regulator-name = "vref_ddr";
|
|
- regulator-always-on;
|
|
- regulator-over-current-protection;
|
|
- };
|
|
-
|
|
- bst_out: boost {
|
|
- regulator-name = "bst_out";
|
|
- interrupts = <IT_OCP_BOOST 0>;
|
|
- };
|
|
-
|
|
- vbus_otg: pwr_sw1 {
|
|
- regulator-name = "vbus_otg";
|
|
- interrupts = <IT_OCP_OTG 0>;
|
|
- };
|
|
-
|
|
- vbus_sw: pwr_sw2 {
|
|
- regulator-name = "vbus_sw";
|
|
- interrupts = <IT_OCP_SWOUT 0>;
|
|
- regulator-active-discharge;
|
|
- };
|
|
- };
|
|
-
|
|
- onkey {
|
|
- compatible = "st,stpmic1-onkey";
|
|
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
- interrupt-names = "onkey-falling", "onkey-rising";
|
|
- power-off-time-sec = <10>;
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- watchdog {
|
|
- compatible = "st,stpmic1-wdt";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&ipcc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&iwdg2 {
|
|
- timeout-sec = <32>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&m4_rproc {
|
|
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
- <&vdev0vring1>, <&vdev0buffer>;
|
|
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
- mbox-names = "vq0", "vq1", "shutdown";
|
|
- interrupt-parent = <&exti>;
|
|
- interrupts = <68 1>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pwr {
|
|
- pwr-regulators {
|
|
- vdd-supply = <&vdd>;
|
|
- vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
- };
|
|
-};
|
|
-
|
|
-&rng1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rtc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sdmmc1 {
|
|
- pinctrl-names = "default", "opendrain", "sleep";
|
|
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
|
- broken-cd;
|
|
- st,sig-dir;
|
|
- st,neg-edge;
|
|
- st,use-ckin;
|
|
- bus-width = <4>;
|
|
- vmmc-supply = <&vdd_sd>;
|
|
- vqmmc-supply = <&sd_switch>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sdmmc2 {
|
|
- pinctrl-names = "default", "opendrain", "sleep";
|
|
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
|
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
|
- non-removable;
|
|
- no-sd;
|
|
- no-sdio;
|
|
- st,neg-edge;
|
|
- bus-width = <8>;
|
|
- vmmc-supply = <&v3v3>;
|
|
- vqmmc-supply = <&v3v3>;
|
|
- mmc-ddr-3_3v;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&timers6 {
|
|
- status = "okay";
|
|
- /* spare dmas for other usage */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- timer@5 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&uart4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&uart4_pins_a>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbotg_hs {
|
|
- vbus-supply = <&vbus_otg>;
|
|
-};
|
|
-
|
|
-&usbphyc_port0 {
|
|
- phy-supply = <&vdd_usb>;
|
|
-};
|
|
-
|
|
-&usbphyc_port1 {
|
|
- phy-supply = <&vdd_usb>;
|
|
};
|
|
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
|
|
index ec60486..cc02806 100644
|
|
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
|
|
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
|
|
@@ -3,51 +3,4 @@
|
|
* Copyright : STMicroelectronics 2018
|
|
*/
|
|
|
|
-#include "stm32mp157c-ed1-u-boot.dtsi"
|
|
-
|
|
-/ {
|
|
- aliases {
|
|
- gpio26 = &stmfx_pinctrl;
|
|
- i2c1 = &i2c2;
|
|
- i2c4 = &i2c5;
|
|
- pinctrl2 = &stmfx_pinctrl;
|
|
- spi0 = &qspi;
|
|
- usb0 = &usbotg_hs;
|
|
- };
|
|
-};
|
|
-
|
|
-&flash0 {
|
|
- u-boot,dm-spl;
|
|
-};
|
|
-
|
|
-&qspi {
|
|
- u-boot,dm-spl;
|
|
-};
|
|
-
|
|
-&qspi_clk_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&qspi_bk1_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins1 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
- pins2 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
-&qspi_bk2_pins_a {
|
|
- u-boot,dm-spl;
|
|
- pins1 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
- pins2 {
|
|
- u-boot,dm-spl;
|
|
- };
|
|
-};
|
|
-
|
|
+#include "stm32mp157a-ev1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
|
|
index 89d29b5..c60727d 100644
|
|
--- a/arch/arm/dts/stm32mp157c-ev1.dts
|
|
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
|
|
@@ -1,13 +1,14 @@
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "stm32mp157c-ed1.dts"
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
|
|
/ {
|
|
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
|
@@ -18,90 +19,14 @@
|
|
};
|
|
|
|
aliases {
|
|
- serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
ethernet0 = ðernet0;
|
|
};
|
|
-
|
|
- clocks {
|
|
- clk_ext_camera: clk-ext-camera {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <24000000>;
|
|
- };
|
|
- };
|
|
-
|
|
- joystick {
|
|
- compatible = "gpio-keys";
|
|
- #size-cells = <0>;
|
|
- pinctrl-0 = <&joystick_pins>;
|
|
- pinctrl-names = "default";
|
|
- button-0 {
|
|
- label = "JoySel";
|
|
- linux,code = <KEY_ENTER>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-1 {
|
|
- label = "JoyDown";
|
|
- linux,code = <KEY_DOWN>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-2 {
|
|
- label = "JoyLeft";
|
|
- linux,code = <KEY_LEFT>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-3 {
|
|
- label = "JoyRight";
|
|
- linux,code = <KEY_RIGHT>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- button-4 {
|
|
- label = "JoyUp";
|
|
- linux,code = <KEY_UP>;
|
|
- interrupt-parent = <&stmfx_pinctrl>;
|
|
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
|
- };
|
|
- };
|
|
-
|
|
- panel_backlight: panel-backlight {
|
|
- compatible = "gpio-backlight";
|
|
- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
|
- default-on;
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&cec {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&cec_pins_a>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&dcmi {
|
|
- status = "okay";
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&dcmi_pins_a>;
|
|
- pinctrl-1 = <&dcmi_sleep_pins_a>;
|
|
-
|
|
- port {
|
|
- dcmi_0: endpoint {
|
|
- remote-endpoint = <&ov5640_0>;
|
|
- bus-width = <8>;
|
|
- hsync-active = <0>;
|
|
- vsync-active = <0>;
|
|
- pclk-sample = <1>;
|
|
- };
|
|
- };
|
|
};
|
|
|
|
&dsi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
- phy-dsi-supply = <®18>;
|
|
status = "okay";
|
|
|
|
ports {
|
|
@@ -123,7 +48,7 @@
|
|
};
|
|
};
|
|
|
|
- panel-dsi@0 {
|
|
+ panel_dsi: panel-dsi@0 {
|
|
compatible = "raydium,rm68200";
|
|
reg = <0>;
|
|
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
@@ -139,122 +64,17 @@
|
|
};
|
|
};
|
|
|
|
-ðernet0 {
|
|
- status = "okay";
|
|
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
- pinctrl-names = "default", "sleep";
|
|
- phy-mode = "rgmii-id";
|
|
- max-speed = <1000>;
|
|
- phy-handle = <&phy0>;
|
|
-
|
|
- mdio0 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "snps,dwmac-mdio";
|
|
- phy0: ethernet-phy@0 {
|
|
- reg = <0>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&fmc {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&fmc_pins_a>;
|
|
- pinctrl-1 = <&fmc_sleep_pins_a>;
|
|
- status = "okay";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- nand@0 {
|
|
- reg = <0>;
|
|
- nand-on-flash-bbt;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-};
|
|
-
|
|
&i2c2 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c2_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
-
|
|
- ov5640: camera@3c {
|
|
- compatible = "ovti,ov5640";
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
pinctrl-names = "default";
|
|
- pinctrl-0 = <&ov5640_pins>;
|
|
- reg = <0x3c>;
|
|
- clocks = <&clk_ext_camera>;
|
|
- clock-names = "xclk";
|
|
- DOVDD-supply = <&v2v8>;
|
|
- powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
|
|
- reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
|
|
- rotation = <180>;
|
|
status = "okay";
|
|
|
|
- port {
|
|
- ov5640_0: endpoint {
|
|
- remote-endpoint = <&dcmi_0>;
|
|
- bus-width = <8>;
|
|
- data-shift = <2>; /* lines 9:2 are used */
|
|
- hsync-active = <0>;
|
|
- vsync-active = <0>;
|
|
- pclk-sample = <1>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- stmfx: stmfx@42 {
|
|
- compatible = "st,stmfx-0300";
|
|
- reg = <0x42>;
|
|
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
|
- interrupt-parent = <&gpioi>;
|
|
- vdd-supply = <&v3v3>;
|
|
-
|
|
- stmfx_pinctrl: stmfx-pin-controller {
|
|
- compatible = "st,stmfx-0300-pinctrl";
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
|
-
|
|
- joystick_pins: joystick {
|
|
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
|
- drive-push-pull;
|
|
- bias-pull-down;
|
|
- };
|
|
-
|
|
- ov5640_pins: camera {
|
|
- pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
|
|
- drive-push-pull;
|
|
- output-low;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c5 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c5_pins_a>;
|
|
- i2c-scl-rising-time-ns = <185>;
|
|
- i2c-scl-falling-time-ns = <20>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-<dc {
|
|
- status = "okay";
|
|
-
|
|
- port {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- ltdc_ep0_out: endpoint@0 {
|
|
- reg = <0>;
|
|
- remote-endpoint = <&dsi_in>;
|
|
- };
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
};
|
|
};
|
|
|
|
@@ -264,97 +84,3 @@
|
|
pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
status = "okay";
|
|
};
|
|
-
|
|
-&qspi {
|
|
- pinctrl-names = "default", "sleep";
|
|
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
|
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
|
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "okay";
|
|
-
|
|
- flash0: mx66l51235l@0 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <0>;
|
|
- spi-rx-bus-width = <4>;
|
|
- spi-max-frequency = <108000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-
|
|
- flash1: mx66l51235l@1 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <1>;
|
|
- spi-rx-bus-width = <4>;
|
|
- spi-max-frequency = <108000000>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- };
|
|
-};
|
|
-
|
|
-&spi1 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&spi1_pins_a>;
|
|
- status = "disabled";
|
|
-};
|
|
-
|
|
-&timers2 {
|
|
- /* spare dmas for other usage (un-delete to enable pwm capture) */
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm2_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@1 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&timers8 {
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm8_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@7 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&timers12 {
|
|
- /delete-property/dmas;
|
|
- /delete-property/dma-names;
|
|
- status = "disabled";
|
|
- pwm {
|
|
- pinctrl-0 = <&pwm12_pins_a>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
- };
|
|
- timer@11 {
|
|
- status = "okay";
|
|
- };
|
|
-};
|
|
-
|
|
-&usbh_ehci {
|
|
- phys = <&usbphyc_port0>;
|
|
- phy-names = "usb";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbotg_hs {
|
|
- dr_mode = "peripheral";
|
|
- phys = <&usbphyc_port1 0>;
|
|
- phy-names = "usb2-phy";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbphyc {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
|
|
deleted file mode 100644
|
|
index 6c670cf..0000000
|
|
--- a/arch/arm/dts/stm32mp157c.dtsi
|
|
+++ /dev/null
|
|
@@ -1,1592 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
- */
|
|
-#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
-#include <dt-bindings/clock/stm32mp1-clks.h>
|
|
-#include <dt-bindings/reset/stm32mp1-resets.h>
|
|
-
|
|
-/ {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
-
|
|
- cpus {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- cpu0: cpu@0 {
|
|
- compatible = "arm,cortex-a7";
|
|
- device_type = "cpu";
|
|
- reg = <0>;
|
|
- };
|
|
-
|
|
- cpu1: cpu@1 {
|
|
- compatible = "arm,cortex-a7";
|
|
- device_type = "cpu";
|
|
- reg = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- psci {
|
|
- compatible = "arm,psci-1.0";
|
|
- method = "smc";
|
|
- cpu_off = <0x84000002>;
|
|
- cpu_on = <0x84000003>;
|
|
- };
|
|
-
|
|
- intc: interrupt-controller@a0021000 {
|
|
- compatible = "arm,cortex-a7-gic";
|
|
- #interrupt-cells = <3>;
|
|
- interrupt-controller;
|
|
- reg = <0xa0021000 0x1000>,
|
|
- <0xa0022000 0x2000>;
|
|
- };
|
|
-
|
|
- timer {
|
|
- compatible = "arm,armv7-timer";
|
|
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
- interrupt-parent = <&intc>;
|
|
- };
|
|
-
|
|
- clocks {
|
|
- clk_hse: clk-hse {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <24000000>;
|
|
- };
|
|
-
|
|
- clk_hsi: clk-hsi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <64000000>;
|
|
- };
|
|
-
|
|
- clk_lse: clk-lse {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <32768>;
|
|
- };
|
|
-
|
|
- clk_lsi: clk-lsi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <32000>;
|
|
- };
|
|
-
|
|
- clk_csi: clk-csi {
|
|
- #clock-cells = <0>;
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <4000000>;
|
|
- };
|
|
- };
|
|
-
|
|
- thermal-zones {
|
|
- cpu_thermal: cpu-thermal {
|
|
- polling-delay-passive = <0>;
|
|
- polling-delay = <0>;
|
|
- thermal-sensors = <&dts>;
|
|
-
|
|
- trips {
|
|
- cpu_alert1: cpu-alert1 {
|
|
- temperature = <85000>;
|
|
- hysteresis = <0>;
|
|
- type = "passive";
|
|
- };
|
|
-
|
|
- cpu-crit {
|
|
- temperature = <120000>;
|
|
- hysteresis = <0>;
|
|
- type = "critical";
|
|
- };
|
|
- };
|
|
-
|
|
- cooling-maps {
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- booster: regulator-booster {
|
|
- compatible = "st,stm32mp1-booster";
|
|
- st,syscfg = <&syscfg>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- reboot {
|
|
- compatible = "syscon-reboot";
|
|
- regmap = <&rcc>;
|
|
- offset = <0x404>;
|
|
- mask = <0x1>;
|
|
- };
|
|
-
|
|
- soc {
|
|
- compatible = "simple-bus";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- interrupt-parent = <&intc>;
|
|
- ranges;
|
|
-
|
|
- timers2: timer@40000000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40000000 0x400>;
|
|
- clocks = <&rcc TIM2_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 18 0x400 0x1>,
|
|
- <&dmamux1 19 0x400 0x1>,
|
|
- <&dmamux1 20 0x400 0x1>,
|
|
- <&dmamux1 21 0x400 0x1>,
|
|
- <&dmamux1 22 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@1 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <1>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers3: timer@40001000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40001000 0x400>;
|
|
- clocks = <&rcc TIM3_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 23 0x400 0x1>,
|
|
- <&dmamux1 24 0x400 0x1>,
|
|
- <&dmamux1 25 0x400 0x1>,
|
|
- <&dmamux1 26 0x400 0x1>,
|
|
- <&dmamux1 27 0x400 0x1>,
|
|
- <&dmamux1 28 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@2 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers4: timer@40002000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40002000 0x400>;
|
|
- clocks = <&rcc TIM4_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 29 0x400 0x1>,
|
|
- <&dmamux1 30 0x400 0x1>,
|
|
- <&dmamux1 31 0x400 0x1>,
|
|
- <&dmamux1 32 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@3 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers5: timer@40003000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40003000 0x400>;
|
|
- clocks = <&rcc TIM5_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 55 0x400 0x1>,
|
|
- <&dmamux1 56 0x400 0x1>,
|
|
- <&dmamux1 57 0x400 0x1>,
|
|
- <&dmamux1 58 0x400 0x1>,
|
|
- <&dmamux1 59 0x400 0x1>,
|
|
- <&dmamux1 60 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@4 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <4>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers6: timer@40004000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40004000 0x400>;
|
|
- clocks = <&rcc TIM6_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 69 0x400 0x1>;
|
|
- dma-names = "up";
|
|
- status = "disabled";
|
|
-
|
|
- timer@5 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <5>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers7: timer@40005000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40005000 0x400>;
|
|
- clocks = <&rcc TIM7_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 70 0x400 0x1>;
|
|
- dma-names = "up";
|
|
- status = "disabled";
|
|
-
|
|
- timer@6 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <6>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers12: timer@40006000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40006000 0x400>;
|
|
- clocks = <&rcc TIM12_K>;
|
|
- clock-names = "int";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@11 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <11>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers13: timer@40007000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40007000 0x400>;
|
|
- clocks = <&rcc TIM13_K>;
|
|
- clock-names = "int";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@12 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <12>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers14: timer@40008000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x40008000 0x400>;
|
|
- clocks = <&rcc TIM14_K>;
|
|
- clock-names = "int";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@13 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <13>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- lptimer1: timer@40009000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-lptimer";
|
|
- reg = <0x40009000 0x400>;
|
|
- clocks = <&rcc LPTIM1_K>;
|
|
- clock-names = "mux";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm-lp";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- trigger@0 {
|
|
- compatible = "st,stm32-lptimer-trigger";
|
|
- reg = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- counter {
|
|
- compatible = "st,stm32-lptimer-counter";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- spi2: spi@4000b000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x4000b000 0x400>;
|
|
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI2_K>;
|
|
- resets = <&rcc SPI2_R>;
|
|
- dmas = <&dmamux1 39 0x400 0x05>,
|
|
- <&dmamux1 40 0x400 0x05>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2s2: audio-controller@4000b000 {
|
|
- compatible = "st,stm32h7-i2s";
|
|
- #sound-dai-cells = <0>;
|
|
- reg = <0x4000b000 0x400>;
|
|
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 39 0x400 0x01>,
|
|
- <&dmamux1 40 0x400 0x01>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- spi3: spi@4000c000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x4000c000 0x400>;
|
|
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI3_K>;
|
|
- resets = <&rcc SPI3_R>;
|
|
- dmas = <&dmamux1 61 0x400 0x05>,
|
|
- <&dmamux1 62 0x400 0x05>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2s3: audio-controller@4000c000 {
|
|
- compatible = "st,stm32h7-i2s";
|
|
- #sound-dai-cells = <0>;
|
|
- reg = <0x4000c000 0x400>;
|
|
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 61 0x400 0x01>,
|
|
- <&dmamux1 62 0x400 0x01>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- spdifrx: audio-controller@4000d000 {
|
|
- compatible = "st,stm32h7-spdifrx";
|
|
- #sound-dai-cells = <0>;
|
|
- reg = <0x4000d000 0x400>;
|
|
- clocks = <&rcc SPDIF_K>;
|
|
- clock-names = "kclk";
|
|
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 93 0x400 0x01>,
|
|
- <&dmamux1 94 0x400 0x01>;
|
|
- dma-names = "rx", "rx-ctrl";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usart2: serial@4000e000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x4000e000 0x400>;
|
|
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc USART2_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usart3: serial@4000f000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x4000f000 0x400>;
|
|
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc USART3_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart4: serial@40010000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x40010000 0x400>;
|
|
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc UART4_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart5: serial@40011000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x40011000 0x400>;
|
|
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc UART5_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c1: i2c@40012000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x40012000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C1_K>;
|
|
- resets = <&rcc I2C1_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c2: i2c@40013000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x40013000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C2_K>;
|
|
- resets = <&rcc I2C2_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c3: i2c@40014000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x40014000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C3_K>;
|
|
- resets = <&rcc I2C3_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c5: i2c@40015000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x40015000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C5_K>;
|
|
- resets = <&rcc I2C5_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- cec: cec@40016000 {
|
|
- compatible = "st,stm32-cec";
|
|
- reg = <0x40016000 0x400>;
|
|
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc CEC_K>, <&clk_lse>;
|
|
- clock-names = "cec", "hdmi-cec";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dac: dac@40017000 {
|
|
- compatible = "st,stm32h7-dac-core";
|
|
- reg = <0x40017000 0x400>;
|
|
- clocks = <&rcc DAC12>;
|
|
- clock-names = "pclk";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
-
|
|
- dac1: dac@1 {
|
|
- compatible = "st,stm32-dac";
|
|
- #io-channels-cells = <1>;
|
|
- reg = <1>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dac2: dac@2 {
|
|
- compatible = "st,stm32-dac";
|
|
- #io-channels-cells = <1>;
|
|
- reg = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- uart7: serial@40018000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x40018000 0x400>;
|
|
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc UART7_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart8: serial@40019000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x40019000 0x400>;
|
|
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc UART8_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timers1: timer@44000000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x44000000 0x400>;
|
|
- clocks = <&rcc TIM1_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 11 0x400 0x1>,
|
|
- <&dmamux1 12 0x400 0x1>,
|
|
- <&dmamux1 13 0x400 0x1>,
|
|
- <&dmamux1 14 0x400 0x1>,
|
|
- <&dmamux1 15 0x400 0x1>,
|
|
- <&dmamux1 16 0x400 0x1>,
|
|
- <&dmamux1 17 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
- "up", "trig", "com";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@0 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers8: timer@44001000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x44001000 0x400>;
|
|
- clocks = <&rcc TIM8_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 47 0x400 0x1>,
|
|
- <&dmamux1 48 0x400 0x1>,
|
|
- <&dmamux1 49 0x400 0x1>,
|
|
- <&dmamux1 50 0x400 0x1>,
|
|
- <&dmamux1 51 0x400 0x1>,
|
|
- <&dmamux1 52 0x400 0x1>,
|
|
- <&dmamux1 53 0x400 0x1>;
|
|
- dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
- "up", "trig", "com";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@7 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <7>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- usart6: serial@44003000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x44003000 0x400>;
|
|
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc USART6_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- spi1: spi@44004000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x44004000 0x400>;
|
|
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI1_K>;
|
|
- resets = <&rcc SPI1_R>;
|
|
- dmas = <&dmamux1 37 0x400 0x05>,
|
|
- <&dmamux1 38 0x400 0x05>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2s1: audio-controller@44004000 {
|
|
- compatible = "st,stm32h7-i2s";
|
|
- #sound-dai-cells = <0>;
|
|
- reg = <0x44004000 0x400>;
|
|
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 37 0x400 0x01>,
|
|
- <&dmamux1 38 0x400 0x01>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- spi4: spi@44005000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x44005000 0x400>;
|
|
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI4_K>;
|
|
- resets = <&rcc SPI4_R>;
|
|
- dmas = <&dmamux1 83 0x400 0x05>,
|
|
- <&dmamux1 84 0x400 0x05>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timers15: timer@44006000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x44006000 0x400>;
|
|
- clocks = <&rcc TIM15_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 105 0x400 0x1>,
|
|
- <&dmamux1 106 0x400 0x1>,
|
|
- <&dmamux1 107 0x400 0x1>,
|
|
- <&dmamux1 108 0x400 0x1>;
|
|
- dma-names = "ch1", "up", "trig", "com";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@14 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <14>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers16: timer@44007000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x44007000 0x400>;
|
|
- clocks = <&rcc TIM16_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 109 0x400 0x1>,
|
|
- <&dmamux1 110 0x400 0x1>;
|
|
- dma-names = "ch1", "up";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
- timer@15 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <15>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- timers17: timer@44008000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-timers";
|
|
- reg = <0x44008000 0x400>;
|
|
- clocks = <&rcc TIM17_K>;
|
|
- clock-names = "int";
|
|
- dmas = <&dmamux1 111 0x400 0x1>,
|
|
- <&dmamux1 112 0x400 0x1>;
|
|
- dma-names = "ch1", "up";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- timer@16 {
|
|
- compatible = "st,stm32h7-timer-trigger";
|
|
- reg = <16>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- spi5: spi@44009000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x44009000 0x400>;
|
|
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI5_K>;
|
|
- resets = <&rcc SPI5_R>;
|
|
- dmas = <&dmamux1 85 0x400 0x05>,
|
|
- <&dmamux1 86 0x400 0x05>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai1: sai@4400a000 {
|
|
- compatible = "st,stm32h7-sai";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges = <0 0x4400a000 0x400>;
|
|
- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
|
|
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
- resets = <&rcc SAI1_R>;
|
|
- status = "disabled";
|
|
-
|
|
- sai1a: audio-controller@4400a004 {
|
|
- #sound-dai-cells = <0>;
|
|
-
|
|
- compatible = "st,stm32-sai-sub-a";
|
|
- reg = <0x4 0x1c>;
|
|
- clocks = <&rcc SAI1_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 87 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai1b: audio-controller@4400a024 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-b";
|
|
- reg = <0x24 0x1c>;
|
|
- clocks = <&rcc SAI1_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 88 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- sai2: sai@4400b000 {
|
|
- compatible = "st,stm32h7-sai";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges = <0 0x4400b000 0x400>;
|
|
- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
|
|
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
- resets = <&rcc SAI2_R>;
|
|
- status = "disabled";
|
|
-
|
|
- sai2a: audio-controller@4400b004 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-a";
|
|
- reg = <0x4 0x1c>;
|
|
- clocks = <&rcc SAI2_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 89 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai2b: audio-controller@4400b024 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-b";
|
|
- reg = <0x24 0x1c>;
|
|
- clocks = <&rcc SAI2_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 90 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- sai3: sai@4400c000 {
|
|
- compatible = "st,stm32h7-sai";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges = <0 0x4400c000 0x400>;
|
|
- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
|
|
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
- resets = <&rcc SAI3_R>;
|
|
- status = "disabled";
|
|
-
|
|
- sai3a: audio-controller@4400c004 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-a";
|
|
- reg = <0x04 0x1c>;
|
|
- clocks = <&rcc SAI3_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 113 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai3b: audio-controller@4400c024 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-b";
|
|
- reg = <0x24 0x1c>;
|
|
- clocks = <&rcc SAI3_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 114 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- dfsdm: dfsdm@4400d000 {
|
|
- compatible = "st,stm32mp1-dfsdm";
|
|
- reg = <0x4400d000 0x800>;
|
|
- clocks = <&rcc DFSDM_K>;
|
|
- clock-names = "dfsdm";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
-
|
|
- dfsdm0: filter@0 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <0>;
|
|
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 101 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dfsdm1: filter@1 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <1>;
|
|
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 102 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dfsdm2: filter@2 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <2>;
|
|
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 103 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dfsdm3: filter@3 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <3>;
|
|
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 104 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dfsdm4: filter@4 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <4>;
|
|
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 91 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dfsdm5: filter@5 {
|
|
- compatible = "st,stm32-dfsdm-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <5>;
|
|
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&dmamux1 92 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- m_can1: can@4400e000 {
|
|
- compatible = "bosch,m_can";
|
|
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
- reg-names = "m_can", "message_ram";
|
|
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "int0", "int1";
|
|
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
- clock-names = "hclk", "cclk";
|
|
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- m_can2: can@4400f000 {
|
|
- compatible = "bosch,m_can";
|
|
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
- reg-names = "m_can", "message_ram";
|
|
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "int0", "int1";
|
|
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
|
- clock-names = "hclk", "cclk";
|
|
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dma1: dma@48000000 {
|
|
- compatible = "st,stm32-dma";
|
|
- reg = <0x48000000 0x400>;
|
|
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc DMA1>;
|
|
- #dma-cells = <4>;
|
|
- st,mem2mem;
|
|
- dma-requests = <8>;
|
|
- };
|
|
-
|
|
- dma2: dma@48001000 {
|
|
- compatible = "st,stm32-dma";
|
|
- reg = <0x48001000 0x400>;
|
|
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc DMA2>;
|
|
- #dma-cells = <4>;
|
|
- st,mem2mem;
|
|
- dma-requests = <8>;
|
|
- };
|
|
-
|
|
- dmamux1: dma-router@48002000 {
|
|
- compatible = "st,stm32h7-dmamux";
|
|
- reg = <0x48002000 0x1c>;
|
|
- #dma-cells = <3>;
|
|
- dma-requests = <128>;
|
|
- dma-masters = <&dma1 &dma2>;
|
|
- dma-channels = <16>;
|
|
- clocks = <&rcc DMAMUX>;
|
|
- };
|
|
-
|
|
- adc: adc@48003000 {
|
|
- compatible = "st,stm32mp1-adc-core";
|
|
- reg = <0x48003000 0x400>;
|
|
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
- clock-names = "bus", "adc";
|
|
- interrupt-controller;
|
|
- st,syscfg = <&syscfg>;
|
|
- #interrupt-cells = <1>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
-
|
|
- adc1: adc@0 {
|
|
- compatible = "st,stm32mp1-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <0x0>;
|
|
- interrupt-parent = <&adc>;
|
|
- interrupts = <0>;
|
|
- dmas = <&dmamux1 9 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- adc2: adc@100 {
|
|
- compatible = "st,stm32mp1-adc";
|
|
- #io-channel-cells = <1>;
|
|
- reg = <0x100>;
|
|
- interrupt-parent = <&adc>;
|
|
- interrupts = <1>;
|
|
- dmas = <&dmamux1 10 0x400 0x01>;
|
|
- dma-names = "rx";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- sdmmc3: sdmmc@48004000 {
|
|
- compatible = "arm,pl18x", "arm,primecell";
|
|
- arm,primecell-periphid = <0x10153180>;
|
|
- reg = <0x48004000 0x400>;
|
|
- reg-names = "sdmmc";
|
|
- interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
|
|
- clocks = <&rcc SDMMC3_K>;
|
|
- clock-names = "apb_pclk";
|
|
- resets = <&rcc SDMMC3_R>;
|
|
- cap-sd-highspeed;
|
|
- cap-mmc-highspeed;
|
|
- max-frequency = <120000000>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usbotg_hs: usb-otg@49000000 {
|
|
- compatible = "snps,dwc2";
|
|
- reg = <0x49000000 0x10000>;
|
|
- clocks = <&rcc USBO_K>;
|
|
- clock-names = "otg";
|
|
- resets = <&rcc USBO_R>;
|
|
- reset-names = "dwc2";
|
|
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
- g-rx-fifo-size = <256>;
|
|
- g-np-tx-fifo-size = <32>;
|
|
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
- dr_mode = "otg";
|
|
- usb33d-supply = <&usb33>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- hwspinlock: hwspinlock@4c000000 {
|
|
- compatible = "st,stm32-hwspinlock";
|
|
- #hwlock-cells = <1>;
|
|
- reg = <0x4c000000 0x400>;
|
|
- clocks = <&rcc HSEM>;
|
|
- clock-names = "hwspinlock";
|
|
- };
|
|
-
|
|
- ipcc: mailbox@4c001000 {
|
|
- compatible = "st,stm32mp1-ipcc";
|
|
- #mbox-cells = <1>;
|
|
- reg = <0x4c001000 0x400>;
|
|
- st,proc-id = <0>;
|
|
- interrupts-extended =
|
|
- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <&exti 61 1>;
|
|
- interrupt-names = "rx", "tx", "wakeup";
|
|
- clocks = <&rcc IPCC>;
|
|
- wakeup-source;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dcmi: dcmi@4c006000 {
|
|
- compatible = "st,stm32-dcmi";
|
|
- reg = <0x4c006000 0x400>;
|
|
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
- resets = <&rcc CAMITF_R>;
|
|
- clocks = <&rcc DCMI>;
|
|
- clock-names = "mclk";
|
|
- dmas = <&dmamux1 75 0x400 0x0d>;
|
|
- dma-names = "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- rcc: rcc@50000000 {
|
|
- compatible = "st,stm32mp1-rcc", "syscon";
|
|
- reg = <0x50000000 0x1000>;
|
|
- #clock-cells = <1>;
|
|
- #reset-cells = <1>;
|
|
- };
|
|
-
|
|
- pwr: pwr@50001000 {
|
|
- compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
|
|
- reg = <0x50001000 0x400>;
|
|
- system-power-controller;
|
|
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
- st,sysrcc = <&rcc>;
|
|
- clocks = <&rcc PLL2_R>;
|
|
- clock-names = "phyclk";
|
|
-
|
|
- pwr-regulators {
|
|
- compatible = "st,stm32mp1,pwr-reg";
|
|
- st,tzcr = <&rcc 0x0 0x1>;
|
|
-
|
|
- reg11: reg11 {
|
|
- regulator-name = "reg11";
|
|
- regulator-min-microvolt = <1100000>;
|
|
- regulator-max-microvolt = <1100000>;
|
|
- };
|
|
-
|
|
- reg18: reg18 {
|
|
- regulator-name = "reg18";
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- };
|
|
-
|
|
- usb33: usb33 {
|
|
- regulator-name = "usb33";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- exti: interrupt-controller@5000d000 {
|
|
- compatible = "st,stm32mp1-exti", "syscon";
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- reg = <0x5000d000 0x400>;
|
|
- };
|
|
-
|
|
- syscfg: syscon@50020000 {
|
|
- compatible = "st,stm32mp157-syscfg", "syscon";
|
|
- reg = <0x50020000 0x400>;
|
|
- clocks = <&rcc SYSCFG>;
|
|
- };
|
|
-
|
|
- lptimer2: timer@50021000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-lptimer";
|
|
- reg = <0x50021000 0x400>;
|
|
- clocks = <&rcc LPTIM2_K>;
|
|
- clock-names = "mux";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm-lp";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- trigger@1 {
|
|
- compatible = "st,stm32-lptimer-trigger";
|
|
- reg = <1>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- counter {
|
|
- compatible = "st,stm32-lptimer-counter";
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- lptimer3: timer@50022000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32-lptimer";
|
|
- reg = <0x50022000 0x400>;
|
|
- clocks = <&rcc LPTIM3_K>;
|
|
- clock-names = "mux";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm-lp";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- trigger@2 {
|
|
- compatible = "st,stm32-lptimer-trigger";
|
|
- reg = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- lptimer4: timer@50023000 {
|
|
- compatible = "st,stm32-lptimer";
|
|
- reg = <0x50023000 0x400>;
|
|
- clocks = <&rcc LPTIM4_K>;
|
|
- clock-names = "mux";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm-lp";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- lptimer5: timer@50024000 {
|
|
- compatible = "st,stm32-lptimer";
|
|
- reg = <0x50024000 0x400>;
|
|
- clocks = <&rcc LPTIM5_K>;
|
|
- clock-names = "mux";
|
|
- status = "disabled";
|
|
-
|
|
- pwm {
|
|
- compatible = "st,stm32-pwm-lp";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- vrefbuf: vrefbuf@50025000 {
|
|
- compatible = "st,stm32-vrefbuf";
|
|
- reg = <0x50025000 0x8>;
|
|
- regulator-min-microvolt = <1500000>;
|
|
- regulator-max-microvolt = <2500000>;
|
|
- clocks = <&rcc VREF>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai4: sai@50027000 {
|
|
- compatible = "st,stm32h7-sai";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges = <0 0x50027000 0x400>;
|
|
- reg = <0x50027000 0x4>, <0x500273f0 0x10>;
|
|
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
- resets = <&rcc SAI4_R>;
|
|
- status = "disabled";
|
|
-
|
|
- sai4a: audio-controller@50027004 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-a";
|
|
- reg = <0x04 0x1c>;
|
|
- clocks = <&rcc SAI4_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 99 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sai4b: audio-controller@50027024 {
|
|
- #sound-dai-cells = <0>;
|
|
- compatible = "st,stm32-sai-sub-b";
|
|
- reg = <0x24 0x1c>;
|
|
- clocks = <&rcc SAI4_K>;
|
|
- clock-names = "sai_ck";
|
|
- dmas = <&dmamux1 100 0x400 0x01>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- dts: thermal@50028000 {
|
|
- compatible = "st,stm32-thermal";
|
|
- reg = <0x50028000 0x100>;
|
|
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc TMPSENS>;
|
|
- clock-names = "pclk";
|
|
- #thermal-sensor-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- cryp1: cryp@54001000 {
|
|
- compatible = "st,stm32mp1-cryp";
|
|
- reg = <0x54001000 0x400>;
|
|
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc CRYP1>;
|
|
- resets = <&rcc CRYP1_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- hash1: hash@54002000 {
|
|
- compatible = "st,stm32f756-hash";
|
|
- reg = <0x54002000 0x400>;
|
|
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc HASH1>;
|
|
- resets = <&rcc HASH1_R>;
|
|
- dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
|
- dma-names = "in";
|
|
- dma-maxburst = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- rng1: rng@54003000 {
|
|
- compatible = "st,stm32-rng";
|
|
- reg = <0x54003000 0x400>;
|
|
- clocks = <&rcc RNG1_K>;
|
|
- resets = <&rcc RNG1_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- mdma1: dma@58000000 {
|
|
- compatible = "st,stm32h7-mdma";
|
|
- reg = <0x58000000 0x1000>;
|
|
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc MDMA>;
|
|
- #dma-cells = <5>;
|
|
- dma-channels = <32>;
|
|
- dma-requests = <48>;
|
|
- };
|
|
-
|
|
- fmc: nand-controller@58002000 {
|
|
- compatible = "st,stm32mp15-fmc2";
|
|
- reg = <0x58002000 0x1000>,
|
|
- <0x80000000 0x1000>,
|
|
- <0x88010000 0x1000>,
|
|
- <0x88020000 0x1000>,
|
|
- <0x81000000 0x1000>,
|
|
- <0x89010000 0x1000>,
|
|
- <0x89020000 0x1000>;
|
|
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
|
|
- <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
|
|
- <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
|
|
- dma-names = "tx", "rx", "ecc";
|
|
- clocks = <&rcc FMC_K>;
|
|
- resets = <&rcc FMC_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- qspi: spi@58003000 {
|
|
- compatible = "st,stm32f469-qspi";
|
|
- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
- reg-names = "qspi", "qspi_mm";
|
|
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
- dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
|
|
- <&mdma1 22 0x10 0x100008 0x0 0x0>;
|
|
- dma-names = "tx", "rx";
|
|
- clocks = <&rcc QSPI_K>;
|
|
- resets = <&rcc QSPI_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sdmmc1: sdmmc@58005000 {
|
|
- compatible = "arm,pl18x", "arm,primecell";
|
|
- arm,primecell-periphid = <0x10153180>;
|
|
- reg = <0x58005000 0x1000>;
|
|
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "cmd_irq";
|
|
- clocks = <&rcc SDMMC1_K>;
|
|
- clock-names = "apb_pclk";
|
|
- resets = <&rcc SDMMC1_R>;
|
|
- cap-sd-highspeed;
|
|
- cap-mmc-highspeed;
|
|
- max-frequency = <120000000>;
|
|
- };
|
|
-
|
|
- sdmmc2: sdmmc@58007000 {
|
|
- compatible = "arm,pl18x", "arm,primecell";
|
|
- arm,primecell-periphid = <0x10153180>;
|
|
- reg = <0x58007000 0x1000>;
|
|
- interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
|
|
- clocks = <&rcc SDMMC2_K>;
|
|
- clock-names = "apb_pclk";
|
|
- resets = <&rcc SDMMC2_R>;
|
|
- cap-sd-highspeed;
|
|
- cap-mmc-highspeed;
|
|
- max-frequency = <120000000>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- crc1: crc@58009000 {
|
|
- compatible = "st,stm32f7-crc";
|
|
- reg = <0x58009000 0x400>;
|
|
- clocks = <&rcc CRC1>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- stmmac_axi_config_0: stmmac-axi-config {
|
|
- snps,wr_osr_lmt = <0x7>;
|
|
- snps,rd_osr_lmt = <0x7>;
|
|
- snps,blen = <0 0 0 0 16 8 4>;
|
|
- };
|
|
-
|
|
- ethernet0: ethernet@5800a000 {
|
|
- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
|
- reg = <0x5800a000 0x2000>;
|
|
- reg-names = "stmmaceth";
|
|
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "macirq";
|
|
- clock-names = "stmmaceth",
|
|
- "mac-clk-tx",
|
|
- "mac-clk-rx",
|
|
- "ethstp",
|
|
- "syscfg-clk";
|
|
- clocks = <&rcc ETHMAC>,
|
|
- <&rcc ETHTX>,
|
|
- <&rcc ETHRX>,
|
|
- <&rcc ETHSTP>,
|
|
- <&rcc SYSCFG>;
|
|
- st,syscon = <&syscfg 0x4>;
|
|
- snps,mixed-burst;
|
|
- snps,pbl = <2>;
|
|
- snps,axi-config = <&stmmac_axi_config_0>;
|
|
- snps,tso;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usbh_ohci: usbh-ohci@5800c000 {
|
|
- compatible = "generic-ohci";
|
|
- reg = <0x5800c000 0x1000>;
|
|
- clocks = <&rcc USBH>;
|
|
- resets = <&rcc USBH_R>;
|
|
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usbh_ehci: usbh-ehci@5800d000 {
|
|
- compatible = "generic-ehci";
|
|
- reg = <0x5800d000 0x1000>;
|
|
- clocks = <&rcc USBH>;
|
|
- resets = <&rcc USBH_R>;
|
|
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
- companion = <&usbh_ohci>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpu: gpu@59000000 {
|
|
- compatible = "vivante,gc";
|
|
- reg = <0x59000000 0x800>;
|
|
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc GPU>, <&rcc GPU_K>;
|
|
- clock-names = "bus" ,"core";
|
|
- resets = <&rcc GPU_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dsi: dsi@5a000000 {
|
|
- compatible = "st,stm32-dsi";
|
|
- reg = <0x5a000000 0x800>;
|
|
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
- clock-names = "pclk", "ref", "px_clk";
|
|
- resets = <&rcc DSI_R>;
|
|
- reset-names = "apb";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- ltdc: display-controller@5a001000 {
|
|
- compatible = "st,stm32-ltdc";
|
|
- reg = <0x5a001000 0x400>;
|
|
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc LTDC_PX>;
|
|
- clock-names = "lcd";
|
|
- resets = <&rcc LTDC_R>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- iwdg2: watchdog@5a002000 {
|
|
- compatible = "st,stm32mp1-iwdg";
|
|
- reg = <0x5a002000 0x400>;
|
|
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
- clock-names = "pclk", "lsi";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- usbphyc: usbphyc@5a006000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32mp1-usbphyc";
|
|
- reg = <0x5a006000 0x1000>;
|
|
- clocks = <&rcc USBPHY_K>;
|
|
- resets = <&rcc USBPHY_R>;
|
|
- vdda1v1-supply = <®11>;
|
|
- vdda1v8-supply = <®18>;
|
|
- status = "disabled";
|
|
-
|
|
- usbphyc_port0: usb-phy@0 {
|
|
- #phy-cells = <0>;
|
|
- reg = <0>;
|
|
- };
|
|
-
|
|
- usbphyc_port1: usb-phy@1 {
|
|
- #phy-cells = <1>;
|
|
- reg = <1>;
|
|
- };
|
|
- };
|
|
-
|
|
- usart1: serial@5c000000 {
|
|
- compatible = "st,stm32h7-uart";
|
|
- reg = <0x5c000000 0x400>;
|
|
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc USART1_K>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- spi6: spi@5c001000 {
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- compatible = "st,stm32h7-spi";
|
|
- reg = <0x5c001000 0x400>;
|
|
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc SPI6_K>;
|
|
- resets = <&rcc SPI6_R>;
|
|
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
|
|
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
|
|
- dma-names = "rx", "tx";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c4: i2c@5c002000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x5c002000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C4_K>;
|
|
- resets = <&rcc I2C4_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- rtc: rtc@5c004000 {
|
|
- compatible = "st,stm32mp1-rtc";
|
|
- reg = <0x5c004000 0x400>;
|
|
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
- clock-names = "pclk", "rtc_ck";
|
|
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- bsec: nvmem@5c005000 {
|
|
- compatible = "st,stm32mp15-bsec";
|
|
- reg = <0x5c005000 0x400>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ts_cal1: calib@5c {
|
|
- reg = <0x5c 0x2>;
|
|
- };
|
|
- ts_cal2: calib@5e {
|
|
- reg = <0x5e 0x2>;
|
|
- };
|
|
- };
|
|
-
|
|
- i2c6: i2c@5c009000 {
|
|
- compatible = "st,stm32f7-i2c";
|
|
- reg = <0x5c009000 0x400>;
|
|
- interrupt-names = "event", "error";
|
|
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&rcc I2C6_K>;
|
|
- resets = <&rcc I2C6_R>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-
|
|
- mlahb {
|
|
- compatible = "simple-bus";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- dma-ranges = <0x00000000 0x38000000 0x10000>,
|
|
- <0x10000000 0x10000000 0x60000>,
|
|
- <0x30000000 0x30000000 0x60000>;
|
|
-
|
|
- m4_rproc: m4@10000000 {
|
|
- compatible = "st,stm32mp1-m4";
|
|
- reg = <0x10000000 0x40000>,
|
|
- <0x30000000 0x40000>,
|
|
- <0x38000000 0x10000>;
|
|
- resets = <&rcc MCU_R>;
|
|
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
|
|
- st,syscfg-tz = <&rcc 0x000 0x1>;
|
|
- status = "disabled";
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..4f9b7a9
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157a-dk1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
|
|
new file mode 100644
|
|
index 0000000..c7d65a6
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-dk1.dts
|
|
@@ -0,0 +1,44 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xd.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
|
|
+ compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..70d9afc
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-ed1-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157a-ed1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts
|
|
new file mode 100644
|
|
index 0000000..ee55ac8
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-ed1.dts
|
|
@@ -0,0 +1,52 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xd.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D eval daughter";
|
|
+ compatible = "st,stm32mp157d-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@fe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..77168a4
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-ev1-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157a-ev1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157d-ev1.dts b/arch/arm/dts/stm32mp157d-ev1.dts
|
|
new file mode 100644
|
|
index 0000000..a4752c1
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157d-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157d-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157D eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..1bed79c
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-dk2-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157c-dk2-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts
|
|
new file mode 100644
|
|
index 0000000..b57db30
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-dk2.dts
|
|
@@ -0,0 +1,185 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xf.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxac-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-dkx.dtsi"
|
|
+#include <dt-bindings/rtc/rtc-stm32.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
|
|
+ compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = ðernet0;
|
|
+ serial0 = &uart4;
|
|
+ serial1 = &usart3;
|
|
+ serial2 = &uart7;
|
|
+ serial3 = &usart2;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@da000000 {
|
|
+ reg = <0xda000000 0x4000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xde000000 {
|
|
+ reg = <0xde000000 0x02000000>;
|
|
+ no-map;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi-pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep1_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_otm8009a: panel-otm8009a@0 {
|
|
+ compatible = "orisetech,otm8009a";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ touchscreen@2a {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x2a>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ touchscreen@38 {
|
|
+ compatible = "focaltech,ft6236";
|
|
+ reg = <0x38>;
|
|
+ interrupts = <2 2>;
|
|
+ interrupt-parent = <&gpiof>;
|
|
+ interrupt-controller;
|
|
+ touchscreen-size-x = <480>;
|
|
+ touchscreen-size-y = <800>;
|
|
+ panel = <&panel_otm8009a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep1_out: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&dsi_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ st,lsco = <RTC_OUT2_RMP>;
|
|
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+/* Wifi */
|
|
+&sdmmc2 {
|
|
+ arm,primecell-periphid = <0x10153180>;
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ brcmf: bcrmf@1 {
|
|
+ reg = <1>;
|
|
+ compatible = "brcm,bcm4329-fmac";
|
|
+ };
|
|
+};
|
|
+
|
|
+/* Bluetooth */
|
|
+&usart2 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart2_pins_a>;
|
|
+ pinctrl-1 = <&usart2_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart2_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
|
|
+ compatible = "brcm,bcm43438-bt";
|
|
+ max-speed = <3000000>;
|
|
+ vbat-supply = <&v3v3>;
|
|
+ vddio-supply = <&v3v3>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&optee_memory {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..2b8d2af
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-ed1-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157c-ed1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts
|
|
new file mode 100644
|
|
index 0000000..6538069
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-ed1.dts
|
|
@@ -0,0 +1,56 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xf.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include "stm32mp15xx-edx.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F eval daughter";
|
|
+ compatible = "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ gpu_reserved: gpu@f6000000 {
|
|
+ reg = <0xf6000000 0x8000000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ optee_memory: optee@0xfe000000 {
|
|
+ reg = <0xfe000000 0x02000000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&cryp1 {
|
|
+ status="okay";
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&optee {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..0e415a1
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-ev1-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright : STMicroelectronics 2019
|
|
+ */
|
|
+
|
|
+#include "stm32mp157c-ev1-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp157f-ev1.dts b/arch/arm/dts/stm32mp157f-ev1.dts
|
|
new file mode 100644
|
|
index 0000000..0c18333
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp157f-ev1.dts
|
|
@@ -0,0 +1,86 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157f-ed1.dts"
|
|
+#include "stm32mp15xx-evx.dtsi"
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP157F eval daughter on eval mother";
|
|
+ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ aliases {
|
|
+ serial1 = &usart3;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+};
|
|
+
|
|
+&dsi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ dsi_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ dsi_out: endpoint {
|
|
+ remote-endpoint = <&dsi_panel_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_dsi: panel-dsi@0 {
|
|
+ compatible = "raydium,rm68200";
|
|
+ reg = <0>;
|
|
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
|
+ backlight = <&panel_backlight>;
|
|
+ power-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dsi_panel_in: endpoint {
|
|
+ remote-endpoint = <&dsi_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ gt9147: goodix_ts@5d {
|
|
+ compatible = "goodix,gt9147";
|
|
+ reg = <0x5d>;
|
|
+ panel = <&panel_dsi>;
|
|
+ pinctrl-0 = <&goodix_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&m_can1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&m_can1_pins_a>;
|
|
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 875adf5..0000000
|
|
--- a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,90 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AA>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 80 16>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 96 16>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 112 16>;
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 128 16>;
|
|
- };
|
|
-
|
|
- gpioj: gpio@5000b000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 144 16>;
|
|
- };
|
|
-
|
|
- gpiok: gpio@5000c000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl 0 160 8>;
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- st,package = <STM32MP_PKG_AA>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 961fa12..0000000
|
|
--- a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,62 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AB>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <6>;
|
|
- gpio-ranges = <&pinctrl 6 86 6>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <10>;
|
|
- gpio-ranges = <&pinctrl 6 102 10>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <2>;
|
|
- gpio-ranges = <&pinctrl 0 112 2>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 26600f1..0000000
|
|
--- a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,78 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AC>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 80 16>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 96 16>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 112 16>;
|
|
- };
|
|
-
|
|
- gpioi: gpio@5000a000 {
|
|
- status = "okay";
|
|
- ngpios = <12>;
|
|
- gpio-ranges = <&pinctrl 0 128 12>;
|
|
- };
|
|
- };
|
|
-
|
|
- pinctrl_z: pin-controller-z@54004000 {
|
|
- st,package = <STM32MP_PKG_AC>;
|
|
-
|
|
- gpioz: gpio@54004000 {
|
|
- status = "okay";
|
|
- ngpios = <8>;
|
|
- gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi
|
|
deleted file mode 100644
|
|
index 910113f..0000000
|
|
--- a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi
|
|
+++ /dev/null
|
|
@@ -1,62 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
-/*
|
|
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
- */
|
|
-
|
|
-#include "stm32mp157-pinctrl.dtsi"
|
|
-/ {
|
|
- soc {
|
|
- pinctrl: pin-controller@50002000 {
|
|
- st,package = <STM32MP_PKG_AD>;
|
|
-
|
|
- gpioa: gpio@50002000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 0 16>;
|
|
- };
|
|
-
|
|
- gpiob: gpio@50003000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 16 16>;
|
|
- };
|
|
-
|
|
- gpioc: gpio@50004000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 32 16>;
|
|
- };
|
|
-
|
|
- gpiod: gpio@50005000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 48 16>;
|
|
- };
|
|
-
|
|
- gpioe: gpio@50006000 {
|
|
- status = "okay";
|
|
- ngpios = <16>;
|
|
- gpio-ranges = <&pinctrl 0 64 16>;
|
|
- };
|
|
-
|
|
- gpiof: gpio@50007000 {
|
|
- status = "okay";
|
|
- ngpios = <6>;
|
|
- gpio-ranges = <&pinctrl 6 86 6>;
|
|
- };
|
|
-
|
|
- gpiog: gpio@50008000 {
|
|
- status = "okay";
|
|
- ngpios = <10>;
|
|
- gpio-ranges = <&pinctrl 6 102 10>;
|
|
- };
|
|
-
|
|
- gpioh: gpio@50009000 {
|
|
- status = "okay";
|
|
- ngpios = <2>;
|
|
- gpio-ranges = <&pinctrl 0 112 2>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi
|
|
new file mode 100644
|
|
index 0000000..5ed7e59
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xa.dtsi
|
|
@@ -0,0 +1,13 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ opp-650000000 {
|
|
+ opp-hz = /bits/ 64 <650000000>;
|
|
+ opp-microvolt = <1200000>;
|
|
+ opp-supported-hw = <0x1>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi
|
|
new file mode 100644
|
|
index 0000000..adc1568
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xc.dtsi
|
|
@@ -0,0 +1,20 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xa.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ cryp1: cryp@54001000 {
|
|
+ compatible = "st,stm32mp1-cryp";
|
|
+ reg = <0x54001000 0x400>;
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_CRYP1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi
|
|
new file mode 100644
|
|
index 0000000..faa039e
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xd.dtsi
|
|
@@ -0,0 +1,42 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+&cpu0_opp_table {
|
|
+ opp-800000000 {
|
|
+ opp-hz = /bits/ 64 <800000000>;
|
|
+ opp-microvolt = <1350000>;
|
|
+ opp-supported-hw = <0x2>;
|
|
+ };
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <1200000>;
|
|
+ opp-supported-hw = <0x2>;
|
|
+ opp-suspend;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu_thermal {
|
|
+ trips {
|
|
+ cpu-crit {
|
|
+ temperature = <105000>;
|
|
+ hysteresis = <0>;
|
|
+ type = "critical";
|
|
+ };
|
|
+
|
|
+ cpu_alert: cpu-alert {
|
|
+ temperature = <950000>;
|
|
+ hysteresis = <10000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device = <&cpu0 1 1>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi
|
|
new file mode 100644
|
|
index 0000000..77f50b9
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xf.dtsi
|
|
@@ -0,0 +1,20 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xd.dtsi"
|
|
+
|
|
+/ {
|
|
+ soc {
|
|
+ cryp1: cryp@54001000 {
|
|
+ compatible = "st,stm32mp1-cryp";
|
|
+ reg = <0x54001000 0x400>;
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&scmi0_clk CK_SCMI0_CRYP1>;
|
|
+ resets = <&scmi0_reset RST_SCMI0_CRYP1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..12f89b3
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
|
|
@@ -0,0 +1,6 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xx-dhcom-u-boot.dtsi"
|
|
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
|
|
new file mode 100644
|
|
index 0000000..dd98c7a
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
|
|
@@ -0,0 +1,88 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
|
|
+ */
|
|
+
|
|
+#include "stm32mp15xx-dhcom.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
|
|
+ compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart4;
|
|
+ ethernet0 = ðernet0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ ethernet_vio: vioregulator {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vio";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+ðernet0 {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <ðernet0_rmii_pins_a>;
|
|
+ pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ phy-mode = "rmii";
|
|
+ max-speed = <100>;
|
|
+ phy-handle = <&phy0>;
|
|
+ st,eth_ref_clk_sel;
|
|
+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
|
|
+
|
|
+ mdio0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+
|
|
+ phy0: ethernet-phy@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ ethernet0_rmii_pins_a: rmii-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
|
|
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
|
|
+ <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
|
|
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
|
|
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
|
|
+ bias-disable;
|
|
+ drive-push-pull;
|
|
+ slew-rate = <2>;
|
|
+ };
|
|
+ pins2 {
|
|
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
|
|
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
|
|
+ pins1 {
|
|
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
|
|
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
|
|
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
|
|
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
|
|
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
|
|
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
|
|
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
|
|
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
|
|
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
|
|
new file mode 100644
|
|
index 0000000..62c45de
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
|
|
@@ -0,0 +1,249 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
+/*
|
|
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
+#include "stm32mp15-u-boot.dtsi"
|
|
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
+
|
|
+/ {
|
|
+ aliases {
|
|
+ i2c1 = &i2c2;
|
|
+ i2c3 = &i2c4;
|
|
+ i2c4 = &i2c5;
|
|
+ mmc0 = &sdmmc1;
|
|
+ mmc1 = &sdmmc2;
|
|
+ spi0 = &qspi;
|
|
+ usb0 = &usbotg_hs;
|
|
+ };
|
|
+
|
|
+ config {
|
|
+ u-boot,boot-led = "heartbeat";
|
|
+ u-boot,error-led = "error";
|
|
+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ red {
|
|
+ label = "error";
|
|
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
+ default-state = "off";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ blue {
|
|
+ default-state = "on";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&i2c4_pins_a {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ pins {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pmic {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&flash0 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&qspi_clk_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi_bk1_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi_bk2_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&rcc {
|
|
+ st,clksrc = <
|
|
+ CLK_MPU_PLL1P
|
|
+ CLK_AXI_PLL2P
|
|
+ CLK_MCU_PLL3P
|
|
+ CLK_PLL12_HSE
|
|
+ CLK_PLL3_HSE
|
|
+ CLK_PLL4_HSE
|
|
+ CLK_RTC_LSE
|
|
+ CLK_MCO1_DISABLED
|
|
+ CLK_MCO2_DISABLED
|
|
+ >;
|
|
+
|
|
+ st,clkdiv = <
|
|
+ 1 /*MPU*/
|
|
+ 0 /*AXI*/
|
|
+ 0 /*MCU*/
|
|
+ 1 /*APB1*/
|
|
+ 1 /*APB2*/
|
|
+ 1 /*APB3*/
|
|
+ 1 /*APB4*/
|
|
+ 2 /*APB5*/
|
|
+ 23 /*RTC*/
|
|
+ 0 /*MCO1*/
|
|
+ 0 /*MCO2*/
|
|
+ >;
|
|
+
|
|
+ st,pkcs = <
|
|
+ CLK_CKPER_HSE
|
|
+ CLK_FMC_ACLK
|
|
+ CLK_QSPI_ACLK
|
|
+ CLK_ETH_PLL4P
|
|
+ CLK_SDMMC12_PLL4P
|
|
+ CLK_DSI_DSIPLL
|
|
+ CLK_STGEN_HSE
|
|
+ CLK_USBPHY_HSE
|
|
+ CLK_SPI2S1_PLL3Q
|
|
+ CLK_SPI2S23_PLL3Q
|
|
+ CLK_SPI45_HSI
|
|
+ CLK_SPI6_HSI
|
|
+ CLK_I2C46_HSI
|
|
+ CLK_SDMMC3_PLL4P
|
|
+ CLK_USBO_USBPHY
|
|
+ CLK_ADC_CKPER
|
|
+ CLK_CEC_LSE
|
|
+ CLK_I2C12_HSI
|
|
+ CLK_I2C35_HSI
|
|
+ CLK_UART1_HSI
|
|
+ CLK_UART24_HSI
|
|
+ CLK_UART35_HSI
|
|
+ CLK_UART6_HSI
|
|
+ CLK_UART78_HSI
|
|
+ CLK_SPDIF_PLL4P
|
|
+ CLK_FDCAN_PLL4R
|
|
+ CLK_SAI1_PLL3Q
|
|
+ CLK_SAI2_PLL3Q
|
|
+ CLK_SAI3_PLL3Q
|
|
+ CLK_SAI4_PLL3Q
|
|
+ CLK_RNG1_LSI
|
|
+ CLK_RNG2_LSI
|
|
+ CLK_LPTIM1_PCLK1
|
|
+ CLK_LPTIM23_PCLK3
|
|
+ CLK_LPTIM45_LSE
|
|
+ >;
|
|
+
|
|
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
|
|
+ pll1: st,pll@0 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <0>;
|
|
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
|
+ frac = < 0x800 >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
+ pll2: st,pll@1 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <1>;
|
|
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
+ frac = < 0x1400 >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
+ pll3: st,pll@2 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <2>;
|
|
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
+ frac = < 0x1a04 >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+
|
|
+ /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
|
|
+ pll4: st,pll@3 {
|
|
+ compatible = "st,stm32mp1-pll";
|
|
+ reg = <3>;
|
|
+ cfg = < 1 49 11 11 11 PQR(1,1,1) >;
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&sdmmc1_b4_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1_dir_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins1 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ u-boot,dm-spl;
|
|
+};
|
|
+
|
|
+&sdmmc2_b4_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc2_d47_pins_a {
|
|
+ u-boot,dm-spl;
|
|
+ pins {
|
|
+ u-boot,dm-spl;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&uart4_pins_a {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ pins1 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ };
|
|
+ pins2 {
|
|
+ u-boot,dm-pre-reloc;
|
|
+ /* pull-up on rx to avoid floating level */
|
|
+ bias-pull-up;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
|
|
new file mode 100644
|
|
index 0000000..31da41b
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
|
|
@@ -0,0 +1,379 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
|
|
+ */
|
|
+/dts-v1/;
|
|
+
|
|
+#include "stm32mp157.dtsi"
|
|
+#include "stm32mp15xc.dtsi"
|
|
+#include "stm32mp15-pinctrl.dtsi"
|
|
+#include "stm32mp15xxaa-pinctrl.dtsi"
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+
|
|
+/ {
|
|
+ memory@c0000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0xC0000000 0x40000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&cec_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dcmi {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&dcmi_pins_a>;
|
|
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
|
|
+};
|
|
+
|
|
+&dts {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ pmic: stpmic@33 {
|
|
+ compatible = "st,stpmic1";
|
|
+ reg = <0x33>;
|
|
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ status = "okay";
|
|
+
|
|
+ regulators {
|
|
+ compatible = "st,stpmic1-regulators";
|
|
+ ldo1-supply = <&v3v3>;
|
|
+ ldo2-supply = <&v3v3>;
|
|
+ ldo3-supply = <&vdd_ddr>;
|
|
+ ldo5-supply = <&v3v3>;
|
|
+ ldo6-supply = <&v3v3>;
|
|
+ pwr_sw1-supply = <&bst_out>;
|
|
+ pwr_sw2-supply = <&bst_out>;
|
|
+
|
|
+ vddcore: buck1 {
|
|
+ regulator-name = "vddcore";
|
|
+ regulator-min-microvolt = <800000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_ddr: buck2 {
|
|
+ regulator-name = "vdd_ddr";
|
|
+ regulator-min-microvolt = <1350000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd: buck3 {
|
|
+ regulator-name = "vdd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ st,mask-reset;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ v3v3: buck4 {
|
|
+ regulator-name = "v3v3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ regulator-initial-mode = <0>;
|
|
+ };
|
|
+
|
|
+ vdda: ldo1 {
|
|
+ regulator-name = "vdda";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO1 0>;
|
|
+ };
|
|
+
|
|
+ v2v8: ldo2 {
|
|
+ regulator-name = "v2v8";
|
|
+ regulator-min-microvolt = <2800000>;
|
|
+ regulator-max-microvolt = <2800000>;
|
|
+ interrupts = <IT_CURLIM_LDO2 0>;
|
|
+ };
|
|
+
|
|
+ vtt_ddr: ldo3 {
|
|
+ regulator-name = "vtt_ddr";
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_usb: ldo4 {
|
|
+ regulator-name = "vdd_usb";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ interrupts = <IT_CURLIM_LDO4 0>;
|
|
+ };
|
|
+
|
|
+ vdd_sd: ldo5 {
|
|
+ regulator-name = "vdd_sd";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO5 0>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+
|
|
+ v1v8: ldo6 {
|
|
+ regulator-name = "v1v8";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ interrupts = <IT_CURLIM_LDO6 0>;
|
|
+ };
|
|
+
|
|
+ vref_ddr: vref_ddr {
|
|
+ regulator-name = "vref_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ bst_out: boost {
|
|
+ regulator-name = "bst_out";
|
|
+ interrupts = <IT_OCP_BOOST 0>;
|
|
+ };
|
|
+
|
|
+ vbus_otg: pwr_sw1 {
|
|
+ regulator-name = "vbus_otg";
|
|
+ interrupts = <IT_OCP_OTG 0>;
|
|
+ };
|
|
+
|
|
+ vbus_sw: pwr_sw2 {
|
|
+ regulator-name = "vbus_sw";
|
|
+ interrupts = <IT_OCP_SWOUT 0>;
|
|
+ regulator-active-discharge;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ onkey {
|
|
+ compatible = "st,stpmic1-onkey";
|
|
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
+ interrupt-names = "onkey-falling", "onkey-rising";
|
|
+ power-off-time-sec = <10>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ watchdog {
|
|
+ compatible = "st,stpmic1-wdt";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ eeprom@50 {
|
|
+ compatible = "atmel,24c02";
|
|
+ reg = <0x50>;
|
|
+ pagesize = <16>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c5_pins_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ipcc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ timeout-sec = <32>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
+ mbox-names = "vq0", "vq1", "shutdown";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
|
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ flash0: mx66l51235l@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+
|
|
+ flash1: mx66l51235l@1 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <1>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
|
+ broken-cd;
|
|
+ st,sig-dir;
|
|
+ st,neg-edge;
|
|
+ st,use-ckin;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&vdd_sd>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
+ non-removable;
|
|
+ no-sd;
|
|
+ no-sdio;
|
|
+ st,sig-dir;
|
|
+ st,neg-edge;
|
|
+ bus-width = <8>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi1_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm2_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@1 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ timer@5 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers8 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm8_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@7 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm12_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@11 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbh_ehci {
|
|
+ phys = <&usbphyc_port0>;
|
|
+ phy-names = "usb";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ dr_mode = "peripheral";
|
|
+ phys = <&usbphyc_port1 0>;
|
|
+ phy-names = "usb2-phy";
|
|
+ vbus-supply = <&vbus_otg>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
|
|
new file mode 100644
|
|
index 0000000..3516938
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
|
|
@@ -0,0 +1,768 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include "stm32mp157-m4-srm.dtsi"
|
|
+#include "stm32mp157-m4-srm-pinctrl.dtsi"
|
|
+#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+
|
|
+/ {
|
|
+ memory@c0000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0xc0000000 0x20000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ mcuram2: mcuram2@10000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring0: vdev0vring0@10040000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10040000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring1: vdev0vring1@10041000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10041000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0buffer: vdev0buffer@10042000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10042000 0x4000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ mcuram: mcuram@30000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x30000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ retram: retram@38000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x38000000 0x10000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ compatible = "gpio-leds";
|
|
+ blue {
|
|
+ label = "heartbeat";
|
|
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "heartbeat";
|
|
+ default-state = "off";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ compatible = "audio-graph-card";
|
|
+ label = "STM32MP1-DK";
|
|
+ routing =
|
|
+ "Playback" , "MCLK",
|
|
+ "Capture" , "MCLK",
|
|
+ "MICL" , "Mic Bias";
|
|
+ dais = <&sai2a_port &sai2b_port &i2s2_port>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ usb_phy_tuning: usb-phy-tuning {
|
|
+ st,hs-dc-level = <2>;
|
|
+ st,fs-rftime-tuning;
|
|
+ st,hs-rftime-reduction;
|
|
+ st,hs-current-trim = <15>;
|
|
+ st,hs-impedance-trim = <1>;
|
|
+ st,squelch-level = <3>;
|
|
+ st,hs-rx-offset = <2>;
|
|
+ st,no-lsfs-sc;
|
|
+ };
|
|
+
|
|
+ vin: vin {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vin";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdda-supply = <&vdd>;
|
|
+ vref-supply = <&vrefbuf>;
|
|
+ status = "disabled";
|
|
+ adc1: adc@0 {
|
|
+ /*
|
|
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
|
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
|
+ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
|
+ * Use arbitrary margin here (e.g. 5us).
|
|
+ */
|
|
+ st,min-sample-time-nsecs = <5000>;
|
|
+ /* AIN connector, USB Type-C CC1 & CC2 */
|
|
+ st,adc-channels = <0 1 6 13 18 19>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ adc2: adc@100 {
|
|
+ /* AIN connector, USB Type-C CC1 & CC2 */
|
|
+ st,adc-channels = <0 1 2 6 18 19>;
|
|
+ st,min-sample-time-nsecs = <5000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&cec_pins_b>;
|
|
+ pinctrl-1 = <&cec_pins_sleep_b>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&cpu0{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&cpu1{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&crc1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dma1 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dts {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+ðernet0 {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ phy-mode = "rgmii-id";
|
|
+ max-speed = <1000>;
|
|
+ phy-handle = <&phy0>;
|
|
+
|
|
+ mdio0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ phy0: ethernet-phy@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ contiguous-area = <&gpu_reserved>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c1_pins_a>;
|
|
+ pinctrl-1 = <&i2c1_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <100>;
|
|
+ i2c-scl-falling-time-ns = <7>;
|
|
+ status = "okay";
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ hdmi-transmitter@39 {
|
|
+ compatible = "sil,sii9022";
|
|
+ reg = <0x39>;
|
|
+ iovcc-supply = <&v3v3_hdmi>;
|
|
+ cvcc12-supply = <&v1v2_hdmi>;
|
|
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
|
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-parent = <&gpiog>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ sii9022_in: endpoint {
|
|
+ remote-endpoint = <<dc_ep0_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@3 {
|
|
+ reg = <3>;
|
|
+ sii9022_tx_endpoint: endpoint {
|
|
+ remote-endpoint = <&i2s2_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cs42l51: cs42l51@4a {
|
|
+ compatible = "cirrus,cs42l51";
|
|
+ reg = <0x4a>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ VL-supply = <&v3v3>;
|
|
+ VD-supply = <&v1v8_audio>;
|
|
+ VA-supply = <&v1v8_audio>;
|
|
+ VAHP-supply = <&v1v8_audio>;
|
|
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
|
+ clocks = <&sai2a>;
|
|
+ clock-names = "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ cs42l51_port: port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cs42l51_tx_endpoint: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&sai2a_endpoint>;
|
|
+ frame-master;
|
|
+ bitclock-master;
|
|
+ };
|
|
+
|
|
+ cs42l51_rx_endpoint: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&sai2b_endpoint>;
|
|
+ frame-master;
|
|
+ bitclock-master;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ pinctrl-1 = <&i2c4_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ stusb1600@28 {
|
|
+ compatible = "st,stusb1600";
|
|
+ reg = <0x28>;
|
|
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-parent = <&gpioi>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&stusb1600_pins_a>;
|
|
+ status = "okay";
|
|
+ vdd-supply = <&vin>;
|
|
+
|
|
+ connector {
|
|
+ compatible = "usb-c-connector";
|
|
+ label = "USB-C";
|
|
+ power-role = "dual";
|
|
+ power-opmode = "default";
|
|
+
|
|
+ port {
|
|
+ con_usbotg_hs_ep: endpoint {
|
|
+ remote-endpoint = <&usbotg_hs_ep>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic: stpmic@33 {
|
|
+ compatible = "st,stpmic1";
|
|
+ reg = <0x33>;
|
|
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ status = "okay";
|
|
+
|
|
+ regulators {
|
|
+ compatible = "st,stpmic1-regulators";
|
|
+ buck1-supply = <&vin>;
|
|
+ buck2-supply = <&vin>;
|
|
+ buck3-supply = <&vin>;
|
|
+ buck4-supply = <&vin>;
|
|
+ ldo1-supply = <&v3v3>;
|
|
+ ldo2-supply = <&vin>;
|
|
+ ldo3-supply = <&vdd_ddr>;
|
|
+ ldo4-supply = <&vin>;
|
|
+ ldo5-supply = <&vin>;
|
|
+ ldo6-supply = <&v3v3>;
|
|
+ vref_ddr-supply = <&vin>;
|
|
+ boost-supply = <&vin>;
|
|
+ pwr_sw1-supply = <&bst_out>;
|
|
+ pwr_sw2-supply = <&bst_out>;
|
|
+
|
|
+ vddcore: buck1 {
|
|
+ regulator-name = "vddcore";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_ddr: buck2 {
|
|
+ regulator-name = "vdd_ddr";
|
|
+ regulator-min-microvolt = <1350000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd: buck3 {
|
|
+ regulator-name = "vdd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ st,mask-reset;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ v3v3: buck4 {
|
|
+ regulator-name = "v3v3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ regulator-initial-mode = <0>;
|
|
+ };
|
|
+
|
|
+ v1v8_audio: ldo1 {
|
|
+ regulator-name = "v1v8_audio";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO1 0>;
|
|
+ };
|
|
+
|
|
+ v3v3_hdmi: ldo2 {
|
|
+ regulator-name = "v3v3_hdmi";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO2 0>;
|
|
+ };
|
|
+
|
|
+ vtt_ddr: ldo3 {
|
|
+ regulator-name = "vtt_ddr";
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_usb: ldo4 {
|
|
+ regulator-name = "vdd_usb";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ interrupts = <IT_CURLIM_LDO4 0>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ vdda: ldo5 {
|
|
+ regulator-name = "vdda";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO5 0>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+
|
|
+ v1v2_hdmi: ldo6 {
|
|
+ regulator-name = "v1v2_hdmi";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-always-on;
|
|
+ interrupts = <IT_CURLIM_LDO6 0>;
|
|
+ };
|
|
+
|
|
+ vref_ddr: vref_ddr {
|
|
+ regulator-name = "vref_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ bst_out: boost {
|
|
+ regulator-name = "bst_out";
|
|
+ interrupts = <IT_OCP_BOOST 0>;
|
|
+ };
|
|
+
|
|
+ vbus_otg: pwr_sw1 {
|
|
+ regulator-name = "vbus_otg";
|
|
+ interrupts = <IT_OCP_OTG 0>;
|
|
+ };
|
|
+
|
|
+ vbus_sw: pwr_sw2 {
|
|
+ regulator-name = "vbus_sw";
|
|
+ interrupts = <IT_OCP_SWOUT 0>;
|
|
+ regulator-active-discharge = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ onkey {
|
|
+ compatible = "st,stpmic1-onkey";
|
|
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
+ interrupt-names = "onkey-falling", "onkey-rising";
|
|
+ power-off-time-sec = <10>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ watchdog {
|
|
+ compatible = "st,stpmic1-wdt";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c5_pins_a>;
|
|
+ pinctrl-1 = <&i2c5_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&i2s2 {
|
|
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2s2_pins_a>;
|
|
+ pinctrl-1 = <&i2s2_pins_sleep_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ i2s2_port: port {
|
|
+ i2s2_endpoint: endpoint {
|
|
+ remote-endpoint = <&sii9022_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ipcc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ timeout-sec = <32>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <<dc_pins_a>;
|
|
+ pinctrl-1 = <<dc_pins_sleep_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep0_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&sii9022_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
+ <&vdev0vring1>, <&vdev0buffer>;
|
|
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
+ mbox-names = "vq0", "vq1", "shutdown";
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <68 1>;
|
|
+ wakeup-source;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
|
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a: audio-controller@4400b004 {
|
|
+ #clock-cells = <0>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a_port: port {
|
|
+ sai2a_endpoint: endpoint {
|
|
+ remote-endpoint = <&cs42l51_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ dai-tdm-slot-num = <2>;
|
|
+ dai-tdm-slot-width = <32>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b: audio-controller@4400b024 {
|
|
+ dma-names = "rx";
|
|
+ st,sync = <&sai2a 2>;
|
|
+ clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
+ clock-names = "sai_ck", "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2b_port: port {
|
|
+ sai2b_endpoint: endpoint {
|
|
+ remote-endpoint = <&cs42l51_rx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ dai-tdm-slot-num = <2>;
|
|
+ dai-tdm-slot-width = <32>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
|
+ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
+ disable-wp;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc3 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
+ broken-cd;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spi4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi4_pins_a>;
|
|
+ pinctrl-1 = <&spi4_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spi5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi5_pins_a>;
|
|
+ pinctrl-1 = <&spi5_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sram {
|
|
+ dma_pool: dma_pool@0 {
|
|
+ reg = <0x50000 0x10000>;
|
|
+ pool;
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers1 {
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm1_pins_a>;
|
|
+ pinctrl-1 = <&pwm1_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@0 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers3 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm3_pins_a>;
|
|
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@2 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers4 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
|
|
+ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@3 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers5 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm5_pins_a>;
|
|
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@4 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ timer@5 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm12_pins_a>;
|
|
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@11 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ pinctrl-1 = <&uart4_sleep_pins_a>;
|
|
+ pinctrl-2 = <&uart4_idle_pins_a>;
|
|
+ pinctrl-3 = <&uart4_pins_a>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart7 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart7_pins_b>;
|
|
+ pinctrl-1 = <&uart7_sleep_pins_b>;
|
|
+ pinctrl-2 = <&uart7_idle_pins_b>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usart3 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart3_pins_b>;
|
|
+ pinctrl-1 = <&usart3_sleep_pins_b>;
|
|
+ pinctrl-2 = <&usart3_idle_pins_b>;
|
|
+ uart-has-rtscts;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usbh_ehci {
|
|
+ phys = <&usbphyc_port0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ phys = <&usbphyc_port1 0>;
|
|
+ phy-names = "usb2-phy";
|
|
+ usb-role-switch;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ usbotg_hs_ep: endpoint {
|
|
+ remote-endpoint = <&con_usbotg_hs_ep>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&usbphyc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&vrefbuf {
|
|
+ regulator-min-microvolt = <2500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ vdda-supply = <&vdd>;
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi
|
|
new file mode 100644
|
|
index 0000000..7ed6b14
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi
|
|
@@ -0,0 +1,408 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/mfd/st,stpmic1.h>
|
|
+
|
|
+/ {
|
|
+ memory@c0000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0xC0000000 0x40000000>;
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ mcuram2: mcuram2@10000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring0: vdev0vring0@10040000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10040000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0vring1: vdev0vring1@10041000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10041000 0x1000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ vdev0buffer: vdev0buffer@10042000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x10042000 0x4000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ mcuram: mcuram@30000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x30000000 0x40000>;
|
|
+ no-map;
|
|
+ };
|
|
+
|
|
+ retram: retram@38000000 {
|
|
+ compatible = "shared-dma-pool";
|
|
+ reg = <0x38000000 0x10000>;
|
|
+ no-map;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ led {
|
|
+ compatible = "gpio-leds";
|
|
+ blue {
|
|
+ label = "heartbeat";
|
|
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
|
|
+ linux,default-trigger = "heartbeat";
|
|
+ default-state = "off";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sd_switch: regulator-sd_switch {
|
|
+ compatible = "regulator-gpio";
|
|
+ regulator-name = "sd_switch";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ regulator-type = "voltage";
|
|
+ regulator-always-on;
|
|
+
|
|
+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
|
|
+ gpios-states = <0>;
|
|
+ states = <1800000 0x1 2900000 0x0>;
|
|
+ };
|
|
+
|
|
+ vin: vin {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vin";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&adc {
|
|
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
|
|
+ pinctrl-0 = <&adc1_in6_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdda-supply = <&vdda>;
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "disabled";
|
|
+ adc1: adc@0 {
|
|
+ st,adc-channels = <0 1 6>;
|
|
+ /* 16.5 ck_cycles sampling time */
|
|
+ st,min-sample-time-nsecs = <400>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu0{
|
|
+ cpu-supply = <&vddcore>;
|
|
+};
|
|
+
|
|
+&crc1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dac {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
|
|
+ vref-supply = <&vdda>;
|
|
+ status = "disabled";
|
|
+ dac1: dac@1 {
|
|
+ status = "okay";
|
|
+ };
|
|
+ dac2: dac@2 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&dma1 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dma2 {
|
|
+ sram = <&dma_pool>;
|
|
+};
|
|
+
|
|
+&dts {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hash1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c4_pins_a>;
|
|
+ pinctrl-1 = <&i2c4_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ clock-frequency = <400000>;
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ pmic: stpmic@33 {
|
|
+ compatible = "st,stpmic1";
|
|
+ reg = <0x33>;
|
|
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ status = "okay";
|
|
+
|
|
+ regulators {
|
|
+ compatible = "st,stpmic1-regulators";
|
|
+ buck1-supply = <&vin>;
|
|
+ buck2-supply = <&vin>;
|
|
+ buck3-supply = <&vin>;
|
|
+ buck4-supply = <&vin>;
|
|
+ ldo1-supply = <&v3v3>;
|
|
+ ldo2-supply = <&v3v3>;
|
|
+ ldo3-supply = <&vdd_ddr>;
|
|
+ ldo4-supply = <&vin>;
|
|
+ ldo5-supply = <&v3v3>;
|
|
+ ldo6-supply = <&v3v3>;
|
|
+ vref_ddr-supply = <&vin>;
|
|
+ boost-supply = <&vin>;
|
|
+ pwr_sw1-supply = <&bst_out>;
|
|
+ pwr_sw2-supply = <&bst_out>;
|
|
+
|
|
+ vddcore: buck1 {
|
|
+ regulator-name = "vddcore";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_ddr: buck2 {
|
|
+ regulator-name = "vdd_ddr";
|
|
+ regulator-min-microvolt = <1350000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-always-on;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd: buck3 {
|
|
+ regulator-name = "vdd";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ st,mask-reset;
|
|
+ regulator-initial-mode = <0>;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ v3v3: buck4 {
|
|
+ regulator-name = "v3v3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ regulator-initial-mode = <0>;
|
|
+ };
|
|
+
|
|
+ vdda: ldo1 {
|
|
+ regulator-name = "vdda";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO1 0>;
|
|
+ };
|
|
+
|
|
+ v2v8: ldo2 {
|
|
+ regulator-name = "v2v8";
|
|
+ regulator-min-microvolt = <2800000>;
|
|
+ regulator-max-microvolt = <2800000>;
|
|
+ interrupts = <IT_CURLIM_LDO2 0>;
|
|
+ };
|
|
+
|
|
+ vtt_ddr: ldo3 {
|
|
+ regulator-name = "vtt_ddr";
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ vdd_usb: ldo4 {
|
|
+ regulator-name = "vdd_usb";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ interrupts = <IT_CURLIM_LDO4 0>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ vdd_sd: ldo5 {
|
|
+ regulator-name = "vdd_sd";
|
|
+ regulator-min-microvolt = <2900000>;
|
|
+ regulator-max-microvolt = <2900000>;
|
|
+ interrupts = <IT_CURLIM_LDO5 0>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+
|
|
+ v1v8: ldo6 {
|
|
+ regulator-name = "v1v8";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ interrupts = <IT_CURLIM_LDO6 0>;
|
|
+ };
|
|
+
|
|
+ vref_ddr: vref_ddr {
|
|
+ regulator-name = "vref_ddr";
|
|
+ regulator-always-on;
|
|
+ regulator-over-current-protection;
|
|
+ };
|
|
+
|
|
+ bst_out: boost {
|
|
+ regulator-name = "bst_out";
|
|
+ interrupts = <IT_OCP_BOOST 0>;
|
|
+ };
|
|
+
|
|
+ vbus_otg: pwr_sw1 {
|
|
+ regulator-name = "vbus_otg";
|
|
+ interrupts = <IT_OCP_OTG 0>;
|
|
+ };
|
|
+
|
|
+ vbus_sw: pwr_sw2 {
|
|
+ regulator-name = "vbus_sw";
|
|
+ interrupts = <IT_OCP_SWOUT 0>;
|
|
+ regulator-active-discharge = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ onkey {
|
|
+ compatible = "st,stpmic1-onkey";
|
|
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
+ interrupt-names = "onkey-falling", "onkey-rising";
|
|
+ power-off-time-sec = <10>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ watchdog {
|
|
+ compatible = "st,stpmic1-wdt";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ipcc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iwdg2 {
|
|
+ timeout-sec = <32>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&m4_rproc {
|
|
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
+ <&vdev0vring1>, <&vdev0buffer>;
|
|
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
|
+ mbox-names = "vq0", "vq1", "shutdown";
|
|
+ interrupt-parent = <&exti>;
|
|
+ interrupts = <68 1>;
|
|
+ wakeup-source;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwr_regulators {
|
|
+ vdd-supply = <&vdd>;
|
|
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&rng1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rtc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
|
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
+ disable-wp;
|
|
+ st,sig-dir;
|
|
+ st,neg-edge;
|
|
+ st,use-ckin;
|
|
+ bus-width = <4>;
|
|
+ vmmc-supply = <&vdd_sd>;
|
|
+ vqmmc-supply = <&sd_switch>;
|
|
+ sd-uhs-sdr12;
|
|
+ sd-uhs-sdr25;
|
|
+ sd-uhs-sdr50;
|
|
+ sd-uhs-ddr50;
|
|
+ sd-uhs-sdr104;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc2 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
|
+ non-removable;
|
|
+ no-sd;
|
|
+ no-sdio;
|
|
+ st,neg-edge;
|
|
+ bus-width = <8>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ vqmmc-supply = <&vdd>;
|
|
+ mmc-ddr-3_3v;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sram {
|
|
+ dma_pool: dma_pool@0 {
|
|
+ reg = <0x50000 0x10000>;
|
|
+ pool;
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers6 {
|
|
+ status = "okay";
|
|
+ /* spare dmas for other usage */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ timer@5 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ pinctrl-1 = <&uart4_sleep_pins_a>;
|
|
+ pinctrl-2 = <&uart4_idle_pins_a>;
|
|
+ pinctrl-3 = <&uart4_pins_a>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ vbus-supply = <&vbus_otg>;
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ phy-supply = <&vdd_usb>;
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi
|
|
new file mode 100644
|
|
index 0000000..07cb93d
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi
|
|
@@ -0,0 +1,680 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include <dt-bindings/soc/stm32-hdp.h>
|
|
+
|
|
+/ {
|
|
+ clocks {
|
|
+ clk_ext_camera: clk-ext-camera {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ joystick {
|
|
+ compatible = "gpio-keys";
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-0 = <&joystick_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ button-0 {
|
|
+ label = "JoySel";
|
|
+ linux,code = <KEY_ENTER>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-1 {
|
|
+ label = "JoyDown";
|
|
+ linux,code = <KEY_DOWN>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-2 {
|
|
+ label = "JoyLeft";
|
|
+ linux,code = <KEY_LEFT>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-3 {
|
|
+ label = "JoyRight";
|
|
+ linux,code = <KEY_RIGHT>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ button-4 {
|
|
+ label = "JoyUp";
|
|
+ linux,code = <KEY_UP>;
|
|
+ interrupt-parent = <&stmfx_pinctrl>;
|
|
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ panel_backlight: panel-backlight {
|
|
+ compatible = "gpio-backlight";
|
|
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
|
+ default-on;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ status = "okay";
|
|
+
|
|
+ spdif_out_port: port {
|
|
+ spdif_out_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai4a_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_in: spdif-in {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dir";
|
|
+ status = "okay";
|
|
+
|
|
+ spdif_in_port: port {
|
|
+ spdif_in_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdifrx_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ compatible = "audio-graph-card";
|
|
+ label = "STM32MP1-EV";
|
|
+ routing =
|
|
+ "AIF1CLK" , "MCLK1",
|
|
+ "AIF2CLK" , "MCLK1",
|
|
+ "IN1LN" , "MICBIAS2",
|
|
+ "DMIC2DAT" , "MICBIAS1",
|
|
+ "DMIC1DAT" , "MICBIAS1";
|
|
+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port
|
|
+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ dmic0: dmic-0 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic0";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic0_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic1: dmic-1 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic1";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic1_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic2: dmic-2 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic2";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic2_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint2>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dmic3: dmic-3 {
|
|
+ compatible = "dmic-codec";
|
|
+ #sound-dai-cells = <1>;
|
|
+ sound-name-prefix = "dmic3";
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ dmic3_endpoint: endpoint {
|
|
+ remote-endpoint = <&dfsdm_endpoint3>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb_phy_tuning: usb-phy-tuning {
|
|
+ st,hs-dc-level = <2>;
|
|
+ st,fs-rftime-tuning;
|
|
+ st,hs-rftime-reduction;
|
|
+ st,hs-current-trim = <15>;
|
|
+ st,hs-impedance-trim = <1>;
|
|
+ st,squelch-level = <3>;
|
|
+ st,hs-rx-offset = <2>;
|
|
+ st,no-lsfs-sc;
|
|
+ };
|
|
+};
|
|
+
|
|
+&cec {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&cec_pins_a>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dcmi {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&dcmi_pins_a>;
|
|
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
|
|
+
|
|
+ port {
|
|
+ dcmi_0: endpoint {
|
|
+ remote-endpoint = <&ov5640_0>;
|
|
+ bus-width = <8>;
|
|
+ hsync-active = <0>;
|
|
+ vsync-active = <0>;
|
|
+ pclk-sample = <1>;
|
|
+ pclk-max-frequency = <77000000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&dfsdm {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&dfsdm_clkout_pins_a
|
|
+ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>;
|
|
+ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a
|
|
+ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>;
|
|
+ spi-max-frequency = <2048000>;
|
|
+
|
|
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
|
|
+ clock-names = "dfsdm", "audio";
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm0: filter@0 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <3>;
|
|
+ st,adc-channel-names = "dmic_u1";
|
|
+ st,adc-channel-types = "SPI_R";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm0: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm0 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm0_port: port {
|
|
+ dfsdm_endpoint0: endpoint {
|
|
+ remote-endpoint = <&dmic0_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm1: filter@1 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <1>;
|
|
+ st,adc-channel-names = "dmic_u2";
|
|
+ st,adc-channel-types = "SPI_F";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm1: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm1 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm1_port: port {
|
|
+ dfsdm_endpoint1: endpoint {
|
|
+ remote-endpoint = <&dmic1_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm2: filter@2 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <3>;
|
|
+ st,adc-channel-names = "dmic_u3";
|
|
+ st,adc-channel-types = "SPI_F";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm2: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm2 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm2_port: port {
|
|
+ dfsdm_endpoint2: endpoint {
|
|
+ remote-endpoint = <&dmic2_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dfsdm3: filter@3 {
|
|
+ compatible = "st,stm32-dfsdm-dmic";
|
|
+ st,adc-channels = <1>;
|
|
+ st,adc-channel-names = "dmic_u4";
|
|
+ st,adc-channel-types = "SPI_R";
|
|
+ st,adc-channel-clk-src = "CLKOUT";
|
|
+ st,filter-order = <3>;
|
|
+ status = "okay";
|
|
+
|
|
+ asoc_pdm3: dfsdm-dai {
|
|
+ compatible = "st,stm32h7-dfsdm-dai";
|
|
+ #sound-dai-cells = <0>;
|
|
+ io-channels = <&dfsdm3 0>;
|
|
+ status = "okay";
|
|
+
|
|
+ dfsdm3_port: port {
|
|
+ dfsdm_endpoint3: endpoint {
|
|
+ remote-endpoint = <&dmic3_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+ðernet0 {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
|
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ phy-mode = "rgmii-id";
|
|
+ max-speed = <1000>;
|
|
+ phy-handle = <&phy0>;
|
|
+
|
|
+ mdio0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ phy0: ethernet-phy@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&fmc {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&fmc_pins_a>;
|
|
+ pinctrl-1 = <&fmc_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ nand-on-flash-bbt;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&hdp {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
|
|
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
|
|
+ status = "disabled";
|
|
+
|
|
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
|
|
+ STM32_HDP(6, HDP6_GPOVAL_6) |
|
|
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c2_pins_a>;
|
|
+ pinctrl-1 = <&i2c2_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ status = "okay";
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+
|
|
+ wm8994: wm8994@1b {
|
|
+ compatible = "wlf,wm8994";
|
|
+ #sound-dai-cells = <0>;
|
|
+ reg = <0x1b>;
|
|
+ status = "okay";
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+
|
|
+ DBVDD-supply = <&vdd>;
|
|
+ SPKVDD1-supply = <&vdd>;
|
|
+ SPKVDD2-supply = <&vdd>;
|
|
+ AVDD2-supply = <&v1v8>;
|
|
+ CPVDD-supply = <&v1v8>;
|
|
+
|
|
+ wlf,ldoena-always-driven;
|
|
+
|
|
+ clocks = <&sai2a>;
|
|
+ clock-names = "MCLK1";
|
|
+
|
|
+ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>;
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ wm8994_tx_port: port@0 {
|
|
+ reg = <0>;
|
|
+ wm8994_tx_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai2a_endpoint>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wm8994_rx_port: port@1 {
|
|
+ reg = <1>;
|
|
+ wm8994_rx_endpoint: endpoint {
|
|
+ remote-endpoint = <&sai2b_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ov5640: camera@3c {
|
|
+ compatible = "ovti,ov5640";
|
|
+ reg = <0x3c>;
|
|
+ clocks = <&clk_ext_camera>;
|
|
+ clock-names = "xclk";
|
|
+ DOVDD-supply = <&v2v8>;
|
|
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
|
|
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
|
|
+ rotation = <180>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ ov5640_0: endpoint {
|
|
+ remote-endpoint = <&dcmi_0>;
|
|
+ bus-width = <8>;
|
|
+ data-shift = <2>; /* lines 9:2 are used */
|
|
+ hsync-active = <0>;
|
|
+ vsync-active = <0>;
|
|
+ pclk-sample = <1>;
|
|
+ pclk-max-frequency = <77000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ stmfx: stmfx@42 {
|
|
+ compatible = "st,stmfx-0300";
|
|
+ reg = <0x42>;
|
|
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-parent = <&gpioi>;
|
|
+ vdd-supply = <&v3v3>;
|
|
+
|
|
+ stmfx_pinctrl: stmfx-pin-controller {
|
|
+ compatible = "st,stmfx-0300-pinctrl";
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
|
+
|
|
+ goodix_pins: goodix {
|
|
+ pins = "gpio14";
|
|
+ bias-pull-down;
|
|
+ };
|
|
+
|
|
+ joystick_pins: joystick {
|
|
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
|
+ bias-pull-down;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ pmic: stpmic@33 {
|
|
+ regulators {
|
|
+ v1v8: ldo6 {
|
|
+ regulator-enable-ramp-delay = <300000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c5 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&i2c5_pins_a>;
|
|
+ pinctrl-1 = <&i2c5_pins_sleep_a>;
|
|
+ i2c-scl-rising-time-ns = <185>;
|
|
+ i2c-scl-falling-time-ns = <20>;
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+<dc {
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ltdc_ep0_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dsi_in>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&qspi {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
|
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+
|
|
+ flash0: mx66l51235l@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+
|
|
+ flash1: mx66l51235l@1 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <1>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sai2 {
|
|
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>;
|
|
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a: audio-controller@4400b004 {
|
|
+ #clock-cells = <0>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI2_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2a_port: port {
|
|
+ sai2a_endpoint: endpoint {
|
|
+ remote-endpoint = <&wm8994_tx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sai2b: audio-controller@4400b024 {
|
|
+ dma-names = "rx";
|
|
+ clocks = <&rcc SAI2_K>, <&sai2a>;
|
|
+ clock-names = "sai_ck", "MCLK";
|
|
+ status = "okay";
|
|
+
|
|
+ sai2b_port: port {
|
|
+ sai2b_endpoint: endpoint {
|
|
+ remote-endpoint = <&wm8994_rx_endpoint>;
|
|
+ format = "i2s";
|
|
+ mclk-fs = <256>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sai4 {
|
|
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
|
+ clock-names = "pclk", "x8k", "x11k";
|
|
+ status = "okay";
|
|
+
|
|
+ sai4a: audio-controller@50027004 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&sai4a_pins_a>;
|
|
+ pinctrl-1 = <&sai4a_sleep_pins_a>;
|
|
+ dma-names = "tx";
|
|
+ clocks = <&rcc SAI4_K>;
|
|
+ clock-names = "sai_ck";
|
|
+ st,iec60958;
|
|
+ status = "okay";
|
|
+
|
|
+ sai4a_port: port {
|
|
+ sai4a_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdif_out_endpoint>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdmmc3 {
|
|
+ pinctrl-names = "default", "opendrain", "sleep";
|
|
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
+ vmmc-supply = <&v3v3>;
|
|
+ broken-cd;
|
|
+ st,neg-edge;
|
|
+ bus-width = <4>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&spdifrx {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spdifrx_pins_a>;
|
|
+ pinctrl-1 = <&spdifrx_sleep_pins_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ spdifrx_port: port {
|
|
+ spdifrx_endpoint: endpoint {
|
|
+ remote-endpoint = <&spdif_in_endpoint>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ pinctrl-0 = <&spi1_pins_a>;
|
|
+ pinctrl-1 = <&spi1_sleep_pins_a>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&timers2 {
|
|
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm2_pins_a>;
|
|
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@1 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers8 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm8_pins_a>;
|
|
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@7 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&timers12 {
|
|
+ /delete-property/dmas;
|
|
+ /delete-property/dma-names;
|
|
+ status = "disabled";
|
|
+ pwm {
|
|
+ pinctrl-0 = <&pwm12_pins_a>;
|
|
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
+ status = "okay";
|
|
+ };
|
|
+ timer@11 {
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&usart3 {
|
|
+ pinctrl-names = "default", "sleep", "idle";
|
|
+ pinctrl-0 = <&usart3_pins_a>;
|
|
+ pinctrl-1 = <&usart3_sleep_pins_a>;
|
|
+ pinctrl-2 = <&usart3_idle_pins_a>;
|
|
+ uart-has-rtscts;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usbh_ehci {
|
|
+ phys = <&usbphyc_port0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg_hs {
|
|
+ pinctrl-0 = <&usbotg_hs_pins_a>;
|
|
+ pinctrl-names = "default";
|
|
+ phys = <&usbphyc_port1 0>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphyc_port0 {
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
+
|
|
+&usbphyc_port1 {
|
|
+ st,phy-tuning = <&usb_phy_tuning>;
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..64e566b
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
|
|
@@ -0,0 +1,85 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AA>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 80 16>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 96 16>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 112 16>;
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 128 16>;
|
|
+ };
|
|
+
|
|
+ gpioj: gpio@5000b000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 144 16>;
|
|
+ };
|
|
+
|
|
+ gpiok: gpio@5000c000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl 0 160 8>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ st,package = <STM32MP_PKG_AA>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..d29af89
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
|
|
@@ -0,0 +1,57 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AB>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <6>;
|
|
+ gpio-ranges = <&pinctrl 6 86 6>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <10>;
|
|
+ gpio-ranges = <&pinctrl 6 102 10>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 112 2>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..5d8199f
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
|
|
@@ -0,0 +1,73 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AC>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 80 16>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 96 16>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 112 16>;
|
|
+ };
|
|
+
|
|
+ gpioi: gpio@5000a000 {
|
|
+ status = "okay";
|
|
+ ngpios = <12>;
|
|
+ gpio-ranges = <&pinctrl 0 128 12>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl_z {
|
|
+ st,package = <STM32MP_PKG_AC>;
|
|
+
|
|
+ gpioz: gpio@54004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <8>;
|
|
+ gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
|
|
new file mode 100644
|
|
index 0000000..023f540
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
|
|
@@ -0,0 +1,57 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
|
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
|
|
+ */
|
|
+
|
|
+&pinctrl {
|
|
+ st,package = <STM32MP_PKG_AD>;
|
|
+
|
|
+ gpioa: gpio@50002000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 0 16>;
|
|
+ };
|
|
+
|
|
+ gpiob: gpio@50003000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 16 16>;
|
|
+ };
|
|
+
|
|
+ gpioc: gpio@50004000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 32 16>;
|
|
+ };
|
|
+
|
|
+ gpiod: gpio@50005000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 48 16>;
|
|
+ };
|
|
+
|
|
+ gpioe: gpio@50006000 {
|
|
+ status = "okay";
|
|
+ ngpios = <16>;
|
|
+ gpio-ranges = <&pinctrl 0 64 16>;
|
|
+ };
|
|
+
|
|
+ gpiof: gpio@50007000 {
|
|
+ status = "okay";
|
|
+ ngpios = <6>;
|
|
+ gpio-ranges = <&pinctrl 6 86 6>;
|
|
+ };
|
|
+
|
|
+ gpiog: gpio@50008000 {
|
|
+ status = "okay";
|
|
+ ngpios = <10>;
|
|
+ gpio-ranges = <&pinctrl 6 102 10>;
|
|
+ };
|
|
+
|
|
+ gpioh: gpio@50009000 {
|
|
+ status = "okay";
|
|
+ ngpios = <2>;
|
|
+ gpio-ranges = <&pinctrl 0 112 2>;
|
|
+ };
|
|
+};
|
|
--
|
|
2.7.4
|
|
|