296 lines
11 KiB
Diff
296 lines
11 KiB
Diff
From 2f115dde2ef6e6e72ff6439f27bc2e20f83b5d10 Mon Sep 17 00:00:00 2001
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From: Antonio Borneo <borneo.antonio@gmail.com>
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Date: Fri, 29 May 2020 17:22:33 +0200
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Subject: [PATCH] fixes for gcc-10 build, macos build, CM4 halt, stlink J28 and
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j37
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Change-Id: If6c44bc94debc305aff1837d74b282f97e7c596a
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Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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---
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src/flash/nor/jtagspi.c | 19 +++++++++++++++----
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src/flash/nor/nrf5.c | 10 +++++++---
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src/jtag/drivers/bitbang.h | 2 +-
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src/jtag/drivers/stlink_usb.c | 32 ++++++++++++++++++++++++++------
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src/server/gdb_server.c | 2 +-
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src/target/cortex_m.c | 21 +++++++++++++++++----
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src/target/startup.tcl | 2 +-
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tcl/target/stm32mp15x.cfg | 2 +-
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8 files changed, 69 insertions(+), 21 deletions(-)
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diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
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index f6e311ab8..73b1c7a26 100644
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--- a/src/flash/nor/jtagspi.c
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+++ b/src/flash/nor/jtagspi.c
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@@ -228,13 +228,16 @@ static int jtagspi_probe(struct flash_bank *bank)
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return ERROR_OK;
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}
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-static void jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
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+static int jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
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{
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uint8_t buf;
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- if (jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, &buf, -8) == ERROR_OK) {
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+ int err = jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, &buf, -8);
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+ if (err == ERROR_OK) {
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*status = buf;
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/* LOG_DEBUG("status=0x%08" PRIx32, *status); */
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}
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+
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+ return err;
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}
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static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
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@@ -245,7 +248,11 @@ static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
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do {
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dt = timeval_ms() - t0;
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- jtagspi_read_status(bank, &status);
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+
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+ int retval = jtagspi_read_status(bank, &status);
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+ if (retval != ERROR_OK)
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+ return retval;
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+
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if ((status & SPIFLASH_BSY_BIT) == 0) {
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LOG_DEBUG("waited %" PRId64 " ms", dt);
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return ERROR_OK;
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@@ -262,7 +269,11 @@ static int jtagspi_write_enable(struct flash_bank *bank)
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uint32_t status;
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jtagspi_cmd(bank, SPIFLASH_WRITE_ENABLE, NULL, NULL, 0);
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- jtagspi_read_status(bank, &status);
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+
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+ int retval = jtagspi_read_status(bank, &status);
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+ if (retval != ERROR_OK)
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+ return retval;
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+
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if ((status & SPIFLASH_WE_BIT) == 0) {
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LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
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return ERROR_FAIL;
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diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
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index 8422589b8..5bef8487c 100644
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--- a/src/flash/nor/nrf5.c
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+++ b/src/flash/nor/nrf5.c
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@@ -570,10 +570,14 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
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static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
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{
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- h_u32_to_be((uint8_t *)bf, variant);
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- bf[4] = '\0';
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- if (isalnum(bf[0]) && isalnum(bf[1]) && isalnum(bf[2]) && isalnum(bf[3]))
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+ uint8_t b[4];
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+
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+ h_u32_to_be(b, variant);
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+ if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
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+ memcpy(bf, b, 4);
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+ bf[4] = 0;
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return true;
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+ }
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strcpy(bf, "xxxx");
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return false;
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diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
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index edb779cad..bbbc693df 100644
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--- a/src/jtag/drivers/bitbang.h
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+++ b/src/jtag/drivers/bitbang.h
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@@ -56,7 +56,7 @@ struct bitbang_interface {
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void (*swdio_drive)(bool on);
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};
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-const struct swd_driver bitbang_swd;
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+extern const struct swd_driver bitbang_swd;
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extern bool swd_mode;
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diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
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index 6c0601d0e..83bb89046 100644
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--- a/src/jtag/drivers/stlink_usb.c
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+++ b/src/jtag/drivers/stlink_usb.c
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@@ -335,6 +335,7 @@ enum stlink_mode {
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#define STLINK_F_HAS_AP_INIT BIT(7)
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#define STLINK_F_HAS_DPBANKSEL BIT(8)
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#define STLINK_F_HAS_RW8_512BYTES BIT(9)
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+#define STLINK_F_FIX_CLOSE_AP BIT(10)
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/* aliases */
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#define STLINK_F_HAS_TARGET_VOLT STLINK_F_HAS_TRACE
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@@ -379,6 +380,7 @@ static int stlink_swim_status(void *handle);
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void stlink_dump_speed_map(const struct speed_map *map, unsigned int map_size);
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static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map);
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static int stlink_speed(void *handle, int khz, bool query);
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+static int stlink_usb_open_ap(void *handle, unsigned short apsel);
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/** */
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static unsigned int stlink_usb_block(void *handle)
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@@ -852,7 +854,7 @@ static int stlink_cmd_allow_retry(void *handle, const uint8_t *buf, int size)
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res = stlink_usb_error_check(handle);
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if (res == ERROR_WAIT && retries < MAX_WAIT_RETRIES) {
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- useconds_t delay_us = (1<<retries++) * 1000;
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+ unsigned int delay_us = (1<<retries++) * 1000;
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LOG_DEBUG("stlink_cmd_allow_retry ERROR_WAIT, retry %d, delaying %u microseconds", retries, delay_us);
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usleep(delay_us);
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continue;
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@@ -1050,6 +1052,10 @@ static int stlink_usb_version(void *handle)
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if (h->version.jtag >= 28)
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flags |= STLINK_F_HAS_AP_INIT;
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+ /* API required to return proper error code on close AP from J29 */
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+ if (h->version.jtag >= 29)
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+ flags |= STLINK_F_FIX_CLOSE_AP;
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+
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/* Banked regs (DPv1 & DPv2) support from V2J32 */
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/* API to read memory without address increment from V2J32 */
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/* Memory R/W supports CSW from V2J32 */
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@@ -1080,6 +1086,9 @@ static int stlink_usb_version(void *handle)
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/* API required to init AP before any AP access */
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flags |= STLINK_F_HAS_AP_INIT;
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+ /* API required to return proper error code on close AP */
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+ flags |= STLINK_F_FIX_CLOSE_AP;
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+
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/* Banked regs (DPv1 & DPv2) support from V3J2 */
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/* API to read memory without address increment from V3J2 */
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/* Memory R/W supports CSW from V3J2 */
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@@ -3121,6 +3130,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
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h->max_mem_packet = (1 << 10);
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uint8_t buffer[4];
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+ stlink_usb_open_ap(h, STLINK_HLA_AP_NUM);
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err = stlink_usb_read_mem32(h, STLINK_HLA_AP_NUM, STLINK_HLA_CSW, CPUID, 4, buffer);
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if (err == ERROR_OK) {
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uint32_t cpuid = le_to_h_u32(buffer);
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@@ -3225,7 +3235,12 @@ static int stlink_usb_close_access_port(void *handle, unsigned char ap_num)
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h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_CLOSE_AP_DBG;
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h->cmdbuf[h->cmdidx++] = ap_num;
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- return stlink_usb_xfer_errcheck(handle, h->databuf, 2);
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+ /* ignore incorrectly returned error on bogus FW */
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+ if (h->version.flags & STLINK_F_FIX_CLOSE_AP)
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+ return stlink_usb_xfer_errcheck(handle, h->databuf, 2);
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+ else
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+ return stlink_usb_xfer_noerrcheck(handle, h->databuf, 2);
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+
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}
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/** */
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@@ -3343,13 +3358,13 @@ static int stlink_dap_get_and_clear_error(void)
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return retval;
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}
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-/** */
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-static int stlink_dap_open_ap(unsigned short apsel)
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+static int stlink_usb_open_ap(void *handle, unsigned short apsel)
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{
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+ struct stlink_usb_handle_s *h = handle;
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int retval;
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/* nothing to do on old versions */
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- if (!(stlink_dap_handle->version.flags & STLINK_F_HAS_AP_INIT))
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+ if (!(h->version.flags & STLINK_F_HAS_AP_INIT))
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return ERROR_OK;
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if (apsel > DP_APSEL_MAX)
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@@ -3358,7 +3373,7 @@ static int stlink_dap_open_ap(unsigned short apsel)
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if (test_bit(apsel, opened_ap))
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return ERROR_OK;
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- retval = stlink_usb_init_access_port(stlink_dap_handle, apsel);
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+ retval = stlink_usb_init_access_port(h, apsel);
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if (retval != ERROR_OK)
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return retval;
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@@ -3367,6 +3382,11 @@ static int stlink_dap_open_ap(unsigned short apsel)
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return ERROR_OK;
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}
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+static int stlink_dap_open_ap(unsigned short apsel)
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+{
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+ return stlink_usb_open_ap(stlink_dap_handle, apsel);
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+}
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+
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/** */
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static int stlink_dap_closeall_ap(void)
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{
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diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
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index 0ca4fa4ee..3f2632b03 100644
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--- a/src/server/gdb_server.c
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+++ b/src/server/gdb_server.c
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@@ -3489,7 +3489,7 @@ static int gdb_target_start(struct target *target, const char *port)
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if (NULL == gdb_service)
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return -ENOMEM;
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- LOG_DEBUG("starting gdb server for %s on %s", target_name(target), port);
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+ LOG_INFO("starting gdb server for %s on %s", target_name(target), port);
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gdb_service->target = target;
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gdb_service->core[0] = -1;
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diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
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index 9a1f2b16f..dbd8ee088 100644
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--- a/src/target/cortex_m.c
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+++ b/src/target/cortex_m.c
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@@ -710,11 +710,11 @@ static int cortex_m_soft_reset_halt(struct target *target)
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uint32_t dcb_dhcsr = 0;
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int retval, timeout = 0;
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- /* soft_reset_halt is deprecated on cortex_m as the same functionality
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- * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
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- * As this reset only used VC_CORERESET it would only ever reset the cortex_m
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+ /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
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+ * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
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+ * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
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* core, not the peripherals */
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- LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
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+ LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
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/* Set C_DEBUGEN */
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retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
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@@ -2231,6 +2231,19 @@ int cortex_m_examine(struct target *target)
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armv7m->debug_ap->tar_autoincr_block = (1 << 10);
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}
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+ /* Enable debug requests */
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+ retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
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+ if (retval != ERROR_OK)
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+ return retval;
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+ if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
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+ uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
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+
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+ retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
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+ if (retval != ERROR_OK)
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+ return retval;
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+ cortex_m->dcb_dhcsr = dhcsr;
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+ }
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+
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/* Configure trace modules */
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retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
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if (retval != ERROR_OK)
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diff --git a/src/target/startup.tcl b/src/target/startup.tcl
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index 976cd2af5..164a0bad8 100644
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--- a/src/target/startup.tcl
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+++ b/src/target/startup.tcl
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@@ -205,7 +205,7 @@ proc init_target_events {} {
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foreach t $targets {
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set_default_target_event $t gdb-flash-erase-start "reset init"
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set_default_target_event $t gdb-flash-write-end "reset halt"
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- set_default_target_event $t gdb-attach "halt"
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+ set_default_target_event $t gdb-attach "halt 1000"
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}
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}
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diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
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index 7f0d19c4d..f2ba94eec 100644
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--- a/tcl/target/stm32mp15x.cfg
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+++ b/tcl/target/stm32mp15x.cfg
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@@ -114,7 +114,7 @@ $_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug}
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$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
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$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}
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$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
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-$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_halt}}
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+$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
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$_CHIPNAME.ap1 configure -event examine-start {dap init}
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$_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug}
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$_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1}
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--
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2.26.2
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