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meta-st-stm32mp/recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0007-v5.15-stm32mp-r2.1-DRM...

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From 6c74d8a9e9dd425dc13d45fcd0c95e0b7dda589b Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:40:32 +0200
Subject: [PATCH 07/22] v5.15-stm32mp-r2.1 DRM
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
drivers/gpu/drm/bridge/sii902x.c | 100 +-
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 5 +-
drivers/gpu/drm/drm_atomic_uapi.c | 4 +
drivers/gpu/drm/drm_bridge.c | 10 +-
drivers/gpu/drm/drm_connector.c | 62 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/panel/panel-orisetech-otm8009a.c | 163 ++-
drivers/gpu/drm/panel/panel-raydium-rm68200.c | 76 +-
drivers/gpu/drm/panel/panel-rocktech-hx8394.c | 432 +++++++
drivers/gpu/drm/panel/panel-simple.c | 16 +
drivers/gpu/drm/stm/drv.c | 6 +
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 118 +-
drivers/gpu/drm/stm/ltdc.c | 1143 ++++++++++++++---
drivers/gpu/drm/stm/ltdc.h | 25 +-
drivers/video/backlight/gpio_backlight.c | 7 +-
drivers/video/fbdev/simplefb.c | 21 +-
include/drm/bridge/dw_mipi_dsi.h | 4 +-
include/drm/drm_connector.h | 14 +
19 files changed, 1918 insertions(+), 298 deletions(-)
create mode 100644 drivers/gpu/drm/panel/panel-rocktech-hx8394.c
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c
index 89558e581530..69208ead5384 100644
--- a/drivers/gpu/drm/bridge/sii902x.c
+++ b/drivers/gpu/drm/bridge/sii902x.c
@@ -16,6 +16,7 @@
#include <linux/i2c-mux.h>
#include <linux/i2c.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/clk.h>
@@ -162,6 +163,11 @@
#define SII902X_AUDIO_PORT_INDEX 3
+/* CEC device */
+#define SII902X_CEC_I2C_ADDR 0x30
+
+#define SII902X_CEC_SETUP 0x8e
+
struct sii902x {
struct i2c_client *i2c;
struct regmap *regmap;
@@ -170,6 +176,7 @@ struct sii902x {
struct gpio_desc *reset_gpio;
struct i2c_mux_core *i2cmux;
struct regulator_bulk_data supplies[2];
+ struct edid *edid;
/*
* Mutex protects audio and video functions from interfering
* each other, by keeping their i2c command sequences atomic.
@@ -280,6 +287,8 @@ static int sii902x_get_modes(struct drm_connector *connector)
mutex_lock(&sii902x->mutex);
+ kfree(sii902x->edid);
+ sii902x->edid = NULL;
edid = drm_get_edid(connector, sii902x->i2cmux->adapter[0]);
drm_connector_update_edid_property(connector, edid);
if (edid) {
@@ -287,7 +296,7 @@ static int sii902x_get_modes(struct drm_connector *connector)
output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
num = drm_add_edid_modes(connector, edid);
- kfree(edid);
+ sii902x->edid = edid;
}
ret = drm_display_info_set_bus_formats(&connector->display_info,
@@ -337,6 +346,7 @@ static void sii902x_bridge_disable(struct drm_bridge *bridge)
static void sii902x_bridge_enable(struct drm_bridge *bridge)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
+ u8 output_mode = SII902X_SYS_CTRL_OUTPUT_DVI;
mutex_lock(&sii902x->mutex);
@@ -346,6 +356,14 @@ static void sii902x_bridge_enable(struct drm_bridge *bridge)
regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
SII902X_SYS_CTRL_PWR_DWN, 0);
+ if (sii902x->edid) {
+ if (drm_detect_hdmi_monitor(sii902x->edid))
+ output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
+ }
+
+ regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
+ SII902X_SYS_CTRL_OUTPUT_MODE, output_mode);
+
mutex_unlock(&sii902x->mutex);
}
@@ -960,6 +978,13 @@ static int sii902x_init(struct sii902x *sii902x)
{
struct device *dev = &sii902x->i2c->dev;
unsigned int status = 0;
+ unsigned char data[2] = { SII902X_CEC_SETUP, 0};
+ struct i2c_msg msg = {
+ .addr = SII902X_CEC_I2C_ADDR << 1,
+ .flags = 0,
+ .len = 2,
+ .buf = data,
+ };
u8 chipid[4];
int ret;
@@ -982,13 +1007,22 @@ static int sii902x_init(struct sii902x *sii902x)
return -EINVAL;
}
+ /*
+ * By default, CEC must be disabled to allow other CEC devives
+ * to bypass the bridge.
+ */
+ ret = i2c_transfer(sii902x->i2c->adapter, &msg, 1);
+ if (ret < 0)
+ dev_warn(&sii902x->i2c->dev, "Failed to disable CEC device!\n");
+
/* Clear all pending interrupts */
regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
regmap_write(sii902x->regmap, SII902X_INT_STATUS, status);
if (sii902x->i2c->irq > 0) {
- regmap_write(sii902x->regmap, SII902X_INT_ENABLE,
- SII902X_HOTPLUG_EVENT);
+ regmap_update_bits(sii902x->regmap, SII902X_INT_ENABLE,
+ SII902X_HOTPLUG_EVENT,
+ SII902X_HOTPLUG_EVENT);
ret = devm_request_threaded_irq(dev, sii902x->i2c->irq, NULL,
sii902x_interrupt,
@@ -1087,6 +1121,65 @@ static int sii902x_remove(struct i2c_client *client)
return 0;
}
+static int sii902x_pm_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct sii902x *sii902x = i2c_get_clientdata(client);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (sii902x->reset_gpio)
+ gpiod_set_value(sii902x->reset_gpio, 1);
+
+ regulator_bulk_disable(ARRAY_SIZE(sii902x->supplies),
+ sii902x->supplies);
+
+ return 0;
+}
+
+static int sii902x_pm_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct sii902x *sii902x = i2c_get_clientdata(client);
+ unsigned char data[2] = { SII902X_CEC_SETUP, 0};
+ struct i2c_msg msg = {
+ .addr = SII902X_CEC_I2C_ADDR << 1,
+ .flags = 0,
+ .len = 2,
+ .buf = data,
+ };
+ int ret;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(sii902x->supplies),
+ sii902x->supplies);
+ if (ret) {
+ DRM_ERROR("regulator_bulk_enable failed\n");
+ return ret;
+ }
+
+ if (sii902x->reset_gpio)
+ gpiod_set_value(sii902x->reset_gpio, 0);
+
+ regmap_write(sii902x->regmap, SII902X_REG_TPI_RQB, 0x00);
+
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ if (ret < 0)
+ DRM_ERROR("Failed to disable CEC device!\n");
+
+ if (client->irq > 0)
+ regmap_update_bits(sii902x->regmap, SII902X_INT_ENABLE,
+ SII902X_HOTPLUG_EVENT,
+ SII902X_HOTPLUG_EVENT);
+
+ return 0;
+}
+
+static const struct dev_pm_ops sii902x_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(sii902x_pm_suspend, sii902x_pm_resume)
+};
+
static const struct of_device_id sii902x_dt_ids[] = {
{ .compatible = "sil,sii9022", },
{ }
@@ -1105,6 +1198,7 @@ static struct i2c_driver sii902x_driver = {
.driver = {
.name = "sii902x",
.of_match_table = sii902x_dt_ids,
+ .pm = &sii902x_pm_ops,
},
.id_table = sii902x_i2c_ids,
};
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 56c3fd08c6a0..2a58b0b7ace5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -998,7 +998,10 @@ dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
enum drm_mode_status mode_status = MODE_OK;
if (pdata->mode_valid)
- mode_status = pdata->mode_valid(pdata->priv_data, mode);
+ mode_status = pdata->mode_valid(pdata->priv_data, mode,
+ dsi->mode_flags,
+ dw_mipi_dsi_get_lanes(dsi),
+ dsi->format);
return mode_status;
}
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index f195c7013137..9301aa72e6cb 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -773,6 +773,8 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector,
state->content_type = val;
} else if (property == connector->scaling_mode_property) {
state->scaling_mode = val;
+ } else if (property == connector->dithering_property) {
+ state->dithering = val;
} else if (property == config->content_protection_property) {
if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
DRM_DEBUG_KMS("only drivers can set CP Enabled\n");
@@ -862,6 +864,8 @@ drm_atomic_connector_get_property(struct drm_connector *connector,
*val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == connector->dithering_property) {
+ *val = state->dithering;
} else if (property == config->hdr_output_metadata_property) {
*val = state->hdr_output_metadata ?
state->hdr_output_metadata->base.id : 0;
diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
index 78bc315b0b73..f240af91d401 100644
--- a/drivers/gpu/drm/drm_bridge.c
+++ b/drivers/gpu/drm/drm_bridge.c
@@ -227,11 +227,13 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge,
list_del(&bridge->chain_node);
#ifdef CONFIG_OF
- DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",
- bridge->of_node, encoder->name, ret);
+ if (ret != -EPROBE_DEFER)
+ DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",
+ bridge->of_node, encoder->name, ret);
#else
- DRM_ERROR("failed to attach bridge to encoder %s: %d\n",
- encoder->name, ret);
+ if (ret != -EPROBE_DEFER)
+ DRM_ERROR("failed to attach bridge to encoder %s: %d\n",
+ encoder->name, ret);
#endif
return ret;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index cfe163103cfd..185df70e94b9 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -827,6 +827,12 @@ static const struct drm_prop_enum_list drm_scaling_mode_enum_list[] = {
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
+static const struct drm_prop_enum_list drm_dithering_enum_list[] = {
+ { DRM_MODE_DITHERING_OFF, "Off" },
+ { DRM_MODE_DITHERING_ON, "On" },
+ { DRM_MODE_DITHERING_AUTO, "Automatic" },
+};
+
static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
{ DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
{ DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
@@ -1779,6 +1785,62 @@ int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_attach_scaling_mode_property);
+/**
+ * drm_connector_attach_dithering_property - attach atomic dithering property
+ * @connector: connector to attach dithering property on.
+ * @dithering_mask: or'ed mask of BIT(%DRM_MODE_DITHERING_\*).
+ *
+ * This is used to add support for dithering to atomic drivers.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_dithering_property(struct drm_connector *connector,
+ u32 dithering_mask)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *dithering_property;
+ int i;
+ const unsigned int valid_dithering_mask =
+ (1U << ARRAY_SIZE(drm_dithering_enum_list)) - 1;
+
+ if (WARN_ON(hweight32(dithering_mask) < 2 ||
+ dithering_mask & ~valid_dithering_mask))
+ return -EINVAL;
+
+ dithering_property =
+ drm_property_create(dev, DRM_MODE_PROP_ENUM, "dithering",
+ hweight32(dithering_mask));
+
+ if (!dithering_property)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(drm_dithering_enum_list); i++) {
+ int ret;
+
+ if (!(BIT(i) & dithering_mask))
+ continue;
+
+ ret = drm_property_add_enum(dithering_property,
+ drm_dithering_enum_list[i].type,
+ drm_dithering_enum_list[i].name);
+
+ if (ret) {
+ drm_property_destroy(dev, dithering_property);
+
+ return ret;
+ }
+ }
+
+ drm_object_attach_property(&connector->base,
+ dithering_property, 0);
+
+ connector->dithering_property = dithering_property;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_dithering_property);
+
/**
* drm_mode_create_aspect_ratio_property - create aspect ratio property
* @dev: DRM device
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 479ffdb64486..c49fb01b1ce5 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -359,6 +359,15 @@ config DRM_PANEL_RAYDIUM_RM68200
Say Y here if you want to enable support for Raydium RM68200
720x1280 DSI video mode panel.
+config DRM_PANEL_ROCKTECH_HX8394
+ tristate "Rocktech HX8394 720x1280 DSI video mode panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for Rocktech HX8394
+ 720x1280 DSI video mode panel.
+
config DRM_PANEL_RONBO_RB070D30
tristate "Ronbo Electronics RB070D30 panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index c8132050bcec..57d7948975c2 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
+obj-$(CONFIG_DRM_PANEL_ROCKTECH_HX8394) += panel-rocktech-hx8394.o
obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index f8dbccd55033..e75d2fdc678f 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -10,6 +10,7 @@
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
@@ -60,6 +61,9 @@
#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
+#define OTM8009A_HDISPLAY 480
+#define OTM8009A_VDISPLAY 800
+
struct otm8009a {
struct device *dev;
struct drm_panel panel;
@@ -70,19 +74,35 @@ struct otm8009a {
bool enabled;
};
-static const struct drm_display_mode default_mode = {
- .clock = 29700,
- .hdisplay = 480,
- .hsync_start = 480 + 98,
- .hsync_end = 480 + 98 + 32,
- .htotal = 480 + 98 + 32 + 98,
- .vdisplay = 800,
- .vsync_start = 800 + 15,
- .vsync_end = 800 + 15 + 10,
- .vtotal = 800 + 15 + 10 + 14,
- .flags = 0,
- .width_mm = 52,
- .height_mm = 86,
+static const struct drm_display_mode modes[] = {
+ { /* 50 Hz, preferred */
+ .clock = 29700,
+ .hdisplay = 480,
+ .hsync_start = 480 + 98,
+ .hsync_end = 480 + 98 + 32,
+ .htotal = 480 + 98 + 32 + 98,
+ .vdisplay = 800,
+ .vsync_start = 800 + 15,
+ .vsync_end = 800 + 15 + 10,
+ .vtotal = 800 + 15 + 10 + 14,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .width_mm = 52,
+ .height_mm = 86,
+ },
+ { /* 60 Hz */
+ .clock = 33000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 70,
+ .hsync_end = 480 + 70 + 32,
+ .htotal = 480 + 70 + 32 + 72,
+ .vdisplay = 800,
+ .vsync_start = 800 + 15,
+ .vsync_end = 800 + 15 + 10,
+ .vtotal = 800 + 15 + 10 + 16,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .width_mm = 52,
+ .height_mm = 86,
+ },
};
static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
@@ -208,12 +228,11 @@ static int otm8009a_init_sequence(struct otm8009a *ctx)
/* Default portrait 480x800 rgb24 */
dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
- ret = mipi_dsi_dcs_set_column_address(dsi, 0,
- default_mode.hdisplay - 1);
+ ret = mipi_dsi_dcs_set_column_address(dsi, 0, OTM8009A_HDISPLAY - 1);
if (ret)
return ret;
- ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
+ ret = mipi_dsi_dcs_set_page_address(dsi, 0, OTM8009A_VDISPLAY - 1);
if (ret)
return ret;
@@ -272,16 +291,15 @@ static int otm8009a_disable(struct drm_panel *panel)
static int otm8009a_unprepare(struct drm_panel *panel)
{
struct otm8009a *ctx = panel_to_otm8009a(panel);
+ int ret;
if (!ctx->prepared)
return 0;
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- }
-
- regulator_disable(ctx->supply);
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
ctx->prepared = false;
@@ -296,20 +314,12 @@ static int otm8009a_prepare(struct drm_panel *panel)
if (ctx->prepared)
return 0;
- ret = regulator_enable(ctx->supply);
+ ret = pm_runtime_get_sync(panel->dev);
if (ret < 0) {
- dev_err(panel->dev, "failed to enable supply: %d\n", ret);
+ pm_runtime_put_autosuspend(panel->dev);
return ret;
}
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- msleep(100);
- }
-
ret = otm8009a_init_sequence(ctx);
if (ret)
return ret;
@@ -337,24 +347,35 @@ static int otm8009a_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct drm_display_mode *mode;
-
- mode = drm_mode_duplicate(connector->dev, &default_mode);
- if (!mode) {
- dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
- default_mode.hdisplay, default_mode.vdisplay,
- drm_mode_vrefresh(&default_mode));
- return -ENOMEM;
+ unsigned int num_modes = ARRAY_SIZE(modes);
+ unsigned int i;
+
+ for (i = 0; i < num_modes; i++) {
+ mode = drm_mode_duplicate(connector->dev, &modes[i]);
+ if (!mode) {
+ dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+ modes[i].hdisplay,
+ modes[i].vdisplay,
+ drm_mode_vrefresh(&modes[i]));
+ return -ENOMEM;
+ }
+
+ mode->type = DRM_MODE_TYPE_DRIVER;
+
+ /* Setting first mode as preferred */
+ if (!i)
+ mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
}
- drm_mode_set_name(mode);
-
- mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
- drm_mode_probed_add(connector, mode);
-
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
+ connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH |
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
- return 1;
+ return num_modes;
}
static const struct drm_panel_funcs otm8009a_drm_funcs = {
@@ -419,8 +440,10 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset_gpio)) {
- dev_err(dev, "cannot get reset-gpio\n");
- return PTR_ERR(ctx->reset_gpio);
+ ret = PTR_ERR(ctx->reset_gpio);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "cannot get reset GPIO: %d\n", ret);
+ return ret;
}
ctx->supply = devm_regulator_get(dev, "power");
@@ -467,6 +490,10 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
return 0;
}
@@ -477,9 +504,50 @@ static int otm8009a_remove(struct mipi_dsi_device *dsi)
mipi_dsi_detach(dsi);
drm_panel_remove(&ctx->panel);
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
return 0;
}
+static __maybe_unused int orisetech_otm8009a_suspend(struct device *dev)
+{
+ struct otm8009a *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int orisetech_otm8009a_resume(struct device *dev)
+{
+ struct otm8009a *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(100);
+
+ return 0;
+}
+
+static const struct dev_pm_ops orisetech_otm8009a_pm_ops = {
+ SET_RUNTIME_PM_OPS(orisetech_otm8009a_suspend, orisetech_otm8009a_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
static const struct of_device_id orisetech_otm8009a_of_match[] = {
{ .compatible = "orisetech,otm8009a" },
{ }
@@ -492,6 +560,7 @@ static struct mipi_dsi_driver orisetech_otm8009a_driver = {
.driver = {
.name = "panel-orisetech-otm8009a",
.of_match_table = orisetech_otm8009a_of_match,
+ .pm = &orisetech_otm8009a_pm_ops,
},
};
module_mipi_dsi_driver(orisetech_otm8009a_driver);
diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index 412c0dbcb2b6..6bd2c6406e4a 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -10,6 +10,7 @@
#include <linux/gpio/consumer.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
@@ -91,7 +92,7 @@ static const struct drm_display_mode default_mode = {
.vsync_start = 1280 + 12,
.vsync_end = 1280 + 12 + 5,
.vtotal = 1280 + 12 + 5 + 12,
- .flags = 0,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
.width_mm = 68,
.height_mm = 122,
};
@@ -260,14 +261,10 @@ static int rm68200_unprepare(struct drm_panel *panel)
if (ret)
dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
- msleep(120);
-
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- }
-
- regulator_disable(ctx->supply);
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
ctx->prepared = false;
@@ -283,19 +280,12 @@ static int rm68200_prepare(struct drm_panel *panel)
if (ctx->prepared)
return 0;
- ret = regulator_enable(ctx->supply);
+ ret = pm_runtime_get_sync(panel->dev);
if (ret < 0) {
- dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ pm_runtime_put_autosuspend(panel->dev);
return ret;
}
- if (ctx->reset_gpio) {
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- msleep(20);
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- msleep(100);
- }
-
rm68200_init_sequence(ctx);
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
@@ -347,6 +337,8 @@ static int rm68200_get_modes(struct drm_panel *panel,
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
+ connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH |
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
return 1;
}
@@ -372,7 +364,8 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset_gpio)) {
ret = PTR_ERR(ctx->reset_gpio);
- dev_err(dev, "cannot get reset GPIO: %d\n", ret);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "cannot get reset GPIO: %d\n", ret);
return ret;
}
@@ -409,6 +402,10 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
return 0;
}
@@ -419,9 +416,49 @@ static int rm68200_remove(struct mipi_dsi_device *dsi)
mipi_dsi_detach(dsi);
drm_panel_remove(&ctx->panel);
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
return 0;
}
+static __maybe_unused int raydium_rm68200_suspend(struct device *dev)
+{
+ struct rm68200 *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int raydium_rm68200_resume(struct device *dev)
+{
+ struct rm68200 *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(100);
+
+ return 0;
+}
+
+static const struct dev_pm_ops raydium_rm68200_pm_ops = {
+ SET_RUNTIME_PM_OPS(raydium_rm68200_suspend, raydium_rm68200_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
static const struct of_device_id raydium_rm68200_of_match[] = {
{ .compatible = "raydium,rm68200" },
{ }
@@ -434,6 +471,7 @@ static struct mipi_dsi_driver raydium_rm68200_driver = {
.driver = {
.name = "panel-raydium-rm68200",
.of_match_table = raydium_rm68200_of_match,
+ .pm = &raydium_rm68200_pm_ops,
},
};
module_mipi_dsi_driver(raydium_rm68200_driver);
diff --git a/drivers/gpu/drm/panel/panel-rocktech-hx8394.c b/drivers/gpu/drm/panel/panel-rocktech-hx8394.c
new file mode 100644
index 000000000000..29a64a546364
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-rocktech-hx8394.c
@@ -0,0 +1,432 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics SA 2022
+ *
+ * Author: Yannick Fertre <yannick.fertre@foss.st.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+struct hx8394 {
+ struct device *dev;
+ struct drm_panel panel;
+ struct gpio_desc *reset_gpio;
+ struct regulator *supply;
+ bool prepared;
+ bool enabled;
+};
+
+static const struct drm_display_mode default_mode = {
+ .clock = 54000,
+ .hdisplay = 720,
+ .hsync_start = 720 + 48,
+ .hsync_end = 720 + 48 + 9,
+ .htotal = 720 + 48 + 9 + 48,
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 12,
+ .vsync_end = 1280 + 12 + 5,
+ .vtotal = 1280 + 12 + 5 + 12,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .width_mm = 68,
+ .height_mm = 122,
+};
+
+#define MCS_SETPOWER 0xB1
+#define MCS_SETDISP 0xB2
+#define MCS_SETCYC 0xB4
+#define MCS_SETVCOM 0xB6
+#define MCS_SETEXTC 0xB9
+#define MCS_SETMIPI 0xBA
+#define MCS_SET_BANK 0xBD
+#define MCS_NO_DOC1 0xBF
+#define MCS_NO_DOC2 0xC0
+#define MCS_NO_DOC3 0xC6
+#define MCS_NO_DOC4 0xD8
+#define MCS_NO_DOC5 0xD4
+#define MCS_SETPANEL 0xCC
+#define MCS_SETGIP_0 0xD3
+#define MCS_SETGIP_1 0xD5
+#define MCS_SETGIP_2 0xD6
+
+#define MCS_SETGAMMA 0xE0
+#define MCS_READ_ID1 0xDA
+#define MCS_READ_ID2 0xDB
+#define MCS_READ_ID3 0xDC
+
+#define MY BIT(7) /* Row Address Order */
+#define MX BIT(6) /* Column Address Order */
+#define MV BIT(5) /* Row/Column Exchange */
+#define ML BIT(4) /* Vertical Refresh Order */
+#define RGB BIT(3) /* RGB-BGR Order */
+#define DDL BIT(2) /* Display Data Latch Order */
+#define FH BIT(1) /* Flip Horizontal */
+#define FV BIT(0) /* Flip Vertical */
+
+static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
+{
+ return container_of(panel, struct hx8394, panel);
+}
+
+#define dcs_write_cmd_seq(ctx, cmd, seq...) \
+({ \
+ static const u8 d[] = { seq }; \
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); \
+ int err; \
+ err = mipi_dsi_dcs_write(dsi, cmd, d, ARRAY_SIZE(d)); \
+ if (err < 0) \
+ dev_err(ctx->dev, "MIPI DSI DCS write failed: %d\n",err); \
+})
+
+static void hx8394_dcs_write_buf(struct hx8394 *ctx, const void *data,
+ size_t len)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ int err;
+
+ err = mipi_dsi_dcs_write_buffer(dsi, data, len);
+ if (err < 0)
+ dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
+}
+
+#define dcs_write_seq(ctx, seq...) \
+({ \
+ static const u8 d[] = { seq }; \
+ \
+ hx8394_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
+})
+
+static void hx8394_init_sequence(struct hx8394 *ctx)
+{
+ dcs_write_cmd_seq(ctx, MCS_SETEXTC, 0xFF, 0x83, 0x94);
+ dcs_write_cmd_seq(ctx, MCS_SETMIPI, 0x61, 0x03, 0x68, 0x6B, 0xB2, 0xC0);
+ dcs_write_seq(ctx, MCS_SETPOWER, 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57,
+ 0x47);
+ dcs_write_cmd_seq(ctx, MCS_SETDISP, 0x00, 0x80, 0x64, 0x0C, 0x0D, 0x2F);
+ dcs_write_seq(ctx, MCS_SETCYC, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86, 0x75,
+ 0x00, 0x3F, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86);
+ dcs_write_seq(ctx, MCS_SETGIP_0, 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0C, 0x00, 0x08, 0x10,
+ 0x08, 0x00, 0x08, 0x54, 0x15, 0x0A, 0x05, 0x0A, 0x02, 0x15, 0x06, 0x05, 0x06,
+ 0x47, 0x44, 0x0A, 0x0A, 0x4B, 0x10, 0x07, 0x07, 0x0C, 0x40);
+ dcs_write_seq(ctx, MCS_SETGIP_1, 0x1C, 0x1C, 0x1D, 0x1D, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+ 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x24, 0x25, 0x18, 0x18, 0x26, 0x27, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18);
+ dcs_write_seq(ctx, MCS_SETGIP_2, 0x1C, 0x1C, 0x1D, 0x1D, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
+ 0x01, 0x00, 0x0B, 0x0A, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18, 0x27, 0x26, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18);
+ dcs_write_cmd_seq(ctx, MCS_SETVCOM, 0x92, 0x92);
+ dcs_write_seq(ctx, MCS_SETGAMMA, 0x00, 0x0A, 0x15, 0x1B, 0x1E, 0x21, 0x24, 0x22, 0x47, 0x56,
+ 0x65, 0x66, 0x6E, 0x82, 0x88, 0x8B, 0x9A, 0x9D, 0x98, 0xA8, 0xB9, 0x5D, 0x5C,
+ 0x61, 0x66, 0x6A, 0x6F, 0x7F, 0x7F, 0x00, 0x0A, 0x15, 0x1B, 0x1E, 0x21, 0x24,
+ 0x22, 0x47, 0x56, 0x65, 0x65, 0x6E, 0x81, 0x87, 0x8B, 0x98, 0x9D, 0x99, 0xA8,
+ 0xBA, 0x5D, 0x5D, 0x62, 0x67, 0x6B, 0x72, 0x7F, 0x7F);
+ dcs_write_cmd_seq(ctx, MCS_NO_DOC2, 0x1F, 0x31);
+ dcs_write_cmd_seq(ctx, MCS_SETPANEL, 0x03);
+ dcs_write_cmd_seq(ctx, MCS_NO_DOC5, 0x02);
+ dcs_write_cmd_seq(ctx, MCS_SET_BANK, 0x02);
+ dcs_write_seq(ctx, MCS_NO_DOC4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF);
+ dcs_write_cmd_seq(ctx, MCS_SET_BANK, 0x00);
+ dcs_write_cmd_seq(ctx, MCS_SET_BANK, 0x01);
+ dcs_write_cmd_seq(ctx, MCS_SETPOWER, 0x00);
+ dcs_write_cmd_seq(ctx, MCS_SET_BANK, 0x00);
+ dcs_write_cmd_seq(ctx, MCS_NO_DOC1, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01);
+ dcs_write_cmd_seq(ctx, MCS_NO_DOC3, 0xED);
+ dcs_write_cmd_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, FH);
+}
+
+
+static int hx8394_read_id(struct hx8394 *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ u8 id1, id2, id3;
+ int ret;
+
+ ret = mipi_dsi_dcs_read(dsi, MCS_READ_ID1, &id1, 1);
+ if (ret < 0) {
+ dev_err(ctx->dev, "could not read MTP ID1\n");
+ return ret;
+ }
+ ret = mipi_dsi_dcs_read(dsi, MCS_READ_ID2, &id2, 1);
+ if (ret < 0) {
+ dev_err(ctx->dev, "could not read MTP ID2\n");
+ return ret;
+ }
+ ret = mipi_dsi_dcs_read(dsi, MCS_READ_ID3, &id3, 1);
+ if (ret < 0) {
+ dev_err(ctx->dev, "could not read MTP ID3\n");
+ return ret;
+ }
+
+ dev_info(ctx->dev, "MTP ID manufacturer: %02x version: %02x driver: %02x\n", id1, id2, id3);
+
+ return 0;
+}
+
+static int hx8394_enable(struct drm_panel *panel)
+{
+ struct hx8394 *ctx = panel_to_hx8394(panel);
+
+ if (ctx->enabled)
+ return 0;
+
+ ctx->enabled = true;
+
+ return 0;
+}
+
+static int hx8394_disable(struct drm_panel *panel)
+{
+ struct hx8394 *ctx = panel_to_hx8394(panel);
+
+ if (!ctx->enabled)
+ return 0;
+
+ ctx->enabled = false;
+
+ return 0;
+}
+
+static int hx8394_prepare(struct drm_panel *panel)
+{
+ struct hx8394 *ctx = panel_to_hx8394(panel);
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ int ret;
+
+ if (ctx->prepared)
+ return 0;
+
+ ret = pm_runtime_get_sync(panel->dev);
+ if (ret < 0) {
+ pm_runtime_put_autosuspend(panel->dev);
+ return ret;
+ }
+
+ ret = hx8394_read_id(ctx);
+ if (ret < 0)
+ return ret;
+
+ hx8394_init_sequence(ctx);
+
+ ret = mipi_dsi_dcs_set_tear_off(dsi);
+ if (ret)
+ return ret;
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret)
+ return ret;
+
+ msleep(120);
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret)
+ return ret;
+
+ msleep(50);
+
+ ctx->prepared = true;
+
+ return 0;
+}
+
+static int hx8394_unprepare(struct drm_panel *panel)
+{
+ struct hx8394 *ctx = panel_to_hx8394(panel);
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ int ret;
+
+ if (!ctx->prepared)
+ return 0;
+
+ ret = mipi_dsi_dcs_set_display_off(dsi);
+ if (ret)
+ dev_warn(panel->dev, "failed to set display off: %d\n", ret);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+ if (ret)
+ dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
+
+ pm_runtime_mark_last_busy(panel->dev);
+ ret = pm_runtime_put_autosuspend(panel->dev);
+ if (ret < 0)
+ return ret;
+
+ ctx->prepared = false;
+
+ return 0;
+}
+
+static int hx8394_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_duplicate(connector->dev, &default_mode);
+ if (!mode) {
+ dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+ default_mode.hdisplay, default_mode.vdisplay,
+ drm_mode_vrefresh(&default_mode));
+ return -ENOMEM;
+ }
+
+ drm_mode_set_name(mode);
+
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ drm_mode_probed_add(connector, mode);
+
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+ connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH |
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
+
+ return 1;
+}
+
+static const struct drm_panel_funcs hx8394_drm_funcs = {
+ .disable = hx8394_disable,
+ .unprepare = hx8394_unprepare,
+ .prepare = hx8394_prepare,
+ .enable = hx8394_enable,
+ .get_modes = hx8394_get_modes,
+};
+
+static int hx8394_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct hx8394 *ctx;
+ int ret;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(ctx->reset_gpio)) {
+ ret = PTR_ERR(ctx->reset_gpio);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "cannot get reset GPIO: %d\n", ret);
+ return ret;
+ }
+
+ ctx->supply = devm_regulator_get(dev, "power");
+ if (IS_ERR(ctx->supply)) {
+ ret = PTR_ERR(ctx->supply);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "cannot get regulator: %d\n", ret);
+ return ret;
+ }
+
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ ctx->dev = dev;
+
+ dsi->lanes = 2;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+ drm_panel_init(&ctx->panel, dev, &hx8394_drm_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return ret;
+
+ drm_panel_add(&ctx->panel);
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+ drm_panel_remove(&ctx->panel);
+ return ret;
+ }
+
+ pm_runtime_enable(ctx->dev);
+ pm_runtime_set_autosuspend_delay(ctx->dev, 1000);
+ pm_runtime_use_autosuspend(ctx->dev);
+
+ return 0;
+}
+
+static int hx8394_remove(struct mipi_dsi_device *dsi)
+{
+ struct hx8394 *ctx = mipi_dsi_get_drvdata(dsi);
+
+ mipi_dsi_detach(dsi);
+ drm_panel_remove(&ctx->panel);
+
+ pm_runtime_dont_use_autosuspend(ctx->dev);
+ pm_runtime_disable(ctx->dev);
+
+ return 0;
+}
+
+static __maybe_unused int rocktech_hx8394_suspend(struct device *dev)
+{
+ struct hx8394 *ctx = dev_get_drvdata(dev);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(20);
+
+ regulator_disable(ctx->supply);
+
+ return 0;
+}
+
+static __maybe_unused int rocktech_hx8394_resume(struct device *dev)
+{
+ struct hx8394 *ctx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(ctx->supply);
+ if (ret < 0) {
+ dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ mdelay(1);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(50);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rocktech_hx8394_pm_ops = {
+ SET_RUNTIME_PM_OPS(rocktech_hx8394_suspend, rocktech_hx8394_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
+static const struct of_device_id rocktech_hx8394_of_match[] = {
+ { .compatible = "rocktech,hx8394" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rocktech_hx8394_of_match);
+
+static struct mipi_dsi_driver rocktech_hx8394_driver = {
+ .probe = hx8394_probe,
+ .remove = hx8394_remove,
+ .driver = {
+ .name = "panel-rocktech-hx8394",
+ .of_match_table = rocktech_hx8394_of_match,
+ .pm = &rocktech_hx8394_pm_ops,
+ },
+};
+module_mipi_dsi_driver(rocktech_hx8394_driver);
+
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@foss.st.com>");
+MODULE_DESCRIPTION("DRM Driver for rocktech HX8394 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index fb785f5a106a..3af0982bed64 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -575,6 +575,7 @@ static int panel_dpi_probe(struct device *dev,
struct panel_desc *desc;
unsigned int bus_flags;
struct videomode vm;
+ const char *mapping;
int ret;
np = dev->of_node;
@@ -599,6 +600,21 @@ static int panel_dpi_probe(struct device *dev,
of_property_read_u32(np, "width-mm", &desc->size.width);
of_property_read_u32(np, "height-mm", &desc->size.height);
+ of_property_read_string(np, "data-mapping", &mapping);
+ if (!strcmp(mapping, "rgb24")) {
+ desc->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ desc->bpc = 8;
+ } else if (!strcmp(mapping, "rgb565")) {
+ desc->bus_format = MEDIA_BUS_FMT_RGB565_1X16;
+ desc->bpc = 6;
+ } else if (!strcmp(mapping, "bgr666")) {
+ desc->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
+ desc->bpc = 6;
+ } else if (!strcmp(mapping, "lvds666")) {
+ desc->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
+ desc->bpc = 6;
+ }
+
/* Extract bus_flags from display_timing */
bus_flags = 0;
vm.flags = timing->flags;
diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
index 222869b232ae..85c94b8f5d54 100644
--- a/drivers/gpu/drm/stm/drv.c
+++ b/drivers/gpu/drm/stm/drv.c
@@ -14,6 +14,7 @@
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
+#include <drm/drm_aperture.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
@@ -93,6 +94,7 @@ static int drv_load(struct drm_device *ddev)
ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
ddev->mode_config.funcs = &drv_mode_config_funcs;
+ ddev->mode_config.normalize_zpos = true;
ret = ltdc_load(ddev);
if (ret)
@@ -183,6 +185,10 @@ static int stm_drm_platform_probe(struct platform_device *pdev)
DRM_DEBUG("%s\n", __func__);
+ ret = drm_aperture_remove_framebuffers(false, &drv_driver);
+ if (ret)
+ return ret;
+
dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
ddev = drm_dev_alloc(&drv_driver, dev);
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 32cb41b2202f..1750b6a25e87 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -247,14 +247,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
int ret, bpp;
u32 val;
- /* Update lane capabilities according to hw version */
- dsi->lane_min_kbps = LANE_MIN_KBPS;
- dsi->lane_max_kbps = LANE_MAX_KBPS;
- if (dsi->hw_version == HWVER_131) {
- dsi->lane_min_kbps *= 2;
- dsi->lane_max_kbps *= 2;
- }
-
pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
/* Compute requested pll out */
@@ -330,6 +322,103 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
return 0;
}
+#define CLK_TOLERANCE_HZ 50
+
+static enum drm_mode_status
+dw_mipi_dsi_stm_mode_valid(void *priv_data,
+ const struct drm_display_mode *mode,
+ unsigned long mode_flags, u32 lanes, u32 format)
+{
+ struct dw_mipi_dsi_stm *dsi = priv_data;
+ unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+ int ret, bpp;
+
+ bpp = mipi_dsi_pixel_format_to_bpp(format);
+ if (bpp < 0)
+ return MODE_BAD;
+
+ /* Compute requested pll out */
+ pll_out_khz = mode->clock * bpp / lanes;
+
+ if (pll_out_khz > dsi->lane_max_kbps)
+ return MODE_CLOCK_HIGH;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ /* Add 20% to pll out to be higher than pixel bw */
+ pll_out_khz = (pll_out_khz * 12) / 10;
+ } else {
+ if (pll_out_khz < dsi->lane_min_kbps)
+ return MODE_CLOCK_LOW;
+ }
+
+ /* Compute best pll parameters */
+ idf = 0;
+ ndiv = 0;
+ odf = 0;
+ pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000;
+ ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
+ if (ret) {
+ DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+ return MODE_ERROR;
+ }
+
+ if (!(mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
+ unsigned int px_clock_hz, target_px_clock_hz, lane_mbps;
+ int dsi_short_packet_size_px, hfp, hsync, hbp, delay_to_lp;
+ struct dw_mipi_dsi_dphy_timing dphy_timing;
+
+ /* Get the adjusted pll out value */
+ pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+ px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
+ target_px_clock_hz = mode->clock * 1000;
+ /*
+ * Filter modes according to the clock value, particularly useful for
+ * hdmi modes that require precise pixel clocks.
+ */
+ if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
+ px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
+ return MODE_CLOCK_RANGE;
+
+ /* sync packets are codes as DSI short packets (4 bytes) */
+ dsi_short_packet_size_px = DIV_ROUND_UP(4 * BITS_PER_BYTE, bpp);
+
+ hfp = mode->hsync_start - mode->hdisplay;
+ hsync = mode->hsync_end - mode->hsync_start;
+ hbp = mode->htotal - mode->hsync_end;
+
+ /* hsync must be longer than 4 bytes HSS packets */
+ if (hsync < dsi_short_packet_size_px)
+ return MODE_HSYNC_NARROW;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
+ /* HBP must be longer than 4 bytes HSE packets */
+ if (hbp < dsi_short_packet_size_px)
+ return MODE_HSYNC_NARROW;
+ hbp -= dsi_short_packet_size_px;
+ } else {
+ /* With sync events HBP extends in the hsync */
+ hbp += hsync - dsi_short_packet_size_px;
+ }
+
+ lane_mbps = pll_out_khz / 1000;
+ ret = dw_mipi_dsi_phy_get_timing(priv_data, lane_mbps, &dphy_timing);
+ if (ret)
+ return MODE_ERROR;
+ /*
+ * In non-burst mode DSI has to enter in LP during HFP
+ * (horizontal front porch) or HBP (horizontal back porch) to
+ * resync with LTDC pixel clock.
+ */
+ delay_to_lp = DIV_ROUND_UP((dphy_timing.data_hs2lp + dphy_timing.data_lp2hs) *
+ lanes * BITS_PER_BYTE, bpp);
+ if (hfp < delay_to_lp && hbp < delay_to_lp)
+ return MODE_HSYNC;
+ }
+
+ return MODE_OK;
+}
+
static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
.init = dw_mipi_dsi_phy_init,
.power_on = dw_mipi_dsi_phy_power_on,
@@ -340,6 +429,7 @@ static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
.max_data_lanes = 2,
+ .mode_valid = dw_mipi_dsi_stm_mode_valid,
.phy_ops = &dw_mipi_dsi_stm_phy_ops,
};
@@ -354,15 +444,13 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct dw_mipi_dsi_stm *dsi;
struct clk *pclk;
- struct resource *res;
int ret;
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- dsi->base = devm_ioremap_resource(dev, res);
+ dsi->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dsi->base)) {
ret = PTR_ERR(dsi->base);
DRM_ERROR("Unable to get dsi registers %d\n", ret);
@@ -417,6 +505,14 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
goto err_dsi_probe;
}
+ /* set lane capabilities according to hw version */
+ dsi->lane_min_kbps = LANE_MIN_KBPS;
+ dsi->lane_max_kbps = LANE_MAX_KBPS;
+ if (dsi->hw_version == HWVER_131) {
+ dsi->lane_min_kbps *= 2;
+ dsi->lane_max_kbps *= 2;
+ }
+
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 9d235b60b428..30f4995f8836 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -18,6 +18,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include <drm/drm_atomic.h>
@@ -46,15 +47,15 @@
#define HWVER_10200 0x010200
#define HWVER_10300 0x010300
#define HWVER_20101 0x020101
+#define HWVER_40100 0x040100
/*
* The address of some registers depends on the HW version: such registers have
- * an extra offset specified with reg_ofs.
+ * an extra offset specified with layer_ofs.
*/
-#define REG_OFS_NONE 0
-#define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
-#define REG_OFS (ldev->caps.reg_ofs)
-#define LAY_OFS 0x80 /* Register Offset between 2 layers */
+#define LAY_OFS_0 0x80
+#define LAY_OFS_1 0x100
+#define LAY_OFS (ldev->caps.layer_ofs)
/* Global register offsets */
#define LTDC_IDR 0x0000 /* IDentification */
@@ -75,29 +76,36 @@
#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
#define LTDC_CPSR 0x0044 /* Current Position Status */
#define LTDC_CDSR 0x0048 /* Current Display Status */
+#define LTDC_EDCR 0x0060 /* External Display Control */
+#define LTDC_CCRCR 0x007C /* Computed CRC value */
+#define LTDC_FUT 0x0090 /* Fifo underrun Threshold */
/* Layer register offsets */
-#define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
-#define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
-#define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
-#define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
-#define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
-#define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
-#define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
-#define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
-#define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
-#define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
-#define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
-#define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
-#define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
-#define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
-#define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
-#define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
-#define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
-#define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
-#define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
-#define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
-#define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
+#define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
+#define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
+#define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
+#define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
+#define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
+#define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
+#define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
+#define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
+#define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
+#define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
+#define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */
+#define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */
+#define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */
+#define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */
+#define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */
+#define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */
+#define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
+#define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
+#define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */
+#define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */
+#define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */
+#define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */
+#define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */
+#define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */
+#define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */
/* Bit definitions */
#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
@@ -114,6 +122,7 @@
#define GCR_LTDCEN BIT(0) /* LTDC ENable */
#define GCR_DEN BIT(16) /* Dither ENable */
+#define GCR_CRCEN BIT(19) /* CRC ENable */
#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
@@ -153,20 +162,29 @@
#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
#define IER_LIE BIT(0) /* Line Interrupt Enable */
-#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
+#define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */
#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
-#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
+#define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */
+#define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */
+#define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */
#define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */
#define ISR_LIF BIT(0) /* Line Interrupt Flag */
-#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
+#define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */
#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
+#define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */
+#define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */
+
+#define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */
+#define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */
+#define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */
#define LXCR_LEN BIT(0) /* Layer ENable */
#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
+#define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */
#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
@@ -175,17 +193,38 @@
#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
+#define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */
#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
+#define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */
#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
-#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
+#define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
+#define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */
+#define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */
+#define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */
+#define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/
+
+#define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */
+#define LxPCR_OF BIT(8) /* Odd pixel First */
+#define LxPCR_CBF BIT(7) /* CB component First */
+#define LxPCR_YF BIT(6) /* Y component First */
+#define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */
+#define YCM_I 0x0 /* Interleaved 422 */
+#define YCM_SP 0x1 /* Semi-Planar 420 */
+#define YCM_FP 0x2 /* Full-Planar 420 */
+#define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */
+
+#define LXRCR_IMR BIT(0) /* IMmediate Reload */
+#define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */
+#define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */
+
#define CLUT_SIZE 256
#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
@@ -196,13 +235,26 @@
#define NB_PF 8 /* Max nb of HW pixel format */
+#define FUT_DFT 128 /* Default value of fifo underrun threshold */
+
+/*
+ * Skip the first value and the second in case CRC was enabled during
+ * the thread irq. This is to be sure CRC value is relevant for the
+ * frame.
+ */
+#define CRC_SKIP_FRAMES 2
+
enum ltdc_pix_fmt {
PF_NONE,
/* RGB formats */
PF_ARGB8888, /* ARGB [32 bits] */
PF_RGBA8888, /* RGBA [32 bits] */
+ PF_ABGR8888, /* ABGR [32 bits] */
+ PF_BGRA8888, /* BGRA [32 bits] */
PF_RGB888, /* RGB [24 bits] */
+ PF_BGR888, /* BGR [24 bits] */
PF_RGB565, /* RGB [16 bits] */
+ PF_BGR565, /* BGR [16 bits] */
PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
/* Indexed formats */
@@ -234,36 +286,198 @@ static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
PF_ARGB4444 /* 0x07 */
};
-static const u64 ltdc_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_ABGR8888, /* 0x01 */
+ PF_RGBA8888, /* 0x02 */
+ PF_BGRA8888, /* 0x03 */
+ PF_RGB565, /* 0x04 */
+ PF_BGR565, /* 0x05 */
+ PF_RGB888, /* 0x06 */
+ PF_NONE /* 0x07 */
};
-static inline u32 reg_read(void __iomem *base, u32 reg)
-{
- return readl_relaxed(base + reg);
-}
+static const u32 ltdc_drm_fmt_a0[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_C8
+};
-static inline void reg_write(void __iomem *base, u32 reg, u32 val)
-{
- writel_relaxed(val, base + reg);
-}
+static const u32 ltdc_drm_fmt_a1[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_C8
+};
-static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
-{
- reg_write(base, reg, reg_read(base, reg) | mask);
-}
+static const u32 ltdc_drm_fmt_a2[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_C8
+};
-static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
-{
- reg_write(base, reg, reg_read(base, reg) & ~mask);
-}
+static const u32 ltdc_drm_fmt_ycbcr_cp[] = {
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY
+};
-static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
- u32 val)
-{
- reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
-}
+static const u32 ltdc_drm_fmt_ycbcr_sp[] = {
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21
+};
+
+static const u32 ltdc_drm_fmt_ycbcr_fp[] = {
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420
+};
+
+/* Layer register offsets */
+static const u32 ltdc_layer_regs_a0[] = {
+ 0x80, /* L1 configuration 0 */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x84, /* L1 control register */
+ 0x88, /* L1 window horizontal position configuration */
+ 0x8c, /* L1 window vertical position configuration */
+ 0x90, /* L1 color keying configuration */
+ 0x94, /* L1 pixel format configuration */
+ 0x98, /* L1 constant alpha configuration */
+ 0x9c, /* L1 default color configuration */
+ 0xa0, /* L1 blending factors configuration */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0xac, /* L1 color frame buffer address */
+ 0xb0, /* L1 color frame buffer length */
+ 0xb4, /* L1 color frame buffer line number */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0xc4, /* L1 CLUT write */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00 /* not available */
+};
+
+static const u32 ltdc_layer_regs_a1[] = {
+ 0x80, /* L1 configuration 0 */
+ 0x84, /* L1 configuration 1 */
+ 0x00, /* L1 reload control */
+ 0x88, /* L1 control register */
+ 0x8c, /* L1 window horizontal position configuration */
+ 0x90, /* L1 window vertical position configuration */
+ 0x94, /* L1 color keying configuration */
+ 0x98, /* L1 pixel format configuration */
+ 0x9c, /* L1 constant alpha configuration */
+ 0xa0, /* L1 default color configuration */
+ 0xa4, /* L1 blending factors configuration */
+ 0xa8, /* L1 burst length configuration */
+ 0x00, /* not available */
+ 0xac, /* L1 color frame buffer address */
+ 0xb0, /* L1 color frame buffer length */
+ 0xb4, /* L1 color frame buffer line number */
+ 0xb8, /* L1 auxiliary frame buffer address 0 */
+ 0xbc, /* L1 auxiliary frame buffer address 1 */
+ 0xc0, /* L1 auxiliary frame buffer length */
+ 0xc4, /* L1 auxiliary frame buffer line number */
+ 0xc8, /* L1 CLUT write */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00, /* not available */
+ 0x00 /* not available */
+};
+
+static const u32 ltdc_layer_regs_a2[] = {
+ 0x100, /* L1 configuration 0 */
+ 0x104, /* L1 configuration 1 */
+ 0x108, /* L1 reload control */
+ 0x10c, /* L1 control register */
+ 0x110, /* L1 window horizontal position configuration */
+ 0x114, /* L1 window vertical position configuration */
+ 0x118, /* L1 color keying configuration */
+ 0x11c, /* L1 pixel format configuration */
+ 0x120, /* L1 constant alpha configuration */
+ 0x124, /* L1 default color configuration */
+ 0x128, /* L1 blending factors configuration */
+ 0x12c, /* L1 burst length configuration */
+ 0x130, /* L1 planar configuration */
+ 0x134, /* L1 color frame buffer address */
+ 0x138, /* L1 color frame buffer length */
+ 0x13c, /* L1 color frame buffer line number */
+ 0x140, /* L1 auxiliary frame buffer address 0 */
+ 0x144, /* L1 auxiliary frame buffer address 1 */
+ 0x148, /* L1 auxiliary frame buffer length */
+ 0x14c, /* L1 auxiliary frame buffer line number */
+ 0x150, /* L1 CLUT write */
+ 0x16c, /* L1 Conversion YCbCr RGB 0 */
+ 0x170, /* L1 Conversion YCbCr RGB 1 */
+ 0x174, /* L1 Flexible Pixel Format 0 */
+ 0x178 /* L1 Flexible Pixel Format 1 */
+};
+
+static const u64 ltdc_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const struct regmap_config stm32_ltdc_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = sizeof(u32),
+ .max_register = 0x400,
+ .use_relaxed_mmio = true,
+ .cache_type = REGCACHE_NONE,
+};
+
+static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = {
+ [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ 0x02040199, /* (b_cb = 516 / r_cr = 409) */
+ 0x006400D0 /* (g_cb = 100 / g_cr = 208) */
+ },
+ [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
+ 0x01C60167, /* (b_cb = 454 / r_cr = 359) */
+ 0x005800B7 /* (g_cb = 88 / g_cr = 183) */
+ },
+ [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */
+ 0x00370089 /* (g_cb = 55 / g_cr = 137) */
+ },
+ [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
+ 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */
+ 0x00300078 /* (g_cb = 48 / g_cr = 120) */
+ }
+ /* BT2020 not supported */
+};
static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
{
@@ -289,16 +503,30 @@ static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
case DRM_FORMAT_XRGB8888:
pf = PF_ARGB8888;
break;
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XBGR8888:
+ pf = PF_ABGR8888;
+ break;
case DRM_FORMAT_RGBA8888:
case DRM_FORMAT_RGBX8888:
pf = PF_RGBA8888;
break;
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_BGRX8888:
+ pf = PF_BGRA8888;
+ break;
case DRM_FORMAT_RGB888:
pf = PF_RGB888;
break;
+ case DRM_FORMAT_BGR888:
+ pf = PF_BGR888;
+ break;
case DRM_FORMAT_RGB565:
pf = PF_RGB565;
break;
+ case DRM_FORMAT_BGR565:
+ pf = PF_BGR565;
+ break;
case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_XRGB1555:
pf = PF_ARGB1555;
@@ -319,49 +547,159 @@ static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
return pf;
}
-static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
+static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt)
{
- switch (pf) {
- case PF_ARGB8888:
- return DRM_FORMAT_ARGB8888;
- case PF_RGBA8888:
- return DRM_FORMAT_RGBA8888;
- case PF_RGB888:
- return DRM_FORMAT_RGB888;
- case PF_RGB565:
- return DRM_FORMAT_RGB565;
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE;
+ int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos;
+
+ switch (pix_fmt) {
+ case PF_BGR888:
+ psize = 3;
+ alen = 0; apos = 0; rlen = 8; rpos = 0;
+ glen = 8; gpos = 8; blen = 8; bpos = 16;
+ break;
case PF_ARGB1555:
- return DRM_FORMAT_ARGB1555;
+ psize = 2;
+ alen = 1; apos = 15; rlen = 5; rpos = 10;
+ glen = 5; gpos = 5; blen = 5; bpos = 0;
+ break;
case PF_ARGB4444:
- return DRM_FORMAT_ARGB4444;
+ psize = 2;
+ alen = 4; apos = 12; rlen = 4; rpos = 8;
+ glen = 4; gpos = 4; blen = 4; bpos = 0;
+ break;
case PF_L8:
- return DRM_FORMAT_C8;
- case PF_AL44: /* No DRM support */
- case PF_AL88: /* No DRM support */
- case PF_NONE:
+ psize = 1;
+ alen = 0; apos = 0; rlen = 8; rpos = 0;
+ glen = 8; gpos = 0; blen = 8; bpos = 0;
+ break;
+ case PF_AL44:
+ psize = 1;
+ alen = 4; apos = 4; rlen = 4; rpos = 0;
+ glen = 4; gpos = 0; blen = 4; bpos = 0;
+ break;
+ case PF_AL88:
+ psize = 2;
+ alen = 8; apos = 8; rlen = 8; rpos = 0;
+ glen = 8; gpos = 0; blen = 8; bpos = 0;
+ break;
default:
- return 0;
+ ret = NB_PF; /* error case, trace msg is handled by the caller */
+ break;
}
+
+ if (ret == PF_FLEXIBLE) {
+ regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
+ (rlen << 14) + (rpos << 9) + (alen << 5) + apos);
+
+ regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
+ (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos);
+ }
+
+ return ret;
}
-static inline u32 get_pixelformat_without_alpha(u32 drm)
+/*
+ * All non-alpha color formats derived from native alpha color formats are
+ * either characterized by a FourCC format code
+ */
+static inline u32 is_xrgb(u32 drm)
{
- switch (drm) {
- case DRM_FORMAT_ARGB4444:
- return DRM_FORMAT_XRGB4444;
- case DRM_FORMAT_RGBA4444:
- return DRM_FORMAT_RGBX4444;
- case DRM_FORMAT_ARGB1555:
- return DRM_FORMAT_XRGB1555;
- case DRM_FORMAT_RGBA5551:
- return DRM_FORMAT_RGBX5551;
- case DRM_FORMAT_ARGB8888:
- return DRM_FORMAT_XRGB8888;
- case DRM_FORMAT_RGBA8888:
- return DRM_FORMAT_RGBX8888;
+ return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
+}
+
+static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ u32 lofs = plane->index * LAY_OFS;
+ u32 val;
+
+ switch (drm_pix_fmt) {
+ case DRM_FORMAT_YUYV:
+ val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF;
+ break;
+ case DRM_FORMAT_YVYU:
+ val = (YCM_I << 4) | LxPCR_YF;
+ break;
+ case DRM_FORMAT_UYVY:
+ val = (YCM_I << 4) | LxPCR_CBF;
+ break;
+ case DRM_FORMAT_VYUY:
+ val = (YCM_I << 4);
+ break;
+ case DRM_FORMAT_NV12:
+ val = (YCM_SP << 4) | LxPCR_CBF;
+ break;
+ case DRM_FORMAT_NV21:
+ val = (YCM_SP << 4);
+ break;
+ case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YVU420:
+ val = (YCM_FP << 4);
+ break;
default:
- return 0;
+ /* RGB or not a YCbCr supported format */
+ DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
+ return;
+ }
+
+ /* Enable limited range */
+ if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
+ val |= LxPCR_YREN;
+
+ /* enable ycbcr conversion */
+ val |= LxPCR_YCEN;
+
+ regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
+}
+
+static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ enum drm_color_encoding enc = state->color_encoding;
+ enum drm_color_range ran = state->color_range;
+ u32 lofs = plane->index * LAY_OFS;
+
+ if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
+ DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
+ /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
+ enc = DRM_COLOR_YCBCR_BT601;
+ }
+
+ if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
+ DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
+ /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
+ ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
}
+
+ DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
+ regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
+ ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
+ regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
+ ltdc_ycbcr2rgb_coeffs[enc][ran][1]);
+}
+
+static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
+ struct drm_crtc *crtc)
+{
+ u32 crc;
+ int ret;
+
+ if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
+ ldev->crc_skip_count++;
+ return;
+ }
+
+ /* Get the CRC of the frame */
+ ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
+ if (ret)
+ return;
+
+ /* Report to DRM the CRC (hw dependent feature) */
+ drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
}
static irqreturn_t ltdc_irq_thread(int irq, void *arg)
@@ -371,15 +709,21 @@ static irqreturn_t ltdc_irq_thread(int irq, void *arg)
struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
/* Line IRQ : trigger the vblank event */
- if (ldev->irq_status & ISR_LIF)
+ if (ldev->irq_status & ISR_LIF) {
drm_crtc_handle_vblank(crtc);
- /* Save FIFO Underrun & Transfer Error status */
+ /* Early return if CRC is not active */
+ if (ldev->crc_active)
+ ltdc_irq_crc_handle(ldev, crtc);
+ }
+
mutex_lock(&ldev->err_lock);
- if (ldev->irq_status & ISR_FUIF)
- ldev->error_status |= ISR_FUIF;
if (ldev->irq_status & ISR_TERRIF)
- ldev->error_status |= ISR_TERRIF;
+ ldev->transfer_err++;
+ if (ldev->irq_status & ISR_FUEIF)
+ ldev->fifo_err++;
+ if (ldev->irq_status & ISR_FUWIF)
+ ldev->fifo_warn++;
mutex_unlock(&ldev->err_lock);
return IRQ_HANDLED;
@@ -391,8 +735,8 @@ static irqreturn_t ltdc_irq(int irq, void *arg)
struct ltdc_device *ldev = ddev->dev_private;
/* Read & Clear the interrupt status */
- ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
- reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
+ ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
+ writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
return IRQ_WAKE_THREAD;
}
@@ -416,7 +760,7 @@ static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
for (i = 0; i < CLUT_SIZE; i++, lut++) {
val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
(lut->blue >> 8) | (i << 24);
- reg_write(ldev->regs, LTDC_L1CLUTWR, val);
+ regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
}
}
@@ -425,19 +769,27 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
struct drm_device *ddev = crtc->dev;
+ int ret;
DRM_DEBUG_DRIVER("\n");
- pm_runtime_get_sync(ddev->dev);
+ if (!pm_runtime_active(ddev->dev)) {
+ ret = pm_runtime_get_sync(ddev->dev);
+ if (ret) {
+ DRM_ERROR("Failed to set mode, cannot get sync\n");
+ return;
+ }
+ }
/* Sets the background color value */
- reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
+ regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
/* Enable IRQ */
- reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+ regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
/* Commit shadow registers = update planes at next vblank */
- reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
+ if (!ldev->caps.plane_reg_shadow)
+ regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
drm_crtc_vblank_on(crtc);
}
@@ -447,18 +799,38 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
struct drm_device *ddev = crtc->dev;
+ int layer_index = 0;
DRM_DEBUG_DRIVER("\n");
drm_crtc_vblank_off(crtc);
+ /* Disable all layers */
+ for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) {
+ regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS,
+ LXCR_CLUTEN | LXCR_LEN, 0);
+
+ /* immediately commit disable of layer */
+ if (ldev->caps.plane_reg_shadow)
+ regmap_write_bits(ldev->regmap, LTDC_L1RCR + layer_index * LAY_OFS,
+ LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_IMR);
+ }
+
/* disable IRQ */
- reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
/* immediately commit disable of layers before switching off LTDC */
- reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+ if (!ldev->caps.plane_reg_shadow)
+ regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
+
+ pm_runtime_put_sync_suspend(ddev->dev);
- pm_runtime_put_sync(ddev->dev);
+ /* clear interrupt error counters */
+ mutex_lock(&ldev->err_lock);
+ ldev->transfer_err = 0;
+ ldev->fifo_err = 0;
+ ldev->fifo_warn = 0;
+ mutex_unlock(&ldev->err_lock);
}
#define CLK_TOLERANCE_HZ 50
@@ -533,6 +905,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
u32 total_width, total_height;
+ u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24;
u32 bus_flags = 0;
u32 val;
int ret;
@@ -560,10 +933,13 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_connector_list_iter_end(&iter);
}
- if (bridge && bridge->timings)
+ if (bridge && bridge->timings) {
bus_flags = bridge->timings->input_bus_flags;
- else if (connector)
+ } else if (connector) {
bus_flags = connector->display_info.bus_flags;
+ if (connector->display_info.num_bus_formats)
+ bus_formats = connector->display_info.bus_formats[0];
+ }
if (!pm_runtime_active(ddev->dev)) {
ret = pm_runtime_get_sync(ddev->dev);
@@ -608,26 +984,59 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
val |= GCR_PCPOL;
- reg_update_bits(ldev->regs, LTDC_GCR,
- GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
+ if (connector && connector->state->dithering == DRM_MODE_DITHERING_ON)
+ val |= GCR_DEN;
+
+ regmap_update_bits(ldev->regmap, LTDC_GCR,
+ GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL | GCR_DEN, val);
/* Set Synchronization size */
val = (hsync << 16) | vsync;
- reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
+ regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
/* Set Accumulated Back porch */
val = (accum_hbp << 16) | accum_vbp;
- reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
+ regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
/* Set Accumulated Active Width */
val = (accum_act_w << 16) | accum_act_h;
- reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
+ regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
/* Set total width & height */
val = (total_width << 16) | total_height;
- reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+ regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
- reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
+ regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
+
+ /* Configure the output format (hw version dependent) */
+ if (ldev->caps.ycbcr_output) {
+ /* Input video dynamic_range & colorimetry */
+ int vic = drm_match_cea_mode(mode);
+ u32 val;
+
+ if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||
+ vic == 2 || vic == 3 || vic == 17 || vic == 18)
+ /* ITU-R BT.601 */
+ val = 0;
+ else
+ /* ITU-R BT.709 */
+ val = EDCR_OCYSEL;
+
+ switch (bus_formats) {
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ /* enable ycbcr output converter */
+ regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
+ break;
+ case MEDIA_BUS_FMT_YVYU8_1X16:
+ /* enable ycbcr output converter & invert chrominance order */
+ regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
+ break;
+ default:
+ /* disable ycbcr output converter */
+ regmap_write(ldev->regmap, LTDC_EDCR, 0);
+ break;
+ }
+ }
}
static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
@@ -642,7 +1051,8 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
ltdc_crtc_update_clut(crtc);
/* Commit shadow registers = update planes at next vblank */
- reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
+ if (!ldev->caps.plane_reg_shadow)
+ regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
if (event) {
crtc->state->event = NULL;
@@ -656,6 +1066,20 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
}
}
+static int ltdc_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ /* force a full mode set if active state changed */
+ if (crtc_state->active_changed)
+ crtc_state->mode_changed = true;
+
+ return 0;
+}
+
static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
bool in_vblank_irq,
int *vpos, int *hpos,
@@ -684,10 +1108,14 @@ static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
* simplify the code and only test if line > vactive_end
*/
if (pm_runtime_active(ddev->dev)) {
- line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
- vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
- vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
- vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
+ regmap_read(ldev->regmap, LTDC_CPSR, &line);
+ line &= CPSR_CYPOS;
+ regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
+ vactive_start &= BPCR_AVBP;
+ regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
+ vactive_end &= AWCR_AAH;
+ regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
+ vtotal &= TWCR_TOTALH;
if (line > vactive_end)
*vpos = line - vtotal - vactive_start;
@@ -712,6 +1140,7 @@ static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
.atomic_flush = ltdc_crtc_atomic_flush,
.atomic_enable = ltdc_crtc_atomic_enable,
.atomic_disable = ltdc_crtc_atomic_disable,
+ .atomic_check = ltdc_crtc_atomic_check,
.get_scanout_position = ltdc_crtc_get_scanout_position,
};
@@ -723,7 +1152,7 @@ static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
DRM_DEBUG_DRIVER("\n");
if (state->enable)
- reg_set(ldev->regs, LTDC_IER, IER_LIE);
+ regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
else
return -EPERM;
@@ -735,7 +1164,61 @@ static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
DRM_DEBUG_DRIVER("\n");
- reg_clear(ldev->regs, LTDC_IER, IER_LIE);
+ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
+}
+
+static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ int ret;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (!crtc)
+ return -ENODEV;
+
+ if (source && strcmp(source, "auto") == 0) {
+ ldev->crc_active = true;
+ ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
+ } else if (!source) {
+ ldev->crc_active = false;
+ ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
+ } else {
+ ret = -EINVAL;
+ }
+
+ ldev->crc_skip_count = 0;
+ return ret;
+}
+
+static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
+ const char *source, size_t *values_cnt)
+{
+ DRM_DEBUG_DRIVER("\n");
+
+ if (!crtc)
+ return -ENODEV;
+
+ if (source && strcmp(source, "auto") != 0) {
+ DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
+ source, crtc->name);
+ return -EINVAL;
+ }
+
+ *values_cnt = 1;
+ return 0;
+}
+
+static void ltdc_crtc_atomic_print_state(struct drm_printer *p,
+ const struct drm_crtc_state *state)
+{
+ struct drm_crtc *crtc = state->crtc;
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+
+ drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err);
+ drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err);
+ drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn);
+ drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold);
}
static const struct drm_crtc_funcs ltdc_crtc_funcs = {
@@ -748,6 +1231,22 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = {
.enable_vblank = ltdc_crtc_enable_vblank,
.disable_vblank = ltdc_crtc_disable_vblank,
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+ .atomic_print_state = ltdc_crtc_atomic_print_state,
+};
+
+static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .enable_vblank = ltdc_crtc_enable_vblank,
+ .disable_vblank = ltdc_crtc_disable_vblank,
+ .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+ .set_crc_source = ltdc_crtc_set_crc_source,
+ .verify_crc_source = ltdc_crtc_verify_crc_source,
+ .atomic_print_state = ltdc_crtc_atomic_print_state,
};
/*
@@ -773,7 +1272,8 @@ static int ltdc_plane_atomic_check(struct drm_plane *plane,
/* Reject scaling */
if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
- DRM_ERROR("Scaling is not supported");
+ DRM_DEBUG_DRIVER("Scaling is not supported");
+
return -EINVAL;
}
@@ -784,6 +1284,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_device *ddev = plane->dev;
struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
plane);
struct drm_framebuffer *fb = newstate->fb;
@@ -793,7 +1294,8 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
u32 y0 = newstate->crtc_y;
u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
u32 src_x, src_y, src_w, src_h;
- u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
+ u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr;
+ u32 paddr, paddr1, paddr2;
enum ltdc_pix_fmt pf;
if (!newstate->crtc || !fb) {
@@ -813,19 +1315,23 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
newstate->crtc_w, newstate->crtc_h,
newstate->crtc_x, newstate->crtc_y);
- bpcr = reg_read(ldev->regs, LTDC_BPCR);
+ if (!pm_runtime_active(ddev->dev))
+ return;
+
+ regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
+
ahbp = (bpcr & BPCR_AHBP) >> 16;
avbp = bpcr & BPCR_AVBP;
/* Configures the horizontal start and stop position */
val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
- reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
- LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
+ regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
+ LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
/* Configures the vertical start and stop position */
val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
- reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
- LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
+ regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
+ LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
/* Specifies the pixel format */
pf = to_ltdc_pixelformat(fb->format->format);
@@ -833,24 +1339,20 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
if (ldev->caps.pix_fmt_hw[val] == pf)
break;
+ /* Use the flexible color format feature if necessary and available */
+ if (ldev->caps.pix_fmt_flex && val == NB_PF)
+ val = ltdc_set_flexible_pixel_format(plane, pf);
+
if (val == NB_PF) {
DRM_ERROR("Pixel format %.4s not supported\n",
(char *)&fb->format->format);
val = 0; /* set by default ARGB 32 bits */
}
- reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
-
- /* Configures the color frame buffer pitch in bytes & line length */
- pitch_in_bytes = fb->pitches[0];
- line_length = fb->format->cpp[0] *
- (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
- val = ((pitch_in_bytes << 16) | line_length);
- reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
- LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+ regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
/* Specifies the constant alpha value */
- val = CONSTA_MAX;
- reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
+ val = newstate->alpha >> 8;
+ regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
/* Specifies the blending factors */
val = BF1_PAXCA | BF2_1PAXCA;
@@ -862,35 +1364,168 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
plane->type != DRM_PLANE_TYPE_PRIMARY)
val = BF1_PAXCA | BF2_1PAXCA;
- reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
- LXBFCR_BF2 | LXBFCR_BF1, val);
-
- /* Configures the frame buffer line number */
- val = y1 - y0 + 1;
- reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
+ if (ldev->caps.dynamic_zorder) {
+ val |= (newstate->normalized_zpos << 16);
+ regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
+ LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val);
+ } else {
+ regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
+ LXBFCR_BF2 | LXBFCR_BF1, val);
+ }
/* Sets the FB address */
paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0);
+ if (newstate->rotation & DRM_MODE_REFLECT_X)
+ paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1;
+
+ if (newstate->rotation & DRM_MODE_REFLECT_Y)
+ paddr += (fb->pitches[0] * (y1 - y0));
+
DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
- reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
+ regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
+
+ /* Configures the color frame buffer pitch in bytes & line length */
+ line_length = fb->format->cpp[0] *
+ (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
+
+ if (newstate->rotation & DRM_MODE_REFLECT_Y)
+ /* Compute negative value (signed on 16 bits) for the picth */
+ pitch_in_bytes = 0x10000 - fb->pitches[0];
+ else
+ pitch_in_bytes = fb->pitches[0];
+
+ val = (pitch_in_bytes << 16) | line_length;
+ regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+
+ /* Configures the frame buffer line number */
+ line_number = y1 - y0 + 1;
+ regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
+
+ if (ldev->caps.ycbcr_input) {
+ if (fb->format->is_yuv) {
+ switch (fb->format->format) {
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ /* Configure the auxiliary frame buffer address 0 */
+ paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
+
+ if (newstate->rotation & DRM_MODE_REFLECT_X)
+ paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
+
+ if (newstate->rotation & DRM_MODE_REFLECT_Y)
+ paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
+
+ regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
+ break;
+ case DRM_FORMAT_YUV420:
+ /* Configure the auxiliary frame buffer address 0 & 1 */
+ paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
+ paddr2 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
+
+ if (newstate->rotation & DRM_MODE_REFLECT_X) {
+ paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
+ paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
+ }
+
+ if (newstate->rotation & DRM_MODE_REFLECT_Y) {
+ paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
+ paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
+ }
+
+ regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
+ regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
+ break;
+ case DRM_FORMAT_YVU420:
+ /* Configure the auxiliary frame buffer address 0 & 1 */
+ paddr1 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
+ paddr2 = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
+
+ if (newstate->rotation & DRM_MODE_REFLECT_X) {
+ paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
+ paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
+ }
+
+ if (newstate->rotation & DRM_MODE_REFLECT_Y) {
+ paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
+ paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
+ }
+
+ regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
+ regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
+ break;
+ }
+
+ /*
+ * Set the length and the number of lines of the auxiliary
+ * buffers if the framebuffer contains more than one plane.
+ */
+ if (fb->format->num_planes > 1) {
+ if (newstate->rotation & DRM_MODE_REFLECT_Y)
+ /*
+ * Compute negative value (signed on 16 bits)
+ * for the picth
+ */
+ pitch_in_bytes = 0x10000 - fb->pitches[1];
+ else
+ pitch_in_bytes = fb->pitches[1];
+
+ line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) +
+ (ldev->caps.bus_width >> 3) - 1;
+
+ /* Configure the auxiliary buffer length */
+ val = (pitch_in_bytes << 16) | line_length;
+ regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
+
+ /* Configure the auxiliary frame buffer line number */
+ val = line_number >> 1;
+ regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
+ }
+
+ /* Configure YCbC conversion coefficient */
+ ltdc_set_ycbcr_coeffs(plane);
+
+ /* Configure YCbCr format and enable/disable conversion */
+ ltdc_set_ycbcr_config(plane, fb->format->format);
+ } else {
+ /* disable ycbcr conversion */
+ regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
+ }
+ }
/* Enable layer and CLUT if needed */
val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
val |= LXCR_LEN;
- reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
- LXCR_LEN | LXCR_CLUTEN, val);
+
+ /* Enable horizontal mirroring if requested */
+ if (newstate->rotation & DRM_MODE_REFLECT_X)
+ val |= LXCR_HMEN;
+
+ regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val);
+
+ /* Commit shadow registers = update plane at next vblank */
+ if (ldev->caps.plane_reg_shadow)
+ regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
+ LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
ldev->plane_fpsi[plane->index].counter++;
mutex_lock(&ldev->err_lock);
- if (ldev->error_status & ISR_FUIF) {
- DRM_WARN("ltdc fifo underrun: please verify display mode\n");
- ldev->error_status &= ~ISR_FUIF;
+ if (ldev->transfer_err) {
+ DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err);
+ ldev->transfer_err = 0;
}
- if (ldev->error_status & ISR_TERRIF) {
- DRM_WARN("ltdc transfer error\n");
- ldev->error_status &= ~ISR_TERRIF;
+
+ if (ldev->caps.fifo_threshold) {
+ if (ldev->fifo_err) {
+ DRM_WARN("ltdc fifo underrun: please verify display mode\n");
+ ldev->fifo_err = 0;
+ }
+ } else {
+ if (ldev->fifo_warn >= ldev->fifo_threshold) {
+ DRM_WARN("ltdc fifo underrun: please verify display mode\n");
+ ldev->fifo_warn = 0;
+ }
}
mutex_unlock(&ldev->err_lock);
}
@@ -901,10 +1536,19 @@ static void ltdc_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
plane);
struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_device *ddev = plane->dev;
u32 lofs = plane->index * LAY_OFS;
- /* disable layer */
- reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
+ if (!pm_runtime_active(ddev->dev))
+ return;
+
+ /* Disable layer */
+ regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, 0);
+
+ /* Commit shadow registers = update plane at next vblank */
+ if (ldev->caps.plane_reg_shadow)
+ regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
+ LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
oldstate->crtc->base.id, plane->base.id);
@@ -957,36 +1601,57 @@ static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
};
static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
- enum drm_plane_type type)
+ enum drm_plane_type type,
+ int index)
{
unsigned long possible_crtcs = CRTC_MASK;
struct ltdc_device *ldev = ddev->dev_private;
struct device *dev = ddev->dev;
struct drm_plane *plane;
unsigned int i, nb_fmt = 0;
- u32 formats[NB_PF * 2];
- u32 drm_fmt, drm_fmt_no_alpha;
+ u32 *formats;
+ u32 drm_fmt;
const u64 *modifiers = ltdc_format_modifiers;
+ u32 lofs = index * LAY_OFS;
+ u32 val;
int ret;
- /* Get supported pixel formats */
- for (i = 0; i < NB_PF; i++) {
- drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
- if (!drm_fmt)
- continue;
- formats[nb_fmt++] = drm_fmt;
+ /* Allocate the biggest size according to supported color formats */
+ formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) +
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) +
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) *
+ sizeof(*formats), GFP_KERNEL);
- /* Add the no-alpha related format if any & supported */
- drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
- if (!drm_fmt_no_alpha)
- continue;
+ for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
+ drm_fmt = ldev->caps.pix_fmt_drm[i];
/* Manage hw-specific capabilities */
- if (ldev->caps.non_alpha_only_l1 &&
- type != DRM_PLANE_TYPE_PRIMARY)
- continue;
+ if (ldev->caps.non_alpha_only_l1)
+ if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
+ continue; /* XR24 & RX24 like formats supported only on primary layer */
- formats[nb_fmt++] = drm_fmt_no_alpha;
+ formats[nb_fmt++] = drm_fmt;
+ }
+
+ /* Add YCbCr supported pixel formats */
+ if (ldev->caps.ycbcr_input) {
+ regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
+ if (val & LXCR_C1R_YIA) {
+ memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp,
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats));
+ nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp);
+ }
+ if (val & LXCR_C1R_YSPA) {
+ memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp,
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats));
+ nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp);
+ }
+ if (val & LXCR_C1R_YFPA) {
+ memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp,
+ ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats));
+ nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp);
+ }
}
plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
@@ -999,8 +1664,21 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
if (ret < 0)
return NULL;
+ if (ldev->caps.ycbcr_input) {
+ if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA))
+ drm_plane_create_color_properties(plane,
+ BIT(DRM_COLOR_YCBCR_BT601) |
+ BIT(DRM_COLOR_YCBCR_BT709),
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+ DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
+ }
+
drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
+ drm_plane_create_alpha_property(plane);
+
DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
return plane;
@@ -1019,17 +1697,42 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
{
struct ltdc_device *ldev = ddev->dev_private;
struct drm_plane *primary, *overlay;
+ int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
unsigned int i;
int ret;
+ struct drm_connector *connector = NULL;
+ struct drm_connector_list_iter iter;
- primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
+ /* Add the dithering property to all connectors */
+ drm_connector_list_iter_begin(ddev, &iter);
+ drm_for_each_connector_iter(connector, &iter)
+ drm_connector_attach_dithering_property(connector,
+ BIT(DRM_MODE_DITHERING_OFF) |
+ BIT(DRM_MODE_DITHERING_ON));
+ drm_connector_list_iter_end(&iter);
+
+ primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
if (!primary) {
DRM_ERROR("Can not create primary plane\n");
return -EINVAL;
}
- ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
- &ltdc_crtc_funcs, NULL);
+ if (ldev->caps.dynamic_zorder)
+ drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1);
+ else
+ drm_plane_create_zpos_immutable_property(primary, 0);
+
+ if (ldev->caps.plane_rotation)
+ drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0,
+ supported_rotations);
+
+ /* Init CRTC according to its hardware features */
+ if (ldev->caps.crc)
+ ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
+ &ltdc_crtc_with_crc_support_funcs, NULL);
+ else
+ ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
+ &ltdc_crtc_funcs, NULL);
if (ret) {
DRM_ERROR("Can not initialize CRTC\n");
goto cleanup;
@@ -1044,12 +1747,20 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
/* Add planes. Note : the first layer is used by primary plane */
for (i = 1; i < ldev->caps.nb_layers; i++) {
- overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
+ overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
if (!overlay) {
ret = -ENOMEM;
DRM_ERROR("Can not create overlay plane %d\n", i);
goto cleanup;
}
+ if (ldev->caps.dynamic_zorder)
+ drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1);
+ else
+ drm_plane_create_zpos_immutable_property(overlay, i);
+
+ if (ldev->caps.plane_rotation)
+ drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0,
+ supported_rotations);
}
return 0;
@@ -1067,7 +1778,7 @@ static void ltdc_encoder_disable(struct drm_encoder *encoder)
DRM_DEBUG_DRIVER("\n");
/* Disable LTDC */
- reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+ regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
/* Set to sleep state the pinctrl whatever type of encoder */
pinctrl_pm_select_sleep_state(ddev->dev);
@@ -1080,8 +1791,12 @@ static void ltdc_encoder_enable(struct drm_encoder *encoder)
DRM_DEBUG_DRIVER("\n");
+ /* set fifo underrun threshold register */
+ if (ldev->caps.fifo_threshold)
+ regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold);
+
/* Enable LTDC */
- reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+ regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
}
static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
@@ -1144,21 +1859,25 @@ static int ltdc_get_caps(struct drm_device *ddev)
* at least 1 layer must be managed & the number of layers
* must not exceed LTDC_MAX_LAYER
*/
- lcr = reg_read(ldev->regs, LTDC_LCR);
+ regmap_read(ldev->regmap, LTDC_LCR, &lcr);
ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
/* set data bus width */
- gc2r = reg_read(ldev->regs, LTDC_GC2R);
+ regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
bus_width_log2 = (gc2r & GC2R_BW) >> 4;
ldev->caps.bus_width = 8 << bus_width_log2;
- ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
+ regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
switch (ldev->caps.hw_version) {
case HWVER_10200:
case HWVER_10300:
- ldev->caps.reg_ofs = REG_OFS_NONE;
+ ldev->caps.layer_ofs = LAY_OFS_0;
+ ldev->caps.layer_regs = ltdc_layer_regs_a0;
ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
+ ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
+ ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
+ ldev->caps.pix_fmt_flex = false;
/*
* Hw older versions support non-alpha color formats derived
* from native alpha color formats only on the primary layer.
@@ -1171,13 +1890,49 @@ static int ltdc_get_caps(struct drm_device *ddev)
if (ldev->caps.hw_version == HWVER_10200)
ldev->caps.pad_max_freq_hz = 65000000;
ldev->caps.nb_irq = 2;
+ ldev->caps.ycbcr_input = false;
+ ldev->caps.ycbcr_output = false;
+ ldev->caps.plane_reg_shadow = false;
+ ldev->caps.crc = false;
+ ldev->caps.dynamic_zorder = false;
+ ldev->caps.plane_rotation = false;
+ ldev->caps.fifo_threshold = false;
break;
case HWVER_20101:
- ldev->caps.reg_ofs = REG_OFS_4;
+ ldev->caps.layer_ofs = LAY_OFS_0;
+ ldev->caps.layer_regs = ltdc_layer_regs_a1;
ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
+ ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
+ ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
+ ldev->caps.pix_fmt_flex = false;
ldev->caps.non_alpha_only_l1 = false;
ldev->caps.pad_max_freq_hz = 150000000;
ldev->caps.nb_irq = 4;
+ ldev->caps.ycbcr_input = false;
+ ldev->caps.ycbcr_output = false;
+ ldev->caps.plane_reg_shadow = false;
+ ldev->caps.crc = false;
+ ldev->caps.dynamic_zorder = false;
+ ldev->caps.plane_rotation = false;
+ ldev->caps.fifo_threshold = false;
+ break;
+ case HWVER_40100:
+ ldev->caps.layer_ofs = LAY_OFS_1;
+ ldev->caps.layer_regs = ltdc_layer_regs_a2;
+ ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
+ ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
+ ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
+ ldev->caps.pix_fmt_flex = true;
+ ldev->caps.non_alpha_only_l1 = false;
+ ldev->caps.pad_max_freq_hz = 90000000;
+ ldev->caps.nb_irq = 2;
+ ldev->caps.ycbcr_input = true;
+ ldev->caps.ycbcr_output = true;
+ ldev->caps.plane_reg_shadow = true;
+ ldev->caps.crc = true;
+ ldev->caps.dynamic_zorder = true;
+ ldev->caps.plane_rotation = true;
+ ldev->caps.fifo_threshold = true;
break;
default:
return -ENODEV;
@@ -1220,7 +1975,6 @@ int ltdc_load(struct drm_device *ddev)
struct drm_panel *panel;
struct drm_crtc *crtc;
struct reset_control *rstc;
- struct resource *res;
int irq, i, nb_endpoints;
int ret = -ENODEV;
@@ -1287,17 +2041,19 @@ int ltdc_load(struct drm_device *ddev)
reset_control_deassert(rstc);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ldev->regs = devm_ioremap_resource(dev, res);
+ ldev->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ldev->regs)) {
DRM_ERROR("Unable to get ltdc registers\n");
ret = PTR_ERR(ldev->regs);
goto err;
}
- /* Disable interrupts */
- reg_clear(ldev->regs, LTDC_IER,
- IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
+ ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
+ if (IS_ERR(ldev->regmap)) {
+ DRM_ERROR("Unable to regmap ltdc registers\n");
+ ret = PTR_ERR(ldev->regmap);
+ goto err;
+ }
ret = ltdc_get_caps(ddev);
if (ret) {
@@ -1306,8 +2062,22 @@ int ltdc_load(struct drm_device *ddev)
goto err;
}
+ /* Disable interrupts */
+ if (ldev->caps.fifo_threshold)
+ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
+ IER_TERRIE);
+ else
+ regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
+ IER_TERRIE | IER_FUEIE);
+
DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
+ /* initialize default value for fifo underrun threshold & clear interrupt error counters */
+ ldev->transfer_err = 0;
+ ldev->fifo_err = 0;
+ ldev->fifo_warn = 0;
+ ldev->fifo_threshold = FUT_DFT;
+
for (i = 0; i < ldev->caps.nb_irq; i++) {
irq = platform_get_irq(pdev, i);
if (irq < 0) {
@@ -1322,7 +2092,6 @@ int ltdc_load(struct drm_device *ddev)
DRM_ERROR("Failed to register LTDC interrupt\n");
goto err;
}
-
}
crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index f153b908c70e..12ee90c8b504 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -14,12 +14,23 @@
struct ltdc_caps {
u32 hw_version; /* hardware version */
u32 nb_layers; /* number of supported layers */
- u32 reg_ofs; /* register offset for applicable regs */
+ u32 layer_ofs; /* layer offset for applicable regs */
+ const u32 *layer_regs; /* layer register offset */
u32 bus_width; /* bus width (32 or 64 bits) */
- const u32 *pix_fmt_hw; /* supported pixel formats */
+ const u32 *pix_fmt_hw; /* supported hw pixel formats */
+ const u32 *pix_fmt_drm; /* supported drm pixel formats */
+ int pix_fmt_nb; /* number of pixel format */
+ bool pix_fmt_flex; /* pixel format flexibility supported */
bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
int pad_max_freq_hz; /* max frequency supported by pad */
int nb_irq; /* number of hardware interrupts */
+ bool ycbcr_input; /* ycbcr input converter supported */
+ bool ycbcr_output; /* ycbcr output converter supported */
+ bool plane_reg_shadow; /* plane shadow registers ability */
+ bool crc; /* cyclic redundancy check supported */
+ bool dynamic_zorder; /* dynamic z-order */
+ bool plane_rotation; /* plane rotation */
+ bool fifo_threshold; /* fifo underrun threshold supported */
};
#define LTDC_MAX_LAYER 4
@@ -31,13 +42,19 @@ struct fps_info {
struct ltdc_device {
void __iomem *regs;
+ struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
- struct mutex err_lock; /* protecting error_status */
+ struct mutex err_lock; /* protecting transfer_err, fifo_err, fifo_warn */
+ u32 transfer_err; /* transfer error counter */
+ u32 fifo_err; /* fifo underrun error counter */
+ u32 fifo_warn; /* fifo underrun warning counter */
+ u32 fifo_threshold; /* fifo underrun threshold */
struct ltdc_caps caps;
- u32 error_status;
u32 irq_status;
struct fps_info plane_fpsi[LTDC_MAX_LAYER];
struct drm_atomic_state *suspend_state;
+ int crc_skip_count;
+ bool crc_active;
};
int ltdc_load(struct drm_device *ddev);
diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c
index 6f78d928f054..d3fa3a8bef4d 100644
--- a/drivers/video/backlight/gpio_backlight.c
+++ b/drivers/video/backlight/gpio_backlight.c
@@ -53,6 +53,7 @@ static int gpio_backlight_probe(struct platform_device *pdev)
struct backlight_device *bl;
struct gpio_backlight *gbl;
int ret, init_brightness, def_value;
+ u32 value;
gbl = devm_kzalloc(dev, sizeof(*gbl), GFP_KERNEL);
if (gbl == NULL)
@@ -93,7 +94,11 @@ static int gpio_backlight_probe(struct platform_device *pdev)
else
bl->props.power = FB_BLANK_UNBLANK;
- bl->props.brightness = 1;
+ ret = device_property_read_u32(dev, "default-brightness-level", &value);
+ if (!ret && value <= props.max_brightness)
+ bl->props.brightness = value;
+ else
+ bl->props.brightness = 1;
init_brightness = backlight_get_brightness(bl);
ret = gpiod_direction_output(gbl->gpiod, init_brightness);
diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c
index a2e3a4690025..efce6ef8532d 100644
--- a/drivers/video/fbdev/simplefb.c
+++ b/drivers/video/fbdev/simplefb.c
@@ -547,26 +547,7 @@ static struct platform_driver simplefb_driver = {
.remove = simplefb_remove,
};
-static int __init simplefb_init(void)
-{
- int ret;
- struct device_node *np;
-
- ret = platform_driver_register(&simplefb_driver);
- if (ret)
- return ret;
-
- if (IS_ENABLED(CONFIG_OF_ADDRESS) && of_chosen) {
- for_each_child_of_node(of_chosen, np) {
- if (of_device_is_compatible(np, "simple-framebuffer"))
- of_platform_device_create(np, NULL, NULL);
- }
- }
-
- return 0;
-}
-
-fs_initcall(simplefb_init);
+module_platform_driver(simplefb_driver);
MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
MODULE_DESCRIPTION("Simple framebuffer driver");
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index bda8aa7c2280..5286a53a1875 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -51,7 +51,9 @@ struct dw_mipi_dsi_plat_data {
unsigned int max_data_lanes;
enum drm_mode_status (*mode_valid)(void *priv_data,
- const struct drm_display_mode *mode);
+ const struct drm_display_mode *mode,
+ unsigned long mode_flags,
+ u32 lanes, u32 format);
const struct dw_mipi_dsi_phy_ops *phy_ops;
const struct dw_mipi_dsi_host_ops *host_ops;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 1f43d7c6724a..ea40115df680 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -749,6 +749,12 @@ struct drm_connector_state {
*/
unsigned int scaling_mode;
+ /**
+ * @dithering: Connector property to control the
+ * dithering.
+ */
+ unsigned int dithering;
+
/**
* @content_protection: Connector property to request content
* protection. This is most commonly used for HDCP.
@@ -1360,6 +1366,12 @@ struct drm_connector {
*/
struct drm_property *scaling_mode_property;
+ /**
+ * @dithering_property: Optional atomic property to control the
+ * dithering.
+ */
+ struct drm_property *dithering_property;
+
/**
* @vrr_capable_property: Optional property to help userspace
* query hardware support for variable refresh rate on a connector.
@@ -1680,6 +1692,8 @@ int drm_mode_create_scaling_mode_property(struct drm_device *dev);
int drm_connector_attach_content_type_property(struct drm_connector *dev);
int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
u32 scaling_mode_mask);
+int drm_connector_attach_dithering_property(struct drm_connector *connector,
+ u32 dithering_mask);
int drm_connector_attach_vrr_capable_property(
struct drm_connector *connector);
int drm_connector_attach_colorspace_property(struct drm_connector *connector);
--
2.17.1
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