public
/
meta-st-stm32mp
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
meta-st-stm32mp/recipes-kernel/linux/linux-stm32mp/5.15/5.15.118/0021-v5.15-stm32mp-r2.1-DEV...

13142 lines
332 KiB
Diff
Raw Blame History

From df78c49519afe6e19ebf5879a8f5a4cd55d51426 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Fri, 7 Jul 2023 16:13:36 +0200
Subject: [PATCH 21/22] v5.15-stm32mp-r2.1 DEVICETREE
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
.../arm/firmware/linaro,optee-tz.yaml | 8 +
.../devicetree/bindings/arm/stm32/stm32.yaml | 4 +
.../bindings/cpufreq/stm32-cpufreq.txt | 61 +
.../bindings/crypto/st,stm32-cryp.yaml | 9 +
.../bindings/crypto/st,stm32-hash.yaml | 1 +
.../bindings/display/panel/panel-dpi.yaml | 10 +
.../display/panel/rocktech,hx8394.yaml | 56 +
.../devicetree/bindings/dma/st,stm32-dma.yaml | 47 +
.../bindings/dma/st,stm32-mdma.yaml | 12 +-
.../devicetree/bindings/hwlock/hwlock.txt | 27 +-
.../bindings/hwlock/st,stm32-hwspinlock.yaml | 4 +-
.../devicetree/bindings/i2c/st,stm32-i2c.yaml | 2 +
.../iio/adc/sigma-delta-modulator.yaml | 3 +
.../bindings/iio/adc/st,stm32-adc.yaml | 175 +-
.../interrupt-controller/st,stm32-exti.yaml | 39 +-
.../leds/backlight/gpio-backlight.yaml | 9 +
.../bindings/media/i2c/galaxycore,gc2145.yaml | 115 ++
.../bindings/media/st,stm32-dcmipp.yaml | 96 +
.../bindings/mfd/st,stm32-lptimer.yaml | 3 +
.../bindings/mfd/st,stm32mp1-pwr.txt | 57 +
.../devicetree/bindings/mmc/arm,pl18x.yaml | 6 +
.../bindings/mtd/nand-controller.yaml | 7 +
.../bindings/nvmem/st,stm32-romem.yaml | 8 +
.../bindings/perf/stm32-ddr-pmu.yaml | 44 +
.../bindings/phy/phy-stm32-usbphyc.yaml | 133 ++
.../bindings/pinctrl/st,stm32-pinctrl.yaml | 8 +
.../regulator/protection-consumer.txt | 23 +
.../bindings/regulator/st,stm32-vrefbuf.yaml | 4 +-
.../bindings/remoteproc/rproc-srm.txt | 58 +
.../bindings/remoteproc/st,stm32-rproc.yaml | 25 +-
.../devicetree/bindings/rng/st,stm32-rng.yaml | 4 +-
.../devicetree/bindings/rtc/st,stm32-rtc.yaml | 37 +
.../devicetree/bindings/serial/rs485.yaml | 14 +
.../bindings/serial/st,stm32-uart.yaml | 5 +
.../bindings/soc/stm32/st,stm32mp1-hslv.yaml | 44 +
.../bindings/soc/stm32/stm32_hdp.txt | 39 +
.../bindings/spi/st,stm32-qspi.yaml | 8 +
.../devicetree/bindings/spi/st,stm32-spi.yaml | 23 +
.../devicetree/bindings/usb/dwc2.yaml | 38 +-
.../devicetree/bindings/usb/generic-ehci.yaml | 5 +
.../devicetree/bindings/usb/generic-ohci.yaml | 5 +
.../bindings/usb/st,typec-stm32g0.yaml | 83 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm/boot/dts/Makefile | 60 +
arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 644 ++++++
arch/arm/boot/dts/stm32mp131.dtsi | 1742 +++++++++++++++++
arch/arm/boot/dts/stm32mp133.dtsi | 100 +
arch/arm/boot/dts/stm32mp135.dtsi | 32 +
.../boot/dts/stm32mp135f-dk-a7-examples.dts | 22 +
arch/arm/boot/dts/stm32mp135f-dk.dts | 704 +++++++
arch/arm/boot/dts/stm32mp13xa.dtsi | 5 +
arch/arm/boot/dts/stm32mp13xc.dtsi | 21 +
arch/arm/boot/dts/stm32mp13xd.dtsi | 5 +
arch/arm/boot/dts/stm32mp13xf.dtsi | 21 +
.../boot/dts/stm32mp15-m4-srm-pinctrl.dtsi | 524 +++++
arch/arm/boot/dts/stm32mp15-m4-srm.dtsi | 447 +++++
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 314 ++-
arch/arm/boot/dts/stm32mp151.dtsi | 661 +++++--
arch/arm/boot/dts/stm32mp153.dtsi | 15 +-
arch/arm/boot/dts/stm32mp157.dtsi | 3 +-
.../boot/dts/stm32mp157a-dk1-a7-examples.dts | 95 +
.../boot/dts/stm32mp157a-dk1-m4-examples.dts | 128 ++
arch/arm/boot/dts/stm32mp157a-dk1.dts | 8 +-
arch/arm/boot/dts/stm32mp157a-ed1.dts | 32 +
arch/arm/boot/dts/stm32mp157a-ev1.dts | 103 +
.../boot/dts/stm32mp157c-dk2-a7-examples.dts | 95 +
.../boot/dts/stm32mp157c-dk2-m4-examples.dts | 128 ++
arch/arm/boot/dts/stm32mp157c-dk2.dts | 67 +-
arch/arm/boot/dts/stm32mp157c-ed1.dts | 374 +---
.../boot/dts/stm32mp157c-ev1-a7-examples.dts | 57 +
.../boot/dts/stm32mp157c-ev1-m4-examples.dts | 150 ++
arch/arm/boot/dts/stm32mp157c-ev1.dts | 326 +--
.../boot/dts/stm32mp157d-dk1-a7-examples.dts | 95 +
.../boot/dts/stm32mp157d-dk1-m4-examples.dts | 128 ++
arch/arm/boot/dts/stm32mp157d-dk1.dts | 26 +
arch/arm/boot/dts/stm32mp157d-ed1.dts | 32 +
arch/arm/boot/dts/stm32mp157d-ev1.dts | 103 +
.../boot/dts/stm32mp157f-dk2-a7-examples.dts | 95 +
.../boot/dts/stm32mp157f-dk2-m4-examples.dts | 128 ++
arch/arm/boot/dts/stm32mp157f-dk2.dts | 154 ++
arch/arm/boot/dts/stm32mp157f-ed1.dts | 36 +
.../boot/dts/stm32mp157f-ev1-a7-examples.dts | 57 +
.../boot/dts/stm32mp157f-ev1-m4-examples.dts | 151 ++
arch/arm/boot/dts/stm32mp157f-ev1.dts | 99 +
arch/arm/boot/dts/stm32mp15xa.dtsi | 13 +
arch/arm/boot/dts/stm32mp15xc.dtsi | 9 +-
arch/arm/boot/dts/stm32mp15xd.dtsi | 42 +
arch/arm/boot/dts/stm32mp15xf.dtsi | 23 +
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 12 +-
.../boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 28 +-
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 143 +-
arch/arm/boot/dts/stm32mp15xx-edx.dtsi | 429 ++++
arch/arm/boot/dts/stm32mp15xx-evx.dtsi | 698 +++++++
93 files changed, 9717 insertions(+), 1028 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
create mode 100644 Documentation/devicetree/bindings/display/panel/rocktech,hx8394.yaml
create mode 100644 Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/protection-consumer.txt
create mode 100644 Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
create mode 100644 Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
create mode 100644 Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
create mode 100644 Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
create mode 100644 arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp131.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp133.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp135.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp135f-dk-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp135f-dk.dts
create mode 100644 arch/arm/boot/dts/stm32mp13xa.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp13xc.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp13xd.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp13xf.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15-m4-srm.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp157a-dk1-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157a-dk1-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157a-ed1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157a-ev1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157d-dk1-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157d-dk1-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157d-dk1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157d-ed1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157d-ev1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-dk2.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-ed1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
create mode 100644 arch/arm/boot/dts/stm32mp157f-ev1.dts
create mode 100644 arch/arm/boot/dts/stm32mp15xa.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15xd.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15xf.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15xx-edx.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp15xx-evx.dtsi
diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
index c24047c1fdd5..9a426110a14a 100644
--- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
+++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
@@ -24,6 +24,12 @@ properties:
compatible:
const: linaro,optee-tz
+ interrupts:
+ maxItems: 1
+ description: |
+ This interrupt which is used to signal an event by the secure world
+ software is expected to be edge-triggered.
+
method:
enum: [smc, hvc]
description: |
@@ -42,10 +48,12 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
+ interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
};
};
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index 9a77ab74be99..9ac7da01c6c3 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -55,6 +55,10 @@ properties:
- enum:
- st,stm32h750i-art-pi
- const: st,stm32h750
+ - items:
+ - enum:
+ - st,stm32mp135f-dk
+ - const: st,stm32mp135
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box
diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
new file mode 100644
index 000000000000..1292eb2612a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
@@ -0,0 +1,61 @@
+STM32 CPUFreq and OPP bindings
+==============================
+
+STM32 CPUFreq driver needs to read chip information from the SoC to list
+available OPPs. Then it depends on cpufreq-dt bindings.
+
+Required properties:
+--------------------
+- clocks: Phandle to the cpu clock "cpu".
+- clocks-name: Should contain "cpu".
+- nvmem-cells: Phandle to nvmem cell that contains "part_number".
+- nvmem-cell-names: Must be "part_number".
+- operating-points-v2: Phandle to operating points table. See ../power/opp.txt
+ for more details.
+
+Optional properties:
+--------------------
+See cpufreq-dt.txt for optional properties.
+
+Examples:
+---------
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
index a4574552502a..6c3f8f7bfd67 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
@@ -27,6 +27,15 @@ properties:
resets:
maxItems: 1
+ dmas:
+ maxItems: 2
+ minItems: 2
+
+ dma-names:
+ items:
+ - const: in
+ - const: out
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 6dd658f0912c..1a944608d8ff 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- st,stm32f456-hash
- st,stm32f756-hash
+ - st,stm32mp13-hash
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
index dae0676b5c6e..8965b627dd3e 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
@@ -21,6 +21,15 @@ properties:
- {}
- const: panel-dpi
+ data-mapping:
+ enum:
+ - rgb24
+ - rgb565
+ - bgr666
+ description: |
+ Describes the media format, how the display panel is connected
+ to the display interface.
+
backlight: true
enable-gpios: true
height-mm: true
@@ -43,6 +52,7 @@ examples:
compatible = "startek,startek-kd050c", "panel-dpi";
label = "osddisplay";
power-supply = <&vcc_supply>;
+ data-mapping = "rgb565";
backlight = <&backlight>;
port {
diff --git a/Documentation/devicetree/bindings/display/panel/rocktech,hx8394.yaml b/Documentation/devicetree/bindings/display/panel/rocktech,hx8394.yaml
new file mode 100644
index 000000000000..db548d94e545
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/rocktech,hx8394.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/rocktech,hx8394.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKTECH DISPLAYS LIMITED HX8394 5.5" 720p MIPI-DSI TFT LCD panel
+
+maintainers:
+ - Yannick Fertre <yannick.fertre@foss.st.com>
+
+description: |
+ The ROCKTECH DISPLAYS LIMITED HX8394 is a 5.5" 720x1280 TFT LCD
+ panel connected using a MIPI-DSI video interface.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+
+ compatible:
+ const: rocktech,hx8394
+
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ backlight: true
+ enable-gpios: true
+ port: true
+ power-supply: true
+
+ reset-gpios:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - power-supply
+ - reg
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "rocktech,hx8394";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 0>;
+ power-supply = <&v1v8>;
+ backlight = <&pwm_backlight>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 4bf676fd25dc..99351fe0fa17 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -47,6 +47,14 @@ description: |
not wait for the de-assertion of the REQuest, ACK is only managed
by transfer completion. This must only be used on channels
managing transfers for STM32 USART/UART.
+ -bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
+ Order is given by those 2 bits starting at 0.
+ Valid only whether Intermediate M2M transfer is set.
+ For cyclic, whether Intermediate M2M transfer is chosen, any value can be set:
+ SRAM buffer size will rely on period size and not on this DT value.
+ -bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
+ 0: MDMA not used to generate an intermediate M2M transfer
+ 1: MDMA used to generate an intermediate M2M transfer.
maintainers:
@@ -82,6 +90,35 @@ properties:
description: if defined, it indicates that the controller
supports memory-to-memory transfer
+ dmas:
+ description: A list of eight dma specifiers, one for each entry in dma-names.
+ Refer to stm32-mdma.yaml for more details.
+ items:
+ - description: DMA channel 0 connected to the MDMA channel specified
+ - description: DMA channel 1 connected to the MDMA channel specified
+ - description: DMA channel 2 connected to the MDMA channel specified
+ - description: DMA channel 3 connected to the MDMA channel specified
+ - description: DMA channel 4 connected to the MDMA channel specified
+ - description: DMA channel 5 connected to the MDMA channel specified
+ - description: DMA channel 6 connected to the MDMA channel specified
+ - description: DMA channel 7 connected to the MDMA channel specified
+
+ dma-names:
+ description: Represents each STM32 DMA channel connected to a STM32 MDMA one.
+ items:
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+
+ memory-region:
+ description: Phandle to a node describing memory to be used for M2M intermediate transfer
+ between DMA and MDMA.
+
required:
- compatible
- reg
@@ -111,6 +148,16 @@ examples:
st,mem2mem;
resets = <&rcc 150>;
dma-requests = <8>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x40026408 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x40026408 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x40026408 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x40026408 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4002640C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4002640C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4002640C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4002640C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ memory-region = <&sram_dmapool>;
};
...
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
index c30be840be1c..c4bb58014374 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
@@ -10,8 +10,8 @@ description: |
The STM32 MDMA is a general-purpose direct memory access controller capable of
supporting 64 independent DMA channels with 256 HW requests.
DMA clients connected to the STM32 MDMA controller must use the format
- described in the dma.txt file, using a five-cell specifier for each channel:
- a phandle to the MDMA controller plus the following five integer cells:
+ described in the dma.txt file, using a six-cell specifier for each channel:
+ a phandle to the MDMA controller plus the following six integer cells:
1. The request line number
2. The priority level
0x0: Low
@@ -48,6 +48,10 @@ description: |
if no HW ack signal is used by the MDMA client
5. A 32bit mask specifying the value to be written to acknowledge the request
if no HW ack signal is used by the MDMA client
+ 6. A bitfield value specifying if the MDMA client wants to generate M2M transfer
+ with HW trigger (1) or not (0). This bitfield should be only enabled for
+ M2M transfer triggered by STM32 DMA client. The memory devices involved in this
+ kind of transfer are SRAM and DDR.
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
@@ -57,7 +61,7 @@ allOf:
properties:
"#dma-cells":
- const: 5
+ const: 6
compatible:
const: st,stm32h7-mdma
@@ -97,7 +101,7 @@ examples:
interrupts = <122>;
clocks = <&timer_clk>;
resets = <&rcc 992>;
- #dma-cells = <5>;
+ #dma-cells = <6>;
dma-channels = <16>;
dma-requests = <32>;
st,ahb-addr-masks = <0x20000000>, <0x00000000>;
diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt
index 085d1f5c916a..e98088a409ba 100644
--- a/Documentation/devicetree/bindings/hwlock/hwlock.txt
+++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt
@@ -13,7 +13,7 @@ hwlock providers:
Required properties:
- #hwlock-cells: Specifies the number of cells needed to represent a
- specific lock.
+ specific lock. Shall be 1 or 2 (see hwlocks below).
hwlock users:
=============
@@ -27,6 +27,11 @@ Required properties:
#hwlock-cells. The list can have just a single hwlock
or multiple hwlocks, with each hwlock represented by
a phandle and a corresponding args specifier.
+ If #hwlock-cells is 1, all of the locks are exclusive
+ (cannot be used by several users).
+ If #hwlock-cells is 2, the value of the second cell
+ defines whether the lock is for exclusive usage (0) or
+ shared (1) i.e. can be used by several users.
Optional properties:
- hwlock-names: List of hwlock name strings defined in the same order
@@ -46,14 +51,22 @@ of length 1.
...
};
-2. Example of a node using multiple specific hwlocks:
+2. Example of nodes using multiple and shared specific hwlocks:
-The following example has a node requesting two hwlocks, a hwlock within
-the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
-hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.
+The following example has a nodeA requesting two hwlocks:
+- an exclusive one (#hwlock-cells = 1) within the hwlock device node 'hwlock1'
+- a shared one (#hwlock-cells = 2, second cell = 1) within the hwlock device
+ node 'hwlock2'.
+The shared lock is also be used by nodeB.
- node {
+ nodeA {
...
- hwlocks = <&hwlock1 2>, <&hwlock2 0 3>;
+ hwlocks = <&hwlock1 2>, <&hwlock2 0 1>;
...
};
+
+ nodeB {
+ ...
+ hwlocks = <&hwlock2 0 1>;
+ ...
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
index 47cf9c8d97e9..539a1dc052b7 100644
--- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
+++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
@@ -12,7 +12,7 @@ maintainers:
properties:
"#hwlock-cells":
- const: 1
+ const: 2
compatible:
const: st,stm32-hwspinlock
@@ -41,7 +41,7 @@ examples:
#include <dt-bindings/clock/stm32mp1-clks.h>
hwspinlock@4c000000 {
compatible = "st,stm32-hwspinlock";
- #hwlock-cells = <1>;
+ #hwlock-cells = <2>;
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
clock-names = "hsem";
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index d747f4990ad8..5df3dbd6091f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -17,6 +17,7 @@ allOf:
contains:
enum:
- st,stm32f7-i2c
+ - st,stm32mp13-i2c
- st,stm32mp15-i2c
then:
properties:
@@ -52,6 +53,7 @@ properties:
enum:
- st,stm32f4-i2c
- st,stm32f7-i2c
+ - st,stm32mp13-i2c
- st,stm32mp15-i2c
reg:
diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
index a390343d0c2a..bf5d71fb60da 100644
--- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
@@ -21,6 +21,9 @@ properties:
'#io-channel-cells':
const: 0
+ vref-supply:
+ description: Phandle to the vref input analog reference voltage.
+
required:
- compatible
- '#io-channel-cells'
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index a58334c3bb76..47883701e331 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -27,6 +27,7 @@ properties:
- st,stm32f4-adc-core
- st,stm32h7-adc-core
- st,stm32mp1-adc-core
+ - st,stm32mp13-adc-core
reg:
maxItems: 1
@@ -37,6 +38,7 @@ properties:
- stm32f4 and stm32h7 share a common ADC interrupt line.
- stm32mp1 has two separate interrupt lines, one for each ADC within
ADC block.
+ - stm32mp13 has an interrupt line per ADC block.
minItems: 1
maxItems: 2
@@ -182,6 +184,34 @@ allOf:
maximum: 36000000
default: 36000000
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc-core
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: bus
+ - const: adc
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ items:
+ - description: ADC interrupt line
+
+ st,max-clk-rate-hz:
+ minimum: 120000
+ maximum: 36000000
+ default: 36000000
+
additionalProperties: false
required:
@@ -210,6 +240,7 @@ patternProperties:
- st,stm32f4-adc
- st,stm32h7-adc
- st,stm32mp1-adc
+ - st,stm32mp13-adc
reg:
description: |
@@ -222,10 +253,16 @@ patternProperties:
'#io-channel-cells':
const: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
interrupts:
description: |
IRQ Line for the ADC instance. Valid values are:
- - 0 for adc@0
+ - 0 for adc@0 (single adc for stm32mp13)
- 1 for adc@100
- 2 for adc@200 (stm32f4 only)
maxItems: 1
@@ -246,16 +283,18 @@ patternProperties:
assigned-resolution-bits:
description: |
Resolution (bits) to use for conversions:
- - can be 6, 8, 10 or 12 on stm32f4
+ - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
- can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
st,adc-channels:
description: |
List of single-ended channels muxed for this ADC. It can have up to:
- 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
+ - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
- 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
stm32mp1.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
st,adc-diff-channels:
description: |
@@ -265,7 +304,9 @@ patternProperties:
<vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
- required. Both properties can be used together. Some channels can be
+ required if no adc generic channel is defined. These legacy channel
+ properties are exclusive with adc generic channel bindings.
+ Both properties can be used together. Some channels can be
used as single-ended and some other ones as differential (mixed). But
channels can't be configured both as single-ended and differential.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
@@ -279,6 +320,7 @@ patternProperties:
"vinn" indicates negative input number
minimum: 0
maximum: 19
+ deprecated: true
st,min-sample-time-nsecs:
description:
@@ -289,6 +331,50 @@ patternProperties:
list, to set sample time resp. for all channels, or independently for
each channel.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
+
+ nvmem-cells:
+ items:
+ - description: Phandle to the calibration vrefint data provided by otp
+
+ nvmem-cell-names:
+ items:
+ - const: vrefint
+
+ patternProperties:
+ "^channel@([0-9]|1[0-9])$":
+ type: object
+ $ref: "adc.yaml"
+ description: Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 19
+
+ label:
+ description: |
+ Unique name to identify which channel this is.
+ Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
+ are used to identify internal channels with matching names.
+
+ diff-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minimum: 0
+ maximum: 19
+
+ st,min-sample-time-ns:
+ description: |
+ Minimum sampling time in nanoseconds. Depending on hardware (board)
+ e.g. high/low analog input source impedance, fine tune of ADC
+ sampling time may be recommended.
+
+ required:
+ - reg
+
+ additionalProperties: false
allOf:
- if:
@@ -367,13 +453,38 @@ patternProperties:
items:
minimum: 40
- additionalProperties: false
- anyOf:
- - required:
- - st,adc-channels
- - required:
- - st,adc-diff-channels
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc
+
+ then:
+ properties:
+ reg:
+ const: 0x0
+
+ interrupts:
+ const: 0
+
+ assigned-resolution-bits:
+ enum: [6, 8, 10, 12]
+ default: 12
+
+ st,adc-channels:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 0
+ maximum: 18
+
+ st,min-sample-time-nsecs:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 40
+ additionalProperties: false
required:
- compatible
@@ -451,4 +562,50 @@ examples:
// other adc child node follow...
};
+ - |
+ // Example 3: with stm32mp157c to setup ADC2 with:
+ // - internal channels 13, 14, 15.
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ adc122: adc@48003000 {
+ compatible = "st,stm32mp1-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ booster-supply = <&booster>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vref>;
+ st,syscfg = <&syscfg>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@100 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@15 {
+ reg = <15>;
+ label = "vbat";
+ st,min-sample-time-ns = <9000>;
+ };
+ };
+ };
+
...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml
index 6d3e68eb2e8b..e3126b712469 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml
@@ -20,6 +20,7 @@ properties:
- items:
- enum:
- st,stm32mp1-exti
+ - st,stm32mp13-exti
- const: syscon
"#interrupt-cells":
@@ -41,6 +42,24 @@ properties:
description:
Interrupts references to primary interrupt controller
+ wakeup-parent: true
+
+patternProperties:
+ '^exti-interrupt-map$':
+ type: object
+ properties:
+ interrupt-map: true
+ interrupt-map-mask: true
+ "#interrupt-cells":
+ const: 2
+ "#address-cells":
+ const: 0
+
+ required:
+ - interrupt-map
+ - "#interrupt-cells"
+ - "#address-cells"
+
required:
- "#interrupt-cells"
- compatible
@@ -89,7 +108,25 @@ examples:
};
//Example 2
- exti2: interrupt-controller@40013c00 {
+ exti1: interrupt-controller@5000d000 {
+ compatible = "st,stm32mp1-exti", "syscon";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000d000 0x400>;
+ wakeup-parent = <&pwr_irq>;
+ exti-interrupt-map {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-map-mask = <0xffffffff 0>;
+ interrupt-map =
+ <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <55 0 &pwr_irq 0 IRQ_TYPE_EDGE_FALLING 0>;
+ };
+ };
+
+ //Example 3
+ exti3: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
index 75cc569b9c55..3097aa976ad6 100644
--- a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
+++ b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
@@ -23,6 +23,15 @@ properties:
description: enable the backlight at boot.
type: boolean
+ default-brightness-level:
+ description:
+ The default brightness level (index into the array defined by the
+ "brightness-levels" property).
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+dependencies:
+ default-brightness-level: [brightness-levels]
+
required:
- compatible
- gpios
diff --git a/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml b/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
new file mode 100644
index 000000000000..af07250ceadb
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/galaxycore,gc2145.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc2145.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Galaxy Core 1/5'' UXGA CMOS Image Sensor
+
+maintainers:
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+description: |
+ The Galaxy Core GC2145 is a high quality 2 Mega CMOS image sensor, for mobile phone camera
+ applications and digital camera products. GC2145 incorporates a 1616V x 1232H active pixel
+ array, on-chip 10-bit ADC, and image signal processor. It is programmable through an I2C
+ interface. Image data is sent either through a parallel interface or through MIPI CSI-2.
+
+allOf:
+ - $ref: ../video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: galaxycore,gc2145
+
+ reg:
+ enum:
+ - 0x3c
+
+ clocks:
+ description: Reference to the xclk clock.
+ maxItems: 1
+
+ powerdown-gpios:
+ description: GPIO descriptor for the powerdown pin.
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO descriptor for the reset pin.
+ maxItems: 1
+
+ IOVDD-supply:
+ description: Power Supply for I/O circuits (1.7 - 3V).
+
+ AVDD-supply:
+ description: Power for analog circuit/sensor array (2.7 - 3V).
+
+ DVDD-supply:
+ description: Power for digital core (1.7 - 1.9V).
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description: |
+ Video output port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ anyOf:
+ - items:
+ - const: 1
+ - const: 2
+ - items:
+ - const: 1
+ - const: 2
+
+ required:
+ - data-lanes
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - powerdown-gpios
+ - reset-gpios
+ - IOVDD-supply
+ - AVDD-supply
+ - DVDD-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gc2145@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ IOVDD-supply = <&scmi_v3v3_sw>;
+ AVDD-supply = <&scmi_v3v3_sw>;
+ DVDD-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
new file mode 100644
index 000000000000..70631046017d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32-dcmipp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor binding
+
+maintainers:
+ - Hugues Fruchet <hugues.fruchet@foss.st.com>
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+properties:
+ compatible:
+ const: st,stm32mp13-dcmipp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: kclk
+
+ resets:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ DCMIPP supports a single port node with parallel bus.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+ default: 5
+
+ bus-width:
+ enum: [8, 10, 12, 14]
+ default: 8
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+ required:
+ - pclk-sample
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp13-clks.h>
+ #include <dt-bindings/reset/stm32mp13-resets.h>
+ dcmipp: dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+ clock-names = "kclk";
+
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ pclk-max-frequency = <120000000>;
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 8bcea8dd7d90..6e518ae12e7f 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,9 @@ properties:
wakeup-source: true
+ power-domains:
+ maxItems: 1
+
pwm:
type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
new file mode 100644
index 000000000000..b5f414a19120
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/st,stm32mp1-pwr.txt
@@ -0,0 +1,57 @@
+STMicroelectronics STM32MP1 Power Management Controller
+=======================================================
+
+The PWR IP is responsible for handling the power related resources such as
+clocks, power supplies and resets. It provides 6 wake-up pins that are handled
+by an interrupt-controller. Wake-up pin can be used to wake-up from STANDBY SoC state.
+
+Required properties:
+- compatible should be: "st,stm32mp1-pwr"
+- reg: should be register base and length as documented in the
+ datasheet
+- interrupts: contains the reference to the gic wake-up pin interrupt
+- interrupt-controller; Enable interrupt controller for wake-up pins.
+- #interrupt-cells = <3>
+- st,wakeup-pins: contains a list of GPIO spec describing each wake-up pin.
+
+Optional Properties:
+- pwr-supply: main soc power supply
+
+Interrupt consumers have to specify 3 cells:
+ - cell 1: wake-up pin id from 0 to 5
+ - cell 2: IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_RISING
+ - cell 3: Pull config: 0 = No Pull, 1=Pull Up, 2=Pull Down
+
+
+Example:
+
+ pwr: pwr@50001000 {
+ compatible = "st,stm32mp1-pwr", "simple-mfd";
+ reg = <0x50001000 0x400>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ st,wakeup-pins = <&gpioa 0 0>, <&gpioa 2 0>,
+ <&gpioc 13 0>, <&gpioi 8 0>,
+ <&gpioi 11 0>, <&gpioc 1 0>;
+
+ pwr-supply = <&vdd>;
+ };
+
+
+Example of interrupt user:
+gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@4 {
+ label = "WakeUp4";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&pwr>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING 1>;
+ wakeup-source;
+ };
+};
+
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 47595cb483be..eed54bee7665 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -53,6 +53,12 @@ properties:
items:
- const: arm,pl18x
- const: arm,primecell
+ - description: Entry for STMicroelectronics variant of PL18x.
+ This dedicated compatible is used by bootloaders.
+ items:
+ - const: st,stm32-sdmmc2
+ - const: arm,pl18x
+ - const: arm,primecell
clocks:
description: One or two clocks, the "apb_pclk" and the "MCLK"
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index 5cd144a9ec99..29c9e5b0bbe7 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -154,6 +154,13 @@ patternProperties:
Ready/Busy pins. Active state refers to the NAND ready state and
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
+ wp-gpios:
+ description:
+ Contains one GPIO descriptor for the Write Protect pin.
+ Active state refers to the NAND Write Protect state and should be
+ set to GPIOD_ACTIVE_LOW unless the signal is inverted.
+ maxItems: 1
+
secure-regions:
$ref: /schemas/types.yaml#/definitions/uint64-matrix
description:
diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml
index 0b80ce22a2f8..f13868d4344b 100644
--- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml
+++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml
@@ -22,8 +22,16 @@ properties:
compatible:
enum:
- st,stm32f4-otp
+ - st,stm32mp13-bsec
- st,stm32mp15-bsec
+ clocks:
+ maxItems: 1
+ description: |
+ - It's not present on stm32f4.
+ - It's not present on stm32mp13.
+ - It's optional on stm32mp15.
+
patternProperties:
"^.*@[0-9a-f]+$":
type: object
diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
new file mode 100644
index 000000000000..085f2886e580
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/stm32-ddr-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+ - Gerald Baeza <gerald.baeza@st.com>
+
+title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) bindings
+
+properties:
+ compatible:
+ const: st,stm32-ddr-pmu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 3329f1d33a4f..750ce7074648 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -74,6 +74,10 @@ patternProperties:
"#phy-cells":
enum: [ 0x0, 0x1 ]
+ interrupts:
+ maxItems: 1
+ description: interrupt used for wakeup when port is used by USBH controller
+
connector:
type: object
allOf:
@@ -81,6 +85,119 @@ patternProperties:
properties:
vbus-supply: true
+ # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due
+ # to USB connector/receptacle, routing, ESD protection component,... Here is the list of
+ # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full-
+ # Speed, LS for Low-Speed)
+
+ st,current-boost-microamp:
+ description: Current boosting in uA
+ enum: [ 1000, 2000 ]
+
+ st,no-lsfs-fb-cap:
+ description: Disables the LS/FS feedback capacitor
+ type: boolean
+
+ st,decrease-hs-slew-rate:
+ description: Decreases the HS driver slew rate by 10%
+ type: boolean
+
+ st,tune-hs-dc-level:
+ description: |
+ Tunes the HS driver DC level
+ - <0> normal level
+ - <1> increases the level by 5 to 7 mV
+ - <2> increases the level by 10 to 14 mV
+ - <3> decreases the level by 5 to 7 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,enable-fs-rftime-tuning:
+ description: Enables the FS rise/fall tuning option
+ type: boolean
+
+ st,enable-hs-rftime-reduction:
+ description: Enables the HS rise/fall reduction feature
+ type: boolean
+
+ st,trim-hs-current:
+ description: |
+ Controls HS driver current trimming for choke compensation
+ - <0> = 18.87 mA target current / nominal + 0%
+ - <1> = 19.165 mA target current / nominal + 1.56%
+ - <2> = 19.46 mA target current / nominal + 3.12%
+ - <3> = 19.755 mA target current / nominal + 4.68%
+ - <4> = 20.05 mA target current / nominal + 6.24%
+ - <5> = 20.345 mA target current / nominal + 7.8%
+ - <6> = 20.64 mA target current / nominal + 9.36%
+ - <7> = 20.935 mA target current / nominal + 10.92%
+ - <8> = 21.23 mA target current / nominal + 12.48%
+ - <9> = 21.525 mA target current / nominal + 14.04%
+ - <10> = 21.82 mA target current / nominal + 15.6%
+ - <11> = 22.115 mA target current / nominal + 17.16%
+ - <12> = 22.458 mA target current / nominal + 19.01%
+ - <13> = 22.755 mA target current / nominal + 20.58%
+ - <14> = 23.052 mA target current / nominal + 22.16%
+ - <15> = 23.348 mA target current / nominal + 23.73%
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ default: 0
+
+ st,trim-hs-impedance:
+ description: |
+ Controls HS driver impedance tuning for choke compensation
+ - <0> = no impedance offset
+ - <1> = reduce the impedance by 2 ohms
+ - <2> = reduce the impedance by 4 ohms
+ - <3> = reduce the impedance by 6 ohms
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,tune-squelch-level:
+ description: |
+ Tunes the squelch DC threshold value
+ - <0> = no shift in threshold
+ - <1> = threshold shift by +7 mV
+ - <2> = threshold shift by -5 mV
+ - <3> = threshold shift by +14 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,enable-hs-rx-gain-eq:
+ description: Enables the HS Rx gain equalizer
+ type: boolean
+
+ st,tune-hs-rx-offset:
+ description: |
+ Adjusts the HS Rx offset
+ - <0> = no offset
+ - <1> = offset of +5 mV
+ - <2> = offset of +10 mV
+ - <3> = offset of -5 mV
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,no-hs-ftime-ctrl:
+ description: Disables the HS fall time control of single ended signals during pre-emphasis
+ type: boolean
+
+ st,no-lsfs-sc:
+ description: Disables the short circuit protection in LS/FS driver
+ type: boolean
+
+ st,enable-hs-tx-staggering:
+ description: Enables the basic staggering in HS Tx mode
+ type: boolean
+
allOf:
- if:
properties:
@@ -137,6 +254,14 @@ examples:
reg = <0>;
phy-supply = <&vdd_usb>;
#phy-cells = <0>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>;
@@ -147,6 +272,14 @@ examples:
reg = <1>;
phy-supply = <&vdd_usb>;
#phy-cells = <1>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
};
...
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index dfee6d38a701..7348f40d49b5 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -140,9 +140,13 @@ patternProperties:
* ...
* 16 : Alternate Function 15
* 17 : Analog
+ * 18 : Reserved
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
+ Setting the pinmux's function to the Reserved (RSVD) value is used to inform
+ the driver that it shall not apply the mux setting. This can be used to
+ reserve some pins, for example to a co-processor not running Linux.
Some examples of using macro:
/* GPIO A9 set as alernate function 2 */
... {
@@ -156,6 +160,10 @@ patternProperties:
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
+ /* GPIO A9 reserved for co-processor */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, RSVD)>;
+ };
bias-disable:
type: boolean
diff --git a/Documentation/devicetree/bindings/regulator/protection-consumer.txt b/Documentation/devicetree/bindings/regulator/protection-consumer.txt
new file mode 100644
index 000000000000..bf8169e008c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/protection-consumer.txt
@@ -0,0 +1,23 @@
+regulator protection bindings
+
+
+Required properties:
+ compatible: "protection-consumer"
+ protection-supply: the phandle of the regulator to control
+
+Optional properties:
+--------------------
+ interrupt
+
+
+Example:
+
+ regulator_protection {
+ compatible = "protection-consumer";
+ protection-supply = <&vdd>;
+ status = "okay";
+
+ interrupts = <15 2>;
+ interrupt-parent = <&gpiof>;
+ };
+
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index 3cd4a254e4cb..fe9c5e83c459 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -19,7 +19,9 @@ allOf:
properties:
compatible:
- const: st,stm32-vrefbuf
+ enum:
+ - st,stm32-vrefbuf
+ - st,stm32mp13-vrefbuf
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
new file mode 100644
index 000000000000..baa6e8e135e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/rproc-srm.txt
@@ -0,0 +1,58 @@
+Remoteproc System Resource Manager
+----------------------------------
+
+The remoteproc SRM (System Resource Manager) handles resources allocated
+to remote processors.
+This makes it possible for remote proc to reserve and initialize system
+resources for a peripheral assigned to a coprocessor.
+
+The devices are grouped in a core node
+
+Core
+====
+Required properties:
+- compatible: should be "rproc-srm-core"
+
+Dev
+===
+Required properties:
+- compatible: should be "rproc-srm-dev"
+
+Optional properties:
+- reg: register base address and length
+- clocks: clocks required by the coprocessor
+- clock-names: see clock-bindings.txt
+- pinctrl-0: pins configurations required by the coprocessor
+ The SRM reserves the pins for the coprocessor, which prevents the local
+ processor to use them.
+- pinctrl-names: must be "default".
+- x-supply: power supplies required by the coprocessor
+- interrupts: external interrupts configurations required by the coprocessor.
+ This is optional since the configuration is done by the coprocessor.
+ When defined, the SRM (over)writes the configuration which allows the
+ interrupt controller to check for configuration conflicts.
+- interrupt-parent: see interrupts.txt
+- interrupt-names: see interrupts.txt
+
+Example:
+ system_resources {
+ compatible = "rproc-srm-core";
+
+ mmc0: sdhci@09060000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x09060000 0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pinctrl_mmc0>;
+ clock-names = "mmc", "icn";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
+ vdda-supply = <&vdda>;
+ };
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <5 1>;
+ interrupt-names = "gpio_key";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
index 1e6225677e00..93c27e3ecd85 100644
--- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
@@ -25,21 +25,12 @@ properties:
maxItems: 3
resets:
- maxItems: 1
-
- st,syscfg-holdboot:
- description: remote processor reset hold boot
- - Phandle of syscon block.
- - The offset of the hold boot setting register.
- - The field mask of the hold boot.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ maxItems: 2
- st,syscfg-tz:
- description:
- Reference to the system configuration which holds the RCC trust zone mode
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
- maxItems: 1
+ reset-names:
+ items:
+ - const: mcu_rst
+ - const: hold_boot
interrupts:
description: Should contain the WWDG1 watchdog reset interrupt
@@ -119,7 +110,6 @@ required:
- reg
- resets
- st,syscfg-holdboot
- - st,syscfg-tz
additionalProperties: false
@@ -131,9 +121,10 @@ examples:
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
};
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 82bb2e97e889..17dd4d826d21 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -15,7 +15,9 @@ maintainers:
properties:
compatible:
- const: st,stm32-rng
+ oneOf:
+ - const: st,stm32-rng
+ - const: st,stm32mp13-rng
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
index 5456604b1c14..d94e1d13d908 100644
--- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
@@ -52,6 +52,20 @@ properties:
override default rtc_ck parent clock phandle of the new parent clock of rtc_ck
maxItems: 1
+ st,lsco:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ To select and enable RTC Low Speed Clock Output.
+ Refer to <include/dt-bindings/rtc/rtc-stm32.h> for the supported values.
+ Pinctrl state named "default" may be defined to reserve pin for RTC output.
+
+ st,alarm:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ To select and enable RTC Alarm A output.
+ Refer to <include/dt-bindings/rtc/rtc-stm32.h> for the supported values.
+ Pinctrl state named "default" may be defined to reserve pin for RTC output.
+
allOf:
- if:
properties:
@@ -65,6 +79,12 @@ allOf:
minItems: 1
maxItems: 1
+ st,lsco:
+ maxItems: 0
+
+ st,alarm:
+ maxItems: 0
+
clock-names: false
required:
@@ -82,6 +102,12 @@ allOf:
minItems: 2
maxItems: 2
+ st,lsco:
+ maxItems: 0
+
+ st,alarm:
+ maxItems: 0
+
required:
- clock-names
- st,syscfg
@@ -101,6 +127,12 @@ allOf:
assigned-clocks: false
assigned-clock-parents: false
+ st,lsco:
+ maxItems: 1
+
+ st,alarm:
+ maxItems: 1
+
required:
- clock-names
@@ -129,12 +161,17 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/rtc/rtc-stm32.h>
rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
clocks = <&rcc RTCAPB>, <&rcc RTC>;
clock-names = "pclk", "rtc_ck";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ st,alarm = <RTC_OUT1>;
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out1_pins_a &rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
};
...
diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml
index 0c9fa694f85c..603d74cf2031 100644
--- a/Documentation/devicetree/bindings/serial/rs485.yaml
+++ b/Documentation/devicetree/bindings/serial/rs485.yaml
@@ -29,6 +29,20 @@ properties:
default: 0
maximum: 1000
+ rs485-rts-delay-ns:
+ description: prop-encoded-array <a b>
+ items:
+ items:
+ - description: Delay between rts signal and beginning of data sent in
+ nanoseconds. It corresponds to the delay before sending data.
+ default: 0
+ maximum: 1000
+ - description: Delay between end of data sent and rts signal in nanoseconds.
+ It corresponds to the delay after sending data and actual release
+ of the line.
+ default: 0
+ maximum: 1000
+
rs485-rts-active-low:
description: drive RTS low when sending (default is high).
$ref: /schemas/types.yaml#/definitions/flag
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index f50f4ca893a0..93ca9aa8f26e 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -61,10 +61,15 @@ properties:
wakeup-source: true
rs485-rts-delay: true
+ rs485-rts-delay-ns: true
rs485-rts-active-low: true
linux,rs485-enabled-at-boot-time: true
rs485-rx-during-tx: true
+ power-domains:
+ $ref: ../power/power-domain.yaml
+ maxItems: 1
+
rx-threshold:
description:
If value is set to 1, RX FIFO threshold is disabled.
diff --git a/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml b/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
new file mode 100644
index 000000000000..a228a5b262d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/stm32/st,stm32mp1-hslv.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/st,stm32mp1-hslv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32MP1 HSLV IO Speed config assistant
+
+maintainers:
+ - Pascal Paillet <p.paillet@st.com>
+
+description: |
+ Some of the STMicroelectronics's STM32 MP13 IOs can be set to high speed mode
+ if their supply is lower than a 2.7V. The goal of this driver is to
+ automatically set the IOs to high speed mode depending on their supply's
+ regulator voltage value.
+
+properties:
+ compatible:
+ const: st,stm32mp13,hslv
+
+ hslv-supply:
+ description: Input supply phandle(s) for hslv input
+
+ st,syscon:
+ description: hslv sysconf register offset and mask
+
+required:
+ - compatible
+ - hslv-supply
+ - st,syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ hslv@1 {
+ compatible = "st,stm32mp13,hslv";
+
+ /* sdmmc1 hslv = 0x50 + 4 * 4 = 0x60 */
+ st,syscon = <&syscfg 0x60 0x1018>;
+ hslv-supply = <&sdmmc1_regu>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
new file mode 100644
index 000000000000..e2bd82f4980e
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/stm32/stm32_hdp.txt
@@ -0,0 +1,39 @@
+STM32 - STM32MP1- HDP Pin configuration for STM32MP1
+=======================================================
+
+The Hardware Debug Port (HDP) allows the observation of internal signals. By using multiplexers,
+up to 16 signals for each of 8-bit output can be observed.
+
+Required Properties:
+
+ - compatible: Must be "st,stm32mp1-hdp"
+ - muxing-hdp: Indicates for each HDP pins selected which HDP output among the 16 available signals you want
+
+For each HDP pins you can select one of 16 signals which will be described in file : include/dt-bindings/soc/stm32-hdp.h
+
+Example
+-------
+
+In common dtsi file:
+
+hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+};
+
+In board-specific file:
+
+In this example I've selected HDP0, HDP6 and HDP7, and for HDP0 the output signal is HDP0_GPOVAL_0,
+for HDP6 is HDP6_GPOVAL_6, and for HDP7 is HDP7_GPOVAL_7.
+
+&hdp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
+
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
+ STM32_HDP(6, HDP6_GPOVAL_6) |
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
+};
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 983c4e54c0be..a21246712f3f 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,14 @@ properties:
- const: tx
- const: rx
+ st,dual-flash:
+ type: boolean
+ description:
+ Allows to use 8 data lines in case cs-gpios property is defined.
+
+dependencies:
+ st,dual-flash: [ cs-gpios ]
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 2d9af4c506bb..8962b2b4de9d 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -27,8 +27,13 @@ allOf:
then:
properties:
st,spi-midi-ns: false
+ spi-slave: false
+ st,spi-slave-underrun: false
properties:
+ "#address-cells": true
+ "#size-cells": true
+
compatible:
enum:
- st,stm32f4-spi
@@ -59,6 +64,24 @@ properties:
- const: rx
- const: tx
+ spi-slave:
+ description:
+ The SPI controller acts as a slave, instead of a master.
+
+ cs-gpios:
+ description:
+ In case of spi-slave not defined, cs-gpios behave as defined in
+ spi-controller.yaml.
+ In case of spi-slave defined, if <0>, indicate that SS should be
+ detected via the dedicated HW pin
+
+ st,spi-slave-underrun:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ First parameter enables and selects slave underrun reaction.
+ Refer to "dt-bindings/spi/spi-stm32.h" for the supported values.
+ Second parameter is the pattern in case of SPI_SEND_PATTERN mode.
+
patternProperties:
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 10c7d9b6cc53..a035cf6e2c0a 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -9,6 +9,9 @@ title: DesignWare HS OTG USB 2.0 controller Bindings
maintainers:
- Rob Herring <robh@kernel.org>
+allOf:
+ - $ref: usb-drd.yaml#
+
properties:
compatible:
oneOf:
@@ -58,11 +61,14 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clock-names:
items:
- const: otg
+ - const: utmi
+ minItems: 1
resets:
items:
@@ -101,12 +107,17 @@ properties:
description: reference to the VBUS and ID sensing comparators supply, in
order to perform OTG operation, used on STM32MP15 SoCs.
- dr_mode:
- enum: [host, peripheral, otg]
+ dr_mode: true
- usb-role-switch:
- $ref: /schemas/types.yaml#/definitions/flag
- description: Support role switch.
+ otg-rev: true
+
+ hnp-disable: true
+
+ srp-disable: true
+
+ usb-role-switch: true
+
+ role-switch-default-mode: true
g-rx-fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -130,6 +141,21 @@ properties:
description: If present indicates that we need to reset the PHY when we
detect a wakeup. This is due to a hardware errata.
+ port:
+ description:
+ Any connector to the data bus of this controller should be modelled
+ using the OF graph bindings specified, if the "usb-role-switch"
+ property is used.
+ $ref: /schemas/graph.yaml#/properties/port
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If present indicates this device has wakeup capabilities
+
+dependencies:
+ port: [ usb-role-switch ]
+ role-switch-default-mode: [ usb-role-switch ]
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index cb5da1df8d40..0b12acf804ec 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -149,6 +149,11 @@ properties:
- host
- otg
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate this device has wakeup capabilities.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index d5fd3aa53ed2..ef237675a83a 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -116,6 +116,11 @@ properties:
- host
- otg
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate this device has wakeup capabilities.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml b/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
new file mode 100644
index 000000000000..b2729bd015a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st,typec-stm32g0.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/st,typec-stm32g0.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: STMicroelectronics STM32G0 Type-C controller bindings
+
+description: |
+ The STM32G0 MCU can be programmed to control Type-C connector(s) through I2C
+ typically using the UCSI protocol over I2C, with a dedicated alert
+ (interrupt) pin.
+
+maintainers:
+ - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+properties:
+ compatible:
+ const: st,stm32g0-typec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ connector:
+ type: object
+ allOf:
+ - $ref: ../connector/usb-connector.yaml#
+
+ firmware-name:
+ description: |
+ Should contain the name of the default firmware image
+ file located on the firmware search path
+
+ wakeup-source: true
+ power-domains: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ stm32g0@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on GPIO PE12 */
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioe>;
+
+ /* Example with one type-C connector */
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+ };
+
+ usbotg_hs {
+ usb-role-switch;
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_ep>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index a867f7102c35..864e10fbf90b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -427,6 +427,8 @@ patternProperties:
description: Freescale Semiconductor
"^fujitsu,.*":
description: Fujitsu Ltd.
+ "^galaxycore,.*":
+ description: Galaxy Core Inc.
"^gardena,.*":
description: GARDENA GmbH
"^gateworks,.*":
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7a72fc636a7a..1f07bf84c45d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,4 +1,42 @@
# SPDX-License-Identifier: GPL-2.0
+
+# board-specific dtc flags
+DTC_FLAGS_stm32mp157c-dk2 += -@
+DTC_FLAGS_stm32f429-disco += -@
+DTC_FLAGS_stm32f469-disco += -@
+DTC_FLAGS_stm32f746-disco += -@
+DTC_FLAGS_stm32f769-disco += -@
+DTC_FLAGS_stm32429i-eval += -@
+DTC_FLAGS_stm32746g-eval += -@
+DTC_FLAGS_stm32h743i-eval += -@
+DTC_FLAGS_stm32h743i-disco += -@
+DTC_FLAGS_stm32mp135f-dk += -@
+DTC_FLAGS_stm32mp135f-dk-a7-examples +=-@
+DTC_FLAGS_stm32mp157a-dk1 += -@
+DTC_FLAGS_stm32mp157a-dk1-a7-examples += -@
+DTC_FLAGS_stm32mp157a-dk1-m4-examples += -@
+DTC_FLAGS_stm32mp157d-dk1 += -@
+DTC_FLAGS_stm32mp157d-dk1-a7-examples += -@
+DTC_FLAGS_stm32mp157d-dk1-m4-examples += -@
+DTC_FLAGS_stm32mp157c-dk2 += -@
+DTC_FLAGS_stm32mp157f-dk2 += -@
+DTC_FLAGS_stm32mp157c-dk2-a7-examples += -@
+DTC_FLAGS_stm32mp157c-dk2-m4-examples += -@
+DTC_FLAGS_stm32mp157f-dk2-a7-examples += -@
+DTC_FLAGS_stm32mp157f-dk2-m4-examples += -@
+DTC_FLAGS_stm32mp157a-ed1 += -@
+DTC_FLAGS_stm32mp157c-ed1 += -@
+DTC_FLAGS_stm32mp157d-ed1 += -@
+DTC_FLAGS_stm32mp157f-ed1 += -@
+DTC_FLAGS_stm32mp157a-ev1 += -@
+DTC_FLAGS_stm32mp157c-ev1 += -@
+DTC_FLAGS_stm32mp157d-ev1 += -@
+DTC_FLAGS_stm32mp157f-ev1 += -@
+DTC_FLAGS_stm32mp157c-ev1-a7-examples += -@
+DTC_FLAGS_stm32mp157c-ev1-m4-examples += -@
+DTC_FLAGS_stm32mp157f-ev1-a7-examples += -@
+DTC_FLAGS_stm32mp157f-ev1-m4-examples += -@
+
dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
dtb-$(CONFIG_MACH_ARTPEC6) += \
@@ -1115,10 +1153,17 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb \
+ stm32mp135f-dk.dtb \
+ stm32mp135f-dk-a7-examples.dtb \
stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
+ stm32mp157a-dk1-a7-examples.dtb \
+ stm32mp157a-dk1-m4-examples.dtb \
+ stm32mp157d-dk1.dtb \
+ stm32mp157d-dk1-a7-examples.dtb \
+ stm32mp157d-dk1-m4-examples.dtb \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
@@ -1128,8 +1173,23 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
stm32mp157c-dk2.dtb \
+ stm32mp157c-dk2-a7-examples.dtb \
+ stm32mp157c-dk2-m4-examples.dtb \
+ stm32mp157f-dk2.dtb \
+ stm32mp157f-dk2-a7-examples.dtb \
+ stm32mp157f-dk2-m4-examples.dtb \
+ stm32mp157a-ed1.dtb \
stm32mp157c-ed1.dtb \
+ stm32mp157d-ed1.dtb \
+ stm32mp157f-ed1.dtb \
+ stm32mp157a-ev1.dtb \
stm32mp157c-ev1.dtb \
+ stm32mp157c-ev1-a7-examples.dtb \
+ stm32mp157c-ev1-m4-examples.dtb \
+ stm32mp157d-ev1.dtb \
+ stm32mp157f-ev1.dtb \
+ stm32mp157f-ev1-a7-examples.dtb \
+ stm32mp157f-ev1-m4-examples.dtb \
stm32mp157c-lxa-mc1.dtb \
stm32mp157c-odyssey.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
new file mode 100644
index 000000000000..b8d53065ae6a
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
@@ -0,0 +1,644 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
+ dcmipp_pins_a: dcmi-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmipp_sleep_pins_a: dcmi-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_CKOUT */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ dfsdm_datin1_pins_a: dfsdm-datin1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, AF6)>; /* DFSDM_DATIN1 */
+ };
+ };
+
+ dfsdm_datin1_sleep_pins_a: dfsdm-datin1-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* DFSDM_DATIN1 */
+ };
+ };
+
+ dfsdm_datin3_pins_a: dfsdm-datin3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATIN3 */
+ };
+ };
+
+ dfsdm_datin3_sleep_pins_a: dfsdm-datin3-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATIN3 */
+ };
+ };
+
+ eth1_rmii_pins_a: eth1-rmii-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ eth2_rmii_pins_a: eth2-rmii-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ goodix_pins_a: goodix-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, GPIO)>;
+ bias-pull-down;
+ };
+ };
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_a: i2c1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c5_pins_a: i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_a: i2c5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
+ <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
+ <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
+ <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
+ <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
+ <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
+ <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ mcp23017_pins_a: mcp23017-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 1, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 3, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 1, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('G', 3, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
+ };
+ };
+
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
+ };
+ };
+
+ pwm14_pins_a: pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm14_sleep_pins_a: pwm12-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
+ };
+ };
+
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
+ };
+ };
+
+ sai1_pins_a: sai1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
+ <STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1_sleep_pins_a: sai1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
+ <STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
+ <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ spi5_sleep_pins_a: spi5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
+ <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
+ <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
+ };
+ };
+
+ stm32g0_intn_pins_a: stm32g0-intn-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_idle_pins_a: uart8-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_sleep_pins_a: uart8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
+ };
+ };
+
+ usart1_pins_a: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
+ <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_a: usart1-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_a: usart1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
+ <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
+ };
+ };
+
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
new file mode 100644
index 000000000000..8121ddc97f10
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -0,0 +1,1742 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <dt-bindings/reset/stm32mp13-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&scmi_perf 0>;
+ clock-names = "cpu";
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ #cooling-cells = <2>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi_shm@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
+ };
+ };
+
+ firmware {
+ optee: optee {
+ method = "smc";
+ compatible = "linaro,optee-tz";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+
+ scmi_voltd: protocol@17 {
+ reg = <0x17>;
+
+ scmi_regu: regulators {
+ scmi_reg11: voltd-reg11 {
+ voltd-name = "reg11";
+ regulator-name = "reg11";
+ };
+ scmi_reg18: voltd-reg18 {
+ voltd-name = "reg18";
+ regulator-name = "reg18";
+ };
+ scmi_usb33: voltd-usb33 {
+ voltd-name = "usb33";
+ regulator-name = "usb33";
+ };
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ always-on;
+ };
+
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&dts>;
+
+ trips {
+ cpu_alert: cpu-alert0 {
+ temperature = <95000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit0 {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 1 1>;
+ };
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ sram: sram@30000000 {
+ compatible = "mmio-sram";
+ reg = <0x30000000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x30000000 0x8000>;
+ };
+
+ timers2: timer@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc TIM2_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 18 0x400 0x80000001>,
+ <&dmamux1 19 0x400 0x80000001>,
+ <&dmamux1 20 0x400 0x80000001>,
+ <&dmamux1 21 0x400 0x80000001>,
+ <&dmamux1 22 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers3: timer@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc TIM3_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 23 0x400 0x80000001>,
+ <&dmamux1 24 0x400 0x80000001>,
+ <&dmamux1 25 0x400 0x80000001>,
+ <&dmamux1 26 0x400 0x80000001>,
+ <&dmamux1 27 0x400 0x80000001>,
+ <&dmamux1 28 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers4: timer@40002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc TIM4_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 29 0x400 0x80000001>,
+ <&dmamux1 30 0x400 0x80000001>,
+ <&dmamux1 31 0x400 0x80000001>,
+ <&dmamux1 32 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers5: timer@40003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40003000 0x400>;
+ clocks = <&rcc TIM5_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 55 0x400 0x80000001>,
+ <&dmamux1 56 0x400 0x80000001>,
+ <&dmamux1 57 0x400 0x80000001>,
+ <&dmamux1 58 0x400 0x80000001>,
+ <&dmamux1 59 0x400 0x80000001>,
+ <&dmamux1 60 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers6: timer@40004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40004000 0x400>;
+ clocks = <&rcc TIM6_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 69 0x400 0x80000001>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@5 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timers7: timer@40005000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40005000 0x400>;
+ clocks = <&rcc TIM7_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 70 0x400 0x80000001>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@6 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ lptimer1: timer@40009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi2: spi@4000b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI2_K>;
+ resets = <&rcc SPI2_R>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s3: audio-controller@4000c000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi3: spi@4000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI3_K>;
+ resets = <&rcc SPI3_R>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdifrx: audio-controller@4000d000 {
+ compatible = "st,stm32h7-spdifrx";
+ #sound-dai-cells = <0>;
+ reg = <0x4000d000 0x400>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 93 0x400 0x01>,
+ <&dmamux1 94 0x400 0x01>;
+ dma-names = "rx", "rx-ctrl";
+ status = "disabled";
+ };
+
+ usart3: serial@4000f000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000f000 0x400>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART3_K>;
+ resets = <&rcc USART3_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 45 0x400 0x5>,
+ <&dmamux1 46 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART4_K>;
+ resets = <&rcc UART4_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 63 0x400 0x5>,
+ <&dmamux1 64 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@40011000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART5_K>;
+ resets = <&rcc UART5_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 65 0x400 0x5>,
+ <&dmamux1 66 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@40012000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40012000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C1_K>;
+ resets = <&rcc I2C1_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 33 0x400 0x80000001>,
+ <&dmamux1 34 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40013000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40013000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C2_K>;
+ resets = <&rcc I2C2_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 35 0x400 0x80000001>,
+ <&dmamux1 36 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ uart7: serial@40018000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40018000 0x400>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART7_K>;
+ resets = <&rcc UART7_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 79 0x400 0x5>,
+ <&dmamux1 80 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart8: serial@40019000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40019000 0x400>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART8_K>;
+ resets = <&rcc UART8_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 81 0x400 0x5>,
+ <&dmamux1 82 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ timers1: timer@44000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44000000 0x400>;
+ clocks = <&rcc TIM1_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 11 0x400 0x80000001>,
+ <&dmamux1 12 0x400 0x80000001>,
+ <&dmamux1 13 0x400 0x80000001>,
+ <&dmamux1 14 0x400 0x80000001>,
+ <&dmamux1 15 0x400 0x80000001>,
+ <&dmamux1 16 0x400 0x80000001>,
+ <&dmamux1 17 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers8: timer@44001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44001000 0x400>;
+ clocks = <&rcc TIM8_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 47 0x400 0x80000001>,
+ <&dmamux1 48 0x400 0x80000001>,
+ <&dmamux1 49 0x400 0x80000001>,
+ <&dmamux1 50 0x400 0x80000001>,
+ <&dmamux1 51 0x400 0x80000001>,
+ <&dmamux1 52 0x400 0x80000001>,
+ <&dmamux1 53 0x400 0x80000001>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ usart6: serial@44003000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x44003000 0x400>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART6_K>;
+ resets = <&rcc USART6_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 71 0x400 0x5>,
+ <&dmamux1 72 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi1: spi@44004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI1_K>;
+ resets = <&rcc SPI1_R>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai1: sai@4400a000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400a000 0x400>;
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+ #sound-dai-cells = <0>;
+
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai1b: audio-controller@4400a024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400b000 0x400>;
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai2b: audio-controller@4400b024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ dfsdm: dfsdm@4400d000 {
+ compatible = "st,stm32mp1-dfsdm";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>;
+ clock-names = "dfsdm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-adc";
+ #io-channel-cells = <1>;
+ reg = <0>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 101 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ dfsdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-adc";
+ #io-channel-cells = <1>;
+ reg = <1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 102 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
+ dma1: dma-controller@48000000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48000000 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ dmas = <&mdma 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
+ <&mdma 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
+ <&mdma 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
+ <&mdma 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
+ <&mdma 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
+ <&mdma 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
+ <&mdma 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
+ <&mdma 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ };
+
+ dma2: dma-controller@48001000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48001000 0x400>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ dmas = <&mdma 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
+ <&mdma 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
+ <&mdma 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
+ <&mdma 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
+ <&mdma 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
+ <&mdma 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
+ <&mdma 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
+ <&mdma 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ };
+
+ dmamux1: dma-router@48002000 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x48002000 0x40>;
+ clocks = <&rcc DMAMUX1>;
+ resets = <&rcc DMAMUX1_R>;
+ #dma-cells = <3>;
+ dma-masters = <&dma1 &dma2>;
+ dma-requests = <128>;
+ dma-channels = <16>;
+ };
+
+ adc_2: adc@48004000 {
+ reg = <0x48004000 0x400>;
+ compatible = "st,stm32mp13-adc-core";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc2: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_2>;
+ interrupts = <0>;
+ dmas = <&dmamux1 10 0x400 0x80000001>;
+ dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
+ status = "disabled";
+
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ };
+ channel@16 {
+ reg = <16>;
+ label = "vddcpu";
+ };
+ channel@17 {
+ reg = <17>;
+ label = "vddq_ddr";
+ };
+ };
+ };
+
+ usbotg_hs: usb-otg@49000000 {
+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+ reg = <0x49000000 0x40000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+ dr_mode = "otg";
+ otg-rev = <0x200>;
+ usb33d-supply = <&scmi_usb33>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ usart1: serial@4c000000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c000000 0x400>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART1_K>;
+ resets = <&rcc USART1_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 41 0x400 0x5>,
+ <&dmamux1 42 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ usart2: serial@4c001000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c001000 0x400>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
+ wakeup-source;
+ power-domains = <&pd_core_ret>;
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s4: audio-controller@4c002000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4c002000 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi4: spi@4c002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c002000 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI4_K>;
+ resets = <&rcc SPI4_R>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi5: spi@4c003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c003000 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI5_K>;
+ resets = <&rcc SPI5_R>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@4c004000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c004000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C3_K>;
+ resets = <&rcc I2C3_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 73 0x400 0x80000001>,
+ <&dmamux1 74 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4c005000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c005000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C4_K>;
+ resets = <&rcc I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 75 0x400 0x80000001>,
+ <&dmamux1 76 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ i2c5: i2c@4c006000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c006000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C5_K>;
+ resets = <&rcc I2C5_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 115 0x400 0x80000001>,
+ <&dmamux1 116 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ i2c-analog-filter;
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ timers12: timer@4c007000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c007000 0x400>;
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timer@4c008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c008000 0x400>;
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@12 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <12>;
+ status = "disabled";
+ };
+ };
+
+ timers14: timer@4c009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c009000 0x400>;
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@13 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <13>;
+ status = "disabled";
+ };
+ };
+
+ timers15: timer@4c00a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00a000 0x400>;
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 105 0x400 0x80000001>,
+ <&dmamux1 106 0x400 0x80000001>,
+ <&dmamux1 107 0x400 0x80000001>,
+ <&dmamux1 108 0x400 0x80000001>;
+ dma-names = "ch1", "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@14 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <14>;
+ status = "disabled";
+ };
+ };
+
+ timers16: timer@4c00b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00b000 0x400>;
+ clocks = <&rcc TIM16_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 109 0x400 0x80000001>,
+ <&dmamux1 110 0x400 0x80000001>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@15 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <15>;
+ status = "disabled";
+ };
+ };
+
+ timers17: timer@4c00c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00c000 0x400>;
+ clocks = <&rcc TIM17_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 111 0x400 0x80000001>,
+ <&dmamux1 112 0x400 0x80000001>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@16 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <16>;
+ status = "disabled";
+ };
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+ };
+
+ exti: interrupt-controller@5000d000 {
+ compatible = "st,stm32mp1-exti", "syscon";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ reg = <0x5000d000 0x400>;
+
+ exti-interrupt-map {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-map-mask = <0xffffffff 0>;
+ interrupt-map =
+ <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <12 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <13 0 &intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <14 0 &intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <15 0 &intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <21 0 &intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <22 0 &intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <23 0 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <24 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <25 0 &intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <26 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <27 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <28 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <29 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <30 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <31 0 &intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <32 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <33 0 &intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <42 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <43 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <44 0 &intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <47 0 &intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <48 0 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <50 0 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <52 0 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <53 0 &intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <68 0 &intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <70 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ clocks = <&rcc SYSCFG>;
+ };
+
+ lptimer2: timer@50021000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer3: timer@50022000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@50023000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@50024000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ power-domains = <&pd_core_ret>;
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ dts: thermal@50028000 {
+ compatible = "st,stm32-thermal";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc DTS>;
+ clock-names = "pclk";
+ #thermal-sensor-cells = <0>;
+ reg = <0x50028000 0x100>;
+ status = "disabled";
+ };
+
+ hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+ status = "disabled";
+ };
+
+ hash: hash@54003000 {
+ compatible = "st,stm32mp13-hash";
+ reg = <0x54003000 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc HASH1>;
+ resets = <&rcc HASH1_R>;
+ dmas = <&mdma 30 0x2 0x1000A02 0x0 0x0 0x0>;
+ dma-names = "in";
+ status = "disabled";
+ };
+
+ rng: rng@54004000 {
+ compatible = "st,stm32mp13-rng";
+ reg = <0x54004000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
+ status = "disabled";
+ };
+
+ mdma: dma-controller@58000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x58000000 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc MDMA>;
+ #dma-cells = <6>;
+ dma-channels = <32>;
+ dma-requests = <48>;
+ };
+
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma 24 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma 25 0x2 0x12000a0a 0x0 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
+ };
+
+ qspi: spi@58003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0 0x0>,
+ <&mdma 26 0x2 0x10100008 0x0 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@58005000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC1_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: mmc@58007000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ crc1: crc@58009000 {
+ compatible = "st,stm32f7-crc";
+ reg = <0x58009000 0x400>;
+ clocks = <&rcc CRC1>;
+ status = "disabled";
+ };
+
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH1MAC>,
+ <&rcc ETH1TX>,
+ <&rcc ETH1RX>,
+ <&rcc ETH1STP>,
+ <&rcc ETH1CK_K>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
+
+ usbh_ohci: usbh-ohci@5800c000 {
+ compatible = "generic-ohci";
+ reg = <0x5800c000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ usbh_ehci: usbh-ehci@5800d000 {
+ compatible = "generic-ehci";
+ reg = <0x5800d000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ companion = <&usbh_ohci>;
+ power-domains = <&pd_core>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ iwdg2: watchdog@5a002000 {
+ compatible = "st,stm32mp1-iwdg";
+ reg = <0x5a002000 0x400>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+ clock-names = "pclk", "lsi";
+ status = "disabled";
+ };
+
+ usbphyc: usbphyc@5a006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc USBPHY_K>;
+ resets = <&rcc USBPHY_R>;
+ vdda1v1-supply = <&scmi_reg11>;
+ vdda1v8-supply = <&scmi_reg18>;
+ status = "disabled";
+
+ usbphyc_port0: usb-phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+ interrupts-extended = <&exti 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ status = "disabled";
+ };
+
+ rtc: rtc@5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+ <&scmi_clk CK_SCMI_RTC>;
+ clock-names = "pclk", "rtc_ck";
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ bsec: efuse@5c005000 {
+ compatible = "st,stm32mp13-bsec";
+ reg = <0x5c005000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x2>;
+ };
+ vrefint: vrefin_cal@52 {
+ reg = <0x52 0x2>;
+ };
+ ts_cal1: calib@5c {
+ reg = <0x5c 0x2>;
+ };
+ ts_cal2: calib@5e {
+ reg = <0x5e 0x2>;
+ };
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
+ };
+
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+ */
+ pinctrl: pinctrl@50002000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp135-pinctrl";
+ ranges = <0 0x50002000 0x8400>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc GPIOA>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc GPIOB>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc GPIOC>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc GPIOD>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc GPIOE>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc GPIOF>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc GPIOG>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc GPIOH>;
+ st,bank-name = "GPIOH";
+ ngpios = <15>;
+ gpio-ranges = <&pinctrl 0 112 15>;
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc GPIOI>;
+ st,bank-name = "GPIOI";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 128 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
new file mode 100644
index 000000000000..b46e38913643
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp131.dtsi"
+
+/ {
+ soc {
+ adc_1: adc@48003000 {
+ compatible = "st,stm32mp13-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_1>;
+ interrupts = <0>;
+ dmas = <&dmamux1 9 0x400 0x80000001>;
+ dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
+ status = "disabled";
+
+ channel@18 {
+ reg = <18>;
+ label = "vrefint";
+ };
+ };
+ };
+
+ m_can1: can@4400e000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ m_can2: can@4400f000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH2MAC>,
+ <&rcc ETH2TX>,
+ <&rcc ETH2RX>,
+ <&rcc ETH2STP>,
+ <&rcc ETH2CK_K>;
+ st,syscon = <&syscfg 0x4 0xff000000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_2>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp135.dtsi b/arch/arm/boot/dts/stm32mp135.dtsi
new file mode 100644
index 000000000000..61052a87d57b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp135.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp133.dtsi"
+
+/ {
+ soc {
+ dcmipp: dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+ clock-names = "kclk";
+ status = "disabled";
+ };
+
+ ltdc: display-controller@5a001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x5a001000 0x400>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LTDC_PX>;
+ clock-names = "lcd";
+ resets = <&scmi_reset RST_SCMI_LTDC>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp135f-dk-a7-examples.dts b/arch/arm/boot/dts/stm32mp135f-dk-a7-examples.dts
new file mode 100644
index 000000000000..e7c39aa5bc69
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp135f-dk-a7-examples.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp135f-dk.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP135F-DK configured to run Linux A7 examples";
+ compatible = "st,stm32mp135f-dk-a7-examples", "st,stm32mp135f-dk", "st,stm32mp135";
+};
+
+&timers4 {
+ status = "okay";
+};
+
+&timers8 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts
new file mode 100644
index 000000000000..4d6bda0ee327
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp135f-dk.dts
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/rtc/rtc-stm32.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP135F-DK Discovery Board";
+ compatible = "st,stm32mp135f-dk", "st,stm32mp135";
+
+ aliases {
+ ethernet0 = &eth1;
+ ethernet1 = &eth2;
+ serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_mco1: clk-mco1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pa13 {
+ label = "User-PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee_framebuffer@dd000000 {
+ reg = <0xdd000000 0x1000000>;
+ no-map;
+ };
+
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
+ };
+
+ v3v3_ao: v3v3_ao {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_ao";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h", "panel-dpi";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ data-mapping = "bgr666";
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <&ltdc_out_rgb>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <10000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <52>;
+ hfront-porch = <10>;
+ hback-porch = <10>;
+ vsync-len = <10>;
+ vfront-porch = <10>;
+ vback-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>;
+ };
+
+ wake_up {
+ compatible = "gpio-keys";
+ status = "okay";
+
+ button {
+ label = "wake-up";
+ linux,code = <KEY_WAKEUP>;
+ interrupts-extended = <&optee 0>;
+ status = "okay";
+ };
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_usb_cc_pins_a>;
+ vdda-supply = <&scmi_vdd_adc>;
+ vref-supply = <&scmi_vdd_adc>;
+ status = "okay";
+ adc1: adc@0 {
+ status = "okay";
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&crc1 {
+ status = "okay";
+};
+
+&cryp {
+ status = "okay";
+};
+
+&dcmipp {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmipp_pins_a>;
+ pinctrl-1 = <&dcmipp_sleep_pins_a>;
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ pclk-max-frequency = <120000000>;
+ };
+ };
+};
+
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&eth1 {
+ status = "okay";
+ pinctrl-0 = <&eth1_rmii_pins_a>;
+ pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth1>;
+ nvmem-cells = <&ethernet_mac1_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0_eth1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ wakeup-source;
+ };
+ };
+};
+
+&eth2 {
+ status = "okay";
+ pinctrl-0 = <&eth2_rmii_pins_a>;
+ pinctrl-1 = <&eth2_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0_eth2>;
+ st,ext-phyclk;
+ phy-supply = <&scmi_v3v3_sw>;
+ nvmem-cells = <&ethernet_mac2_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0_eth2: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>;
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <1000000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ mcp23017: pinctrl@21 {
+ compatible = "microchip,mcp23017";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp23017_pins_a>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ microchip,irq-mirror;
+ };
+
+ stm32g0@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on PI2 (PWR wakeup pin), managed by optee */
+ interrupts-extended = <&optee 1>;
+ firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
+ wakeup-source;
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_g0_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <170>;
+ i2c-scl-falling-time-ns = <5>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ gc2145: gc2145@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ IOVDD-supply = <&scmi_v3v3_sw>;
+ AVDD-supply = <&scmi_v3v3_sw>;
+ DVDD-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ status = "okay";
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ goodix: goodix_ts@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&goodix_pins_a>;
+ interrupt-parent = <&gpiof>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
+ AVDD28-supply = <&scmi_v3v3_sw>;
+ VDDIO-supply = <&scmi_v3v3_sw>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <272>;
+ status = "okay";
+ };
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&scmi_v3v3_sw>;
+ status = "disabled";
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ ov5640_0: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ stmipi: stmipi@14 {
+ compatible = "st,st-mipid02";
+ reg = <0x14>;
+ status = "okay";
+ clocks = <&clk_mco1>;
+ clock-names = "xclk";
+ VDDE-supply = <&scmi_v1v8_periph>;
+ VDDIN-supply = <&scmi_v1v8_periph>;
+ reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ mipid02_0: endpoint {
+ data-lanes = <1 2>;
+ lane-polarities = <0 0 0>;
+ remote-endpoint = <&gc2145_ep>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+
+ mipid02_2: endpoint {
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ remote-endpoint = <&dcmipp_0>;
+ };
+ };
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&ltdc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_out_rgb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scmi_regu {
+ scmi_vddcpu: voltd-vddcpu {
+ voltd-name = "vddcpu";
+ regulator-name = "vddcpu";
+ };
+ scmi_vdd: voltd-vdd {
+ voltd-name = "vdd";
+ regulator-name = "vdd";
+ };
+ scmi_vddcore: voltd-vddcore {
+ voltd-name = "vddcore";
+ regulator-name = "vddcore";
+ };
+ scmi_vdd_adc: voltd-vdd_adc {
+ voltd-name = "vdd_adc";
+ regulator-name = "vdd_adc";
+ };
+ scmi_vdd_usb: voltd-vdd_usb {
+ voltd-name = "vdd_usb";
+ regulator-name = "vdd_usb";
+ };
+ scmi_vdd_sd: voltd-vdd_sd {
+ voltd-name = "vdd_sd";
+ regulator-name = "vdd_sd";
+ };
+ scmi_v1v8_periph: voltd-v1v8_periph {
+ voltd-name = "v1v8_periph";
+ regulator-name = "v1v8_periph";
+ };
+ scmi_v3v3_sw: voltd-v3v3_sw {
+ voltd-name = "v3v3_sw";
+ regulator-name = "v3v3_sw";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&scmi_vdd_sd>;
+ status = "okay";
+};
+
+/* Wifi */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3_ao>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpiof>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; /* WL_HOST_WAKE */
+ interrupt-names = "host-wake";
+ };
+};
+
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&sram {
+ dma_pool: dma-sram@0 {
+ reg = <0x0 0x4000>;
+ pool;
+ };
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers14 {
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm14_pins_a>;
+ pinctrl-1 = <&pwm14_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@13 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart8_pins_a>;
+ pinctrl-1 = <&uart8_sleep_pins_a>;
+ pinctrl-2 = <&uart8_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&usart1 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-1 = <&usart1_sleep_pins_a>;
+ pinctrl-2 = <&usart1_idle_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ pinctrl-2 = <&usart2_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3_ao>;
+ vddio-supply = <&v3v3_ao>;
+ };
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ status = "okay";
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_g0_ep>;
+ };
+ };
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active if wakeup source is enabled
+ * otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&scmi_v3v3_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&scmi_vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+};
diff --git a/arch/arm/boot/dts/stm32mp13xa.dtsi b/arch/arm/boot/dts/stm32mp13xa.dtsi
new file mode 100644
index 000000000000..20e52cd27154
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xa.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
new file mode 100644
index 000000000000..fc4ba53fecaa
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>,
+ <&mdma 29 0x3 0x400808 0x0 0x0 0x0>;
+ dma-names = "in", "out";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp13xd.dtsi b/arch/arm/boot/dts/stm32mp13xd.dtsi
new file mode 100644
index 000000000000..aa8e235686a7
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xd.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
new file mode 100644
index 000000000000..fc4ba53fecaa
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>,
+ <&mdma 29 0x3 0x400808 0x0 0x0 0x0>;
+ dma-names = "in", "out";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi
new file mode 100644
index 000000000000..bfa78e50b3bc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-m4-srm-pinctrl.dtsi
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ m4_adc1_in6_pins_a: m4-adc1-in6 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, RSVD)>;
+ };
+ };
+
+ m4_adc12_ain_pins_a: m4-adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
+ };
+ };
+
+ m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
+ <STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
+ };
+ };
+
+ m4_cec_pins_a: m4-cec-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>;
+ };
+ };
+
+ m4_cec_pins_b: m4-cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, RSVD)>;
+ };
+ };
+
+ m4_dac_ch1_pins_a: m4-dac-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, RSVD)>;
+ };
+ };
+
+ m4_dac_ch2_pins_a: m4-dac-ch2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, RSVD)>;
+ };
+ };
+
+ m4_dcmi_pins_a: m4-dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
+ };
+ };
+
+ m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ m4_ethernet0_rgmii_pins_a: m4-ethernet0-rgmii-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ m4_fmc_pins_a: m4-fmc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
+ <STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
+ };
+ };
+
+ m4_hdp0_pins_a: m4-hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
+ };
+ };
+
+ m4_hdp6_pins_a: m4-hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
+ };
+ };
+
+ m4_hdp7_pins_a: m4-hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
+ };
+ };
+
+ m4_i2c1_pins_a: m4-i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
+ };
+ };
+
+ m4_i2c2_pins_a: m4-i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
+ };
+ };
+
+ m4_i2c5_pins_a: m4-i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
+ };
+ };
+
+ m4_i2s2_pins_a: m4-i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
+ };
+ };
+
+ m4_ltdc_pins_a: m4-ltdc-a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_ltdc_pins_b: m4-ltdc-b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
+ };
+ };
+
+ m4_m_can1_pins_a: m4-m-can1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
+ };
+ };
+
+ m4_pwm1_pins_a: m4-pwm1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
+ };
+ };
+
+ m4_pwm2_pins_a: m4-pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
+ };
+ };
+
+ m4_pwm3_pins_a: m4-pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
+ };
+ };
+
+ m4_pwm4_pins_a: m4-pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
+ };
+ };
+
+ m4_pwm4_pins_b: m4-pwm4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
+ };
+ };
+
+ m4_pwm5_pins_a: m4-pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
+ };
+ };
+
+ m4_pwm8_pins_a: m4-pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
+ };
+ };
+
+ m4_pwm12_pins_a: m4-pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ m4_qspi_clk_pins_a: m4-qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
+ };
+ };
+
+ m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
+ };
+ };
+
+ m4_sai2a_pins_a: m4-sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ m4_sai2b_pins_a: m4-sai2b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
+ <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai2b_pins_b: m4-sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
+ };
+ };
+
+ m4_sai4a_pins_a: m4-sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
+ };
+ };
+
+ m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
+ <STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
+ };
+ };
+
+ m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
+ <STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
+ };
+ };
+
+ m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
+ };
+ };
+
+ m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
+ };
+ };
+
+ m4_spdifrx_pins_a: m4-spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
+ };
+ };
+
+ m4_spi4_pins_a: m4-spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
+ <STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
+ };
+ };
+
+ m4_spi5_pins_a: m4-spi5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
+ <STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
+ };
+ };
+
+ m4_stusb1600_pins_a: m4-stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, RSVD)>;
+ };
+ };
+
+ m4_uart4_pins_a: m4-uart4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
+ };
+ };
+
+ m4_uart7_pins_a: m4-uart7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
+ <STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
+ };
+ };
+
+ m4_usart2_pins_a: m4-usart2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_a: m4-usart3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usart3_pins_b: m4-usart3-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
+ };
+ };
+
+ m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
+ };
+ };
+
+ m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
+ };
+ };
+};
+
+&pinctrl_z {
+ m4_i2c4_pins_a: m4-i2c4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
+ };
+ };
+
+ m4_spi1_pins_a: m4-spi1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
+ <STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi b/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi
new file mode 100644
index 000000000000..7fa3ca411a95
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-m4-srm.dtsi
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+&m4_rproc {
+ m4_system_resources {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m4_timers2: timer@40000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40000000 0x400>;
+ clocks = <&rcc TIM2_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers3: timer@40001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40001000 0x400>;
+ clocks = <&rcc TIM3_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers4: timer@40002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40002000 0x400>;
+ clocks = <&rcc TIM4_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers5: timer@40003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40003000 0x400>;
+ clocks = <&rcc TIM5_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers6: timer@40004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40004000 0x400>;
+ clocks = <&rcc TIM6_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers7: timer@40005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40005000 0x400>;
+ clocks = <&rcc TIM7_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers12: timer@40006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40006000 0x400>;
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers13: timer@40007000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40007000 0x400>;
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers14: timer@40008000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40008000 0x400>;
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_lptimer1: timer@40009000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40009000 0x400>;
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_spi2: spi@4000b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000b000 0x400>;
+ clocks = <&rcc SPI2_K>;
+ status = "disabled";
+ };
+ m4_i2s2: audio-controller@4000b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000b000 0x400>;
+ status = "disabled";
+ };
+ m4_spi3: spi@4000c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000c000 0x400>;
+ clocks = <&rcc SPI3_K>;
+ status = "disabled";
+ };
+ m4_i2s3: audio-controller@4000c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000c000 0x400>;
+ status = "disabled";
+ };
+ m4_spdifrx: audio-controller@4000d000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000d000 0x400>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ status = "disabled";
+ };
+ m4_usart2: serial@4000e000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000e000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <27 1>;
+ clocks = <&rcc USART2_K>;
+ status = "disabled";
+ };
+ m4_usart3: serial@4000f000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4000f000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <28 1>;
+ clocks = <&rcc USART3_K>;
+ status = "disabled";
+ };
+ m4_uart4: serial@40010000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40010000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <30 1>;
+ clocks = <&rcc UART4_K>;
+ status = "disabled";
+ };
+ m4_uart5: serial@40011000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40011000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <31 1>;
+ clocks = <&rcc UART5_K>;
+ status = "disabled";
+ };
+ m4_i2c1: i2c@40012000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40012000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <21 1>;
+ clocks = <&rcc I2C1_K>;
+ status = "disabled";
+ };
+ m4_i2c2: i2c@40013000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40013000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <22 1>;
+ clocks = <&rcc I2C2_K>;
+ status = "disabled";
+ };
+ m4_i2c3: i2c@40014000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40014000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <23 1>;
+ clocks = <&rcc I2C3_K>;
+ status = "disabled";
+ };
+ m4_i2c5: i2c@40015000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40015000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <25 1>;
+ clocks = <&rcc I2C5_K>;
+ status = "disabled";
+ };
+ m4_cec: cec@40016000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40016000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <69 1>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
+ clock-names = "cec", "hdmi-cec";
+ status = "disabled";
+ };
+ m4_dac: dac@40017000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40017000 0x400>;
+ clocks = <&rcc DAC12>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+ m4_uart7: serial@40018000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40018000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <32 1>;
+ clocks = <&rcc UART7_K>;
+ status = "disabled";
+ };
+ m4_uart8: serial@40019000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x40019000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <33 1>;
+ clocks = <&rcc UART8_K>;
+ status = "disabled";
+ };
+ m4_timers1: timer@44000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44000000 0x400>;
+ clocks = <&rcc TIM1_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers8: timer@44001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44001000 0x400>;
+ clocks = <&rcc TIM8_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_usart6: serial@44003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44003000 0x400>;
+ interrupt-parent = <&exti>;
+ interrupts = <29 1>;
+ clocks = <&rcc USART6_K>;
+ status = "disabled";
+ };
+ m4_spi1: spi@44004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44004000 0x400>;
+ clocks = <&rcc SPI1_K>;
+ status = "disabled";
+ };
+ m4_i2s1: audio-controller@44004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44004000 0x400>;
+ status = "disabled";
+ };
+ m4_spi4: spi@44005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44005000 0x400>;
+ clocks = <&rcc SPI4_K>;
+ status = "disabled";
+ };
+ m4_timers15: timer@44006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44006000 0x400>;
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers16: timer@44007000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44007000 0x400>;
+ clocks = <&rcc TIM16_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_timers17: timer@44008000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44008000 0x400>;
+ clocks = <&rcc TIM17_K>;
+ clock-names = "int";
+ status = "disabled";
+ };
+ m4_spi5: spi@44009000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x44009000 0x400>;
+ clocks = <&rcc SPI5_K>;
+ status = "disabled";
+ };
+ m4_sai1: sai@4400a000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400a000 0x4>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_sai2: sai@4400b000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400b000 0x4>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_sai3: sai@4400c000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400c000 0x4>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_dfsdm: dfsdm@4400d000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+ clock-names = "dfsdm", "audio";
+ status = "disabled";
+ };
+ m4_m_can1: can@4400e000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ status = "disabled";
+ };
+ m4_m_can2: can@4400f000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ status = "disabled";
+ };
+ m4_dma1: dma@48000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48000000 0x400>;
+ clocks = <&rcc DMA1>;
+ status = "disabled";
+ };
+ m4_dma2: dma@48001000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48001000 0x400>;
+ clocks = <&rcc DMA2>;
+ status = "disabled";
+ };
+ m4_dmamux1: dma-router@48002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48002000 0x1c>;
+ clocks = <&rcc DMAMUX>;
+ status = "disabled";
+ };
+ m4_adc: adc@48003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48003000 0x400>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ status = "disabled";
+ };
+ m4_sdmmc3: sdmmc@48004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
+ clocks = <&rcc SDMMC3_K>;
+ status = "disabled";
+ };
+ m4_usbotg_hs: usb-otg@49000000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x49000000 0x10000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+ m4_hash2: hash@4c002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c002000 0x400>;
+ clocks = <&rcc HASH2>;
+ status = "disabled";
+ };
+ m4_rng2: rng@4c003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c003000 0x400>;
+ clocks = <&rcc RNG2_K>;
+ status = "disabled";
+ };
+ m4_crc2: crc@4c004000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c004000 0x400>;
+ clocks = <&rcc CRC2>;
+ status = "disabled";
+ };
+ m4_cryp2: cryp@4c005000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c005000 0x400>;
+ clocks = <&rcc CRYP2>;
+ status = "disabled";
+ };
+ m4_dcmi: dcmi@4c006000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x4c006000 0x400>;
+ clocks = <&rcc DCMI>;
+ clock-names = "mclk";
+ status = "disabled";
+ };
+ m4_lptimer2: timer@50021000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50021000 0x400>;
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer3: timer@50022000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50022000 0x400>;
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer4: timer@50023000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50023000 0x400>;
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_lptimer5: timer@50024000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50024000 0x400>;
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ status = "disabled";
+ };
+ m4_sai4: sai@50027000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x50027000 0x4>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ status = "disabled";
+ };
+ m4_fmc: memory-controller@58002000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x5800200 0x1000>;
+ clocks = <&rcc FMC_K>;
+ status = "disabled";
+ };
+ m4_qspi: qspi@58003000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ clocks = <&rcc QSPI_K>;
+ status = "disabled";
+ };
+ m4_ethernet0: ethernet@5800a000 {
+ compatible = "rproc-srm-dev";
+ reg = <0x5800a000 0x2000>;
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "syscfg-clk";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
+ <&rcc ETHSTP>,
+ <&rcc SYSCFG>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index d3553e0f0187..43eb55cb1f55 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -151,7 +151,46 @@
};
};
- ethernet0_rgmii_pins_a: rgmii-0 {
+ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
+ };
+ };
+
+ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
+ };
+ };
+
+ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
+ };
+ };
+
+ ethernet0_rgmii_pins_a: ethernet0-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@@ -182,7 +221,7 @@
};
};
- ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
+ ethernet0_rgmii_sleep_pins_a: ethernet0-rgmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@@ -202,7 +241,7 @@
};
};
- ethernet0_rgmii_pins_b: rgmii-1 {
+ ethernet0_rgmii_pins_b: ethernet0-rgmii-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@@ -233,7 +272,7 @@
};
};
- ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
+ ethernet0_rgmii_sleep_pins_b: ethernet0-rgmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@@ -253,7 +292,7 @@
};
};
- ethernet0_rgmii_pins_c: rgmii-2 {
+ ethernet0_rgmii_pins_c: ethernet0-rgmii-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@@ -284,7 +323,7 @@
};
};
- ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
+ ethernet0_rgmii_sleep_pins_c: ethernet0-rgmii-sleep-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@@ -304,7 +343,7 @@
};
};
- ethernet0_rmii_pins_a: rmii-0 {
+ ethernet0_rmii_pins_a: ethernet0-rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
@@ -324,7 +363,7 @@
};
};
- ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
+ ethernet0_rmii_sleep_pins_a: ethernet0-rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
@@ -437,6 +476,51 @@
};
};
+ hdp0_pins_a: hdp0-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp0_pins_sleep_a: hdp0-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
+ };
+ };
+
+ hdp6_pins_a: hdp6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp6_pins_sleep_a: hdp6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
+ };
+ };
+
+ hdp7_pins_a: hdp7-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ hdp7_pins_sleep_a: hdp7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -861,7 +945,7 @@
};
};
- m_can1_sleep_pins_a: m_can1-sleep-0 {
+ m_can1_sleep_pins_a: m-can1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
@@ -881,7 +965,7 @@
};
};
- m_can1_sleep_pins_b: m_can1-sleep-1 {
+ m_can1_sleep_pins_b: m-can1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
@@ -901,7 +985,7 @@
};
};
- m_can2_sleep_pins_a: m_can2-sleep-0 {
+ m_can2_sleep_pins_a: m-can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
@@ -1068,23 +1152,8 @@
};
};
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -1093,12 +1162,6 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
@@ -1106,13 +1169,12 @@
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -1121,7 +1183,49 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
+ };
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
+ };
+ };
+
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ qspi_cs2_pins_a: qspi-cs2-0 {
+ pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@@ -1129,13 +1233,15 @@
};
};
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
};
};
@@ -1282,6 +1388,18 @@
};
};
+ sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -1306,18 +1424,6 @@
};
};
- sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@@ -1716,9 +1822,55 @@
};
};
+ spi4_pins_b: spi4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+ bias-disable;
+ };
+ };
+
+ spi4_sleep_pins_b: spi4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
+ };
+ };
+
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ spi5_sleep_pins_a: spi5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
+ };
+ };
+
stusb1600_pins_a: stusb1600-0 {
pins {
- pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ pinmux = <STM32_PINMUX('I', 11, GPIO)>;
bias-pull-up;
};
};
@@ -1737,20 +1889,20 @@
};
uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
};
uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
+ pins {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
+ };
};
uart4_pins_b: uart4-1 {
@@ -1816,7 +1968,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1826,7 +1978,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1850,7 +2002,7 @@
};
};
- uart8_rtscts_pins_a: uart8rtscts-0 {
+ uart8_rtscts_pins_a: uart8-rtscts-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
<STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
@@ -1912,7 +2064,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -1930,7 +2082,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2012,7 +2164,7 @@
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
@@ -2029,7 +2181,7 @@
};
pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -2042,16 +2194,16 @@
};
};
- usbotg_hs_pins_a: usbotg-hs-0 {
+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
- pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
};
};
- usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
};
@@ -2120,4 +2272,12 @@
bias-disable;
};
};
+
+ spi1_sleep_pins_a: spi1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
+ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
};
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index e0d483318798..e7e081f781aa 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
/ {
@@ -17,9 +18,14 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
device_type = "cpu";
reg = <0>;
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ #cooling-cells = <2>;
};
};
@@ -30,6 +36,49 @@
interrupt-parent = <&intc>;
};
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ };
+
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi_shm@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -45,45 +94,13 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_csi: clk-csi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4000000>;
- };
- };
-
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@@ -91,12 +108,6 @@
thermal-sensors = <&dts>;
trips {
- cpu_alert1: cpu-alert1 {
- temperature = <85000>;
- hysteresis = <0>;
- type = "passive";
- };
-
cpu-crit {
temperature = <120000>;
hysteresis = <0>;
@@ -115,6 +126,26 @@
status = "disabled";
};
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -122,6 +153,14 @@
interrupt-parent = <&intc>;
ranges;
+ sram: sram@10000000 {
+ compatible = "mmio-sram";
+ reg = <0x10000000 0x60000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10000000 0x60000>;
+ };
+
timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -129,11 +168,11 @@
reg = <0x40000000 0x400>;
clocks = <&rcc TIM2_K>;
clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
+ dmas = <&dmamux1 18 0x400 0x80000001>,
+ <&dmamux1 19 0x400 0x80000001>,
+ <&dmamux1 20 0x400 0x80000001>,
+ <&dmamux1 21 0x400 0x80000001>,
+ <&dmamux1 22 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up";
status = "disabled";
@@ -162,12 +201,12 @@
reg = <0x40001000 0x400>;
clocks = <&rcc TIM3_K>;
clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
+ dmas = <&dmamux1 23 0x400 0x80000001>,
+ <&dmamux1 24 0x400 0x80000001>,
+ <&dmamux1 25 0x400 0x80000001>,
+ <&dmamux1 26 0x400 0x80000001>,
+ <&dmamux1 27 0x400 0x80000001>,
+ <&dmamux1 28 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
@@ -196,10 +235,10 @@
reg = <0x40002000 0x400>;
clocks = <&rcc TIM4_K>;
clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
+ dmas = <&dmamux1 29 0x400 0x80000001>,
+ <&dmamux1 30 0x400 0x80000001>,
+ <&dmamux1 31 0x400 0x80000001>,
+ <&dmamux1 32 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4";
status = "disabled";
@@ -228,12 +267,12 @@
reg = <0x40003000 0x400>;
clocks = <&rcc TIM5_K>;
clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
+ dmas = <&dmamux1 55 0x400 0x80000001>,
+ <&dmamux1 56 0x400 0x80000001>,
+ <&dmamux1 57 0x400 0x80000001>,
+ <&dmamux1 58 0x400 0x80000001>,
+ <&dmamux1 59 0x400 0x80000001>,
+ <&dmamux1 60 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
@@ -262,7 +301,7 @@
reg = <0x40004000 0x400>;
clocks = <&rcc TIM6_K>;
clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
+ dmas = <&dmamux1 69 0x400 0x80000001>;
dma-names = "up";
status = "disabled";
@@ -280,7 +319,7 @@
reg = <0x40005000 0x400>;
clocks = <&rcc TIM7_K>;
clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
+ dmas = <&dmamux1 70 0x400 0x80000001>;
dma-names = "up";
status = "disabled";
@@ -365,6 +404,7 @@
interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -384,6 +424,22 @@
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
};
spi2: spi@4000b000 {
@@ -394,19 +450,19 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI2_K>;
resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
- i2s2: audio-controller@4000b000 {
+ i2s3: audio-controller@4000c000 {
compatible = "st,stm32h7-i2s";
#sound-dai-cells = <0>;
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -419,17 +475,6 @@
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI3_K>;
resets = <&rcc SPI3_R>;
- dmas = <&dmamux1 61 0x400 0x05>,
- <&dmamux1 62 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s3: audio-controller@4000c000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 61 0x400 0x01>,
<&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
@@ -455,6 +500,10 @@
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 43 0x400 0x15>,
+ <&dmamux1 44 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -464,6 +513,10 @@
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 45 0x400 0x15>,
+ <&dmamux1 46 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -473,6 +526,10 @@
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 63 0x400 0x15>,
+ <&dmamux1 64 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -482,6 +539,10 @@
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 65 0x400 0x15>,
+ <&dmamux1 66 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -489,12 +550,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40012000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C1_K>;
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 33 0x400 0x80000001>,
+ <&dmamux1 34 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
i2c-analog-filter;
@@ -505,12 +570,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C2_K>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 35 0x400 0x80000001>,
+ <&dmamux1 36 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
i2c-analog-filter;
@@ -521,12 +590,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40014000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 73 0x400 0x80000001>,
+ <&dmamux1 74 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
i2c-analog-filter;
@@ -537,12 +610,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40015000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&dmamux1 115 0x400 0x80000001>,
+ <&dmamux1 116 0x400 0x80000001>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
i2c-analog-filter;
@@ -588,6 +665,10 @@
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 79 0x400 0x15>,
+ <&dmamux1 80 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -597,6 +678,10 @@
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 81 0x400 0x15>,
+ <&dmamux1 82 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -607,13 +692,13 @@
reg = <0x44000000 0x400>;
clocks = <&rcc TIM1_K>;
clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
+ dmas = <&dmamux1 11 0x400 0x80000001>,
+ <&dmamux1 12 0x400 0x80000001>,
+ <&dmamux1 13 0x400 0x80000001>,
+ <&dmamux1 14 0x400 0x80000001>,
+ <&dmamux1 15 0x400 0x80000001>,
+ <&dmamux1 16 0x400 0x80000001>,
+ <&dmamux1 17 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
status = "disabled";
@@ -643,13 +728,13 @@
reg = <0x44001000 0x400>;
clocks = <&rcc TIM8_K>;
clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
+ dmas = <&dmamux1 47 0x400 0x80000001>,
+ <&dmamux1 48 0x400 0x80000001>,
+ <&dmamux1 49 0x400 0x80000001>,
+ <&dmamux1 50 0x400 0x80000001>,
+ <&dmamux1 51 0x400 0x80000001>,
+ <&dmamux1 52 0x400 0x80000001>,
+ <&dmamux1 53 0x400 0x80000001>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
status = "disabled";
@@ -678,28 +763,32 @@
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
wakeup-source;
+ power-domains = <&pd_core>;
+ dmas = <&dmamux1 71 0x400 0x15>,
+ <&dmamux1 72 0x400 0x11>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi1: spi@44004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
reg = <0x44004000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI1_K>;
- resets = <&rcc SPI1_R>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
- i2s1: audio-controller@44004000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
+ spi1: spi@44004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
reg = <0x44004000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI1_K>;
+ resets = <&rcc SPI1_R>;
dmas = <&dmamux1 37 0x400 0x01>,
<&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
@@ -714,8 +803,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
- dmas = <&dmamux1 83 0x400 0x05>,
- <&dmamux1 84 0x400 0x05>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -727,10 +816,10 @@
reg = <0x44006000 0x400>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
+ dmas = <&dmamux1 105 0x400 0x80000001>,
+ <&dmamux1 106 0x400 0x80000001>,
+ <&dmamux1 107 0x400 0x80000001>,
+ <&dmamux1 108 0x400 0x80000001>;
dma-names = "ch1", "up", "trig", "com";
status = "disabled";
@@ -754,8 +843,8 @@
reg = <0x44007000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
+ dmas = <&dmamux1 109 0x400 0x80000001>,
+ <&dmamux1 110 0x400 0x80000001>;
dma-names = "ch1", "up";
status = "disabled";
@@ -778,8 +867,8 @@
reg = <0x44008000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
+ dmas = <&dmamux1 111 0x400 0x80000001>,
+ <&dmamux1 112 0x400 0x80000001>;
dma-names = "ch1", "up";
status = "disabled";
@@ -804,8 +893,8 @@
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI5_K>;
resets = <&rcc SPI5_R>;
- dmas = <&dmamux1 85 0x400 0x05>,
- <&dmamux1 86 0x400 0x05>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -990,6 +1079,15 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
dma2: dma-controller@48001000 {
@@ -1008,6 +1106,15 @@
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
};
dmamux1: dma-router@48002000 {
@@ -1038,10 +1145,12 @@
adc1: adc@0 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x01>;
+ dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
};
@@ -1049,17 +1158,29 @@
adc2: adc@100 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
- dmas = <&dmamux1 10 0x400 0x01>;
+ dmas = <&dmamux1 10 0x400 0x80000001>;
dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
status = "disabled";
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ };
};
};
sdmmc3: mmc@48004000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@@ -1076,31 +1197,42 @@
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
- clocks = <&rcc USBO_K>;
- clock-names = "otg";
+ clocks = <&rcc USBO_K>, <&usbphyc>;
+ clock-names = "otg", "utmi";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
+ otg-rev = <0x200>;
usb33d-supply = <&usb33>;
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
+ hsem: hwspinlock@4c000000 {
+ compatible = "st,stm32-hwspinlock";
+ #hwlock-cells = <2>;
+ reg = <0x4c000000 0x400>;
+ clocks = <&rcc HSEM>;
+ clock-names = "hsem";
+ };
+
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 61 1>;
- interrupt-names = "rx", "tx", "wakeup";
+ <&exti 61 1>,
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;
wakeup-source;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1111,21 +1243,29 @@
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0x01>;
+ dmas = <&dmamux1 75 0x400 0xe0000001>;
dma-names = "tx";
status = "disabled";
};
rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
+ compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
};
pwr_regulators: pwr@50001000 {
compatible = "st,stm32mp1,pwr-reg";
reg = <0x50001000 0x10>;
+ st,tzcr = <&rcc 0x0 0x1>;
reg11: reg11 {
regulator-name = "reg11";
@@ -1151,11 +1291,87 @@
reg = <0x50001014 0x4>;
};
+ pwr_irq: pwr@50001020 {
+ compatible = "st,stm32mp1-pwr";
+ reg = <0x50001020 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ st,wakeup-pins = <&gpioa 0 GPIO_ACTIVE_HIGH>,
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
+ #address-cells = <0>;
reg = <0x5000d000 0x400>;
+ hwlocks = <&hsem 1 1>;
+ wakeup-parent = <&pwr_irq>;
+
+ exti-interrupt-map {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-map-mask = <0xffffffff 0>;
+ interrupt-map =
+ <0 0 &intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <12 0 &intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <13 0 &intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <14 0 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <15 0 &intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <16 0 &intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <19 0 &intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <21 0 &intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <22 0 &intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <23 0 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <24 0 &intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <25 0 &intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <26 0 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <27 0 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <28 0 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <29 0 &intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <30 0 &intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <31 0 &intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <32 0 &intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <33 0 &intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <43 0 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <44 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <47 0 &intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <48 0 &intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <50 0 &intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <52 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <53 0 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <54 0 &intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <55 0 &pwr_irq 0 IRQ_TYPE_EDGE_FALLING 0>,
+ <56 0 &pwr_irq 1 IRQ_TYPE_EDGE_FALLING 0>,
+ <57 0 &pwr_irq 2 IRQ_TYPE_EDGE_FALLING 0>,
+ <58 0 &pwr_irq 3 IRQ_TYPE_EDGE_FALLING 0>,
+ <59 0 &pwr_irq 4 IRQ_TYPE_EDGE_FALLING 0>,
+ <60 0 &pwr_irq 5 IRQ_TYPE_EDGE_FALLING 0>,
+ <61 0 &intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <65 0 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <68 0 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <69 0 &intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <70 0 &intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <73 0 &intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
syscfg: syscon@50020000 {
@@ -1172,6 +1388,7 @@
interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1191,6 +1408,11 @@
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer3: timer@50022000 {
@@ -1201,6 +1423,7 @@
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1215,6 +1438,11 @@
reg = <2>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer4: timer@50023000 {
@@ -1223,6 +1451,7 @@
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1231,6 +1460,11 @@
#pwm-cells = <3>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
lptimer5: timer@50024000 {
@@ -1239,6 +1473,7 @@
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
wakeup-source;
status = "disabled";
@@ -1247,6 +1482,11 @@
#pwm-cells = <3>;
status = "disabled";
};
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
vrefbuf: vrefbuf@50025000 {
@@ -1299,13 +1539,21 @@
status = "disabled";
};
+ hdp: hdp@5002a000 {
+ compatible = "st,stm32mp1-hdp";
+ reg = <0x5002a000 0x400>;
+ clocks = <&rcc HDP>;
+ clock-names = "hdp";
+ status = "disabled";
+ };
+
hash1: hash@54002000 {
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc HASH1>;
- resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@@ -1314,8 +1562,8 @@
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
status = "disabled";
};
@@ -1324,8 +1572,8 @@
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
- resets = <&rcc MDMA_R>;
- #dma-cells = <5>;
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+ #dma-cells = <6>;
dma-channels = <32>;
dma-requests = <48>;
};
@@ -1356,9 +1604,9 @@
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
status = "disabled";
};
@@ -1369,8 +1617,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
- <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0 0x0>,
+ <&mdma1 22 0x2 0x10100008 0x0 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1380,7 +1628,7 @@
};
sdmmc1: mmc@58005000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -1395,7 +1643,7 @@
};
sdmmc2: mmc@58007000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -1420,8 +1668,10 @@
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_wake_irq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
@@ -1441,6 +1691,7 @@
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
+ power-domains = <&pd_core>;
stmmac_axi_config_0: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
@@ -1463,8 +1714,10 @@
reg = <0x5800d000 0x1000>;
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
};
@@ -1487,7 +1740,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
@@ -1515,12 +1768,21 @@
};
};
+ ddrperfm: perf@5a007000 {
+ compatible = "st,stm32-ddr-pmu";
+ reg = <0x5a007000 0x400>;
+ clocks = <&rcc DDRPERFM>;
+ resets = <&rcc DDRPERFM_R>;
+ status = "disabled";
+ };
+
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
+ clocks = <&scmi_clk CK_SCMI_USART1>;
wakeup-source;
+ power-domains = <&pd_core>;
status = "disabled";
};
@@ -1530,10 +1792,10 @@
compatible = "st,stm32h7-spi";
reg = <0x5c001000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI6_K>;
- resets = <&rcc SPI6_R>;
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
+ clocks = <&scmi_clk CK_SCMI_SPI6>;
+ resets = <&scmi_reset RST_SCMI_SPI6>;
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1542,12 +1804,16 @@
compatible = "st,stm32mp15-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
+ interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
i2c-analog-filter;
@@ -1557,35 +1823,50 @@
rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+ <&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
+ clocks = <&scmi_clk CK_SCMI_BSEC>;
#address-cells = <1>;
#size-cells = <1>;
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x1>;
+ };
+ vrefint: calib@52 {
+ reg = <0x52 0x2>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac_address: mac@e4 {
+ reg = <0xe4 0x6>;
+ };
};
i2c6: i2c@5c009000 {
compatible = "st,stm32mp15-i2c";
reg = <0x5c009000 0x400>;
interrupt-names = "event", "error";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C6_K>;
- resets = <&rcc I2C6_R>;
+ interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_I2C6>;
+ resets = <&scmi_reset RST_SCMI_I2C6>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
i2c-analog-filter;
@@ -1595,19 +1876,33 @@
tamp: tamp@5c00a000 {
compatible = "st,stm32-tamp", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x150>; /* reg20 */
+ mask = <0xff>;
+ mode-normal = <0>;
+ mode-fastboot = <0x1>;
+ mode-recovery = <0x2>;
+ mode-stm32cubeprogrammer = <0x3>;
+ mode-ums_mmc0 = <0x10>;
+ mode-ums_mmc1 = <0x11>;
+ mode-ums_mmc2 = <0x12>;
+ };
};
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
- pinctrl: pin-controller@50002000 {
+ pinctrl: pinctrl@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-pinctrl";
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hsem 0 1>;
pins-are-numbered;
gpioa: gpio@50002000 {
@@ -1732,7 +2027,7 @@
};
};
- pinctrl_z: pin-controller-z@54004000 {
+ pinctrl_z: pinctrl@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
@@ -1740,6 +2035,7 @@
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hsem 0 1>;
gpioz: gpio@54004000 {
gpio-controller;
@@ -1747,7 +2043,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
@@ -1769,13 +2065,18 @@
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
+ resets = <&scmi_reset RST_SCMI_MCU>,
+ <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
status = "disabled";
+
+ m4_system_resources {
+ compatible = "rproc-srm-core";
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 1c1889b194cf..56ff32b4a42f 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -10,9 +10,11 @@
cpus {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
device_type = "cpu";
reg = <1>;
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -22,6 +24,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+ timer {
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
@@ -30,7 +39,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@@ -43,7 +52,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi
index 54e73ccea446..1d82868f3657 100644
--- a/arch/arm/boot/dts/stm32mp157.dtsi
+++ b/arch/arm/boot/dts/stm32mp157.dtsi
@@ -20,7 +20,8 @@
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ phy-dsi-supply = <&reg18>;
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157a-dk1-a7-examples.dts
new file mode 100644
index 000000000000..f58b679ef127
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-a7-examples.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157A-DK1 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157a-dk1-a7-examples", "st,stm32mp157a-dk1", "st,stm32mp157";
+};
+
+&adc {
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+
+ adc1: adc@0 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@13 {
+ reg = <13>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+
+ adc2: adc@100 {
+ /* Set IRQ mode as example. DMA is the preferred mode, yet. */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+};
+
+&timers3 {
+ status = "okay";
+};
+
+&timers4 {
+ status = "okay";
+};
+
+&timers5 {
+ status = "okay";
+};
+
+&timers6 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157a-dk1-m4-examples.dts
new file mode 100644
index 000000000000..a6e9e1af9e16
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-m4-examples.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157A-DK1 configured to run M4 examples";
+ compatible = "st,stm32mp157a-dk1-m4-examples", "st,stm32mp157a-dk1", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&m4_adc {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi4_pins_a>;
+ status = "okay";
+};
+
+&m4_timers1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ status = "okay";
+};
+
+&m4_uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_uart7_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
+ };
+ };
+
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
+ };
+ };
+};
+
+&timers1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 4c8be9c8eb20..f48207dad581 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
@@ -15,13 +16,6 @@
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
- aliases {
- ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/stm32mp157a-ed1.dts b/arch/arm/boot/dts/stm32mp157a-ed1.dts
new file mode 100644
index 000000000000..0213ca5c17fa
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157A eval daughter";
+ compatible = "st,stm32mp157a-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-ev1.dts b/arch/arm/boot/dts/stm32mp157a-ev1.dts
new file mode 100644
index 000000000000..a96fbc84067a
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-ev1.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157a-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157A eval daughter on eval mother";
+ compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
new file mode 100644
index 000000000000..6c7608fc45f8
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-a7-examples.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157c-dk2-a7-examples", "st,stm32mp157c-dk2", "st,stm32mp157";
+};
+
+&adc {
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+
+ adc1: adc@0 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@13 {
+ reg = <13>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+
+ adc2: adc@100 {
+ /* Set IRQ mode as example. DMA is the preferred mode, yet. */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+};
+
+&timers3 {
+ status = "okay";
+};
+
+&timers4 {
+ status = "okay";
+};
+
+&timers5 {
+ status = "okay";
+};
+
+&timers6 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
new file mode 100644
index 000000000000..e770942e8369
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-m4-examples.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 configured to run M4 examples";
+ compatible = "st,stm32mp157c-dk2-m4-examples", "st,stm32mp157c-dk2", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&m4_adc {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi4_pins_a>;
+ status = "okay";
+};
+
+&m4_timers1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ status = "okay";
+};
+
+&m4_uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_uart7_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
+ };
+ };
+
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
+ };
+ };
+};
+
+&timers1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 2bc92ef3aeb9..ae907776617b 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -11,21 +11,32 @@
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
+#include <dt-bindings/rtc/rtc-stm32.h>
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
- ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
serial3 = &usart2;
};
chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
};
};
@@ -35,7 +46,6 @@
&dsi {
status = "okay";
- phy-dsi-supply = <&reg18>;
ports {
port@0 {
@@ -53,7 +63,7 @@
};
};
- panel@0 {
+ panel_otm8009a: panel-otm8009a@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@@ -77,6 +87,9 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
+ panel = <&panel_otm8009a>;
+ vcc-supply = <&v3v3>;
+ iovcc-supply = <&v3v3>;
status = "okay";
};
};
@@ -92,10 +105,50 @@
};
};
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+};
+
+/* Wifi */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpiod>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; /* WL_HOST_WAKE */
+ interrupt-names = "host-wake";
+ };
+};
+
+/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
- status = "disabled";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3>;
+ vddio-supply = <&v3v3>;
+ };
};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 46b471d09c50..d2c24803b99e 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
@@ -9,8 +9,7 @@
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
+#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter";
@@ -20,381 +19,18 @@
stdout-path = "serial0:115200n8";
};
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x40000000>;
- };
-
reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
-
- gpu_reserved: gpu@e8000000 {
- reg = <0xe8000000 0x8000000>;
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
no-map;
};
};
-
- aliases {
- serial0 = &uart4;
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
- pinctrl-0 = <&adc1_in6_pins_a>;
- pinctrl-names = "default";
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "disabled";
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- /* 16.5 ck_cycles sampling time */
- st,min-sample-time-nsecs = <400>;
- status = "okay";
- };
-};
-
-&crc1 {
- status = "okay";
};
&cryp1 {
status = "okay";
};
-&dac {
- pinctrl-names = "default";
- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
- vref-supply = <&vdda>;
- status = "disabled";
- dac1: dac@1 {
- status = "okay";
- };
- dac2: dac@2 {
- status = "okay";
- };
-};
-
-&dts {
- status = "okay";
-};
-
&gpu {
contiguous-area = <&gpu_reserved>;
};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
- mbox-names = "vq0", "vq1", "shutdown", "detach";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&timers6 {
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- timer@5 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- status = "okay";
-};
-
-&usbotg_hs {
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
new file mode 100644
index 000000000000..9f516309c29f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-a7-examples.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-ev1.dts"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157C-EV1 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157c-ev1-a7-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ test_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ status = "okay";
+ /* gpio needs vdd core in retention for wakeup */
+ power-domains = <&pd_core_ret>;
+
+ button-1 {
+ label = "PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ status = "okay";
+ wakeup-source;
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+};
+
+&dac {
+ status = "okay";
+};
+
+&timers2 {
+ status = "okay";
+};
+
+&timers8 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
new file mode 100644
index 000000000000..07684f340b39
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-m4-examples.dts
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-ev1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-EV1 configured to run M4 examples";
+ compatible = "st,stm32mp157c-ev1-m4-examples", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dcmi {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&fmc {
+ status = "disabled";
+};
+
+&i2c5 {
+ status = "disabled";
+};
+
+&m4_adc {
+ vref-supply = <&vdda>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vdda>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a
+ &m4_qspi_bk2_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ /* button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+ */
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi1_pins_a>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm2_pins_a>;
+ status = "okay";
+};
+
+&m4_usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_usart3_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 8, RSVD)>;
+ };
+ };
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&sai2b {
+ status = "disabled";
+};
+
+&sound {
+ status = "disabled";
+};
+
+&timers2 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 5c5b1ddf7bfd..17434d903f10 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -1,69 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157c-ed1.dts"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- ethernet0 = &ethernet0;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
};
};
@@ -75,35 +33,15 @@
};
};
-&cec {
- pinctrl-names = "default";
- pinctrl-0 = <&cec_pins_a>;
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dcmi_pins_a>;
- pinctrl-1 = <&dcmi_sleep_pins_a>;
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov5640_0>;
- bus-type = <5>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
&dsi {
- phy-dsi-supply = <&reg18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
port@0 {
reg = <0>;
dsi_in: endpoint {
@@ -119,7 +57,7 @@
};
};
- panel-dsi@0 {
+ panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@@ -135,106 +73,20 @@
};
};
-&ethernet0 {
- status = "okay";
- pinctrl-0 = <&ethernet0_rgmii_pins_a>;
- pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
&i2c2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- ov5640: camera@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- DOVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
- rotation = <180>;
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
status = "okay";
- port {
- ov5640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
- };
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick-pins {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- bias-pull-down;
- };
- };
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
};
};
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
&ltdc {
status = "okay";
@@ -245,133 +97,3 @@
};
};
};
-
-&m_can1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: mx66l51235l@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- flash1: mx66l51235l@1 {
- compatible = "jedec,spi-nor";
- reg = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "disabled";
-};
-
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-1 = <&pwm2_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_b>;
- pinctrl-1 = <&usart3_sleep_pins_b>;
- pinctrl-2 = <&usart3_idle_pins_b>;
- /*
- * HW flow control USART3_RTS is optional, and isn't default wired to
- * the connector. SB23 needs to be soldered in order to use it, and R77
- * (ETH_CLK) should be removed.
- */
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157d-dk1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157d-dk1-a7-examples.dts
new file mode 100644
index 000000000000..745cec886c25
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157d-dk1-a7-examples.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157d-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157D-DK1 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157d-dk1-a7-examples", "st,stm32mp157d-dk1", "st,stm32mp157";
+};
+
+&adc {
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+
+ adc1: adc@0 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@13 {
+ reg = <13>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+
+ adc2: adc@100 {
+ /* Set IRQ mode as example. DMA is the preferred mode, yet. */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+};
+
+&timers3 {
+ status = "okay";
+};
+
+&timers4 {
+ status = "okay";
+};
+
+&timers5 {
+ status = "okay";
+};
+
+&timers6 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157d-dk1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157d-dk1-m4-examples.dts
new file mode 100644
index 000000000000..d1088b95f7fd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157d-dk1-m4-examples.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157d-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157D-DK1 configured to run M4 examples";
+ compatible = "st,stm32mp157d-dk1-m4-examples", "st,stm32mp157d-dk1", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&m4_adc {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi4_pins_a>;
+ status = "okay";
+};
+
+&m4_timers1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ status = "okay";
+};
+
+&m4_uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_uart7_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
+ };
+ };
+
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
+ };
+ };
+};
+
+&timers1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157d-dk1.dts b/arch/arm/boot/dts/stm32mp157d-dk1.dts
new file mode 100644
index 000000000000..99a4e0f9c471
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157d-dk1.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xd.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
+ compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157d-ed1.dts b/arch/arm/boot/dts/stm32mp157d-ed1.dts
new file mode 100644
index 000000000000..18d807437632
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157d-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xd.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D eval daughter";
+ compatible = "st,stm32mp157d-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157d-ev1.dts b/arch/arm/boot/dts/stm32mp157d-ev1.dts
new file mode 100644
index 000000000000..f19ca6ada2d6
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157d-ev1.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157d-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157D eval daughter on eval mother";
+ compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ ethernet0 = &ethernet0;
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
new file mode 100644
index 000000000000..99dc3ed596bd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-dk2-a7-examples.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157f-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157F-DK2 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157f-dk2-a7-examples", "st,stm32mp157f-dk2", "st,stm32mp157";
+};
+
+&adc {
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+
+ adc1: adc@0 {
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@13 {
+ reg = <13>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+
+ adc2: adc@100 {
+ /* Set IRQ mode as example. DMA is the preferred mode, yet. */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&timers1 {
+ status = "okay";
+};
+
+&timers3 {
+ status = "okay";
+};
+
+&timers4 {
+ status = "okay";
+};
+
+&timers5 {
+ status = "okay";
+};
+
+&timers6 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
new file mode 100644
index 000000000000..38f8a1bbb8dd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-dk2-m4-examples.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157f-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157F-DK2 configured to run M4 examples";
+ compatible = "st,stm32mp157f-dk2-m4-examples", "st,stm32mp157f-dk2", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&m4_adc {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vrefbuf>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi4_pins_a>;
+ status = "okay";
+};
+
+&m4_timers1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm1_pins_a_ch1>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ status = "okay";
+};
+
+&m4_uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_uart7_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, RSVD)>;
+ };
+ };
+
+ m4_pwm1_pins_a_ch1: m4-pwm1-0-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, RSVD)>;
+ };
+ };
+};
+
+&timers1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-dk2.dts b/arch/arm/boot/dts/stm32mp157f-dk2.dts
new file mode 100644
index 000000000000..78391bed1351
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-dk2.dts
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xf.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
+#include <dt-bindings/rtc/rtc-stm32.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
+ compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
+
+ aliases {
+ serial3 = &usart2;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cryp1 {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel_otm8009a: panel-otm8009a@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ touchscreen@38 {
+ compatible = "focaltech,ft6236";
+ reg = <0x38>;
+ interrupts = <2 2>;
+ interrupt-parent = <&gpiof>;
+ interrupt-controller;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ panel = <&panel_otm8009a>;
+ vcc-supply = <&v3v3>;
+ iovcc-supply = <&v3v3>;
+ status = "okay";
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep1_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
+
+&rtc {
+ st,lsco = <RTC_OUT2_RMP>;
+ pinctrl-0 = <&rtc_out2_rmp_pins_a>;
+ pinctrl-names = "default";
+};
+
+/* Wifi */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpiod>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; /* WL_HOST_WAKE */
+ interrupt-names = "host-wake";
+ };
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
+ pinctrl-1 = <&usart2_sleep_pins_c>;
+ pinctrl-2 = <&usart2_idle_pins_c>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ vbat-supply = <&v3v3>;
+ vddio-supply = <&v3v3>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-ed1.dts b/arch/arm/boot/dts/stm32mp157f-ed1.dts
new file mode 100644
index 000000000000..bb3f8dfdcb8b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-ed1.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xf.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15xx-edx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157F eval daughter";
+ compatible = "st,stm32mp157f-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ gpu_reserved: gpu@f6000000 {
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ };
+};
+
+&cryp1 {
+ status = "okay";
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
new file mode 100644
index 000000000000..373307ff60a6
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-ev1-a7-examples.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157f-ev1.dts"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157F-EV1 configured to run Linux A7 examples";
+ compatible = "st,stm32mp157f-ev1-a7-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
+
+ test_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ status = "okay";
+ /* gpio needs vdd core in retention for wakeup */
+ power-domains = <&pd_core_ret>;
+
+ button-1 {
+ label = "PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ status = "okay";
+ wakeup-source;
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+};
+
+&dac {
+ status = "okay";
+};
+
+&timers2 {
+ status = "okay";
+};
+
+&timers8 {
+ status = "okay";
+};
+
+&timers12 {
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
new file mode 100644
index 000000000000..fd7be9c73b72
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-ev1-m4-examples.dts
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157f-ev1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157F-EV1 configured to run M4 examples";
+ compatible = "st,stm32mp157f-ev1-m4-examples", "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&dcmi {
+ status = "disabled";
+};
+
+&dma2 {
+ status = "disabled";
+};
+
+&dmamux1 {
+ dma-masters = <&dma1>;
+ dma-channels = <8>;
+};
+
+&fmc {
+ status = "disabled";
+};
+
+&i2c5 {
+ status = "disabled";
+};
+
+&m4_adc {
+ vref-supply = <&vdda>;
+ status = "okay";
+};
+
+&m4_crc2 {
+ status = "okay";
+};
+
+&m4_cryp2 {
+ status = "okay";
+};
+
+&m4_dac {
+ vref-supply = <&vdda>;
+ status = "okay";
+};
+
+&m4_dma2 {
+ status = "okay";
+};
+
+&m4_hash2 {
+ status = "okay";
+};
+
+&m4_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_i2c5_pins_a>;
+ status = "okay";
+};
+
+&m4_qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_qspi_clk_pins_a &m4_qspi_bk1_pins_a
+ &m4_qspi_bk2_pins_a>;
+ status = "okay";
+};
+
+&m4_rng2 {
+ status = "okay";
+};
+
+&m4_rproc {
+ m4_system_resources {
+ status = "okay";
+
+ /*
+ button {
+ compatible = "rproc-srm-dev";
+ interrupt-parent = <&gpioa>;
+ interrupts = <14 2>;
+ interrupt-names = "irq";
+ status = "okay";
+ };
+ */
+
+ m4_led: m4_led {
+ compatible = "rproc-srm-dev";
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_leds_orange_pins>;
+ status = "okay";
+ };
+ };
+};
+
+&m4_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi1_pins_a>;
+ status = "okay";
+};
+
+&m4_timers2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_pwm2_pins_a>;
+ status = "okay";
+};
+
+&m4_usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_usart3_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ m4_leds_orange_pins: m4-leds-orange-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 8, RSVD)>;
+ };
+ };
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&sai2b {
+ status = "disabled";
+};
+
+&sound {
+ status = "disabled";
+};
+
+&timers2 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157f-ev1.dts b/arch/arm/boot/dts/stm32mp157f-ev1.dts
new file mode 100644
index 000000000000..b831f04532fd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157f-ev1.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157f-ed1.dts"
+#include "stm32mp15xx-evx.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157F eval daughter on eval mother";
+ compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc LTDC_PX>;
+ status = "disabled";
+ };
+ };
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+ default-on;
+ status = "okay";
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel_dsi: panel-dsi@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ gt9147: goodix_ts@5d {
+ compatible = "goodix,gt9147";
+ reg = <0x5d>;
+ panel = <&panel_dsi>;
+ pinctrl-0 = <&goodix_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ };
+};
+
+&ltdc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xa.dtsi b/arch/arm/boot/dts/stm32mp15xa.dtsi
new file mode 100644
index 000000000000..5ed7e594f4cd
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xa.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&cpu0_opp_table {
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..71787e804f3a 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -4,14 +4,19 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
+#include "stm32mp15xa.dtsi"
+
/ {
soc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+ dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>,
+ <&mdma1 30 0x3 0x400808 0x0 0x0 0x0>;
+ dma-names = "in", "out";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/stm32mp15xd.dtsi b/arch/arm/boot/dts/stm32mp15xd.dtsi
new file mode 100644
index 000000000000..e2f8b1297c33
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xd.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&cpu0_opp_table {
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x2>;
+ opp-suspend;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu-crit {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_alert: cpu-alert {
+ temperature = <95000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 1 1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xf.dtsi b/arch/arm/boot/dts/stm32mp15xf.dtsi
new file mode 100644
index 000000000000..26989fae4739
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xf.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp15xd.dtsi"
+
+/ {
+ soc {
+ cryp1: cryp@54001000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54001000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+ dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>,
+ <&mdma1 30 0x3 0x400808 0x0 0x0 0x0>;
+ dma-names = "in", "out";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
index 8c41f819f776..dfaf71b9a5e0 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -82,15 +82,19 @@
status = "okay";
adc1: adc@0 {
- st,min-sample-time-nsecs = <5000>;
- st,adc-channels = <0>;
status = "okay";
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
};
adc2: adc@100 {
- st,adc-channels = <1>;
- st,min-sample-time-nsecs = <5000>;
status = "okay";
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
index d3375ad8c91f..d1e68cfd3664 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -114,15 +114,35 @@
status = "okay";
adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- st,min-sample-time-nsecs = <5000>;
status = "okay";
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
};
adc2: adc@100 {
- st,adc-channels = <0 1 2>;
- st,min-sample-time-nsecs = <5000>;
status = "okay";
+ channel@0 {
+ reg = <0>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 48beed0f1f30..58bb9eca86a0 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -4,10 +4,19 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
+#include "stm32mp15-m4-srm.dtsi"
+#include "stm32mp15-m4-srm-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -42,6 +51,12 @@
no-map;
};
+ mcu_rsc_table: mcu_rsc_table@10048000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
@@ -58,6 +73,11 @@
reg = <0xd4000000 0x4000000>;
no-map;
};
+
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
};
led {
@@ -70,9 +90,9 @@
};
};
- sound {
+ sound: sound {
compatible = "audio-graph-card";
- label = "STM32MP1-DK";
+ label = "STM32MP15-DK";
routing =
"Playback" , "MCLK",
"Capture" , "MCLK",
@@ -92,28 +112,39 @@
&adc {
pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ pinctrl-0 = <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
- status = "disabled";
+ status = "okay";
adc1: adc@0 {
+ status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
* Use arbitrary margin here (e.g. 5us).
*/
- st,min-sample-time-nsecs = <5000>;
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 6 13 18 19>;
- status = "okay";
+ channel@18 {
+ reg = <18>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@19 {
+ reg = <19>;
+ st,min-sample-time-ns = <5000>;
+ };
};
adc2: adc@100 {
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 2 6 18 19>;
- st,min-sample-time-nsecs = <5000>;
status = "okay";
+ /* USB Type-C CC1 & CC2 */
+ channel@18 {
+ reg = <18>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@19 {
+ reg = <19>;
+ st,min-sample-time-ns = <5000>;
+ };
};
};
@@ -124,10 +155,26 @@
status = "okay";
};
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
&crc1 {
status = "okay";
};
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
&dts {
status = "okay";
};
@@ -140,6 +187,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
@@ -273,7 +322,7 @@
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
@@ -382,21 +431,21 @@
regulator-always-on;
};
- bst_out: boost {
+ bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
- };
+ };
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- };
+ };
- vbus_sw: pwr_sw2 {
+ vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
- };
+ };
};
onkey {
@@ -469,11 +518,12 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
+ <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
+ wakeup-source;
status = "okay";
};
@@ -482,10 +532,6 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
-&rng1 {
- status = "okay";
-};
-
&rtc {
status = "okay";
};
@@ -501,8 +547,6 @@
sai2a: audio-controller@4400b004 {
#clock-cells = <0>;
dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
status = "okay";
sai2a_port: port {
@@ -560,6 +604,27 @@
status = "disabled";
};
+&spi4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi4_pins_b>;
+ pinctrl-1 = <&spi4_sleep_pins_b>;
+ status = "disabled";
+};
+
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&sram {
+ dma_pool: dma_pool@0 {
+ reg = <0x50000 0x10000>;
+ pool;
+ };
+};
+
&timers1 {
/* spare dmas for other usage */
/delete-property/dmas;
@@ -650,6 +715,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "okay";
};
@@ -658,6 +725,8 @@
pinctrl-0 = <&uart7_pins_c>;
pinctrl-1 = <&uart7_sleep_pins_c>;
pinctrl-2 = <&uart7_idle_pins_c>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
};
@@ -694,10 +763,36 @@
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active until all connected devices are suspended
+ * otherwise the hub will be powered off as soon as the v3v3 is disabled
+ * and it can disturb connected devices.
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&v3v3>;
+ };
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
};
&vrefbuf {
diff --git a/arch/arm/boot/dts/stm32mp15xx-edx.dtsi b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi
new file mode 100644
index 000000000000..014ce3863d3e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-edx.dtsi
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp15-m4-srm.dtsi"
+#include "stm32mp15-m4-srm-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xC0000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcu_rsc_table: mcu_rsc_table@10048000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ optee@fe000000 {
+ reg = <0xfe000000 0x2000000>;
+ no-map;
+ };
+ };
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led-blue {
+ label = "heartbeat";
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&adc {
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
+ pinctrl-0 = <&adc1_in6_pins_a>;
+ pinctrl-names = "default";
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ adc1: adc@0 {
+ status = "okay";
+ channel@0 {
+ reg = <0>;
+ /* 16.5 ck_cycles sampling time */
+ st,min-sample-time-ns = <400>;
+ };
+ channel@1 {
+ reg = <1>;
+ st,min-sample-time-ns = <400>;
+ };
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <400>;
+ };
+ };
+};
+
+&cpu0{
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+ cpu-supply = <&vddcore>;
+};
+
+&crc1 {
+ status = "okay";
+};
+
+&dac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ dac1: dac@1 {
+ status = "okay";
+ };
+ dac2: dac@2 {
+ status = "okay";
+ };
+};
+
+&dma1 {
+ sram = <&dma_pool>;
+};
+
+&dma2 {
+ sram = <&dma_pool>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&hash1 {
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ wakeup-source;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
+&sram {
+ dma_pool: dma_pool@0 {
+ reg = <0x50000 0x10000>;
+ pool;
+ };
+};
+
+&timers6 {
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ timer@5 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&usbotg_hs {
+ vbus-supply = <&vbus_otg>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-evx.dtsi b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi
new file mode 100644
index 000000000000..fe8a8dfc46b8
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-evx.dtsi
@@ -0,0 +1,698 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/stm32-hdp.h>
+
+/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ serial1 = &usart3;
+ };
+
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ joystick {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&joystick_pins>;
+ pinctrl-names = "default";
+ button-0 {
+ label = "JoySel";
+ linux,code = <KEY_ENTER>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-1 {
+ label = "JoyDown";
+ linux,code = <KEY_DOWN>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-2 {
+ label = "JoyLeft";
+ linux,code = <KEY_LEFT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-3 {
+ label = "JoyRight";
+ linux,code = <KEY_RIGHT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-4 {
+ label = "JoyUp";
+ linux,code = <KEY_UP>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+
+ spdif_out_port: port {
+ spdif_out_endpoint: endpoint {
+ remote-endpoint = <&sai4a_endpoint>;
+ };
+ };
+ };
+
+ spdif_in: spdif-in {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dir";
+ status = "okay";
+
+ spdif_in_port: port {
+ spdif_in_endpoint: endpoint {
+ remote-endpoint = <&spdifrx_endpoint>;
+ };
+ };
+ };
+
+ sound: sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP15-EV";
+ routing =
+ "AIF1CLK" , "MCLK1",
+ "AIF2CLK" , "MCLK1",
+ "IN1LN" , "MICBIAS2",
+ "DMIC2DAT" , "MICBIAS1",
+ "DMIC1DAT" , "MICBIAS1";
+ dais = <&sai2a_port &sai2b_port &sai4a_port &spdifrx_port
+ &dfsdm0_port &dfsdm1_port &dfsdm2_port &dfsdm3_port>;
+ status = "okay";
+ };
+
+ dmic0: dmic-0 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic0";
+ status = "okay";
+
+ port {
+ dmic0_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint0>;
+ };
+ };
+ };
+
+ dmic1: dmic-1 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic1";
+ status = "okay";
+
+ port {
+ dmic1_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint1>;
+ };
+ };
+ };
+
+ dmic2: dmic-2 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic2";
+ status = "okay";
+
+ port {
+ dmic2_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint2>;
+ };
+ };
+ };
+
+ dmic3: dmic-3 {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "dmic3";
+ status = "okay";
+
+ port {
+ dmic3_endpoint: endpoint {
+ remote-endpoint = <&dfsdm_endpoint3>;
+ };
+ };
+ };
+
+};
+
+&cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cec_pins_a>;
+ status = "okay";
+};
+
+&dcmi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_a>;
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov5640_0>;
+ bus-type = <5>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ pclk-max-frequency = <77000000>;
+ };
+ };
+};
+
+&dfsdm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dfsdm_clkout_pins_a
+ &dfsdm_data1_pins_a &dfsdm_data3_pins_a>;
+ pinctrl-1 = <&dfsdm_clkout_sleep_pins_a
+ &dfsdm_data1_sleep_pins_a &dfsdm_data3_sleep_pins_a>;
+ spi-max-frequency = <2048000>;
+
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+ clock-names = "dfsdm", "audio";
+ status = "okay";
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <3>;
+ st,adc-channel-names = "dmic_u1";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm0: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm0 0>;
+ status = "okay";
+
+ dfsdm0_port: port {
+ dfsdm_endpoint0: endpoint {
+ remote-endpoint = <&dmic0_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <0>;
+ st,adc-channel-names = "dmic_u2";
+ st,adc-channel-types = "SPI_F";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ st,adc-alt-channel = <1>;
+ status = "okay";
+
+ asoc_pdm1: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm1 0>;
+ status = "okay";
+
+ dfsdm1_port: port {
+ dfsdm_endpoint1: endpoint {
+ remote-endpoint = <&dmic1_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm2: filter@2 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <2>;
+ st,adc-channel-names = "dmic_u3";
+ st,adc-channel-types = "SPI_F";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,adc-alt-channel = <1>;
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm2: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm2 0>;
+ status = "okay";
+
+ dfsdm2_port: port {
+ dfsdm_endpoint2: endpoint {
+ remote-endpoint = <&dmic2_endpoint>;
+ };
+ };
+ };
+ };
+
+ dfsdm3: filter@3 {
+ compatible = "st,stm32-dfsdm-dmic";
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic_u4";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <3>;
+ status = "okay";
+
+ asoc_pdm3: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm3 0>;
+ status = "okay";
+
+ dfsdm3_port: port {
+ dfsdm_endpoint3: endpoint {
+ remote-endpoint = <&dmic3_endpoint>;
+ };
+ };
+ };
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+ pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&fmc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&fmc_pins_a>;
+ pinctrl-1 = <&fmc_sleep_pins_a>;
+ status = "okay";
+
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&hdp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdp0_pins_a &hdp6_pins_a &hdp7_pins_a>;
+ pinctrl-1 = <&hdp0_pins_sleep_a &hdp6_pins_sleep_a &hdp7_pins_sleep_a>;
+ status = "disabled";
+
+ muxing-hdp = <(STM32_HDP(0, HDP0_GPOVAL_0) |
+ STM32_HDP(6, HDP6_GPOVAL_6) |
+ STM32_HDP(7, HDP7_GPOVAL_7))>;
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-1 = <&i2c2_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ wm8994: wm8994@1b {
+ compatible = "wlf,wm8994";
+ #sound-dai-cells = <0>;
+ reg = <0x1b>;
+ status = "okay";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ DBVDD-supply = <&vdd>;
+ SPKVDD1-supply = <&vdd>;
+ SPKVDD2-supply = <&vdd>;
+ AVDD2-supply = <&v1v8>;
+ CPVDD-supply = <&v1v8>;
+
+ wlf,ldoena-always-driven;
+
+ clocks = <&sai2a>;
+ clock-names = "MCLK1";
+
+ wlf,gpio-cfg = <0x8101 0xa100 0xa100 0xa100 0xa101 0xa101 0xa100 0xa101 0xa101 0xa101 0xa101>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wm8994_tx_port: port@0 {
+ reg = <0>;
+ wm8994_tx_endpoint: endpoint {
+ remote-endpoint = <&sai2a_endpoint>;
+ };
+ };
+
+ wm8994_rx_port: port@1 {
+ reg = <1>;
+ wm8994_rx_endpoint: endpoint {
+ remote-endpoint = <&sai2b_endpoint>;
+ };
+ };
+ };
+ };
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&v2v8>;
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ rotation = <180>;
+ status = "okay";
+
+ port {
+ ov5640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ pclk-max-frequency = <77000000>;
+ };
+ };
+ };
+
+ stmfx: stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+ vdd-supply = <&v3v3>;
+
+ stmfx_pinctrl: pinctrl {
+ compatible = "st,stmfx-0300-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ goodix_pins: goodix {
+ pins = "gpio14";
+ bias-pull-down;
+ };
+
+ joystick_pins: joystick-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ bias-pull-down;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pmic: stpmic@33 {
+ regulators {
+ v1v8: ldo6 {
+ regulator-enable-ramp-delay = <300000>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a
+ &qspi_bk2_pins_a
+ &qspi_cs2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a
+ &qspi_bk2_sleep_pins_a
+ &qspi_cs2_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash1: mx66l51235l@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_a>;
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_a>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&wm8994_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+ };
+
+ sai2b: audio-controller@4400b024 {
+ dma-names = "rx";
+ clocks = <&rcc SAI2_K>, <&sai2a>;
+ clock-names = "sai_ck", "MCLK";
+ status = "okay";
+
+ sai2b_port: port {
+ sai2b_endpoint: endpoint {
+ remote-endpoint = <&wm8994_rx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+ };
+};
+
+&sai4 {
+ clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+
+ sai4a: audio-controller@50027004 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai4a_pins_a>;
+ pinctrl-1 = <&sai4a_sleep_pins_a>;
+ dma-names = "tx";
+ st,iec60958;
+ status = "okay";
+
+ sai4a_port: port {
+ sai4a_endpoint: endpoint {
+ remote-endpoint = <&spdif_out_endpoint>;
+ };
+ };
+ };
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
+&spdifrx {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spdifrx_pins_a>;
+ pinctrl-1 = <&spdifrx_sleep_pins_a>;
+ status = "okay";
+
+ spdifrx_port: port {
+ spdifrx_endpoint: endpoint {
+ remote-endpoint = <&spdif_in_endpoint>;
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_a>;
+ pinctrl-1 = <&spi1_sleep_pins_a>;
+ status = "disabled";
+};
+
+&timers2 {
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@1 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_b>;
+ pinctrl-1 = <&usart3_sleep_pins_b>;
+ pinctrl-2 = <&usart3_idle_pins_b>;
+ /*
+ * HW flow control USART3_RTS is optional, and isn't default wired to
+ * the connector. SB23 needs to be soldered in order to use it, and R77
+ * (ETH_CLK) should be removed.
+ */
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+
+ /*
+ * Hack to keep hub active until all connected devices are suspended
+ * otherwise the hub will be powered off as soon as the v3v3 is disabled
+ * and it can disturb connected devices.
+ */
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&v3v3>;
+ };
+};
+
+&usbphyc_port1 {
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+};
--
2.17.1
Reference in New Issue View Git Blame Copy Permalink