118 lines
3.7 KiB
Diff
118 lines
3.7 KiB
Diff
From ad6a40bb66269882f124e9c2b6b106cca3fb8abc Mon Sep 17 00:00:00 2001
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From: Lionel Vitte <lionel.vitte@st.com>
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Date: Mon, 18 Oct 2021 17:10:51 +0200
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Subject: [PATCH 08/11] ARM v2020.10-stm32mp-r2 BOARD
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---
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board/dhelectronics/dh_stm32mp1/board.c | 7 ++-----
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board/raspberrypi/rpi/rpi.c | 2 +-
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board/st/stm32mp1/stm32mp1.c | 13 ++++++++-----
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3 files changed, 11 insertions(+), 11 deletions(-)
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diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
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index c9abe3cc6d..77f2730a3f 100644
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--- a/board/dhelectronics/dh_stm32mp1/board.c
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+++ b/board/dhelectronics/dh_stm32mp1/board.c
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@@ -551,9 +551,6 @@ int board_init(void)
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/* address of boot parameters */
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gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
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- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
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- gpio_hog_probe_all();
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-
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board_key_check();
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#ifdef CONFIG_DM_REGULATOR
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@@ -618,11 +615,11 @@ int board_interface_eth_init(struct udevice *dev,
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bool eth_ref_clk_sel_reg = false;
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/* Gigabit Ethernet 125MHz clock selection. */
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- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
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+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
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/* Ethernet 50Mhz RMII clock selection */
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eth_ref_clk_sel_reg =
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- dev_read_bool(dev, "st,eth_ref_clk_sel");
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+ dev_read_bool(dev, "st,eth-ref-clk-sel");
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
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index 6b1fa5fc14..f25b2aa219 100644
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--- a/board/raspberrypi/rpi/rpi.c
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+++ b/board/raspberrypi/rpi/rpi.c
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@@ -485,7 +485,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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* should be more intelligent, and e.g. only do this if no enabled DT
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* node exists for the "real" graphics driver.
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*/
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- lcd_dt_simplefb_add_node(blob);
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+ fdt_simplefb_add_node(blob);
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#ifdef CONFIG_EFI_LOADER
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/* Reserve the spin table */
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diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
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index 9a02e14ba5..42979d80f5 100644
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--- a/board/st/stm32mp1/stm32mp1.c
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+++ b/board/st/stm32mp1/stm32mp1.c
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@@ -10,6 +10,7 @@
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#include <dm.h>
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#include <env.h>
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#include <env_internal.h>
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+#include <fdt_simplefb.h>
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#include <fdt_support.h>
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#include <g_dnl.h>
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#include <generic-phy.h>
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@@ -155,6 +156,7 @@ static void board_key_check(void)
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debug("%s: could not find a /config/st,fastboot-gpios\n",
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__func__);
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} else {
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+ udelay(20);
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if (dm_gpio_get_value(&gpio)) {
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puts("Fastboot key pressed, ");
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boot_mode = BOOT_FASTBOOT;
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@@ -169,6 +171,7 @@ static void board_key_check(void)
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debug("%s: could not find a /config/st,stm32prog-gpios\n",
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__func__);
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} else {
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+ udelay(20);
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if (dm_gpio_get_value(&gpio)) {
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puts("STM32Programmer key pressed, ");
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boot_mode = BOOT_STM32PROG;
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@@ -649,9 +652,6 @@ int board_init(void)
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/* address of boot parameters */
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gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
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- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
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- gpio_hog_probe_all();
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-
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board_key_check();
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if (board_is_ev1())
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@@ -739,11 +739,11 @@ int board_interface_eth_init(struct udevice *dev,
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bool eth_ref_clk_sel_reg = false;
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/* Gigabit Ethernet 125MHz clock selection. */
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- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
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+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
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/* Ethernet 50Mhz RMII clock selection */
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eth_ref_clk_sel_reg =
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- dev_read_bool(dev, "st,eth_ref_clk_sel");
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+ dev_read_bool(dev, "st,eth-ref-clk-sel");
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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@@ -886,6 +886,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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+ if (CONFIG_IS_ENABLED(FDT_SIMPLEFB))
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+ fdt_simplefb_add_node_and_mem_rsv(blob);
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+
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return 0;
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}
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#endif
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--
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2.25.1
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