meta-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.10-stm32mp-r...

118 lines
3.7 KiB
Diff

From ad6a40bb66269882f124e9c2b6b106cca3fb8abc Mon Sep 17 00:00:00 2001
From: Lionel Vitte <lionel.vitte@st.com>
Date: Mon, 18 Oct 2021 17:10:51 +0200
Subject: [PATCH 08/11] ARM v2020.10-stm32mp-r2 BOARD
---
board/dhelectronics/dh_stm32mp1/board.c | 7 ++-----
board/raspberrypi/rpi/rpi.c | 2 +-
board/st/stm32mp1/stm32mp1.c | 13 ++++++++-----
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index c9abe3cc6d..77f2730a3f 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -551,9 +551,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
#ifdef CONFIG_DM_REGULATOR
@@ -618,11 +615,11 @@ int board_interface_eth_init(struct udevice *dev,
bool eth_ref_clk_sel_reg = false;
/* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
/* Ethernet 50Mhz RMII clock selection */
eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth_ref_clk_sel");
+ dev_read_bool(dev, "st,eth-ref-clk-sel");
syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 6b1fa5fc14..f25b2aa219 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -485,7 +485,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
* should be more intelligent, and e.g. only do this if no enabled DT
* node exists for the "real" graphics driver.
*/
- lcd_dt_simplefb_add_node(blob);
+ fdt_simplefb_add_node(blob);
#ifdef CONFIG_EFI_LOADER
/* Reserve the spin table */
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 9a02e14ba5..42979d80f5 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <env.h>
#include <env_internal.h>
+#include <fdt_simplefb.h>
#include <fdt_support.h>
#include <g_dnl.h>
#include <generic-phy.h>
@@ -155,6 +156,7 @@ static void board_key_check(void)
debug("%s: could not find a /config/st,fastboot-gpios\n",
__func__);
} else {
+ udelay(20);
if (dm_gpio_get_value(&gpio)) {
puts("Fastboot key pressed, ");
boot_mode = BOOT_FASTBOOT;
@@ -169,6 +171,7 @@ static void board_key_check(void)
debug("%s: could not find a /config/st,stm32prog-gpios\n",
__func__);
} else {
+ udelay(20);
if (dm_gpio_get_value(&gpio)) {
puts("STM32Programmer key pressed, ");
boot_mode = BOOT_STM32PROG;
@@ -649,9 +652,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
if (board_is_ev1())
@@ -739,11 +739,11 @@ int board_interface_eth_init(struct udevice *dev,
bool eth_ref_clk_sel_reg = false;
/* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
/* Ethernet 50Mhz RMII clock selection */
eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth_ref_clk_sel");
+ dev_read_bool(dev, "st,eth-ref-clk-sel");
syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
@@ -886,6 +886,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ if (CONFIG_IS_ENABLED(FDT_SIMPLEFB))
+ fdt_simplefb_add_node_and_mem_rsv(blob);
+
return 0;
}
#endif
--
2.25.1