238 lines
6.9 KiB
Diff
238 lines
6.9 KiB
Diff
From 7b129c9db71e9dcb515a4585861898b6a3644f1b Mon Sep 17 00:00:00 2001
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From: Romuald JEANNE <romuald.jeanne@st.com>
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Date: Thu, 3 Nov 2022 15:23:32 +0100
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Subject: [PATCH 03/22] v5.15-stm32mp-r2 CPUFREQ
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Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
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---
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.../bindings/cpufreq/stm32-cpufreq.txt | 61 +++++++++++
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drivers/cpufreq/Kconfig.arm | 7 ++
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drivers/cpufreq/Makefile | 1 +
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/stm32-cpufreq.c | 103 ++++++++++++++++++
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5 files changed, 173 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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create mode 100644 drivers/cpufreq/stm32-cpufreq.c
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diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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new file mode 100644
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index 000000000000..1292eb2612a0
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
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@@ -0,0 +1,61 @@
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+STM32 CPUFreq and OPP bindings
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+==============================
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+
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+STM32 CPUFreq driver needs to read chip information from the SoC to list
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+available OPPs. Then it depends on cpufreq-dt bindings.
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+
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+Required properties:
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+--------------------
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+- clocks: Phandle to the cpu clock "cpu".
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+- clocks-name: Should contain "cpu".
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+- nvmem-cells: Phandle to nvmem cell that contains "part_number".
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+- nvmem-cell-names: Must be "part_number".
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+- operating-points-v2: Phandle to operating points table. See ../power/opp.txt
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+ for more details.
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+
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+Optional properties:
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+--------------------
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+See cpufreq-dt.txt for optional properties.
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+
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+Examples:
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+---------
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <0>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ nvmem-cells = <&part_number_otp>;
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+ nvmem-cell-names = "part_number";
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+ };
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+
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+ cpu1: cpu@1 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <1>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ };
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+ };
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+
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+ cpu0_opp_table: cpu0-opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-650000000 {
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+ opp-hz = /bits/ 64 <650000000>;
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+ opp-microvolt = <1200000>;
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+ opp-supported-hw = <0x1>;
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+ };
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1350000>;
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+ opp-supported-hw = <0x2>;
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+ };
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+ };
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diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
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index 954749afb5fe..eac08e90768c 100644
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--- a/drivers/cpufreq/Kconfig.arm
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+++ b/drivers/cpufreq/Kconfig.arm
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@@ -311,6 +311,13 @@ config ARM_STI_CPUFREQ
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this config option if you wish to add CPUFreq support for STi based
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SoCs.
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+config ARM_STM32_CPUFREQ
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+ tristate "STM32 CPUFreq support"
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+ depends on MACH_STM32MP157
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+ default y
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+ help
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+ This adds the CPUFreq driver support for STM32 MPU SOCs.
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+
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config ARM_TEGRA20_CPUFREQ
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tristate "Tegra20/30 CPUFreq support"
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depends on ARCH_TEGRA && CPUFREQ_DT
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diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
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index 48ee5859030c..d34de1b927bf 100644
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--- a/drivers/cpufreq/Makefile
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+++ b/drivers/cpufreq/Makefile
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@@ -78,6 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ) += scmi-cpufreq.o
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obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o
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obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
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obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o
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+obj-$(CONFIG_ARM_STM32_CPUFREQ) += stm32-cpufreq.o
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obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
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obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
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obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
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diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
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index ca1d103ec449..f205e6e9703e 100644
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -150,6 +150,7 @@ static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "st,stih407", },
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{ .compatible = "st,stih410", },
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{ .compatible = "st,stih418", },
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+ { .compatible = "st,stm32mp157", },
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{ .compatible = "ti,am33xx", },
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{ .compatible = "ti,am43", },
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diff --git a/drivers/cpufreq/stm32-cpufreq.c b/drivers/cpufreq/stm32-cpufreq.c
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new file mode 100644
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index 000000000000..d7b1b16ea1d1
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--- /dev/null
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+++ b/drivers/cpufreq/stm32-cpufreq.c
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@@ -0,0 +1,103 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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+ * Authors: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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+ */
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+
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+#include <linux/cpu.h>
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+#include <linux/cpufreq.h>
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/nvmem-consumer.h>
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+#include <linux/of_platform.h>
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+#include <linux/pm_opp.h>
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+
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+struct stm32_cpufreq_priv {
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+ struct opp_table *opps;
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+ struct platform_device *cpufreq_dt_pdev;
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+};
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+
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+static int stm32_cpufreq_probe(struct platform_device *pdev)
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+{
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+ struct stm32_cpufreq_priv *priv;
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+ struct device_node *opp_node;
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+ struct device *cpu_dev;
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+ u8 part_number;
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+ u32 supported_hw;
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+ int ret;
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+
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+ cpu_dev = get_cpu_device(0);
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+ if (!cpu_dev) {
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+ dev_err(&pdev->dev, "failed to get cpu0 device\n");
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+ return -ENODEV;
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+ }
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+ opp_node = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
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+ if (!opp_node) {
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+ dev_err(&pdev->dev, "OPP-v2 not supported\n");
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+ return -ENODEV;
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+ }
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+
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+ /* Get chip info */
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+ ret = nvmem_cell_read_u8(cpu_dev, "part_number", &part_number);
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+ if (ret) {
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(&pdev->dev, "Failed to get chip info: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ supported_hw = BIT((part_number & 0x80) >> 7);
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+
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+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ priv->opps = dev_pm_opp_set_supported_hw(cpu_dev, &supported_hw, 1);
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+ if (IS_ERR(priv->opps)) {
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+ ret = PTR_ERR(priv->opps);
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(&pdev->dev, "Failed to set supported opp: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ of_node_put(opp_node);
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+ priv->cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt",
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+ -1, NULL, 0);
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+
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+ platform_set_drvdata(pdev, priv);
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+
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+ return 0;
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+}
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+
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+static int stm32_cpufreq_remove(struct platform_device *pdev)
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+{
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+ struct stm32_cpufreq_priv *priv = platform_get_drvdata(pdev);
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+
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+ platform_device_unregister(priv->cpufreq_dt_pdev);
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+ dev_pm_opp_put_supported_hw(priv->opps);
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+
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+ return 0;
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+}
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+
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+static int stm32_cpufreq_init(void)
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+{
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+ platform_device_register_simple("stm32-cpufreq", -1, NULL, 0);
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+
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+ return 0;
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+}
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+module_init(stm32_cpufreq_init);
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+
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+static struct platform_driver stm32_cpufreq_platdrv = {
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+ .driver = {
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+ .name = "stm32-cpufreq",
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+ },
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+ .probe = stm32_cpufreq_probe,
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+ .remove = stm32_cpufreq_remove,
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+};
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+module_platform_driver(stm32_cpufreq_platdrv);
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+
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+MODULE_DESCRIPTION("STM32 CPU freq driver");
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+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
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+MODULE_LICENSE("GPL v2");
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--
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2.17.1
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