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U-BOOT-STM32MP: update to v2020.01-stm32mp-r2 

Change-Id: I72aa61336719bb899c5c2b24562460c2f70d373a
This commit is contained in:
Christophe Priouzeau 2020-10-27 12:17:44 +01:00 committed by Bernard PUEL
parent 562904550d
commit 6852cc81f2
6 changed files with 5631 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
recipes-bsp/u-boot/u-boot-stm32mp-common_2020.01.inc
View File

@ -21,11 +21,17 @@ SRC_URI += "\
file://0004-ARM-v2020.01-stm32mp-r1-DEVICETREE.patch \
file://0005-ARM-v2020.01-stm32mp-r1-CONFIG.patch \
\
file://0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch \
file://0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch \
file://0008-ARM-v2020.01-stm32mp-r2-BOARD.patch \
file://0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch \
file://0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch \
\
file://0099-Add-external-var-to-allow-build-of-new-devicetree-fi.patch \
"
U_BOOT_VERSION = "2020.01"
PV = "${U_BOOT_VERSION}"
PV = "${U_BOOT_VERSION}.r2"
S = "${WORKDIR}/git"
@ -35,7 +41,7 @@ S = "${WORKDIR}/git"
BBCLASSEXTEND = "devupstream:target"
SRC_URI_class-devupstream = "git://github.com/STMicroelectronics/u-boot.git;protocol=https;branch=v${U_BOOT_VERSION}-stm32mp"
SRCREV_class-devupstream = "764fc8b2591139fb6a729516ccb4f9836b310d63"
SRCREV_class-devupstream = "7d786860495d4d121a13f949cdca589ebfb281bf"
# ---------------------------------
# Configure default preference to manage dynamic selection between tarball and github

778
recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2020.01-stm32mp-r2-DEVICETREE.patch Normal file
View File

@ -0,0 +1,778 @@
From 1f4593f966441e5ea3477f974eea8043b75c003c Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@st.com>
Date: Tue, 27 Oct 2020 11:47:53 +0100
Subject: [PATCH 06/10] ARM-v2020.01-stm32mp-r2-DEVICETREE
---
arch/arm/dts/stm32mp15-no-scmi.dtsi | 11 ++--
arch/arm/dts/stm32mp15-pinctrl.dtsi | 8 +--
arch/arm/dts/stm32mp15-u-boot.dtsi | 57 +++++++++++------
arch/arm/dts/stm32mp151.dtsi | 81 +++++++++++++++---------
arch/arm/dts/stm32mp157a-avenger96.dts | 3 +
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 15 +++++
arch/arm/dts/stm32mp157a-dk1.dts | 9 ---
arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi | 14 ++++
arch/arm/dts/stm32mp157a-ed1.dts | 9 ---
arch/arm/dts/stm32mp157c-dk2.dts | 13 ----
arch/arm/dts/stm32mp157c-ed1.dts | 9 ---
arch/arm/dts/stm32mp157d-dk1.dts | 9 ---
arch/arm/dts/stm32mp157d-ed1.dts | 9 ---
arch/arm/dts/stm32mp157f-dk2.dts | 14 ----
arch/arm/dts/stm32mp157f-ed1.dts | 9 ---
arch/arm/dts/stm32mp15xd.dtsi | 2 +-
arch/arm/dts/stm32mp15xx-dkx.dtsi | 2 +
arch/arm/dts/stm32mp15xx-edx.dtsi | 1 -
arch/arm/dts/stm32mp15xx-evx.dtsi | 25 +++++---
19 files changed, 147 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi
index 3bb96ab8a2..b58b4b0526 100644
--- a/arch/arm/dts/stm32mp15-no-scmi.dtsi
+++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi
@@ -61,11 +61,15 @@
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
};
+
+ dsi: dsi@5a000000 {
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ };
};
mlahb {
m4_rproc: m4@10000000 {
- resets = <&rcc MCU_R>;
+ resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>;
m4_system_resources {
m4_cec: cec@40016000 {
@@ -100,10 +104,6 @@
clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
};
-&dsi {
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
-};
-
&gpioz {
clocks = <&rcc GPIOZ>;
};
@@ -153,5 +153,4 @@
&usart1 {
clocks = <&rcc USART1_K>;
- resets = <&rcc USART1_R>;
};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index b8e82adeca..9d51384c18 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1225,7 +1225,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1235,7 +1235,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1329,7 +1329,7 @@
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
+ bias-pull-up;
};
};
@@ -1341,7 +1341,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
+ bias-pull-up;
};
};
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index 823e281906..02f9d836ec 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -164,6 +164,38 @@
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
+&usart1 {
+ resets = <&scmi0_reset RST_SCMI0_USART1>;
+};
+
+&usart2 {
+ resets = <&rcc USART2_R>;
+};
+
+&usart3 {
+ resets = <&rcc USART3_R>;
+};
+
+&uart4 {
+ resets = <&rcc UART4_R>;
+};
+
+&uart5 {
+ resets = <&rcc UART5_R>;
+};
+
+&usart6 {
+ resets = <&rcc USART6_R>;
+};
+
+&uart7 {
+ resets = <&rcc UART7_R>;
+};
+
+&uart8{
+ resets = <&rcc UART8_R>;
+};
+
/* NO MORE USE SCMI SUPPORT for BASIC boot chain */
#ifndef CONFIG_STM32MP1_TRUSTED
@@ -172,26 +204,6 @@
/ {
clocks {
u-boot,dm-pre-reloc;
-
- clk_hse: clk-hse {
- u-boot,dm-pre-reloc;
- };
-
- clk_hsi: clk-hsi {
- u-boot,dm-pre-reloc;
- };
-
- clk_lse: clk-lse {
- u-boot,dm-pre-reloc;
- };
-
- clk_lsi: clk-lsi {
- u-boot,dm-pre-reloc;
- };
-
- clk_csi: clk-csi {
- u-boot,dm-pre-reloc;
- };
};
reboot {
@@ -228,4 +240,9 @@
u-boot,dm-spl;
};
};
+
+&usart1 {
+ resets = <&rcc USART1_R>;
+};
+
#endif /* CONFIG_STM32MP1_TRUSTED */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index c516e2ed03..f0211917bb 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -106,12 +106,6 @@
#clock-cells = <1>;
};
};
-
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- status = "disabled";
- };
};
psci {
@@ -444,8 +438,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -536,7 +533,6 @@
reg = <0x4000e000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
- resets = <&rcc USART2_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 43 0x400 0x5>,
@@ -550,7 +546,6 @@
reg = <0x4000f000 0x400>;
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
- resets = <&rcc USART3_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 45 0x400 0x5>,
@@ -564,7 +559,6 @@
reg = <0x40010000 0x400>;
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
- resets = <&rcc UART4_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 63 0x400 0x5>,
@@ -578,7 +572,6 @@
reg = <0x40011000 0x400>;
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
- resets = <&rcc UART5_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 65 0x400 0x5>,
@@ -701,7 +694,6 @@
reg = <0x40018000 0x400>;
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
- resets = <&rcc UART7_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 79 0x400 0x5>,
@@ -715,7 +707,6 @@
reg = <0x40019000 0x400>;
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
- resets = <&rcc UART8_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 81 0x400 0x5>,
@@ -801,7 +792,6 @@
reg = <0x44003000 0x400>;
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
- resets = <&rcc USART6_R>;
wakeup-source;
power-domains = <&pd_core>;
dmas = <&dmamux1 71 0x400 0x5>,
@@ -1365,8 +1355,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1392,8 +1385,11 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1412,8 +1408,11 @@
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1426,8 +1425,11 @@
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
+ power-domains = <&pd_core>;
+ wakeup-source;
status = "disabled";
pwm {
@@ -1526,23 +1528,38 @@
dma-requests = <48>;
};
- fmc: nand-controller@58002000 {
- compatible = "st,stm32mp15-fmc2";
- reg = <0x58002000 0x1000>,
- <0x80000000 0x1000>,
- <0x88010000 0x1000>,
- <0x88020000 0x1000>,
- <0x81000000 0x1000>,
- <0x89010000 0x1000>,
- <0x89020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
};
qspi: spi@58003000 {
@@ -1703,7 +1720,6 @@
reg = <0x5c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi0_clk CK_SCMI0_USART1>;
- resets = <&scmi0_reset RST_SCMI0_USART1>;
wakeup-source;
power-domains = <&pd_core>;
status = "disabled";
@@ -1768,6 +1784,9 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac_address: mac@e4 {
+ reg = <0xe4 0x6>;
+ };
};
i2c6: i2c@5c009000 {
@@ -1980,9 +1999,9 @@
reg = <0x10000000 0x40000>,
<0x30000000 0x40000>,
<0x38000000 0x10000>;
- resets = <&scmi0_reset RST_SCMI0_MCU>;
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
+ resets = <&scmi0_reset RST_SCMI0_MCU>,
+ <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>;
+ reset-names = "mcu_rst", "hold_boot";
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
index 941963ccc2..75efd45179 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -92,6 +92,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+
phy0: ethernet-phy@7 {
reg = <7>;
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 62d7062885..0edcbe9620 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -21,6 +21,7 @@
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
+
led {
red {
label = "error";
@@ -29,6 +30,20 @@
status = "okay";
};
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ optee@de000000 {
+ reg = <0xde000000 0x02000000>;
+ no-map;
+ };
+ };
};
&adc {
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index baff3f6944..1f265fed2c 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -31,14 +31,5 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
index 0f163bc566..23affacad0 100644
--- a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
@@ -30,6 +30,20 @@
status = "okay";
};
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ optee@fe000000 {
+ reg = <0xfe000000 0x02000000>;
+ no-map;
+ };
+ };
};
#ifndef CONFIG_STM32MP1_TRUSTED
diff --git a/arch/arm/dts/stm32mp157a-ed1.dts b/arch/arm/dts/stm32mp157a-ed1.dts
index 5dca956843..e7fad7d394 100644
--- a/arch/arm/dts/stm32mp157a-ed1.dts
+++ b/arch/arm/dts/stm32mp157a-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -46,7 +41,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index a7d5e86a14..ba1d15de2f 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -34,11 +34,6 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
wifi_pwrseq: wifi-pwrseq {
@@ -174,11 +169,3 @@
vddio-supply = <&v3v3>;
};
};
-
-&optee_memory {
- status = "okay";
-};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index bf2d7e7b7d..16ddc0e9f8 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -50,7 +45,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
index c7d65a65e4..aa98012fd3 100644
--- a/arch/arm/dts/stm32mp157d-dk1.dts
+++ b/arch/arm/dts/stm32mp157d-dk1.dts
@@ -31,14 +31,5 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- };
};
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157d-ed1.dts b/arch/arm/dts/stm32mp157d-ed1.dts
index ee55ac8f33..aaf9adf51c 100644
--- a/arch/arm/dts/stm32mp157d-ed1.dts
+++ b/arch/arm/dts/stm32mp157d-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@fe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -46,7 +41,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts
index b57db3037d..1123d0f3ed 100644
--- a/arch/arm/dts/stm32mp157f-dk2.dts
+++ b/arch/arm/dts/stm32mp157f-dk2.dts
@@ -34,12 +34,6 @@
reg = <0xda000000 0x4000000>;
no-map;
};
-
- optee_memory: optee@0xde000000 {
- reg = <0xde000000 0x02000000>;
- no-map;
- status = "disabled";
- };
};
wifi_pwrseq: wifi-pwrseq {
@@ -175,11 +169,3 @@
vddio-supply = <&v3v3>;
};
};
-
-&optee_memory {
- status = "okay";
-};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157f-ed1.dts b/arch/arm/dts/stm32mp157f-ed1.dts
index 65380693c8..7ddb96a0ef 100644
--- a/arch/arm/dts/stm32mp157f-ed1.dts
+++ b/arch/arm/dts/stm32mp157f-ed1.dts
@@ -30,11 +30,6 @@
reg = <0xf6000000 0x8000000>;
no-map;
};
-
- optee_memory: optee@0xfe000000 {
- reg = <0xfe000000 0x02000000>;
- no-map;
- };
};
};
@@ -50,7 +45,3 @@
contiguous-area = <&gpu_reserved>;
status = "okay";
};
-
-&optee {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi
index faa039ea24..e2f8b1297c 100644
--- a/arch/arm/dts/stm32mp15xd.dtsi
+++ b/arch/arm/dts/stm32mp15xd.dtsi
@@ -27,7 +27,7 @@
};
cpu_alert: cpu-alert {
- temperature = <950000>;
+ temperature = <95000>;
hysteresis = <10000>;
type = "passive";
};
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 35169385fd..685a82161c 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -163,6 +163,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi
index 7ed6b14d77..c67d57cc02 100644
--- a/arch/arm/dts/stm32mp15xx-edx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-edx.dtsi
@@ -389,7 +389,6 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
- pinctrl-3 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi
index 07cb93db93..1a2b49cada 100644
--- a/arch/arm/dts/stm32mp15xx-evx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-evx.dtsi
@@ -223,11 +223,12 @@
dfsdm1: filter@1 {
compatible = "st,stm32-dfsdm-dmic";
- st,adc-channels = <1>;
+ st,adc-channels = <0>;
st,adc-channel-names = "dmic_u2";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
st,filter-order = <3>;
+ st,adc-alt-channel = <1>;
status = "okay";
asoc_pdm1: dfsdm-dai {
@@ -246,10 +247,11 @@
dfsdm2: filter@2 {
compatible = "st,stm32-dfsdm-dmic";
- st,adc-channels = <3>;
+ st,adc-channels = <2>;
st,adc-channel-names = "dmic_u3";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
+ st,adc-alt-channel = <1>;
st,filter-order = <3>;
status = "okay";
@@ -299,6 +301,8 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ nvmem-cells = <&ethernet_mac_address>;
+ nvmem-cell-names = "mac-address";
mdio0 {
#address-cells = <1>;
@@ -315,14 +319,16 @@
pinctrl-0 = <&fmc_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_a>;
status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
@@ -673,6 +679,7 @@
&usbphyc_port0 {
st,phy-tuning = <&usb_phy_tuning>;
+ vbus-supply = <&vbus_sw>;
};
&usbphyc_port1 {
--
2.17.1

529
recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2020.01-stm32mp-r2-MACHINE.patch Normal file
View File

@ -0,0 +1,529 @@
From 84a856108aaf180a2cfda252a9b952b55062442e Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@st.com>
Date: Tue, 27 Oct 2020 11:48:20 +0100
Subject: [PATCH 07/10] ARM-v2020.01-stm32mp-r2-MACHINE
---
Makefile | 2 +-
arch/arm/Kconfig | 28 ++++++++++
arch/arm/include/asm/iproc-common/configs.h | 1 -
arch/arm/include/asm/system.h | 11 ++++
arch/arm/lib/cache-cp15.c | 29 +++++++---
arch/arm/lib/cache.c | 13 +++--
arch/arm/mach-stm32mp/Kconfig | 13 +++++
.../mach-stm32mp/cmd_stm32prog/stm32prog.c | 2 +-
arch/arm/mach-stm32mp/cpu.c | 53 ++++++++++++++++---
arch/arm/mach-stm32mp/fdt.c | 14 +++--
.../mach-stm32mp/include/mach/stm32mp1_smc.h | 48 ++++++++++++-----
.../arm/mach-stm32mp/include/mach/sys_proto.h | 2 +
arch/arm/mach-stm32mp/spl.c | 20 +++++++
13 files changed, 197 insertions(+), 39 deletions(-)
diff --git a/Makefile b/Makefile
index 8b390bc5a3..64b0560af5 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2020
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -stm32mp-r1
+EXTRAVERSION = -stm32mp-r2
NAME =
# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36c9c2fecd..f04c37c88c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -329,6 +329,34 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+choice
+ prompt "Select the ARM data write cache policy"
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+ TARGET_BCMNSP || CPU_PXA || RZA1
+ default SYS_ARM_CACHE_WRITEBACK
+
+config SYS_ARM_CACHE_WRITEBACK
+ bool "Write-back (WB)"
+ help
+ A write updates the cache only and marks the cache line as dirty.
+ External memory is updated only when the line is evicted or explicitly
+ cleaned.
+
+config SYS_ARM_CACHE_WRITETHROUGH
+ bool "Write-through (WT)"
+ help
+ A write updates both the cache and the external memory system.
+ This does not mark the cache line as dirty.
+
+config SYS_ARM_CACHE_WRITEALLOC
+ bool "Write allocation (WA)"
+ help
+ A cache line is allocated on a write miss. This means that executing a
+ store instruction on the processor might cause a burst read to occur.
+ There is a linefill to obtain the data for the cache line, before the
+ write is performed.
+endchoice
+
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
index 96c4f54f4a..4733c0793c 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -10,7 +10,6 @@
/* Architecture, CPU, chip, etc */
#define CONFIG_IPROC
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* Memory Info */
#define CONFIG_SYS_SDRAM_BASE 0x61000000
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index a1a5e35ef6..9fd3b321fc 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -447,6 +447,7 @@ static inline void set_dacr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
@@ -468,6 +469,7 @@ enum dcache_option {
/* options available for data cache on each page */
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
@@ -477,6 +479,7 @@ enum dcache_option {
#define TTB_SECT_AP (3 << 10)
/* options available for data cache on each page */
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
@@ -484,6 +487,14 @@ enum dcache_option {
};
#endif
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
+#endif
+
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f8d20960da..16067cf8da 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <lmb.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <linux/compiler.h>
@@ -61,8 +62,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
unsigned long startpt, stoppt;
unsigned long upto, end;
- end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+ /* div by 2 before start + size to avoid phys_addr_t overflow */
+ end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
+ >> (MMU_SECTION_SHIFT - 1);
start = start >> MMU_SECTION_SHIFT;
+
#ifdef CONFIG_ARMV7_LPAE
debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
option);
@@ -89,20 +93,29 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
+ struct lmb lmb;
int i;
+ /* bd->bi_dram is available only after relocation */
+ if ((gd->flags & GD_FLG_RELOC) == 0)
+ return;
+
+ /*
+ * don't allow cache on reserved memory tagged 'no-map' in DT
+ * => avoid speculative access to "secure" data
+ */
+ lmb_init_and_reserve(&lmb, bd, (void *)gd->fdt_blob);
+
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
i++) {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- set_section_dcache(i, DCACHE_WRITETHROUGH);
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
- set_section_dcache(i, DCACHE_WRITEALLOC);
-#else
- set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
+ if (lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT,
+ LMB_NOMAP))
+ set_section_dcache(i, INVALID_ENTRY);
+ else
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
}
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 007d4ebc49..7f3cfb407c 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -73,6 +73,15 @@ static unsigned long noncached_start;
static unsigned long noncached_end;
static unsigned long noncached_next;
+void noncached_set_region(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+ mmu_set_region_dcache_behaviour(noncached_start,
+ noncached_end - noncached_start,
+ DCACHE_OFF);
+#endif
+}
+
void noncached_init(void)
{
phys_addr_t start, end;
@@ -89,9 +98,7 @@ void noncached_init(void)
noncached_end = end;
noncached_next = start;
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
- mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
-#endif
+ noncached_set_region();
}
phys_addr_t noncached_alloc(size_t size, size_t align)
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index f9f79437e4..c24717d36d 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -103,6 +103,19 @@ config SYS_TEXT_BASE
config NR_DRAM_BANKS
default 1
+config DDR_CACHEABLE_SIZE
+ hex "Size of the DDR marked cacheable in pre-reloc stage"
+ default 0x10000000 if TFABOOT
+ default 0x40000000
+ help
+ Define the size of the DDR marked as cacheable in U-Boot
+ pre-reloc stage.
+ This option can be useful to avoid speculatif access
+ to secured area of DDR used by TF-A or OP-TEE before U-Boot
+ initialization.
+ The areas marked "no-map" in device tree should be located
+ before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
+
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
hex "Partition on MMC2 to use to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index f2f9ed9f36..531df60404 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -560,7 +560,7 @@ static int init_device(struct stm32prog_data *data,
#ifdef CONFIG_MMC
case STM32PROG_MMC:
mmc = find_mmc_device(dev->dev_id);
- if (mmc_init(mmc)) {
+ if (!mmc || mmc_init(mmc)) {
stm32prog_err("mmc device %d not found", dev->dev_id);
return -ENODEV;
}
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 305534f2ba..aee0f2bf81 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -76,6 +76,12 @@
#define PKG_SHIFT 27
#define PKG_MASK GENMASK(2, 0)
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
+ */
+u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_STM32MP1_TRUSTED
static void security_init(void)
@@ -142,17 +148,17 @@ static void security_init(void)
/*
* Debug init
*/
-static void dbgmcu_init(void)
+void dbgmcu_init(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
-
/*
* Freeze IWDG2 if Cortex-A7 is in debug mode
* done in TF-A for TRUSTED boot and
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
*/
- if (!CONFIG_IS_ENABLED(STM32MP1_TRUSTED) && bsec_dbgswenable())
+ if (!IS_ENABLED(CONFIG_STM32MP1_TRUSTED) && bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+ }
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
@@ -192,6 +198,33 @@ u32 get_bootmode(void)
TAMP_BOOT_MODE_SHIFT;
}
+/*
+ * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
+ */
+static void early_enable_caches(void)
+{
+ /* I-cache is already enabled in start.S: cpu_init_cp15 */
+
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+
+ dcache_enable();
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
+ STM32_SYSRAM_SIZE,
+ DCACHE_DEFAULT_OPTION);
+ else
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+ CONFIG_DDR_CACHEABLE_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
/*
* Early system init
*/
@@ -199,11 +232,12 @@ int arch_cpu_init(void)
{
u32 boot_mode;
+ early_enable_caches();
+
/* early armv7 timer init: needed for polling */
timer_init();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
- dbgmcu_init();
#ifndef CONFIG_STM32MP1_TRUSTED
security_init();
update_bootmode();
@@ -231,7 +265,14 @@ int arch_cpu_init(void)
void enable_caches(void)
{
- /* Enable D-cache. I-cache is already enabled in start.S */
+ /* I-cache is already enabled in start.S: icache_enable() not needed */
+
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * update MMU after relocation and enable the data cache
+ * warning: the TLB location udpated in board_f.c::reserve_mmu
+ */
dcache_enable();
}
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
index 21b5f09728..8d9a58186d 100644
--- a/arch/arm/mach-stm32mp/fdt.c
+++ b/arch/arm/mach-stm32mp/fdt.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
@@ -223,19 +223,23 @@ static void stm32_fdt_disable_optee(void *blob)
{
int off, node;
+ /* Delete "optee" firmware node */
off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
if (off >= 0 && fdtdec_get_is_enabled(blob, off))
- fdt_status_disabled(blob, off);
+ fdt_del_node(blob, off);
- /* Disabled "optee@..." reserved-memory node */
+ /* Delete "optee@..." reserved-memory node */
off = fdt_path_offset(blob, "/reserved-memory/");
if (off < 0)
return;
for (node = fdt_first_subnode(blob, off);
node >= 0;
node = fdt_next_subnode(blob, node)) {
- if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
- fdt_status_disabled(blob, node);
+ if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
+ continue;
+
+ if (fdt_del_node(blob, node))
+ printf("Failed to remove optee reserved-memory node\n");
}
}
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
index dea5b4a6b4..d72747ca31 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
@@ -8,27 +8,53 @@
#include <linux/arm-smccc.h>
+/* SMC service generic return codes */
+#define STM32_SMC_OK 0x00000000U
+#define STM32_SMC_NOT_SUPPORTED 0xFFFFFFFFU
+#define STM32_SMC_FAILED 0xFFFFFFFEU
+#define STM32_SMC_INVALID_PARAMS 0xFFFFFFFDU
+
/*
- * SMC function IDs for STM32 Service queries
+ * SMC function IDs for STM32 Service queries.
* STM32 SMC services use the space between 0x82000000 and 0x8200FFFF
* like this is defined in SMC calling Convention by ARM
- * for SiP (silicon Partner)
- * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+ * for SiP (silicon Partner).
+ * https://developer.arm.com/docs/den0028/latest
*/
-#define STM32_SMC_VERSION 0x82000000
/* Secure Service access from Non-secure */
-#define STM32_SMC_RCC 0x82001000
+
+/*
+ * SMC function STM32_SMC_PWR.
+ *
+ * Argument a0: (input) SMCC ID.
+ * (output) Status return code.
+ * Argument a1: (input) Service ID (STM32_SMC_REG_xxx).
+ * Argument a2: (input) Register offset or physical address.
+ * (output) Register read value, if applicable.
+ * Argument a3: (input) Register target value if applicable.
+ */
#define STM32_SMC_PWR 0x82001001
-#define STM32_SMC_RTC 0x82001002
+
+/*
+ * SMC functions STM32_SMC_BSEC.
+ *
+ * Argument a0: (input) SMCC ID.
+ * (output) Status return code.
+ * Argument a1: (input) Service ID (STM32_SMC_READ_xxx/_PROG_xxx/_WRITE_xxx).
+ * (output) OTP read value, if applicable.
+ * Argument a2: (input) OTP index.
+ * Argument a3: (input) OTP value if applicable.
+ */
#define STM32_SMC_BSEC 0x82001003
-/* Register access service use for RCC/RTC/PWR */
+/* Service ID for STM32_SMC_PWR */
+#define STM32_SMC_REG_READ 0x0
#define STM32_SMC_REG_WRITE 0x1
#define STM32_SMC_REG_SET 0x2
#define STM32_SMC_REG_CLEAR 0x3
-/* Service for BSEC */
+/* Service ID for STM32_SMC_BSEC */
#define STM32_SMC_READ_SHADOW 0x01
#define STM32_SMC_PROG_OTP 0x02
#define STM32_SMC_WRITE_SHADOW 0x03
@@ -37,12 +63,6 @@
#define STM32_SMC_WRITE_ALL 0x06
#define STM32_SMC_WRLOCK_OTP 0x07
-/* SMC error codes */
-#define STM32_SMC_OK 0x0
-#define STM32_SMC_NOT_SUPPORTED -1
-#define STM32_SMC_FAILED -2
-#define STM32_SMC_INVALID_PARAMS -3
-
#define stm32_smc_exec(svc, op, data1, data2) \
stm32_smc(svc, op, data1, data2, NULL)
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index b6ad3c67ae..c5cab9f21b 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -52,3 +52,5 @@ int setup_mac_address(void);
/* board power management : configure vddcore according OPP */
void board_vddcore_init(u32 voltage_mv);
int board_vddcore_set(void);
+
+void dbgmcu_init(void);
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index f4b4c3bd82..41f3fd4b7c 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <spl.h>
#include <asm/io.h>
@@ -123,4 +124,23 @@ void board_init_f(ulong dummy)
printf("DRAM init failed: %d\n", ret);
hang();
}
+
+ /*
+ * activate cache on DDR only when DDR is fully initialized
+ * to avoid speculative access and issue in get_ram_size()
+ */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+ CONFIG_DDR_CACHEABLE_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+ dcache_disable();
}
--
2.17.1

247
recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.01-stm32mp-r2-BOARD.patch Normal file
View File

@ -0,0 +1,247 @@
From c4ead8e3640dd3d0810bff2cbd4b6c14c2139a04 Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@st.com>
Date: Tue, 27 Oct 2020 11:48:28 +0100
Subject: [PATCH 08/10] ARM-v2020.01-stm32mp-r2-BOARD
---
board/st/stm32mp1/spl.c | 4 ++
board/st/stm32mp1/stm32mp1.c | 136 +++++++++++++++++++++++------------
2 files changed, 95 insertions(+), 45 deletions(-)
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index e65ff288ea..058d47e0e7 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -12,9 +12,13 @@
#include <power/pmic.h>
#include <power/stpmic1.h>
#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
void spl_board_init(void)
{
+ /* init DBGMU */
+ dbgmcu_init();
+
/* Keep vdd on during the reset cycle */
#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT)
struct udevice *dev;
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 617d05d209..6dad00600e 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -22,6 +22,7 @@
#include <remoteproc.h>
#include <reset.h>
#include <syscon.h>
+#include <tee.h>
#include <usb.h>
#include <watchdog.h>
#include <asm/io.h>
@@ -118,7 +119,7 @@ int checkboard(void)
const char *fdt_compat;
int fdt_compat_len;
- if (CONFIG_IS_ENABLED(STM32MP1_TRUSTED))
+ if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
mode = "trusted";
else
mode = "basic";
@@ -362,38 +363,14 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
}
#ifdef CONFIG_ADC
-static int board_check_usb_power(void)
+
+static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
{
struct ofnode_phandle_args adc_args;
struct udevice *adc;
- ofnode node;
unsigned int raw;
- int max_uV = 0;
- int min_uV = USB_START_HIGH_THRESHOLD_UV;
- int ret, uV, adc_count;
- u32 nb_blink;
- u8 i;
- node = ofnode_path("/config");
- if (!ofnode_valid(node)) {
- debug("%s: no /config node?\n", __func__);
- return -ENOENT;
- }
-
- /*
- * Retrieve the ADC channels devices and get measurement
- * for each of them
- */
- adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
- "#io-channel-cells");
- if (adc_count < 0) {
- if (adc_count == -ENOENT)
- return 0;
-
- pr_err("%s: can't find adc channel (%d)\n", __func__,
- adc_count);
-
- return adc_count;
- }
+ int ret, uV;
+ int i;
for (i = 0; i < adc_count; i++) {
if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
@@ -422,10 +399,10 @@ static int board_check_usb_power(void)
}
/* Convert to uV */
if (!adc_raw_to_uV(adc, raw, &uV)) {
- if (uV > max_uV)
- max_uV = uV;
- if (uV < min_uV)
- min_uV = uV;
+ if (uV > *max_uV)
+ *max_uV = uV;
+ if (uV < *min_uV)
+ *min_uV = uV;
pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
adc->name, adc_args.args[0], raw, uV);
} else {
@@ -433,19 +410,62 @@ static int board_check_usb_power(void)
__func__, adc->name, adc_args.args[0]);
}
}
+ return 0;
+}
+
+static int board_check_usb_power(void)
+{
+ ofnode node;
+ int max_uV = 0;
+ int min_uV = USB_START_HIGH_THRESHOLD_UV;
+ int adc_count, ret;
+ u32 nb_blink;
+ u8 i;
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ debug("%s: no /config node?\n", __func__);
+ return -ENOENT;
+ }
/*
- * If highest value is inside 1.23 Volts and 2.10 Volts, that means
- * board is plugged on an USB-C 3A power supply and boot process can
- * continue.
+ * Retrieve the ADC channels devices and get measurement
+ * for each of them
*/
- if (max_uV > USB_START_LOW_THRESHOLD_UV &&
- max_uV <= USB_START_HIGH_THRESHOLD_UV &&
- min_uV <= USB_LOW_THRESHOLD_UV)
- return 0;
+ adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
+ "#io-channel-cells");
+ if (adc_count < 0) {
+ if (adc_count == -ENOENT)
+ return 0;
- pr_err("****************************************************\n");
+ pr_err("%s: can't find adc channel (%d)\n", __func__,
+ adc_count);
+
+ return adc_count;
+ }
+
+ /* perform maximum of 2 ADC measurement to detect power supply current */
+ for (i = 0; i < 2; i++) {
+ ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
+ if (ret)
+ return ret;
+
+ /*
+ * If highest value is inside 1.23 Volts and 2.10 Volts, that means
+ * board is plugged on an USB-C 3A power supply and boot process can
+ * continue.
+ */
+ if (max_uV > USB_START_LOW_THRESHOLD_UV &&
+ max_uV <= USB_START_HIGH_THRESHOLD_UV &&
+ min_uV <= USB_LOW_THRESHOLD_UV)
+ return 0;
+
+ if (i == 0) {
+ pr_debug("Previous ADC measurements was not the one expected, retry in 20ms\n");
+ mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */
+ }
+ }
+ pr_err("****************************************************\n");
/*
* If highest and lowest value are either both below
* USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
@@ -737,7 +757,7 @@ int board_init(void)
int board_late_init(void)
{
- char *boot_device;
+ char *boot_device, *boot_instance;
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
const void *fdt_compat;
int fdt_compat_len;
@@ -770,7 +790,7 @@ int board_late_init(void)
if (!ret)
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
&otp, sizeof(otp));
- if (!ret && otp) {
+ if (ret > 0 && otp) {
snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
env_set("board_id", buf);
@@ -791,6 +811,25 @@ int board_late_init(void)
(!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")))
env_set("bootdelay", "0");
+ /* define dynamic variables for FASTBOOT and ANDROID bootargs*/
+ if (CONFIG_IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC) &&
+ boot_device && !strcmp(boot_device, "mmc")) {
+ boot_instance = env_get("boot_instance");
+ env_set("fastboot.boot_instance", boot_instance);
+ }
+ if (CONFIG_IS_ENABLED(OPTEE) &&
+ tee_find_device(NULL, NULL, NULL, NULL)) {
+ if (CONFIG_IS_ENABLED(CONFIG_CMD_DTIMG))
+ env_set("android_bootargs", "androidboot.optee=true");
+ if (CONFIG_IS_ENABLED(FASTBOOT))
+ env_set("fastboot.boot_mode", "optee");
+ } else {
+ if (CONFIG_IS_ENABLED(CONFIG_CMD_DTIMG))
+ env_set("android_bootargs", "");
+ if (CONFIG_IS_ENABLED(FASTBOOT))
+ env_set("fastboot.boot_mode", "trusted");
+ }
+
return 0;
}
@@ -939,12 +978,19 @@ int mmc_get_env_dev(void)
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- struct node_info nodes[] = {
+ static const struct node_info nodes[] = {
{ "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
{ "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND},
{ "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
+ { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, },
};
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ char *boot_device;
+
+ /* Check the boot-source and don't update MTD for serial or usb boot */
+ boot_device = env_get("boot_device");
+ if (!boot_device ||
+ (strcmp(boot_device, "serial") && strcmp(boot_device, "usb")))
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
return 0;
--
2.17.1

4006
recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2020.01-stm32mp-r2-MISC-DRIVERS.patch Normal file
View File

File diff suppressed because it is too large Load Diff

63
recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2020.01-stm32mp-r2-CONFIG.patch Normal file
View File

@ -0,0 +1,63 @@
From 881509572b6d9fac6dc570b710e89d47cabbf05b Mon Sep 17 00:00:00 2001
From: Christophe Priouzeau <christophe.priouzeau@st.com>
Date: Tue, 27 Oct 2020 11:49:05 +0100
Subject: [PATCH 10/10] ARM-v2020.01-stm32mp-r2-CONFIG
---
configs/stm32mp15_basic_defconfig | 3 +--
configs/stm32mp15_trusted_defconfig | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index cf282177f7..79e77e122c 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -27,8 +27,6 @@ CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
@@ -89,6 +87,7 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
+CONFIG_STM32_FMC2_EBI=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index e248b7d1d3..b5069bc6d5 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -15,8 +15,6 @@ CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
@@ -77,6 +75,7 @@ CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_ARM_SMC_MAILBOX=y
+CONFIG_STM32_FMC2_EBI=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
@@ -106,6 +105,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_OPTEE=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RTC=y
--
2.17.1