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openocd: support of stm32mp machine 

Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
This commit is contained in:
Christophe Priouzeau 2019-02-04 15:44:44 +01:00
parent 6c2e5c1d24
commit 7e6e8d6eb6
7 changed files with 7934 additions and 0 deletions
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53
recipes-devtools/openocd/openocd-stm32mp.inc Normal file
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@ -0,0 +1,53 @@
inherit pkgconfig autotools-brokensep gettext
SRC_URI = " \
git://repo.or.cz/r/git2cl.git;protocol=http;destsuffix=git/tools/git2cl;name=git2cl \
git://repo.or.cz/r/jimtcl.git;protocol=http;destsuffix=git/jimtcl;name=jimtcl \
git://repo.or.cz/r/libjaylink.git;protocol=http;destsuffix=git/src/jtag/drivers/libjaylink;name=libjaylink \
"
SRCREV_git2cl = "8373c9f74993e218a08819cbcdbab3f3564bbeba"
SRCREV_jimtcl = "a9bf5975fd0f89974d689a2d9ebd0873c8d64787"
SRCREV_libjaylink = "8645845c1abebd004e991ba9a7f808f4fd0c608b"
S = "${WORKDIR}/git"
BBCLASSEXTEND += "native nativesdk"
DEPENDS += "hidapi-stm32mp"
DEPENDS_class-native = "hidapi-stm32mp-native"
DEPENDS_class-nativesdk = "nativesdk-hidapi-stm32mp"
RDEPENDS_${PN} += "libusb1 hidapi-stm32mp"
EXTRA_OECONF = " \
--disable-werror \
--enable-stlink \
--enable-cmsis-dap \
MAKEINFO=true \
HIDAPI_CFLAGS=-I${STAGING_INCDIR}/hidapi \
HIDAPI_LIBS=-L${STAGING_LIBDIR}\ -lhidapi-libusb \
"
do_configure() {
./bootstrap nosubmodule
oe_runconf ${EXTRA_OECONF}
}
do_install() {
oe_runmake DESTDIR=${D} install
if [ -e "${D}${infodir}" ]; then
rm -Rf ${D}${infodir}
fi
if [ -e "${D}${mandir}" ]; then
rm -Rf ${D}${mandir}
fi
if [ -e "${D}${bindir}/.debug" ]; then
rm -Rf ${D}${bindir}/.debug
fi
}
FILES_${PN} = " \
${datadir}/openocd/* \
${bindir}/openocd \
"

5378
recipes-devtools/openocd/openocd-stm32mp/0001-Add-support-of-STLINK-for-stm32mp1.patch Normal file
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458
recipes-devtools/openocd/openocd-stm32mp/0002-Add-support-for-silicon-revB.patch Normal file
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@ -0,0 +1,458 @@
From df2861a1384f3bf2ab8236ee51f8a5ff40e8f45b Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 12 Oct 2018 11:49:18 +0200
Subject: [PATCH] Add support for silicon revB
---
src/jtag/drivers/cmsis_dap_usb.c | 4 +-
src/jtag/drivers/libusb0_common.c | 7 ++
src/jtag/drivers/libusb1_common.c | 7 ++
tcl/board/stm32mp15x_dk2.cfg | 2 +-
tcl/board/stm32mp15x_ev1_jlink_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_jlink_swd.cfg | 2 +-
tcl/board/stm32mp15x_ev1_stlink_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_stlink_swd.cfg | 2 +-
tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_ulink2_swd.cfg | 2 +-
tcl/target/stm32mp15x.cfg | 11 ++-
tcl/target/stm32mp15x_stpmic1.cfg | 113 +++++++++++++++++++++++++++++++
tcl/target/stm32mp15x_stpmu1.cfg | 113 -------------------------------
13 files changed, 145 insertions(+), 124 deletions(-)
diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index 4ee4836..9e723b5 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -895,9 +895,7 @@ static int cmsis_dap_init(void)
retval = cmsis_dap_swd_open();
if (retval != ERROR_OK)
return retval;
- }
-
- if (cmsis_dap_handle == NULL) {
+ } else {
/* Connect in JTAG mode */
if (!(cmsis_dap_handle->caps & INFO_CAPS_JTAG)) {
LOG_ERROR("CMSIS-DAP: JTAG not supported");
diff --git a/src/jtag/drivers/libusb0_common.c b/src/jtag/drivers/libusb0_common.c
index 1825543..04f88b6 100644
--- a/src/jtag/drivers/libusb0_common.c
+++ b/src/jtag/drivers/libusb0_common.c
@@ -68,6 +68,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
struct jtag_libusb_device_handle **out)
{
int retval = -ENODEV;
+ bool serial_mismatch = false;
struct jtag_libusb_device_handle *libusb_handle;
usb_init();
@@ -90,14 +91,20 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Device must be open to use libusb_get_string_descriptor_ascii. */
if (serial != NULL &&
!string_descriptor_equal(libusb_handle, dev->descriptor.iSerialNumber, serial)) {
+ serial_mismatch = true;
usb_close(libusb_handle);
continue;
}
*out = libusb_handle;
retval = 0;
+ serial_mismatch = false;
break;
}
}
+
+ if (serial_mismatch)
+ LOG_DEBUG("No device matches the serial string");
+
return retval;
}
diff --git a/src/jtag/drivers/libusb1_common.c b/src/jtag/drivers/libusb1_common.c
index a1db86f..0ec5fb9 100644
--- a/src/jtag/drivers/libusb1_common.c
+++ b/src/jtag/drivers/libusb1_common.c
@@ -72,6 +72,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
{
int cnt, idx, errCode;
int retval = ERROR_FAIL;
+ bool serial_mismatch = false;
struct jtag_libusb_device_handle *libusb_handle = NULL;
if (libusb_init(&jtag_libusb_context) < 0)
@@ -99,6 +100,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Device must be open to use libusb_get_string_descriptor_ascii. */
if (serial != NULL &&
!string_descriptor_equal(libusb_handle, dev_desc.iSerialNumber, serial)) {
+ serial_mismatch = true;
libusb_close(libusb_handle);
continue;
}
@@ -106,10 +108,15 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Success. */
*out = libusb_handle;
retval = ERROR_OK;
+ serial_mismatch = false;
break;
}
if (cnt >= 0)
libusb_free_device_list(devs, 1);
+
+ if (serial_mismatch)
+ LOG_DEBUG("No device matches the serial string");
+
return retval;
}
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg
index 82617c5..8d673fa 100644
--- a/tcl/board/stm32mp15x_dk2.cfg
+++ b/tcl/board/stm32mp15x_dk2.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
index 7d74fa6..665dc82 100644
--- a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/jlink.cfg]
transport select jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
index 33e6ef5..7ca27af 100644
--- a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/jlink.cfg]
transport select swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
index 6fb1e31..9364c92 100644
--- a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
index 3c561c9..d8527ee 100644
--- a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
index 6b10351..c7954ea 100644
--- a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg]
transport select jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
index 5495bc3..b00cc61 100644
--- a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg]
transport select swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 0def780..5d7e230 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -77,7 +77,7 @@ proc delayed_reset_halt_cpu0 { } {
global _CHIPNAME
global arp_reset_mode
- set rom_halt_pc 0x0000688c
+ set rom_halt_pc 0x000079ac
# only "reset halt" or "reset init"
if { 0 != [ string compare "$arp_reset_mode" "run" ] } {
@@ -85,6 +85,15 @@ proc delayed_reset_halt_cpu0 { } {
targets $_CHIPNAME.cpu0
arp_reset_default_handler post $_CHIPNAME.cpu0
+ # quick test for cut1.0, check bootrom
+ set v ""
+ ap0_non_secure_access
+ mem2array v 32 0x0000a000 1 phys
+ ap0_secure_access
+ if { $v(0) == 0x1e494610 } {
+ set rom_halt_pc 0x0000688c
+ }
+
poll on
catch { $_CHIPNAME.cpu0 arp_waitstate halted 1000 }
bp $rom_halt_pc 2 hw
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
new file mode 100644
index 0000000..c080441
--- /dev/null
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -0,0 +1,113 @@
+# script for stm32mp15x family with companion PMIC STPMIC1
+
+source [find target/stm32mp15x.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
+
+# Wait for expression to be true with a timeout of 200ms
+proc wait_state {condition} {
+ for {set t 0} {$t < 200} {incr t} {
+ if {[uplevel 1 $condition] == 0} {
+ return
+ }
+ sleep 1
+ }
+ return -code 1 "Timed out"
+}
+
+proc mrw_phys {reg} {
+ set value ""
+ mem2array value 32 $reg 1 phys
+ return $value(0)
+}
+
+proc mmw_phys {reg setbits clearbits} {
+ set old [mrw_phys $reg]
+ set new [expr ($old & ~$clearbits) | $setbits]
+ mww phys $reg $new
+}
+
+# Set mask_reset bits in PMIC to keep all powers on at next reset event
+# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
+# This procedure requires Secure memory access
+proc pmic_init {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ set RCC_BASE 0x50000000
+ set GPIO_BASE 0x54004000
+ set I2C_BASE 0x5c002000
+
+ # i2c @ 100kHz, rise 100ns, fall 100ns
+ # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz
+ set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b}
+
+ mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI)
+ mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck)
+
+ mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1
+ mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST
+ mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST
+
+ mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ)
+ mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF
+ mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain
+ mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed
+ mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down
+ mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6
+
+ set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3]
+ mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
+ mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1
+ mww phys [expr $I2C_BASE + 0x004] 0x02043066
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x18
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x0f
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x00
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x6f
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
+ mww phys [expr $I2C_BASE + 0x01c] 0x00000020
+ mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe
+
+# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4)
+# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
+}
+
+# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
+# are in a debug session. This will force them (at next reboot) to program
+# the PMIC for keeping powered-on the debug unit during reset.
+proc set_pmic_in_backup_reg {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ mmw_phys 0x5c00a150 0x00010000 0x00000000
+}
+
+proc clear_pmic_in_backup_reg {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ mmw_phys 0x5c00a150 0x00000000 0x00010000
+}
+
+# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown
+rename init _init
+proc init {} {
+ _init
+ set_pmic_in_backup_reg
+}
+
+rename shutdown _shutdown
+proc shutdown {} {
+ clear_pmic_in_backup_reg
+ _shutdown
+}
diff --git a/tcl/target/stm32mp15x_stpmu1.cfg b/tcl/target/stm32mp15x_stpmu1.cfg
deleted file mode 100644
index 413abf2..0000000
--- a/tcl/target/stm32mp15x_stpmu1.cfg
+++ /dev/null
@@ -1,113 +0,0 @@
-# script for stm32mp15x family with companion PMIC STPMU1
-
-source [find target/stm32mp15x.cfg]
-
-$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
-
-# Wait for expression to be true with a timeout of 200ms
-proc wait_state {condition} {
- for {set t 0} {$t < 200} {incr t} {
- if {[uplevel 1 $condition] == 0} {
- return
- }
- sleep 1
- }
- return -code 1 "Timed out"
-}
-
-proc mrw_phys {reg} {
- set value ""
- mem2array value 32 $reg 1 phys
- return $value(0)
-}
-
-proc mmw_phys {reg setbits clearbits} {
- set old [mrw_phys $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww phys $reg $new
-}
-
-# Set mask_reset bits in PMIC to keep all powers on at next reset event
-# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
-# This procedure requires Secure memory access
-proc pmic_init {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- set RCC_BASE 0x50000000
- set GPIO_BASE 0x54004000
- set I2C_BASE 0x5c002000
-
- # i2c @ 100kHz, rise 100ns, fall 100ns
- # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz
- set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b}
-
- mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI)
- mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck)
-
- mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1
- mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST
- mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST
-
- mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ)
- mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF
- mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain
- mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed
- mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down
- mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6
-
- set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3]
- mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
- mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1
- mww phys [expr $I2C_BASE + 0x004] 0x02043066
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x18
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x0f
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x00
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x6f
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
- mww phys [expr $I2C_BASE + 0x01c] 0x00000020
- mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe
-
-# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4)
-# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
-}
-
-# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
-# are in a debug session. This will force them (at next reboot) to program
-# the PMIC for keeping powered-on the debug unit during reset.
-proc set_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- mmw_phys 0x5c00a150 0x00010000 0x00000000
-}
-
-proc clear_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- mmw_phys 0x5c00a150 0x00000000 0x00010000
-}
-
-# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown
-rename init _init
-proc init {} {
- _init
- set_pmic_in_backup_reg
-}
-
-rename shutdown _shutdown
-proc shutdown {} {
- clear_pmic_in_backup_reg
- _shutdown
-}
--
2.7.4

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recipes-devtools/openocd/openocd-stm32mp/0004-Fix-init-command.patch Normal file
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From 4b82bf719f303b77df9a2310f75da4ce81098b17 Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 9 Nov 2018 11:26:47 +0100
Subject: [PATCH 4/4] Fix init command
---
tcl/target/stm32mp15x_stpmic1.cfg | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
index a6446c640..2a32610fc 100644
--- a/tcl/target/stm32mp15x_stpmic1.cfg
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -85,13 +85,21 @@ proc pmic_init {} {
proc set_pmic_in_backup_reg {} {
global _CHIPNAME
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
$_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
+ $_CHIPNAME.dap apcsw $old_csw
}
proc clear_pmic_in_backup_reg {} {
global _CHIPNAME
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
$_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
+ $_CHIPNAME.dap apcsw $old_csw
}
# Wrap around init/shutdown. Typing CTRL-C will also invoke shutdown
--
2.19.1

424
recipes-devtools/openocd/openocd-stm32mp/0005-Add-CTI-plus-fixes.patch Normal file
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From 4e6c43b1054ee6544f2f1758963c886fa03136ae Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 18 Jan 2019 16:52:07 +0100
Subject: [PATCH] Add CTI plus fixes
---
src/target/arm_cti.c | 4 +-
src/target/cortex_a.c | 39 ++++---
tcl/target/stm32mp15x.cfg | 162 ++++++++++++++++++++++++++++--
tcl/target/stm32mp15x_stpmic1.cfg | 62 +++---------
4 files changed, 196 insertions(+), 71 deletions(-)
diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c
index dcaf21e50..e6cb3cde3 100644
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@@ -173,7 +173,7 @@ int arm_cti_clear_channel(struct arm_cti *self, uint32_t channel)
return arm_cti_write_reg(self, CTI_APPCLEAR, CTI_CHNL(channel));
}
-static uint32_t cti_regs[26];
+static uint32_t cti_regs[28];
static const struct {
uint32_t offset;
@@ -206,6 +206,8 @@ static const struct {
{ CTI_CHOU_STATUS, "CHOUT", &cti_regs[23] },
{ CTI_APPSET, "APPSET", &cti_regs[24] },
{ CTI_APPCLEAR, "APPCLR", &cti_regs[25] },
+ { CTI_APPPULSE, "APPPULSE", &cti_regs[26] },
+ { CTI_INACK, "INACK", &cti_regs[27] },
};
static int cti_find_reg_offset(const char *name)
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index b281233ca..499dacc9b 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -201,6 +201,7 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
+ uint32_t dscr;
int retval;
/* lock memory-mapped access to debug registers to prevent
@@ -230,6 +231,16 @@ static int cortex_a_init_debug_access(struct target *target)
/* Resync breakpoint registers */
+ /* Enable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
+ if (retval != ERROR_OK)
+ return retval;
+
/* Since this is likely called from init or reset, update target state information*/
return cortex_a_poll(target);
}
@@ -768,19 +779,6 @@ static int cortex_a_halt(struct target *target)
if (retval != ERROR_OK)
return retval;
- /*
- * enter halting debug mode
- */
- retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
- if (retval != ERROR_OK)
- return retval;
-
int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
@@ -2977,7 +2975,20 @@ static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
static void cortex_a_deinit_target(struct target *target)
{
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct arm_dpm *dpm = &armv7a->dpm;
+ uint32_t dscr;
+ int retval;
+
+ if (target_was_examined(target)) {
+ /* Disable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval == ERROR_OK)
+ mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR,
+ dscr & ~DSCR_HALT_DBG_MODE);
+ }
free(cortex_a->brp_list);
free(dpm->dbp);
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 0d10021ef..992975f87 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -47,6 +47,69 @@ if { [using_jtag] } {
swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# in smp mode, if one core is halted the event 'halted' get fired for the selected core only.
+# so the halt event remains unacknowledged for other cores.
+proc cti_prepare_restart_all {} {
+ global _CHIPNAME
+
+ cti_prepare_restart cti0
+ cti_prepare_restart cti1
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ cti_prepare_restart cti2
+ }
+}
+
+proc cti_prepare_restart {cti} {
+ global _CHIPNAME
+
+ # Acknowlodge EDBGRQ at TRIGOUT0
+ $_CHIPNAME.$cti write INACK 0x01
+ $_CHIPNAME.$cti write INACK 0x00
+}
+
+proc cti_start {} {
+ global _CHIPNAME
+
+ # Configure both Cortex-A CTIs to halt each other
+ # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+ $_CHIPNAME.cti0 write INEN0 0x1
+ $_CHIPNAME.cti1 write INEN0 0x1
+ $_CHIPNAME.cti0 write OUTEN0 0x1
+ $_CHIPNAME.cti1 write OUTEN0 0x1
+
+ $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
+ $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
+
+ # enable CTIs
+ $_CHIPNAME.cti0 enable on
+ $_CHIPNAME.cti1 enable on
+
+ # Cortex-M4 CTI configuration (enable CM4.CTI and join same CTM channels)
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ $_CHIPNAME.cti2 write INEN0 0x1
+ $_CHIPNAME.cti2 write OUTEN0 0x1
+ $_CHIPNAME.cpu2 configure -event halted { cti_prepare_restart_all }
+ $_CHIPNAME.cti2 enable on
+ }
+}
+
+proc cti_stop {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.cti0 enable off
+ $_CHIPNAME.cti1 enable off
+
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ $_CHIPNAME.cti2 enable off
+ }
+}
+
+cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
+cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
+cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
+cti create $_CHIPNAME.cti2 -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0xE00D0000
target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
@@ -83,8 +146,23 @@ $_CHIPNAME.cpu0 configure -gdb-port [expr $_GDB_PORT + 1]
$_CHIPNAME.cpu1 configure -gdb-port [expr $_GDB_PORT + 2]
$_CHIPNAME.cpu2 configure -gdb-port [expr $_GDB_PORT + 0]
+$_CHIPNAME.cpu0 configure -event reset-assert-pre { pre_reset_halt_cpu0 }
$_CHIPNAME.cpu0 configure -event reset-deassert-post { delayed_reset_halt_cpu0 }
+proc pre_reset_halt_cpu0 {} {
+ global _CHIPNAME
+ global ENG_MODE
+ global arp_reset_mode
+ global workaround_revision_0x2000
+
+ catch { unset workaround_revision_0x2000 }
+ if { ([eval chip_revision] == 0x2000) && ![info exists ENG_MODE] && ([string compare "$arp_reset_mode" "run"] != 0) } {
+ set workaround_revision_0x2000 1
+ set_debugflag_in_backup_reg
+ }
+ arp_reset_default_handler pre $_CHIPNAME.cpu0
+}
+
# In production mode, reset-halt stops in bootrom when only
# cpu0 can be attached due to security mode.
# Set a breakpoint to stop cpu0 when cpu1 can be attached too.
@@ -92,10 +170,27 @@ proc delayed_reset_halt_cpu0 { } {
global _CHIPNAME
global ENG_MODE
global arp_reset_mode
+ global workaround_revision_0x2000
if { [info exists ENG_MODE] || ([string compare "$arp_reset_mode" "run"] == 0) } {
# default reset-deassert-post handler
arp_reset_default_handler post $_CHIPNAME.cpu0
+ } elseif { [info exists workaround_revision_0x2000] } {
+ unset workaround_revision_0x2000
+ cortex_a smp_off
+ $_CHIPNAME.cpu0 arp_examine
+ catch { $_CHIPNAME.cpu0 arp_waitstate halted 500 }
+ halt
+ cortex_a smp_on
+ catch { clear_debugflag_in_backup_reg }
+
+ # incr PC if insn is "BKPT 5"
+ set pc [ocd_reg pc]
+ regsub {pc[^:]*: } $pc "" pc
+ if { ([expr $pc & 3] == 0) && ([mrw $pc] == 0xe1200075) } {
+ reg pc [expr $pc + 4]
+ }
+ arp_reset_halt_default_handler $_CHIPNAME.cpu0
} else {
# only in production mode for "reset halt" or "reset init"
cortex_a smp_off
@@ -103,12 +198,7 @@ proc delayed_reset_halt_cpu0 { } {
arp_reset_default_handler post $_CHIPNAME.cpu0
set rom_halt_pc 0x000079ac
- # quick test for rev.A, check bootrom
- set v ""
- axi_non_secure_access
- $_CHIPNAME.axi mem2array v 32 0x0000a000 1 phys
- axi_secure_access
- if { $v(0) == 0x1e494610 } {
+ if { [eval chip_revision] == 0x1000 } {
set rom_halt_pc 0x0000688c
}
@@ -176,6 +266,57 @@ $_CHIPNAME.cpu0 configure -event gdb-detach { catch { resume }; clients_dec_and_
$_CHIPNAME.cpu1 configure -event gdb-detach { catch { resume }; clients_dec_and_shutdown }
$_CHIPNAME.cpu2 configure -event gdb-detach { catch { resume }; clients_dec_and_shutdown }
+proc chip_revision {} {
+ global _CHIPNAME
+
+ # read DBGMCU_IDC
+ $_CHIPNAME.ap1 mem2array v 32 0xe0081000 1
+ return [expr $v(0) >> 16]
+}
+
+proc $_CHIPNAME.axi_mrw {reg} {
+ global _CHIPNAME
+
+ set value ""
+ $_CHIPNAME.axi mem2array value 32 $reg 1
+ return $value(0)
+}
+
+proc $_CHIPNAME.axi_mmw {reg setbits clearbits} {
+ global _CHIPNAME
+
+ set old [$_CHIPNAME.axi_mrw $reg]
+ set new [expr ($old & ~$clearbits) | $setbits]
+ $_CHIPNAME.axi mww $reg $new
+}
+
+# Backup registers are battery powered and keep the value both across power
+# cycles and reset pulses on NRST_CORE pin.
+# Bit 16 in TAMP_BACKUP_REGISTER(20) is used as special signal between the
+# debugger and the application across a reset.
+proc set_debugflag_in_backup_reg {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_secure_access
+ catch { $_CHIPNAME.axi_mmw 0x50001000 0x00000100 0x00000000 }
+ catch { $_CHIPNAME.axi_mmw 0x50000208 0x00000100 0x00000000 }
+ axi_non_secure_access
+ $_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
+ $_CHIPNAME.dap apcsw $old_csw
+}
+
+proc clear_debugflag_in_backup_reg {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
+ $_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
+ $_CHIPNAME.dap apcsw $old_csw
+}
+
proc axi_secure_access {} {
global _CHIPNAME
@@ -191,3 +332,12 @@ proc axi_non_secure_access {} {
}
axi_secure_access
+
+rename init __init
+proc init {} {
+ __init
+ if { [eval chip_revision] == 0x2000 } {
+ # srst pulse causes a reset of the debug port
+ reset_config srst_pulls_trst
+ }
+}
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
index 2a32610fc..16cf9b0ae 100644
--- a/tcl/target/stm32mp15x_stpmic1.cfg
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -2,7 +2,7 @@
source [find target/stm32mp15x.cfg]
-$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
+$_CHIPNAME.cpu0 configure -event reset-halt { catch { if { [eval chip_revision] != 0x2000 } { pmic_init } } }
# Wait for expression to be true with a timeout of 200ms
proc wait_state {condition} {
@@ -15,24 +15,8 @@ proc wait_state {condition} {
return -code 1 "Timed out"
}
-proc $_CHIPNAME.axi_mrw {reg} {
- global _CHIPNAME
-
- set value ""
- $_CHIPNAME.axi mem2array value 32 $reg 1
- return $value(0)
-}
-
-proc $_CHIPNAME.axi_mmw {reg setbits clearbits} {
- global _CHIPNAME
-
- set old [$_CHIPNAME.axi_mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- $_CHIPNAME.axi mww $reg $new
-}
-
-# Set mask_reset bits in PMIC to keep all powers on at next reset event
-# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
+# Set mask_reset bits in PMIC to keep VDD and VDD_CORE on at next reset event
+# Mask_reset for SD-card power "must" not be enabled to guarantee boot from SD
# This procedure requires Secure memory access
proc pmic_init {} {
global _CHIPNAME
@@ -62,15 +46,11 @@ proc pmic_init {} {
set hsidiv [expr [$_CHIPNAME.axi_mrw [expr $RCC_BASE + 0x018]] & 0x3]
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x000] 1; # set PE = 1
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x02043066
+ $_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x02023066
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x18
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x0f
- wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x00
- wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x6f
+ $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x05
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x01c] 0x00000020
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x01ff14fe
@@ -79,39 +59,21 @@ proc pmic_init {} {
# $_CHIPNAME.axi mww [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
}
-# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
-# are in a debug session. This will force them (at next reboot) to program
-# the PMIC for keeping powered-on the debug unit during reset.
-proc set_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- $_CHIPNAME.dap apsel 0
- set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
- axi_non_secure_access
- $_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
- $_CHIPNAME.dap apcsw $old_csw
-}
-
-proc clear_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- $_CHIPNAME.dap apsel 0
- set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
- axi_non_secure_access
- $_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
- $_CHIPNAME.dap apcsw $old_csw
-}
-
# Wrap around init/shutdown. Typing CTRL-C will also invoke shutdown
rename init _init
proc init {} {
_init
- set_pmic_in_backup_reg
+ if { [eval chip_revision] != 0x2000 } {
+ # Use debug flag to signal to SPL and TF-A that we are in a debug
+ # session. This will force them (at next reboot) to program the PMIC
+ # for keeping powered-on the debug unit during reset.
+ set_debugflag_in_backup_reg
+ }
}
rename shutdown _shutdown
proc shutdown {} {
- catch { clear_pmic_in_backup_reg }
+ catch { clear_debugflag_in_backup_reg }
_shutdown
}
--
2.20.0

20
recipes-devtools/openocd/openocd-stm32mp_0.10.0.bb Normal file
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@ -0,0 +1,20 @@
SUMMARY = "Free and Open On-Chip Debugging, In-System Programming and Boundary-Scan Testing"
HOMEPAGE = "http://openocd.org"
LICENSE = "GPLv2"
LIC_FILES_CHKSUM = "file://COPYING;md5=b234ee4d69f5fce4486a80fdaf4a4263"
require openocd-stm32mp.inc
SRC_URI_prepend = " git://repo.or.cz/openocd.git;name=openocd "
SRCREV_FORMAT = "openocd"
SRCREV_openocd = "1afec4f561392539197fae678de4cd2ca01c127d"
PV = "0.10.0"
PR = "release.${SRCPV}"
SRC_URI += "file://0001-Add-support-of-STLINK-for-stm32mp1.patch"
SRC_URI += "file://0002-Add-support-for-silicon-revB.patch"
SRC_URI += "file://0003-Align-to-community-code-for-cache-coherency-and-rese.patch"
SRC_URI += "file://0004-Fix-init-command.patch"
SRC_URI += "file://0005-Add-CTI-plus-fixes.patch"