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OPENOCD: Support stlink traces, silicon rev.2.1, fix CSW 

Change-Id: I0d607eeee909e44e5d1e90db39bda30f03739819
This commit is contained in:
Romuald JEANNE 2020-06-17 16:58:25 +02:00
parent c3ccf68bd4
commit c9e37af629
11 changed files with 1826 additions and 8295 deletions
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4
recipes-devtools/openocd/openocd-stm32mp.inc
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@ -7,8 +7,8 @@ SRC_URI = " \
"
SRCREV_git2cl = "8373c9f74993e218a08819cbcdbab3f3564bbeba"
SRCREV_jimtcl = "a9bf5975fd0f89974d689a2d9ebd0873c8d64787"
SRCREV_libjaylink = "8645845c1abebd004e991ba9a7f808f4fd0c608b"
SRCREV_jimtcl = "0aa0fb4e3a38d38a49de9eb585d93d63a370dcf6"
SRCREV_libjaylink = "f73ad5e667ae8b26a52b847c603fdadaabf302a6"
S = "${WORKDIR}/git"

5378
recipes-devtools/openocd/openocd-stm32mp/0001-Add-support-of-STLINK-for-stm32mp1.patch
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1525
recipes-devtools/openocd/openocd-stm32mp/0001-M4-visible-rebase-on-b5d2b1224fed-fixes.patch Normal file
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458
recipes-devtools/openocd/openocd-stm32mp/0002-Add-support-for-silicon-revB.patch
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@ -1,458 +0,0 @@
From df2861a1384f3bf2ab8236ee51f8a5ff40e8f45b Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 12 Oct 2018 11:49:18 +0200
Subject: [PATCH] Add support for silicon revB
---
src/jtag/drivers/cmsis_dap_usb.c | 4 +-
src/jtag/drivers/libusb0_common.c | 7 ++
src/jtag/drivers/libusb1_common.c | 7 ++
tcl/board/stm32mp15x_dk2.cfg | 2 +-
tcl/board/stm32mp15x_ev1_jlink_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_jlink_swd.cfg | 2 +-
tcl/board/stm32mp15x_ev1_stlink_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_stlink_swd.cfg | 2 +-
tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg | 2 +-
tcl/board/stm32mp15x_ev1_ulink2_swd.cfg | 2 +-
tcl/target/stm32mp15x.cfg | 11 ++-
tcl/target/stm32mp15x_stpmic1.cfg | 113 +++++++++++++++++++++++++++++++
tcl/target/stm32mp15x_stpmu1.cfg | 113 -------------------------------
13 files changed, 145 insertions(+), 124 deletions(-)
diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index 4ee4836..9e723b5 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -895,9 +895,7 @@ static int cmsis_dap_init(void)
retval = cmsis_dap_swd_open();
if (retval != ERROR_OK)
return retval;
- }
-
- if (cmsis_dap_handle == NULL) {
+ } else {
/* Connect in JTAG mode */
if (!(cmsis_dap_handle->caps & INFO_CAPS_JTAG)) {
LOG_ERROR("CMSIS-DAP: JTAG not supported");
diff --git a/src/jtag/drivers/libusb0_common.c b/src/jtag/drivers/libusb0_common.c
index 1825543..04f88b6 100644
--- a/src/jtag/drivers/libusb0_common.c
+++ b/src/jtag/drivers/libusb0_common.c
@@ -68,6 +68,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
struct jtag_libusb_device_handle **out)
{
int retval = -ENODEV;
+ bool serial_mismatch = false;
struct jtag_libusb_device_handle *libusb_handle;
usb_init();
@@ -90,14 +91,20 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Device must be open to use libusb_get_string_descriptor_ascii. */
if (serial != NULL &&
!string_descriptor_equal(libusb_handle, dev->descriptor.iSerialNumber, serial)) {
+ serial_mismatch = true;
usb_close(libusb_handle);
continue;
}
*out = libusb_handle;
retval = 0;
+ serial_mismatch = false;
break;
}
}
+
+ if (serial_mismatch)
+ LOG_DEBUG("No device matches the serial string");
+
return retval;
}
diff --git a/src/jtag/drivers/libusb1_common.c b/src/jtag/drivers/libusb1_common.c
index a1db86f..0ec5fb9 100644
--- a/src/jtag/drivers/libusb1_common.c
+++ b/src/jtag/drivers/libusb1_common.c
@@ -72,6 +72,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
{
int cnt, idx, errCode;
int retval = ERROR_FAIL;
+ bool serial_mismatch = false;
struct jtag_libusb_device_handle *libusb_handle = NULL;
if (libusb_init(&jtag_libusb_context) < 0)
@@ -99,6 +100,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Device must be open to use libusb_get_string_descriptor_ascii. */
if (serial != NULL &&
!string_descriptor_equal(libusb_handle, dev_desc.iSerialNumber, serial)) {
+ serial_mismatch = true;
libusb_close(libusb_handle);
continue;
}
@@ -106,10 +108,15 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Success. */
*out = libusb_handle;
retval = ERROR_OK;
+ serial_mismatch = false;
break;
}
if (cnt >= 0)
libusb_free_device_list(devs, 1);
+
+ if (serial_mismatch)
+ LOG_DEBUG("No device matches the serial string");
+
return retval;
}
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg
index 82617c5..8d673fa 100644
--- a/tcl/board/stm32mp15x_dk2.cfg
+++ b/tcl/board/stm32mp15x_dk2.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
index 7d74fa6..665dc82 100644
--- a/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_jlink_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/jlink.cfg]
transport select jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
index 33e6ef5..7ca27af 100644
--- a/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_jlink_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/jlink.cfg]
transport select swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
index 6fb1e31..9364c92 100644
--- a/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_stlink_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
index 3c561c9..d8527ee 100644
--- a/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_stlink_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/stlink-dap.cfg]
transport select stlink_swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
index 6b10351..c7954ea 100644
--- a/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
+++ b/tcl/board/stm32mp15x_ev1_ulink2_jtag.cfg
@@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg]
transport select jtag
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
index 5495bc3..b00cc61 100644
--- a/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
+++ b/tcl/board/stm32mp15x_ev1_ulink2_swd.cfg
@@ -4,6 +4,6 @@ source [find interface/cmsis-dap.cfg]
transport select swd
-source [find target/stm32mp15x_stpmu1.cfg]
+source [find target/stm32mp15x_stpmic1.cfg]
reset_config srst_only
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 0def780..5d7e230 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -77,7 +77,7 @@ proc delayed_reset_halt_cpu0 { } {
global _CHIPNAME
global arp_reset_mode
- set rom_halt_pc 0x0000688c
+ set rom_halt_pc 0x000079ac
# only "reset halt" or "reset init"
if { 0 != [ string compare "$arp_reset_mode" "run" ] } {
@@ -85,6 +85,15 @@ proc delayed_reset_halt_cpu0 { } {
targets $_CHIPNAME.cpu0
arp_reset_default_handler post $_CHIPNAME.cpu0
+ # quick test for cut1.0, check bootrom
+ set v ""
+ ap0_non_secure_access
+ mem2array v 32 0x0000a000 1 phys
+ ap0_secure_access
+ if { $v(0) == 0x1e494610 } {
+ set rom_halt_pc 0x0000688c
+ }
+
poll on
catch { $_CHIPNAME.cpu0 arp_waitstate halted 1000 }
bp $rom_halt_pc 2 hw
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
new file mode 100644
index 0000000..c080441
--- /dev/null
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -0,0 +1,113 @@
+# script for stm32mp15x family with companion PMIC STPMIC1
+
+source [find target/stm32mp15x.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
+
+# Wait for expression to be true with a timeout of 200ms
+proc wait_state {condition} {
+ for {set t 0} {$t < 200} {incr t} {
+ if {[uplevel 1 $condition] == 0} {
+ return
+ }
+ sleep 1
+ }
+ return -code 1 "Timed out"
+}
+
+proc mrw_phys {reg} {
+ set value ""
+ mem2array value 32 $reg 1 phys
+ return $value(0)
+}
+
+proc mmw_phys {reg setbits clearbits} {
+ set old [mrw_phys $reg]
+ set new [expr ($old & ~$clearbits) | $setbits]
+ mww phys $reg $new
+}
+
+# Set mask_reset bits in PMIC to keep all powers on at next reset event
+# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
+# This procedure requires Secure memory access
+proc pmic_init {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ set RCC_BASE 0x50000000
+ set GPIO_BASE 0x54004000
+ set I2C_BASE 0x5c002000
+
+ # i2c @ 100kHz, rise 100ns, fall 100ns
+ # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz
+ set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b}
+
+ mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI)
+ mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck)
+
+ mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1
+ mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST
+ mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST
+
+ mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ)
+ mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF
+ mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain
+ mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed
+ mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down
+ mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6
+
+ set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3]
+ mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
+ mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1
+ mww phys [expr $I2C_BASE + 0x004] 0x02043066
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x18
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x0f
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x00
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
+ mww phys [expr $I2C_BASE + 0x028] 0x6f
+ wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
+ mww phys [expr $I2C_BASE + 0x01c] 0x00000020
+ mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe
+
+# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4)
+# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
+}
+
+# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
+# are in a debug session. This will force them (at next reboot) to program
+# the PMIC for keeping powered-on the debug unit during reset.
+proc set_pmic_in_backup_reg {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ mmw_phys 0x5c00a150 0x00010000 0x00000000
+}
+
+proc clear_pmic_in_backup_reg {} {
+ global _CHIPNAME
+
+ targets $_CHIPNAME.cpu0
+ $_CHIPNAME.dap apsel 0
+
+ mmw_phys 0x5c00a150 0x00000000 0x00010000
+}
+
+# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown
+rename init _init
+proc init {} {
+ _init
+ set_pmic_in_backup_reg
+}
+
+rename shutdown _shutdown
+proc shutdown {} {
+ clear_pmic_in_backup_reg
+ _shutdown
+}
diff --git a/tcl/target/stm32mp15x_stpmu1.cfg b/tcl/target/stm32mp15x_stpmu1.cfg
deleted file mode 100644
index 413abf2..0000000
--- a/tcl/target/stm32mp15x_stpmu1.cfg
+++ /dev/null
@@ -1,113 +0,0 @@
-# script for stm32mp15x family with companion PMIC STPMU1
-
-source [find target/stm32mp15x.cfg]
-
-$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
-
-# Wait for expression to be true with a timeout of 200ms
-proc wait_state {condition} {
- for {set t 0} {$t < 200} {incr t} {
- if {[uplevel 1 $condition] == 0} {
- return
- }
- sleep 1
- }
- return -code 1 "Timed out"
-}
-
-proc mrw_phys {reg} {
- set value ""
- mem2array value 32 $reg 1 phys
- return $value(0)
-}
-
-proc mmw_phys {reg setbits clearbits} {
- set old [mrw_phys $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww phys $reg $new
-}
-
-# Set mask_reset bits in PMIC to keep all powers on at next reset event
-# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
-# This procedure requires Secure memory access
-proc pmic_init {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- set RCC_BASE 0x50000000
- set GPIO_BASE 0x54004000
- set I2C_BASE 0x5c002000
-
- # i2c @ 100kHz, rise 100ns, fall 100ns
- # timing depending from HSIDIV[1:0] = {0 1 2 3} means hsi_ker_ck = {64 32 16 8} MHz
- set I2C_TIMING {0x10b17db5 0x00b07cb4 0x00503d58 0x00201d2b}
-
- mww phys [expr $RCC_BASE + 0x00c] 1; # set HSION = 1 (enable HSI)
- mww phys [expr $RCC_BASE + 0x0c0] 2; # set I2C46SRC[2:0] = 2 (hsi_ker_ck)
-
- mww phys [expr $RCC_BASE + 0x208] 4; # set I2C4EN = 1
- mww phys [expr $RCC_BASE + 0x188] 4; # assert I2C4RST
- mww phys [expr $RCC_BASE + 0x18c] 4; # deassert I2C4RST
-
- mww phys [expr $RCC_BASE + 0x210] 1; # set GPIOZEN = 1 (enable GPIOZ)
- mmw_phys [expr $GPIO_BASE + 0x00] 0x00000a00 0x00000f00; # GPIOZ4/5 AF
- mmw_phys [expr $GPIO_BASE + 0x04] 0x00000030 0x00000000; # GPIOZ4/5 open drain
- mmw_phys [expr $GPIO_BASE + 0x08] 0x00000000 0x00000f00; # GPIOZ4/5 low speed
- mmw_phys [expr $GPIO_BASE + 0x0c] 0x00000000 0x00000f00; # GPIOZ4/5 no pull-up/down
- mmw_phys [expr $GPIO_BASE + 0x20] 0x00660000 0x00ff0000; # GPIOZ4/5 AF6
-
- set hsidiv [expr [mrw_phys [expr $RCC_BASE + 0x018]] & 0x3]
- mww phys [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
- mww phys [expr $I2C_BASE + 0x000] 1; # set PE = 1
- mww phys [expr $I2C_BASE + 0x004] 0x02043066
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x18
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x0f
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x00
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- mww phys [expr $I2C_BASE + 0x028] 0x6f
- wait_state {expr {([mrw_phys [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
- mww phys [expr $I2C_BASE + 0x01c] 0x00000020
- mww phys [expr $I2C_BASE + 0x004] 0x01ff14fe
-
-# mww phys [expr $RCC_BASE + 0x20c] 4; # set I2C4EN = 0 (disable I2C4)
-# mww phys [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
-}
-
-# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
-# are in a debug session. This will force them (at next reboot) to program
-# the PMIC for keeping powered-on the debug unit during reset.
-proc set_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- mmw_phys 0x5c00a150 0x00010000 0x00000000
-}
-
-proc clear_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- targets $_CHIPNAME.cpu0
- $_CHIPNAME.dap apsel 0
-
- mmw_phys 0x5c00a150 0x00000000 0x00010000
-}
-
-# Wrap around init/shutdown. Attention: CTRL-C will not invoke shutdown
-rename init _init
-proc init {} {
- _init
- set_pmic_in_backup_reg
-}
-
-rename shutdown _shutdown
-proc shutdown {} {
- clear_pmic_in_backup_reg
- _shutdown
-}
--
2.7.4

295
recipes-devtools/openocd/openocd-stm32mp/0002-fixes-for-gcc-10-build-macos-build-CM4-halt-stlink-J.patch Normal file
View File

@ -0,0 +1,295 @@
From 2f115dde2ef6e6e72ff6439f27bc2e20f83b5d10 Mon Sep 17 00:00:00 2001
From: Antonio Borneo <borneo.antonio@gmail.com>
Date: Fri, 29 May 2020 17:22:33 +0200
Subject: [PATCH] fixes for gcc-10 build, macos build, CM4 halt, stlink J28 and
j37
Change-Id: If6c44bc94debc305aff1837d74b282f97e7c596a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
---
src/flash/nor/jtagspi.c | 19 +++++++++++++++----
src/flash/nor/nrf5.c | 10 +++++++---
src/jtag/drivers/bitbang.h | 2 +-
src/jtag/drivers/stlink_usb.c | 32 ++++++++++++++++++++++++++------
src/server/gdb_server.c | 2 +-
src/target/cortex_m.c | 21 +++++++++++++++++----
src/target/startup.tcl | 2 +-
tcl/target/stm32mp15x.cfg | 2 +-
8 files changed, 69 insertions(+), 21 deletions(-)
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index f6e311ab8..73b1c7a26 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -228,13 +228,16 @@ static int jtagspi_probe(struct flash_bank *bank)
return ERROR_OK;
}
-static void jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
+static int jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
{
uint8_t buf;
- if (jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, &buf, -8) == ERROR_OK) {
+ int err = jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, &buf, -8);
+ if (err == ERROR_OK) {
*status = buf;
/* LOG_DEBUG("status=0x%08" PRIx32, *status); */
}
+
+ return err;
}
static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
@@ -245,7 +248,11 @@ static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
do {
dt = timeval_ms() - t0;
- jtagspi_read_status(bank, &status);
+
+ int retval = jtagspi_read_status(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
if ((status & SPIFLASH_BSY_BIT) == 0) {
LOG_DEBUG("waited %" PRId64 " ms", dt);
return ERROR_OK;
@@ -262,7 +269,11 @@ static int jtagspi_write_enable(struct flash_bank *bank)
uint32_t status;
jtagspi_cmd(bank, SPIFLASH_WRITE_ENABLE, NULL, NULL, 0);
- jtagspi_read_status(bank, &status);
+
+ int retval = jtagspi_read_status(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
if ((status & SPIFLASH_WE_BIT) == 0) {
LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
return ERROR_FAIL;
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 8422589b8..5bef8487c 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -570,10 +570,14 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
{
- h_u32_to_be((uint8_t *)bf, variant);
- bf[4] = '\0';
- if (isalnum(bf[0]) && isalnum(bf[1]) && isalnum(bf[2]) && isalnum(bf[3]))
+ uint8_t b[4];
+
+ h_u32_to_be(b, variant);
+ if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
+ memcpy(bf, b, 4);
+ bf[4] = 0;
return true;
+ }
strcpy(bf, "xxxx");
return false;
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index edb779cad..bbbc693df 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -56,7 +56,7 @@ struct bitbang_interface {
void (*swdio_drive)(bool on);
};
-const struct swd_driver bitbang_swd;
+extern const struct swd_driver bitbang_swd;
extern bool swd_mode;
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 6c0601d0e..83bb89046 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -335,6 +335,7 @@ enum stlink_mode {
#define STLINK_F_HAS_AP_INIT BIT(7)
#define STLINK_F_HAS_DPBANKSEL BIT(8)
#define STLINK_F_HAS_RW8_512BYTES BIT(9)
+#define STLINK_F_FIX_CLOSE_AP BIT(10)
/* aliases */
#define STLINK_F_HAS_TARGET_VOLT STLINK_F_HAS_TRACE
@@ -379,6 +380,7 @@ static int stlink_swim_status(void *handle);
void stlink_dump_speed_map(const struct speed_map *map, unsigned int map_size);
static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map);
static int stlink_speed(void *handle, int khz, bool query);
+static int stlink_usb_open_ap(void *handle, unsigned short apsel);
/** */
static unsigned int stlink_usb_block(void *handle)
@@ -852,7 +854,7 @@ static int stlink_cmd_allow_retry(void *handle, const uint8_t *buf, int size)
res = stlink_usb_error_check(handle);
if (res == ERROR_WAIT && retries < MAX_WAIT_RETRIES) {
- useconds_t delay_us = (1<<retries++) * 1000;
+ unsigned int delay_us = (1<<retries++) * 1000;
LOG_DEBUG("stlink_cmd_allow_retry ERROR_WAIT, retry %d, delaying %u microseconds", retries, delay_us);
usleep(delay_us);
continue;
@@ -1050,6 +1052,10 @@ static int stlink_usb_version(void *handle)
if (h->version.jtag >= 28)
flags |= STLINK_F_HAS_AP_INIT;
+ /* API required to return proper error code on close AP from J29 */
+ if (h->version.jtag >= 29)
+ flags |= STLINK_F_FIX_CLOSE_AP;
+
/* Banked regs (DPv1 & DPv2) support from V2J32 */
/* API to read memory without address increment from V2J32 */
/* Memory R/W supports CSW from V2J32 */
@@ -1080,6 +1086,9 @@ static int stlink_usb_version(void *handle)
/* API required to init AP before any AP access */
flags |= STLINK_F_HAS_AP_INIT;
+ /* API required to return proper error code on close AP */
+ flags |= STLINK_F_FIX_CLOSE_AP;
+
/* Banked regs (DPv1 & DPv2) support from V3J2 */
/* API to read memory without address increment from V3J2 */
/* Memory R/W supports CSW from V3J2 */
@@ -3121,6 +3130,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
h->max_mem_packet = (1 << 10);
uint8_t buffer[4];
+ stlink_usb_open_ap(h, STLINK_HLA_AP_NUM);
err = stlink_usb_read_mem32(h, STLINK_HLA_AP_NUM, STLINK_HLA_CSW, CPUID, 4, buffer);
if (err == ERROR_OK) {
uint32_t cpuid = le_to_h_u32(buffer);
@@ -3225,7 +3235,12 @@ static int stlink_usb_close_access_port(void *handle, unsigned char ap_num)
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_CLOSE_AP_DBG;
h->cmdbuf[h->cmdidx++] = ap_num;
- return stlink_usb_xfer_errcheck(handle, h->databuf, 2);
+ /* ignore incorrectly returned error on bogus FW */
+ if (h->version.flags & STLINK_F_FIX_CLOSE_AP)
+ return stlink_usb_xfer_errcheck(handle, h->databuf, 2);
+ else
+ return stlink_usb_xfer_noerrcheck(handle, h->databuf, 2);
+
}
/** */
@@ -3343,13 +3358,13 @@ static int stlink_dap_get_and_clear_error(void)
return retval;
}
-/** */
-static int stlink_dap_open_ap(unsigned short apsel)
+static int stlink_usb_open_ap(void *handle, unsigned short apsel)
{
+ struct stlink_usb_handle_s *h = handle;
int retval;
/* nothing to do on old versions */
- if (!(stlink_dap_handle->version.flags & STLINK_F_HAS_AP_INIT))
+ if (!(h->version.flags & STLINK_F_HAS_AP_INIT))
return ERROR_OK;
if (apsel > DP_APSEL_MAX)
@@ -3358,7 +3373,7 @@ static int stlink_dap_open_ap(unsigned short apsel)
if (test_bit(apsel, opened_ap))
return ERROR_OK;
- retval = stlink_usb_init_access_port(stlink_dap_handle, apsel);
+ retval = stlink_usb_init_access_port(h, apsel);
if (retval != ERROR_OK)
return retval;
@@ -3367,6 +3382,11 @@ static int stlink_dap_open_ap(unsigned short apsel)
return ERROR_OK;
}
+static int stlink_dap_open_ap(unsigned short apsel)
+{
+ return stlink_usb_open_ap(stlink_dap_handle, apsel);
+}
+
/** */
static int stlink_dap_closeall_ap(void)
{
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 0ca4fa4ee..3f2632b03 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3489,7 +3489,7 @@ static int gdb_target_start(struct target *target, const char *port)
if (NULL == gdb_service)
return -ENOMEM;
- LOG_DEBUG("starting gdb server for %s on %s", target_name(target), port);
+ LOG_INFO("starting gdb server for %s on %s", target_name(target), port);
gdb_service->target = target;
gdb_service->core[0] = -1;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9a1f2b16f..dbd8ee088 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -710,11 +710,11 @@ static int cortex_m_soft_reset_halt(struct target *target)
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
- /* soft_reset_halt is deprecated on cortex_m as the same functionality
- * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
- * As this reset only used VC_CORERESET it would only ever reset the cortex_m
+ /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
+ * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
+ * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
* core, not the peripherals */
- LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
+ LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
/* Set C_DEBUGEN */
retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
@@ -2231,6 +2231,19 @@ int cortex_m_examine(struct target *target)
armv7m->debug_ap->tar_autoincr_block = (1 << 10);
}
+ /* Enable debug requests */
+ retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
+ if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
+ uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
+
+ retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
+ if (retval != ERROR_OK)
+ return retval;
+ cortex_m->dcb_dhcsr = dhcsr;
+ }
+
/* Configure trace modules */
retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
if (retval != ERROR_OK)
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 976cd2af5..164a0bad8 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -205,7 +205,7 @@ proc init_target_events {} {
foreach t $targets {
set_default_target_event $t gdb-flash-erase-start "reset init"
set_default_target_event $t gdb-flash-write-end "reset halt"
- set_default_target_event $t gdb-attach "halt"
+ set_default_target_event $t gdb-attach "halt 1000"
}
}
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 7f0d19c4d..f2ba94eec 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -114,7 +114,7 @@ $_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}
$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
$_CHIPNAME.ap1 configure -event examine-start {dap init}
$_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1}
--
2.26.2

1563
recipes-devtools/openocd/openocd-stm32mp/0003-Align-to-community-code-for-cache-coherency-and-rese.patch
View File

File diff suppressed because it is too large Load Diff

38
recipes-devtools/openocd/openocd-stm32mp/0004-Fix-init-command.patch
View File

@ -1,38 +0,0 @@
From 4b82bf719f303b77df9a2310f75da4ce81098b17 Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 9 Nov 2018 11:26:47 +0100
Subject: [PATCH 4/4] Fix init command
---
tcl/target/stm32mp15x_stpmic1.cfg | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
index a6446c640..2a32610fc 100644
--- a/tcl/target/stm32mp15x_stpmic1.cfg
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -85,13 +85,21 @@ proc pmic_init {} {
proc set_pmic_in_backup_reg {} {
global _CHIPNAME
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
$_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
+ $_CHIPNAME.dap apcsw $old_csw
}
proc clear_pmic_in_backup_reg {} {
global _CHIPNAME
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
$_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
+ $_CHIPNAME.dap apcsw $old_csw
}
# Wrap around init/shutdown. Typing CTRL-C will also invoke shutdown
--
2.19.1

424
recipes-devtools/openocd/openocd-stm32mp/0005-Add-CTI-plus-fixes.patch
View File

@ -1,424 +0,0 @@
From 4e6c43b1054ee6544f2f1758963c886fa03136ae Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Fri, 18 Jan 2019 16:52:07 +0100
Subject: [PATCH] Add CTI plus fixes
---
src/target/arm_cti.c | 4 +-
src/target/cortex_a.c | 39 ++++---
tcl/target/stm32mp15x.cfg | 162 ++++++++++++++++++++++++++++--
tcl/target/stm32mp15x_stpmic1.cfg | 62 +++---------
4 files changed, 196 insertions(+), 71 deletions(-)
diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c
index dcaf21e50..e6cb3cde3 100644
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@@ -173,7 +173,7 @@ int arm_cti_clear_channel(struct arm_cti *self, uint32_t channel)
return arm_cti_write_reg(self, CTI_APPCLEAR, CTI_CHNL(channel));
}
-static uint32_t cti_regs[26];
+static uint32_t cti_regs[28];
static const struct {
uint32_t offset;
@@ -206,6 +206,8 @@ static const struct {
{ CTI_CHOU_STATUS, "CHOUT", &cti_regs[23] },
{ CTI_APPSET, "APPSET", &cti_regs[24] },
{ CTI_APPCLEAR, "APPCLR", &cti_regs[25] },
+ { CTI_APPPULSE, "APPPULSE", &cti_regs[26] },
+ { CTI_INACK, "INACK", &cti_regs[27] },
};
static int cti_find_reg_offset(const char *name)
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index b281233ca..499dacc9b 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -201,6 +201,7 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
+ uint32_t dscr;
int retval;
/* lock memory-mapped access to debug registers to prevent
@@ -230,6 +231,16 @@ static int cortex_a_init_debug_access(struct target *target)
/* Resync breakpoint registers */
+ /* Enable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
+ if (retval != ERROR_OK)
+ return retval;
+
/* Since this is likely called from init or reset, update target state information*/
return cortex_a_poll(target);
}
@@ -768,19 +779,6 @@ static int cortex_a_halt(struct target *target)
if (retval != ERROR_OK)
return retval;
- /*
- * enter halting debug mode
- */
- retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
- if (retval != ERROR_OK)
- return retval;
-
int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
@@ -2977,7 +2975,20 @@ static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
static void cortex_a_deinit_target(struct target *target)
{
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct arm_dpm *dpm = &armv7a->dpm;
+ uint32_t dscr;
+ int retval;
+
+ if (target_was_examined(target)) {
+ /* Disable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval == ERROR_OK)
+ mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR,
+ dscr & ~DSCR_HALT_DBG_MODE);
+ }
free(cortex_a->brp_list);
free(dpm->dbp);
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 0d10021ef..992975f87 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -47,6 +47,69 @@ if { [using_jtag] } {
swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# in smp mode, if one core is halted the event 'halted' get fired for the selected core only.
+# so the halt event remains unacknowledged for other cores.
+proc cti_prepare_restart_all {} {
+ global _CHIPNAME
+
+ cti_prepare_restart cti0
+ cti_prepare_restart cti1
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ cti_prepare_restart cti2
+ }
+}
+
+proc cti_prepare_restart {cti} {
+ global _CHIPNAME
+
+ # Acknowlodge EDBGRQ at TRIGOUT0
+ $_CHIPNAME.$cti write INACK 0x01
+ $_CHIPNAME.$cti write INACK 0x00
+}
+
+proc cti_start {} {
+ global _CHIPNAME
+
+ # Configure both Cortex-A CTIs to halt each other
+ # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+ $_CHIPNAME.cti0 write INEN0 0x1
+ $_CHIPNAME.cti1 write INEN0 0x1
+ $_CHIPNAME.cti0 write OUTEN0 0x1
+ $_CHIPNAME.cti1 write OUTEN0 0x1
+
+ $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
+ $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
+
+ # enable CTIs
+ $_CHIPNAME.cti0 enable on
+ $_CHIPNAME.cti1 enable on
+
+ # Cortex-M4 CTI configuration (enable CM4.CTI and join same CTM channels)
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ $_CHIPNAME.cti2 write INEN0 0x1
+ $_CHIPNAME.cti2 write OUTEN0 0x1
+ $_CHIPNAME.cpu2 configure -event halted { cti_prepare_restart_all }
+ $_CHIPNAME.cti2 enable on
+ }
+}
+
+proc cti_stop {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.cti0 enable off
+ $_CHIPNAME.cti1 enable off
+
+ if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ $_CHIPNAME.cti2 enable off
+ }
+}
+
+cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
+cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
+cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
+cti create $_CHIPNAME.cti2 -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0xE00D0000
target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
@@ -83,8 +146,23 @@ $_CHIPNAME.cpu0 configure -gdb-port [expr $_GDB_PORT + 1]
$_CHIPNAME.cpu1 configure -gdb-port [expr $_GDB_PORT + 2]
$_CHIPNAME.cpu2 configure -gdb-port [expr $_GDB_PORT + 0]
+$_CHIPNAME.cpu0 configure -event reset-assert-pre { pre_reset_halt_cpu0 }
$_CHIPNAME.cpu0 configure -event reset-deassert-post { delayed_reset_halt_cpu0 }
+proc pre_reset_halt_cpu0 {} {
+ global _CHIPNAME
+ global ENG_MODE
+ global arp_reset_mode
+ global workaround_revision_0x2000
+
+ catch { unset workaround_revision_0x2000 }
+ if { ([eval chip_revision] == 0x2000) && ![info exists ENG_MODE] && ([string compare "$arp_reset_mode" "run"] != 0) } {
+ set workaround_revision_0x2000 1
+ set_debugflag_in_backup_reg
+ }
+ arp_reset_default_handler pre $_CHIPNAME.cpu0
+}
+
# In production mode, reset-halt stops in bootrom when only
# cpu0 can be attached due to security mode.
# Set a breakpoint to stop cpu0 when cpu1 can be attached too.
@@ -92,10 +170,27 @@ proc delayed_reset_halt_cpu0 { } {
global _CHIPNAME
global ENG_MODE
global arp_reset_mode
+ global workaround_revision_0x2000
if { [info exists ENG_MODE] || ([string compare "$arp_reset_mode" "run"] == 0) } {
# default reset-deassert-post handler
arp_reset_default_handler post $_CHIPNAME.cpu0
+ } elseif { [info exists workaround_revision_0x2000] } {
+ unset workaround_revision_0x2000
+ cortex_a smp_off
+ $_CHIPNAME.cpu0 arp_examine
+ catch { $_CHIPNAME.cpu0 arp_waitstate halted 500 }
+ halt
+ cortex_a smp_on
+ catch { clear_debugflag_in_backup_reg }
+
+ # incr PC if insn is "BKPT 5"
+ set pc [ocd_reg pc]
+ regsub {pc[^:]*: } $pc "" pc
+ if { ([expr $pc & 3] == 0) && ([mrw $pc] == 0xe1200075) } {
+ reg pc [expr $pc + 4]
+ }
+ arp_reset_halt_default_handler $_CHIPNAME.cpu0
} else {
# only in production mode for "reset halt" or "reset init"
cortex_a smp_off
@@ -103,12 +198,7 @@ proc delayed_reset_halt_cpu0 { } {
arp_reset_default_handler post $_CHIPNAME.cpu0
set rom_halt_pc 0x000079ac
- # quick test for rev.A, check bootrom
- set v ""
- axi_non_secure_access
- $_CHIPNAME.axi mem2array v 32 0x0000a000 1 phys
- axi_secure_access
- if { $v(0) == 0x1e494610 } {
+ if { [eval chip_revision] == 0x1000 } {
set rom_halt_pc 0x0000688c
}
@@ -176,6 +266,57 @@ $_CHIPNAME.cpu0 configure -event gdb-detach { catch { resume }; clients_dec_and_
$_CHIPNAME.cpu1 configure -event gdb-detach { catch { resume }; clients_dec_and_shutdown }
$_CHIPNAME.cpu2 configure -event gdb-detach { catch { resume }; clients_dec_and_shutdown }
+proc chip_revision {} {
+ global _CHIPNAME
+
+ # read DBGMCU_IDC
+ $_CHIPNAME.ap1 mem2array v 32 0xe0081000 1
+ return [expr $v(0) >> 16]
+}
+
+proc $_CHIPNAME.axi_mrw {reg} {
+ global _CHIPNAME
+
+ set value ""
+ $_CHIPNAME.axi mem2array value 32 $reg 1
+ return $value(0)
+}
+
+proc $_CHIPNAME.axi_mmw {reg setbits clearbits} {
+ global _CHIPNAME
+
+ set old [$_CHIPNAME.axi_mrw $reg]
+ set new [expr ($old & ~$clearbits) | $setbits]
+ $_CHIPNAME.axi mww $reg $new
+}
+
+# Backup registers are battery powered and keep the value both across power
+# cycles and reset pulses on NRST_CORE pin.
+# Bit 16 in TAMP_BACKUP_REGISTER(20) is used as special signal between the
+# debugger and the application across a reset.
+proc set_debugflag_in_backup_reg {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_secure_access
+ catch { $_CHIPNAME.axi_mmw 0x50001000 0x00000100 0x00000000 }
+ catch { $_CHIPNAME.axi_mmw 0x50000208 0x00000100 0x00000000 }
+ axi_non_secure_access
+ $_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
+ $_CHIPNAME.dap apcsw $old_csw
+}
+
+proc clear_debugflag_in_backup_reg {} {
+ global _CHIPNAME
+
+ $_CHIPNAME.dap apsel 0
+ set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
+ axi_non_secure_access
+ $_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
+ $_CHIPNAME.dap apcsw $old_csw
+}
+
proc axi_secure_access {} {
global _CHIPNAME
@@ -191,3 +332,12 @@ proc axi_non_secure_access {} {
}
axi_secure_access
+
+rename init __init
+proc init {} {
+ __init
+ if { [eval chip_revision] == 0x2000 } {
+ # srst pulse causes a reset of the debug port
+ reset_config srst_pulls_trst
+ }
+}
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
index 2a32610fc..16cf9b0ae 100644
--- a/tcl/target/stm32mp15x_stpmic1.cfg
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -2,7 +2,7 @@
source [find target/stm32mp15x.cfg]
-$_CHIPNAME.cpu0 configure -event reset-halt { catch { pmic_init }}
+$_CHIPNAME.cpu0 configure -event reset-halt { catch { if { [eval chip_revision] != 0x2000 } { pmic_init } } }
# Wait for expression to be true with a timeout of 200ms
proc wait_state {condition} {
@@ -15,24 +15,8 @@ proc wait_state {condition} {
return -code 1 "Timed out"
}
-proc $_CHIPNAME.axi_mrw {reg} {
- global _CHIPNAME
-
- set value ""
- $_CHIPNAME.axi mem2array value 32 $reg 1
- return $value(0)
-}
-
-proc $_CHIPNAME.axi_mmw {reg setbits clearbits} {
- global _CHIPNAME
-
- set old [$_CHIPNAME.axi_mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- $_CHIPNAME.axi mww $reg $new
-}
-
-# Set mask_reset bits in PMIC to keep all powers on at next reset event
-# Only the mask_reset of SD-card power is not enabled to guarantee boot from SD
+# Set mask_reset bits in PMIC to keep VDD and VDD_CORE on at next reset event
+# Mask_reset for SD-card power "must" not be enabled to guarantee boot from SD
# This procedure requires Secure memory access
proc pmic_init {} {
global _CHIPNAME
@@ -62,15 +46,11 @@ proc pmic_init {} {
set hsidiv [expr [$_CHIPNAME.axi_mrw [expr $RCC_BASE + 0x018]] & 0x3]
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x010] [lindex $I2C_TIMING $hsidiv]
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x000] 1; # set PE = 1
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x02043066
+ $_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x02023066
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x18
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x0f
- wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x00
- wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000002) == 0}}; # wait TXIS
- $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x6f
+ $_CHIPNAME.axi mww [expr $I2C_BASE + 0x028] 0x05
wait_state {expr {([$_CHIPNAME.axi_mrw [expr $I2C_BASE + 0x018]] & 0x00000020) == 0}}; # wait STOPF
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x01c] 0x00000020
$_CHIPNAME.axi mww [expr $I2C_BASE + 0x004] 0x01ff14fe
@@ -79,39 +59,21 @@ proc pmic_init {} {
# $_CHIPNAME.axi mww [expr $RCC_BASE + 0x214] 1; # set GPIOZEN = 0 (disable GPIOZ)
}
-# Set bit 16 in TAMP_BACKUP_REGISTER(20) to signal to SPL and TF-A that we
-# are in a debug session. This will force them (at next reboot) to program
-# the PMIC for keeping powered-on the debug unit during reset.
-proc set_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- $_CHIPNAME.dap apsel 0
- set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
- axi_non_secure_access
- $_CHIPNAME.axi_mmw 0x5c00a150 0x00010000 0x00000000
- $_CHIPNAME.dap apcsw $old_csw
-}
-
-proc clear_pmic_in_backup_reg {} {
- global _CHIPNAME
-
- $_CHIPNAME.dap apsel 0
- set old_csw [lindex [ocd_$_CHIPNAME.dap apcsw] 4]
- axi_non_secure_access
- $_CHIPNAME.axi_mmw 0x5c00a150 0x00000000 0x00010000
- $_CHIPNAME.dap apcsw $old_csw
-}
-
# Wrap around init/shutdown. Typing CTRL-C will also invoke shutdown
rename init _init
proc init {} {
_init
- set_pmic_in_backup_reg
+ if { [eval chip_revision] != 0x2000 } {
+ # Use debug flag to signal to SPL and TF-A that we are in a debug
+ # session. This will force them (at next reboot) to program the PMIC
+ # for keeping powered-on the debug unit during reset.
+ set_debugflag_in_backup_reg
+ }
}
rename shutdown _shutdown
proc shutdown {} {
- catch { clear_pmic_in_backup_reg }
+ catch { clear_debugflag_in_backup_reg }
_shutdown
}
--
2.20.0

251
recipes-devtools/openocd/openocd-stm32mp/0006-Support-single-core-align-access-with-mmu-off-plus-f.patch
View File

@ -1,251 +0,0 @@
From b411d805477bd67856403c73bad41534bcf2aa31 Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Mon, 20 May 2019 17:25:18 +0200
Subject: [PATCH] Support single-core, align access with mmu off, plus fixes
---
src/target/adi_v5_stlink.c | 12 --------
src/target/cortex_a.c | 43 ++++++++++++++++++++++++++---
src/target/cortex_m.c | 8 +++---
tcl/target/stm32mp15x.cfg | 56 ++++++++++++++++++++++++++++----------
4 files changed, 84 insertions(+), 35 deletions(-)
diff --git a/src/target/adi_v5_stlink.c b/src/target/adi_v5_stlink.c
index 9e7ab0f64..fd4a4e28a 100644
--- a/src/target/adi_v5_stlink.c
+++ b/src/target/adi_v5_stlink.c
@@ -120,18 +120,6 @@ static int stlink_connect(struct adiv5_dap *dap)
LOG_INFO("stlink_connect(%sconnect)", dap->do_reconnect ? "re" : "");
- /* Check if we should reset srst already when connecting, but not if reconnecting. */
- if (!dap->do_reconnect) {
- enum reset_types jtag_reset_config = jtag_get_reset_config();
-
- if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
- if (jtag_reset_config & RESET_SRST_NO_GATING)
- adapter_assert_reset();
- else
- LOG_WARNING("\'srst_nogate\' reset_config option is required");
- }
- }
-
dap->do_reconnect = false;
dap_invalidate_cache(dap);
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 499dacc9b..9f6f3d5d2 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1220,6 +1220,8 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
retval = cortex_a_poll(target);
if (retval != ERROR_OK)
return retval;
+ if (target->state == TARGET_HALTED)
+ break;
if (timeval_ms() > then + 1000) {
LOG_ERROR("timeout waiting for target halt");
return ERROR_FAIL;
@@ -2017,7 +2019,8 @@ static int cortex_a_write_cpu_memory_slow(struct target *target,
{
/* Writes count objects of size size from *buffer. Old value of DSCR must
* be in *dscr; updated to new value. This is slow because it works for
- * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
+ * non-word-sized objects. Avoid unaligned accesses as they do not work
+ * on memory address space without "Normal" attribute. If size == 4 and
* the address is aligned, cortex_a_write_cpu_memory_fast should be
* preferred.
* Preconditions:
@@ -2174,7 +2177,22 @@ static int cortex_a_write_cpu_memory(struct target *target,
/* We are doing a word-aligned transfer, so use fast mode. */
retval = cortex_a_write_cpu_memory_fast(target, count, buffer, &dscr);
} else {
- /* Use slow path. */
+ /* Use slow path. Adjust size for aligned accesses */
+ switch (address % 4) {
+ case 1:
+ case 3:
+ count *= size;
+ size = 1;
+ break;
+ case 2:
+ if (size == 4) {
+ count *= 2;
+ size = 2;
+ }
+ case 0:
+ default:
+ break;
+ }
retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
}
@@ -2260,7 +2278,8 @@ static int cortex_a_read_cpu_memory_slow(struct target *target,
{
/* Reads count objects of size size into *buffer. Old value of DSCR must be
* in *dscr; updated to new value. This is slow because it works for
- * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
+ * non-word-sized objects. Avoid unaligned accesses as they do not work
+ * on memory address space without "Normal" attribute. If size == 4 and
* the address is aligned, cortex_a_read_cpu_memory_fast should be
* preferred.
* Preconditions:
@@ -2476,7 +2495,23 @@ static int cortex_a_read_cpu_memory(struct target *target,
/* We are doing a word-aligned transfer, so use fast mode. */
retval = cortex_a_read_cpu_memory_fast(target, count, buffer, &dscr);
} else {
- /* Use slow path. */
+ /* Use slow path. Adjust size for aligned accesses */
+ switch (address % 4) {
+ case 1:
+ case 3:
+ count *= size;
+ size = 1;
+ break;
+ case 2:
+ if (size == 4) {
+ count *= 2;
+ size = 2;
+ }
+ break;
+ case 0:
+ default:
+ break;
+ }
retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
}
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 79975aa89..9b962192f 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -532,21 +532,21 @@ static int cortex_m_poll(struct target *target)
if (cortex_m->dcb_dhcsr & S_HALT) {
target->state = TARGET_HALTED;
- if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
+ if (prev_target_state != TARGET_HALTED) {
retval = cortex_m_debug_entry(target);
if (retval != ERROR_OK)
return retval;
+ }
+ if (prev_target_state == TARGET_RUNNING || prev_target_state == TARGET_RESET) {
if (arm_semihosting(target, &retval) != 0)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
+
if (prev_target_state == TARGET_DEBUG_RUNNING) {
LOG_DEBUG(" ");
- retval = cortex_m_debug_entry(target);
- if (retval != ERROR_OK)
- return retval;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 992975f87..f95070c3c 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -54,8 +54,10 @@ proc cti_prepare_restart_all {} {
global _CHIPNAME
cti_prepare_restart cti0
- cti_prepare_restart cti1
- if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ if { [$_CHIPNAME.cpu1 was_examined] } {
+ cti_prepare_restart cti1
+ }
+ if { [$_CHIPNAME.cpu2 was_examined] } {
cti_prepare_restart cti2
}
}
@@ -71,22 +73,22 @@ proc cti_prepare_restart {cti} {
proc cti_start {} {
global _CHIPNAME
- # Configure both Cortex-A CTIs to halt each other
+ # Configure CTIs to halt the other cores
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
$_CHIPNAME.cti0 write INEN0 0x1
- $_CHIPNAME.cti1 write INEN0 0x1
$_CHIPNAME.cti0 write OUTEN0 0x1
- $_CHIPNAME.cti1 write OUTEN0 0x1
-
- $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
- $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
-
- # enable CTIs
+ $_CHIPNAME.cpu0 configure -event halted { cti_prepare_restart_all }
$_CHIPNAME.cti0 enable on
- $_CHIPNAME.cti1 enable on
+
+ if { [$_CHIPNAME.cpu1 was_examined] } {
+ $_CHIPNAME.cti1 write INEN0 0x1
+ $_CHIPNAME.cti1 write OUTEN0 0x1
+ $_CHIPNAME.cpu1 configure -event halted { cti_prepare_restart_all }
+ $_CHIPNAME.cti1 enable on
+ }
# Cortex-M4 CTI configuration (enable CM4.CTI and join same CTM channels)
- if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
+ if { [$_CHIPNAME.cpu2 was_examined] } {
$_CHIPNAME.cti2 write INEN0 0x1
$_CHIPNAME.cti2 write OUTEN0 0x1
$_CHIPNAME.cpu2 configure -event halted { cti_prepare_restart_all }
@@ -98,8 +100,9 @@ proc cti_stop {} {
global _CHIPNAME
$_CHIPNAME.cti0 enable off
- $_CHIPNAME.cti1 enable off
-
+ if { [$_CHIPNAME.cpu1 was_examined] } {
+ $_CHIPNAME.cti1 enable off
+ }
if { [$_CHIPNAME.cpu2 curstate] ne "examine deferred" } {
$_CHIPNAME.cti2 enable off
}
@@ -111,7 +114,7 @@ cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
cti create $_CHIPNAME.cti2 -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0xE00D0000
-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0xE00D2000 -defer-examine
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
@@ -228,6 +231,29 @@ adapter_khz $_CLOCK_FREQ
adapter_nsrst_assert_width 200
adapter_nsrst_delay 200
+$_CHIPNAME.ap1 configure -event examine-end {
+ global _CHIPNAME
+
+ # only on dual-cores chips, examine the second core
+ $_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
+ if {$cpu1_prsr(0) & 1} {
+ $_CHIPNAME.cpu1 invoke-event examine-start
+ set err [catch "$_CHIPNAME.cpu1 arp_examine"]
+ if { $err } {
+ $_CHIPNAME.cpu1 invoke-event examine-fail
+ } else {
+ $_CHIPNAME.cpu1 invoke-event examine-end
+ }
+ }
+}
+
+$_CHIPNAME.cpu1 configure -event examine-end {
+ global _CHIPNAME
+
+ if {[$_CHIPNAME.cpu1 was_examined] && [$_CHIPNAME.cpu0 curstate] eq "halted"} {
+ halt
+ }
+}
set clients_num 0
proc clients_inc {} {
--
2.21.0

171
recipes-devtools/openocd/openocd-stm32mp/0007-Add-support-for-stlink-traces-and-silicon-rev.2.1-fi.patch
View File

@ -1,171 +0,0 @@
From d4528c355d28480ceb546f9dcee00f28a01bc5c2 Mon Sep 17 00:00:00 2001
From: Antonio Borneo <antonio.borneo@st.com>
Date: Mon, 14 Oct 2019 13:02:11 +0200
Subject: [PATCH] Add support for stlink traces and silicon rev.2.1, fix CSW
---
src/jtag/drivers/stlink_usb.c | 39 +++++++++++++++++--------------
src/target/armv8.c | 3 ++-
tcl/target/stm32mp15x.cfg | 17 ++++++++++----
tcl/target/stm32mp15x_stpmic1.cfg | 5 ++--
4 files changed, 38 insertions(+), 26 deletions(-)
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index b27d04318..a4944e7bd 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -2937,7 +2937,7 @@ int stlink_dap_dap_write(unsigned short dap_port, unsigned short addr, uint32_t
*
* This workaround leverage the CSW caching operated by ST-Link. At every
* memory R/W, ST-Link computes the new CSW value based on word size. If it
- * match the previous CSW value than it has wrote in CSW register, ST-Link
+ * match the previous CSW value that it has wrote in CSW register, ST-Link
* will not write in CSW register again.
*
* Here we track the word size used in the last memory R/W. If it does not
@@ -2956,18 +2956,6 @@ static int stlink_dap_set_csw(struct adiv5_ap *ap, uint32_t size, bool addrinc)
ap_num = ap->ap_num;
struct stlink_usb_handle_s *h = stlink_dap_handle;
- if ((h->version.stlink == 2 && h->version.jtag >= 32) || (h->version.stlink == 3 && h->version.jtag >= 2)) {
- csw = ap->csw_default;
- if (csw != (ap->csw_value & ~(CSW_SIZE_MASK | CSW_ADDRINC_MASK))) {
- retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
- if (retval != ERROR_OK) {
- ap->csw_value = 0;
- return retval;
- }
- ap->csw_value = csw;
- }
- return ERROR_OK;
- }
switch (size) {
case 2:
@@ -2991,12 +2979,14 @@ static int stlink_dap_set_csw(struct adiv5_ap *ap, uint32_t size, bool addrinc)
}
csw |= ap->csw_default;
- if (ap_csw_size_cached[ap_num] != size) {
- ap_csw_size_cached[ap_num] = size;
+ if ((h->version.stlink == 2 && h->version.jtag < 32) || (h->version.stlink == 3 && h->version.jtag < 2)) {
+ if (ap_csw_size_cached[ap_num] != size) {
+ ap_csw_size_cached[ap_num] = size;
- /* The mem read below will change CSW */
- ap->csw_value = 0;
- stlink_usb_read_ap_mem(stlink_dap_handle, ap_num, 0x00000000, size, 1, dummy);
+ /* The mem read below will change CSW */
+ ap->csw_value = 0;
+ stlink_usb_read_ap_mem(stlink_dap_handle, ap_num, 0x00000000, size, 1, dummy);
+ }
}
if (ap->csw_value != csw) {
@@ -3324,6 +3314,17 @@ static int stlink_dap_quit(void)
return stlink_usb_close(stlink_dap_handle);
}
+static int stlink_dap_config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
+ uint32_t port_size, unsigned int *trace_freq)
+{
+ return stlink_config_trace(stlink_dap_handle, enabled, pin_protocol, port_size, trace_freq);
+}
+
+static int stlink_dap_trace_read(uint8_t *buf, size_t *size)
+{
+ return stlink_usb_trace_read(stlink_dap_handle, buf, size);
+}
+
COMMAND_HANDLER(stlink_dap_serial_command)
{
LOG_DEBUG("stlink_dap_serial_command");
@@ -3416,4 +3417,6 @@ struct jtag_interface stlink_dap_interface = {
.khz = stlink_dap_khz,
.init = stlink_dap_init,
.quit = stlink_dap_quit,
+ .config_trace = stlink_dap_config_trace,
+ .poll_trace = stlink_dap_trace_read,
};
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 39ce7e129..c3e3460fc 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1670,7 +1670,8 @@ const struct command_registration armv8_command_handlers[] = {
const char *armv8_get_gdb_arch(struct target *target)
{
- return "aarch64";
+ struct arm *arm = target_to_arm(target);
+ return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
}
int armv8_get_gdb_reg_list(struct target *target,
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index f95070c3c..ec9f279f4 100644
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -159,7 +159,8 @@ proc pre_reset_halt_cpu0 {} {
global workaround_revision_0x2000
catch { unset workaround_revision_0x2000 }
- if { ([eval chip_revision] == 0x2000) && ![info exists ENG_MODE] && ([string compare "$arp_reset_mode" "run"] != 0) } {
+ set chip_rev [expr [chip_revision] & 0xfffe]
+ if { ($chip_rev == 0x2000) && ![info exists ENG_MODE] && ([string compare "$arp_reset_mode" "run"] != 0) } {
set workaround_revision_0x2000 1
set_debugflag_in_backup_reg
}
@@ -200,9 +201,14 @@ proc delayed_reset_halt_cpu0 { } {
targets $_CHIPNAME.cpu0
arp_reset_default_handler post $_CHIPNAME.cpu0
- set rom_halt_pc 0x000079ac
- if { [eval chip_revision] == 0x1000 } {
- set rom_halt_pc 0x0000688c
+ switch [chip_revision] {
+ 0x1000
+ { set rom_halt_pc 0x0000688c }
+ 0x2000
+ { set rom_halt_pc 0x000079ac }
+ 0x2001 -
+ default
+ { set rom_halt_pc 0x00000000 }
}
poll on
@@ -362,7 +368,8 @@ axi_secure_access
rename init __init
proc init {} {
__init
- if { [eval chip_revision] == 0x2000 } {
+ set chip_rev [expr [chip_revision] & 0xfffe]
+ if { $chip_rev == 0x2000 } {
# srst pulse causes a reset of the debug port
reset_config srst_pulls_trst
}
diff --git a/tcl/target/stm32mp15x_stpmic1.cfg b/tcl/target/stm32mp15x_stpmic1.cfg
index 16cf9b0ae..ac57ba171 100644
--- a/tcl/target/stm32mp15x_stpmic1.cfg
+++ b/tcl/target/stm32mp15x_stpmic1.cfg
@@ -2,7 +2,7 @@
source [find target/stm32mp15x.cfg]
-$_CHIPNAME.cpu0 configure -event reset-halt { catch { if { [eval chip_revision] != 0x2000 } { pmic_init } } }
+$_CHIPNAME.cpu0 configure -event reset-halt { catch { set chip_rev [expr [chip_revision] & 0xfffe]; if { $chip_rev != 0x2000 } { pmic_init } } }
# Wait for expression to be true with a timeout of 200ms
proc wait_state {condition} {
@@ -63,7 +63,8 @@ proc pmic_init {} {
rename init _init
proc init {} {
_init
- if { [eval chip_revision] != 0x2000 } {
+ set chip_rev [expr [chip_revision] & 0xfffe]
+ if { $chip_rev != 0x2000 } {
# Use debug flag to signal to SPL and TF-A that we are in a debug
# session. This will force them (at next reboot) to program the PMIC
# for keeping powered-on the debug unit during reset.
--
2.25.0

14
recipes-devtools/openocd/openocd-stm32mp_0.10.0.bb
View File

@ -8,15 +8,9 @@ require openocd-stm32mp.inc
SRC_URI_prepend = " git://repo.or.cz/openocd.git;name=openocd "
SRCREV_FORMAT = "openocd"
SRCREV_openocd = "1afec4f561392539197fae678de4cd2ca01c127d"
SRCREV_openocd = "b5d2b1224fed3909aa3314339611ac5ac7ab0f82"
PV = "0.10.0"
PR = "release.${SRCPV}"
PV = "0.10.0-release.${SRCPV}"
SRC_URI += "file://0001-Add-support-of-STLINK-for-stm32mp1.patch"
SRC_URI += "file://0002-Add-support-for-silicon-revB.patch"
SRC_URI += "file://0003-Align-to-community-code-for-cache-coherency-and-rese.patch"
SRC_URI += "file://0004-Fix-init-command.patch"
SRC_URI += "file://0005-Add-CTI-plus-fixes.patch"
SRC_URI += "file://0006-Support-single-core-align-access-with-mmu-off-plus-f.patch"
SRC_URI += "file://0007-Add-support-for-stlink-traces-and-silicon-rev.2.1-fi.patch"
SRC_URI += "file://0001-M4-visible-rebase-on-b5d2b1224fed-fixes.patch"
SRC_URI += "file://0002-fixes-for-gcc-10-build-macos-build-CM4-halt-stlink-J.patch"