U-BOOT-STM32MP: update to v2020.10-stm32mp-r2

Change-Id: I4e58162aafc5f6dcd94793dae7018bc03ae136e9

recipes-bsp/u-boot/u-boot-stm32mp-common_2020.10.inc

@@ -21,6 +21,13 @@ SRC_URI += "\
     file://0004-ARM-v2020.10-stm32mp-r1-DEVICETREE.patch \
     file://0005-ARM-v2020.10-stm32mp-r1-CONFIG.patch \
     \
+    file://0006-ARM-v2020.10-stm32mp-r1.1.patch \
+    file://0007-ARM-v2020.10-stm32mp-r2-MACHINE.patch \
+    file://0008-ARM-v2020.10-stm32mp-r2-BOARD.patch \
+    file://0009-ARM-v2020.10-stm32mp-r2-MISC-DRIVERS.patch \
+    file://0010-ARM-v2020.10-stm32mp-r2-DEVICETREE.patch \
+    file://0011-ARM-v2020.10-stm32mp-r2-CONFIG.patch \
+    \
     file://0099-Add-external-var-to-allow-build-of-new-devicetree-fi.patch \
 "
 
@@ -29,7 +36,7 @@ SRC_URI += "${@bb.utils.contains('ST_UBOOT_DEBUG_TRACE', '1', '', 'file://0098-s
 
 U_BOOT_VERSION = "v2020.10"
 U_BOOT_SUBVERSION = "stm32mp"
-U_BOOT_RELEASE = "r1"
+U_BOOT_RELEASE = "r2"
 PV = "${U_BOOT_VERSION}-${U_BOOT_SUBVERSION}-${U_BOOT_RELEASE}"
 
 ARCHIVER_ST_BRANCH = "${U_BOOT_VERSION}-${U_BOOT_SUBVERSION}"
@@ -45,7 +52,7 @@ S = "${WORKDIR}/git"
 BBCLASSEXTEND = "devupstream:target"
 
 SRC_URI_class-devupstream = "git://github.com/STMicroelectronics/u-boot.git;protocol=https;branch=${ARCHIVER_ST_BRANCH}"
-SRCREV_class-devupstream = "d2c99cb7e5b7dc74236f67fcced156956155cd71"
+SRCREV_class-devupstream = "6fde82adf71ebad4b16d99f76ed69abfd9cfaf42"
 
 # ---------------------------------
 # Configure default preference to manage dynamic selection between tarball and github

recipes-bsp/u-boot/u-boot-stm32mp/0006-ARM-v2020.10-stm32mp-r1.1.patch

@@ -0,0 +1,340 @@
+From 77f5697167358c634bee38a98ad059f1b6b33dbf Mon Sep 17 00:00:00 2001
+From: Romuald JEANNE <romuald.jeanne@st.com>
+Date: Tue, 25 May 2021 20:18:25 +0200
+Subject: [PATCH 6/7] ARM v2020.10-stm32mp-r1.1
+
+Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
+---
+ Makefile                                      |   2 +-
+ .../mach-stm32mp/cmd_stm32prog/stm32prog.c    |  14 +-
+ .../mach-stm32mp/cmd_stm32prog/stm32prog.h    |   5 -
+ .../cmd_stm32prog/stm32prog_serial.c          | 163 +++---------------
+ 4 files changed, 33 insertions(+), 151 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 6bd0841c4b..59493deed3 100644
+--- a/Makefile
++++ b/Makefile
+@@ -3,7 +3,7 @@
+ VERSION = 2020
+ PATCHLEVEL = 10
+ SUBLEVEL =
+-EXTRAVERSION = -stm32mp-r1
++EXTRAVERSION = -stm32mp-r1.1
+ NAME =
+ 
+ # *DOCUMENTATION*
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+index 627bb52a11..7cd31462ba 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+@@ -368,23 +368,24 @@ static int parse_flash_layout(struct stm32prog_data *data,
+ 	bool end_of_line, eof;
+ 	char *p, *start, *last, *col;
+ 	struct stm32prog_part_t *part;
++	struct image_header_s header;
+ 	int part_list_size;
+ 	int i;
+ 
+ 	data->part_nb = 0;
+ 
+ 	/* check if STM32image is detected */
+-	stm32prog_header_check((struct raw_header_s *)addr, &data->header);
+-	if (data->header.type == HEADER_STM32IMAGE) {
++	stm32prog_header_check((struct raw_header_s *)addr, &header);
++	if (header.type == HEADER_STM32IMAGE) {
+ 		u32 checksum;
+ 
+ 		addr = addr + BL_HEADER_SIZE;
+-		size = data->header.image_length;
++		size = header.image_length;
+ 
+-		checksum = stm32prog_header_checksum(addr, &data->header);
+-		if (checksum != data->header.image_checksum) {
++		checksum = stm32prog_header_checksum(addr, &header);
++		if (checksum != header.image_checksum) {
+ 			stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x",
+-				      checksum, data->header.image_checksum);
++				      checksum, header.image_checksum);
+ 			return -EIO;
+ 		}
+ 	}
+@@ -1730,7 +1731,6 @@ void stm32prog_clean(struct stm32prog_data *data)
+ 	free(data->part_array);
+ 	free(data->otp_part);
+ 	free(data->buffer);
+-	free(data->header_data);
+ }
+ 
+ /* DFU callback: used after serial and direct DFU USB access */
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+index fadcd1fa8f..eebc4d2e71 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+@@ -134,14 +134,9 @@ struct stm32prog_data {
+ 	u32			*otp_part;
+ 	u8			pmic_part[PMIC_SIZE];
+ 
+-	/* STM32 header information */
+-	struct raw_header_s	*header_data;
+-	struct image_header_s	header;
+-
+ 	/* SERIAL information */
+ 	u32	cursor;
+ 	u32	packet_number;
+-	u32	checksum;
+ 	u8	*buffer; /* size = USART_RAM_BUFFER_SIZE*/
+ 	int	dfu_seq;
+ 	u8	read_phase;
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+index 0c3c215b3d..a0bf7e1884 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+@@ -59,6 +59,9 @@ const u8 cmd_id[] = {
+ 
+ #define NB_CMD sizeof(cmd_id)
+ 
++/* with 115200 bauds, 20 ms allow to receive the 256 bytes buffer */
++#define TIMEOUT_SERIAL_BUFFER	30
++
+ /* DFU support for serial *********************************************/
+ static struct dfu_entity *stm32prog_get_entity(struct stm32prog_data *data)
+ {
+@@ -263,6 +266,7 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count)
+ {
+ 	struct dm_serial_ops *ops = serial_get_ops(down_serial_dev);
+ 	int err;
++	ulong start = get_timer(0);
+ 
+ 	do {
+ 		err = ops->getc(down_serial_dev);
+@@ -272,6 +276,10 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count)
+ 		} else if (err == -EAGAIN) {
+ 			ctrlc();
+ 			WATCHDOG_RESET();
++			if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) {
++				err = -ETIMEDOUT;
++				break;
++			}
+ 		} else {
+ 			break;
+ 		}
+@@ -291,56 +299,6 @@ static void stm32prog_serial_putc(u8 w_byte)
+ }
+ 
+ /* Helper function ************************************************/
+-
+-static u8 stm32prog_header(struct stm32prog_data *data)
+-{
+-	u8 ret;
+-	u8 boot = 0;
+-	struct dfu_entity *dfu_entity;
+-	u64 size = 0;
+-
+-	dfu_entity = stm32prog_get_entity(data);
+-	if (!dfu_entity)
+-		return -ENODEV;
+-
+-	printf("\nSTM32 download write %s\n", dfu_entity->name);
+-
+-	/* force cleanup to avoid issue with previous read */
+-	dfu_transaction_cleanup(dfu_entity);
+-
+-	stm32prog_header_check(data->header_data, &data->header);
+-
+-	/* no stm32 image header : max size is partition size */
+-	if (data->header.type != HEADER_STM32IMAGE) {
+-		dfu_entity->get_medium_size(dfu_entity, &size);
+-		data->header.image_length = size;
+-	}
+-
+-	/**** Flash the header if necessary for boot partition */
+-	if (data->phase < PHASE_FIRST_USER)
+-		boot = 1;
+-
+-	/* write header if boot partition */
+-	if (boot) {
+-		if (ret) {
+-			stm32prog_err("invalid header (error %d)", ret);
+-		} else {
+-			ret = stm32prog_write(data,
+-					      (u8 *)data->header_data,
+-					      BL_HEADER_SIZE);
+-		}
+-	} else {
+-		if (ret)
+-			printf("  partition without checksum\n");
+-		ret = 0;
+-	}
+-
+-	free(data->header_data);
+-	data->header_data = NULL;
+-
+-	return ret;
+-}
+-
+ static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
+ {
+ 	u8 ret = 0;
+@@ -387,23 +345,6 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address)
+ 		data->dfu_seq = 0;
+ 
+ 		printf("\n  received length = 0x%x\n", data->cursor);
+-		if (data->header.type == HEADER_STM32IMAGE) {
+-			if (data->cursor !=
+-			    (data->header.image_length + BL_HEADER_SIZE)) {
+-				stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)",
+-					      data->cursor,
+-					      data->header.image_length +
+-					      BL_HEADER_SIZE);
+-				return -EIO;
+-			}
+-			if (data->header.image_checksum != data->checksum) {
+-				stm32prog_err("invalid checksum received (0x%x expected 0x%x)",
+-					      data->checksum,
+-					      data->header.image_checksum);
+-				return -EIO;
+-			}
+-			printf("\n  checksum OK (0x%x)\n", data->checksum);
+-		}
+ 
+ 		/* update DFU with received flashlayout */
+ 		if (data->phase == PHASE_FLASHLAYOUT)
+@@ -626,14 +567,12 @@ static void download_command(struct stm32prog_data *data)
+ 	u32 counter = 0x0, codesize = 0x0;
+ 	u8 *ramaddress = 0;
+ 	u8 rcv_data = 0x0;
+-	struct image_header_s *image_header = &data->header;
+ 	u32 cursor = data->cursor;
+ 	long size = 0;
+ 	u8 operation;
+ 	u32 packet_number;
+ 	u32 result = ACK_BYTE;
+ 	u8 ret;
+-	unsigned int i;
+ 	bool error;
+ 	int rcv;
+ 
+@@ -667,13 +606,8 @@ static void download_command(struct stm32prog_data *data)
+ 	if (packet_number == 0) {
+ 		/* erase: re-initialize the image_header struct */
+ 		data->packet_number = 0;
+-		if (data->header_data)
+-			memset(data->header_data, 0, BL_HEADER_SIZE);
+-		else
+-			data->header_data = calloc(1, BL_HEADER_SIZE);
+ 		cursor = 0;
+ 		data->cursor = 0;
+-		data->checksum = 0;
+ 		/*idx = cursor;*/
+ 	} else {
+ 		data->packet_number++;
+@@ -721,7 +655,7 @@ static void download_command(struct stm32prog_data *data)
+ 		printf("transmission error on packet %d, byte %d\n",
+ 		       packet_number, codesize - counter);
+ 		/* waiting end of packet before flush & NACK */
+-		mdelay(30);
++		mdelay(TIMEOUT_SERIAL_BUFFER);
+ 		data->packet_number--;
+ 		result = NACK_BYTE;
+ 		goto end;
+@@ -739,80 +673,33 @@ static void download_command(struct stm32prog_data *data)
+ 		/* wait to be sure that all data are received
+ 		 * in the FIFO before flush
+ 		 */
+-		mdelay(30);
++		mdelay(TIMEOUT_SERIAL_BUFFER);
+ 		data->packet_number--;
+ 		result = NACK_BYTE;
+ 		goto end;
+ 	}
+ 
+-	/* Update current position in buffer */
+-	data->cursor += codesize;
+-
+-	if (operation == PHASE_OTP) {
+-		size = data->cursor - cursor;
+-		/* no header for OTP */
+-		if (stm32prog_otp_write(data, cursor,
+-					data->buffer, &size))
+-			result = ABORT_BYTE;
+-		goto end;
+-	}
++	switch (operation) {
++	case PHASE_OTP:
++		size = codesize;
++		ret = stm32prog_otp_write(data, cursor, data->buffer, &size);
++		break;
+ 
+-	if (operation == PHASE_PMIC) {
+-		size = data->cursor - cursor;
+-		/* no header for PMIC */
+-		if (stm32prog_pmic_write(data, cursor,
+-					 data->buffer, &size))
+-			result = ABORT_BYTE;
+-		goto end;
+-	}
++	case PHASE_PMIC:
++		size = codesize;
++		ret = stm32prog_pmic_write(data, cursor, data->buffer, &size);
++		break;
+ 
+-	if (cursor < BL_HEADER_SIZE) {
+-		/* size = portion of header in this chunck */
+-		if (data->cursor >= BL_HEADER_SIZE)
+-			size = BL_HEADER_SIZE - cursor;
+-		else
+-			size = data->cursor - cursor;
+-		memcpy((void *)((u32)(data->header_data) + cursor),
+-		       data->buffer, size);
+-		cursor += size;
+-
+-		if (cursor == BL_HEADER_SIZE) {
+-			/* Check and Write the header */
+-			if (stm32prog_header(data)) {
+-				result = ABORT_BYTE;
+-				goto end;
+-			}
+-		} else {
+-			goto end;
+-		}
++	default:
++		ret = stm32prog_write(data, data->buffer, codesize);
++		break;
+ 	}
+ 
+-	if (data->header.type == HEADER_STM32IMAGE) {
+-		if (data->cursor <= BL_HEADER_SIZE)
+-			goto end;
+-		/* compute checksum on payload */
+-		for (i = (unsigned long)size; i < codesize; i++)
+-			data->checksum += data->buffer[i];
+-
+-		if (data->cursor >
+-		    image_header->image_length + BL_HEADER_SIZE) {
+-			pr_err("expected size exceeded\n");
+-			result = ABORT_BYTE;
+-			goto end;
+-		}
+-
+-		/* write data (payload) */
+-		ret = stm32prog_write(data,
+-				      &data->buffer[size],
+-				      codesize - size);
+-	} else {
+-		/* write all */
+-		ret = stm32prog_write(data,
+-				      data->buffer,
+-				      codesize);
+-	}
+ 	if (ret)
+ 		result = ABORT_BYTE;
++	else
++		/* Update current position in buffer */
++		data->cursor += codesize;
+ 
+ end:
+ 	stm32prog_serial_result(result);
+-- 
+2.17.1
+

recipes-bsp/u-boot/u-boot-stm32mp/0007-ARM-v2020.10-stm32mp-r2-MACHINE.patch

@@ -0,0 +1,946 @@
+From 85fa6b016df48fdd465f8b5314b2e96a575c3228 Mon Sep 17 00:00:00 2001
+From: Lionel Vitte <lionel.vitte@st.com>
+Date: Mon, 18 Oct 2021 17:10:29 +0200
+Subject: [PATCH 07/11] ARM v2020.10-stm32mp-r2 MACHINE
+
+---
+ Makefile                                      |   2 +-
+ arch/arm/cpu/armv7/cache_v7.c                 |   3 -
+ arch/arm/include/asm/cache.h                  |   1 -
+ arch/arm/include/asm/system.h                 |  18 +-
+ arch/arm/lib/cache-cp15.c                     |  13 +-
+ arch/arm/mach-omap2/omap-cache.c              |  17 --
+ arch/arm/mach-stm32mp/Kconfig                 |   4 +-
+ arch/arm/mach-stm32mp/cmd_stm32key.c          | 235 +++++++++++++++---
+ .../cmd_stm32prog/cmd_stm32prog.c             |  36 ++-
+ .../mach-stm32mp/cmd_stm32prog/stm32prog.c    |  35 ++-
+ .../mach-stm32mp/cmd_stm32prog/stm32prog.h    |   3 +
+ .../cmd_stm32prog/stm32prog_serial.c          |  10 +-
+ .../cmd_stm32prog/stm32prog_usb.c             |   9 +-
+ arch/arm/mach-stm32mp/cpu.c                   |  61 ++++-
+ arch/arm/mach-stm32mp/dram_init.c             |  19 +-
+ arch/arm/mach-stm32mp/syscon.c                |  14 ++
+ 16 files changed, 351 insertions(+), 129 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 59493deed3..25a42acc37 100644
+--- a/Makefile
++++ b/Makefile
+@@ -3,7 +3,7 @@
+ VERSION = 2020
+ PATCHLEVEL = 10
+ SUBLEVEL =
+-EXTRAVERSION = -stm32mp-r1.1
++EXTRAVERSION = -stm32mp-r2
+ NAME =
+ 
+ # *DOCUMENTATION*
+diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
+index 146cf52608..19ff432352 100644
+--- a/arch/arm/cpu/armv7/cache_v7.c
++++ b/arch/arm/cpu/armv7/cache_v7.c
+@@ -176,9 +176,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
+ {
+ }
+ 
+-void arm_init_domains(void)
+-{
+-}
+ #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+ 
+ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
+index c20e05ec7f..b10edf805b 100644
+--- a/arch/arm/include/asm/cache.h
++++ b/arch/arm/include/asm/cache.h
+@@ -35,7 +35,6 @@ void l2_cache_disable(void);
+ void set_section_dcache(int section, enum dcache_option option);
+ 
+ void arm_init_before_mmu(void);
+-void arm_init_domains(void);
+ void cpu_cache_initialization(void);
+ void dram_bank_mmu_setup(int bank);
+ 
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 932f12af1c..cab23ca7b2 100644
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -397,20 +397,6 @@ static inline void set_cr(unsigned int val)
+ 	isb();
+ }
+ 
+-static inline unsigned int get_dacr(void)
+-{
+-	unsigned int val;
+-	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
+-	return val;
+-}
+-
+-static inline void set_dacr(unsigned int val)
+-{
+-	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
+-	  : : "r" (val) : "cc");
+-	isb();
+-}
+-
+ #ifdef CONFIG_ARMV7_LPAE
+ /* Long-Descriptor Translation Table Level 1/2 Bits */
+ #define TTB_SECT_XN_MASK	(1ULL << 54)
+@@ -476,7 +462,7 @@ enum dcache_option {
+ #define TTB_SECT_XN_MASK	(1 << 4)
+ #define TTB_SECT_C_MASK		(1 << 3)
+ #define TTB_SECT_B_MASK		(1 << 2)
+-#define TTB_SECT			(2 << 0)
++#define TTB_SECT		(2 << 0)
+ 
+ /*
+  * Short-descriptor format memory region attributes, without TEX remap
+@@ -491,7 +477,7 @@ enum dcache_option {
+ enum dcache_option {
+ 	INVALID_ENTRY = 0,
+ 	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
+-	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
++	DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
+ 	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+ 	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+ };
+diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
+index 94e9b9c861..369be44b17 100644
+--- a/arch/arm/lib/cache-cp15.c
++++ b/arch/arm/lib/cache-cp15.c
+@@ -22,10 +22,6 @@ __weak void arm_init_before_mmu(void)
+ {
+ }
+ 
+-__weak void arm_init_domains(void)
+-{
+-}
+-
+ static void set_section_phys(int section, phys_addr_t phys,
+ 			     enum dcache_option option)
+ {
+@@ -209,11 +205,12 @@ static inline void mmu_setup(void)
+ 	asm volatile("mcr p15, 0, %0, c2, c0, 0"
+ 		     : : "r" (gd->arch.tlb_addr) : "memory");
+ #endif
+-	/* Set the access control to all-supervisor */
++	/*
++	 * initial value of Domain Access Control Register (DACR)
++	 * Set the access control to client (1U) for each of the 16 domains
++	 */
+ 	asm volatile("mcr p15, 0, %0, c3, c0, 0"
+-		     : : "r" (~0));
+-
+-	arm_init_domains();
++		     : : "r" (0x55555555));
+ 
+ 	/* and enable the mmu */
+ 	reg = get_cr();	/* get control reg. */
+diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
+index 502ea6987a..451d8e4542 100644
+--- a/arch/arm/mach-omap2/omap-cache.c
++++ b/arch/arm/mach-omap2/omap-cache.c
+@@ -40,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define ARMV7_DCACHE_POLICY	DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
+ #endif
+ 
+-#define ARMV7_DOMAIN_CLIENT	1
+-#define ARMV7_DOMAIN_MASK	(0x3 << 0)
+-
+ void enable_caches(void)
+ {
+ 
+@@ -66,17 +63,3 @@ void dram_bank_mmu_setup(int bank)
+ 	for (i = start; i < end; i++)
+ 		set_section_dcache(i, ARMV7_DCACHE_POLICY);
+ }
+-
+-void arm_init_domains(void)
+-{
+-	u32 reg;
+-
+-	reg = get_dacr();
+-	/*
+-	* Set DOMAIN to client access so that all permissions
+-	* set in pagetables are validated by the mmu.
+-	*/
+-	reg &= ~ARMV7_DOMAIN_MASK;
+-	reg |= ARMV7_DOMAIN_CLIENT;
+-	set_dacr(reg);
+-}
+diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
+index af0246d031..44bfac9000 100644
+--- a/arch/arm/mach-stm32mp/Kconfig
++++ b/arch/arm/mach-stm32mp/Kconfig
+@@ -130,10 +130,12 @@ config STM32_ETZPC
+ 
+ config CMD_STM32KEY
+ 	bool "command stm32key to fuse public key hash"
+-	default y
++	default n
+ 	help
+ 		fuse public key hash in corresponding fuse used to authenticate
+ 		binary.
++		This command is used to evaluate the secure boot on stm32mp SOC,
++		it is deactivated by default in real products.
+ 
+ config PRE_CON_BUF_ADDR
+ 	default 0xC02FF000
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
+index f191085a12..d1755f4595 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
+@@ -10,13 +10,30 @@
+ #include <dm/device.h>
+ #include <dm/uclass.h>
+ 
+-#define STM32_OTP_HASH_KEY_START 24
+-#define STM32_OTP_HASH_KEY_SIZE 8
++/* Closed device : bit 6 of OPT0*/
++#define STM32_OTP_CLOSE_ID		0
++#define STM32_OTP_CLOSE_MASK		BIT(6)
++
++/* HASH of key: 8 OTPs, starting with OTP24) */
++#define STM32_OTP_HASH_KEY_START	24
++#define STM32_OTP_HASH_KEY_SIZE		8
++
++static int get_misc_dev(struct udevice **dev)
++{
++	int ret;
++
++	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(stm32mp_bsec), dev);
++	if (ret)
++		pr_err("Can't find stm32mp_bsec driver\n");
++
++	return ret;
++}
+ 
+ static void read_hash_value(u32 addr)
+ {
+ 	int i;
+ 
++	printf("Read KEY at 0x%x\n", addr);
+ 	for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
+ 		printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i,
+ 		       __be32_to_cpu(*(u32 *)addr));
+@@ -24,32 +41,101 @@ static void read_hash_value(u32 addr)
+ 	}
+ }
+ 
+-static void fuse_hash_value(u32 addr, bool print)
++static int read_hash_otp(bool print, bool *locked, bool *closed)
+ {
+ 	struct udevice *dev;
+-	u32 word, val;
+-	int i, ret;
++	int i, word, ret;
++	int nb_invalid = 0, nb_zero = 0, nb_lock = 0;
++	u32 val, lock;
++	bool status;
+ 
+-	ret = uclass_get_device_by_driver(UCLASS_MISC,
+-					  DM_GET_DRIVER(stm32mp_bsec),
+-					  &dev);
+-	if (ret) {
+-		pr_err("Can't find stm32mp_bsec driver\n");
+-		return;
++	ret = get_misc_dev(&dev);
++	if (ret)
++		return ret;
++
++	for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) {
++		ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
++		if (ret != 4)
++			val = ~0x0;
++		ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
++		if (ret != 4)
++			lock = -1;
++		if (print)
++			printf("OTP HASH %i: %x lock : %d\n", word, val, lock);
++		if (val == ~0x0)
++			nb_invalid++;
++		else if (val == 0x0)
++			nb_zero++;
++		if (lock == 1)
++			nb_lock++;
+ 	}
+ 
+-	for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
++	word = STM32_OTP_CLOSE_ID;
++	ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
++	if (ret != 4)
++		val = 0x0;
++	ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
++	if (ret != 4)
++		lock = -1;
++
++	status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK;
++	if (closed)
++		*closed = status;
++	if (print)
++		printf("OTP %d: closed status: %d lock : %d\n", word, status, lock);
++
++	status = (nb_lock == STM32_OTP_HASH_KEY_SIZE);
++	if (locked)
++		*locked = status;
++	if (!status && print)
++		printf("HASK key is not locked!\n");
++
++	if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) {
++		if (print)
++			printf("HASK key is invalid!\n");
++		return -EINVAL;
++	}
++	if (nb_zero == STM32_OTP_HASH_KEY_SIZE) {
+ 		if (print)
+-			printf("Fuse OTP %i : %x\n",
+-			       STM32_OTP_HASH_KEY_START + i,
+-			       __be32_to_cpu(*(u32 *)addr));
++			printf("HASK key is free!\n");
++		return -ENOENT;
++	}
++
++	return 0;
++}
+ 
+-		word = STM32_OTP_HASH_KEY_START + i;
++static int fuse_hash_value(u32 addr, bool print)
++{
++	struct udevice *dev;
++	u32 word, val;
++	int i, ret;
++
++	ret = get_misc_dev(&dev);
++	if (ret)
++		return ret;
++
++	for (i = 0, word = STM32_OTP_HASH_KEY_START;
++	     i < STM32_OTP_HASH_KEY_SIZE;
++	     i++, word++, addr += 4) {
+ 		val = __be32_to_cpu(*(u32 *)addr);
+-		misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
++		if (print)
++			printf("Fuse OTP %i : %x\n", word, val);
+ 
+-		addr += 4;
++		ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
++		if (ret != 4) {
++			printf("Fuse OTP %i failed\n", word);
++			return ret;
++		}
++		/* on success, lock the OTP for HASH key */
++		val = 1;
++		ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
++		if (ret != 4) {
++			printf("Lock OTP %i failed\n", word);
++			return ret;
++		}
+ 	}
++
++	return 0;
+ }
+ 
+ static int confirm_prog(void)
+@@ -66,36 +152,113 @@ static int confirm_prog(void)
+ 	return 0;
+ }
+ 
+-static int do_stm32key(struct cmd_tbl *cmdtp, int flag, int argc,
+-		       char *const argv[])
++static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+ {
+ 	u32 addr;
+-	const char *op = argc >= 2 ? argv[1] : NULL;
+-	int confirmed = argc > 3 && !strcmp(argv[2], "-y");
+ 
+-	argc -= 2 + confirmed;
+-	argv += 2 + confirmed;
++	if (argc == 1) {
++		read_hash_otp(true, NULL, NULL);
++		return CMD_RET_SUCCESS;
++	}
+ 
+-	if (argc < 1)
++	addr = simple_strtoul(argv[1], NULL, 16);
++	if (!addr)
+ 		return CMD_RET_USAGE;
+ 
+-	addr = simple_strtoul(argv[0], NULL, 16);
++	read_hash_value(addr);
++
++	return CMD_RET_SUCCESS;
++}
++
++static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++	u32 addr;
++	bool yes = false, lock, closed;
++
++	if (argc < 2)
++		return CMD_RET_USAGE;
++
++	if (argc == 3) {
++		if (strcmp(argv[1], "-y"))
++			return CMD_RET_USAGE;
++		yes = true;
++	}
++
++	addr = simple_strtoul(argv[argc - 1], NULL, 16);
+ 	if (!addr)
+ 		return CMD_RET_USAGE;
+ 
+-	if (!strcmp(op, "read"))
+-		read_hash_value(addr);
++	if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) {
++		printf("Error: can't fuse again the OTP\n");
++		return CMD_RET_FAILURE;
++	}
+ 
+-	if (!strcmp(op, "fuse")) {
+-		if (!confirmed && !confirm_prog())
+-			return CMD_RET_FAILURE;
+-		fuse_hash_value(addr, !confirmed);
++	if (lock || closed) {
++		printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed);
++		return CMD_RET_FAILURE;
+ 	}
+ 
++	if (!yes && !confirm_prog())
++		return CMD_RET_FAILURE;
++
++	if (fuse_hash_value(addr, !yes))
++		return CMD_RET_FAILURE;
++
++	printf("Hash key updated !\n");
++
+ 	return CMD_RET_SUCCESS;
+ }
+ 
+-U_BOOT_CMD(stm32key, 4, 1, do_stm32key,
+-	   "Fuse ST Hash key",
+-	   "read <addr>: Read the hash store at addr in memory\n"
+-	   "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n");
++static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
++{
++	bool yes, lock, closed;
++	struct udevice *dev;
++	u32 val;
++	int ret;
++
++	yes = false;
++	if (argc == 2) {
++		if (strcmp(argv[1], "-y"))
++			return CMD_RET_USAGE;
++		yes = true;
++	}
++
++	if (read_hash_otp(!yes, &lock, &closed))
++		return CMD_RET_FAILURE;
++
++	if (closed) {
++		printf("Error: already closed!\n");
++		return CMD_RET_FAILURE;
++	}
++
++	if (!lock)
++		printf("Warning: OTP not locked, revocation is possible!\n");
++
++	if (!yes && !confirm_prog())
++		return CMD_RET_FAILURE;
++
++	ret = get_misc_dev(&dev);
++	if (ret)
++		return CMD_RET_FAILURE;
++
++	val = STM32_OTP_CLOSE_MASK;
++	ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
++	if (ret != 4) {
++		printf("Error: can't update OTP\n");
++		return CMD_RET_FAILURE;
++	}
++
++	printf("Device is closed !\n");
++
++	return CMD_RET_SUCCESS;
++}
++
++static char stm32key_help_text[] =
++	"read [<addr>]: Read the hash stored at addr in memory or in OTP\n"
++	"stm32key fuse [-y] <addr> : Fuse hash stored at addr in OTP\n"
++	"stm32key close [-y] : Close the device, the hash stored in OTP\n";
++
++U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text,
++	U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
++	U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
++	U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+index a20980a6ae..b2a17314ee 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+@@ -45,7 +45,6 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
+ 	bool reset = false;
+ 	struct image_header_s header;
+ 	struct stm32prog_data *data;
+-	u32 uimage, dtb;
+ 
+ 	if (argc < 3 ||  argc > 5)
+ 		return CMD_RET_USAGE;
+@@ -78,10 +77,12 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
+ 		if (header.type == HEADER_STM32IMAGE) {
+ 			size = header.image_length + BL_HEADER_SIZE;
+ 
++#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
+ 			/* uImage detected in STM32IMAGE, execute the script */
+ 			if (IMAGE_FORMAT_LEGACY ==
+ 			    genimg_get_format((void *)(addr + BL_HEADER_SIZE)))
+ 				return image_source_script(addr + BL_HEADER_SIZE, "script@1");
++#endif
+ 		}
+ 	}
+ 
+@@ -98,7 +99,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
+ 
+ 	ret = stm32prog_init(data, addr, size);
+ 	if (ret)
+-		printf("Invalid or missing layout file.");
++		log_debug("Invalid or missing layout file at 0x%lx.\n", addr);
+ 
+ 	/* prepare DFU for device read/write */
+ 	ret = stm32prog_dfu_init(data);
+@@ -119,21 +120,23 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
+ 		goto cleanup;
+ 	}
+ 
+-	uimage = data->uimage;
+-	dtb = data->dtb;
+-
+ 	stm32prog_clean(data);
+ 	free(stm32prog_data);
+ 	stm32prog_data = NULL;
+ 
+ 	puts("Download done\n");
+ 
+-	if (uimage) {
++	if (data->uimage) {
+ 		char boot_addr_start[20];
+ 		char dtb_addr[20];
++		char initrd_addr[40];
+ 		char *bootm_argv[5] = {
+ 			"bootm", boot_addr_start, "-", dtb_addr, NULL
+ 		};
++		u32 uimage = data->uimage;
++		u32 dtb = data->dtb;
++		u32 initrd = data->initrd;
++
+ 		if (!dtb)
+ 			bootm_argv[3] = env_get("fdtcontroladdr");
+ 		else
+@@ -142,8 +145,15 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
+ 
+ 		snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
+ 			 "0x%x", uimage);
+-		printf("Booting kernel at %s - %s...\n\n\n",
+-		       boot_addr_start, bootm_argv[3]);
++
++		if (initrd) {
++			snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%x:0x%x",
++				 initrd, data->initrd_size);
++			bootm_argv[2] = initrd_addr;
++		}
++
++		printf("Booting kernel at %s %s %s...\n\n\n",
++		       boot_addr_start, bootm_argv[2], bootm_argv[3]);
+ 		/* Try bootm for legacy and FIT format image */
+ 		if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID)
+ 			do_bootm(cmdtp, 0, 4, bootm_argv);
+@@ -167,12 +177,12 @@ cleanup:
+ }
+ 
+ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
++	   "start communication with tools STM32Cubeprogrammer",
+ 	   "<link> <dev> [<addr>] [<size>]\n"
+-	   "start communication with tools STM32Cubeprogrammer on <link> with Flashlayout at <addr>",
+-	   "<link> = serial|usb\n"
+-	   "<dev>  = device instance\n"
+-	   "<addr> = address of flashlayout\n"
+-	   "<size> = size of flashlayout\n"
++	   "  <link> = serial|usb\n"
++	   "  <dev>  = device instance\n"
++	   "  <addr> = address of flashlayout\n"
++	   "  <size> = size of flashlayout (optional for image with STM32 header)\n"
+ );
+ 
+ #ifdef CONFIG_STM32MP15x_STM32IMAGE
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+index 7cd31462ba..62b386582d 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+@@ -1153,7 +1153,10 @@ static int dfu_init_entities(struct stm32prog_data *data)
+ 	struct dfu_entity *dfu;
+ 	int alt_nb;
+ 
+-	alt_nb = 3; /* number of virtual = CMD, OTP, PMIC*/
++	alt_nb = 2; /* number of virtual = CMD, OTP*/
++	if (CONFIG_IS_ENABLED(DM_PMIC))
++		alt_nb++; /* PMIC NVMEM*/
++
+ 	if (data->part_nb == 0)
+ 		alt_nb++;  /* +1 for FlashLayout */
+ 	else
+@@ -1199,13 +1202,13 @@ static int dfu_init_entities(struct stm32prog_data *data)
+ 	}
+ 
+ 	if (!ret)
+-		ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, 512);
++		ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
+ 
+ 	if (!ret)
+-		ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, 512);
++		ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE);
+ 
+ 	if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
+-		ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, 8);
++		ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
+ 
+ 	if (ret)
+ 		stm32prog_err("dfu init failed: %d", ret);
+@@ -1476,7 +1479,7 @@ error:
+ 	return ret;
+ }
+ 
+-static void stm32prog_end_phase(struct stm32prog_data *data)
++static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset)
+ {
+ 	if (data->phase == PHASE_FLASHLAYOUT) {
+ 		if (parse_flash_layout(data, STM32_DDR_BASE, 0))
+@@ -1492,6 +1495,10 @@ static void stm32prog_end_phase(struct stm32prog_data *data)
+ 			data->uimage = data->cur_part->addr;
+ 		if (data->cur_part->part_type == PART_FILESYSTEM)
+ 			data->dtb = data->cur_part->addr;
++		if (data->cur_part->part_type == PART_BINARY) {
++			data->initrd = data->cur_part->addr;
++			data->initrd_size = offset;
++		}
+ 	}
+ 
+ 	if (CONFIG_IS_ENABLED(MMC) &&
+@@ -1750,7 +1757,7 @@ void dfu_flush_callback(struct dfu_entity *dfu)
+ 	if (dfu->dev_type == DFU_DEV_RAM) {
+ 		if (dfu->alt == 0 &&
+ 		    stm32prog_data->phase == PHASE_FLASHLAYOUT) {
+-			stm32prog_end_phase(stm32prog_data);
++			stm32prog_end_phase(stm32prog_data, dfu->offset);
+ 			/* waiting DFU DETACH for reenumeration */
+ 		}
+ 	}
+@@ -1759,7 +1766,7 @@ void dfu_flush_callback(struct dfu_entity *dfu)
+ 		return;
+ 
+ 	if (dfu->alt == stm32prog_data->cur_part->alt_id) {
+-		stm32prog_end_phase(stm32prog_data);
++		stm32prog_end_phase(stm32prog_data, dfu->offset);
+ 		stm32prog_next_phase(stm32prog_data);
+ 	}
+ }
+@@ -1779,3 +1786,17 @@ void dfu_initiated_callback(struct dfu_entity *dfu)
+ 		pr_debug("dfu offset = 0x%llx\n", dfu->offset);
+ 	}
+ }
++
++void dfu_error_callback(struct dfu_entity *dfu, const char *msg)
++{
++	struct stm32prog_data *data = stm32prog_data;
++
++	if (!stm32prog_data)
++		return;
++
++	if (!stm32prog_data->cur_part)
++		return;
++
++	if (dfu->alt == stm32prog_data->cur_part->alt_id)
++		stm32prog_err(msg);
++}
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+index eebc4d2e71..f4243ae2ec 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+@@ -19,6 +19,7 @@
+ 
+ #define DEFAULT_ADDRESS		0xFFFFFFFF
+ 
++#define CMD_SIZE		512
+ #define OTP_SIZE		1024
+ #define PMIC_SIZE		8
+ 
+@@ -144,6 +145,8 @@ struct stm32prog_data {
+ 	/* bootm information */
+ 	u32	uimage;
+ 	u32	dtb;
++	u32	initrd;
++	u32	initrd_size;
+ };
+ 
+ extern struct stm32prog_data *stm32prog_data;
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+index a0bf7e1884..3d32adcf62 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+@@ -10,6 +10,7 @@
+ #include <malloc.h>
+ #include <serial.h>
+ #include <watchdog.h>
++#include <asm/arch/sys_proto.h>
+ #include <dm/lists.h>
+ #include <dm/device-internal.h>
+ #include <linux/delay.h>
+@@ -18,8 +19,7 @@
+ /* - configuration part -----------------------------*/
+ #define USART_BL_VERSION	0x40	/* USART bootloader version V4.0*/
+ #define UBOOT_BL_VERSION	0x03	/* bootloader version V0.3*/
+-#define DEVICE_ID_BYTE1		0x05	/* MSB byte of device ID*/
+-#define DEVICE_ID_BYTE2		0x00	/* LSB byte of device ID*/
++
+ #define USART_RAM_BUFFER_SIZE	256	/* Size of USART_RAM_Buf buffer*/
+ 
+ /* - Commands -----------------------------*/
+@@ -435,10 +435,12 @@ static void get_version_command(struct stm32prog_data *data)
+  */
+ static void get_id_command(struct stm32prog_data *data)
+ {
++	u32 cpu = get_cpu_dev();
++
+ 	/* Send Device IDCode */
+ 	stm32prog_serial_putc(0x1);
+-	stm32prog_serial_putc(DEVICE_ID_BYTE1);
+-	stm32prog_serial_putc(DEVICE_ID_BYTE2);
++	stm32prog_serial_putc((cpu >> 8) & 0xFF);
++	stm32prog_serial_putc(cpu & 0xFF);
+ 	stm32prog_serial_result(ACK_BYTE);
+ }
+ 
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+index 30547f94c9..6ddf08523e 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+@@ -178,7 +178,7 @@ int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
+ 
+ 	switch (dfu->data.virt.dev_num) {
+ 	case PHASE_CMD:
+-		*size = 512;
++		*size = CMD_SIZE;
+ 		break;
+ 	case PHASE_OTP:
+ 		*size = OTP_SIZE;
+@@ -207,13 +207,10 @@ bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
+ 
+ 	if (stm32prog_data->phase == PHASE_FLASHLAYOUT) {
+ 		ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu");
+-		if (ret || stm32prog_data->phase == PHASE_DO_RESET)
++		if (ret || stm32prog_data->phase != PHASE_FLASHLAYOUT)
+ 			return ret;
+ 		/* prepare the second enumeration with the FlashLayout */
+-		if (stm32prog_data->phase == PHASE_FLASHLAYOUT)
+-			stm32prog_dfu_init(data);
+-		/* found next selected partition */
+-		stm32prog_next_phase(data);
++		stm32prog_dfu_init(data);
+ 	}
+ 
+ 	ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu");
+diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
+index b81825a0bf..2495d4aaad 100644
+--- a/arch/arm/mach-stm32mp/cpu.c
++++ b/arch/arm/mach-stm32mp/cpu.c
+@@ -9,6 +9,7 @@
+ #include <env.h>
+ #include <init.h>
+ #include <log.h>
++#include <lmb.h>
+ #include <misc.h>
+ #include <net.h>
+ #include <asm/io.h>
+@@ -86,6 +87,8 @@
+  */
+ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+ 
++struct lmb lmb;
++
+ #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ #ifndef CONFIG_TFABOOT
+ static void security_init(void)
+@@ -207,6 +210,44 @@ u32 get_bootmode(void)
+ 		    TAMP_BOOT_MODE_SHIFT;
+ }
+ 
++/*
++ * weak function overidde: set the DDR/SYSRAM executable before to enable the
++ * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
++ */
++void dram_bank_mmu_setup(int bank)
++{
++	struct bd_info *bd = gd->bd;
++	int	i;
++	phys_addr_t start;
++	phys_size_t size;
++	bool use_lmb = false;
++	enum dcache_option option;
++
++	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
++#ifdef CONFIG_SPL
++		start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
++		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
++#endif
++	} else if (gd->flags & GD_FLG_RELOC) {
++		/* bd->bi_dram is available only after relocation */
++		start = bd->bi_dram[bank].start;
++		size =  bd->bi_dram[bank].size;
++		use_lmb = true;
++	} else {
++		/* mark cacheable and executable the beggining of the DDR */
++		start = STM32_DDR_BASE;
++		size = CONFIG_DDR_CACHEABLE_SIZE;
++	}
++
++	for (i = start >> MMU_SECTION_SHIFT;
++	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
++	     i++) {
++		option = DCACHE_DEFAULT_OPTION;
++		if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
++			option = INVALID_ENTRY;
++		set_section_dcache(i, option);
++	}
++}
+ /*
+  * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
+  * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+@@ -224,17 +265,8 @@ static void early_enable_caches(void)
+ 	gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ #endif
+ 
++	/* enable MMU (default configuration) */
+ 	dcache_enable();
+-
+-	if (IS_ENABLED(CONFIG_SPL_BUILD))
+-		mmu_set_region_dcache_behaviour(
+-			ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
+-			ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
+-			DCACHE_DEFAULT_OPTION);
+-	else
+-		mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+-						CONFIG_DDR_CACHEABLE_SIZE,
+-						DCACHE_DEFAULT_OPTION);
+ }
+ 
+ /*
+@@ -278,6 +310,9 @@ int arch_cpu_init(void)
+ 
+ void enable_caches(void)
+ {
++	/* parse device tree when data cache is still activated */
++	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
++
+ 	/* I-cache is already enabled in start.S: icache_enable() not needed */
+ 
+ 	/* deactivate the data cache, early enabled in arch_cpu_init() */
+@@ -479,7 +514,7 @@ static void setup_boot_mode(void)
+ 				gd->flags &= ~(GD_FLG_SILENT |
+ 					       GD_FLG_DISABLE_CONSOLE);
+ 			printf("uart%d = %s not found in device tree!\n",
+-			       instance, cmd);
++			       instance + 1, cmd);
+ 			break;
+ 		}
+ 		sprintf(cmd, "%d", dev->seq);
+@@ -517,7 +552,9 @@ static void setup_boot_mode(void)
+ 		env_set("boot_instance", "0");
+ 		break;
+ 	default:
+-		pr_debug("unexpected boot mode = %x\n", boot_mode);
++		env_set("boot_device", "invalid");
++		env_set("boot_instance", "");
++		log_err("unexpected boot mode = %x\n", boot_mode);
+ 		break;
+ 	}
+ 
+diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
+index 0e8ce63f4a..2c409ee217 100644
+--- a/arch/arm/mach-stm32mp/dram_init.c
++++ b/arch/arm/mach-stm32mp/dram_init.c
+@@ -10,6 +10,7 @@
+ #include <lmb.h>
+ #include <log.h>
+ #include <ram.h>
++#include <asm/system.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -38,17 +39,27 @@ int dram_init(void)
+ 
+ ulong board_get_usable_ram_top(ulong total_size)
+ {
++	phys_size_t size;
+ 	phys_addr_t reg;
+ 	struct lmb lmb;
+ 
++	if (!total_size)
++		return gd->ram_top;
++
+ 	/* found enough not-reserved memory to relocated U-Boot */
+ 	lmb_init(&lmb);
+ 	lmb_add(&lmb, gd->ram_base, gd->ram_size);
+ 	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
+-	reg = lmb_alloc(&lmb, CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K);
++	/* add 8M for reserved memory for display, fdt, gd,... */
++	size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
++	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
++
++	if (!reg)
++		reg = gd->ram_top - size;
+ 
+-	if (reg)
+-		return ALIGN(reg + CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K);
++	/* before relocation, mark the U-Boot memory as cacheable by default */
++	if (!(gd->flags & GD_FLG_RELOC))
++		mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
+ 
+-	return gd->ram_top;
++	return reg + size;
+ }
+diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
+index 3e61ce4097..a0e8e1dfdc 100644
+--- a/arch/arm/mach-stm32mp/syscon.c
++++ b/arch/arm/mach-stm32mp/syscon.c
+@@ -4,6 +4,7 @@
+  */
+ 
+ #include <common.h>
++#include <clk.h>
+ #include <dm.h>
+ #include <syscon.h>
+ #include <asm/arch/stm32.h>
+@@ -14,9 +15,22 @@ static const struct udevice_id stm32mp_syscon_ids[] = {
+ 	{ }
+ };
+ 
++static int stm32mp_syscon_probe(struct udevice *dev)
++{
++	struct clk_bulk clk_bulk;
++	int ret;
++
++	ret = clk_get_bulk(dev, &clk_bulk);
++	if (!ret)
++		clk_enable_bulk(&clk_bulk);
++
++	return 0;
++}
++
+ U_BOOT_DRIVER(syscon_stm32mp) = {
+ 	.name = "stmp32mp_syscon",
+ 	.id = UCLASS_SYSCON,
+ 	.of_match = stm32mp_syscon_ids,
+ 	.bind = dm_scan_fdt_dev,
++	.probe = stm32mp_syscon_probe,
+ };
+-- 
+2.25.1
+

recipes-bsp/u-boot/u-boot-stm32mp/0008-ARM-v2020.10-stm32mp-r2-BOARD.patch

@@ -0,0 +1,117 @@
+From ad6a40bb66269882f124e9c2b6b106cca3fb8abc Mon Sep 17 00:00:00 2001
+From: Lionel Vitte <lionel.vitte@st.com>
+Date: Mon, 18 Oct 2021 17:10:51 +0200
+Subject: [PATCH 08/11] ARM v2020.10-stm32mp-r2 BOARD
+
+---
+ board/dhelectronics/dh_stm32mp1/board.c |  7 ++-----
+ board/raspberrypi/rpi/rpi.c             |  2 +-
+ board/st/stm32mp1/stm32mp1.c            | 13 ++++++++-----
+ 3 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
+index c9abe3cc6d..77f2730a3f 100644
+--- a/board/dhelectronics/dh_stm32mp1/board.c
++++ b/board/dhelectronics/dh_stm32mp1/board.c
+@@ -551,9 +551,6 @@ int board_init(void)
+ 	/* address of boot parameters */
+ 	gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+ 
+-	if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+-		gpio_hog_probe_all();
+-
+ 	board_key_check();
+ 
+ #ifdef CONFIG_DM_REGULATOR
+@@ -618,11 +615,11 @@ int board_interface_eth_init(struct udevice *dev,
+ 	bool eth_ref_clk_sel_reg = false;
+ 
+ 	/* Gigabit Ethernet 125MHz clock selection. */
+-	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
++	eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
+ 
+ 	/* Ethernet 50Mhz RMII clock selection */
+ 	eth_ref_clk_sel_reg =
+-		dev_read_bool(dev, "st,eth_ref_clk_sel");
++		dev_read_bool(dev, "st,eth-ref-clk-sel");
+ 
+ 	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+ 
+diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
+index 6b1fa5fc14..f25b2aa219 100644
+--- a/board/raspberrypi/rpi/rpi.c
++++ b/board/raspberrypi/rpi/rpi.c
+@@ -485,7 +485,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
+ 	 * should be more intelligent, and e.g. only do this if no enabled DT
+ 	 * node exists for the "real" graphics driver.
+ 	 */
+-	lcd_dt_simplefb_add_node(blob);
++	fdt_simplefb_add_node(blob);
+ 
+ #ifdef CONFIG_EFI_LOADER
+ 	/* Reserve the spin table */
+diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
+index 9a02e14ba5..42979d80f5 100644
+--- a/board/st/stm32mp1/stm32mp1.c
++++ b/board/st/stm32mp1/stm32mp1.c
+@@ -10,6 +10,7 @@
+ #include <dm.h>
+ #include <env.h>
+ #include <env_internal.h>
++#include <fdt_simplefb.h>
+ #include <fdt_support.h>
+ #include <g_dnl.h>
+ #include <generic-phy.h>
+@@ -155,6 +156,7 @@ static void board_key_check(void)
+ 			debug("%s: could not find a /config/st,fastboot-gpios\n",
+ 			      __func__);
+ 		} else {
++			udelay(20);
+ 			if (dm_gpio_get_value(&gpio)) {
+ 				puts("Fastboot key pressed, ");
+ 				boot_mode = BOOT_FASTBOOT;
+@@ -169,6 +171,7 @@ static void board_key_check(void)
+ 			debug("%s: could not find a /config/st,stm32prog-gpios\n",
+ 			      __func__);
+ 		} else {
++			udelay(20);
+ 			if (dm_gpio_get_value(&gpio)) {
+ 				puts("STM32Programmer key pressed, ");
+ 				boot_mode = BOOT_STM32PROG;
+@@ -649,9 +652,6 @@ int board_init(void)
+ 	/* address of boot parameters */
+ 	gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+ 
+-	if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
+-		gpio_hog_probe_all();
+-
+ 	board_key_check();
+ 
+ 	if (board_is_ev1())
+@@ -739,11 +739,11 @@ int board_interface_eth_init(struct udevice *dev,
+ 	bool eth_ref_clk_sel_reg = false;
+ 
+ 	/* Gigabit Ethernet 125MHz clock selection. */
+-	eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
++	eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
+ 
+ 	/* Ethernet 50Mhz RMII clock selection */
+ 	eth_ref_clk_sel_reg =
+-		dev_read_bool(dev, "st,eth_ref_clk_sel");
++		dev_read_bool(dev, "st,eth-ref-clk-sel");
+ 
+ 	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+ 
+@@ -886,6 +886,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
+ 		if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
+ 			fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ 
++	if (CONFIG_IS_ENABLED(FDT_SIMPLEFB))
++		fdt_simplefb_add_node_and_mem_rsv(blob);
++
+ 	return 0;
+ }
+ #endif
+-- 
+2.25.1
+

recipes-bsp/u-boot/u-boot-stm32mp/0010-ARM-v2020.10-stm32mp-r2-DEVICETREE.patch

@@ -0,0 +1,573 @@
+From bb83031bcca4f234206cc428cb9c79d9ec652ba6 Mon Sep 17 00:00:00 2001
+From: Lionel Vitte <lionel.vitte@st.com>
+Date: Mon, 18 Oct 2021 17:14:59 +0200
+Subject: [PATCH 10/11] ARM v2020.10-stm32mp-r2 DEVICETREE
+
+---
+ arch/arm/dts/stm32f746.dtsi              |  4 +++
+ arch/arm/dts/stm32h743.dtsi              |  4 +++
+ arch/arm/dts/stm32mp15-m4-srm.dtsi       |  8 +++++-
+ arch/arm/dts/stm32mp15-no-scmi.dtsi      |  8 ++----
+ arch/arm/dts/stm32mp15-pinctrl.dtsi      |  4 +--
+ arch/arm/dts/stm32mp151.dtsi             | 35 ++++++++++++++++--------
+ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi |  4 +--
+ arch/arm/dts/stm32mp157a-dk1.dts         |  6 ----
+ arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi |  4 +--
+ arch/arm/dts/stm32mp157a-ev1.dts         |  5 ----
+ arch/arm/dts/stm32mp157c-dk2.dts         |  3 --
+ arch/arm/dts/stm32mp157c-ev1.dts         |  5 ----
+ arch/arm/dts/stm32mp157d-dk1.dts         |  6 ----
+ arch/arm/dts/stm32mp157d-ev1.dts         |  5 ----
+ arch/arm/dts/stm32mp157f-dk2.dts         |  3 --
+ arch/arm/dts/stm32mp157f-ev1.dts         |  5 ----
+ arch/arm/dts/stm32mp15xx-dkx.dtsi        | 23 ++++++++++++++--
+ arch/arm/dts/stm32mp15xx-edx.dtsi        |  8 +++++-
+ arch/arm/dts/stm32mp15xx-evx.dtsi        | 12 +++++++-
+ 19 files changed, 85 insertions(+), 67 deletions(-)
+
+diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
+index 3f312ab3a7..c32d2a81f1 100644
+--- a/arch/arm/dts/stm32f746.dtsi
++++ b/arch/arm/dts/stm32f746.dtsi
+@@ -315,6 +315,7 @@
+ 			clocks = <&rcc 1 CLK_I2C1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -327,6 +328,7 @@
+ 			clocks = <&rcc 1 CLK_I2C2>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -339,6 +341,7 @@
+ 			clocks = <&rcc 1 CLK_I2C3>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -351,6 +354,7 @@
+ 			clocks = <&rcc 1 CLK_I2C4>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
+index 4b4e7a99f7..5964f7b238 100644
+--- a/arch/arm/dts/stm32h743.dtsi
++++ b/arch/arm/dts/stm32h743.dtsi
+@@ -106,6 +106,7 @@
+ 				     <32>;
+ 			resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
+ 			clocks = <&rcc I2C1_CK>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -118,6 +119,7 @@
+ 				     <34>;
+ 			resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
+ 			clocks = <&rcc I2C2_CK>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -130,6 +132,7 @@
+ 				     <73>;
+ 			resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
+ 			clocks = <&rcc I2C3_CK>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+@@ -349,6 +352,7 @@
+ 				     <96>;
+ 			resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
+ 			clocks = <&rcc I2C4_CK>;
++			i2c-analog-filter;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/arch/arm/dts/stm32mp15-m4-srm.dtsi b/arch/arm/dts/stm32mp15-m4-srm.dtsi
+index 60454aee41..3162c35950 100644
+--- a/arch/arm/dts/stm32mp15-m4-srm.dtsi
++++ b/arch/arm/dts/stm32mp15-m4-srm.dtsi
+@@ -177,7 +177,7 @@
+ 			reg = <0x40016000 0x400>;
+ 			interrupt-parent = <&exti>;
+ 			interrupts = <69 1>;
+-			clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
++			clocks = <&rcc CEC_K>, <&rcc CEC>;
+ 			clock-names = "cec", "hdmi-cec";
+ 			status = "disabled";
+ 		};
+@@ -415,6 +415,12 @@
+ 			clocks = <&rcc SAI4_K>;
+ 			clock-names = "sai_ck";
+ 			status = "disabled";
++			};
++		m4_fmc: memory-controller@58002000 {
++			compatible = "rproc-srm-dev";
++			reg = <0x5800200 0x1000>;
++			clocks = <&rcc FMC_K>;
++			status = "disabled";
+ 		};
+ 		m4_qspi: qspi@58003000 {
+ 			compatible = "rproc-srm-dev";
+diff --git a/arch/arm/dts/stm32mp15-no-scmi.dtsi b/arch/arm/dts/stm32mp15-no-scmi.dtsi
+index 94a10b86a1..c7d2d7c8f5 100644
+--- a/arch/arm/dts/stm32mp15-no-scmi.dtsi
++++ b/arch/arm/dts/stm32mp15-no-scmi.dtsi
+@@ -79,10 +79,6 @@
+ 			resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>;
+ 
+ 			m4_system_resources {
+-				m4_cec: cec@40016000 {
+-					clocks = <&rcc CEC_K>, <&rcc CK_LSE>;
+-				};
+-
+ 				m4_m_can1: can@4400e000 {
+ 					clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ 				};
+@@ -101,8 +97,8 @@
+ 	/delete-node/ sram@2ffff000;
+ };
+ 
+-&cec {
+-	clocks = <&rcc CEC_K>, <&clk_lse>;
++&bsec {
++	clocks = <&rcc BSEC>;
+ };
+ 
+ &gpioz {
+diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+index a0b76e238c..236d77e09c 100644
+--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
++++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+@@ -1937,7 +1937,7 @@
+ 				 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ 			bias-disable;
+ 			drive-push-pull;
+-			slew-rate = <3>;
++			slew-rate = <0>;
+ 		};
+ 		pins2 {
+ 			pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+@@ -1955,7 +1955,7 @@
+ 			pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ 			bias-disable;
+ 			drive-push-pull;
+-			slew-rate = <3>;
++			slew-rate = <0>;
+ 		};
+ 		pins3 {
+ 			pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
+index ca71139f3a..ab5723c472 100644
+--- a/arch/arm/dts/stm32mp151.dtsi
++++ b/arch/arm/dts/stm32mp151.dtsi
+@@ -647,7 +647,7 @@
+ 			compatible = "st,stm32-cec";
+ 			reg = <0x40016000 0x400>;
+ 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
++			clocks = <&rcc CEC_K>, <&rcc CEC>;
+ 			clock-names = "cec", "hdmi-cec";
+ 			status = "disabled";
+ 		};
+@@ -1181,6 +1181,8 @@
+ 				interrupts = <1>;
+ 				dmas = <&dmamux1 10 0x400 0x80000001>;
+ 				dma-names = "rx";
++				nvmem-cells = <&vrefint>;
++				nvmem-cell-names = "vrefint";
+ 				status = "disabled";
+ 			};
+ 		};
+@@ -1212,6 +1214,7 @@
+ 			g-np-tx-fifo-size = <32>;
+ 			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+ 			dr_mode = "otg";
++			otg-rev = <0x200>;
+ 			usb33d-supply = <&usb33>;
+ 			power-domains = <&pd_core>;
+ 			wakeup-source;
+@@ -1266,6 +1269,7 @@
+ 				 <&scmi0_clk CK_SCMI0_CSI>,
+ 				 <&scmi0_clk CK_SCMI0_LSE>,
+ 				 <&scmi0_clk CK_SCMI0_LSI>;
++			clocks-boot-on = <LTDC_PX>;
+ 		};
+ 
+ 		pwr_regulators: pwr@50001000 {
+@@ -1574,8 +1578,8 @@
+ 			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ 			reg-names = "qspi", "qspi_mm";
+ 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+-			dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
+-			       <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
++			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0 0x0>,
++			       <&mdma1 22 0x2 0x10100008 0x0 0x0 0x0>;
+ 			dma-names = "tx", "rx";
+ 			clocks = <&rcc QSPI_K>;
+ 			resets = <&rcc QSPI_R>;
+@@ -1621,12 +1625,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		stmmac_axi_config_0: stmmac-axi-config {
+-			snps,wr_osr_lmt = <0x7>;
+-			snps,rd_osr_lmt = <0x7>;
+-			snps,blen = <0 0 0 0 16 8 4>;
+-		};
+-
+ 		ethernet0: ethernet@5800a000 {
+ 			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+ 			reg = <0x5800a000 0x2000>;
+@@ -1639,12 +1637,14 @@
+ 				      "mac-clk-tx",
+ 				      "mac-clk-rx",
+ 				      "eth-ck",
+-				      "ethstp";
++				      "ethstp",
++				      "ptp_ref";
+ 			clocks = <&rcc ETHMAC>,
+ 				 <&rcc ETHTX>,
+ 				 <&rcc ETHRX>,
+ 				 <&rcc ETHCK_K>,
+-				 <&rcc ETHSTP>;
++				 <&rcc ETHSTP>,
++				 <&rcc ETHPTP_K>;
+ 			st,syscon = <&syscfg 0x4>;
+ 			snps,mixed-burst;
+ 			snps,pbl = <2>;
+@@ -1653,12 +1653,18 @@
+ 			snps,tso;
+ 			power-domains = <&pd_core>;
+ 			status = "disabled";
++
++			stmmac_axi_config_0: stmmac-axi-config {
++				snps,wr_osr_lmt = <0x7>;
++				snps,rd_osr_lmt = <0x7>;
++				snps,blen = <0 0 0 0 16 8 4>;
++			};
+ 		};
+ 
+ 		usbh_ohci: usbh-ohci@5800c000 {
+ 			compatible = "generic-ohci";
+ 			reg = <0x5800c000 0x1000>;
+-			clocks = <&rcc USBH>;
++			clocks = <&rcc USBH>, <&usbphyc>;
+ 			resets = <&rcc USBH_R>;
+ 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ 			status = "disabled";
+@@ -1728,6 +1734,7 @@
+ 			reg = <0x5a007000 0x400>;
+ 			clocks = <&rcc DDRPERFM>;
+ 			resets = <&rcc DDRPERFM_R>;
++			status = "disabled";
+ 		};
+ 
+ 		usart1: serial@5c000000 {
+@@ -1789,11 +1796,15 @@
+ 		bsec: efuse@5c005000 {
+ 			compatible = "st,stm32mp15-bsec";
+ 			reg = <0x5c005000 0x400>;
++			clocks = <&scmi0_clk CK_SCMI0_BSEC>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			part_number_otp: part_number_otp@4 {
+ 				reg = <0x4 0x1>;
+ 			};
++			vrefint: calib@52 {
++				reg = <0x52 0x2>;
++			};
+ 			ts_cal1: calib@5c {
+ 				reg = <0x5c 0x2>;
+ 			};
+diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+index 8553570642..06267f2917 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+@@ -18,8 +18,8 @@
+ 		u-boot,error-led = "error";
+ 		u-boot,mmc-env-partition = "fip";
+ 		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
+-		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+-		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
++		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
++		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 	};
+ 
+ #ifdef CONFIG_STM32MP15x_STM32IMAGE
+diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
+index f415e581a6..f48207dad5 100644
+--- a/arch/arm/dts/stm32mp157a-dk1.dts
++++ b/arch/arm/dts/stm32mp157a-dk1.dts
+@@ -16,12 +16,6 @@
+ 	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
+ 	compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
+ 
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-		serial2 = &uart7;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+diff --git a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
+index f0761901a6..5b9772a0a9 100644
+--- a/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-ed1-u-boot.dtsi
+@@ -18,8 +18,8 @@
+ 		u-boot,boot-led = "heartbeat";
+ 		u-boot,error-led = "error";
+ 		u-boot,mmc-env-partition = "fip";
+-		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+-		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
++		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
++		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 	};
+ 
+ 	led {
+diff --git a/arch/arm/dts/stm32mp157a-ev1.dts b/arch/arm/dts/stm32mp157a-ev1.dts
+index 11bd88a82f..85c73a916c 100644
+--- a/arch/arm/dts/stm32mp157a-ev1.dts
++++ b/arch/arm/dts/stm32mp157a-ev1.dts
+@@ -15,11 +15,6 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+-
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-	};
+ };
+ 
+ &ltdc {
+diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
+index 1c894f288c..53d75e1c25 100644
+--- a/arch/arm/dts/stm32mp157c-dk2.dts
++++ b/arch/arm/dts/stm32mp157c-dk2.dts
+@@ -18,9 +18,6 @@
+ 	compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
+ 
+ 	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-		serial2 = &uart7;
+ 		serial3 = &usart2;
+ 	};
+ 
+diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
+index e84897ef44..3dd1244121 100644
+--- a/arch/arm/dts/stm32mp157c-ev1.dts
++++ b/arch/arm/dts/stm32mp157c-ev1.dts
+@@ -15,11 +15,6 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+-
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-	};
+ };
+ 
+ &ltdc {
+diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
+index bcc012cfff..d54dcf16a7 100644
+--- a/arch/arm/dts/stm32mp157d-dk1.dts
++++ b/arch/arm/dts/stm32mp157d-dk1.dts
+@@ -16,12 +16,6 @@
+ 	model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
+ 	compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
+ 
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-		serial2 = &uart7;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+diff --git a/arch/arm/dts/stm32mp157d-ev1.dts b/arch/arm/dts/stm32mp157d-ev1.dts
+index 5cb08c7079..dbb2b3e059 100644
+--- a/arch/arm/dts/stm32mp157d-ev1.dts
++++ b/arch/arm/dts/stm32mp157d-ev1.dts
+@@ -15,11 +15,6 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+-
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-	};
+ };
+ 
+ &ltdc {
+diff --git a/arch/arm/dts/stm32mp157f-dk2.dts b/arch/arm/dts/stm32mp157f-dk2.dts
+index 15a397c4cf..1244ae1841 100644
+--- a/arch/arm/dts/stm32mp157f-dk2.dts
++++ b/arch/arm/dts/stm32mp157f-dk2.dts
+@@ -18,9 +18,6 @@
+ 	compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
+ 
+ 	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-		serial2 = &uart7;
+ 		serial3 = &usart2;
+ 	};
+ 
+diff --git a/arch/arm/dts/stm32mp157f-ev1.dts b/arch/arm/dts/stm32mp157f-ev1.dts
+index 6fe600f813..0ef17cdc63 100644
+--- a/arch/arm/dts/stm32mp157f-ev1.dts
++++ b/arch/arm/dts/stm32mp157f-ev1.dts
+@@ -16,11 +16,6 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+-
+-	aliases {
+-		serial0 = &uart4;
+-		serial1 = &usart3;
+-	};
+ };
+ 
+ &ltdc {
+diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+index acff8755d3..884c538fcb 100644
+--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
++++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+@@ -12,6 +12,9 @@
+ / {
+ 	aliases {
+ 		ethernet0 = &ethernet0;
++		serial0 = &uart4;
++		serial1 = &usart3;
++		serial2 = &uart7;
+ 	};
+ 
+ 	memory@c0000000 {
+@@ -48,6 +51,12 @@
+ 			no-map;
+ 		};
+ 
++		mcu_rsc_table: mcu_rsc_table@10048000 {
++			compatible = "shared-dma-pool";
++			reg = <0x10048000 0x8000>;
++			no-map;
++		};
++
+ 		mcuram: mcuram@30000000 {
+ 			compatible = "shared-dma-pool";
+ 			reg = <0x30000000 0x40000>;
+@@ -284,7 +293,7 @@
+ 	stusb1600@28 {
+ 		compatible = "st,stusb1600";
+ 		reg = <0x28>;
+-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
++		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ 		interrupt-parent = <&gpioi>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&stusb1600_pins_a>;
+@@ -505,7 +514,7 @@
+ 
+ &m4_rproc {
+ 	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+-			<&vdev0vring1>, <&vdev0buffer>;
++			<&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ 	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ 	mbox-names = "vq0", "vq1", "shutdown";
+ 	interrupt-parent = <&exti>;
+@@ -755,6 +764,16 @@
+ &usbphyc_port0 {
+ 	phy-supply = <&vdd_usb>;
+ 	st,phy-tuning = <&usb_phy_tuning>;
++
++	/*
++	 * Hack to keep hub active until all connected devices are suspended
++	 * otherwise the hub will be powered off as soon as the v3v3 is disabled
++	 * and it can disturb connected devices.
++	 */
++	connector {
++		compatible = "usb-a-connector";
++		vbus-supply = <&v3v3>;
++	};
+ };
+ 
+ &usbphyc_port1 {
+diff --git a/arch/arm/dts/stm32mp15xx-edx.dtsi b/arch/arm/dts/stm32mp15xx-edx.dtsi
+index 3662f449de..817982009c 100644
+--- a/arch/arm/dts/stm32mp15xx-edx.dtsi
++++ b/arch/arm/dts/stm32mp15xx-edx.dtsi
+@@ -44,6 +44,12 @@
+ 			no-map;
+ 		};
+ 
++		mcu_rsc_table: mcu_rsc_table@10048000 {
++			compatible = "shared-dma-pool";
++			reg = <0x10048000 0x8000>;
++			no-map;
++		};
++
+ 		mcuram: mcuram@30000000 {
+ 			compatible = "shared-dma-pool";
+ 			reg = <0x30000000 0x40000>;
+@@ -315,7 +321,7 @@
+ 
+ &m4_rproc {
+ 	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+-			<&vdev0vring1>, <&vdev0buffer>;
++			<&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ 	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ 	mbox-names = "vq0", "vq1", "shutdown";
+ 	interrupt-parent = <&exti>;
+diff --git a/arch/arm/dts/stm32mp15xx-evx.dtsi b/arch/arm/dts/stm32mp15xx-evx.dtsi
+index 47a2c8e5ea..a7589d9d73 100644
+--- a/arch/arm/dts/stm32mp15xx-evx.dtsi
++++ b/arch/arm/dts/stm32mp15xx-evx.dtsi
+@@ -10,6 +10,7 @@
+ / {
+ 	aliases {
+ 		ethernet0 = &ethernet0;
++		serial1 = &usart3;
+ 	};
+ 
+ 	clocks {
+@@ -678,7 +679,16 @@
+ 
+ &usbphyc_port0 {
+ 	st,phy-tuning = <&usb_phy_tuning>;
+-	vbus-supply = <&vbus_sw>;
++
++	/*
++	 * Hack to keep hub active until all connected devices are suspended
++	 * otherwise the hub will be powered off as soon as the v3v3 is disabled
++	 * and it can disturb connected devices.
++	 */
++	connector {
++		compatible = "usb-a-connector";
++		vbus-supply = <&v3v3>;
++	};
+ };
+ 
+ &usbphyc_port1 {
+-- 
+2.25.1
+

recipes-bsp/u-boot/u-boot-stm32mp/0011-ARM-v2020.10-stm32mp-r2-CONFIG.patch

@@ -0,0 +1,186 @@
+From e1969811c8ae2c4874734aab703ff54ba1fe5206 Mon Sep 17 00:00:00 2001
+From: Lionel Vitte <lionel.vitte@st.com>
+Date: Mon, 18 Oct 2021 17:12:48 +0200
+Subject: [PATCH 11/11] ARM v2020.10-stm32mp-r2 CONFIG
+
+---
+ configs/rpi_0_w_defconfig           | 1 +
+ configs/rpi_2_defconfig             | 1 +
+ configs/rpi_3_32b_defconfig         | 1 +
+ configs/rpi_3_b_plus_defconfig      | 1 +
+ configs/rpi_3_defconfig             | 1 +
+ configs/rpi_4_32b_defconfig         | 1 +
+ configs/rpi_4_defconfig             | 1 +
+ configs/rpi_arm64_defconfig         | 1 +
+ configs/rpi_defconfig               | 1 +
+ configs/stm32mp15_basic_defconfig   | 3 +++
+ configs/stm32mp15_trusted_defconfig | 3 +++
+ 11 files changed, 15 insertions(+)
+
+diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
+index bba5e12b12..ed0707ea21 100644
+--- a/configs/rpi_0_w_defconfig
++++ b/configs/rpi_0_w_defconfig
+@@ -12,6 +12,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
+index 1c2bbb29ce..1bbb2adf36 100644
+--- a/configs/rpi_2_defconfig
++++ b/configs/rpi_2_defconfig
+@@ -12,6 +12,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
+index b8a3d17f43..c3f1e4a2db 100644
+--- a/configs/rpi_3_32b_defconfig
++++ b/configs/rpi_3_32b_defconfig
+@@ -13,6 +13,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
+index 4c361438fa..6fd55a8e45 100644
+--- a/configs/rpi_3_b_plus_defconfig
++++ b/configs/rpi_3_b_plus_defconfig
+@@ -13,6 +13,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
+index 9b281a4f15..08db309452 100644
+--- a/configs/rpi_3_defconfig
++++ b/configs/rpi_3_defconfig
+@@ -13,6 +13,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
+index 4a88448e9d..05bd355d5b 100644
+--- a/configs/rpi_4_32b_defconfig
++++ b/configs/rpi_4_32b_defconfig
+@@ -11,6 +11,7 @@ CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_DFU=y
+ CONFIG_CMD_GPIO=y
+diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
+index 71f95ed8f7..367abb5bac 100644
+--- a/configs/rpi_4_defconfig
++++ b/configs/rpi_4_defconfig
+@@ -11,6 +11,7 @@ CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_DFU=y
+ CONFIG_CMD_GPIO=y
+diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
+index 4ce8469f43..cb1513bb31 100644
+--- a/configs/rpi_arm64_defconfig
++++ b/configs/rpi_arm64_defconfig
+@@ -11,6 +11,7 @@ CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
+index b5ad53c37b..4722f161c9 100644
+--- a/configs/rpi_defconfig
++++ b/configs/rpi_defconfig
+@@ -12,6 +12,7 @@ CONFIG_USE_PREBOOT=y
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
+diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
+index c08d06474b..c90220a60d 100644
+--- a/configs/stm32mp15_basic_defconfig
++++ b/configs/stm32mp15_basic_defconfig
+@@ -8,6 +8,7 @@ CONFIG_SPL_DM_SPI=y
+ CONFIG_SPL_TEXT_BASE=0x2FFC2500
+ CONFIG_SPL_MMC_SUPPORT=y
+ CONFIG_SPL=y
++CONFIG_CMD_STM32KEY=y
+ CONFIG_TARGET_ST_STM32MP15x=y
+ CONFIG_CMD_STM32PROG=y
+ CONFIG_TYPEC_STUSB160X=y
+@@ -29,6 +30,7 @@ CONFIG_SPL_MTD_SUPPORT=y
+ CONFIG_SPL_DM_SPI_FLASH=y
+ CONFIG_SPL_POWER_SUPPORT=y
+ CONFIG_SPL_SPI_FLASH_MTD=y
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="STM32MP> "
+ CONFIG_CMD_ADTIMG=y
+ # CONFIG_CMD_ELF is not set
+@@ -51,6 +53,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
+ CONFIG_CMD_BMP=y
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_TIME=y
++CONFIG_CMD_RNG=y
+ CONFIG_CMD_TIMER=y
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
+diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
+index 5b4cfc4ca3..2161ccbefa 100644
+--- a/configs/stm32mp15_trusted_defconfig
++++ b/configs/stm32mp15_trusted_defconfig
+@@ -4,6 +4,7 @@ CONFIG_TFABOOT=y
+ CONFIG_SYS_MALLOC_F_LEN=0x3000
+ CONFIG_ENV_OFFSET=0x480000
+ CONFIG_ENV_SECT_SIZE=0x40000
++CONFIG_CMD_STM32KEY=y
+ CONFIG_TARGET_ST_STM32MP15x=y
+ CONFIG_CMD_STM32PROG=y
+ CONFIG_TYPEC_STUSB160X=y
+@@ -13,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_FIT=y
+ CONFIG_BOOTDELAY=1
+ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
++CONFIG_FDT_SIMPLEFB=y
+ CONFIG_SYS_PROMPT="STM32MP> "
+ CONFIG_CMD_ADTIMG=y
+ # CONFIG_CMD_ELF is not set
+@@ -35,6 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
+ CONFIG_CMD_BMP=y
+ CONFIG_CMD_CACHE=y
+ CONFIG_CMD_TIME=y
++CONFIG_CMD_RNG=y
+ CONFIG_CMD_TIMER=y
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
+-- 
+2.25.1
+